| 1 | /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. |
| 2 | * |
| 3 | * Copyright (C) 2001, 2002, 2003, 2007 David S. Miller (davem@davemloft.net) |
| 4 | */ |
| 5 | |
| 6 | #include <linux/kernel.h> |
| 7 | #include <linux/types.h> |
| 8 | #include <linux/pci.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/slab.h> |
| 11 | #include <linux/interrupt.h> |
| 12 | |
| 13 | #include <asm/pbm.h> |
| 14 | #include <asm/iommu.h> |
| 15 | #include <asm/irq.h> |
| 16 | #include <asm/upa.h> |
| 17 | #include <asm/pstate.h> |
| 18 | #include <asm/prom.h> |
| 19 | |
| 20 | #include "pci_impl.h" |
| 21 | #include "iommu_common.h" |
| 22 | |
| 23 | /* All SCHIZO registers are 64-bits. The following accessor |
| 24 | * routines are how they are accessed. The REG parameter |
| 25 | * is a physical address. |
| 26 | */ |
| 27 | #define schizo_read(__reg) \ |
| 28 | ({ u64 __ret; \ |
| 29 | __asm__ __volatile__("ldxa [%1] %2, %0" \ |
| 30 | : "=r" (__ret) \ |
| 31 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ |
| 32 | : "memory"); \ |
| 33 | __ret; \ |
| 34 | }) |
| 35 | #define schizo_write(__reg, __val) \ |
| 36 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
| 37 | : /* no outputs */ \ |
| 38 | : "r" (__val), "r" (__reg), \ |
| 39 | "i" (ASI_PHYS_BYPASS_EC_E) \ |
| 40 | : "memory") |
| 41 | |
| 42 | /* This is a convention that at least Excalibur and Merlin |
| 43 | * follow. I suppose the SCHIZO used in Starcat and friends |
| 44 | * will do similar. |
| 45 | * |
| 46 | * The only way I could see this changing is if the newlink |
| 47 | * block requires more space in Schizo's address space than |
| 48 | * they predicted, thus requiring an address space reorg when |
| 49 | * the newer Schizo is taped out. |
| 50 | */ |
| 51 | |
| 52 | /* Streaming buffer control register. */ |
| 53 | #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ |
| 54 | #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ |
| 55 | #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ |
| 56 | #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
| 57 | #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ |
| 58 | |
| 59 | /* IOMMU control register. */ |
| 60 | #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ |
| 61 | #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ |
| 62 | #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ |
| 63 | #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ |
| 64 | #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ |
| 65 | #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
| 66 | #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ |
| 67 | #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ |
| 68 | #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ |
| 69 | #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ |
| 70 | #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ |
| 71 | #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ |
| 72 | #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ |
| 73 | #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ |
| 74 | #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ |
| 75 | #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ |
| 76 | #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ |
| 77 | #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
| 78 | |
| 79 | /* Schizo config space address format is nearly identical to |
| 80 | * that of PSYCHO: |
| 81 | * |
| 82 | * 32 24 23 16 15 11 10 8 7 2 1 0 |
| 83 | * --------------------------------------------------------- |
| 84 | * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | |
| 85 | * --------------------------------------------------------- |
| 86 | */ |
| 87 | #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) |
| 88 | #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ |
| 89 | (((unsigned long)(BUS) << 16) | \ |
| 90 | ((unsigned long)(DEVFN) << 8) | \ |
| 91 | ((unsigned long)(REG))) |
| 92 | |
| 93 | static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, |
| 94 | unsigned char bus, |
| 95 | unsigned int devfn, |
| 96 | int where) |
| 97 | { |
| 98 | if (!pbm) |
| 99 | return NULL; |
| 100 | bus -= pbm->pci_first_busno; |
| 101 | return (void *) |
| 102 | (SCHIZO_CONFIG_BASE(pbm) | |
| 103 | SCHIZO_CONFIG_ENCODE(bus, devfn, where)); |
| 104 | } |
| 105 | |
| 106 | /* Just make sure the bus number is in range. */ |
| 107 | static int schizo_out_of_range(struct pci_pbm_info *pbm, |
| 108 | unsigned char bus, |
| 109 | unsigned char devfn) |
| 110 | { |
| 111 | if (bus < pbm->pci_first_busno || |
| 112 | bus > pbm->pci_last_busno) |
| 113 | return 1; |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /* SCHIZO PCI configuration space accessors. */ |
| 118 | |
| 119 | static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
| 120 | int where, int size, u32 *value) |
| 121 | { |
| 122 | struct pci_pbm_info *pbm = bus_dev->sysdata; |
| 123 | unsigned char bus = bus_dev->number; |
| 124 | u32 *addr; |
| 125 | u16 tmp16; |
| 126 | u8 tmp8; |
| 127 | |
| 128 | if (bus_dev == pbm->pci_bus && devfn == 0x00) |
| 129 | return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where, |
| 130 | size, value); |
| 131 | switch (size) { |
| 132 | case 1: |
| 133 | *value = 0xff; |
| 134 | break; |
| 135 | case 2: |
| 136 | *value = 0xffff; |
| 137 | break; |
| 138 | case 4: |
| 139 | *value = 0xffffffff; |
| 140 | break; |
| 141 | } |
| 142 | |
| 143 | addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where); |
| 144 | if (!addr) |
| 145 | return PCIBIOS_SUCCESSFUL; |
| 146 | |
| 147 | if (schizo_out_of_range(pbm, bus, devfn)) |
| 148 | return PCIBIOS_SUCCESSFUL; |
| 149 | switch (size) { |
| 150 | case 1: |
| 151 | pci_config_read8((u8 *)addr, &tmp8); |
| 152 | *value = tmp8; |
| 153 | break; |
| 154 | |
| 155 | case 2: |
| 156 | if (where & 0x01) { |
| 157 | printk("pci_read_config_word: misaligned reg [%x]\n", |
| 158 | where); |
| 159 | return PCIBIOS_SUCCESSFUL; |
| 160 | } |
| 161 | pci_config_read16((u16 *)addr, &tmp16); |
| 162 | *value = tmp16; |
| 163 | break; |
| 164 | |
| 165 | case 4: |
| 166 | if (where & 0x03) { |
| 167 | printk("pci_read_config_dword: misaligned reg [%x]\n", |
| 168 | where); |
| 169 | return PCIBIOS_SUCCESSFUL; |
| 170 | } |
| 171 | pci_config_read32(addr, value); |
| 172 | break; |
| 173 | } |
| 174 | return PCIBIOS_SUCCESSFUL; |
| 175 | } |
| 176 | |
| 177 | static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
| 178 | int where, int size, u32 value) |
| 179 | { |
| 180 | struct pci_pbm_info *pbm = bus_dev->sysdata; |
| 181 | unsigned char bus = bus_dev->number; |
| 182 | u32 *addr; |
| 183 | |
| 184 | if (bus_dev == pbm->pci_bus && devfn == 0x00) |
| 185 | return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where, |
| 186 | size, value); |
| 187 | addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where); |
| 188 | if (!addr) |
| 189 | return PCIBIOS_SUCCESSFUL; |
| 190 | |
| 191 | if (schizo_out_of_range(pbm, bus, devfn)) |
| 192 | return PCIBIOS_SUCCESSFUL; |
| 193 | |
| 194 | switch (size) { |
| 195 | case 1: |
| 196 | pci_config_write8((u8 *)addr, value); |
| 197 | break; |
| 198 | |
| 199 | case 2: |
| 200 | if (where & 0x01) { |
| 201 | printk("pci_write_config_word: misaligned reg [%x]\n", |
| 202 | where); |
| 203 | return PCIBIOS_SUCCESSFUL; |
| 204 | } |
| 205 | pci_config_write16((u16 *)addr, value); |
| 206 | break; |
| 207 | |
| 208 | case 4: |
| 209 | if (where & 0x03) { |
| 210 | printk("pci_write_config_dword: misaligned reg [%x]\n", |
| 211 | where); |
| 212 | return PCIBIOS_SUCCESSFUL; |
| 213 | } |
| 214 | |
| 215 | pci_config_write32(addr, value); |
| 216 | } |
| 217 | return PCIBIOS_SUCCESSFUL; |
| 218 | } |
| 219 | |
| 220 | static struct pci_ops schizo_ops = { |
| 221 | .read = schizo_read_pci_cfg, |
| 222 | .write = schizo_write_pci_cfg, |
| 223 | }; |
| 224 | |
| 225 | /* SCHIZO error handling support. */ |
| 226 | enum schizo_error_type { |
| 227 | UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR |
| 228 | }; |
| 229 | |
| 230 | static DEFINE_SPINLOCK(stc_buf_lock); |
| 231 | static unsigned long stc_error_buf[128]; |
| 232 | static unsigned long stc_tag_buf[16]; |
| 233 | static unsigned long stc_line_buf[16]; |
| 234 | |
| 235 | #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ |
| 236 | #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ |
| 237 | #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ |
| 238 | #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ |
| 239 | #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ |
| 240 | |
| 241 | struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino) |
| 242 | { |
| 243 | ino &= IMAP_INO; |
| 244 | if (p->pbm_A.ino_bitmap & (1UL << ino)) |
| 245 | return &p->pbm_A; |
| 246 | if (p->pbm_B.ino_bitmap & (1UL << ino)) |
| 247 | return &p->pbm_B; |
| 248 | |
| 249 | printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps " |
| 250 | "PBM_A[%016lx] PBM_B[%016lx]", |
| 251 | p->index, ino, |
| 252 | p->pbm_A.ino_bitmap, |
| 253 | p->pbm_B.ino_bitmap); |
| 254 | printk("PCI%d: Using PBM_A, report this problem immediately.\n", |
| 255 | p->index); |
| 256 | |
| 257 | return &p->pbm_A; |
| 258 | } |
| 259 | |
| 260 | #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ |
| 261 | #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ |
| 262 | #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ |
| 263 | |
| 264 | #define SCHIZO_STCERR_WRITE 0x2UL |
| 265 | #define SCHIZO_STCERR_READ 0x1UL |
| 266 | |
| 267 | #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL |
| 268 | #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL |
| 269 | #define SCHIZO_STCTAG_VALID 0x8000000000000000UL |
| 270 | #define SCHIZO_STCTAG_READ 0x4000000000000000UL |
| 271 | |
| 272 | #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL |
| 273 | #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL |
| 274 | #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL |
| 275 | #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL |
| 276 | #define SCHIZO_STCLINE_VALID 0x0000000000600000UL |
| 277 | #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL |
| 278 | |
| 279 | static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, |
| 280 | enum schizo_error_type type) |
| 281 | { |
| 282 | struct strbuf *strbuf = &pbm->stc; |
| 283 | unsigned long regbase = pbm->pbm_regs; |
| 284 | unsigned long err_base, tag_base, line_base; |
| 285 | u64 control; |
| 286 | int i; |
| 287 | |
| 288 | err_base = regbase + SCHIZO_STC_ERR; |
| 289 | tag_base = regbase + SCHIZO_STC_TAG; |
| 290 | line_base = regbase + SCHIZO_STC_LINE; |
| 291 | |
| 292 | spin_lock(&stc_buf_lock); |
| 293 | |
| 294 | /* This is __REALLY__ dangerous. When we put the |
| 295 | * streaming buffer into diagnostic mode to probe |
| 296 | * it's tags and error status, we _must_ clear all |
| 297 | * of the line tag valid bits before re-enabling |
| 298 | * the streaming buffer. If any dirty data lives |
| 299 | * in the STC when we do this, we will end up |
| 300 | * invalidating it before it has a chance to reach |
| 301 | * main memory. |
| 302 | */ |
| 303 | control = schizo_read(strbuf->strbuf_control); |
| 304 | schizo_write(strbuf->strbuf_control, |
| 305 | (control | SCHIZO_STRBUF_CTRL_DENAB)); |
| 306 | for (i = 0; i < 128; i++) { |
| 307 | unsigned long val; |
| 308 | |
| 309 | val = schizo_read(err_base + (i * 8UL)); |
| 310 | schizo_write(err_base + (i * 8UL), 0UL); |
| 311 | stc_error_buf[i] = val; |
| 312 | } |
| 313 | for (i = 0; i < 16; i++) { |
| 314 | stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL)); |
| 315 | stc_line_buf[i] = schizo_read(line_base + (i * 8UL)); |
| 316 | schizo_write(tag_base + (i * 8UL), 0UL); |
| 317 | schizo_write(line_base + (i * 8UL), 0UL); |
| 318 | } |
| 319 | |
| 320 | /* OK, state is logged, exit diagnostic mode. */ |
| 321 | schizo_write(strbuf->strbuf_control, control); |
| 322 | |
| 323 | for (i = 0; i < 16; i++) { |
| 324 | int j, saw_error, first, last; |
| 325 | |
| 326 | saw_error = 0; |
| 327 | first = i * 8; |
| 328 | last = first + 8; |
| 329 | for (j = first; j < last; j++) { |
| 330 | unsigned long errval = stc_error_buf[j]; |
| 331 | if (errval != 0) { |
| 332 | saw_error++; |
| 333 | printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", |
| 334 | pbm->name, |
| 335 | j, |
| 336 | (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, |
| 337 | (errval & SCHIZO_STCERR_READ) ? 1 : 0); |
| 338 | } |
| 339 | } |
| 340 | if (saw_error != 0) { |
| 341 | unsigned long tagval = stc_tag_buf[i]; |
| 342 | unsigned long lineval = stc_line_buf[i]; |
| 343 | printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", |
| 344 | pbm->name, |
| 345 | i, |
| 346 | ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), |
| 347 | (tagval & SCHIZO_STCTAG_VPN), |
| 348 | ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), |
| 349 | ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); |
| 350 | |
| 351 | /* XXX Should spit out per-bank error information... -DaveM */ |
| 352 | printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" |
| 353 | "V(%d)FOFN(%d)]\n", |
| 354 | pbm->name, |
| 355 | i, |
| 356 | ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), |
| 357 | ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), |
| 358 | ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), |
| 359 | ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), |
| 360 | ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), |
| 361 | ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); |
| 362 | } |
| 363 | } |
| 364 | |
| 365 | spin_unlock(&stc_buf_lock); |
| 366 | } |
| 367 | |
| 368 | /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous |
| 369 | * controller level errors. |
| 370 | */ |
| 371 | |
| 372 | #define SCHIZO_IOMMU_TAG 0xa580UL |
| 373 | #define SCHIZO_IOMMU_DATA 0xa600UL |
| 374 | |
| 375 | #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL |
| 376 | #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL |
| 377 | #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL |
| 378 | #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL |
| 379 | #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL |
| 380 | #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL |
| 381 | #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL |
| 382 | |
| 383 | #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL |
| 384 | #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL |
| 385 | #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL |
| 386 | |
| 387 | static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, |
| 388 | enum schizo_error_type type) |
| 389 | { |
| 390 | struct iommu *iommu = pbm->iommu; |
| 391 | unsigned long iommu_tag[16]; |
| 392 | unsigned long iommu_data[16]; |
| 393 | unsigned long flags; |
| 394 | u64 control; |
| 395 | int i; |
| 396 | |
| 397 | spin_lock_irqsave(&iommu->lock, flags); |
| 398 | control = schizo_read(iommu->iommu_control); |
| 399 | if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { |
| 400 | unsigned long base; |
| 401 | char *type_string; |
| 402 | |
| 403 | /* Clear the error encountered bit. */ |
| 404 | control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; |
| 405 | schizo_write(iommu->iommu_control, control); |
| 406 | |
| 407 | switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { |
| 408 | case 0: |
| 409 | type_string = "Protection Error"; |
| 410 | break; |
| 411 | case 1: |
| 412 | type_string = "Invalid Error"; |
| 413 | break; |
| 414 | case 2: |
| 415 | type_string = "TimeOut Error"; |
| 416 | break; |
| 417 | case 3: |
| 418 | default: |
| 419 | type_string = "ECC Error"; |
| 420 | break; |
| 421 | }; |
| 422 | printk("%s: IOMMU Error, type[%s]\n", |
| 423 | pbm->name, type_string); |
| 424 | |
| 425 | /* Put the IOMMU into diagnostic mode and probe |
| 426 | * it's TLB for entries with error status. |
| 427 | * |
| 428 | * It is very possible for another DVMA to occur |
| 429 | * while we do this probe, and corrupt the system |
| 430 | * further. But we are so screwed at this point |
| 431 | * that we are likely to crash hard anyways, so |
| 432 | * get as much diagnostic information to the |
| 433 | * console as we can. |
| 434 | */ |
| 435 | schizo_write(iommu->iommu_control, |
| 436 | control | SCHIZO_IOMMU_CTRL_DENAB); |
| 437 | |
| 438 | base = pbm->pbm_regs; |
| 439 | |
| 440 | for (i = 0; i < 16; i++) { |
| 441 | iommu_tag[i] = |
| 442 | schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL)); |
| 443 | iommu_data[i] = |
| 444 | schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL)); |
| 445 | |
| 446 | /* Now clear out the entry. */ |
| 447 | schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0); |
| 448 | schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0); |
| 449 | } |
| 450 | |
| 451 | /* Leave diagnostic mode. */ |
| 452 | schizo_write(iommu->iommu_control, control); |
| 453 | |
| 454 | for (i = 0; i < 16; i++) { |
| 455 | unsigned long tag, data; |
| 456 | |
| 457 | tag = iommu_tag[i]; |
| 458 | if (!(tag & SCHIZO_IOMMU_TAG_ERR)) |
| 459 | continue; |
| 460 | |
| 461 | data = iommu_data[i]; |
| 462 | switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { |
| 463 | case 0: |
| 464 | type_string = "Protection Error"; |
| 465 | break; |
| 466 | case 1: |
| 467 | type_string = "Invalid Error"; |
| 468 | break; |
| 469 | case 2: |
| 470 | type_string = "TimeOut Error"; |
| 471 | break; |
| 472 | case 3: |
| 473 | default: |
| 474 | type_string = "ECC Error"; |
| 475 | break; |
| 476 | }; |
| 477 | printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " |
| 478 | "sz(%dK) vpg(%08lx)]\n", |
| 479 | pbm->name, i, type_string, |
| 480 | (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), |
| 481 | ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), |
| 482 | ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), |
| 483 | ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), |
| 484 | (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); |
| 485 | printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", |
| 486 | pbm->name, i, |
| 487 | ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), |
| 488 | ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), |
| 489 | (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); |
| 490 | } |
| 491 | } |
| 492 | if (pbm->stc.strbuf_enabled) |
| 493 | __schizo_check_stc_error_pbm(pbm, type); |
| 494 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 495 | } |
| 496 | |
| 497 | static void schizo_check_iommu_error(struct pci_controller_info *p, |
| 498 | enum schizo_error_type type) |
| 499 | { |
| 500 | schizo_check_iommu_error_pbm(&p->pbm_A, type); |
| 501 | schizo_check_iommu_error_pbm(&p->pbm_B, type); |
| 502 | } |
| 503 | |
| 504 | /* Uncorrectable ECC error status gathering. */ |
| 505 | #define SCHIZO_UE_AFSR 0x10030UL |
| 506 | #define SCHIZO_UE_AFAR 0x10038UL |
| 507 | |
| 508 | #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ |
| 509 | #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ |
| 510 | #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ |
| 511 | #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ |
| 512 | #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ |
| 513 | #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ |
| 514 | #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ |
| 515 | #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ |
| 516 | #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ |
| 517 | #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ |
| 518 | #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ |
| 519 | #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ |
| 520 | #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ |
| 521 | #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ |
| 522 | |
| 523 | static irqreturn_t schizo_ue_intr(int irq, void *dev_id) |
| 524 | { |
| 525 | struct pci_controller_info *p = dev_id; |
| 526 | unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR; |
| 527 | unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR; |
| 528 | unsigned long afsr, afar, error_bits; |
| 529 | int reported, limit; |
| 530 | |
| 531 | /* Latch uncorrectable error status. */ |
| 532 | afar = schizo_read(afar_reg); |
| 533 | |
| 534 | /* If either of the error pending bits are set in the |
| 535 | * AFSR, the error status is being actively updated by |
| 536 | * the hardware and we must re-read to get a clean value. |
| 537 | */ |
| 538 | limit = 1000; |
| 539 | do { |
| 540 | afsr = schizo_read(afsr_reg); |
| 541 | } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); |
| 542 | |
| 543 | /* Clear the primary/secondary error status bits. */ |
| 544 | error_bits = afsr & |
| 545 | (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | |
| 546 | SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); |
| 547 | if (!error_bits) |
| 548 | return IRQ_NONE; |
| 549 | schizo_write(afsr_reg, error_bits); |
| 550 | |
| 551 | /* Log the error. */ |
| 552 | printk("PCI%d: Uncorrectable Error, primary error type[%s]\n", |
| 553 | p->index, |
| 554 | (((error_bits & SCHIZO_UEAFSR_PPIO) ? |
| 555 | "PIO" : |
| 556 | ((error_bits & SCHIZO_UEAFSR_PDRD) ? |
| 557 | "DMA Read" : |
| 558 | ((error_bits & SCHIZO_UEAFSR_PDWR) ? |
| 559 | "DMA Write" : "???"))))); |
| 560 | printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", |
| 561 | p->index, |
| 562 | (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, |
| 563 | (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, |
| 564 | (afsr & SCHIZO_UEAFSR_AID) >> 24UL); |
| 565 | printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", |
| 566 | p->index, |
| 567 | (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, |
| 568 | (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, |
| 569 | (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, |
| 570 | (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, |
| 571 | (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); |
| 572 | printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar); |
| 573 | printk("PCI%d: UE Secondary errors [", p->index); |
| 574 | reported = 0; |
| 575 | if (afsr & SCHIZO_UEAFSR_SPIO) { |
| 576 | reported++; |
| 577 | printk("(PIO)"); |
| 578 | } |
| 579 | if (afsr & SCHIZO_UEAFSR_SDMA) { |
| 580 | reported++; |
| 581 | printk("(DMA)"); |
| 582 | } |
| 583 | if (!reported) |
| 584 | printk("(none)"); |
| 585 | printk("]\n"); |
| 586 | |
| 587 | /* Interrogate IOMMU for error status. */ |
| 588 | schizo_check_iommu_error(p, UE_ERR); |
| 589 | |
| 590 | return IRQ_HANDLED; |
| 591 | } |
| 592 | |
| 593 | #define SCHIZO_CE_AFSR 0x10040UL |
| 594 | #define SCHIZO_CE_AFAR 0x10048UL |
| 595 | |
| 596 | #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL |
| 597 | #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL |
| 598 | #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL |
| 599 | #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL |
| 600 | #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL |
| 601 | #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL |
| 602 | #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL |
| 603 | #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL |
| 604 | #define SCHIZO_CEAFSR_AID 0x000000001f000000UL |
| 605 | #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL |
| 606 | #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL |
| 607 | #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL |
| 608 | #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL |
| 609 | #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL |
| 610 | |
| 611 | static irqreturn_t schizo_ce_intr(int irq, void *dev_id) |
| 612 | { |
| 613 | struct pci_controller_info *p = dev_id; |
| 614 | unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR; |
| 615 | unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR; |
| 616 | unsigned long afsr, afar, error_bits; |
| 617 | int reported, limit; |
| 618 | |
| 619 | /* Latch error status. */ |
| 620 | afar = schizo_read(afar_reg); |
| 621 | |
| 622 | /* If either of the error pending bits are set in the |
| 623 | * AFSR, the error status is being actively updated by |
| 624 | * the hardware and we must re-read to get a clean value. |
| 625 | */ |
| 626 | limit = 1000; |
| 627 | do { |
| 628 | afsr = schizo_read(afsr_reg); |
| 629 | } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); |
| 630 | |
| 631 | /* Clear primary/secondary error status bits. */ |
| 632 | error_bits = afsr & |
| 633 | (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | |
| 634 | SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); |
| 635 | if (!error_bits) |
| 636 | return IRQ_NONE; |
| 637 | schizo_write(afsr_reg, error_bits); |
| 638 | |
| 639 | /* Log the error. */ |
| 640 | printk("PCI%d: Correctable Error, primary error type[%s]\n", |
| 641 | p->index, |
| 642 | (((error_bits & SCHIZO_CEAFSR_PPIO) ? |
| 643 | "PIO" : |
| 644 | ((error_bits & SCHIZO_CEAFSR_PDRD) ? |
| 645 | "DMA Read" : |
| 646 | ((error_bits & SCHIZO_CEAFSR_PDWR) ? |
| 647 | "DMA Write" : "???"))))); |
| 648 | |
| 649 | /* XXX Use syndrome and afar to print out module string just like |
| 650 | * XXX UDB CE trap handler does... -DaveM |
| 651 | */ |
| 652 | printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", |
| 653 | p->index, |
| 654 | (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, |
| 655 | (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, |
| 656 | (afsr & SCHIZO_UEAFSR_AID) >> 24UL); |
| 657 | printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", |
| 658 | p->index, |
| 659 | (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, |
| 660 | (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, |
| 661 | (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, |
| 662 | (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, |
| 663 | (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); |
| 664 | printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar); |
| 665 | printk("PCI%d: CE Secondary errors [", p->index); |
| 666 | reported = 0; |
| 667 | if (afsr & SCHIZO_CEAFSR_SPIO) { |
| 668 | reported++; |
| 669 | printk("(PIO)"); |
| 670 | } |
| 671 | if (afsr & SCHIZO_CEAFSR_SDMA) { |
| 672 | reported++; |
| 673 | printk("(DMA)"); |
| 674 | } |
| 675 | if (!reported) |
| 676 | printk("(none)"); |
| 677 | printk("]\n"); |
| 678 | |
| 679 | return IRQ_HANDLED; |
| 680 | } |
| 681 | |
| 682 | #define SCHIZO_PCI_AFSR 0x2010UL |
| 683 | #define SCHIZO_PCI_AFAR 0x2018UL |
| 684 | |
| 685 | #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ |
| 686 | #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ |
| 687 | #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ |
| 688 | #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ |
| 689 | #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ |
| 690 | #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ |
| 691 | #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ |
| 692 | #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ |
| 693 | #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ |
| 694 | #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ |
| 695 | #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ |
| 696 | #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ |
| 697 | #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ |
| 698 | #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ |
| 699 | #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ |
| 700 | #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ |
| 701 | #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ |
| 702 | |
| 703 | #define SCHIZO_PCI_CTRL (0x2000UL) |
| 704 | #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ |
| 705 | #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ |
| 706 | #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ |
| 707 | #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ |
| 708 | #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ |
| 709 | #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ |
| 710 | #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ |
| 711 | #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ |
| 712 | #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ |
| 713 | #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ |
| 714 | #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ |
| 715 | #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ |
| 716 | #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ |
| 717 | #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ |
| 718 | #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ |
| 719 | #define SCHIZO_PCICTRL_PTO_SHIFT 24UL |
| 720 | #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ |
| 721 | #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ |
| 722 | #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ |
| 723 | #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ |
| 724 | #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ |
| 725 | #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ |
| 726 | #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ |
| 727 | #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ |
| 728 | #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ |
| 729 | #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ |
| 730 | #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ |
| 731 | |
| 732 | static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) |
| 733 | { |
| 734 | unsigned long csr_reg, csr, csr_error_bits; |
| 735 | irqreturn_t ret = IRQ_NONE; |
| 736 | u16 stat; |
| 737 | |
| 738 | csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; |
| 739 | csr = schizo_read(csr_reg); |
| 740 | csr_error_bits = |
| 741 | csr & (SCHIZO_PCICTRL_BUS_UNUS | |
| 742 | SCHIZO_PCICTRL_TTO_ERR | |
| 743 | SCHIZO_PCICTRL_RTRY_ERR | |
| 744 | SCHIZO_PCICTRL_DTO_ERR | |
| 745 | SCHIZO_PCICTRL_SBH_ERR | |
| 746 | SCHIZO_PCICTRL_SERR); |
| 747 | if (csr_error_bits) { |
| 748 | /* Clear the errors. */ |
| 749 | schizo_write(csr_reg, csr); |
| 750 | |
| 751 | /* Log 'em. */ |
| 752 | if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) |
| 753 | printk("%s: Bus unusable error asserted.\n", |
| 754 | pbm->name); |
| 755 | if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) |
| 756 | printk("%s: PCI TRDY# timeout error asserted.\n", |
| 757 | pbm->name); |
| 758 | if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) |
| 759 | printk("%s: PCI excessive retry error asserted.\n", |
| 760 | pbm->name); |
| 761 | if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) |
| 762 | printk("%s: PCI discard timeout error asserted.\n", |
| 763 | pbm->name); |
| 764 | if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) |
| 765 | printk("%s: PCI streaming byte hole error asserted.\n", |
| 766 | pbm->name); |
| 767 | if (csr_error_bits & SCHIZO_PCICTRL_SERR) |
| 768 | printk("%s: PCI SERR signal asserted.\n", |
| 769 | pbm->name); |
| 770 | ret = IRQ_HANDLED; |
| 771 | } |
| 772 | pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); |
| 773 | if (stat & (PCI_STATUS_PARITY | |
| 774 | PCI_STATUS_SIG_TARGET_ABORT | |
| 775 | PCI_STATUS_REC_TARGET_ABORT | |
| 776 | PCI_STATUS_REC_MASTER_ABORT | |
| 777 | PCI_STATUS_SIG_SYSTEM_ERROR)) { |
| 778 | printk("%s: PCI bus error, PCI_STATUS[%04x]\n", |
| 779 | pbm->name, stat); |
| 780 | pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); |
| 781 | ret = IRQ_HANDLED; |
| 782 | } |
| 783 | return ret; |
| 784 | } |
| 785 | |
| 786 | static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id) |
| 787 | { |
| 788 | struct pci_pbm_info *pbm = dev_id; |
| 789 | struct pci_controller_info *p = pbm->parent; |
| 790 | unsigned long afsr_reg, afar_reg, base; |
| 791 | unsigned long afsr, afar, error_bits; |
| 792 | int reported; |
| 793 | |
| 794 | base = pbm->pbm_regs; |
| 795 | |
| 796 | afsr_reg = base + SCHIZO_PCI_AFSR; |
| 797 | afar_reg = base + SCHIZO_PCI_AFAR; |
| 798 | |
| 799 | /* Latch error status. */ |
| 800 | afar = schizo_read(afar_reg); |
| 801 | afsr = schizo_read(afsr_reg); |
| 802 | |
| 803 | /* Clear primary/secondary error status bits. */ |
| 804 | error_bits = afsr & |
| 805 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | |
| 806 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | |
| 807 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | |
| 808 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | |
| 809 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | |
| 810 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); |
| 811 | if (!error_bits) |
| 812 | return schizo_pcierr_intr_other(pbm); |
| 813 | schizo_write(afsr_reg, error_bits); |
| 814 | |
| 815 | /* Log the error. */ |
| 816 | printk("%s: PCI Error, primary error type[%s]\n", |
| 817 | pbm->name, |
| 818 | (((error_bits & SCHIZO_PCIAFSR_PMA) ? |
| 819 | "Master Abort" : |
| 820 | ((error_bits & SCHIZO_PCIAFSR_PTA) ? |
| 821 | "Target Abort" : |
| 822 | ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? |
| 823 | "Excessive Retries" : |
| 824 | ((error_bits & SCHIZO_PCIAFSR_PPERR) ? |
| 825 | "Parity Error" : |
| 826 | ((error_bits & SCHIZO_PCIAFSR_PTTO) ? |
| 827 | "Timeout" : |
| 828 | ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? |
| 829 | "Bus Unusable" : "???")))))))); |
| 830 | printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", |
| 831 | pbm->name, |
| 832 | (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, |
| 833 | (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, |
| 834 | ((afsr & SCHIZO_PCIAFSR_CFG) ? |
| 835 | "Config" : |
| 836 | ((afsr & SCHIZO_PCIAFSR_MEM) ? |
| 837 | "Memory" : |
| 838 | ((afsr & SCHIZO_PCIAFSR_IO) ? |
| 839 | "I/O" : "???")))); |
| 840 | printk("%s: PCI AFAR [%016lx]\n", |
| 841 | pbm->name, afar); |
| 842 | printk("%s: PCI Secondary errors [", |
| 843 | pbm->name); |
| 844 | reported = 0; |
| 845 | if (afsr & SCHIZO_PCIAFSR_SMA) { |
| 846 | reported++; |
| 847 | printk("(Master Abort)"); |
| 848 | } |
| 849 | if (afsr & SCHIZO_PCIAFSR_STA) { |
| 850 | reported++; |
| 851 | printk("(Target Abort)"); |
| 852 | } |
| 853 | if (afsr & SCHIZO_PCIAFSR_SRTRY) { |
| 854 | reported++; |
| 855 | printk("(Excessive Retries)"); |
| 856 | } |
| 857 | if (afsr & SCHIZO_PCIAFSR_SPERR) { |
| 858 | reported++; |
| 859 | printk("(Parity Error)"); |
| 860 | } |
| 861 | if (afsr & SCHIZO_PCIAFSR_STTO) { |
| 862 | reported++; |
| 863 | printk("(Timeout)"); |
| 864 | } |
| 865 | if (afsr & SCHIZO_PCIAFSR_SUNUS) { |
| 866 | reported++; |
| 867 | printk("(Bus Unusable)"); |
| 868 | } |
| 869 | if (!reported) |
| 870 | printk("(none)"); |
| 871 | printk("]\n"); |
| 872 | |
| 873 | /* For the error types shown, scan PBM's PCI bus for devices |
| 874 | * which have logged that error type. |
| 875 | */ |
| 876 | |
| 877 | /* If we see a Target Abort, this could be the result of an |
| 878 | * IOMMU translation error of some sort. It is extremely |
| 879 | * useful to log this information as usually it indicates |
| 880 | * a bug in the IOMMU support code or a PCI device driver. |
| 881 | */ |
| 882 | if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { |
| 883 | schizo_check_iommu_error(p, PCI_ERR); |
| 884 | pci_scan_for_target_abort(p, pbm, pbm->pci_bus); |
| 885 | } |
| 886 | if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) |
| 887 | pci_scan_for_master_abort(p, pbm, pbm->pci_bus); |
| 888 | |
| 889 | /* For excessive retries, PSYCHO/PBM will abort the device |
| 890 | * and there is no way to specifically check for excessive |
| 891 | * retries in the config space status registers. So what |
| 892 | * we hope is that we'll catch it via the master/target |
| 893 | * abort events. |
| 894 | */ |
| 895 | |
| 896 | if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) |
| 897 | pci_scan_for_parity_error(p, pbm, pbm->pci_bus); |
| 898 | |
| 899 | return IRQ_HANDLED; |
| 900 | } |
| 901 | |
| 902 | #define SCHIZO_SAFARI_ERRLOG 0x10018UL |
| 903 | |
| 904 | #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL |
| 905 | |
| 906 | #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ |
| 907 | #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ |
| 908 | #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ |
| 909 | #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ |
| 910 | #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ |
| 911 | #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ |
| 912 | #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ |
| 913 | #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ |
| 914 | #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ |
| 915 | #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ |
| 916 | #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ |
| 917 | #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ |
| 918 | #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ |
| 919 | #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ |
| 920 | #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ |
| 921 | #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ |
| 922 | #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ |
| 923 | #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ |
| 924 | #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ |
| 925 | #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ |
| 926 | #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ |
| 927 | #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ |
| 928 | #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ |
| 929 | #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ |
| 930 | #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ |
| 931 | #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ |
| 932 | #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ |
| 933 | #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ |
| 934 | #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ |
| 935 | #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ |
| 936 | #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ |
| 937 | |
| 938 | /* We only expect UNMAP errors here. The rest of the Safari errors |
| 939 | * are marked fatal and thus cause a system reset. |
| 940 | */ |
| 941 | static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id) |
| 942 | { |
| 943 | struct pci_controller_info *p = dev_id; |
| 944 | u64 errlog; |
| 945 | |
| 946 | errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG); |
| 947 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG, |
| 948 | errlog & ~(SAFARI_ERRLOG_ERROUT)); |
| 949 | |
| 950 | if (!(errlog & BUS_ERROR_UNMAP)) { |
| 951 | printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n", |
| 952 | p->index, errlog); |
| 953 | |
| 954 | return IRQ_HANDLED; |
| 955 | } |
| 956 | |
| 957 | printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", |
| 958 | p->index); |
| 959 | schizo_check_iommu_error(p, SAFARI_ERR); |
| 960 | |
| 961 | return IRQ_HANDLED; |
| 962 | } |
| 963 | |
| 964 | /* Nearly identical to PSYCHO equivalents... */ |
| 965 | #define SCHIZO_ECC_CTRL 0x10020UL |
| 966 | #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ |
| 967 | #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ |
| 968 | #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ |
| 969 | |
| 970 | #define SCHIZO_SAFARI_ERRCTRL 0x10008UL |
| 971 | #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL |
| 972 | #define SCHIZO_SAFARI_IRQCTRL 0x10010UL |
| 973 | #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL |
| 974 | |
| 975 | /* How the Tomatillo IRQs are routed around is pure guesswork here. |
| 976 | * |
| 977 | * All the Tomatillo devices I see in prtconf dumps seem to have only |
| 978 | * a single PCI bus unit attached to it. It would seem they are seperate |
| 979 | * devices because their PortID (ie. JBUS ID) values are all different |
| 980 | * and thus the registers are mapped to totally different locations. |
| 981 | * |
| 982 | * However, two Tomatillo's look "similar" in that the only difference |
| 983 | * in their PortID is the lowest bit. |
| 984 | * |
| 985 | * So if we were to ignore this lower bit, it certainly looks like two |
| 986 | * PCI bus units of the same Tomatillo. I still have not really |
| 987 | * figured this out... |
| 988 | */ |
| 989 | static void tomatillo_register_error_handlers(struct pci_controller_info *p) |
| 990 | { |
| 991 | struct pci_pbm_info *pbm; |
| 992 | struct of_device *op; |
| 993 | u64 tmp, err_mask, err_no_mask; |
| 994 | |
| 995 | /* Tomatillo IRQ property layout is: |
| 996 | * 0: PCIERR |
| 997 | * 1: UE ERR |
| 998 | * 2: CE ERR |
| 999 | * 3: SERR |
| 1000 | * 4: POWER FAIL? |
| 1001 | */ |
| 1002 | |
| 1003 | pbm = pbm_for_ino(p, SCHIZO_UE_INO); |
| 1004 | op = of_find_device_by_node(pbm->prom_node); |
| 1005 | if (op) |
| 1006 | request_irq(op->irqs[1], schizo_ue_intr, IRQF_SHARED, |
| 1007 | "TOMATILLO_UE", p); |
| 1008 | |
| 1009 | pbm = pbm_for_ino(p, SCHIZO_CE_INO); |
| 1010 | op = of_find_device_by_node(pbm->prom_node); |
| 1011 | if (op) |
| 1012 | request_irq(op->irqs[2], schizo_ce_intr, IRQF_SHARED, |
| 1013 | "TOMATILLO CE", p); |
| 1014 | |
| 1015 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); |
| 1016 | op = of_find_device_by_node(pbm->prom_node); |
| 1017 | if (op) |
| 1018 | request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED, |
| 1019 | "TOMATILLO PCIERR-A", pbm); |
| 1020 | |
| 1021 | |
| 1022 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); |
| 1023 | op = of_find_device_by_node(pbm->prom_node); |
| 1024 | if (op) |
| 1025 | request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED, |
| 1026 | "TOMATILLO PCIERR-B", pbm); |
| 1027 | |
| 1028 | pbm = pbm_for_ino(p, SCHIZO_SERR_INO); |
| 1029 | op = of_find_device_by_node(pbm->prom_node); |
| 1030 | if (op) |
| 1031 | request_irq(op->irqs[3], schizo_safarierr_intr, IRQF_SHARED, |
| 1032 | "TOMATILLO SERR", p); |
| 1033 | |
| 1034 | /* Enable UE and CE interrupts for controller. */ |
| 1035 | schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, |
| 1036 | (SCHIZO_ECCCTRL_EE | |
| 1037 | SCHIZO_ECCCTRL_UE | |
| 1038 | SCHIZO_ECCCTRL_CE)); |
| 1039 | |
| 1040 | schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL, |
| 1041 | (SCHIZO_ECCCTRL_EE | |
| 1042 | SCHIZO_ECCCTRL_UE | |
| 1043 | SCHIZO_ECCCTRL_CE)); |
| 1044 | |
| 1045 | /* Enable PCI Error interrupts and clear error |
| 1046 | * bits. |
| 1047 | */ |
| 1048 | err_mask = (SCHIZO_PCICTRL_BUS_UNUS | |
| 1049 | SCHIZO_PCICTRL_TTO_ERR | |
| 1050 | SCHIZO_PCICTRL_RTRY_ERR | |
| 1051 | SCHIZO_PCICTRL_SERR | |
| 1052 | SCHIZO_PCICTRL_EEN); |
| 1053 | |
| 1054 | err_no_mask = SCHIZO_PCICTRL_DTO_ERR; |
| 1055 | |
| 1056 | tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); |
| 1057 | tmp |= err_mask; |
| 1058 | tmp &= ~err_no_mask; |
| 1059 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp); |
| 1060 | |
| 1061 | tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL); |
| 1062 | tmp |= err_mask; |
| 1063 | tmp &= ~err_no_mask; |
| 1064 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); |
| 1065 | |
| 1066 | err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | |
| 1067 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | |
| 1068 | SCHIZO_PCIAFSR_PTTO | |
| 1069 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | |
| 1070 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | |
| 1071 | SCHIZO_PCIAFSR_STTO); |
| 1072 | |
| 1073 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask); |
| 1074 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask); |
| 1075 | |
| 1076 | err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | |
| 1077 | BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | |
| 1078 | BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | |
| 1079 | BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | |
| 1080 | BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | |
| 1081 | BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | |
| 1082 | BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | |
| 1083 | BUS_ERROR_APERR | BUS_ERROR_UNMAP | |
| 1084 | BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); |
| 1085 | |
| 1086 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, |
| 1087 | (SCHIZO_SAFERRCTRL_EN | err_mask)); |
| 1088 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL, |
| 1089 | (SCHIZO_SAFERRCTRL_EN | err_mask)); |
| 1090 | |
| 1091 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, |
| 1092 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); |
| 1093 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL, |
| 1094 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); |
| 1095 | } |
| 1096 | |
| 1097 | static void schizo_register_error_handlers(struct pci_controller_info *p) |
| 1098 | { |
| 1099 | struct pci_pbm_info *pbm; |
| 1100 | struct of_device *op; |
| 1101 | u64 tmp, err_mask, err_no_mask; |
| 1102 | |
| 1103 | /* Schizo IRQ property layout is: |
| 1104 | * 0: PCIERR |
| 1105 | * 1: UE ERR |
| 1106 | * 2: CE ERR |
| 1107 | * 3: SERR |
| 1108 | * 4: POWER FAIL? |
| 1109 | */ |
| 1110 | |
| 1111 | pbm = pbm_for_ino(p, SCHIZO_UE_INO); |
| 1112 | op = of_find_device_by_node(pbm->prom_node); |
| 1113 | if (op) |
| 1114 | request_irq(op->irqs[1], schizo_ue_intr, IRQF_SHARED, |
| 1115 | "SCHIZO_UE", p); |
| 1116 | |
| 1117 | pbm = pbm_for_ino(p, SCHIZO_CE_INO); |
| 1118 | op = of_find_device_by_node(pbm->prom_node); |
| 1119 | if (op) |
| 1120 | request_irq(op->irqs[2], schizo_ce_intr, IRQF_SHARED, |
| 1121 | "SCHIZO CE", p); |
| 1122 | |
| 1123 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); |
| 1124 | op = of_find_device_by_node(pbm->prom_node); |
| 1125 | if (op) |
| 1126 | request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED, |
| 1127 | "SCHIZO PCIERR-A", pbm); |
| 1128 | |
| 1129 | |
| 1130 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); |
| 1131 | op = of_find_device_by_node(pbm->prom_node); |
| 1132 | if (op) |
| 1133 | request_irq(op->irqs[0], schizo_pcierr_intr, IRQF_SHARED, |
| 1134 | "SCHIZO PCIERR-B", pbm); |
| 1135 | |
| 1136 | pbm = pbm_for_ino(p, SCHIZO_SERR_INO); |
| 1137 | op = of_find_device_by_node(pbm->prom_node); |
| 1138 | if (op) |
| 1139 | request_irq(op->irqs[3], schizo_safarierr_intr, IRQF_SHARED, |
| 1140 | "SCHIZO SERR", p); |
| 1141 | |
| 1142 | /* Enable UE and CE interrupts for controller. */ |
| 1143 | schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, |
| 1144 | (SCHIZO_ECCCTRL_EE | |
| 1145 | SCHIZO_ECCCTRL_UE | |
| 1146 | SCHIZO_ECCCTRL_CE)); |
| 1147 | |
| 1148 | err_mask = (SCHIZO_PCICTRL_BUS_UNUS | |
| 1149 | SCHIZO_PCICTRL_ESLCK | |
| 1150 | SCHIZO_PCICTRL_TTO_ERR | |
| 1151 | SCHIZO_PCICTRL_RTRY_ERR | |
| 1152 | SCHIZO_PCICTRL_SBH_ERR | |
| 1153 | SCHIZO_PCICTRL_SERR | |
| 1154 | SCHIZO_PCICTRL_EEN); |
| 1155 | |
| 1156 | err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | |
| 1157 | SCHIZO_PCICTRL_SBH_INT); |
| 1158 | |
| 1159 | /* Enable PCI Error interrupts and clear error |
| 1160 | * bits for each PBM. |
| 1161 | */ |
| 1162 | tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); |
| 1163 | tmp |= err_mask; |
| 1164 | tmp &= ~err_no_mask; |
| 1165 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp); |
| 1166 | |
| 1167 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, |
| 1168 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | |
| 1169 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | |
| 1170 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | |
| 1171 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | |
| 1172 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | |
| 1173 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); |
| 1174 | |
| 1175 | tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL); |
| 1176 | tmp |= err_mask; |
| 1177 | tmp &= ~err_no_mask; |
| 1178 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); |
| 1179 | |
| 1180 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, |
| 1181 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | |
| 1182 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | |
| 1183 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | |
| 1184 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | |
| 1185 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | |
| 1186 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); |
| 1187 | |
| 1188 | /* Make all Safari error conditions fatal except unmapped |
| 1189 | * errors which we make generate interrupts. |
| 1190 | */ |
| 1191 | err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | |
| 1192 | BUS_ERROR_BADMA | BUS_ERROR_BADMB | |
| 1193 | BUS_ERROR_BADMC | |
| 1194 | BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | |
| 1195 | BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | |
| 1196 | BUS_ERROR_CIQTO | |
| 1197 | BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | |
| 1198 | BUS_ERROR_UFPQTO | BUS_ERROR_APERR | |
| 1199 | BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | |
| 1200 | BUS_ERROR_ILL); |
| 1201 | #if 1 |
| 1202 | /* XXX Something wrong with some Excalibur systems |
| 1203 | * XXX Sun is shipping. The behavior on a 2-cpu |
| 1204 | * XXX machine is that both CPU1 parity error bits |
| 1205 | * XXX are set and are immediately set again when |
| 1206 | * XXX their error status bits are cleared. Just |
| 1207 | * XXX ignore them for now. -DaveM |
| 1208 | */ |
| 1209 | err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | |
| 1210 | BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); |
| 1211 | #endif |
| 1212 | |
| 1213 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, |
| 1214 | (SCHIZO_SAFERRCTRL_EN | err_mask)); |
| 1215 | |
| 1216 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, |
| 1217 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); |
| 1218 | } |
| 1219 | |
| 1220 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
| 1221 | { |
| 1222 | u8 *addr; |
| 1223 | |
| 1224 | /* Set cache-line size to 64 bytes, this is actually |
| 1225 | * a nop but I do it for completeness. |
| 1226 | */ |
| 1227 | addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 1228 | 0, PCI_CACHE_LINE_SIZE); |
| 1229 | pci_config_write8(addr, 64 / sizeof(u32)); |
| 1230 | |
| 1231 | /* Set PBM latency timer to 64 PCI clocks. */ |
| 1232 | addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 1233 | 0, PCI_LATENCY_TIMER); |
| 1234 | pci_config_write8(addr, 64); |
| 1235 | } |
| 1236 | |
| 1237 | static void schizo_scan_bus(struct pci_controller_info *p) |
| 1238 | { |
| 1239 | pbm_config_busmastering(&p->pbm_B); |
| 1240 | p->pbm_B.is_66mhz_capable = |
| 1241 | (of_find_property(p->pbm_B.prom_node, "66mhz-capable", NULL) |
| 1242 | != NULL); |
| 1243 | pbm_config_busmastering(&p->pbm_A); |
| 1244 | p->pbm_A.is_66mhz_capable = |
| 1245 | (of_find_property(p->pbm_A.prom_node, "66mhz-capable", NULL) |
| 1246 | != NULL); |
| 1247 | |
| 1248 | p->pbm_B.pci_bus = pci_scan_one_pbm(&p->pbm_B); |
| 1249 | p->pbm_A.pci_bus = pci_scan_one_pbm(&p->pbm_A); |
| 1250 | |
| 1251 | /* After the PCI bus scan is complete, we can register |
| 1252 | * the error interrupt handlers. |
| 1253 | */ |
| 1254 | if (p->pbm_B.chip_type == PBM_CHIP_TYPE_TOMATILLO) |
| 1255 | tomatillo_register_error_handlers(p); |
| 1256 | else |
| 1257 | schizo_register_error_handlers(p); |
| 1258 | } |
| 1259 | |
| 1260 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) |
| 1261 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) |
| 1262 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) |
| 1263 | #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) |
| 1264 | #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) |
| 1265 | |
| 1266 | static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) |
| 1267 | { |
| 1268 | unsigned long base = pbm->pbm_regs; |
| 1269 | u64 control; |
| 1270 | |
| 1271 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { |
| 1272 | /* TOMATILLO lacks streaming cache. */ |
| 1273 | return; |
| 1274 | } |
| 1275 | |
| 1276 | /* SCHIZO has context flushing. */ |
| 1277 | pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; |
| 1278 | pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; |
| 1279 | pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; |
| 1280 | pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; |
| 1281 | pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; |
| 1282 | |
| 1283 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) |
| 1284 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) |
| 1285 | + 63UL) |
| 1286 | & ~63UL); |
| 1287 | pbm->stc.strbuf_flushflag_pa = (unsigned long) |
| 1288 | __pa(pbm->stc.strbuf_flushflag); |
| 1289 | |
| 1290 | /* Turn off LRU locking and diag mode, enable the |
| 1291 | * streaming buffer and leave the rerun-disable |
| 1292 | * setting however OBP set it. |
| 1293 | */ |
| 1294 | control = schizo_read(pbm->stc.strbuf_control); |
| 1295 | control &= ~(SCHIZO_STRBUF_CTRL_LPTR | |
| 1296 | SCHIZO_STRBUF_CTRL_LENAB | |
| 1297 | SCHIZO_STRBUF_CTRL_DENAB); |
| 1298 | control |= SCHIZO_STRBUF_CTRL_ENAB; |
| 1299 | schizo_write(pbm->stc.strbuf_control, control); |
| 1300 | |
| 1301 | pbm->stc.strbuf_enabled = 1; |
| 1302 | } |
| 1303 | |
| 1304 | #define SCHIZO_IOMMU_CONTROL (0x00200UL) |
| 1305 | #define SCHIZO_IOMMU_TSBBASE (0x00208UL) |
| 1306 | #define SCHIZO_IOMMU_FLUSH (0x00210UL) |
| 1307 | #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) |
| 1308 | |
| 1309 | static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm) |
| 1310 | { |
| 1311 | struct iommu *iommu = pbm->iommu; |
| 1312 | unsigned long i, tagbase, database; |
| 1313 | struct property *prop; |
| 1314 | u32 vdma[2], dma_mask; |
| 1315 | u64 control; |
| 1316 | int tsbsize; |
| 1317 | |
| 1318 | prop = of_find_property(pbm->prom_node, "virtual-dma", NULL); |
| 1319 | if (prop) { |
| 1320 | u32 *val = prop->value; |
| 1321 | |
| 1322 | vdma[0] = val[0]; |
| 1323 | vdma[1] = val[1]; |
| 1324 | } else { |
| 1325 | /* No property, use default values. */ |
| 1326 | vdma[0] = 0xc0000000; |
| 1327 | vdma[1] = 0x40000000; |
| 1328 | } |
| 1329 | |
| 1330 | dma_mask = vdma[0]; |
| 1331 | switch (vdma[1]) { |
| 1332 | case 0x20000000: |
| 1333 | dma_mask |= 0x1fffffff; |
| 1334 | tsbsize = 64; |
| 1335 | break; |
| 1336 | |
| 1337 | case 0x40000000: |
| 1338 | dma_mask |= 0x3fffffff; |
| 1339 | tsbsize = 128; |
| 1340 | break; |
| 1341 | |
| 1342 | case 0x80000000: |
| 1343 | dma_mask |= 0x7fffffff; |
| 1344 | tsbsize = 128; |
| 1345 | break; |
| 1346 | |
| 1347 | default: |
| 1348 | prom_printf("SCHIZO: strange virtual-dma size.\n"); |
| 1349 | prom_halt(); |
| 1350 | }; |
| 1351 | |
| 1352 | /* Register addresses, SCHIZO has iommu ctx flushing. */ |
| 1353 | iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; |
| 1354 | iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; |
| 1355 | iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; |
| 1356 | iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; |
| 1357 | |
| 1358 | /* We use the main control/status register of SCHIZO as the write |
| 1359 | * completion register. |
| 1360 | */ |
| 1361 | iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; |
| 1362 | |
| 1363 | /* |
| 1364 | * Invalidate TLB Entries. |
| 1365 | */ |
| 1366 | control = schizo_read(iommu->iommu_control); |
| 1367 | control |= SCHIZO_IOMMU_CTRL_DENAB; |
| 1368 | schizo_write(iommu->iommu_control, control); |
| 1369 | |
| 1370 | tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; |
| 1371 | |
| 1372 | for(i = 0; i < 16; i++) { |
| 1373 | schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0); |
| 1374 | schizo_write(pbm->pbm_regs + database + (i * 8UL), 0); |
| 1375 | } |
| 1376 | |
| 1377 | /* Leave diag mode enabled for full-flushing done |
| 1378 | * in pci_iommu.c |
| 1379 | */ |
| 1380 | pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask); |
| 1381 | |
| 1382 | schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table)); |
| 1383 | |
| 1384 | control = schizo_read(iommu->iommu_control); |
| 1385 | control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); |
| 1386 | switch (tsbsize) { |
| 1387 | case 64: |
| 1388 | control |= SCHIZO_IOMMU_TSBSZ_64K; |
| 1389 | break; |
| 1390 | case 128: |
| 1391 | control |= SCHIZO_IOMMU_TSBSZ_128K; |
| 1392 | break; |
| 1393 | }; |
| 1394 | |
| 1395 | control |= SCHIZO_IOMMU_CTRL_ENAB; |
| 1396 | schizo_write(iommu->iommu_control, control); |
| 1397 | } |
| 1398 | |
| 1399 | #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) |
| 1400 | #define SCHIZO_IRQ_RETRY_INF 0xffUL |
| 1401 | |
| 1402 | #define SCHIZO_PCI_DIAG (0x2020UL) |
| 1403 | #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ |
| 1404 | #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ |
| 1405 | #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ |
| 1406 | #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ |
| 1407 | #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ |
| 1408 | #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ |
| 1409 | #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ |
| 1410 | #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ |
| 1411 | #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ |
| 1412 | |
| 1413 | #define TOMATILLO_PCI_IOC_CSR (0x2248UL) |
| 1414 | #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL |
| 1415 | #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL |
| 1416 | #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL |
| 1417 | #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL |
| 1418 | #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL |
| 1419 | #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL |
| 1420 | #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL |
| 1421 | #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL |
| 1422 | #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL |
| 1423 | #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL |
| 1424 | #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL |
| 1425 | #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL |
| 1426 | #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL |
| 1427 | #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL |
| 1428 | #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL |
| 1429 | |
| 1430 | #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) |
| 1431 | #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) |
| 1432 | |
| 1433 | static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) |
| 1434 | { |
| 1435 | struct property *prop; |
| 1436 | u64 tmp; |
| 1437 | |
| 1438 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5); |
| 1439 | |
| 1440 | tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); |
| 1441 | |
| 1442 | /* Enable arbiter for all PCI slots. */ |
| 1443 | tmp |= 0xff; |
| 1444 | |
| 1445 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && |
| 1446 | pbm->chip_version >= 0x2) |
| 1447 | tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; |
| 1448 | |
| 1449 | prop = of_find_property(pbm->prom_node, "no-bus-parking", NULL); |
| 1450 | if (!prop) |
| 1451 | tmp |= SCHIZO_PCICTRL_PARK; |
| 1452 | else |
| 1453 | tmp &= ~SCHIZO_PCICTRL_PARK; |
| 1454 | |
| 1455 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && |
| 1456 | pbm->chip_version <= 0x1) |
| 1457 | tmp |= SCHIZO_PCICTRL_DTO_INT; |
| 1458 | else |
| 1459 | tmp &= ~SCHIZO_PCICTRL_DTO_INT; |
| 1460 | |
| 1461 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) |
| 1462 | tmp |= (SCHIZO_PCICTRL_MRM_PREF | |
| 1463 | SCHIZO_PCICTRL_RDO_PREF | |
| 1464 | SCHIZO_PCICTRL_RDL_PREF); |
| 1465 | |
| 1466 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); |
| 1467 | |
| 1468 | tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG); |
| 1469 | tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | |
| 1470 | SCHIZO_PCIDIAG_D_RETRY | |
| 1471 | SCHIZO_PCIDIAG_D_INTSYNC); |
| 1472 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp); |
| 1473 | |
| 1474 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { |
| 1475 | /* Clear prefetch lengths to workaround a bug in |
| 1476 | * Jalapeno... |
| 1477 | */ |
| 1478 | tmp = (TOMATILLO_IOC_PART_WPENAB | |
| 1479 | (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | |
| 1480 | TOMATILLO_IOC_RDMULT_CPENAB | |
| 1481 | TOMATILLO_IOC_RDONE_CPENAB | |
| 1482 | TOMATILLO_IOC_RDLINE_CPENAB); |
| 1483 | |
| 1484 | schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR, |
| 1485 | tmp); |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | static void schizo_pbm_init(struct pci_controller_info *p, |
| 1490 | struct device_node *dp, u32 portid, |
| 1491 | int chip_type) |
| 1492 | { |
| 1493 | const struct linux_prom64_registers *regs; |
| 1494 | const unsigned int *busrange; |
| 1495 | struct pci_pbm_info *pbm; |
| 1496 | const char *chipset_name; |
| 1497 | const u32 *ino_bitmap; |
| 1498 | int is_pbm_a; |
| 1499 | |
| 1500 | switch (chip_type) { |
| 1501 | case PBM_CHIP_TYPE_TOMATILLO: |
| 1502 | chipset_name = "TOMATILLO"; |
| 1503 | break; |
| 1504 | |
| 1505 | case PBM_CHIP_TYPE_SCHIZO_PLUS: |
| 1506 | chipset_name = "SCHIZO+"; |
| 1507 | break; |
| 1508 | |
| 1509 | case PBM_CHIP_TYPE_SCHIZO: |
| 1510 | default: |
| 1511 | chipset_name = "SCHIZO"; |
| 1512 | break; |
| 1513 | }; |
| 1514 | |
| 1515 | /* For SCHIZO, three OBP regs: |
| 1516 | * 1) PBM controller regs |
| 1517 | * 2) Schizo front-end controller regs (same for both PBMs) |
| 1518 | * 3) PBM PCI config space |
| 1519 | * |
| 1520 | * For TOMATILLO, four OBP regs: |
| 1521 | * 1) PBM controller regs |
| 1522 | * 2) Tomatillo front-end controller regs |
| 1523 | * 3) PBM PCI config space |
| 1524 | * 4) Ichip regs |
| 1525 | */ |
| 1526 | regs = of_get_property(dp, "reg", NULL); |
| 1527 | |
| 1528 | is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000); |
| 1529 | if (is_pbm_a) |
| 1530 | pbm = &p->pbm_A; |
| 1531 | else |
| 1532 | pbm = &p->pbm_B; |
| 1533 | |
| 1534 | pbm->portid = portid; |
| 1535 | pbm->parent = p; |
| 1536 | pbm->prom_node = dp; |
| 1537 | |
| 1538 | pbm->chip_type = chip_type; |
| 1539 | pbm->chip_version = of_getintprop_default(dp, "version#", 0); |
| 1540 | pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0); |
| 1541 | |
| 1542 | pbm->pbm_regs = regs[0].phys_addr; |
| 1543 | pbm->controller_regs = regs[1].phys_addr - 0x10000UL; |
| 1544 | |
| 1545 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) |
| 1546 | pbm->sync_reg = regs[3].phys_addr + 0x1a18UL; |
| 1547 | |
| 1548 | pbm->name = dp->full_name; |
| 1549 | |
| 1550 | printk("%s: %s PCI Bus Module ver[%x:%x]\n", |
| 1551 | pbm->name, chipset_name, |
| 1552 | pbm->chip_version, pbm->chip_revision); |
| 1553 | |
| 1554 | schizo_pbm_hw_init(pbm); |
| 1555 | |
| 1556 | pci_determine_mem_io_space(pbm); |
| 1557 | |
| 1558 | ino_bitmap = of_get_property(dp, "ino-bitmap", NULL); |
| 1559 | pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) | |
| 1560 | ((u64)ino_bitmap[0] << 0UL)); |
| 1561 | |
| 1562 | busrange = of_get_property(dp, "bus-range", NULL); |
| 1563 | pbm->pci_first_busno = busrange[0]; |
| 1564 | pbm->pci_last_busno = busrange[1]; |
| 1565 | |
| 1566 | schizo_pbm_iommu_init(pbm); |
| 1567 | schizo_pbm_strbuf_init(pbm); |
| 1568 | } |
| 1569 | |
| 1570 | static inline int portid_compare(u32 x, u32 y, int chip_type) |
| 1571 | { |
| 1572 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { |
| 1573 | if (x == (y ^ 1)) |
| 1574 | return 1; |
| 1575 | return 0; |
| 1576 | } |
| 1577 | return (x == y); |
| 1578 | } |
| 1579 | |
| 1580 | static void __schizo_init(struct device_node *dp, char *model_name, int chip_type) |
| 1581 | { |
| 1582 | struct pci_controller_info *p; |
| 1583 | struct iommu *iommu; |
| 1584 | u32 portid; |
| 1585 | |
| 1586 | portid = of_getintprop_default(dp, "portid", 0xff); |
| 1587 | |
| 1588 | for (p = pci_controller_root; p; p = p->next) { |
| 1589 | struct pci_pbm_info *pbm; |
| 1590 | |
| 1591 | if (p->pbm_A.prom_node && p->pbm_B.prom_node) |
| 1592 | continue; |
| 1593 | |
| 1594 | pbm = (p->pbm_A.prom_node ? |
| 1595 | &p->pbm_A : |
| 1596 | &p->pbm_B); |
| 1597 | |
| 1598 | if (portid_compare(pbm->portid, portid, chip_type)) { |
| 1599 | schizo_pbm_init(p, dp, portid, chip_type); |
| 1600 | return; |
| 1601 | } |
| 1602 | } |
| 1603 | |
| 1604 | p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
| 1605 | if (!p) |
| 1606 | goto memfail; |
| 1607 | |
| 1608 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
| 1609 | if (!iommu) |
| 1610 | goto memfail; |
| 1611 | |
| 1612 | p->pbm_A.iommu = iommu; |
| 1613 | |
| 1614 | iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); |
| 1615 | if (!iommu) |
| 1616 | goto memfail; |
| 1617 | |
| 1618 | p->pbm_B.iommu = iommu; |
| 1619 | |
| 1620 | p->next = pci_controller_root; |
| 1621 | pci_controller_root = p; |
| 1622 | |
| 1623 | p->index = pci_num_controllers++; |
| 1624 | p->scan_bus = schizo_scan_bus; |
| 1625 | p->pci_ops = &schizo_ops; |
| 1626 | |
| 1627 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ |
| 1628 | pci_memspace_mask = 0x7fffffffUL; |
| 1629 | |
| 1630 | schizo_pbm_init(p, dp, portid, chip_type); |
| 1631 | return; |
| 1632 | |
| 1633 | memfail: |
| 1634 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); |
| 1635 | prom_halt(); |
| 1636 | } |
| 1637 | |
| 1638 | void schizo_init(struct device_node *dp, char *model_name) |
| 1639 | { |
| 1640 | __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO); |
| 1641 | } |
| 1642 | |
| 1643 | void schizo_plus_init(struct device_node *dp, char *model_name) |
| 1644 | { |
| 1645 | __schizo_init(dp, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS); |
| 1646 | } |
| 1647 | |
| 1648 | void tomatillo_init(struct device_node *dp, char *model_name) |
| 1649 | { |
| 1650 | __schizo_init(dp, model_name, PBM_CHIP_TYPE_TOMATILLO); |
| 1651 | } |