| 1 | #include <linux/perf_event.h> |
| 2 | #include <linux/types.h> |
| 3 | |
| 4 | #include "perf_event.h" |
| 5 | |
| 6 | /* |
| 7 | * Not sure about some of these |
| 8 | */ |
| 9 | static const u64 p6_perfmon_event_map[] = |
| 10 | { |
| 11 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, |
| 12 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| 13 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, |
| 14 | [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, |
| 15 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 16 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
| 17 | [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, |
| 18 | }; |
| 19 | |
| 20 | static u64 p6_pmu_event_map(int hw_event) |
| 21 | { |
| 22 | return p6_perfmon_event_map[hw_event]; |
| 23 | } |
| 24 | |
| 25 | /* |
| 26 | * Event setting that is specified not to count anything. |
| 27 | * We use this to effectively disable a counter. |
| 28 | * |
| 29 | * L2_RQSTS with 0 MESI unit mask. |
| 30 | */ |
| 31 | #define P6_NOP_EVENT 0x0000002EULL |
| 32 | |
| 33 | static struct event_constraint p6_event_constraints[] = |
| 34 | { |
| 35 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ |
| 36 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
| 37 | INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */ |
| 38 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ |
| 39 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ |
| 40 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ |
| 41 | EVENT_CONSTRAINT_END |
| 42 | }; |
| 43 | |
| 44 | static void p6_pmu_disable_all(void) |
| 45 | { |
| 46 | u64 val; |
| 47 | |
| 48 | /* p6 only has one enable register */ |
| 49 | rdmsrl(MSR_P6_EVNTSEL0, val); |
| 50 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
| 51 | wrmsrl(MSR_P6_EVNTSEL0, val); |
| 52 | } |
| 53 | |
| 54 | static void p6_pmu_enable_all(int added) |
| 55 | { |
| 56 | unsigned long val; |
| 57 | |
| 58 | /* p6 only has one enable register */ |
| 59 | rdmsrl(MSR_P6_EVNTSEL0, val); |
| 60 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
| 61 | wrmsrl(MSR_P6_EVNTSEL0, val); |
| 62 | } |
| 63 | |
| 64 | static inline void |
| 65 | p6_pmu_disable_event(struct perf_event *event) |
| 66 | { |
| 67 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 68 | struct hw_perf_event *hwc = &event->hw; |
| 69 | u64 val = P6_NOP_EVENT; |
| 70 | |
| 71 | if (cpuc->enabled) |
| 72 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
| 73 | |
| 74 | (void)wrmsrl_safe(hwc->config_base, val); |
| 75 | } |
| 76 | |
| 77 | static void p6_pmu_enable_event(struct perf_event *event) |
| 78 | { |
| 79 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 80 | struct hw_perf_event *hwc = &event->hw; |
| 81 | u64 val; |
| 82 | |
| 83 | val = hwc->config; |
| 84 | if (cpuc->enabled) |
| 85 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
| 86 | |
| 87 | (void)wrmsrl_safe(hwc->config_base, val); |
| 88 | } |
| 89 | |
| 90 | PMU_FORMAT_ATTR(event, "config:0-7" ); |
| 91 | PMU_FORMAT_ATTR(umask, "config:8-15" ); |
| 92 | PMU_FORMAT_ATTR(edge, "config:18" ); |
| 93 | PMU_FORMAT_ATTR(pc, "config:19" ); |
| 94 | PMU_FORMAT_ATTR(inv, "config:23" ); |
| 95 | PMU_FORMAT_ATTR(cmask, "config:24-31" ); |
| 96 | |
| 97 | static struct attribute *intel_p6_formats_attr[] = { |
| 98 | &format_attr_event.attr, |
| 99 | &format_attr_umask.attr, |
| 100 | &format_attr_edge.attr, |
| 101 | &format_attr_pc.attr, |
| 102 | &format_attr_inv.attr, |
| 103 | &format_attr_cmask.attr, |
| 104 | NULL, |
| 105 | }; |
| 106 | |
| 107 | static __initconst const struct x86_pmu p6_pmu = { |
| 108 | .name = "p6", |
| 109 | .handle_irq = x86_pmu_handle_irq, |
| 110 | .disable_all = p6_pmu_disable_all, |
| 111 | .enable_all = p6_pmu_enable_all, |
| 112 | .enable = p6_pmu_enable_event, |
| 113 | .disable = p6_pmu_disable_event, |
| 114 | .hw_config = x86_pmu_hw_config, |
| 115 | .schedule_events = x86_schedule_events, |
| 116 | .eventsel = MSR_P6_EVNTSEL0, |
| 117 | .perfctr = MSR_P6_PERFCTR0, |
| 118 | .event_map = p6_pmu_event_map, |
| 119 | .max_events = ARRAY_SIZE(p6_perfmon_event_map), |
| 120 | .apic = 1, |
| 121 | .max_period = (1ULL << 31) - 1, |
| 122 | .version = 0, |
| 123 | .num_counters = 2, |
| 124 | /* |
| 125 | * Events have 40 bits implemented. However they are designed such |
| 126 | * that bits [32-39] are sign extensions of bit 31. As such the |
| 127 | * effective width of a event for P6-like PMU is 32 bits only. |
| 128 | * |
| 129 | * See IA-32 Intel Architecture Software developer manual Vol 3B |
| 130 | */ |
| 131 | .cntval_bits = 32, |
| 132 | .cntval_mask = (1ULL << 32) - 1, |
| 133 | .get_event_constraints = x86_get_event_constraints, |
| 134 | .event_constraints = p6_event_constraints, |
| 135 | |
| 136 | .format_attrs = intel_p6_formats_attr, |
| 137 | }; |
| 138 | |
| 139 | __init int p6_pmu_init(void) |
| 140 | { |
| 141 | switch (boot_cpu_data.x86_model) { |
| 142 | case 1: |
| 143 | case 3: /* Pentium Pro */ |
| 144 | case 5: |
| 145 | case 6: /* Pentium II */ |
| 146 | case 7: |
| 147 | case 8: |
| 148 | case 11: /* Pentium III */ |
| 149 | case 9: |
| 150 | case 13: |
| 151 | /* Pentium M */ |
| 152 | break; |
| 153 | default: |
| 154 | pr_cont("unsupported p6 CPU model %d ", |
| 155 | boot_cpu_data.x86_model); |
| 156 | return -ENODEV; |
| 157 | } |
| 158 | |
| 159 | x86_pmu = p6_pmu; |
| 160 | |
| 161 | return 0; |
| 162 | } |