| 1 | /* |
| 2 | * Intel IO-APIC support for multi-Pentium hosts. |
| 3 | * |
| 4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo |
| 5 | * |
| 6 | * Many thanks to Stig Venaas for trying out countless experimental |
| 7 | * patches and reporting/debugging problems patiently! |
| 8 | * |
| 9 | * (c) 1999, Multiple IO-APIC support, developed by |
| 10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and |
| 11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, |
| 12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> |
| 13 | * and Ingo Molnar <mingo@redhat.com> |
| 14 | * |
| 15 | * Fixes |
| 16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 17 | * thanks to Eric Gilmore |
| 18 | * and Rolf G. Tews |
| 19 | * for testing these extensively |
| 20 | * Paul Diefenbaugh : Added full ACPI support |
| 21 | */ |
| 22 | |
| 23 | #include <linux/mm.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/sched.h> |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/mc146818rtc.h> |
| 30 | #include <linux/compiler.h> |
| 31 | #include <linux/acpi.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <linux/sysdev.h> |
| 34 | #include <linux/msi.h> |
| 35 | #include <linux/htirq.h> |
| 36 | #include <linux/freezer.h> |
| 37 | #include <linux/kthread.h> |
| 38 | #include <linux/jiffies.h> /* time_after() */ |
| 39 | #ifdef CONFIG_ACPI |
| 40 | #include <acpi/acpi_bus.h> |
| 41 | #endif |
| 42 | #include <linux/bootmem.h> |
| 43 | #include <linux/dmar.h> |
| 44 | #include <linux/hpet.h> |
| 45 | |
| 46 | #include <asm/idle.h> |
| 47 | #include <asm/io.h> |
| 48 | #include <asm/smp.h> |
| 49 | #include <asm/desc.h> |
| 50 | #include <asm/proto.h> |
| 51 | #include <asm/acpi.h> |
| 52 | #include <asm/dma.h> |
| 53 | #include <asm/timer.h> |
| 54 | #include <asm/i8259.h> |
| 55 | #include <asm/nmi.h> |
| 56 | #include <asm/msidef.h> |
| 57 | #include <asm/hypertransport.h> |
| 58 | #include <asm/setup.h> |
| 59 | #include <asm/irq_remapping.h> |
| 60 | #include <asm/hpet.h> |
| 61 | #include <asm/uv/uv_hub.h> |
| 62 | #include <asm/uv/uv_irq.h> |
| 63 | |
| 64 | #include <mach_ipi.h> |
| 65 | #include <mach_apic.h> |
| 66 | #include <mach_apicdef.h> |
| 67 | |
| 68 | #define __apicdebuginit(type) static type __init |
| 69 | |
| 70 | /* |
| 71 | * Is the SiS APIC rmw bug present ? |
| 72 | * -1 = don't know, 0 = no, 1 = yes |
| 73 | */ |
| 74 | int sis_apic_bug = -1; |
| 75 | |
| 76 | static DEFINE_SPINLOCK(ioapic_lock); |
| 77 | static DEFINE_SPINLOCK(vector_lock); |
| 78 | |
| 79 | /* |
| 80 | * # of IRQ routing registers |
| 81 | */ |
| 82 | int nr_ioapic_registers[MAX_IO_APICS]; |
| 83 | |
| 84 | /* I/O APIC entries */ |
| 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
| 86 | int nr_ioapics; |
| 87 | |
| 88 | /* MP IRQ source entries */ |
| 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
| 90 | |
| 91 | /* # of MP IRQ source entries */ |
| 92 | int mp_irq_entries; |
| 93 | |
| 94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
| 95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
| 96 | #endif |
| 97 | |
| 98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
| 99 | |
| 100 | int skip_ioapic_setup; |
| 101 | |
| 102 | static int __init parse_noapic(char *str) |
| 103 | { |
| 104 | /* disable IO-APIC */ |
| 105 | disable_ioapic_setup(); |
| 106 | return 0; |
| 107 | } |
| 108 | early_param("noapic", parse_noapic); |
| 109 | |
| 110 | struct irq_cfg; |
| 111 | struct irq_pin_list; |
| 112 | struct irq_cfg { |
| 113 | unsigned int irq; |
| 114 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
| 115 | struct irq_cfg *next; |
| 116 | #endif |
| 117 | struct irq_pin_list *irq_2_pin; |
| 118 | cpumask_t domain; |
| 119 | cpumask_t old_domain; |
| 120 | unsigned move_cleanup_count; |
| 121 | u8 vector; |
| 122 | u8 move_in_progress : 1; |
| 123 | }; |
| 124 | |
| 125 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
| 126 | static struct irq_cfg irq_cfg_legacy[] __initdata = { |
| 127 | [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
| 128 | [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, |
| 129 | [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, |
| 130 | [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, |
| 131 | [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, |
| 132 | [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, |
| 133 | [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, |
| 134 | [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, |
| 135 | [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, |
| 136 | [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, |
| 137 | [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, |
| 138 | [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, |
| 139 | [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, |
| 140 | [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, |
| 141 | [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, |
| 142 | [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, |
| 143 | }; |
| 144 | |
| 145 | static struct irq_cfg irq_cfg_init = { .irq = -1U, }; |
| 146 | |
| 147 | static void init_one_irq_cfg(struct irq_cfg *cfg) |
| 148 | { |
| 149 | memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg)); |
| 150 | } |
| 151 | |
| 152 | static struct irq_cfg *irq_cfgx; |
| 153 | |
| 154 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
| 155 | /* |
| 156 | * Protect the irq_cfgx_free freelist: |
| 157 | */ |
| 158 | static DEFINE_SPINLOCK(irq_cfg_lock); |
| 159 | |
| 160 | static struct irq_cfg *irq_cfgx_free; |
| 161 | #endif |
| 162 | |
| 163 | static void __init init_work(void *data) |
| 164 | { |
| 165 | struct dyn_array *da = data; |
| 166 | struct irq_cfg *cfg; |
| 167 | int legacy_count; |
| 168 | int i; |
| 169 | |
| 170 | cfg = *da->name; |
| 171 | |
| 172 | memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy)); |
| 173 | |
| 174 | legacy_count = ARRAY_SIZE(irq_cfg_legacy); |
| 175 | for (i = legacy_count; i < *da->nr; i++) |
| 176 | init_one_irq_cfg(&cfg[i]); |
| 177 | |
| 178 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
| 179 | for (i = 1; i < *da->nr; i++) |
| 180 | cfg[i-1].next = &cfg[i]; |
| 181 | |
| 182 | irq_cfgx_free = &irq_cfgx[legacy_count]; |
| 183 | irq_cfgx[legacy_count - 1].next = NULL; |
| 184 | #endif |
| 185 | } |
| 186 | |
| 187 | #ifdef CONFIG_HAVE_SPARSE_IRQ |
| 188 | /* need to be biger than size of irq_cfg_legacy */ |
| 189 | static int nr_irq_cfg = 32; |
| 190 | |
| 191 | static int __init parse_nr_irq_cfg(char *arg) |
| 192 | { |
| 193 | if (arg) { |
| 194 | nr_irq_cfg = simple_strtoul(arg, NULL, 0); |
| 195 | if (nr_irq_cfg < 32) |
| 196 | nr_irq_cfg = 32; |
| 197 | } |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | early_param("nr_irq_cfg", parse_nr_irq_cfg); |
| 202 | |
| 203 | #define for_each_irq_cfg(irqX, cfg) \ |
| 204 | for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U) |
| 205 | |
| 206 | |
| 207 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work); |
| 208 | |
| 209 | static struct irq_cfg *irq_cfg(unsigned int irq) |
| 210 | { |
| 211 | struct irq_cfg *cfg; |
| 212 | |
| 213 | cfg = irq_cfgx; |
| 214 | while (cfg) { |
| 215 | if (cfg->irq == irq) |
| 216 | return cfg; |
| 217 | |
| 218 | cfg = cfg->next; |
| 219 | } |
| 220 | |
| 221 | return NULL; |
| 222 | } |
| 223 | |
| 224 | static struct irq_cfg *irq_cfg_alloc(unsigned int irq) |
| 225 | { |
| 226 | struct irq_cfg *cfg, *cfg_pri; |
| 227 | unsigned long flags; |
| 228 | int count = 0; |
| 229 | int i; |
| 230 | |
| 231 | cfg_pri = cfg = irq_cfgx; |
| 232 | while (cfg) { |
| 233 | if (cfg->irq == irq) |
| 234 | return cfg; |
| 235 | |
| 236 | cfg_pri = cfg; |
| 237 | cfg = cfg->next; |
| 238 | count++; |
| 239 | } |
| 240 | |
| 241 | spin_lock_irqsave(&irq_cfg_lock, flags); |
| 242 | if (!irq_cfgx_free) { |
| 243 | unsigned long phys; |
| 244 | unsigned long total_bytes; |
| 245 | /* |
| 246 | * we run out of pre-allocate ones, allocate more |
| 247 | */ |
| 248 | printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg); |
| 249 | |
| 250 | total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg; |
| 251 | if (after_bootmem) |
| 252 | cfg = kzalloc(total_bytes, GFP_ATOMIC); |
| 253 | else |
| 254 | cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0); |
| 255 | |
| 256 | if (!cfg) |
| 257 | panic("please boot with nr_irq_cfg= %d\n", count * 2); |
| 258 | |
| 259 | phys = __pa(cfg); |
| 260 | printk(KERN_DEBUG "irq_cfg ==> [%#lx - %#lx]\n", phys, phys + total_bytes); |
| 261 | |
| 262 | for (i = 0; i < nr_irq_cfg; i++) |
| 263 | init_one_irq_cfg(&cfg[i]); |
| 264 | |
| 265 | for (i = 1; i < nr_irq_cfg; i++) |
| 266 | cfg[i-1].next = &cfg[i]; |
| 267 | |
| 268 | irq_cfgx_free = cfg; |
| 269 | } |
| 270 | |
| 271 | cfg = irq_cfgx_free; |
| 272 | irq_cfgx_free = irq_cfgx_free->next; |
| 273 | cfg->next = NULL; |
| 274 | if (cfg_pri) |
| 275 | cfg_pri->next = cfg; |
| 276 | else |
| 277 | irq_cfgx = cfg; |
| 278 | cfg->irq = irq; |
| 279 | |
| 280 | spin_unlock_irqrestore(&irq_cfg_lock, flags); |
| 281 | |
| 282 | return cfg; |
| 283 | } |
| 284 | #else |
| 285 | |
| 286 | #define for_each_irq_cfg(irq, cfg) \ |
| 287 | for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq]) |
| 288 | |
| 289 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work); |
| 290 | |
| 291 | struct irq_cfg *irq_cfg(unsigned int irq) |
| 292 | { |
| 293 | if (irq < nr_irqs) |
| 294 | return &irq_cfgx[irq]; |
| 295 | |
| 296 | return NULL; |
| 297 | } |
| 298 | struct irq_cfg *irq_cfg_alloc(unsigned int irq) |
| 299 | { |
| 300 | return irq_cfg(irq); |
| 301 | } |
| 302 | |
| 303 | #endif |
| 304 | /* |
| 305 | * This is performance-critical, we want to do it O(1) |
| 306 | * |
| 307 | * the indexing order of this array favors 1:1 mappings |
| 308 | * between pins and IRQs. |
| 309 | */ |
| 310 | |
| 311 | struct irq_pin_list { |
| 312 | int apic, pin; |
| 313 | struct irq_pin_list *next; |
| 314 | }; |
| 315 | |
| 316 | static struct irq_pin_list *irq_2_pin_head; |
| 317 | /* fill one page ? */ |
| 318 | static int nr_irq_2_pin = 0x100; |
| 319 | static struct irq_pin_list *irq_2_pin_ptr; |
| 320 | static void __init irq_2_pin_init_work(void *data) |
| 321 | { |
| 322 | struct dyn_array *da = data; |
| 323 | struct irq_pin_list *pin; |
| 324 | int i; |
| 325 | |
| 326 | pin = *da->name; |
| 327 | |
| 328 | for (i = 1; i < *da->nr; i++) |
| 329 | pin[i-1].next = &pin[i]; |
| 330 | |
| 331 | irq_2_pin_ptr = &pin[0]; |
| 332 | } |
| 333 | DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work); |
| 334 | |
| 335 | static struct irq_pin_list *get_one_free_irq_2_pin(void) |
| 336 | { |
| 337 | struct irq_pin_list *pin; |
| 338 | int i; |
| 339 | |
| 340 | pin = irq_2_pin_ptr; |
| 341 | |
| 342 | if (pin) { |
| 343 | irq_2_pin_ptr = pin->next; |
| 344 | pin->next = NULL; |
| 345 | return pin; |
| 346 | } |
| 347 | |
| 348 | /* |
| 349 | * we run out of pre-allocate ones, allocate more |
| 350 | */ |
| 351 | printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin); |
| 352 | |
| 353 | if (after_bootmem) |
| 354 | pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin, |
| 355 | GFP_ATOMIC); |
| 356 | else |
| 357 | pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) * |
| 358 | nr_irq_2_pin, PAGE_SIZE, 0); |
| 359 | |
| 360 | if (!pin) |
| 361 | panic("can not get more irq_2_pin\n"); |
| 362 | |
| 363 | for (i = 1; i < nr_irq_2_pin; i++) |
| 364 | pin[i-1].next = &pin[i]; |
| 365 | |
| 366 | irq_2_pin_ptr = pin->next; |
| 367 | pin->next = NULL; |
| 368 | |
| 369 | return pin; |
| 370 | } |
| 371 | |
| 372 | struct io_apic { |
| 373 | unsigned int index; |
| 374 | unsigned int unused[3]; |
| 375 | unsigned int data; |
| 376 | }; |
| 377 | |
| 378 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) |
| 379 | { |
| 380 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) |
| 381 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
| 382 | } |
| 383 | |
| 384 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
| 385 | { |
| 386 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 387 | writel(reg, &io_apic->index); |
| 388 | return readl(&io_apic->data); |
| 389 | } |
| 390 | |
| 391 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
| 392 | { |
| 393 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 394 | writel(reg, &io_apic->index); |
| 395 | writel(value, &io_apic->data); |
| 396 | } |
| 397 | |
| 398 | /* |
| 399 | * Re-write a value: to be used for read-modify-write |
| 400 | * cycles where the read already set up the index register. |
| 401 | * |
| 402 | * Older SiS APIC requires we rewrite the index register |
| 403 | */ |
| 404 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
| 405 | { |
| 406 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 407 | if (sis_apic_bug) |
| 408 | writel(reg, &io_apic->index); |
| 409 | writel(value, &io_apic->data); |
| 410 | } |
| 411 | |
| 412 | static bool io_apic_level_ack_pending(unsigned int irq) |
| 413 | { |
| 414 | struct irq_pin_list *entry; |
| 415 | unsigned long flags; |
| 416 | struct irq_cfg *cfg = irq_cfg(irq); |
| 417 | |
| 418 | spin_lock_irqsave(&ioapic_lock, flags); |
| 419 | entry = cfg->irq_2_pin; |
| 420 | for (;;) { |
| 421 | unsigned int reg; |
| 422 | int pin; |
| 423 | |
| 424 | if (!entry) |
| 425 | break; |
| 426 | pin = entry->pin; |
| 427 | reg = io_apic_read(entry->apic, 0x10 + pin*2); |
| 428 | /* Is the remote IRR bit set? */ |
| 429 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { |
| 430 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 431 | return true; |
| 432 | } |
| 433 | if (!entry->next) |
| 434 | break; |
| 435 | entry = entry->next; |
| 436 | } |
| 437 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 438 | |
| 439 | return false; |
| 440 | } |
| 441 | |
| 442 | union entry_union { |
| 443 | struct { u32 w1, w2; }; |
| 444 | struct IO_APIC_route_entry entry; |
| 445 | }; |
| 446 | |
| 447 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
| 448 | { |
| 449 | union entry_union eu; |
| 450 | unsigned long flags; |
| 451 | spin_lock_irqsave(&ioapic_lock, flags); |
| 452 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
| 453 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); |
| 454 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 455 | return eu.entry; |
| 456 | } |
| 457 | |
| 458 | /* |
| 459 | * When we write a new IO APIC routing entry, we need to write the high |
| 460 | * word first! If the mask bit in the low word is clear, we will enable |
| 461 | * the interrupt, and we need to make sure the entry is fully populated |
| 462 | * before that happens. |
| 463 | */ |
| 464 | static void |
| 465 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
| 466 | { |
| 467 | union entry_union eu; |
| 468 | eu.entry = e; |
| 469 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
| 470 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
| 471 | } |
| 472 | |
| 473 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
| 474 | { |
| 475 | unsigned long flags; |
| 476 | spin_lock_irqsave(&ioapic_lock, flags); |
| 477 | __ioapic_write_entry(apic, pin, e); |
| 478 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 479 | } |
| 480 | |
| 481 | /* |
| 482 | * When we mask an IO APIC routing entry, we need to write the low |
| 483 | * word first, in order to set the mask bit before we change the |
| 484 | * high bits! |
| 485 | */ |
| 486 | static void ioapic_mask_entry(int apic, int pin) |
| 487 | { |
| 488 | unsigned long flags; |
| 489 | union entry_union eu = { .entry.mask = 1 }; |
| 490 | |
| 491 | spin_lock_irqsave(&ioapic_lock, flags); |
| 492 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
| 493 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
| 494 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 495 | } |
| 496 | |
| 497 | #ifdef CONFIG_SMP |
| 498 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) |
| 499 | { |
| 500 | int apic, pin; |
| 501 | struct irq_cfg *cfg; |
| 502 | struct irq_pin_list *entry; |
| 503 | |
| 504 | cfg = irq_cfg(irq); |
| 505 | entry = cfg->irq_2_pin; |
| 506 | for (;;) { |
| 507 | unsigned int reg; |
| 508 | |
| 509 | if (!entry) |
| 510 | break; |
| 511 | |
| 512 | apic = entry->apic; |
| 513 | pin = entry->pin; |
| 514 | #ifdef CONFIG_INTR_REMAP |
| 515 | /* |
| 516 | * With interrupt-remapping, destination information comes |
| 517 | * from interrupt-remapping table entry. |
| 518 | */ |
| 519 | if (!irq_remapped(irq)) |
| 520 | io_apic_write(apic, 0x11 + pin*2, dest); |
| 521 | #else |
| 522 | io_apic_write(apic, 0x11 + pin*2, dest); |
| 523 | #endif |
| 524 | reg = io_apic_read(apic, 0x10 + pin*2); |
| 525 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; |
| 526 | reg |= vector; |
| 527 | io_apic_modify(apic, 0x10 + pin*2, reg); |
| 528 | if (!entry->next) |
| 529 | break; |
| 530 | entry = entry->next; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | static int assign_irq_vector(int irq, cpumask_t mask); |
| 535 | |
| 536 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
| 537 | { |
| 538 | struct irq_cfg *cfg; |
| 539 | unsigned long flags; |
| 540 | unsigned int dest; |
| 541 | cpumask_t tmp; |
| 542 | struct irq_desc *desc; |
| 543 | |
| 544 | cpus_and(tmp, mask, cpu_online_map); |
| 545 | if (cpus_empty(tmp)) |
| 546 | return; |
| 547 | |
| 548 | cfg = irq_cfg(irq); |
| 549 | if (assign_irq_vector(irq, mask)) |
| 550 | return; |
| 551 | |
| 552 | cpus_and(tmp, cfg->domain, mask); |
| 553 | dest = cpu_mask_to_apicid(tmp); |
| 554 | /* |
| 555 | * Only the high 8 bits are valid. |
| 556 | */ |
| 557 | dest = SET_APIC_LOGICAL_ID(dest); |
| 558 | |
| 559 | desc = irq_to_desc(irq); |
| 560 | spin_lock_irqsave(&ioapic_lock, flags); |
| 561 | __target_IO_APIC_irq(irq, dest, cfg->vector); |
| 562 | desc->affinity = mask; |
| 563 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 564 | } |
| 565 | #endif /* CONFIG_SMP */ |
| 566 | |
| 567 | /* |
| 568 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are |
| 569 | * shared ISA-space IRQs, so we have to support them. We are super |
| 570 | * fast in the common case, and fast for shared ISA-space IRQs. |
| 571 | */ |
| 572 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) |
| 573 | { |
| 574 | struct irq_cfg *cfg; |
| 575 | struct irq_pin_list *entry; |
| 576 | |
| 577 | /* first time to refer irq_cfg, so with new */ |
| 578 | cfg = irq_cfg_alloc(irq); |
| 579 | entry = cfg->irq_2_pin; |
| 580 | if (!entry) { |
| 581 | entry = get_one_free_irq_2_pin(); |
| 582 | cfg->irq_2_pin = entry; |
| 583 | entry->apic = apic; |
| 584 | entry->pin = pin; |
| 585 | return; |
| 586 | } |
| 587 | |
| 588 | while (entry->next) { |
| 589 | /* not again, please */ |
| 590 | if (entry->apic == apic && entry->pin == pin) |
| 591 | return; |
| 592 | |
| 593 | entry = entry->next; |
| 594 | } |
| 595 | |
| 596 | entry->next = get_one_free_irq_2_pin(); |
| 597 | entry = entry->next; |
| 598 | entry->apic = apic; |
| 599 | entry->pin = pin; |
| 600 | } |
| 601 | |
| 602 | /* |
| 603 | * Reroute an IRQ to a different pin. |
| 604 | */ |
| 605 | static void __init replace_pin_at_irq(unsigned int irq, |
| 606 | int oldapic, int oldpin, |
| 607 | int newapic, int newpin) |
| 608 | { |
| 609 | struct irq_cfg *cfg = irq_cfg(irq); |
| 610 | struct irq_pin_list *entry = cfg->irq_2_pin; |
| 611 | int replaced = 0; |
| 612 | |
| 613 | while (entry) { |
| 614 | if (entry->apic == oldapic && entry->pin == oldpin) { |
| 615 | entry->apic = newapic; |
| 616 | entry->pin = newpin; |
| 617 | replaced = 1; |
| 618 | /* every one is different, right? */ |
| 619 | break; |
| 620 | } |
| 621 | entry = entry->next; |
| 622 | } |
| 623 | |
| 624 | /* why? call replace before add? */ |
| 625 | if (!replaced) |
| 626 | add_pin_to_irq(irq, newapic, newpin); |
| 627 | } |
| 628 | |
| 629 | static inline void io_apic_modify_irq(unsigned int irq, |
| 630 | int mask_and, int mask_or, |
| 631 | void (*final)(struct irq_pin_list *entry)) |
| 632 | { |
| 633 | int pin; |
| 634 | struct irq_cfg *cfg; |
| 635 | struct irq_pin_list *entry; |
| 636 | |
| 637 | cfg = irq_cfg(irq); |
| 638 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
| 639 | unsigned int reg; |
| 640 | pin = entry->pin; |
| 641 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); |
| 642 | reg &= mask_and; |
| 643 | reg |= mask_or; |
| 644 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); |
| 645 | if (final) |
| 646 | final(entry); |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | static void __unmask_IO_APIC_irq(unsigned int irq) |
| 651 | { |
| 652 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL); |
| 653 | } |
| 654 | |
| 655 | #ifdef CONFIG_X86_64 |
| 656 | void io_apic_sync(struct irq_pin_list *entry) |
| 657 | { |
| 658 | /* |
| 659 | * Synchronize the IO-APIC and the CPU by doing |
| 660 | * a dummy read from the IO-APIC |
| 661 | */ |
| 662 | struct io_apic __iomem *io_apic; |
| 663 | io_apic = io_apic_base(entry->apic); |
| 664 | readl(&io_apic->data); |
| 665 | } |
| 666 | |
| 667 | static void __mask_IO_APIC_irq(unsigned int irq) |
| 668 | { |
| 669 | io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
| 670 | } |
| 671 | #else /* CONFIG_X86_32 */ |
| 672 | static void __mask_IO_APIC_irq(unsigned int irq) |
| 673 | { |
| 674 | io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL); |
| 675 | } |
| 676 | |
| 677 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
| 678 | { |
| 679 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
| 680 | IO_APIC_REDIR_MASKED, NULL); |
| 681 | } |
| 682 | |
| 683 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
| 684 | { |
| 685 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, |
| 686 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
| 687 | } |
| 688 | #endif /* CONFIG_X86_32 */ |
| 689 | |
| 690 | static void mask_IO_APIC_irq (unsigned int irq) |
| 691 | { |
| 692 | unsigned long flags; |
| 693 | |
| 694 | spin_lock_irqsave(&ioapic_lock, flags); |
| 695 | __mask_IO_APIC_irq(irq); |
| 696 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 697 | } |
| 698 | |
| 699 | static void unmask_IO_APIC_irq (unsigned int irq) |
| 700 | { |
| 701 | unsigned long flags; |
| 702 | |
| 703 | spin_lock_irqsave(&ioapic_lock, flags); |
| 704 | __unmask_IO_APIC_irq(irq); |
| 705 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 706 | } |
| 707 | |
| 708 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
| 709 | { |
| 710 | struct IO_APIC_route_entry entry; |
| 711 | |
| 712 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
| 713 | entry = ioapic_read_entry(apic, pin); |
| 714 | if (entry.delivery_mode == dest_SMI) |
| 715 | return; |
| 716 | /* |
| 717 | * Disable it in the IO-APIC irq-routing table: |
| 718 | */ |
| 719 | ioapic_mask_entry(apic, pin); |
| 720 | } |
| 721 | |
| 722 | static void clear_IO_APIC (void) |
| 723 | { |
| 724 | int apic, pin; |
| 725 | |
| 726 | for (apic = 0; apic < nr_ioapics; apic++) |
| 727 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
| 728 | clear_IO_APIC_pin(apic, pin); |
| 729 | } |
| 730 | |
| 731 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
| 732 | void send_IPI_self(int vector) |
| 733 | { |
| 734 | unsigned int cfg; |
| 735 | |
| 736 | /* |
| 737 | * Wait for idle. |
| 738 | */ |
| 739 | apic_wait_icr_idle(); |
| 740 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; |
| 741 | /* |
| 742 | * Send the IPI. The write to APIC_ICR fires this off. |
| 743 | */ |
| 744 | apic_write(APIC_ICR, cfg); |
| 745 | } |
| 746 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
| 747 | |
| 748 | #ifdef CONFIG_X86_32 |
| 749 | /* |
| 750 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to |
| 751 | * specific CPU-side IRQs. |
| 752 | */ |
| 753 | |
| 754 | #define MAX_PIRQS 8 |
| 755 | static int pirq_entries [MAX_PIRQS]; |
| 756 | static int pirqs_enabled; |
| 757 | |
| 758 | static int __init ioapic_pirq_setup(char *str) |
| 759 | { |
| 760 | int i, max; |
| 761 | int ints[MAX_PIRQS+1]; |
| 762 | |
| 763 | get_options(str, ARRAY_SIZE(ints), ints); |
| 764 | |
| 765 | for (i = 0; i < MAX_PIRQS; i++) |
| 766 | pirq_entries[i] = -1; |
| 767 | |
| 768 | pirqs_enabled = 1; |
| 769 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 770 | "PIRQ redirection, working around broken MP-BIOS.\n"); |
| 771 | max = MAX_PIRQS; |
| 772 | if (ints[0] < MAX_PIRQS) |
| 773 | max = ints[0]; |
| 774 | |
| 775 | for (i = 0; i < max; i++) { |
| 776 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 777 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); |
| 778 | /* |
| 779 | * PIRQs are mapped upside down, usually. |
| 780 | */ |
| 781 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; |
| 782 | } |
| 783 | return 1; |
| 784 | } |
| 785 | |
| 786 | __setup("pirq=", ioapic_pirq_setup); |
| 787 | #endif /* CONFIG_X86_32 */ |
| 788 | |
| 789 | #ifdef CONFIG_INTR_REMAP |
| 790 | /* I/O APIC RTE contents at the OS boot up */ |
| 791 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; |
| 792 | |
| 793 | /* |
| 794 | * Saves and masks all the unmasked IO-APIC RTE's |
| 795 | */ |
| 796 | int save_mask_IO_APIC_setup(void) |
| 797 | { |
| 798 | union IO_APIC_reg_01 reg_01; |
| 799 | unsigned long flags; |
| 800 | int apic, pin; |
| 801 | |
| 802 | /* |
| 803 | * The number of IO-APIC IRQ registers (== #pins): |
| 804 | */ |
| 805 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 806 | spin_lock_irqsave(&ioapic_lock, flags); |
| 807 | reg_01.raw = io_apic_read(apic, 1); |
| 808 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 809 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
| 810 | } |
| 811 | |
| 812 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 813 | early_ioapic_entries[apic] = |
| 814 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
| 815 | nr_ioapic_registers[apic], GFP_KERNEL); |
| 816 | if (!early_ioapic_entries[apic]) |
| 817 | goto nomem; |
| 818 | } |
| 819 | |
| 820 | for (apic = 0; apic < nr_ioapics; apic++) |
| 821 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 822 | struct IO_APIC_route_entry entry; |
| 823 | |
| 824 | entry = early_ioapic_entries[apic][pin] = |
| 825 | ioapic_read_entry(apic, pin); |
| 826 | if (!entry.mask) { |
| 827 | entry.mask = 1; |
| 828 | ioapic_write_entry(apic, pin, entry); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | return 0; |
| 833 | |
| 834 | nomem: |
| 835 | while (apic >= 0) |
| 836 | kfree(early_ioapic_entries[apic--]); |
| 837 | memset(early_ioapic_entries, 0, |
| 838 | ARRAY_SIZE(early_ioapic_entries)); |
| 839 | |
| 840 | return -ENOMEM; |
| 841 | } |
| 842 | |
| 843 | void restore_IO_APIC_setup(void) |
| 844 | { |
| 845 | int apic, pin; |
| 846 | |
| 847 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 848 | if (!early_ioapic_entries[apic]) |
| 849 | break; |
| 850 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
| 851 | ioapic_write_entry(apic, pin, |
| 852 | early_ioapic_entries[apic][pin]); |
| 853 | kfree(early_ioapic_entries[apic]); |
| 854 | early_ioapic_entries[apic] = NULL; |
| 855 | } |
| 856 | } |
| 857 | |
| 858 | void reinit_intr_remapped_IO_APIC(int intr_remapping) |
| 859 | { |
| 860 | /* |
| 861 | * for now plain restore of previous settings. |
| 862 | * TBD: In the case of OS enabling interrupt-remapping, |
| 863 | * IO-APIC RTE's need to be setup to point to interrupt-remapping |
| 864 | * table entries. for now, do a plain restore, and wait for |
| 865 | * the setup_IO_APIC_irqs() to do proper initialization. |
| 866 | */ |
| 867 | restore_IO_APIC_setup(); |
| 868 | } |
| 869 | #endif |
| 870 | |
| 871 | /* |
| 872 | * Find the IRQ entry number of a certain pin. |
| 873 | */ |
| 874 | static int find_irq_entry(int apic, int pin, int type) |
| 875 | { |
| 876 | int i; |
| 877 | |
| 878 | for (i = 0; i < mp_irq_entries; i++) |
| 879 | if (mp_irqs[i].mp_irqtype == type && |
| 880 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || |
| 881 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && |
| 882 | mp_irqs[i].mp_dstirq == pin) |
| 883 | return i; |
| 884 | |
| 885 | return -1; |
| 886 | } |
| 887 | |
| 888 | /* |
| 889 | * Find the pin to which IRQ[irq] (ISA) is connected |
| 890 | */ |
| 891 | static int __init find_isa_irq_pin(int irq, int type) |
| 892 | { |
| 893 | int i; |
| 894 | |
| 895 | for (i = 0; i < mp_irq_entries; i++) { |
| 896 | int lbus = mp_irqs[i].mp_srcbus; |
| 897 | |
| 898 | if (test_bit(lbus, mp_bus_not_pci) && |
| 899 | (mp_irqs[i].mp_irqtype == type) && |
| 900 | (mp_irqs[i].mp_srcbusirq == irq)) |
| 901 | |
| 902 | return mp_irqs[i].mp_dstirq; |
| 903 | } |
| 904 | return -1; |
| 905 | } |
| 906 | |
| 907 | static int __init find_isa_irq_apic(int irq, int type) |
| 908 | { |
| 909 | int i; |
| 910 | |
| 911 | for (i = 0; i < mp_irq_entries; i++) { |
| 912 | int lbus = mp_irqs[i].mp_srcbus; |
| 913 | |
| 914 | if (test_bit(lbus, mp_bus_not_pci) && |
| 915 | (mp_irqs[i].mp_irqtype == type) && |
| 916 | (mp_irqs[i].mp_srcbusirq == irq)) |
| 917 | break; |
| 918 | } |
| 919 | if (i < mp_irq_entries) { |
| 920 | int apic; |
| 921 | for(apic = 0; apic < nr_ioapics; apic++) { |
| 922 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
| 923 | return apic; |
| 924 | } |
| 925 | } |
| 926 | |
| 927 | return -1; |
| 928 | } |
| 929 | |
| 930 | /* |
| 931 | * Find a specific PCI IRQ entry. |
| 932 | * Not an __init, possibly needed by modules |
| 933 | */ |
| 934 | static int pin_2_irq(int idx, int apic, int pin); |
| 935 | |
| 936 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
| 937 | { |
| 938 | int apic, i, best_guess = -1; |
| 939 | |
| 940 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
| 941 | bus, slot, pin); |
| 942 | if (test_bit(bus, mp_bus_not_pci)) { |
| 943 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
| 944 | return -1; |
| 945 | } |
| 946 | for (i = 0; i < mp_irq_entries; i++) { |
| 947 | int lbus = mp_irqs[i].mp_srcbus; |
| 948 | |
| 949 | for (apic = 0; apic < nr_ioapics; apic++) |
| 950 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
| 951 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) |
| 952 | break; |
| 953 | |
| 954 | if (!test_bit(lbus, mp_bus_not_pci) && |
| 955 | !mp_irqs[i].mp_irqtype && |
| 956 | (bus == lbus) && |
| 957 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
| 958 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
| 959 | |
| 960 | if (!(apic || IO_APIC_IRQ(irq))) |
| 961 | continue; |
| 962 | |
| 963 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
| 964 | return irq; |
| 965 | /* |
| 966 | * Use the first all-but-pin matching entry as a |
| 967 | * best-guess fuzzy result for broken mptables. |
| 968 | */ |
| 969 | if (best_guess < 0) |
| 970 | best_guess = irq; |
| 971 | } |
| 972 | } |
| 973 | return best_guess; |
| 974 | } |
| 975 | |
| 976 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
| 977 | |
| 978 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
| 979 | /* |
| 980 | * EISA Edge/Level control register, ELCR |
| 981 | */ |
| 982 | static int EISA_ELCR(unsigned int irq) |
| 983 | { |
| 984 | if (irq < 16) { |
| 985 | unsigned int port = 0x4d0 + (irq >> 3); |
| 986 | return (inb(port) >> (irq & 7)) & 1; |
| 987 | } |
| 988 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 989 | "Broken MPtable reports ISA irq %d\n", irq); |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | #endif |
| 994 | |
| 995 | /* ISA interrupts are always polarity zero edge triggered, |
| 996 | * when listed as conforming in the MP table. */ |
| 997 | |
| 998 | #define default_ISA_trigger(idx) (0) |
| 999 | #define default_ISA_polarity(idx) (0) |
| 1000 | |
| 1001 | /* EISA interrupts are always polarity zero and can be edge or level |
| 1002 | * trigger depending on the ELCR value. If an interrupt is listed as |
| 1003 | * EISA conforming in the MP table, that means its trigger type must |
| 1004 | * be read in from the ELCR */ |
| 1005 | |
| 1006 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
| 1007 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
| 1008 | |
| 1009 | /* PCI interrupts are always polarity one level triggered, |
| 1010 | * when listed as conforming in the MP table. */ |
| 1011 | |
| 1012 | #define default_PCI_trigger(idx) (1) |
| 1013 | #define default_PCI_polarity(idx) (1) |
| 1014 | |
| 1015 | /* MCA interrupts are always polarity zero level triggered, |
| 1016 | * when listed as conforming in the MP table. */ |
| 1017 | |
| 1018 | #define default_MCA_trigger(idx) (1) |
| 1019 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
| 1020 | |
| 1021 | static int MPBIOS_polarity(int idx) |
| 1022 | { |
| 1023 | int bus = mp_irqs[idx].mp_srcbus; |
| 1024 | int polarity; |
| 1025 | |
| 1026 | /* |
| 1027 | * Determine IRQ line polarity (high active or low active): |
| 1028 | */ |
| 1029 | switch (mp_irqs[idx].mp_irqflag & 3) |
| 1030 | { |
| 1031 | case 0: /* conforms, ie. bus-type dependent polarity */ |
| 1032 | if (test_bit(bus, mp_bus_not_pci)) |
| 1033 | polarity = default_ISA_polarity(idx); |
| 1034 | else |
| 1035 | polarity = default_PCI_polarity(idx); |
| 1036 | break; |
| 1037 | case 1: /* high active */ |
| 1038 | { |
| 1039 | polarity = 0; |
| 1040 | break; |
| 1041 | } |
| 1042 | case 2: /* reserved */ |
| 1043 | { |
| 1044 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 1045 | polarity = 1; |
| 1046 | break; |
| 1047 | } |
| 1048 | case 3: /* low active */ |
| 1049 | { |
| 1050 | polarity = 1; |
| 1051 | break; |
| 1052 | } |
| 1053 | default: /* invalid */ |
| 1054 | { |
| 1055 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 1056 | polarity = 1; |
| 1057 | break; |
| 1058 | } |
| 1059 | } |
| 1060 | return polarity; |
| 1061 | } |
| 1062 | |
| 1063 | static int MPBIOS_trigger(int idx) |
| 1064 | { |
| 1065 | int bus = mp_irqs[idx].mp_srcbus; |
| 1066 | int trigger; |
| 1067 | |
| 1068 | /* |
| 1069 | * Determine IRQ trigger mode (edge or level sensitive): |
| 1070 | */ |
| 1071 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
| 1072 | { |
| 1073 | case 0: /* conforms, ie. bus-type dependent */ |
| 1074 | if (test_bit(bus, mp_bus_not_pci)) |
| 1075 | trigger = default_ISA_trigger(idx); |
| 1076 | else |
| 1077 | trigger = default_PCI_trigger(idx); |
| 1078 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
| 1079 | switch (mp_bus_id_to_type[bus]) { |
| 1080 | case MP_BUS_ISA: /* ISA pin */ |
| 1081 | { |
| 1082 | /* set before the switch */ |
| 1083 | break; |
| 1084 | } |
| 1085 | case MP_BUS_EISA: /* EISA pin */ |
| 1086 | { |
| 1087 | trigger = default_EISA_trigger(idx); |
| 1088 | break; |
| 1089 | } |
| 1090 | case MP_BUS_PCI: /* PCI pin */ |
| 1091 | { |
| 1092 | /* set before the switch */ |
| 1093 | break; |
| 1094 | } |
| 1095 | case MP_BUS_MCA: /* MCA pin */ |
| 1096 | { |
| 1097 | trigger = default_MCA_trigger(idx); |
| 1098 | break; |
| 1099 | } |
| 1100 | default: |
| 1101 | { |
| 1102 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 1103 | trigger = 1; |
| 1104 | break; |
| 1105 | } |
| 1106 | } |
| 1107 | #endif |
| 1108 | break; |
| 1109 | case 1: /* edge */ |
| 1110 | { |
| 1111 | trigger = 0; |
| 1112 | break; |
| 1113 | } |
| 1114 | case 2: /* reserved */ |
| 1115 | { |
| 1116 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 1117 | trigger = 1; |
| 1118 | break; |
| 1119 | } |
| 1120 | case 3: /* level */ |
| 1121 | { |
| 1122 | trigger = 1; |
| 1123 | break; |
| 1124 | } |
| 1125 | default: /* invalid */ |
| 1126 | { |
| 1127 | printk(KERN_WARNING "broken BIOS!!\n"); |
| 1128 | trigger = 0; |
| 1129 | break; |
| 1130 | } |
| 1131 | } |
| 1132 | return trigger; |
| 1133 | } |
| 1134 | |
| 1135 | static inline int irq_polarity(int idx) |
| 1136 | { |
| 1137 | return MPBIOS_polarity(idx); |
| 1138 | } |
| 1139 | |
| 1140 | static inline int irq_trigger(int idx) |
| 1141 | { |
| 1142 | return MPBIOS_trigger(idx); |
| 1143 | } |
| 1144 | |
| 1145 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
| 1146 | static int pin_2_irq(int idx, int apic, int pin) |
| 1147 | { |
| 1148 | int irq, i; |
| 1149 | int bus = mp_irqs[idx].mp_srcbus; |
| 1150 | |
| 1151 | /* |
| 1152 | * Debugging check, we are in big trouble if this message pops up! |
| 1153 | */ |
| 1154 | if (mp_irqs[idx].mp_dstirq != pin) |
| 1155 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
| 1156 | |
| 1157 | if (test_bit(bus, mp_bus_not_pci)) { |
| 1158 | irq = mp_irqs[idx].mp_srcbusirq; |
| 1159 | } else { |
| 1160 | /* |
| 1161 | * PCI IRQs are mapped in order |
| 1162 | */ |
| 1163 | i = irq = 0; |
| 1164 | while (i < apic) |
| 1165 | irq += nr_ioapic_registers[i++]; |
| 1166 | irq += pin; |
| 1167 | /* |
| 1168 | * For MPS mode, so far only needed by ES7000 platform |
| 1169 | */ |
| 1170 | if (ioapic_renumber_irq) |
| 1171 | irq = ioapic_renumber_irq(apic, irq); |
| 1172 | } |
| 1173 | |
| 1174 | #ifdef CONFIG_X86_32 |
| 1175 | /* |
| 1176 | * PCI IRQ command line redirection. Yes, limits are hardcoded. |
| 1177 | */ |
| 1178 | if ((pin >= 16) && (pin <= 23)) { |
| 1179 | if (pirq_entries[pin-16] != -1) { |
| 1180 | if (!pirq_entries[pin-16]) { |
| 1181 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 1182 | "disabling PIRQ%d\n", pin-16); |
| 1183 | } else { |
| 1184 | irq = pirq_entries[pin-16]; |
| 1185 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 1186 | "using PIRQ%d -> IRQ %d\n", |
| 1187 | pin-16, irq); |
| 1188 | } |
| 1189 | } |
| 1190 | } |
| 1191 | #endif |
| 1192 | |
| 1193 | return irq; |
| 1194 | } |
| 1195 | |
| 1196 | void lock_vector_lock(void) |
| 1197 | { |
| 1198 | /* Used to the online set of cpus does not change |
| 1199 | * during assign_irq_vector. |
| 1200 | */ |
| 1201 | spin_lock(&vector_lock); |
| 1202 | } |
| 1203 | |
| 1204 | void unlock_vector_lock(void) |
| 1205 | { |
| 1206 | spin_unlock(&vector_lock); |
| 1207 | } |
| 1208 | |
| 1209 | static int __assign_irq_vector(int irq, cpumask_t mask) |
| 1210 | { |
| 1211 | /* |
| 1212 | * NOTE! The local APIC isn't very good at handling |
| 1213 | * multiple interrupts at the same interrupt level. |
| 1214 | * As the interrupt level is determined by taking the |
| 1215 | * vector number and shifting that right by 4, we |
| 1216 | * want to spread these out a bit so that they don't |
| 1217 | * all fall in the same interrupt level. |
| 1218 | * |
| 1219 | * Also, we've got to be careful not to trash gate |
| 1220 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
| 1221 | */ |
| 1222 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
| 1223 | unsigned int old_vector; |
| 1224 | int cpu; |
| 1225 | struct irq_cfg *cfg; |
| 1226 | |
| 1227 | cfg = irq_cfg(irq); |
| 1228 | |
| 1229 | /* Only try and allocate irqs on cpus that are present */ |
| 1230 | cpus_and(mask, mask, cpu_online_map); |
| 1231 | |
| 1232 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
| 1233 | return -EBUSY; |
| 1234 | |
| 1235 | old_vector = cfg->vector; |
| 1236 | if (old_vector) { |
| 1237 | cpumask_t tmp; |
| 1238 | cpus_and(tmp, cfg->domain, mask); |
| 1239 | if (!cpus_empty(tmp)) |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
| 1243 | for_each_cpu_mask_nr(cpu, mask) { |
| 1244 | cpumask_t domain, new_mask; |
| 1245 | int new_cpu; |
| 1246 | int vector, offset; |
| 1247 | |
| 1248 | domain = vector_allocation_domain(cpu); |
| 1249 | cpus_and(new_mask, domain, cpu_online_map); |
| 1250 | |
| 1251 | vector = current_vector; |
| 1252 | offset = current_offset; |
| 1253 | next: |
| 1254 | vector += 8; |
| 1255 | if (vector >= first_system_vector) { |
| 1256 | /* If we run out of vectors on large boxen, must share them. */ |
| 1257 | offset = (offset + 1) % 8; |
| 1258 | vector = FIRST_DEVICE_VECTOR + offset; |
| 1259 | } |
| 1260 | if (unlikely(current_vector == vector)) |
| 1261 | continue; |
| 1262 | #ifdef CONFIG_X86_64 |
| 1263 | if (vector == IA32_SYSCALL_VECTOR) |
| 1264 | goto next; |
| 1265 | #else |
| 1266 | if (vector == SYSCALL_VECTOR) |
| 1267 | goto next; |
| 1268 | #endif |
| 1269 | for_each_cpu_mask_nr(new_cpu, new_mask) |
| 1270 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
| 1271 | goto next; |
| 1272 | /* Found one! */ |
| 1273 | current_vector = vector; |
| 1274 | current_offset = offset; |
| 1275 | if (old_vector) { |
| 1276 | cfg->move_in_progress = 1; |
| 1277 | cfg->old_domain = cfg->domain; |
| 1278 | } |
| 1279 | for_each_cpu_mask_nr(new_cpu, new_mask) |
| 1280 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
| 1281 | cfg->vector = vector; |
| 1282 | cfg->domain = domain; |
| 1283 | return 0; |
| 1284 | } |
| 1285 | return -ENOSPC; |
| 1286 | } |
| 1287 | |
| 1288 | static int assign_irq_vector(int irq, cpumask_t mask) |
| 1289 | { |
| 1290 | int err; |
| 1291 | unsigned long flags; |
| 1292 | |
| 1293 | spin_lock_irqsave(&vector_lock, flags); |
| 1294 | err = __assign_irq_vector(irq, mask); |
| 1295 | spin_unlock_irqrestore(&vector_lock, flags); |
| 1296 | return err; |
| 1297 | } |
| 1298 | |
| 1299 | static void __clear_irq_vector(int irq) |
| 1300 | { |
| 1301 | struct irq_cfg *cfg; |
| 1302 | cpumask_t mask; |
| 1303 | int cpu, vector; |
| 1304 | |
| 1305 | cfg = irq_cfg(irq); |
| 1306 | BUG_ON(!cfg->vector); |
| 1307 | |
| 1308 | vector = cfg->vector; |
| 1309 | cpus_and(mask, cfg->domain, cpu_online_map); |
| 1310 | for_each_cpu_mask_nr(cpu, mask) |
| 1311 | per_cpu(vector_irq, cpu)[vector] = -1; |
| 1312 | |
| 1313 | cfg->vector = 0; |
| 1314 | cpus_clear(cfg->domain); |
| 1315 | } |
| 1316 | |
| 1317 | void __setup_vector_irq(int cpu) |
| 1318 | { |
| 1319 | /* Initialize vector_irq on a new cpu */ |
| 1320 | /* This function must be called with vector_lock held */ |
| 1321 | int irq, vector; |
| 1322 | struct irq_cfg *cfg; |
| 1323 | |
| 1324 | /* Mark the inuse vectors */ |
| 1325 | for_each_irq_cfg(irq, cfg) { |
| 1326 | if (!cpu_isset(cpu, cfg->domain)) |
| 1327 | continue; |
| 1328 | vector = cfg->vector; |
| 1329 | per_cpu(vector_irq, cpu)[vector] = irq; |
| 1330 | } |
| 1331 | /* Mark the free vectors */ |
| 1332 | for (vector = 0; vector < NR_VECTORS; ++vector) { |
| 1333 | irq = per_cpu(vector_irq, cpu)[vector]; |
| 1334 | if (irq < 0) |
| 1335 | continue; |
| 1336 | |
| 1337 | cfg = irq_cfg(irq); |
| 1338 | if (!cpu_isset(cpu, cfg->domain)) |
| 1339 | per_cpu(vector_irq, cpu)[vector] = -1; |
| 1340 | } |
| 1341 | } |
| 1342 | |
| 1343 | static struct irq_chip ioapic_chip; |
| 1344 | #ifdef CONFIG_INTR_REMAP |
| 1345 | static struct irq_chip ir_ioapic_chip; |
| 1346 | #endif |
| 1347 | |
| 1348 | #define IOAPIC_AUTO -1 |
| 1349 | #define IOAPIC_EDGE 0 |
| 1350 | #define IOAPIC_LEVEL 1 |
| 1351 | |
| 1352 | #ifdef CONFIG_X86_32 |
| 1353 | static inline int IO_APIC_irq_trigger(int irq) |
| 1354 | { |
| 1355 | int apic, idx, pin; |
| 1356 | |
| 1357 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1358 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 1359 | idx = find_irq_entry(apic, pin, mp_INT); |
| 1360 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) |
| 1361 | return irq_trigger(idx); |
| 1362 | } |
| 1363 | } |
| 1364 | /* |
| 1365 | * nonexistent IRQs are edge default |
| 1366 | */ |
| 1367 | return 0; |
| 1368 | } |
| 1369 | #else |
| 1370 | static inline int IO_APIC_irq_trigger(int irq) |
| 1371 | { |
| 1372 | return 1; |
| 1373 | } |
| 1374 | #endif |
| 1375 | |
| 1376 | static void ioapic_register_intr(int irq, unsigned long trigger) |
| 1377 | { |
| 1378 | struct irq_desc *desc; |
| 1379 | |
| 1380 | /* first time to use this irq_desc */ |
| 1381 | if (irq < 16) |
| 1382 | desc = irq_to_desc(irq); |
| 1383 | else |
| 1384 | desc = irq_to_desc_alloc(irq); |
| 1385 | |
| 1386 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
| 1387 | trigger == IOAPIC_LEVEL) |
| 1388 | desc->status |= IRQ_LEVEL; |
| 1389 | else |
| 1390 | desc->status &= ~IRQ_LEVEL; |
| 1391 | |
| 1392 | #ifdef CONFIG_INTR_REMAP |
| 1393 | if (irq_remapped(irq)) { |
| 1394 | desc->status |= IRQ_MOVE_PCNTXT; |
| 1395 | if (trigger) |
| 1396 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, |
| 1397 | handle_fasteoi_irq, |
| 1398 | "fasteoi"); |
| 1399 | else |
| 1400 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, |
| 1401 | handle_edge_irq, "edge"); |
| 1402 | return; |
| 1403 | } |
| 1404 | #endif |
| 1405 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
| 1406 | trigger == IOAPIC_LEVEL) |
| 1407 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
| 1408 | handle_fasteoi_irq, |
| 1409 | "fasteoi"); |
| 1410 | else |
| 1411 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
| 1412 | handle_edge_irq, "edge"); |
| 1413 | } |
| 1414 | |
| 1415 | static int setup_ioapic_entry(int apic, int irq, |
| 1416 | struct IO_APIC_route_entry *entry, |
| 1417 | unsigned int destination, int trigger, |
| 1418 | int polarity, int vector) |
| 1419 | { |
| 1420 | /* |
| 1421 | * add it to the IO-APIC irq-routing table: |
| 1422 | */ |
| 1423 | memset(entry,0,sizeof(*entry)); |
| 1424 | |
| 1425 | #ifdef CONFIG_INTR_REMAP |
| 1426 | if (intr_remapping_enabled) { |
| 1427 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); |
| 1428 | struct irte irte; |
| 1429 | struct IR_IO_APIC_route_entry *ir_entry = |
| 1430 | (struct IR_IO_APIC_route_entry *) entry; |
| 1431 | int index; |
| 1432 | |
| 1433 | if (!iommu) |
| 1434 | panic("No mapping iommu for ioapic %d\n", apic); |
| 1435 | |
| 1436 | index = alloc_irte(iommu, irq, 1); |
| 1437 | if (index < 0) |
| 1438 | panic("Failed to allocate IRTE for ioapic %d\n", apic); |
| 1439 | |
| 1440 | memset(&irte, 0, sizeof(irte)); |
| 1441 | |
| 1442 | irte.present = 1; |
| 1443 | irte.dst_mode = INT_DEST_MODE; |
| 1444 | irte.trigger_mode = trigger; |
| 1445 | irte.dlvry_mode = INT_DELIVERY_MODE; |
| 1446 | irte.vector = vector; |
| 1447 | irte.dest_id = IRTE_DEST(destination); |
| 1448 | |
| 1449 | modify_irte(irq, &irte); |
| 1450 | |
| 1451 | ir_entry->index2 = (index >> 15) & 0x1; |
| 1452 | ir_entry->zero = 0; |
| 1453 | ir_entry->format = 1; |
| 1454 | ir_entry->index = (index & 0x7fff); |
| 1455 | } else |
| 1456 | #endif |
| 1457 | { |
| 1458 | entry->delivery_mode = INT_DELIVERY_MODE; |
| 1459 | entry->dest_mode = INT_DEST_MODE; |
| 1460 | entry->dest = destination; |
| 1461 | } |
| 1462 | |
| 1463 | entry->mask = 0; /* enable IRQ */ |
| 1464 | entry->trigger = trigger; |
| 1465 | entry->polarity = polarity; |
| 1466 | entry->vector = vector; |
| 1467 | |
| 1468 | /* Mask level triggered irqs. |
| 1469 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
| 1470 | */ |
| 1471 | if (trigger) |
| 1472 | entry->mask = 1; |
| 1473 | return 0; |
| 1474 | } |
| 1475 | |
| 1476 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, |
| 1477 | int trigger, int polarity) |
| 1478 | { |
| 1479 | struct irq_cfg *cfg; |
| 1480 | struct IO_APIC_route_entry entry; |
| 1481 | cpumask_t mask; |
| 1482 | |
| 1483 | if (!IO_APIC_IRQ(irq)) |
| 1484 | return; |
| 1485 | |
| 1486 | cfg = irq_cfg(irq); |
| 1487 | |
| 1488 | mask = TARGET_CPUS; |
| 1489 | if (assign_irq_vector(irq, mask)) |
| 1490 | return; |
| 1491 | |
| 1492 | cpus_and(mask, cfg->domain, mask); |
| 1493 | |
| 1494 | apic_printk(APIC_VERBOSE,KERN_DEBUG |
| 1495 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " |
| 1496 | "IRQ %d Mode:%i Active:%i)\n", |
| 1497 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, |
| 1498 | irq, trigger, polarity); |
| 1499 | |
| 1500 | |
| 1501 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, |
| 1502 | cpu_mask_to_apicid(mask), trigger, polarity, |
| 1503 | cfg->vector)) { |
| 1504 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
| 1505 | mp_ioapics[apic].mp_apicid, pin); |
| 1506 | __clear_irq_vector(irq); |
| 1507 | return; |
| 1508 | } |
| 1509 | |
| 1510 | ioapic_register_intr(irq, trigger); |
| 1511 | if (irq < 16) |
| 1512 | disable_8259A_irq(irq); |
| 1513 | |
| 1514 | ioapic_write_entry(apic, pin, entry); |
| 1515 | } |
| 1516 | |
| 1517 | static void __init setup_IO_APIC_irqs(void) |
| 1518 | { |
| 1519 | int apic, pin, idx, irq; |
| 1520 | int notcon = 0; |
| 1521 | |
| 1522 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); |
| 1523 | |
| 1524 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1525 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 1526 | |
| 1527 | idx = find_irq_entry(apic, pin, mp_INT); |
| 1528 | if (idx == -1) { |
| 1529 | if (!notcon) { |
| 1530 | notcon = 1; |
| 1531 | apic_printk(APIC_VERBOSE, |
| 1532 | KERN_DEBUG " %d-%d", |
| 1533 | mp_ioapics[apic].mp_apicid, |
| 1534 | pin); |
| 1535 | } else |
| 1536 | apic_printk(APIC_VERBOSE, " %d-%d", |
| 1537 | mp_ioapics[apic].mp_apicid, |
| 1538 | pin); |
| 1539 | continue; |
| 1540 | } |
| 1541 | if (notcon) { |
| 1542 | apic_printk(APIC_VERBOSE, |
| 1543 | " (apicid-pin) not connected\n"); |
| 1544 | notcon = 0; |
| 1545 | } |
| 1546 | |
| 1547 | irq = pin_2_irq(idx, apic, pin); |
| 1548 | #ifdef CONFIG_X86_32 |
| 1549 | if (multi_timer_check(apic, irq)) |
| 1550 | continue; |
| 1551 | #endif |
| 1552 | add_pin_to_irq(irq, apic, pin); |
| 1553 | |
| 1554 | setup_IO_APIC_irq(apic, pin, irq, |
| 1555 | irq_trigger(idx), irq_polarity(idx)); |
| 1556 | } |
| 1557 | } |
| 1558 | |
| 1559 | if (notcon) |
| 1560 | apic_printk(APIC_VERBOSE, |
| 1561 | " (apicid-pin) not connected\n"); |
| 1562 | } |
| 1563 | |
| 1564 | /* |
| 1565 | * Set up the timer pin, possibly with the 8259A-master behind. |
| 1566 | */ |
| 1567 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
| 1568 | int vector) |
| 1569 | { |
| 1570 | struct IO_APIC_route_entry entry; |
| 1571 | |
| 1572 | #ifdef CONFIG_INTR_REMAP |
| 1573 | if (intr_remapping_enabled) |
| 1574 | return; |
| 1575 | #endif |
| 1576 | |
| 1577 | memset(&entry, 0, sizeof(entry)); |
| 1578 | |
| 1579 | /* |
| 1580 | * We use logical delivery to get the timer IRQ |
| 1581 | * to the first CPU. |
| 1582 | */ |
| 1583 | entry.dest_mode = INT_DEST_MODE; |
| 1584 | entry.mask = 1; /* mask IRQ now */ |
| 1585 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
| 1586 | entry.delivery_mode = INT_DELIVERY_MODE; |
| 1587 | entry.polarity = 0; |
| 1588 | entry.trigger = 0; |
| 1589 | entry.vector = vector; |
| 1590 | |
| 1591 | /* |
| 1592 | * The timer IRQ doesn't have to know that behind the |
| 1593 | * scene we may have a 8259A-master in AEOI mode ... |
| 1594 | */ |
| 1595 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
| 1596 | |
| 1597 | /* |
| 1598 | * Add it to the IO-APIC irq-routing table: |
| 1599 | */ |
| 1600 | ioapic_write_entry(apic, pin, entry); |
| 1601 | } |
| 1602 | |
| 1603 | |
| 1604 | __apicdebuginit(void) print_IO_APIC(void) |
| 1605 | { |
| 1606 | int apic, i; |
| 1607 | union IO_APIC_reg_00 reg_00; |
| 1608 | union IO_APIC_reg_01 reg_01; |
| 1609 | union IO_APIC_reg_02 reg_02; |
| 1610 | union IO_APIC_reg_03 reg_03; |
| 1611 | unsigned long flags; |
| 1612 | struct irq_cfg *cfg; |
| 1613 | unsigned int irq; |
| 1614 | |
| 1615 | if (apic_verbosity == APIC_QUIET) |
| 1616 | return; |
| 1617 | |
| 1618 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
| 1619 | for (i = 0; i < nr_ioapics; i++) |
| 1620 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
| 1621 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
| 1622 | |
| 1623 | /* |
| 1624 | * We are a bit conservative about what we expect. We have to |
| 1625 | * know about every hardware change ASAP. |
| 1626 | */ |
| 1627 | printk(KERN_INFO "testing the IO APIC.......................\n"); |
| 1628 | |
| 1629 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1630 | |
| 1631 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1632 | reg_00.raw = io_apic_read(apic, 0); |
| 1633 | reg_01.raw = io_apic_read(apic, 1); |
| 1634 | if (reg_01.bits.version >= 0x10) |
| 1635 | reg_02.raw = io_apic_read(apic, 2); |
| 1636 | if (reg_01.bits.version >= 0x20) |
| 1637 | reg_03.raw = io_apic_read(apic, 3); |
| 1638 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1639 | |
| 1640 | printk("\n"); |
| 1641 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
| 1642 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
| 1643 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
| 1644 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); |
| 1645 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); |
| 1646 | |
| 1647 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
| 1648 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
| 1649 | |
| 1650 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); |
| 1651 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); |
| 1652 | |
| 1653 | /* |
| 1654 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, |
| 1655 | * but the value of reg_02 is read as the previous read register |
| 1656 | * value, so ignore it if reg_02 == reg_01. |
| 1657 | */ |
| 1658 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { |
| 1659 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); |
| 1660 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); |
| 1661 | } |
| 1662 | |
| 1663 | /* |
| 1664 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 |
| 1665 | * or reg_03, but the value of reg_0[23] is read as the previous read |
| 1666 | * register value, so ignore it if reg_03 == reg_0[12]. |
| 1667 | */ |
| 1668 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && |
| 1669 | reg_03.raw != reg_01.raw) { |
| 1670 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); |
| 1671 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); |
| 1672 | } |
| 1673 | |
| 1674 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); |
| 1675 | |
| 1676 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
| 1677 | " Stat Dmod Deli Vect: \n"); |
| 1678 | |
| 1679 | for (i = 0; i <= reg_01.bits.entries; i++) { |
| 1680 | struct IO_APIC_route_entry entry; |
| 1681 | |
| 1682 | entry = ioapic_read_entry(apic, i); |
| 1683 | |
| 1684 | printk(KERN_DEBUG " %02x %03X ", |
| 1685 | i, |
| 1686 | entry.dest |
| 1687 | ); |
| 1688 | |
| 1689 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", |
| 1690 | entry.mask, |
| 1691 | entry.trigger, |
| 1692 | entry.irr, |
| 1693 | entry.polarity, |
| 1694 | entry.delivery_status, |
| 1695 | entry.dest_mode, |
| 1696 | entry.delivery_mode, |
| 1697 | entry.vector |
| 1698 | ); |
| 1699 | } |
| 1700 | } |
| 1701 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
| 1702 | for_each_irq_cfg(irq, cfg) { |
| 1703 | struct irq_pin_list *entry = cfg->irq_2_pin; |
| 1704 | if (!entry) |
| 1705 | continue; |
| 1706 | printk(KERN_DEBUG "IRQ%d ", irq); |
| 1707 | for (;;) { |
| 1708 | printk("-> %d:%d", entry->apic, entry->pin); |
| 1709 | if (!entry->next) |
| 1710 | break; |
| 1711 | entry = entry->next; |
| 1712 | } |
| 1713 | printk("\n"); |
| 1714 | } |
| 1715 | |
| 1716 | printk(KERN_INFO ".................................... done.\n"); |
| 1717 | |
| 1718 | return; |
| 1719 | } |
| 1720 | |
| 1721 | __apicdebuginit(void) print_APIC_bitfield(int base) |
| 1722 | { |
| 1723 | unsigned int v; |
| 1724 | int i, j; |
| 1725 | |
| 1726 | if (apic_verbosity == APIC_QUIET) |
| 1727 | return; |
| 1728 | |
| 1729 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); |
| 1730 | for (i = 0; i < 8; i++) { |
| 1731 | v = apic_read(base + i*0x10); |
| 1732 | for (j = 0; j < 32; j++) { |
| 1733 | if (v & (1<<j)) |
| 1734 | printk("1"); |
| 1735 | else |
| 1736 | printk("0"); |
| 1737 | } |
| 1738 | printk("\n"); |
| 1739 | } |
| 1740 | } |
| 1741 | |
| 1742 | __apicdebuginit(void) print_local_APIC(void *dummy) |
| 1743 | { |
| 1744 | unsigned int v, ver, maxlvt; |
| 1745 | u64 icr; |
| 1746 | |
| 1747 | if (apic_verbosity == APIC_QUIET) |
| 1748 | return; |
| 1749 | |
| 1750 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
| 1751 | smp_processor_id(), hard_smp_processor_id()); |
| 1752 | v = apic_read(APIC_ID); |
| 1753 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
| 1754 | v = apic_read(APIC_LVR); |
| 1755 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); |
| 1756 | ver = GET_APIC_VERSION(v); |
| 1757 | maxlvt = lapic_get_maxlvt(); |
| 1758 | |
| 1759 | v = apic_read(APIC_TASKPRI); |
| 1760 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
| 1761 | |
| 1762 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
| 1763 | if (!APIC_XAPIC(ver)) { |
| 1764 | v = apic_read(APIC_ARBPRI); |
| 1765 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, |
| 1766 | v & APIC_ARBPRI_MASK); |
| 1767 | } |
| 1768 | v = apic_read(APIC_PROCPRI); |
| 1769 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); |
| 1770 | } |
| 1771 | |
| 1772 | /* |
| 1773 | * Remote read supported only in the 82489DX and local APIC for |
| 1774 | * Pentium processors. |
| 1775 | */ |
| 1776 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { |
| 1777 | v = apic_read(APIC_RRR); |
| 1778 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); |
| 1779 | } |
| 1780 | |
| 1781 | v = apic_read(APIC_LDR); |
| 1782 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); |
| 1783 | if (!x2apic_enabled()) { |
| 1784 | v = apic_read(APIC_DFR); |
| 1785 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); |
| 1786 | } |
| 1787 | v = apic_read(APIC_SPIV); |
| 1788 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); |
| 1789 | |
| 1790 | printk(KERN_DEBUG "... APIC ISR field:\n"); |
| 1791 | print_APIC_bitfield(APIC_ISR); |
| 1792 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
| 1793 | print_APIC_bitfield(APIC_TMR); |
| 1794 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
| 1795 | print_APIC_bitfield(APIC_IRR); |
| 1796 | |
| 1797 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
| 1798 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 1799 | apic_write(APIC_ESR, 0); |
| 1800 | |
| 1801 | v = apic_read(APIC_ESR); |
| 1802 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); |
| 1803 | } |
| 1804 | |
| 1805 | icr = apic_icr_read(); |
| 1806 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
| 1807 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); |
| 1808 | |
| 1809 | v = apic_read(APIC_LVTT); |
| 1810 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); |
| 1811 | |
| 1812 | if (maxlvt > 3) { /* PC is LVT#4. */ |
| 1813 | v = apic_read(APIC_LVTPC); |
| 1814 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); |
| 1815 | } |
| 1816 | v = apic_read(APIC_LVT0); |
| 1817 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); |
| 1818 | v = apic_read(APIC_LVT1); |
| 1819 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); |
| 1820 | |
| 1821 | if (maxlvt > 2) { /* ERR is LVT#3. */ |
| 1822 | v = apic_read(APIC_LVTERR); |
| 1823 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); |
| 1824 | } |
| 1825 | |
| 1826 | v = apic_read(APIC_TMICT); |
| 1827 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); |
| 1828 | v = apic_read(APIC_TMCCT); |
| 1829 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); |
| 1830 | v = apic_read(APIC_TDCR); |
| 1831 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); |
| 1832 | printk("\n"); |
| 1833 | } |
| 1834 | |
| 1835 | __apicdebuginit(void) print_all_local_APICs(void) |
| 1836 | { |
| 1837 | int cpu; |
| 1838 | |
| 1839 | preempt_disable(); |
| 1840 | for_each_online_cpu(cpu) |
| 1841 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
| 1842 | preempt_enable(); |
| 1843 | } |
| 1844 | |
| 1845 | __apicdebuginit(void) print_PIC(void) |
| 1846 | { |
| 1847 | unsigned int v; |
| 1848 | unsigned long flags; |
| 1849 | |
| 1850 | if (apic_verbosity == APIC_QUIET) |
| 1851 | return; |
| 1852 | |
| 1853 | printk(KERN_DEBUG "\nprinting PIC contents\n"); |
| 1854 | |
| 1855 | spin_lock_irqsave(&i8259A_lock, flags); |
| 1856 | |
| 1857 | v = inb(0xa1) << 8 | inb(0x21); |
| 1858 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); |
| 1859 | |
| 1860 | v = inb(0xa0) << 8 | inb(0x20); |
| 1861 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); |
| 1862 | |
| 1863 | outb(0x0b,0xa0); |
| 1864 | outb(0x0b,0x20); |
| 1865 | v = inb(0xa0) << 8 | inb(0x20); |
| 1866 | outb(0x0a,0xa0); |
| 1867 | outb(0x0a,0x20); |
| 1868 | |
| 1869 | spin_unlock_irqrestore(&i8259A_lock, flags); |
| 1870 | |
| 1871 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); |
| 1872 | |
| 1873 | v = inb(0x4d1) << 8 | inb(0x4d0); |
| 1874 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); |
| 1875 | } |
| 1876 | |
| 1877 | __apicdebuginit(int) print_all_ICs(void) |
| 1878 | { |
| 1879 | print_PIC(); |
| 1880 | print_all_local_APICs(); |
| 1881 | print_IO_APIC(); |
| 1882 | |
| 1883 | return 0; |
| 1884 | } |
| 1885 | |
| 1886 | fs_initcall(print_all_ICs); |
| 1887 | |
| 1888 | |
| 1889 | /* Where if anywhere is the i8259 connect in external int mode */ |
| 1890 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; |
| 1891 | |
| 1892 | void __init enable_IO_APIC(void) |
| 1893 | { |
| 1894 | union IO_APIC_reg_01 reg_01; |
| 1895 | int i8259_apic, i8259_pin; |
| 1896 | int apic; |
| 1897 | unsigned long flags; |
| 1898 | |
| 1899 | #ifdef CONFIG_X86_32 |
| 1900 | int i; |
| 1901 | if (!pirqs_enabled) |
| 1902 | for (i = 0; i < MAX_PIRQS; i++) |
| 1903 | pirq_entries[i] = -1; |
| 1904 | #endif |
| 1905 | |
| 1906 | /* |
| 1907 | * The number of IO-APIC IRQ registers (== #pins): |
| 1908 | */ |
| 1909 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 1910 | spin_lock_irqsave(&ioapic_lock, flags); |
| 1911 | reg_01.raw = io_apic_read(apic, 1); |
| 1912 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 1913 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
| 1914 | } |
| 1915 | for(apic = 0; apic < nr_ioapics; apic++) { |
| 1916 | int pin; |
| 1917 | /* See if any of the pins is in ExtINT mode */ |
| 1918 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
| 1919 | struct IO_APIC_route_entry entry; |
| 1920 | entry = ioapic_read_entry(apic, pin); |
| 1921 | |
| 1922 | /* If the interrupt line is enabled and in ExtInt mode |
| 1923 | * I have found the pin where the i8259 is connected. |
| 1924 | */ |
| 1925 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { |
| 1926 | ioapic_i8259.apic = apic; |
| 1927 | ioapic_i8259.pin = pin; |
| 1928 | goto found_i8259; |
| 1929 | } |
| 1930 | } |
| 1931 | } |
| 1932 | found_i8259: |
| 1933 | /* Look to see what if the MP table has reported the ExtINT */ |
| 1934 | /* If we could not find the appropriate pin by looking at the ioapic |
| 1935 | * the i8259 probably is not connected the ioapic but give the |
| 1936 | * mptable a chance anyway. |
| 1937 | */ |
| 1938 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); |
| 1939 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); |
| 1940 | /* Trust the MP table if nothing is setup in the hardware */ |
| 1941 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { |
| 1942 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); |
| 1943 | ioapic_i8259.pin = i8259_pin; |
| 1944 | ioapic_i8259.apic = i8259_apic; |
| 1945 | } |
| 1946 | /* Complain if the MP table and the hardware disagree */ |
| 1947 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && |
| 1948 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) |
| 1949 | { |
| 1950 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); |
| 1951 | } |
| 1952 | |
| 1953 | /* |
| 1954 | * Do not trust the IO-APIC being empty at bootup |
| 1955 | */ |
| 1956 | clear_IO_APIC(); |
| 1957 | } |
| 1958 | |
| 1959 | /* |
| 1960 | * Not an __init, needed by the reboot code |
| 1961 | */ |
| 1962 | void disable_IO_APIC(void) |
| 1963 | { |
| 1964 | /* |
| 1965 | * Clear the IO-APIC before rebooting: |
| 1966 | */ |
| 1967 | clear_IO_APIC(); |
| 1968 | |
| 1969 | /* |
| 1970 | * If the i8259 is routed through an IOAPIC |
| 1971 | * Put that IOAPIC in virtual wire mode |
| 1972 | * so legacy interrupts can be delivered. |
| 1973 | */ |
| 1974 | if (ioapic_i8259.pin != -1) { |
| 1975 | struct IO_APIC_route_entry entry; |
| 1976 | |
| 1977 | memset(&entry, 0, sizeof(entry)); |
| 1978 | entry.mask = 0; /* Enabled */ |
| 1979 | entry.trigger = 0; /* Edge */ |
| 1980 | entry.irr = 0; |
| 1981 | entry.polarity = 0; /* High */ |
| 1982 | entry.delivery_status = 0; |
| 1983 | entry.dest_mode = 0; /* Physical */ |
| 1984 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
| 1985 | entry.vector = 0; |
| 1986 | entry.dest = read_apic_id(); |
| 1987 | |
| 1988 | /* |
| 1989 | * Add it to the IO-APIC irq-routing table: |
| 1990 | */ |
| 1991 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
| 1992 | } |
| 1993 | |
| 1994 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
| 1995 | } |
| 1996 | |
| 1997 | #ifdef CONFIG_X86_32 |
| 1998 | /* |
| 1999 | * function to set the IO-APIC physical IDs based on the |
| 2000 | * values stored in the MPC table. |
| 2001 | * |
| 2002 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 |
| 2003 | */ |
| 2004 | |
| 2005 | static void __init setup_ioapic_ids_from_mpc(void) |
| 2006 | { |
| 2007 | union IO_APIC_reg_00 reg_00; |
| 2008 | physid_mask_t phys_id_present_map; |
| 2009 | int apic; |
| 2010 | int i; |
| 2011 | unsigned char old_id; |
| 2012 | unsigned long flags; |
| 2013 | |
| 2014 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
| 2015 | return; |
| 2016 | |
| 2017 | /* |
| 2018 | * Don't check I/O APIC IDs for xAPIC systems. They have |
| 2019 | * no meaning without the serial APIC bus. |
| 2020 | */ |
| 2021 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
| 2022 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) |
| 2023 | return; |
| 2024 | /* |
| 2025 | * This is broken; anything with a real cpu count has to |
| 2026 | * circumvent this idiocy regardless. |
| 2027 | */ |
| 2028 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); |
| 2029 | |
| 2030 | /* |
| 2031 | * Set the IOAPIC ID to the value stored in the MPC table. |
| 2032 | */ |
| 2033 | for (apic = 0; apic < nr_ioapics; apic++) { |
| 2034 | |
| 2035 | /* Read the register 0 value */ |
| 2036 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2037 | reg_00.raw = io_apic_read(apic, 0); |
| 2038 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2039 | |
| 2040 | old_id = mp_ioapics[apic].mp_apicid; |
| 2041 | |
| 2042 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
| 2043 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
| 2044 | apic, mp_ioapics[apic].mp_apicid); |
| 2045 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
| 2046 | reg_00.bits.ID); |
| 2047 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
| 2048 | } |
| 2049 | |
| 2050 | /* |
| 2051 | * Sanity check, is the ID really free? Every APIC in a |
| 2052 | * system must have a unique ID or we get lots of nice |
| 2053 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
| 2054 | */ |
| 2055 | if (check_apicid_used(phys_id_present_map, |
| 2056 | mp_ioapics[apic].mp_apicid)) { |
| 2057 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
| 2058 | apic, mp_ioapics[apic].mp_apicid); |
| 2059 | for (i = 0; i < get_physical_broadcast(); i++) |
| 2060 | if (!physid_isset(i, phys_id_present_map)) |
| 2061 | break; |
| 2062 | if (i >= get_physical_broadcast()) |
| 2063 | panic("Max APIC ID exceeded!\n"); |
| 2064 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
| 2065 | i); |
| 2066 | physid_set(i, phys_id_present_map); |
| 2067 | mp_ioapics[apic].mp_apicid = i; |
| 2068 | } else { |
| 2069 | physid_mask_t tmp; |
| 2070 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
| 2071 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
| 2072 | "phys_id_present_map\n", |
| 2073 | mp_ioapics[apic].mp_apicid); |
| 2074 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
| 2075 | } |
| 2076 | |
| 2077 | |
| 2078 | /* |
| 2079 | * We need to adjust the IRQ routing table |
| 2080 | * if the ID changed. |
| 2081 | */ |
| 2082 | if (old_id != mp_ioapics[apic].mp_apicid) |
| 2083 | for (i = 0; i < mp_irq_entries; i++) |
| 2084 | if (mp_irqs[i].mp_dstapic == old_id) |
| 2085 | mp_irqs[i].mp_dstapic |
| 2086 | = mp_ioapics[apic].mp_apicid; |
| 2087 | |
| 2088 | /* |
| 2089 | * Read the right value from the MPC table and |
| 2090 | * write it into the ID register. |
| 2091 | */ |
| 2092 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 2093 | "...changing IO-APIC physical APIC ID to %d ...", |
| 2094 | mp_ioapics[apic].mp_apicid); |
| 2095 | |
| 2096 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
| 2097 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2098 | io_apic_write(apic, 0, reg_00.raw); |
| 2099 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2100 | |
| 2101 | /* |
| 2102 | * Sanity check |
| 2103 | */ |
| 2104 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2105 | reg_00.raw = io_apic_read(apic, 0); |
| 2106 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2107 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
| 2108 | printk("could not set ID!\n"); |
| 2109 | else |
| 2110 | apic_printk(APIC_VERBOSE, " ok.\n"); |
| 2111 | } |
| 2112 | } |
| 2113 | #endif |
| 2114 | |
| 2115 | int no_timer_check __initdata; |
| 2116 | |
| 2117 | static int __init notimercheck(char *s) |
| 2118 | { |
| 2119 | no_timer_check = 1; |
| 2120 | return 1; |
| 2121 | } |
| 2122 | __setup("no_timer_check", notimercheck); |
| 2123 | |
| 2124 | /* |
| 2125 | * There is a nasty bug in some older SMP boards, their mptable lies |
| 2126 | * about the timer IRQ. We do the following to work around the situation: |
| 2127 | * |
| 2128 | * - timer IRQ defaults to IO-APIC IRQ |
| 2129 | * - if this function detects that timer IRQs are defunct, then we fall |
| 2130 | * back to ISA timer IRQs |
| 2131 | */ |
| 2132 | static int __init timer_irq_works(void) |
| 2133 | { |
| 2134 | unsigned long t1 = jiffies; |
| 2135 | unsigned long flags; |
| 2136 | |
| 2137 | if (no_timer_check) |
| 2138 | return 1; |
| 2139 | |
| 2140 | local_save_flags(flags); |
| 2141 | local_irq_enable(); |
| 2142 | /* Let ten ticks pass... */ |
| 2143 | mdelay((10 * 1000) / HZ); |
| 2144 | local_irq_restore(flags); |
| 2145 | |
| 2146 | /* |
| 2147 | * Expect a few ticks at least, to be sure some possible |
| 2148 | * glue logic does not lock up after one or two first |
| 2149 | * ticks in a non-ExtINT mode. Also the local APIC |
| 2150 | * might have cached one ExtINT interrupt. Finally, at |
| 2151 | * least one tick may be lost due to delays. |
| 2152 | */ |
| 2153 | |
| 2154 | /* jiffies wrap? */ |
| 2155 | if (time_after(jiffies, t1 + 4)) |
| 2156 | return 1; |
| 2157 | return 0; |
| 2158 | } |
| 2159 | |
| 2160 | /* |
| 2161 | * In the SMP+IOAPIC case it might happen that there are an unspecified |
| 2162 | * number of pending IRQ events unhandled. These cases are very rare, |
| 2163 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much |
| 2164 | * better to do it this way as thus we do not have to be aware of |
| 2165 | * 'pending' interrupts in the IRQ path, except at this point. |
| 2166 | */ |
| 2167 | /* |
| 2168 | * Edge triggered needs to resend any interrupt |
| 2169 | * that was delayed but this is now handled in the device |
| 2170 | * independent code. |
| 2171 | */ |
| 2172 | |
| 2173 | /* |
| 2174 | * Starting up a edge-triggered IO-APIC interrupt is |
| 2175 | * nasty - we need to make sure that we get the edge. |
| 2176 | * If it is already asserted for some reason, we need |
| 2177 | * return 1 to indicate that is was pending. |
| 2178 | * |
| 2179 | * This is not complete - we should be able to fake |
| 2180 | * an edge even if it isn't on the 8259A... |
| 2181 | */ |
| 2182 | |
| 2183 | static unsigned int startup_ioapic_irq(unsigned int irq) |
| 2184 | { |
| 2185 | int was_pending = 0; |
| 2186 | unsigned long flags; |
| 2187 | |
| 2188 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2189 | if (irq < 16) { |
| 2190 | disable_8259A_irq(irq); |
| 2191 | if (i8259A_irq_pending(irq)) |
| 2192 | was_pending = 1; |
| 2193 | } |
| 2194 | __unmask_IO_APIC_irq(irq); |
| 2195 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2196 | |
| 2197 | return was_pending; |
| 2198 | } |
| 2199 | |
| 2200 | #ifdef CONFIG_X86_64 |
| 2201 | static int ioapic_retrigger_irq(unsigned int irq) |
| 2202 | { |
| 2203 | |
| 2204 | struct irq_cfg *cfg = irq_cfg(irq); |
| 2205 | unsigned long flags; |
| 2206 | |
| 2207 | spin_lock_irqsave(&vector_lock, flags); |
| 2208 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); |
| 2209 | spin_unlock_irqrestore(&vector_lock, flags); |
| 2210 | |
| 2211 | return 1; |
| 2212 | } |
| 2213 | #else |
| 2214 | static int ioapic_retrigger_irq(unsigned int irq) |
| 2215 | { |
| 2216 | send_IPI_self(irq_cfg(irq)->vector); |
| 2217 | |
| 2218 | return 1; |
| 2219 | } |
| 2220 | #endif |
| 2221 | |
| 2222 | /* |
| 2223 | * Level and edge triggered IO-APIC interrupts need different handling, |
| 2224 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be |
| 2225 | * handled with the level-triggered descriptor, but that one has slightly |
| 2226 | * more overhead. Level-triggered interrupts cannot be handled with the |
| 2227 | * edge-triggered handler, without risking IRQ storms and other ugly |
| 2228 | * races. |
| 2229 | */ |
| 2230 | |
| 2231 | #ifdef CONFIG_SMP |
| 2232 | |
| 2233 | #ifdef CONFIG_INTR_REMAP |
| 2234 | static void ir_irq_migration(struct work_struct *work); |
| 2235 | |
| 2236 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
| 2237 | |
| 2238 | /* |
| 2239 | * Migrate the IO-APIC irq in the presence of intr-remapping. |
| 2240 | * |
| 2241 | * For edge triggered, irq migration is a simple atomic update(of vector |
| 2242 | * and cpu destination) of IRTE and flush the hardware cache. |
| 2243 | * |
| 2244 | * For level triggered, we need to modify the io-apic RTE aswell with the update |
| 2245 | * vector information, along with modifying IRTE with vector and destination. |
| 2246 | * So irq migration for level triggered is little bit more complex compared to |
| 2247 | * edge triggered migration. But the good news is, we use the same algorithm |
| 2248 | * for level triggered migration as we have today, only difference being, |
| 2249 | * we now initiate the irq migration from process context instead of the |
| 2250 | * interrupt context. |
| 2251 | * |
| 2252 | * In future, when we do a directed EOI (combined with cpu EOI broadcast |
| 2253 | * suppression) to the IO-APIC, level triggered irq migration will also be |
| 2254 | * as simple as edge triggered migration and we can do the irq migration |
| 2255 | * with a simple atomic update to IO-APIC RTE. |
| 2256 | */ |
| 2257 | static void migrate_ioapic_irq(int irq, cpumask_t mask) |
| 2258 | { |
| 2259 | struct irq_cfg *cfg; |
| 2260 | struct irq_desc *desc; |
| 2261 | cpumask_t tmp, cleanup_mask; |
| 2262 | struct irte irte; |
| 2263 | int modify_ioapic_rte; |
| 2264 | unsigned int dest; |
| 2265 | unsigned long flags; |
| 2266 | |
| 2267 | cpus_and(tmp, mask, cpu_online_map); |
| 2268 | if (cpus_empty(tmp)) |
| 2269 | return; |
| 2270 | |
| 2271 | if (get_irte(irq, &irte)) |
| 2272 | return; |
| 2273 | |
| 2274 | if (assign_irq_vector(irq, mask)) |
| 2275 | return; |
| 2276 | |
| 2277 | cfg = irq_cfg(irq); |
| 2278 | cpus_and(tmp, cfg->domain, mask); |
| 2279 | dest = cpu_mask_to_apicid(tmp); |
| 2280 | |
| 2281 | desc = irq_to_desc(irq); |
| 2282 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
| 2283 | if (modify_ioapic_rte) { |
| 2284 | spin_lock_irqsave(&ioapic_lock, flags); |
| 2285 | __target_IO_APIC_irq(irq, dest, cfg->vector); |
| 2286 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2287 | } |
| 2288 | |
| 2289 | irte.vector = cfg->vector; |
| 2290 | irte.dest_id = IRTE_DEST(dest); |
| 2291 | |
| 2292 | /* |
| 2293 | * Modified the IRTE and flushes the Interrupt entry cache. |
| 2294 | */ |
| 2295 | modify_irte(irq, &irte); |
| 2296 | |
| 2297 | if (cfg->move_in_progress) { |
| 2298 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); |
| 2299 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); |
| 2300 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
| 2301 | cfg->move_in_progress = 0; |
| 2302 | } |
| 2303 | |
| 2304 | desc->affinity = mask; |
| 2305 | } |
| 2306 | |
| 2307 | static int migrate_irq_remapped_level(int irq) |
| 2308 | { |
| 2309 | int ret = -1; |
| 2310 | struct irq_desc *desc = irq_to_desc(irq); |
| 2311 | |
| 2312 | mask_IO_APIC_irq(irq); |
| 2313 | |
| 2314 | if (io_apic_level_ack_pending(irq)) { |
| 2315 | /* |
| 2316 | * Interrupt in progress. Migrating irq now will change the |
| 2317 | * vector information in the IO-APIC RTE and that will confuse |
| 2318 | * the EOI broadcast performed by cpu. |
| 2319 | * So, delay the irq migration to the next instance. |
| 2320 | */ |
| 2321 | schedule_delayed_work(&ir_migration_work, 1); |
| 2322 | goto unmask; |
| 2323 | } |
| 2324 | |
| 2325 | /* everthing is clear. we have right of way */ |
| 2326 | migrate_ioapic_irq(irq, desc->pending_mask); |
| 2327 | |
| 2328 | ret = 0; |
| 2329 | desc->status &= ~IRQ_MOVE_PENDING; |
| 2330 | cpus_clear(desc->pending_mask); |
| 2331 | |
| 2332 | unmask: |
| 2333 | unmask_IO_APIC_irq(irq); |
| 2334 | return ret; |
| 2335 | } |
| 2336 | |
| 2337 | static void ir_irq_migration(struct work_struct *work) |
| 2338 | { |
| 2339 | unsigned int irq; |
| 2340 | struct irq_desc *desc; |
| 2341 | |
| 2342 | for_each_irq_desc(irq, desc) { |
| 2343 | if (desc->status & IRQ_MOVE_PENDING) { |
| 2344 | unsigned long flags; |
| 2345 | |
| 2346 | spin_lock_irqsave(&desc->lock, flags); |
| 2347 | if (!desc->chip->set_affinity || |
| 2348 | !(desc->status & IRQ_MOVE_PENDING)) { |
| 2349 | desc->status &= ~IRQ_MOVE_PENDING; |
| 2350 | spin_unlock_irqrestore(&desc->lock, flags); |
| 2351 | continue; |
| 2352 | } |
| 2353 | |
| 2354 | desc->chip->set_affinity(irq, desc->pending_mask); |
| 2355 | spin_unlock_irqrestore(&desc->lock, flags); |
| 2356 | } |
| 2357 | } |
| 2358 | } |
| 2359 | |
| 2360 | /* |
| 2361 | * Migrates the IRQ destination in the process context. |
| 2362 | */ |
| 2363 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
| 2364 | { |
| 2365 | struct irq_desc *desc = irq_to_desc(irq); |
| 2366 | |
| 2367 | if (desc->status & IRQ_LEVEL) { |
| 2368 | desc->status |= IRQ_MOVE_PENDING; |
| 2369 | desc->pending_mask = mask; |
| 2370 | migrate_irq_remapped_level(irq); |
| 2371 | return; |
| 2372 | } |
| 2373 | |
| 2374 | migrate_ioapic_irq(irq, mask); |
| 2375 | } |
| 2376 | #endif |
| 2377 | |
| 2378 | asmlinkage void smp_irq_move_cleanup_interrupt(void) |
| 2379 | { |
| 2380 | unsigned vector, me; |
| 2381 | ack_APIC_irq(); |
| 2382 | #ifdef CONFIG_X86_64 |
| 2383 | exit_idle(); |
| 2384 | #endif |
| 2385 | irq_enter(); |
| 2386 | |
| 2387 | me = smp_processor_id(); |
| 2388 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
| 2389 | unsigned int irq; |
| 2390 | struct irq_desc *desc; |
| 2391 | struct irq_cfg *cfg; |
| 2392 | irq = __get_cpu_var(vector_irq)[vector]; |
| 2393 | |
| 2394 | desc = irq_to_desc(irq); |
| 2395 | if (!desc) |
| 2396 | continue; |
| 2397 | |
| 2398 | cfg = irq_cfg(irq); |
| 2399 | spin_lock(&desc->lock); |
| 2400 | if (!cfg->move_cleanup_count) |
| 2401 | goto unlock; |
| 2402 | |
| 2403 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) |
| 2404 | goto unlock; |
| 2405 | |
| 2406 | __get_cpu_var(vector_irq)[vector] = -1; |
| 2407 | cfg->move_cleanup_count--; |
| 2408 | unlock: |
| 2409 | spin_unlock(&desc->lock); |
| 2410 | } |
| 2411 | |
| 2412 | irq_exit(); |
| 2413 | } |
| 2414 | |
| 2415 | static void irq_complete_move(unsigned int irq) |
| 2416 | { |
| 2417 | struct irq_cfg *cfg = irq_cfg(irq); |
| 2418 | unsigned vector, me; |
| 2419 | |
| 2420 | if (likely(!cfg->move_in_progress)) |
| 2421 | return; |
| 2422 | |
| 2423 | vector = ~get_irq_regs()->orig_ax; |
| 2424 | me = smp_processor_id(); |
| 2425 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { |
| 2426 | cpumask_t cleanup_mask; |
| 2427 | |
| 2428 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); |
| 2429 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); |
| 2430 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
| 2431 | cfg->move_in_progress = 0; |
| 2432 | } |
| 2433 | } |
| 2434 | #else |
| 2435 | static inline void irq_complete_move(unsigned int irq) {} |
| 2436 | #endif |
| 2437 | #ifdef CONFIG_INTR_REMAP |
| 2438 | static void ack_x2apic_level(unsigned int irq) |
| 2439 | { |
| 2440 | ack_x2APIC_irq(); |
| 2441 | } |
| 2442 | |
| 2443 | static void ack_x2apic_edge(unsigned int irq) |
| 2444 | { |
| 2445 | ack_x2APIC_irq(); |
| 2446 | } |
| 2447 | #endif |
| 2448 | |
| 2449 | static void ack_apic_edge(unsigned int irq) |
| 2450 | { |
| 2451 | irq_complete_move(irq); |
| 2452 | move_native_irq(irq); |
| 2453 | ack_APIC_irq(); |
| 2454 | } |
| 2455 | |
| 2456 | #ifdef CONFIG_X86_32 |
| 2457 | atomic_t irq_mis_count; |
| 2458 | #endif |
| 2459 | |
| 2460 | static void ack_apic_level(unsigned int irq) |
| 2461 | { |
| 2462 | #ifdef CONFIG_X86_32 |
| 2463 | unsigned long v; |
| 2464 | int i; |
| 2465 | #endif |
| 2466 | int do_unmask_irq = 0; |
| 2467 | |
| 2468 | irq_complete_move(irq); |
| 2469 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
| 2470 | /* If we are moving the irq we need to mask it */ |
| 2471 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { |
| 2472 | do_unmask_irq = 1; |
| 2473 | mask_IO_APIC_irq(irq); |
| 2474 | } |
| 2475 | #endif |
| 2476 | |
| 2477 | #ifdef CONFIG_X86_32 |
| 2478 | /* |
| 2479 | * It appears there is an erratum which affects at least version 0x11 |
| 2480 | * of I/O APIC (that's the 82093AA and cores integrated into various |
| 2481 | * chipsets). Under certain conditions a level-triggered interrupt is |
| 2482 | * erroneously delivered as edge-triggered one but the respective IRR |
| 2483 | * bit gets set nevertheless. As a result the I/O unit expects an EOI |
| 2484 | * message but it will never arrive and further interrupts are blocked |
| 2485 | * from the source. The exact reason is so far unknown, but the |
| 2486 | * phenomenon was observed when two consecutive interrupt requests |
| 2487 | * from a given source get delivered to the same CPU and the source is |
| 2488 | * temporarily disabled in between. |
| 2489 | * |
| 2490 | * A workaround is to simulate an EOI message manually. We achieve it |
| 2491 | * by setting the trigger mode to edge and then to level when the edge |
| 2492 | * trigger mode gets detected in the TMR of a local APIC for a |
| 2493 | * level-triggered interrupt. We mask the source for the time of the |
| 2494 | * operation to prevent an edge-triggered interrupt escaping meanwhile. |
| 2495 | * The idea is from Manfred Spraul. --macro |
| 2496 | */ |
| 2497 | i = irq_cfg(irq)->vector; |
| 2498 | |
| 2499 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
| 2500 | #endif |
| 2501 | |
| 2502 | /* |
| 2503 | * We must acknowledge the irq before we move it or the acknowledge will |
| 2504 | * not propagate properly. |
| 2505 | */ |
| 2506 | ack_APIC_irq(); |
| 2507 | |
| 2508 | /* Now we can move and renable the irq */ |
| 2509 | if (unlikely(do_unmask_irq)) { |
| 2510 | /* Only migrate the irq if the ack has been received. |
| 2511 | * |
| 2512 | * On rare occasions the broadcast level triggered ack gets |
| 2513 | * delayed going to ioapics, and if we reprogram the |
| 2514 | * vector while Remote IRR is still set the irq will never |
| 2515 | * fire again. |
| 2516 | * |
| 2517 | * To prevent this scenario we read the Remote IRR bit |
| 2518 | * of the ioapic. This has two effects. |
| 2519 | * - On any sane system the read of the ioapic will |
| 2520 | * flush writes (and acks) going to the ioapic from |
| 2521 | * this cpu. |
| 2522 | * - We get to see if the ACK has actually been delivered. |
| 2523 | * |
| 2524 | * Based on failed experiments of reprogramming the |
| 2525 | * ioapic entry from outside of irq context starting |
| 2526 | * with masking the ioapic entry and then polling until |
| 2527 | * Remote IRR was clear before reprogramming the |
| 2528 | * ioapic I don't trust the Remote IRR bit to be |
| 2529 | * completey accurate. |
| 2530 | * |
| 2531 | * However there appears to be no other way to plug |
| 2532 | * this race, so if the Remote IRR bit is not |
| 2533 | * accurate and is causing problems then it is a hardware bug |
| 2534 | * and you can go talk to the chipset vendor about it. |
| 2535 | */ |
| 2536 | if (!io_apic_level_ack_pending(irq)) |
| 2537 | move_masked_irq(irq); |
| 2538 | unmask_IO_APIC_irq(irq); |
| 2539 | } |
| 2540 | |
| 2541 | #ifdef CONFIG_X86_32 |
| 2542 | if (!(v & (1 << (i & 0x1f)))) { |
| 2543 | atomic_inc(&irq_mis_count); |
| 2544 | spin_lock(&ioapic_lock); |
| 2545 | __mask_and_edge_IO_APIC_irq(irq); |
| 2546 | __unmask_and_level_IO_APIC_irq(irq); |
| 2547 | spin_unlock(&ioapic_lock); |
| 2548 | } |
| 2549 | #endif |
| 2550 | } |
| 2551 | |
| 2552 | static struct irq_chip ioapic_chip __read_mostly = { |
| 2553 | .name = "IO-APIC", |
| 2554 | .startup = startup_ioapic_irq, |
| 2555 | .mask = mask_IO_APIC_irq, |
| 2556 | .unmask = unmask_IO_APIC_irq, |
| 2557 | .ack = ack_apic_edge, |
| 2558 | .eoi = ack_apic_level, |
| 2559 | #ifdef CONFIG_SMP |
| 2560 | .set_affinity = set_ioapic_affinity_irq, |
| 2561 | #endif |
| 2562 | .retrigger = ioapic_retrigger_irq, |
| 2563 | }; |
| 2564 | |
| 2565 | #ifdef CONFIG_INTR_REMAP |
| 2566 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
| 2567 | .name = "IR-IO-APIC", |
| 2568 | .startup = startup_ioapic_irq, |
| 2569 | .mask = mask_IO_APIC_irq, |
| 2570 | .unmask = unmask_IO_APIC_irq, |
| 2571 | .ack = ack_x2apic_edge, |
| 2572 | .eoi = ack_x2apic_level, |
| 2573 | #ifdef CONFIG_SMP |
| 2574 | .set_affinity = set_ir_ioapic_affinity_irq, |
| 2575 | #endif |
| 2576 | .retrigger = ioapic_retrigger_irq, |
| 2577 | }; |
| 2578 | #endif |
| 2579 | |
| 2580 | static inline void init_IO_APIC_traps(void) |
| 2581 | { |
| 2582 | int irq; |
| 2583 | struct irq_desc *desc; |
| 2584 | struct irq_cfg *cfg; |
| 2585 | |
| 2586 | /* |
| 2587 | * NOTE! The local APIC isn't very good at handling |
| 2588 | * multiple interrupts at the same interrupt level. |
| 2589 | * As the interrupt level is determined by taking the |
| 2590 | * vector number and shifting that right by 4, we |
| 2591 | * want to spread these out a bit so that they don't |
| 2592 | * all fall in the same interrupt level. |
| 2593 | * |
| 2594 | * Also, we've got to be careful not to trash gate |
| 2595 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
| 2596 | */ |
| 2597 | for_each_irq_cfg(irq, cfg) { |
| 2598 | if (IO_APIC_IRQ(irq) && !cfg->vector) { |
| 2599 | /* |
| 2600 | * Hmm.. We don't have an entry for this, |
| 2601 | * so default to an old-fashioned 8259 |
| 2602 | * interrupt if we can.. |
| 2603 | */ |
| 2604 | if (irq < 16) |
| 2605 | make_8259A_irq(irq); |
| 2606 | else { |
| 2607 | desc = irq_to_desc(irq); |
| 2608 | /* Strange. Oh, well.. */ |
| 2609 | desc->chip = &no_irq_chip; |
| 2610 | } |
| 2611 | } |
| 2612 | } |
| 2613 | } |
| 2614 | |
| 2615 | /* |
| 2616 | * The local APIC irq-chip implementation: |
| 2617 | */ |
| 2618 | |
| 2619 | static void mask_lapic_irq(unsigned int irq) |
| 2620 | { |
| 2621 | unsigned long v; |
| 2622 | |
| 2623 | v = apic_read(APIC_LVT0); |
| 2624 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
| 2625 | } |
| 2626 | |
| 2627 | static void unmask_lapic_irq(unsigned int irq) |
| 2628 | { |
| 2629 | unsigned long v; |
| 2630 | |
| 2631 | v = apic_read(APIC_LVT0); |
| 2632 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
| 2633 | } |
| 2634 | |
| 2635 | static void ack_lapic_irq (unsigned int irq) |
| 2636 | { |
| 2637 | ack_APIC_irq(); |
| 2638 | } |
| 2639 | |
| 2640 | static struct irq_chip lapic_chip __read_mostly = { |
| 2641 | .name = "local-APIC", |
| 2642 | .mask = mask_lapic_irq, |
| 2643 | .unmask = unmask_lapic_irq, |
| 2644 | .ack = ack_lapic_irq, |
| 2645 | }; |
| 2646 | |
| 2647 | static void lapic_register_intr(int irq) |
| 2648 | { |
| 2649 | struct irq_desc *desc; |
| 2650 | |
| 2651 | desc = irq_to_desc(irq); |
| 2652 | desc->status &= ~IRQ_LEVEL; |
| 2653 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
| 2654 | "edge"); |
| 2655 | } |
| 2656 | |
| 2657 | static void __init setup_nmi(void) |
| 2658 | { |
| 2659 | /* |
| 2660 | * Dirty trick to enable the NMI watchdog ... |
| 2661 | * We put the 8259A master into AEOI mode and |
| 2662 | * unmask on all local APICs LVT0 as NMI. |
| 2663 | * |
| 2664 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') |
| 2665 | * is from Maciej W. Rozycki - so we do not have to EOI from |
| 2666 | * the NMI handler or the timer interrupt. |
| 2667 | */ |
| 2668 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
| 2669 | |
| 2670 | enable_NMI_through_LVT0(); |
| 2671 | |
| 2672 | apic_printk(APIC_VERBOSE, " done.\n"); |
| 2673 | } |
| 2674 | |
| 2675 | /* |
| 2676 | * This looks a bit hackish but it's about the only one way of sending |
| 2677 | * a few INTA cycles to 8259As and any associated glue logic. ICR does |
| 2678 | * not support the ExtINT mode, unfortunately. We need to send these |
| 2679 | * cycles as some i82489DX-based boards have glue logic that keeps the |
| 2680 | * 8259A interrupt line asserted until INTA. --macro |
| 2681 | */ |
| 2682 | static inline void __init unlock_ExtINT_logic(void) |
| 2683 | { |
| 2684 | int apic, pin, i; |
| 2685 | struct IO_APIC_route_entry entry0, entry1; |
| 2686 | unsigned char save_control, save_freq_select; |
| 2687 | |
| 2688 | pin = find_isa_irq_pin(8, mp_INT); |
| 2689 | if (pin == -1) { |
| 2690 | WARN_ON_ONCE(1); |
| 2691 | return; |
| 2692 | } |
| 2693 | apic = find_isa_irq_apic(8, mp_INT); |
| 2694 | if (apic == -1) { |
| 2695 | WARN_ON_ONCE(1); |
| 2696 | return; |
| 2697 | } |
| 2698 | |
| 2699 | entry0 = ioapic_read_entry(apic, pin); |
| 2700 | clear_IO_APIC_pin(apic, pin); |
| 2701 | |
| 2702 | memset(&entry1, 0, sizeof(entry1)); |
| 2703 | |
| 2704 | entry1.dest_mode = 0; /* physical delivery */ |
| 2705 | entry1.mask = 0; /* unmask IRQ now */ |
| 2706 | entry1.dest = hard_smp_processor_id(); |
| 2707 | entry1.delivery_mode = dest_ExtINT; |
| 2708 | entry1.polarity = entry0.polarity; |
| 2709 | entry1.trigger = 0; |
| 2710 | entry1.vector = 0; |
| 2711 | |
| 2712 | ioapic_write_entry(apic, pin, entry1); |
| 2713 | |
| 2714 | save_control = CMOS_READ(RTC_CONTROL); |
| 2715 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); |
| 2716 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, |
| 2717 | RTC_FREQ_SELECT); |
| 2718 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); |
| 2719 | |
| 2720 | i = 100; |
| 2721 | while (i-- > 0) { |
| 2722 | mdelay(10); |
| 2723 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) |
| 2724 | i -= 10; |
| 2725 | } |
| 2726 | |
| 2727 | CMOS_WRITE(save_control, RTC_CONTROL); |
| 2728 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); |
| 2729 | clear_IO_APIC_pin(apic, pin); |
| 2730 | |
| 2731 | ioapic_write_entry(apic, pin, entry0); |
| 2732 | } |
| 2733 | |
| 2734 | static int disable_timer_pin_1 __initdata; |
| 2735 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
| 2736 | static int __init disable_timer_pin_setup(char *arg) |
| 2737 | { |
| 2738 | disable_timer_pin_1 = 1; |
| 2739 | return 0; |
| 2740 | } |
| 2741 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
| 2742 | |
| 2743 | int timer_through_8259 __initdata; |
| 2744 | |
| 2745 | /* |
| 2746 | * This code may look a bit paranoid, but it's supposed to cooperate with |
| 2747 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ |
| 2748 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast |
| 2749 | * fanatically on his truly buggy board. |
| 2750 | * |
| 2751 | * FIXME: really need to revamp this for all platforms. |
| 2752 | */ |
| 2753 | static inline void __init check_timer(void) |
| 2754 | { |
| 2755 | struct irq_cfg *cfg = irq_cfg(0); |
| 2756 | int apic1, pin1, apic2, pin2; |
| 2757 | unsigned long flags; |
| 2758 | unsigned int ver; |
| 2759 | int no_pin1 = 0; |
| 2760 | |
| 2761 | local_irq_save(flags); |
| 2762 | |
| 2763 | ver = apic_read(APIC_LVR); |
| 2764 | ver = GET_APIC_VERSION(ver); |
| 2765 | |
| 2766 | /* |
| 2767 | * get/set the timer IRQ vector: |
| 2768 | */ |
| 2769 | disable_8259A_irq(0); |
| 2770 | assign_irq_vector(0, TARGET_CPUS); |
| 2771 | |
| 2772 | /* |
| 2773 | * As IRQ0 is to be enabled in the 8259A, the virtual |
| 2774 | * wire has to be disabled in the local APIC. Also |
| 2775 | * timer interrupts need to be acknowledged manually in |
| 2776 | * the 8259A for the i82489DX when using the NMI |
| 2777 | * watchdog as that APIC treats NMIs as level-triggered. |
| 2778 | * The AEOI mode will finish them in the 8259A |
| 2779 | * automatically. |
| 2780 | */ |
| 2781 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
| 2782 | init_8259A(1); |
| 2783 | #ifdef CONFIG_X86_32 |
| 2784 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
| 2785 | #endif |
| 2786 | |
| 2787 | pin1 = find_isa_irq_pin(0, mp_INT); |
| 2788 | apic1 = find_isa_irq_apic(0, mp_INT); |
| 2789 | pin2 = ioapic_i8259.pin; |
| 2790 | apic2 = ioapic_i8259.apic; |
| 2791 | |
| 2792 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
| 2793 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", |
| 2794 | cfg->vector, apic1, pin1, apic2, pin2); |
| 2795 | |
| 2796 | /* |
| 2797 | * Some BIOS writers are clueless and report the ExtINTA |
| 2798 | * I/O APIC input from the cascaded 8259A as the timer |
| 2799 | * interrupt input. So just in case, if only one pin |
| 2800 | * was found above, try it both directly and through the |
| 2801 | * 8259A. |
| 2802 | */ |
| 2803 | if (pin1 == -1) { |
| 2804 | #ifdef CONFIG_INTR_REMAP |
| 2805 | if (intr_remapping_enabled) |
| 2806 | panic("BIOS bug: timer not connected to IO-APIC"); |
| 2807 | #endif |
| 2808 | pin1 = pin2; |
| 2809 | apic1 = apic2; |
| 2810 | no_pin1 = 1; |
| 2811 | } else if (pin2 == -1) { |
| 2812 | pin2 = pin1; |
| 2813 | apic2 = apic1; |
| 2814 | } |
| 2815 | |
| 2816 | if (pin1 != -1) { |
| 2817 | /* |
| 2818 | * Ok, does IRQ0 through the IOAPIC work? |
| 2819 | */ |
| 2820 | if (no_pin1) { |
| 2821 | add_pin_to_irq(0, apic1, pin1); |
| 2822 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
| 2823 | } |
| 2824 | unmask_IO_APIC_irq(0); |
| 2825 | if (timer_irq_works()) { |
| 2826 | if (nmi_watchdog == NMI_IO_APIC) { |
| 2827 | setup_nmi(); |
| 2828 | enable_8259A_irq(0); |
| 2829 | } |
| 2830 | if (disable_timer_pin_1 > 0) |
| 2831 | clear_IO_APIC_pin(0, pin1); |
| 2832 | goto out; |
| 2833 | } |
| 2834 | #ifdef CONFIG_INTR_REMAP |
| 2835 | if (intr_remapping_enabled) |
| 2836 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); |
| 2837 | #endif |
| 2838 | clear_IO_APIC_pin(apic1, pin1); |
| 2839 | if (!no_pin1) |
| 2840 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
| 2841 | "8254 timer not connected to IO-APIC\n"); |
| 2842 | |
| 2843 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
| 2844 | "(IRQ0) through the 8259A ...\n"); |
| 2845 | apic_printk(APIC_QUIET, KERN_INFO |
| 2846 | "..... (found apic %d pin %d) ...\n", apic2, pin2); |
| 2847 | /* |
| 2848 | * legacy devices should be connected to IO APIC #0 |
| 2849 | */ |
| 2850 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
| 2851 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
| 2852 | unmask_IO_APIC_irq(0); |
| 2853 | enable_8259A_irq(0); |
| 2854 | if (timer_irq_works()) { |
| 2855 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
| 2856 | timer_through_8259 = 1; |
| 2857 | if (nmi_watchdog == NMI_IO_APIC) { |
| 2858 | disable_8259A_irq(0); |
| 2859 | setup_nmi(); |
| 2860 | enable_8259A_irq(0); |
| 2861 | } |
| 2862 | goto out; |
| 2863 | } |
| 2864 | /* |
| 2865 | * Cleanup, just in case ... |
| 2866 | */ |
| 2867 | disable_8259A_irq(0); |
| 2868 | clear_IO_APIC_pin(apic2, pin2); |
| 2869 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
| 2870 | } |
| 2871 | |
| 2872 | if (nmi_watchdog == NMI_IO_APIC) { |
| 2873 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
| 2874 | "through the IO-APIC - disabling NMI Watchdog!\n"); |
| 2875 | nmi_watchdog = NMI_NONE; |
| 2876 | } |
| 2877 | #ifdef CONFIG_X86_32 |
| 2878 | timer_ack = 0; |
| 2879 | #endif |
| 2880 | |
| 2881 | apic_printk(APIC_QUIET, KERN_INFO |
| 2882 | "...trying to set up timer as Virtual Wire IRQ...\n"); |
| 2883 | |
| 2884 | lapic_register_intr(0); |
| 2885 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
| 2886 | enable_8259A_irq(0); |
| 2887 | |
| 2888 | if (timer_irq_works()) { |
| 2889 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
| 2890 | goto out; |
| 2891 | } |
| 2892 | disable_8259A_irq(0); |
| 2893 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
| 2894 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
| 2895 | |
| 2896 | apic_printk(APIC_QUIET, KERN_INFO |
| 2897 | "...trying to set up timer as ExtINT IRQ...\n"); |
| 2898 | |
| 2899 | init_8259A(0); |
| 2900 | make_8259A_irq(0); |
| 2901 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
| 2902 | |
| 2903 | unlock_ExtINT_logic(); |
| 2904 | |
| 2905 | if (timer_irq_works()) { |
| 2906 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
| 2907 | goto out; |
| 2908 | } |
| 2909 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
| 2910 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
| 2911 | "report. Then try booting with the 'noapic' option.\n"); |
| 2912 | out: |
| 2913 | local_irq_restore(flags); |
| 2914 | } |
| 2915 | |
| 2916 | /* |
| 2917 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
| 2918 | * to devices. However there may be an I/O APIC pin available for |
| 2919 | * this interrupt regardless. The pin may be left unconnected, but |
| 2920 | * typically it will be reused as an ExtINT cascade interrupt for |
| 2921 | * the master 8259A. In the MPS case such a pin will normally be |
| 2922 | * reported as an ExtINT interrupt in the MP table. With ACPI |
| 2923 | * there is no provision for ExtINT interrupts, and in the absence |
| 2924 | * of an override it would be treated as an ordinary ISA I/O APIC |
| 2925 | * interrupt, that is edge-triggered and unmasked by default. We |
| 2926 | * used to do this, but it caused problems on some systems because |
| 2927 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using |
| 2928 | * the same ExtINT cascade interrupt to drive the local APIC of the |
| 2929 | * bootstrap processor. Therefore we refrain from routing IRQ2 to |
| 2930 | * the I/O APIC in all cases now. No actual device should request |
| 2931 | * it anyway. --macro |
| 2932 | */ |
| 2933 | #define PIC_IRQS (1 << PIC_CASCADE_IR) |
| 2934 | |
| 2935 | void __init setup_IO_APIC(void) |
| 2936 | { |
| 2937 | |
| 2938 | #ifdef CONFIG_X86_32 |
| 2939 | enable_IO_APIC(); |
| 2940 | #else |
| 2941 | /* |
| 2942 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP |
| 2943 | */ |
| 2944 | #endif |
| 2945 | |
| 2946 | io_apic_irqs = ~PIC_IRQS; |
| 2947 | |
| 2948 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
| 2949 | /* |
| 2950 | * Set up IO-APIC IRQ routing. |
| 2951 | */ |
| 2952 | #ifdef CONFIG_X86_32 |
| 2953 | if (!acpi_ioapic) |
| 2954 | setup_ioapic_ids_from_mpc(); |
| 2955 | #endif |
| 2956 | sync_Arb_IDs(); |
| 2957 | setup_IO_APIC_irqs(); |
| 2958 | init_IO_APIC_traps(); |
| 2959 | check_timer(); |
| 2960 | } |
| 2961 | |
| 2962 | /* |
| 2963 | * Called after all the initialization is done. If we didnt find any |
| 2964 | * APIC bugs then we can allow the modify fast path |
| 2965 | */ |
| 2966 | |
| 2967 | static int __init io_apic_bug_finalize(void) |
| 2968 | { |
| 2969 | if (sis_apic_bug == -1) |
| 2970 | sis_apic_bug = 0; |
| 2971 | return 0; |
| 2972 | } |
| 2973 | |
| 2974 | late_initcall(io_apic_bug_finalize); |
| 2975 | |
| 2976 | struct sysfs_ioapic_data { |
| 2977 | struct sys_device dev; |
| 2978 | struct IO_APIC_route_entry entry[0]; |
| 2979 | }; |
| 2980 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
| 2981 | |
| 2982 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
| 2983 | { |
| 2984 | struct IO_APIC_route_entry *entry; |
| 2985 | struct sysfs_ioapic_data *data; |
| 2986 | int i; |
| 2987 | |
| 2988 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
| 2989 | entry = data->entry; |
| 2990 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
| 2991 | *entry = ioapic_read_entry(dev->id, i); |
| 2992 | |
| 2993 | return 0; |
| 2994 | } |
| 2995 | |
| 2996 | static int ioapic_resume(struct sys_device *dev) |
| 2997 | { |
| 2998 | struct IO_APIC_route_entry *entry; |
| 2999 | struct sysfs_ioapic_data *data; |
| 3000 | unsigned long flags; |
| 3001 | union IO_APIC_reg_00 reg_00; |
| 3002 | int i; |
| 3003 | |
| 3004 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
| 3005 | entry = data->entry; |
| 3006 | |
| 3007 | spin_lock_irqsave(&ioapic_lock, flags); |
| 3008 | reg_00.raw = io_apic_read(dev->id, 0); |
| 3009 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
| 3010 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; |
| 3011 | io_apic_write(dev->id, 0, reg_00.raw); |
| 3012 | } |
| 3013 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 3014 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
| 3015 | ioapic_write_entry(dev->id, i, entry[i]); |
| 3016 | |
| 3017 | return 0; |
| 3018 | } |
| 3019 | |
| 3020 | static struct sysdev_class ioapic_sysdev_class = { |
| 3021 | .name = "ioapic", |
| 3022 | .suspend = ioapic_suspend, |
| 3023 | .resume = ioapic_resume, |
| 3024 | }; |
| 3025 | |
| 3026 | static int __init ioapic_init_sysfs(void) |
| 3027 | { |
| 3028 | struct sys_device * dev; |
| 3029 | int i, size, error; |
| 3030 | |
| 3031 | error = sysdev_class_register(&ioapic_sysdev_class); |
| 3032 | if (error) |
| 3033 | return error; |
| 3034 | |
| 3035 | for (i = 0; i < nr_ioapics; i++ ) { |
| 3036 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
| 3037 | * sizeof(struct IO_APIC_route_entry); |
| 3038 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
| 3039 | if (!mp_ioapic_data[i]) { |
| 3040 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
| 3041 | continue; |
| 3042 | } |
| 3043 | dev = &mp_ioapic_data[i]->dev; |
| 3044 | dev->id = i; |
| 3045 | dev->cls = &ioapic_sysdev_class; |
| 3046 | error = sysdev_register(dev); |
| 3047 | if (error) { |
| 3048 | kfree(mp_ioapic_data[i]); |
| 3049 | mp_ioapic_data[i] = NULL; |
| 3050 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); |
| 3051 | continue; |
| 3052 | } |
| 3053 | } |
| 3054 | |
| 3055 | return 0; |
| 3056 | } |
| 3057 | |
| 3058 | device_initcall(ioapic_init_sysfs); |
| 3059 | |
| 3060 | /* |
| 3061 | * Dynamic irq allocate and deallocation |
| 3062 | */ |
| 3063 | unsigned int create_irq_nr(unsigned int irq_want) |
| 3064 | { |
| 3065 | /* Allocate an unused irq */ |
| 3066 | unsigned int irq; |
| 3067 | unsigned int new; |
| 3068 | unsigned long flags; |
| 3069 | struct irq_cfg *cfg_new; |
| 3070 | |
| 3071 | #ifndef CONFIG_HAVE_SPARSE_IRQ |
| 3072 | irq_want = nr_irqs - 1; |
| 3073 | #endif |
| 3074 | |
| 3075 | irq = 0; |
| 3076 | spin_lock_irqsave(&vector_lock, flags); |
| 3077 | for (new = irq_want; new > 0; new--) { |
| 3078 | if (platform_legacy_irq(new)) |
| 3079 | continue; |
| 3080 | cfg_new = irq_cfg(new); |
| 3081 | if (cfg_new && cfg_new->vector != 0) |
| 3082 | continue; |
| 3083 | /* check if need to create one */ |
| 3084 | if (!cfg_new) |
| 3085 | cfg_new = irq_cfg_alloc(new); |
| 3086 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
| 3087 | irq = new; |
| 3088 | break; |
| 3089 | } |
| 3090 | spin_unlock_irqrestore(&vector_lock, flags); |
| 3091 | |
| 3092 | if (irq > 0) { |
| 3093 | dynamic_irq_init(irq); |
| 3094 | } |
| 3095 | return irq; |
| 3096 | } |
| 3097 | |
| 3098 | int create_irq(void) |
| 3099 | { |
| 3100 | int irq; |
| 3101 | |
| 3102 | irq = create_irq_nr(nr_irqs - 1); |
| 3103 | |
| 3104 | if (irq == 0) |
| 3105 | irq = -1; |
| 3106 | |
| 3107 | return irq; |
| 3108 | } |
| 3109 | |
| 3110 | void destroy_irq(unsigned int irq) |
| 3111 | { |
| 3112 | unsigned long flags; |
| 3113 | |
| 3114 | dynamic_irq_cleanup(irq); |
| 3115 | |
| 3116 | #ifdef CONFIG_INTR_REMAP |
| 3117 | free_irte(irq); |
| 3118 | #endif |
| 3119 | spin_lock_irqsave(&vector_lock, flags); |
| 3120 | __clear_irq_vector(irq); |
| 3121 | spin_unlock_irqrestore(&vector_lock, flags); |
| 3122 | } |
| 3123 | |
| 3124 | /* |
| 3125 | * MSI message composition |
| 3126 | */ |
| 3127 | #ifdef CONFIG_PCI_MSI |
| 3128 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
| 3129 | { |
| 3130 | struct irq_cfg *cfg; |
| 3131 | int err; |
| 3132 | unsigned dest; |
| 3133 | cpumask_t tmp; |
| 3134 | |
| 3135 | tmp = TARGET_CPUS; |
| 3136 | err = assign_irq_vector(irq, tmp); |
| 3137 | if (err) |
| 3138 | return err; |
| 3139 | |
| 3140 | cfg = irq_cfg(irq); |
| 3141 | cpus_and(tmp, cfg->domain, tmp); |
| 3142 | dest = cpu_mask_to_apicid(tmp); |
| 3143 | |
| 3144 | #ifdef CONFIG_INTR_REMAP |
| 3145 | if (irq_remapped(irq)) { |
| 3146 | struct irte irte; |
| 3147 | int ir_index; |
| 3148 | u16 sub_handle; |
| 3149 | |
| 3150 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); |
| 3151 | BUG_ON(ir_index == -1); |
| 3152 | |
| 3153 | memset (&irte, 0, sizeof(irte)); |
| 3154 | |
| 3155 | irte.present = 1; |
| 3156 | irte.dst_mode = INT_DEST_MODE; |
| 3157 | irte.trigger_mode = 0; /* edge */ |
| 3158 | irte.dlvry_mode = INT_DELIVERY_MODE; |
| 3159 | irte.vector = cfg->vector; |
| 3160 | irte.dest_id = IRTE_DEST(dest); |
| 3161 | |
| 3162 | modify_irte(irq, &irte); |
| 3163 | |
| 3164 | msg->address_hi = MSI_ADDR_BASE_HI; |
| 3165 | msg->data = sub_handle; |
| 3166 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | |
| 3167 | MSI_ADDR_IR_SHV | |
| 3168 | MSI_ADDR_IR_INDEX1(ir_index) | |
| 3169 | MSI_ADDR_IR_INDEX2(ir_index); |
| 3170 | } else |
| 3171 | #endif |
| 3172 | { |
| 3173 | msg->address_hi = MSI_ADDR_BASE_HI; |
| 3174 | msg->address_lo = |
| 3175 | MSI_ADDR_BASE_LO | |
| 3176 | ((INT_DEST_MODE == 0) ? |
| 3177 | MSI_ADDR_DEST_MODE_PHYSICAL: |
| 3178 | MSI_ADDR_DEST_MODE_LOGICAL) | |
| 3179 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? |
| 3180 | MSI_ADDR_REDIRECTION_CPU: |
| 3181 | MSI_ADDR_REDIRECTION_LOWPRI) | |
| 3182 | MSI_ADDR_DEST_ID(dest); |
| 3183 | |
| 3184 | msg->data = |
| 3185 | MSI_DATA_TRIGGER_EDGE | |
| 3186 | MSI_DATA_LEVEL_ASSERT | |
| 3187 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? |
| 3188 | MSI_DATA_DELIVERY_FIXED: |
| 3189 | MSI_DATA_DELIVERY_LOWPRI) | |
| 3190 | MSI_DATA_VECTOR(cfg->vector); |
| 3191 | } |
| 3192 | return err; |
| 3193 | } |
| 3194 | |
| 3195 | #ifdef CONFIG_SMP |
| 3196 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) |
| 3197 | { |
| 3198 | struct irq_cfg *cfg; |
| 3199 | struct msi_msg msg; |
| 3200 | unsigned int dest; |
| 3201 | cpumask_t tmp; |
| 3202 | struct irq_desc *desc; |
| 3203 | |
| 3204 | cpus_and(tmp, mask, cpu_online_map); |
| 3205 | if (cpus_empty(tmp)) |
| 3206 | return; |
| 3207 | |
| 3208 | if (assign_irq_vector(irq, mask)) |
| 3209 | return; |
| 3210 | |
| 3211 | cfg = irq_cfg(irq); |
| 3212 | cpus_and(tmp, cfg->domain, mask); |
| 3213 | dest = cpu_mask_to_apicid(tmp); |
| 3214 | |
| 3215 | read_msi_msg(irq, &msg); |
| 3216 | |
| 3217 | msg.data &= ~MSI_DATA_VECTOR_MASK; |
| 3218 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
| 3219 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
| 3220 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); |
| 3221 | |
| 3222 | write_msi_msg(irq, &msg); |
| 3223 | desc = irq_to_desc(irq); |
| 3224 | desc->affinity = mask; |
| 3225 | } |
| 3226 | |
| 3227 | #ifdef CONFIG_INTR_REMAP |
| 3228 | /* |
| 3229 | * Migrate the MSI irq to another cpumask. This migration is |
| 3230 | * done in the process context using interrupt-remapping hardware. |
| 3231 | */ |
| 3232 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) |
| 3233 | { |
| 3234 | struct irq_cfg *cfg; |
| 3235 | unsigned int dest; |
| 3236 | cpumask_t tmp, cleanup_mask; |
| 3237 | struct irte irte; |
| 3238 | struct irq_desc *desc; |
| 3239 | |
| 3240 | cpus_and(tmp, mask, cpu_online_map); |
| 3241 | if (cpus_empty(tmp)) |
| 3242 | return; |
| 3243 | |
| 3244 | if (get_irte(irq, &irte)) |
| 3245 | return; |
| 3246 | |
| 3247 | if (assign_irq_vector(irq, mask)) |
| 3248 | return; |
| 3249 | |
| 3250 | cfg = irq_cfg(irq); |
| 3251 | cpus_and(tmp, cfg->domain, mask); |
| 3252 | dest = cpu_mask_to_apicid(tmp); |
| 3253 | |
| 3254 | irte.vector = cfg->vector; |
| 3255 | irte.dest_id = IRTE_DEST(dest); |
| 3256 | |
| 3257 | /* |
| 3258 | * atomically update the IRTE with the new destination and vector. |
| 3259 | */ |
| 3260 | modify_irte(irq, &irte); |
| 3261 | |
| 3262 | /* |
| 3263 | * After this point, all the interrupts will start arriving |
| 3264 | * at the new destination. So, time to cleanup the previous |
| 3265 | * vector allocation. |
| 3266 | */ |
| 3267 | if (cfg->move_in_progress) { |
| 3268 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); |
| 3269 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); |
| 3270 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
| 3271 | cfg->move_in_progress = 0; |
| 3272 | } |
| 3273 | |
| 3274 | desc = irq_to_desc(irq); |
| 3275 | desc->affinity = mask; |
| 3276 | } |
| 3277 | #endif |
| 3278 | #endif /* CONFIG_SMP */ |
| 3279 | |
| 3280 | /* |
| 3281 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, |
| 3282 | * which implement the MSI or MSI-X Capability Structure. |
| 3283 | */ |
| 3284 | static struct irq_chip msi_chip = { |
| 3285 | .name = "PCI-MSI", |
| 3286 | .unmask = unmask_msi_irq, |
| 3287 | .mask = mask_msi_irq, |
| 3288 | .ack = ack_apic_edge, |
| 3289 | #ifdef CONFIG_SMP |
| 3290 | .set_affinity = set_msi_irq_affinity, |
| 3291 | #endif |
| 3292 | .retrigger = ioapic_retrigger_irq, |
| 3293 | }; |
| 3294 | |
| 3295 | #ifdef CONFIG_INTR_REMAP |
| 3296 | static struct irq_chip msi_ir_chip = { |
| 3297 | .name = "IR-PCI-MSI", |
| 3298 | .unmask = unmask_msi_irq, |
| 3299 | .mask = mask_msi_irq, |
| 3300 | .ack = ack_x2apic_edge, |
| 3301 | #ifdef CONFIG_SMP |
| 3302 | .set_affinity = ir_set_msi_irq_affinity, |
| 3303 | #endif |
| 3304 | .retrigger = ioapic_retrigger_irq, |
| 3305 | }; |
| 3306 | |
| 3307 | /* |
| 3308 | * Map the PCI dev to the corresponding remapping hardware unit |
| 3309 | * and allocate 'nvec' consecutive interrupt-remapping table entries |
| 3310 | * in it. |
| 3311 | */ |
| 3312 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) |
| 3313 | { |
| 3314 | struct intel_iommu *iommu; |
| 3315 | int index; |
| 3316 | |
| 3317 | iommu = map_dev_to_ir(dev); |
| 3318 | if (!iommu) { |
| 3319 | printk(KERN_ERR |
| 3320 | "Unable to map PCI %s to iommu\n", pci_name(dev)); |
| 3321 | return -ENOENT; |
| 3322 | } |
| 3323 | |
| 3324 | index = alloc_irte(iommu, irq, nvec); |
| 3325 | if (index < 0) { |
| 3326 | printk(KERN_ERR |
| 3327 | "Unable to allocate %d IRTE for PCI %s\n", nvec, |
| 3328 | pci_name(dev)); |
| 3329 | return -ENOSPC; |
| 3330 | } |
| 3331 | return index; |
| 3332 | } |
| 3333 | #endif |
| 3334 | |
| 3335 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq) |
| 3336 | { |
| 3337 | int ret; |
| 3338 | struct msi_msg msg; |
| 3339 | |
| 3340 | ret = msi_compose_msg(dev, irq, &msg); |
| 3341 | if (ret < 0) |
| 3342 | return ret; |
| 3343 | |
| 3344 | set_irq_msi(irq, desc); |
| 3345 | write_msi_msg(irq, &msg); |
| 3346 | |
| 3347 | #ifdef CONFIG_INTR_REMAP |
| 3348 | if (irq_remapped(irq)) { |
| 3349 | struct irq_desc *desc = irq_to_desc(irq); |
| 3350 | /* |
| 3351 | * irq migration in process context |
| 3352 | */ |
| 3353 | desc->status |= IRQ_MOVE_PCNTXT; |
| 3354 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); |
| 3355 | } else |
| 3356 | #endif |
| 3357 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
| 3358 | |
| 3359 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
| 3360 | |
| 3361 | return 0; |
| 3362 | } |
| 3363 | |
| 3364 | static unsigned int build_irq_for_pci_dev(struct pci_dev *dev) |
| 3365 | { |
| 3366 | unsigned int irq; |
| 3367 | |
| 3368 | irq = dev->bus->number; |
| 3369 | irq <<= 8; |
| 3370 | irq |= dev->devfn; |
| 3371 | irq <<= 12; |
| 3372 | |
| 3373 | return irq; |
| 3374 | } |
| 3375 | |
| 3376 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
| 3377 | { |
| 3378 | unsigned int irq; |
| 3379 | int ret; |
| 3380 | unsigned int irq_want; |
| 3381 | |
| 3382 | irq_want = build_irq_for_pci_dev(dev) + 0x100; |
| 3383 | |
| 3384 | irq = create_irq_nr(irq_want); |
| 3385 | if (irq == 0) |
| 3386 | return -1; |
| 3387 | |
| 3388 | #ifdef CONFIG_INTR_REMAP |
| 3389 | if (!intr_remapping_enabled) |
| 3390 | goto no_ir; |
| 3391 | |
| 3392 | ret = msi_alloc_irte(dev, irq, 1); |
| 3393 | if (ret < 0) |
| 3394 | goto error; |
| 3395 | no_ir: |
| 3396 | #endif |
| 3397 | ret = setup_msi_irq(dev, desc, irq); |
| 3398 | if (ret < 0) { |
| 3399 | destroy_irq(irq); |
| 3400 | return ret; |
| 3401 | } |
| 3402 | return 0; |
| 3403 | |
| 3404 | #ifdef CONFIG_INTR_REMAP |
| 3405 | error: |
| 3406 | destroy_irq(irq); |
| 3407 | return ret; |
| 3408 | #endif |
| 3409 | } |
| 3410 | |
| 3411 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
| 3412 | { |
| 3413 | unsigned int irq; |
| 3414 | int ret, sub_handle; |
| 3415 | struct msi_desc *desc; |
| 3416 | unsigned int irq_want; |
| 3417 | |
| 3418 | #ifdef CONFIG_INTR_REMAP |
| 3419 | struct intel_iommu *iommu = 0; |
| 3420 | int index = 0; |
| 3421 | #endif |
| 3422 | |
| 3423 | irq_want = build_irq_for_pci_dev(dev) + 0x100; |
| 3424 | sub_handle = 0; |
| 3425 | list_for_each_entry(desc, &dev->msi_list, list) { |
| 3426 | irq = create_irq_nr(irq_want--); |
| 3427 | if (irq == 0) |
| 3428 | return -1; |
| 3429 | #ifdef CONFIG_INTR_REMAP |
| 3430 | if (!intr_remapping_enabled) |
| 3431 | goto no_ir; |
| 3432 | |
| 3433 | if (!sub_handle) { |
| 3434 | /* |
| 3435 | * allocate the consecutive block of IRTE's |
| 3436 | * for 'nvec' |
| 3437 | */ |
| 3438 | index = msi_alloc_irte(dev, irq, nvec); |
| 3439 | if (index < 0) { |
| 3440 | ret = index; |
| 3441 | goto error; |
| 3442 | } |
| 3443 | } else { |
| 3444 | iommu = map_dev_to_ir(dev); |
| 3445 | if (!iommu) { |
| 3446 | ret = -ENOENT; |
| 3447 | goto error; |
| 3448 | } |
| 3449 | /* |
| 3450 | * setup the mapping between the irq and the IRTE |
| 3451 | * base index, the sub_handle pointing to the |
| 3452 | * appropriate interrupt remap table entry. |
| 3453 | */ |
| 3454 | set_irte_irq(irq, iommu, index, sub_handle); |
| 3455 | } |
| 3456 | no_ir: |
| 3457 | #endif |
| 3458 | ret = setup_msi_irq(dev, desc, irq); |
| 3459 | if (ret < 0) |
| 3460 | goto error; |
| 3461 | sub_handle++; |
| 3462 | } |
| 3463 | return 0; |
| 3464 | |
| 3465 | error: |
| 3466 | destroy_irq(irq); |
| 3467 | return ret; |
| 3468 | } |
| 3469 | |
| 3470 | void arch_teardown_msi_irq(unsigned int irq) |
| 3471 | { |
| 3472 | destroy_irq(irq); |
| 3473 | } |
| 3474 | |
| 3475 | #ifdef CONFIG_DMAR |
| 3476 | #ifdef CONFIG_SMP |
| 3477 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) |
| 3478 | { |
| 3479 | struct irq_cfg *cfg; |
| 3480 | struct msi_msg msg; |
| 3481 | unsigned int dest; |
| 3482 | cpumask_t tmp; |
| 3483 | struct irq_desc *desc; |
| 3484 | |
| 3485 | cpus_and(tmp, mask, cpu_online_map); |
| 3486 | if (cpus_empty(tmp)) |
| 3487 | return; |
| 3488 | |
| 3489 | if (assign_irq_vector(irq, mask)) |
| 3490 | return; |
| 3491 | |
| 3492 | cfg = irq_cfg(irq); |
| 3493 | cpus_and(tmp, cfg->domain, mask); |
| 3494 | dest = cpu_mask_to_apicid(tmp); |
| 3495 | |
| 3496 | dmar_msi_read(irq, &msg); |
| 3497 | |
| 3498 | msg.data &= ~MSI_DATA_VECTOR_MASK; |
| 3499 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
| 3500 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
| 3501 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); |
| 3502 | |
| 3503 | dmar_msi_write(irq, &msg); |
| 3504 | desc = irq_to_desc(irq); |
| 3505 | desc->affinity = mask; |
| 3506 | } |
| 3507 | #endif /* CONFIG_SMP */ |
| 3508 | |
| 3509 | struct irq_chip dmar_msi_type = { |
| 3510 | .name = "DMAR_MSI", |
| 3511 | .unmask = dmar_msi_unmask, |
| 3512 | .mask = dmar_msi_mask, |
| 3513 | .ack = ack_apic_edge, |
| 3514 | #ifdef CONFIG_SMP |
| 3515 | .set_affinity = dmar_msi_set_affinity, |
| 3516 | #endif |
| 3517 | .retrigger = ioapic_retrigger_irq, |
| 3518 | }; |
| 3519 | |
| 3520 | int arch_setup_dmar_msi(unsigned int irq) |
| 3521 | { |
| 3522 | int ret; |
| 3523 | struct msi_msg msg; |
| 3524 | |
| 3525 | ret = msi_compose_msg(NULL, irq, &msg); |
| 3526 | if (ret < 0) |
| 3527 | return ret; |
| 3528 | dmar_msi_write(irq, &msg); |
| 3529 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
| 3530 | "edge"); |
| 3531 | return 0; |
| 3532 | } |
| 3533 | #endif |
| 3534 | |
| 3535 | #ifdef CONFIG_HPET_TIMER |
| 3536 | |
| 3537 | #ifdef CONFIG_SMP |
| 3538 | static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask) |
| 3539 | { |
| 3540 | struct irq_cfg *cfg; |
| 3541 | struct irq_desc *desc; |
| 3542 | struct msi_msg msg; |
| 3543 | unsigned int dest; |
| 3544 | cpumask_t tmp; |
| 3545 | |
| 3546 | cpus_and(tmp, mask, cpu_online_map); |
| 3547 | if (cpus_empty(tmp)) |
| 3548 | return; |
| 3549 | |
| 3550 | if (assign_irq_vector(irq, mask)) |
| 3551 | return; |
| 3552 | |
| 3553 | cfg = irq_cfg(irq); |
| 3554 | cpus_and(tmp, cfg->domain, mask); |
| 3555 | dest = cpu_mask_to_apicid(tmp); |
| 3556 | |
| 3557 | hpet_msi_read(irq, &msg); |
| 3558 | |
| 3559 | msg.data &= ~MSI_DATA_VECTOR_MASK; |
| 3560 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
| 3561 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
| 3562 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); |
| 3563 | |
| 3564 | hpet_msi_write(irq, &msg); |
| 3565 | desc = irq_to_desc(irq); |
| 3566 | desc->affinity = mask; |
| 3567 | } |
| 3568 | #endif /* CONFIG_SMP */ |
| 3569 | |
| 3570 | struct irq_chip hpet_msi_type = { |
| 3571 | .name = "HPET_MSI", |
| 3572 | .unmask = hpet_msi_unmask, |
| 3573 | .mask = hpet_msi_mask, |
| 3574 | .ack = ack_apic_edge, |
| 3575 | #ifdef CONFIG_SMP |
| 3576 | .set_affinity = hpet_msi_set_affinity, |
| 3577 | #endif |
| 3578 | .retrigger = ioapic_retrigger_irq, |
| 3579 | }; |
| 3580 | |
| 3581 | int arch_setup_hpet_msi(unsigned int irq) |
| 3582 | { |
| 3583 | int ret; |
| 3584 | struct msi_msg msg; |
| 3585 | |
| 3586 | ret = msi_compose_msg(NULL, irq, &msg); |
| 3587 | if (ret < 0) |
| 3588 | return ret; |
| 3589 | |
| 3590 | hpet_msi_write(irq, &msg); |
| 3591 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
| 3592 | "edge"); |
| 3593 | |
| 3594 | return 0; |
| 3595 | } |
| 3596 | #endif |
| 3597 | |
| 3598 | #endif /* CONFIG_PCI_MSI */ |
| 3599 | /* |
| 3600 | * Hypertransport interrupt support |
| 3601 | */ |
| 3602 | #ifdef CONFIG_HT_IRQ |
| 3603 | |
| 3604 | #ifdef CONFIG_SMP |
| 3605 | |
| 3606 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
| 3607 | { |
| 3608 | struct ht_irq_msg msg; |
| 3609 | fetch_ht_irq_msg(irq, &msg); |
| 3610 | |
| 3611 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
| 3612 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
| 3613 | |
| 3614 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
| 3615 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
| 3616 | |
| 3617 | write_ht_irq_msg(irq, &msg); |
| 3618 | } |
| 3619 | |
| 3620 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) |
| 3621 | { |
| 3622 | struct irq_cfg *cfg; |
| 3623 | unsigned int dest; |
| 3624 | cpumask_t tmp; |
| 3625 | struct irq_desc *desc; |
| 3626 | |
| 3627 | cpus_and(tmp, mask, cpu_online_map); |
| 3628 | if (cpus_empty(tmp)) |
| 3629 | return; |
| 3630 | |
| 3631 | if (assign_irq_vector(irq, mask)) |
| 3632 | return; |
| 3633 | |
| 3634 | cfg = irq_cfg(irq); |
| 3635 | cpus_and(tmp, cfg->domain, mask); |
| 3636 | dest = cpu_mask_to_apicid(tmp); |
| 3637 | |
| 3638 | target_ht_irq(irq, dest, cfg->vector); |
| 3639 | desc = irq_to_desc(irq); |
| 3640 | desc->affinity = mask; |
| 3641 | } |
| 3642 | #endif |
| 3643 | |
| 3644 | static struct irq_chip ht_irq_chip = { |
| 3645 | .name = "PCI-HT", |
| 3646 | .mask = mask_ht_irq, |
| 3647 | .unmask = unmask_ht_irq, |
| 3648 | .ack = ack_apic_edge, |
| 3649 | #ifdef CONFIG_SMP |
| 3650 | .set_affinity = set_ht_irq_affinity, |
| 3651 | #endif |
| 3652 | .retrigger = ioapic_retrigger_irq, |
| 3653 | }; |
| 3654 | |
| 3655 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) |
| 3656 | { |
| 3657 | struct irq_cfg *cfg; |
| 3658 | int err; |
| 3659 | cpumask_t tmp; |
| 3660 | |
| 3661 | tmp = TARGET_CPUS; |
| 3662 | err = assign_irq_vector(irq, tmp); |
| 3663 | if (!err) { |
| 3664 | struct ht_irq_msg msg; |
| 3665 | unsigned dest; |
| 3666 | |
| 3667 | cfg = irq_cfg(irq); |
| 3668 | cpus_and(tmp, cfg->domain, tmp); |
| 3669 | dest = cpu_mask_to_apicid(tmp); |
| 3670 | |
| 3671 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
| 3672 | |
| 3673 | msg.address_lo = |
| 3674 | HT_IRQ_LOW_BASE | |
| 3675 | HT_IRQ_LOW_DEST_ID(dest) | |
| 3676 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
| 3677 | ((INT_DEST_MODE == 0) ? |
| 3678 | HT_IRQ_LOW_DM_PHYSICAL : |
| 3679 | HT_IRQ_LOW_DM_LOGICAL) | |
| 3680 | HT_IRQ_LOW_RQEOI_EDGE | |
| 3681 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? |
| 3682 | HT_IRQ_LOW_MT_FIXED : |
| 3683 | HT_IRQ_LOW_MT_ARBITRATED) | |
| 3684 | HT_IRQ_LOW_IRQ_MASKED; |
| 3685 | |
| 3686 | write_ht_irq_msg(irq, &msg); |
| 3687 | |
| 3688 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
| 3689 | handle_edge_irq, "edge"); |
| 3690 | |
| 3691 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
| 3692 | } |
| 3693 | return err; |
| 3694 | } |
| 3695 | #endif /* CONFIG_HT_IRQ */ |
| 3696 | |
| 3697 | #ifdef CONFIG_X86_64 |
| 3698 | /* |
| 3699 | * Re-target the irq to the specified CPU and enable the specified MMR located |
| 3700 | * on the specified blade to allow the sending of MSIs to the specified CPU. |
| 3701 | */ |
| 3702 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, |
| 3703 | unsigned long mmr_offset) |
| 3704 | { |
| 3705 | const cpumask_t *eligible_cpu = get_cpu_mask(cpu); |
| 3706 | struct irq_cfg *cfg; |
| 3707 | int mmr_pnode; |
| 3708 | unsigned long mmr_value; |
| 3709 | struct uv_IO_APIC_route_entry *entry; |
| 3710 | unsigned long flags; |
| 3711 | int err; |
| 3712 | |
| 3713 | err = assign_irq_vector(irq, *eligible_cpu); |
| 3714 | if (err != 0) |
| 3715 | return err; |
| 3716 | |
| 3717 | spin_lock_irqsave(&vector_lock, flags); |
| 3718 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, |
| 3719 | irq_name); |
| 3720 | spin_unlock_irqrestore(&vector_lock, flags); |
| 3721 | |
| 3722 | cfg = irq_cfg(irq); |
| 3723 | |
| 3724 | mmr_value = 0; |
| 3725 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; |
| 3726 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
| 3727 | |
| 3728 | entry->vector = cfg->vector; |
| 3729 | entry->delivery_mode = INT_DELIVERY_MODE; |
| 3730 | entry->dest_mode = INT_DEST_MODE; |
| 3731 | entry->polarity = 0; |
| 3732 | entry->trigger = 0; |
| 3733 | entry->mask = 0; |
| 3734 | entry->dest = cpu_mask_to_apicid(*eligible_cpu); |
| 3735 | |
| 3736 | mmr_pnode = uv_blade_to_pnode(mmr_blade); |
| 3737 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); |
| 3738 | |
| 3739 | return irq; |
| 3740 | } |
| 3741 | |
| 3742 | /* |
| 3743 | * Disable the specified MMR located on the specified blade so that MSIs are |
| 3744 | * longer allowed to be sent. |
| 3745 | */ |
| 3746 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) |
| 3747 | { |
| 3748 | unsigned long mmr_value; |
| 3749 | struct uv_IO_APIC_route_entry *entry; |
| 3750 | int mmr_pnode; |
| 3751 | |
| 3752 | mmr_value = 0; |
| 3753 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; |
| 3754 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
| 3755 | |
| 3756 | entry->mask = 1; |
| 3757 | |
| 3758 | mmr_pnode = uv_blade_to_pnode(mmr_blade); |
| 3759 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); |
| 3760 | } |
| 3761 | #endif /* CONFIG_X86_64 */ |
| 3762 | |
| 3763 | int __init io_apic_get_redir_entries (int ioapic) |
| 3764 | { |
| 3765 | union IO_APIC_reg_01 reg_01; |
| 3766 | unsigned long flags; |
| 3767 | |
| 3768 | spin_lock_irqsave(&ioapic_lock, flags); |
| 3769 | reg_01.raw = io_apic_read(ioapic, 1); |
| 3770 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 3771 | |
| 3772 | return reg_01.bits.entries; |
| 3773 | } |
| 3774 | |
| 3775 | int __init probe_nr_irqs(void) |
| 3776 | { |
| 3777 | int idx; |
| 3778 | int nr = 0; |
| 3779 | #ifndef CONFIG_XEN |
| 3780 | int nr_min = 32; |
| 3781 | #else |
| 3782 | int nr_min = NR_IRQS; |
| 3783 | #endif |
| 3784 | |
| 3785 | for (idx = 0; idx < nr_ioapics; idx++) |
| 3786 | nr += io_apic_get_redir_entries(idx) + 1; |
| 3787 | |
| 3788 | /* double it for hotplug and msi and nmi */ |
| 3789 | nr <<= 1; |
| 3790 | |
| 3791 | /* something wrong ? */ |
| 3792 | if (nr < nr_min) |
| 3793 | nr = nr_min; |
| 3794 | |
| 3795 | return nr; |
| 3796 | } |
| 3797 | |
| 3798 | /* -------------------------------------------------------------------------- |
| 3799 | ACPI-based IOAPIC Configuration |
| 3800 | -------------------------------------------------------------------------- */ |
| 3801 | |
| 3802 | #ifdef CONFIG_ACPI |
| 3803 | |
| 3804 | #ifdef CONFIG_X86_32 |
| 3805 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
| 3806 | { |
| 3807 | union IO_APIC_reg_00 reg_00; |
| 3808 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; |
| 3809 | physid_mask_t tmp; |
| 3810 | unsigned long flags; |
| 3811 | int i = 0; |
| 3812 | |
| 3813 | /* |
| 3814 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
| 3815 | * buses (one for LAPICs, one for IOAPICs), where predecessors only |
| 3816 | * supports up to 16 on one shared APIC bus. |
| 3817 | * |
| 3818 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
| 3819 | * advantage of new APIC bus architecture. |
| 3820 | */ |
| 3821 | |
| 3822 | if (physids_empty(apic_id_map)) |
| 3823 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); |
| 3824 | |
| 3825 | spin_lock_irqsave(&ioapic_lock, flags); |
| 3826 | reg_00.raw = io_apic_read(ioapic, 0); |
| 3827 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 3828 | |
| 3829 | if (apic_id >= get_physical_broadcast()) { |
| 3830 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " |
| 3831 | "%d\n", ioapic, apic_id, reg_00.bits.ID); |
| 3832 | apic_id = reg_00.bits.ID; |
| 3833 | } |
| 3834 | |
| 3835 | /* |
| 3836 | * Every APIC in a system must have a unique ID or we get lots of nice |
| 3837 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
| 3838 | */ |
| 3839 | if (check_apicid_used(apic_id_map, apic_id)) { |
| 3840 | |
| 3841 | for (i = 0; i < get_physical_broadcast(); i++) { |
| 3842 | if (!check_apicid_used(apic_id_map, i)) |
| 3843 | break; |
| 3844 | } |
| 3845 | |
| 3846 | if (i == get_physical_broadcast()) |
| 3847 | panic("Max apic_id exceeded!\n"); |
| 3848 | |
| 3849 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " |
| 3850 | "trying %d\n", ioapic, apic_id, i); |
| 3851 | |
| 3852 | apic_id = i; |
| 3853 | } |
| 3854 | |
| 3855 | tmp = apicid_to_cpu_present(apic_id); |
| 3856 | physids_or(apic_id_map, apic_id_map, tmp); |
| 3857 | |
| 3858 | if (reg_00.bits.ID != apic_id) { |
| 3859 | reg_00.bits.ID = apic_id; |
| 3860 | |
| 3861 | spin_lock_irqsave(&ioapic_lock, flags); |
| 3862 | io_apic_write(ioapic, 0, reg_00.raw); |
| 3863 | reg_00.raw = io_apic_read(ioapic, 0); |
| 3864 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 3865 | |
| 3866 | /* Sanity check */ |
| 3867 | if (reg_00.bits.ID != apic_id) { |
| 3868 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); |
| 3869 | return -1; |
| 3870 | } |
| 3871 | } |
| 3872 | |
| 3873 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 3874 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); |
| 3875 | |
| 3876 | return apic_id; |
| 3877 | } |
| 3878 | |
| 3879 | int __init io_apic_get_version(int ioapic) |
| 3880 | { |
| 3881 | union IO_APIC_reg_01 reg_01; |
| 3882 | unsigned long flags; |
| 3883 | |
| 3884 | spin_lock_irqsave(&ioapic_lock, flags); |
| 3885 | reg_01.raw = io_apic_read(ioapic, 1); |
| 3886 | spin_unlock_irqrestore(&ioapic_lock, flags); |
| 3887 | |
| 3888 | return reg_01.bits.version; |
| 3889 | } |
| 3890 | #endif |
| 3891 | |
| 3892 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
| 3893 | { |
| 3894 | if (!IO_APIC_IRQ(irq)) { |
| 3895 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
| 3896 | ioapic); |
| 3897 | return -EINVAL; |
| 3898 | } |
| 3899 | |
| 3900 | /* |
| 3901 | * IRQs < 16 are already in the irq_2_pin[] map |
| 3902 | */ |
| 3903 | if (irq >= 16) |
| 3904 | add_pin_to_irq(irq, ioapic, pin); |
| 3905 | |
| 3906 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
| 3907 | |
| 3908 | return 0; |
| 3909 | } |
| 3910 | |
| 3911 | |
| 3912 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
| 3913 | { |
| 3914 | int i; |
| 3915 | |
| 3916 | if (skip_ioapic_setup) |
| 3917 | return -1; |
| 3918 | |
| 3919 | for (i = 0; i < mp_irq_entries; i++) |
| 3920 | if (mp_irqs[i].mp_irqtype == mp_INT && |
| 3921 | mp_irqs[i].mp_srcbusirq == bus_irq) |
| 3922 | break; |
| 3923 | if (i >= mp_irq_entries) |
| 3924 | return -1; |
| 3925 | |
| 3926 | *trigger = irq_trigger(i); |
| 3927 | *polarity = irq_polarity(i); |
| 3928 | return 0; |
| 3929 | } |
| 3930 | |
| 3931 | #endif /* CONFIG_ACPI */ |
| 3932 | |
| 3933 | /* |
| 3934 | * This function currently is only a helper for the i386 smp boot process where |
| 3935 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
| 3936 | * so mask in all cases should simply be TARGET_CPUS |
| 3937 | */ |
| 3938 | #ifdef CONFIG_SMP |
| 3939 | void __init setup_ioapic_dest(void) |
| 3940 | { |
| 3941 | int pin, ioapic, irq, irq_entry; |
| 3942 | struct irq_cfg *cfg; |
| 3943 | |
| 3944 | if (skip_ioapic_setup == 1) |
| 3945 | return; |
| 3946 | |
| 3947 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { |
| 3948 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
| 3949 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
| 3950 | if (irq_entry == -1) |
| 3951 | continue; |
| 3952 | irq = pin_2_irq(irq_entry, ioapic, pin); |
| 3953 | |
| 3954 | /* setup_IO_APIC_irqs could fail to get vector for some device |
| 3955 | * when you have too many devices, because at that time only boot |
| 3956 | * cpu is online. |
| 3957 | */ |
| 3958 | cfg = irq_cfg(irq); |
| 3959 | if (!cfg->vector) |
| 3960 | setup_IO_APIC_irq(ioapic, pin, irq, |
| 3961 | irq_trigger(irq_entry), |
| 3962 | irq_polarity(irq_entry)); |
| 3963 | #ifdef CONFIG_INTR_REMAP |
| 3964 | else if (intr_remapping_enabled) |
| 3965 | set_ir_ioapic_affinity_irq(irq, TARGET_CPUS); |
| 3966 | #endif |
| 3967 | else |
| 3968 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
| 3969 | } |
| 3970 | |
| 3971 | } |
| 3972 | } |
| 3973 | #endif |
| 3974 | |
| 3975 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
| 3976 | |
| 3977 | static struct resource *ioapic_resources; |
| 3978 | |
| 3979 | static struct resource * __init ioapic_setup_resources(void) |
| 3980 | { |
| 3981 | unsigned long n; |
| 3982 | struct resource *res; |
| 3983 | char *mem; |
| 3984 | int i; |
| 3985 | |
| 3986 | if (nr_ioapics <= 0) |
| 3987 | return NULL; |
| 3988 | |
| 3989 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); |
| 3990 | n *= nr_ioapics; |
| 3991 | |
| 3992 | mem = alloc_bootmem(n); |
| 3993 | res = (void *)mem; |
| 3994 | |
| 3995 | if (mem != NULL) { |
| 3996 | mem += sizeof(struct resource) * nr_ioapics; |
| 3997 | |
| 3998 | for (i = 0; i < nr_ioapics; i++) { |
| 3999 | res[i].name = mem; |
| 4000 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
| 4001 | sprintf(mem, "IOAPIC %u", i); |
| 4002 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
| 4003 | } |
| 4004 | } |
| 4005 | |
| 4006 | ioapic_resources = res; |
| 4007 | |
| 4008 | return res; |
| 4009 | } |
| 4010 | |
| 4011 | void __init ioapic_init_mappings(void) |
| 4012 | { |
| 4013 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; |
| 4014 | int i; |
| 4015 | struct resource *ioapic_res; |
| 4016 | |
| 4017 | ioapic_res = ioapic_setup_resources(); |
| 4018 | for (i = 0; i < nr_ioapics; i++) { |
| 4019 | if (smp_found_config) { |
| 4020 | ioapic_phys = mp_ioapics[i].mp_apicaddr; |
| 4021 | #ifdef CONFIG_X86_32 |
| 4022 | if (!ioapic_phys) { |
| 4023 | printk(KERN_ERR |
| 4024 | "WARNING: bogus zero IO-APIC " |
| 4025 | "address found in MPTABLE, " |
| 4026 | "disabling IO/APIC support!\n"); |
| 4027 | smp_found_config = 0; |
| 4028 | skip_ioapic_setup = 1; |
| 4029 | goto fake_ioapic_page; |
| 4030 | } |
| 4031 | #endif |
| 4032 | } else { |
| 4033 | #ifdef CONFIG_X86_32 |
| 4034 | fake_ioapic_page: |
| 4035 | #endif |
| 4036 | ioapic_phys = (unsigned long) |
| 4037 | alloc_bootmem_pages(PAGE_SIZE); |
| 4038 | ioapic_phys = __pa(ioapic_phys); |
| 4039 | } |
| 4040 | set_fixmap_nocache(idx, ioapic_phys); |
| 4041 | apic_printk(APIC_VERBOSE, |
| 4042 | "mapped IOAPIC to %08lx (%08lx)\n", |
| 4043 | __fix_to_virt(idx), ioapic_phys); |
| 4044 | idx++; |
| 4045 | |
| 4046 | if (ioapic_res != NULL) { |
| 4047 | ioapic_res->start = ioapic_phys; |
| 4048 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; |
| 4049 | ioapic_res++; |
| 4050 | } |
| 4051 | } |
| 4052 | } |
| 4053 | |
| 4054 | static int __init ioapic_insert_resources(void) |
| 4055 | { |
| 4056 | int i; |
| 4057 | struct resource *r = ioapic_resources; |
| 4058 | |
| 4059 | if (!r) { |
| 4060 | printk(KERN_ERR |
| 4061 | "IO APIC resources could be not be allocated.\n"); |
| 4062 | return -1; |
| 4063 | } |
| 4064 | |
| 4065 | for (i = 0; i < nr_ioapics; i++) { |
| 4066 | insert_resource(&iomem_resource, r); |
| 4067 | r++; |
| 4068 | } |
| 4069 | |
| 4070 | return 0; |
| 4071 | } |
| 4072 | |
| 4073 | /* Insert the IO APIC resources after PCI initialization has occured to handle |
| 4074 | * IO APICS that are mapped in on a BAR in PCI space. */ |
| 4075 | late_initcall(ioapic_insert_resources); |