[deliverable/linux.git] / arch / x86 / kernel / irq.c

/*
 * Common interrupt code for 32 and 64 bit
 */
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/of.h>
#include <linux/seq_file.h>
#include <linux/smp.h>
#include <linux/ftrace.h>
#include <linux/delay.h>
#include <linux/export.h>

#include <asm/apic.h>
#include <asm/io_apic.h>
#include <asm/irq.h>
#include <asm/idle.h>
#include <asm/mce.h>
#include <asm/hw_irq.h>

atomic_t irq_err_count;

/* Function pointer for generic interrupt vector handling */
void (*x86_platform_ipi_callback)(void) = NULL;

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	if (printk_ratelimit())
		pr_err("unexpected IRQ trap at vector %02x\n", irq);

	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But only ack when the APIC is enabled -AK
	 */
	ack_APIC_irq();
}

#define irq_stats(x)		(&per_cpu(irq_stat, x))
/*
 * /proc/interrupts printing for arch specific interrupts
 */
int arch_show_interrupts(struct seq_file *p, int prec)
{
	int j;

	seq_printf(p, "%*s: ", prec, "NMI");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
	seq_printf(p, "  Non-maskable interrupts\n");
#ifdef CONFIG_X86_LOCAL_APIC
	seq_printf(p, "%*s: ", prec, "LOC");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
	seq_printf(p, "  Local timer interrupts\n");

	seq_printf(p, "%*s: ", prec, "SPU");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
	seq_printf(p, "  Spurious interrupts\n");
	seq_printf(p, "%*s: ", prec, "PMI");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
	seq_printf(p, "  Performance monitoring interrupts\n");
	seq_printf(p, "%*s: ", prec, "IWI");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
	seq_printf(p, "  IRQ work interrupts\n");
	seq_printf(p, "%*s: ", prec, "RTR");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
	seq_printf(p, "  APIC ICR read retries\n");
#endif
	if (x86_platform_ipi_callback) {
		seq_printf(p, "%*s: ", prec, "PLT");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
		seq_printf(p, "  Platform interrupts\n");
	}
#ifdef CONFIG_SMP
	seq_printf(p, "%*s: ", prec, "RES");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
	seq_printf(p, "  Rescheduling interrupts\n");
	seq_printf(p, "%*s: ", prec, "CAL");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
	seq_printf(p, "  Function call interrupts\n");
	seq_printf(p, "%*s: ", prec, "TLB");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
	seq_printf(p, "  TLB shootdowns\n");
#endif
#ifdef CONFIG_X86_THERMAL_VECTOR
	seq_printf(p, "%*s: ", prec, "TRM");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
	seq_printf(p, "  Thermal event interrupts\n");
#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
	seq_printf(p, "%*s: ", prec, "THR");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
	seq_printf(p, "  Threshold APIC interrupts\n");
#endif
#ifdef CONFIG_X86_MCE
	seq_printf(p, "%*s: ", prec, "MCE");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
	seq_printf(p, "  Machine check exceptions\n");
	seq_printf(p, "%*s: ", prec, "MCP");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
	seq_printf(p, "  Machine check polls\n");
#endif
	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
#if defined(CONFIG_X86_IO_APIC)
	seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
#endif
	return 0;
}

/*
 * /proc/stat helpers
 */
u64 arch_irq_stat_cpu(unsigned int cpu)
{
	u64 sum = irq_stats(cpu)->__nmi_count;

#ifdef CONFIG_X86_LOCAL_APIC
	sum += irq_stats(cpu)->apic_timer_irqs;
	sum += irq_stats(cpu)->irq_spurious_count;
	sum += irq_stats(cpu)->apic_perf_irqs;
	sum += irq_stats(cpu)->apic_irq_work_irqs;
	sum += irq_stats(cpu)->icr_read_retry_count;
#endif
	if (x86_platform_ipi_callback)
		sum += irq_stats(cpu)->x86_platform_ipis;
#ifdef CONFIG_SMP
	sum += irq_stats(cpu)->irq_resched_count;
	sum += irq_stats(cpu)->irq_call_count;
	sum += irq_stats(cpu)->irq_tlb_count;
#endif
#ifdef CONFIG_X86_THERMAL_VECTOR
	sum += irq_stats(cpu)->irq_thermal_count;
#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
	sum += irq_stats(cpu)->irq_threshold_count;
#endif
#ifdef CONFIG_X86_MCE
	sum += per_cpu(mce_exception_count, cpu);
	sum += per_cpu(mce_poll_count, cpu);
#endif
	return sum;
}

u64 arch_irq_stat(void)
{
	u64 sum = atomic_read(&irq_err_count);

#ifdef CONFIG_X86_IO_APIC
	sum += atomic_read(&irq_mis_count);
#endif
	return sum;
}


/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/* high bit used in ret_from_ code  */
	unsigned vector = ~regs->orig_ax;
	unsigned irq;

	irq_enter();
	exit_idle();

	irq = __this_cpu_read(vector_irq[vector]);

	if (!handle_irq(irq, regs)) {
		ack_APIC_irq();

		if (printk_ratelimit())
			pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
				__func__, smp_processor_id(), vector, irq);
	}

	irq_exit();

	set_irq_regs(old_regs);
	return 1;
}

/*
 * Handler for X86_PLATFORM_IPI_VECTOR.
 */
void smp_x86_platform_ipi(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	ack_APIC_irq();

	irq_enter();

	exit_idle();

	inc_irq_stat(x86_platform_ipis);

	if (x86_platform_ipi_callback)
		x86_platform_ipi_callback();

	irq_exit();

	set_irq_regs(old_regs);
}

EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);

#ifdef CONFIG_HOTPLUG_CPU
/* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
void fixup_irqs(void)
{
	unsigned int irq, vector;
	static int warned;
	struct irq_desc *desc;
	struct irq_data *data;
	struct irq_chip *chip;

	for_each_irq_desc(irq, desc) {
		int break_affinity = 0;
		int set_affinity = 1;
		const struct cpumask *affinity;

		if (!desc)
			continue;
		if (irq == 2)
			continue;

		/* interrupt's are disabled at this point */
		raw_spin_lock(&desc->lock);

		data = irq_desc_get_irq_data(desc);
		affinity = data->affinity;
		if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
		    cpumask_subset(affinity, cpu_online_mask)) {
			raw_spin_unlock(&desc->lock);
			continue;
		}

		/*
		 * Complete the irq move. This cpu is going down and for
		 * non intr-remapping case, we can't wait till this interrupt
		 * arrives at this cpu before completing the irq move.
		 */
		irq_force_complete_move(irq);

		if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
			break_affinity = 1;
			affinity = cpu_all_mask;
		}

		chip = irq_data_get_irq_chip(data);
		if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
			chip->irq_mask(data);

		if (chip->irq_set_affinity)
			chip->irq_set_affinity(data, affinity, true);
		else if (!(warned++))
			set_affinity = 0;

		/*
		 * We unmask if the irq was not marked masked by the
		 * core code. That respects the lazy irq disable
		 * behaviour.
		 */
		if (!irqd_can_move_in_process_context(data) &&
		    !irqd_irq_masked(data) && chip->irq_unmask)
			chip->irq_unmask(data);

		raw_spin_unlock(&desc->lock);

		if (break_affinity && set_affinity)
			pr_notice("Broke affinity for irq %i\n", irq);
		else if (!set_affinity)
			pr_notice("Cannot set affinity for irq %i\n", irq);
	}

	/*
	 * We can remove mdelay() and then send spuriuous interrupts to
	 * new cpu targets for all the irqs that were handled previously by
	 * this cpu. While it works, I have seen spurious interrupt messages
	 * (nothing wrong but still...).
	 *
	 * So for now, retain mdelay(1) and check the IRR and then send those
	 * interrupts to new targets as this cpu is already offlined...
	 */
	mdelay(1);

	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
		unsigned int irr;

		if (__this_cpu_read(vector_irq[vector]) < 0)
			continue;

		irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
		if (irr  & (1 << (vector % 32))) {
			irq = __this_cpu_read(vector_irq[vector]);

			desc = irq_to_desc(irq);
			data = irq_desc_get_irq_data(desc);
			chip = irq_data_get_irq_chip(data);
			raw_spin_lock(&desc->lock);
			if (chip->irq_retrigger)
				chip->irq_retrigger(data);
			raw_spin_unlock(&desc->lock);
		}
	}
}
#endif
Commit	Line	Data
	1	/*
	2	* Common interrupt code for 32 and 64 bit
	3	*/
	4	#include <linux/cpu.h>
	5	#include <linux/interrupt.h>
	6	#include <linux/kernel_stat.h>
	7	#include <linux/of.h>
	8	#include <linux/seq_file.h>
	9	#include <linux/smp.h>
	10	#include <linux/ftrace.h>
	11	#include <linux/delay.h>
	12	#include <linux/export.h>
	13
	14	#include <asm/apic.h>
	15	#include <asm/io_apic.h>
	16	#include <asm/irq.h>
	17	#include <asm/idle.h>
	18	#include <asm/mce.h>
	19	#include <asm/hw_irq.h>
	20
	21	atomic_t irq_err_count;
	22
	23	/* Function pointer for generic interrupt vector handling */
	24	void (*x86_platform_ipi_callback)(void) = NULL;
	25
	26	/*
	27	* 'what should we do if we get a hw irq event on an illegal vector'.
	28	* each architecture has to answer this themselves.
	29	*/
	30	void ack_bad_irq(unsigned int irq)
	31	{
	32	if (printk_ratelimit())
	33	pr_err("unexpected IRQ trap at vector %02x\n", irq);
	34
	35	/*
	36	* Currently unexpected vectors happen only on SMP and APIC.
	37	* We _must_ ack these because every local APIC has only N
	38	* irq slots per priority level, and a 'hanging, unacked' IRQ
	39	* holds up an irq slot - in excessive cases (when multiple
	40	* unexpected vectors occur) that might lock up the APIC
	41	* completely.
	42	* But only ack when the APIC is enabled -AK
	43	*/
	44	ack_APIC_irq();
	45	}
	46
	47	#define irq_stats(x) (&per_cpu(irq_stat, x))
	48	/*
	49	* /proc/interrupts printing for arch specific interrupts
	50	*/
	51	int arch_show_interrupts(struct seq_file *p, int prec)
	52	{
	53	int j;
	54
	55	seq_printf(p, "%*s: ", prec, "NMI");
	56	for_each_online_cpu(j)
	57	seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
	58	seq_printf(p, " Non-maskable interrupts\n");
	59	#ifdef CONFIG_X86_LOCAL_APIC
	60	seq_printf(p, "%*s: ", prec, "LOC");
	61	for_each_online_cpu(j)
	62	seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
	63	seq_printf(p, " Local timer interrupts\n");
	64
	65	seq_printf(p, "%*s: ", prec, "SPU");
	66	for_each_online_cpu(j)
	67	seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
	68	seq_printf(p, " Spurious interrupts\n");
	69	seq_printf(p, "%*s: ", prec, "PMI");
	70	for_each_online_cpu(j)
	71	seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
	72	seq_printf(p, " Performance monitoring interrupts\n");
	73	seq_printf(p, "%*s: ", prec, "IWI");
	74	for_each_online_cpu(j)
	75	seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
	76	seq_printf(p, " IRQ work interrupts\n");
	77	seq_printf(p, "%*s: ", prec, "RTR");
	78	for_each_online_cpu(j)
	79	seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
	80	seq_printf(p, " APIC ICR read retries\n");
	81	#endif
	82	if (x86_platform_ipi_callback) {
	83	seq_printf(p, "%*s: ", prec, "PLT");
	84	for_each_online_cpu(j)
	85	seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
	86	seq_printf(p, " Platform interrupts\n");
	87	}
	88	#ifdef CONFIG_SMP
	89	seq_printf(p, "%*s: ", prec, "RES");
	90	for_each_online_cpu(j)
	91	seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
	92	seq_printf(p, " Rescheduling interrupts\n");
	93	seq_printf(p, "%*s: ", prec, "CAL");
	94	for_each_online_cpu(j)
	95	seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
	96	seq_printf(p, " Function call interrupts\n");
	97	seq_printf(p, "%*s: ", prec, "TLB");
	98	for_each_online_cpu(j)
	99	seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
	100	seq_printf(p, " TLB shootdowns\n");
	101	#endif
	102	#ifdef CONFIG_X86_THERMAL_VECTOR
	103	seq_printf(p, "%*s: ", prec, "TRM");
	104	for_each_online_cpu(j)
	105	seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
	106	seq_printf(p, " Thermal event interrupts\n");
	107	#endif
	108	#ifdef CONFIG_X86_MCE_THRESHOLD
	109	seq_printf(p, "%*s: ", prec, "THR");
	110	for_each_online_cpu(j)
	111	seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
	112	seq_printf(p, " Threshold APIC interrupts\n");
	113	#endif
	114	#ifdef CONFIG_X86_MCE
	115	seq_printf(p, "%*s: ", prec, "MCE");
	116	for_each_online_cpu(j)
	117	seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
	118	seq_printf(p, " Machine check exceptions\n");
	119	seq_printf(p, "%*s: ", prec, "MCP");
	120	for_each_online_cpu(j)
	121	seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
	122	seq_printf(p, " Machine check polls\n");
	123	#endif
	124	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
	125	#if defined(CONFIG_X86_IO_APIC)
	126	seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
	127	#endif
	128	return 0;
	129	}
	130
	131	/*
	132	* /proc/stat helpers
	133	*/
	134	u64 arch_irq_stat_cpu(unsigned int cpu)
	135	{
	136	u64 sum = irq_stats(cpu)->__nmi_count;
	137
	138	#ifdef CONFIG_X86_LOCAL_APIC
	139	sum += irq_stats(cpu)->apic_timer_irqs;
	140	sum += irq_stats(cpu)->irq_spurious_count;
	141	sum += irq_stats(cpu)->apic_perf_irqs;
	142	sum += irq_stats(cpu)->apic_irq_work_irqs;
	143	sum += irq_stats(cpu)->icr_read_retry_count;
	144	#endif
	145	if (x86_platform_ipi_callback)
	146	sum += irq_stats(cpu)->x86_platform_ipis;
	147	#ifdef CONFIG_SMP
	148	sum += irq_stats(cpu)->irq_resched_count;
	149	sum += irq_stats(cpu)->irq_call_count;
	150	sum += irq_stats(cpu)->irq_tlb_count;
	151	#endif
	152	#ifdef CONFIG_X86_THERMAL_VECTOR
	153	sum += irq_stats(cpu)->irq_thermal_count;
	154	#endif
	155	#ifdef CONFIG_X86_MCE_THRESHOLD
	156	sum += irq_stats(cpu)->irq_threshold_count;
	157	#endif
	158	#ifdef CONFIG_X86_MCE
	159	sum += per_cpu(mce_exception_count, cpu);
	160	sum += per_cpu(mce_poll_count, cpu);
	161	#endif
	162	return sum;
	163	}
	164
	165	u64 arch_irq_stat(void)
	166	{
	167	u64 sum = atomic_read(&irq_err_count);
	168
	169	#ifdef CONFIG_X86_IO_APIC
	170	sum += atomic_read(&irq_mis_count);
	171	#endif
	172	return sum;
	173	}
	174
	175
	176	/*
	177	* do_IRQ handles all normal device IRQ's (the special
	178	* SMP cross-CPU interrupts have their own specific
	179	* handlers).
	180	*/
	181	unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
	182	{
	183	struct pt_regs *old_regs = set_irq_regs(regs);
	184
	185	/* high bit used in ret_from_ code */
	186	unsigned vector = ~regs->orig_ax;
	187	unsigned irq;
	188
	189	irq_enter();
	190	exit_idle();
	191
	192	irq = __this_cpu_read(vector_irq[vector]);
	193
	194	if (!handle_irq(irq, regs)) {
	195	ack_APIC_irq();
	196
	197	if (printk_ratelimit())
	198	pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
	199	__func__, smp_processor_id(), vector, irq);
	200	}
	201
	202	irq_exit();
	203
	204	set_irq_regs(old_regs);
	205	return 1;
	206	}
	207
	208	/*
	209	* Handler for X86_PLATFORM_IPI_VECTOR.
	210	*/
	211	void smp_x86_platform_ipi(struct pt_regs *regs)
	212	{
	213	struct pt_regs *old_regs = set_irq_regs(regs);
	214
	215	ack_APIC_irq();
	216
	217	irq_enter();
	218
	219	exit_idle();
	220
	221	inc_irq_stat(x86_platform_ipis);
	222
	223	if (x86_platform_ipi_callback)
	224	x86_platform_ipi_callback();
	225
	226	irq_exit();
	227
	228	set_irq_regs(old_regs);
	229	}
	230
	231	EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
	232
	233	#ifdef CONFIG_HOTPLUG_CPU
	234	/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
	235	void fixup_irqs(void)
	236	{
	237	unsigned int irq, vector;
	238	static int warned;
	239	struct irq_desc *desc;
	240	struct irq_data *data;
	241	struct irq_chip *chip;
	242
	243	for_each_irq_desc(irq, desc) {
	244	int break_affinity = 0;
	245	int set_affinity = 1;
	246	const struct cpumask *affinity;
	247
	248	if (!desc)
	249	continue;
	250	if (irq == 2)
	251	continue;
	252
	253	/* interrupt's are disabled at this point */
	254	raw_spin_lock(&desc->lock);
	255
	256	data = irq_desc_get_irq_data(desc);
	257	affinity = data->affinity;
	258	if (!irq_has_action(irq) \|\| irqd_is_per_cpu(data) \|\|
	259	cpumask_subset(affinity, cpu_online_mask)) {
	260	raw_spin_unlock(&desc->lock);
	261	continue;
	262	}
	263
	264	/*
	265	* Complete the irq move. This cpu is going down and for
	266	* non intr-remapping case, we can't wait till this interrupt
	267	* arrives at this cpu before completing the irq move.
	268	*/
	269	irq_force_complete_move(irq);
	270
	271	if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
	272	break_affinity = 1;
	273	affinity = cpu_all_mask;
	274	}
	275
	276	chip = irq_data_get_irq_chip(data);
	277	if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
	278	chip->irq_mask(data);
	279
	280	if (chip->irq_set_affinity)
	281	chip->irq_set_affinity(data, affinity, true);
	282	else if (!(warned++))
	283	set_affinity = 0;
	284
	285	/*
	286	* We unmask if the irq was not marked masked by the
	287	* core code. That respects the lazy irq disable
	288	* behaviour.
	289	*/
	290	if (!irqd_can_move_in_process_context(data) &&
	291	!irqd_irq_masked(data) && chip->irq_unmask)
	292	chip->irq_unmask(data);
	293
	294	raw_spin_unlock(&desc->lock);
	295
	296	if (break_affinity && set_affinity)
	297	pr_notice("Broke affinity for irq %i\n", irq);
	298	else if (!set_affinity)
	299	pr_notice("Cannot set affinity for irq %i\n", irq);
	300	}
	301
	302	/*
	303	* We can remove mdelay() and then send spuriuous interrupts to
	304	* new cpu targets for all the irqs that were handled previously by
	305	* this cpu. While it works, I have seen spurious interrupt messages
	306	* (nothing wrong but still...).
	307	*
	308	* So for now, retain mdelay(1) and check the IRR and then send those
	309	* interrupts to new targets as this cpu is already offlined...
	310	*/
	311	mdelay(1);
	312
	313	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
	314	unsigned int irr;
	315
	316	if (__this_cpu_read(vector_irq[vector]) < 0)
	317	continue;
	318
	319	irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
	320	if (irr & (1 << (vector % 32))) {
	321	irq = __this_cpu_read(vector_irq[vector]);
	322
	323	desc = irq_to_desc(irq);
	324	data = irq_desc_get_irq_data(desc);
	325	chip = irq_data_get_irq_chip(data);
	326	raw_spin_lock(&desc->lock);
	327	if (chip->irq_retrigger)
	328	chip->irq_retrigger(data);
	329	raw_spin_unlock(&desc->lock);
	330	}
	331	}
	332	}
	333	#endif