| 1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 2 | |
| 3 | #include <linux/errno.h> |
| 4 | #include <linux/kernel.h> |
| 5 | #include <linux/mm.h> |
| 6 | #include <linux/smp.h> |
| 7 | #include <linux/prctl.h> |
| 8 | #include <linux/slab.h> |
| 9 | #include <linux/sched.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/pm.h> |
| 12 | #include <linux/tick.h> |
| 13 | #include <linux/random.h> |
| 14 | #include <linux/user-return-notifier.h> |
| 15 | #include <linux/dmi.h> |
| 16 | #include <linux/utsname.h> |
| 17 | #include <linux/stackprotector.h> |
| 18 | #include <linux/tick.h> |
| 19 | #include <linux/cpuidle.h> |
| 20 | #include <trace/events/power.h> |
| 21 | #include <linux/hw_breakpoint.h> |
| 22 | #include <asm/cpu.h> |
| 23 | #include <asm/apic.h> |
| 24 | #include <asm/syscalls.h> |
| 25 | #include <asm/idle.h> |
| 26 | #include <asm/uaccess.h> |
| 27 | #include <asm/mwait.h> |
| 28 | #include <asm/fpu-internal.h> |
| 29 | #include <asm/debugreg.h> |
| 30 | #include <asm/nmi.h> |
| 31 | #include <asm/tlbflush.h> |
| 32 | |
| 33 | /* |
| 34 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, |
| 35 | * no more per-task TSS's. The TSS size is kept cacheline-aligned |
| 36 | * so they are allowed to end up in the .data..cacheline_aligned |
| 37 | * section. Since TSS's are completely CPU-local, we want them |
| 38 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. |
| 39 | */ |
| 40 | __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = { |
| 41 | .x86_tss = { |
| 42 | .sp0 = TOP_OF_INIT_STACK, |
| 43 | #ifdef CONFIG_X86_32 |
| 44 | .ss0 = __KERNEL_DS, |
| 45 | .ss1 = __KERNEL_CS, |
| 46 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, |
| 47 | #endif |
| 48 | }, |
| 49 | #ifdef CONFIG_X86_32 |
| 50 | /* |
| 51 | * Note that the .io_bitmap member must be extra-big. This is because |
| 52 | * the CPU will access an additional byte beyond the end of the IO |
| 53 | * permission bitmap. The extra byte must be all 1 bits, and must |
| 54 | * be within the limit. |
| 55 | */ |
| 56 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, |
| 57 | #endif |
| 58 | }; |
| 59 | EXPORT_PER_CPU_SYMBOL(cpu_tss); |
| 60 | |
| 61 | #ifdef CONFIG_X86_64 |
| 62 | static DEFINE_PER_CPU(unsigned char, is_idle); |
| 63 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); |
| 64 | |
| 65 | void idle_notifier_register(struct notifier_block *n) |
| 66 | { |
| 67 | atomic_notifier_chain_register(&idle_notifier, n); |
| 68 | } |
| 69 | EXPORT_SYMBOL_GPL(idle_notifier_register); |
| 70 | |
| 71 | void idle_notifier_unregister(struct notifier_block *n) |
| 72 | { |
| 73 | atomic_notifier_chain_unregister(&idle_notifier, n); |
| 74 | } |
| 75 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); |
| 76 | #endif |
| 77 | |
| 78 | /* |
| 79 | * this gets called so that we can store lazy state into memory and copy the |
| 80 | * current task into the new thread. |
| 81 | */ |
| 82 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
| 83 | { |
| 84 | *dst = *src; |
| 85 | |
| 86 | return fpu__copy(dst, src); |
| 87 | } |
| 88 | |
| 89 | void arch_release_task_struct(struct task_struct *tsk) |
| 90 | { |
| 91 | fpstate_free(&tsk->thread.fpu); |
| 92 | } |
| 93 | |
| 94 | void arch_task_cache_init(void) |
| 95 | { |
| 96 | fpstate_cache_init(); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * Free current thread data structures etc.. |
| 101 | */ |
| 102 | void exit_thread(void) |
| 103 | { |
| 104 | struct task_struct *me = current; |
| 105 | struct thread_struct *t = &me->thread; |
| 106 | unsigned long *bp = t->io_bitmap_ptr; |
| 107 | struct fpu *fpu = &t->fpu; |
| 108 | |
| 109 | if (bp) { |
| 110 | struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu()); |
| 111 | |
| 112 | t->io_bitmap_ptr = NULL; |
| 113 | clear_thread_flag(TIF_IO_BITMAP); |
| 114 | /* |
| 115 | * Careful, clear this in the TSS too: |
| 116 | */ |
| 117 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); |
| 118 | t->io_bitmap_max = 0; |
| 119 | put_cpu(); |
| 120 | kfree(bp); |
| 121 | } |
| 122 | |
| 123 | drop_fpu(fpu); |
| 124 | } |
| 125 | |
| 126 | void flush_thread(void) |
| 127 | { |
| 128 | struct task_struct *tsk = current; |
| 129 | |
| 130 | flush_ptrace_hw_breakpoint(tsk); |
| 131 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
| 132 | |
| 133 | fpu__flush_thread(tsk); |
| 134 | } |
| 135 | |
| 136 | static void hard_disable_TSC(void) |
| 137 | { |
| 138 | cr4_set_bits(X86_CR4_TSD); |
| 139 | } |
| 140 | |
| 141 | void disable_TSC(void) |
| 142 | { |
| 143 | preempt_disable(); |
| 144 | if (!test_and_set_thread_flag(TIF_NOTSC)) |
| 145 | /* |
| 146 | * Must flip the CPU state synchronously with |
| 147 | * TIF_NOTSC in the current running context. |
| 148 | */ |
| 149 | hard_disable_TSC(); |
| 150 | preempt_enable(); |
| 151 | } |
| 152 | |
| 153 | static void hard_enable_TSC(void) |
| 154 | { |
| 155 | cr4_clear_bits(X86_CR4_TSD); |
| 156 | } |
| 157 | |
| 158 | static void enable_TSC(void) |
| 159 | { |
| 160 | preempt_disable(); |
| 161 | if (test_and_clear_thread_flag(TIF_NOTSC)) |
| 162 | /* |
| 163 | * Must flip the CPU state synchronously with |
| 164 | * TIF_NOTSC in the current running context. |
| 165 | */ |
| 166 | hard_enable_TSC(); |
| 167 | preempt_enable(); |
| 168 | } |
| 169 | |
| 170 | int get_tsc_mode(unsigned long adr) |
| 171 | { |
| 172 | unsigned int val; |
| 173 | |
| 174 | if (test_thread_flag(TIF_NOTSC)) |
| 175 | val = PR_TSC_SIGSEGV; |
| 176 | else |
| 177 | val = PR_TSC_ENABLE; |
| 178 | |
| 179 | return put_user(val, (unsigned int __user *)adr); |
| 180 | } |
| 181 | |
| 182 | int set_tsc_mode(unsigned int val) |
| 183 | { |
| 184 | if (val == PR_TSC_SIGSEGV) |
| 185 | disable_TSC(); |
| 186 | else if (val == PR_TSC_ENABLE) |
| 187 | enable_TSC(); |
| 188 | else |
| 189 | return -EINVAL; |
| 190 | |
| 191 | return 0; |
| 192 | } |
| 193 | |
| 194 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, |
| 195 | struct tss_struct *tss) |
| 196 | { |
| 197 | struct thread_struct *prev, *next; |
| 198 | |
| 199 | prev = &prev_p->thread; |
| 200 | next = &next_p->thread; |
| 201 | |
| 202 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
| 203 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { |
| 204 | unsigned long debugctl = get_debugctlmsr(); |
| 205 | |
| 206 | debugctl &= ~DEBUGCTLMSR_BTF; |
| 207 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) |
| 208 | debugctl |= DEBUGCTLMSR_BTF; |
| 209 | |
| 210 | update_debugctlmsr(debugctl); |
| 211 | } |
| 212 | |
| 213 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
| 214 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { |
| 215 | /* prev and next are different */ |
| 216 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) |
| 217 | hard_disable_TSC(); |
| 218 | else |
| 219 | hard_enable_TSC(); |
| 220 | } |
| 221 | |
| 222 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { |
| 223 | /* |
| 224 | * Copy the relevant range of the IO bitmap. |
| 225 | * Normally this is 128 bytes or less: |
| 226 | */ |
| 227 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, |
| 228 | max(prev->io_bitmap_max, next->io_bitmap_max)); |
| 229 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { |
| 230 | /* |
| 231 | * Clear any possible leftover bits: |
| 232 | */ |
| 233 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); |
| 234 | } |
| 235 | propagate_user_return_notify(prev_p, next_p); |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * Idle related variables and functions |
| 240 | */ |
| 241 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
| 242 | EXPORT_SYMBOL(boot_option_idle_override); |
| 243 | |
| 244 | static void (*x86_idle)(void); |
| 245 | |
| 246 | #ifndef CONFIG_SMP |
| 247 | static inline void play_dead(void) |
| 248 | { |
| 249 | BUG(); |
| 250 | } |
| 251 | #endif |
| 252 | |
| 253 | #ifdef CONFIG_X86_64 |
| 254 | void enter_idle(void) |
| 255 | { |
| 256 | this_cpu_write(is_idle, 1); |
| 257 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
| 258 | } |
| 259 | |
| 260 | static void __exit_idle(void) |
| 261 | { |
| 262 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) |
| 263 | return; |
| 264 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); |
| 265 | } |
| 266 | |
| 267 | /* Called from interrupts to signify idle end */ |
| 268 | void exit_idle(void) |
| 269 | { |
| 270 | /* idle loop has pid 0 */ |
| 271 | if (current->pid) |
| 272 | return; |
| 273 | __exit_idle(); |
| 274 | } |
| 275 | #endif |
| 276 | |
| 277 | void arch_cpu_idle_enter(void) |
| 278 | { |
| 279 | local_touch_nmi(); |
| 280 | enter_idle(); |
| 281 | } |
| 282 | |
| 283 | void arch_cpu_idle_exit(void) |
| 284 | { |
| 285 | __exit_idle(); |
| 286 | } |
| 287 | |
| 288 | void arch_cpu_idle_dead(void) |
| 289 | { |
| 290 | play_dead(); |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * Called from the generic idle code. |
| 295 | */ |
| 296 | void arch_cpu_idle(void) |
| 297 | { |
| 298 | x86_idle(); |
| 299 | } |
| 300 | |
| 301 | /* |
| 302 | * We use this if we don't have any better idle routine.. |
| 303 | */ |
| 304 | void default_idle(void) |
| 305 | { |
| 306 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
| 307 | safe_halt(); |
| 308 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
| 309 | } |
| 310 | #ifdef CONFIG_APM_MODULE |
| 311 | EXPORT_SYMBOL(default_idle); |
| 312 | #endif |
| 313 | |
| 314 | #ifdef CONFIG_XEN |
| 315 | bool xen_set_default_idle(void) |
| 316 | { |
| 317 | bool ret = !!x86_idle; |
| 318 | |
| 319 | x86_idle = default_idle; |
| 320 | |
| 321 | return ret; |
| 322 | } |
| 323 | #endif |
| 324 | void stop_this_cpu(void *dummy) |
| 325 | { |
| 326 | local_irq_disable(); |
| 327 | /* |
| 328 | * Remove this CPU: |
| 329 | */ |
| 330 | set_cpu_online(smp_processor_id(), false); |
| 331 | disable_local_APIC(); |
| 332 | |
| 333 | for (;;) |
| 334 | halt(); |
| 335 | } |
| 336 | |
| 337 | bool amd_e400_c1e_detected; |
| 338 | EXPORT_SYMBOL(amd_e400_c1e_detected); |
| 339 | |
| 340 | static cpumask_var_t amd_e400_c1e_mask; |
| 341 | |
| 342 | void amd_e400_remove_cpu(int cpu) |
| 343 | { |
| 344 | if (amd_e400_c1e_mask != NULL) |
| 345 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); |
| 346 | } |
| 347 | |
| 348 | /* |
| 349 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
| 350 | * pending message MSR. If we detect C1E, then we handle it the same |
| 351 | * way as C3 power states (local apic timer and TSC stop) |
| 352 | */ |
| 353 | static void amd_e400_idle(void) |
| 354 | { |
| 355 | if (!amd_e400_c1e_detected) { |
| 356 | u32 lo, hi; |
| 357 | |
| 358 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); |
| 359 | |
| 360 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
| 361 | amd_e400_c1e_detected = true; |
| 362 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
| 363 | mark_tsc_unstable("TSC halt in AMD C1E"); |
| 364 | pr_info("System has AMD C1E enabled\n"); |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | if (amd_e400_c1e_detected) { |
| 369 | int cpu = smp_processor_id(); |
| 370 | |
| 371 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
| 372 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); |
| 373 | /* Force broadcast so ACPI can not interfere. */ |
| 374 | tick_broadcast_force(); |
| 375 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
| 376 | } |
| 377 | tick_broadcast_enter(); |
| 378 | |
| 379 | default_idle(); |
| 380 | |
| 381 | /* |
| 382 | * The switch back from broadcast mode needs to be |
| 383 | * called with interrupts disabled. |
| 384 | */ |
| 385 | local_irq_disable(); |
| 386 | tick_broadcast_exit(); |
| 387 | local_irq_enable(); |
| 388 | } else |
| 389 | default_idle(); |
| 390 | } |
| 391 | |
| 392 | /* |
| 393 | * Intel Core2 and older machines prefer MWAIT over HALT for C1. |
| 394 | * We can't rely on cpuidle installing MWAIT, because it will not load |
| 395 | * on systems that support only C1 -- so the boot default must be MWAIT. |
| 396 | * |
| 397 | * Some AMD machines are the opposite, they depend on using HALT. |
| 398 | * |
| 399 | * So for default C1, which is used during boot until cpuidle loads, |
| 400 | * use MWAIT-C1 on Intel HW that has it, else use HALT. |
| 401 | */ |
| 402 | static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) |
| 403 | { |
| 404 | if (c->x86_vendor != X86_VENDOR_INTEL) |
| 405 | return 0; |
| 406 | |
| 407 | if (!cpu_has(c, X86_FEATURE_MWAIT)) |
| 408 | return 0; |
| 409 | |
| 410 | return 1; |
| 411 | } |
| 412 | |
| 413 | /* |
| 414 | * MONITOR/MWAIT with no hints, used for default default C1 state. |
| 415 | * This invokes MWAIT with interrutps enabled and no flags, |
| 416 | * which is backwards compatible with the original MWAIT implementation. |
| 417 | */ |
| 418 | |
| 419 | static void mwait_idle(void) |
| 420 | { |
| 421 | if (!current_set_polling_and_test()) { |
| 422 | if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { |
| 423 | smp_mb(); /* quirk */ |
| 424 | clflush((void *)¤t_thread_info()->flags); |
| 425 | smp_mb(); /* quirk */ |
| 426 | } |
| 427 | |
| 428 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
| 429 | if (!need_resched()) |
| 430 | __sti_mwait(0, 0); |
| 431 | else |
| 432 | local_irq_enable(); |
| 433 | } else { |
| 434 | local_irq_enable(); |
| 435 | } |
| 436 | __current_clr_polling(); |
| 437 | } |
| 438 | |
| 439 | void select_idle_routine(const struct cpuinfo_x86 *c) |
| 440 | { |
| 441 | #ifdef CONFIG_SMP |
| 442 | if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1) |
| 443 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
| 444 | #endif |
| 445 | if (x86_idle || boot_option_idle_override == IDLE_POLL) |
| 446 | return; |
| 447 | |
| 448 | if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) { |
| 449 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
| 450 | pr_info("using AMD E400 aware idle routine\n"); |
| 451 | x86_idle = amd_e400_idle; |
| 452 | } else if (prefer_mwait_c1_over_halt(c)) { |
| 453 | pr_info("using mwait in idle threads\n"); |
| 454 | x86_idle = mwait_idle; |
| 455 | } else |
| 456 | x86_idle = default_idle; |
| 457 | } |
| 458 | |
| 459 | void __init init_amd_e400_c1e_mask(void) |
| 460 | { |
| 461 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
| 462 | if (x86_idle == amd_e400_idle) |
| 463 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); |
| 464 | } |
| 465 | |
| 466 | static int __init idle_setup(char *str) |
| 467 | { |
| 468 | if (!str) |
| 469 | return -EINVAL; |
| 470 | |
| 471 | if (!strcmp(str, "poll")) { |
| 472 | pr_info("using polling idle threads\n"); |
| 473 | boot_option_idle_override = IDLE_POLL; |
| 474 | cpu_idle_poll_ctrl(true); |
| 475 | } else if (!strcmp(str, "halt")) { |
| 476 | /* |
| 477 | * When the boot option of idle=halt is added, halt is |
| 478 | * forced to be used for CPU idle. In such case CPU C2/C3 |
| 479 | * won't be used again. |
| 480 | * To continue to load the CPU idle driver, don't touch |
| 481 | * the boot_option_idle_override. |
| 482 | */ |
| 483 | x86_idle = default_idle; |
| 484 | boot_option_idle_override = IDLE_HALT; |
| 485 | } else if (!strcmp(str, "nomwait")) { |
| 486 | /* |
| 487 | * If the boot option of "idle=nomwait" is added, |
| 488 | * it means that mwait will be disabled for CPU C2/C3 |
| 489 | * states. In such case it won't touch the variable |
| 490 | * of boot_option_idle_override. |
| 491 | */ |
| 492 | boot_option_idle_override = IDLE_NOMWAIT; |
| 493 | } else |
| 494 | return -1; |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | early_param("idle", idle_setup); |
| 499 | |
| 500 | unsigned long arch_align_stack(unsigned long sp) |
| 501 | { |
| 502 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) |
| 503 | sp -= get_random_int() % 8192; |
| 504 | return sp & ~0xf; |
| 505 | } |
| 506 | |
| 507 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
| 508 | { |
| 509 | unsigned long range_end = mm->brk + 0x02000000; |
| 510 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; |
| 511 | } |
| 512 | |