| 1 | /* |
| 2 | * x86 SMP booting functions |
| 3 | * |
| 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
| 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
| 6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
| 7 | * |
| 8 | * Much of the core SMP work is based on previous work by Thomas Radke, to |
| 9 | * whom a great many thanks are extended. |
| 10 | * |
| 11 | * Thanks to Intel for making available several different Pentium, |
| 12 | * Pentium Pro and Pentium-II/Xeon MP machines. |
| 13 | * Original development of Linux SMP code supported by Caldera. |
| 14 | * |
| 15 | * This code is released under the GNU General Public License version 2 or |
| 16 | * later. |
| 17 | * |
| 18 | * Fixes |
| 19 | * Felix Koop : NR_CPUS used properly |
| 20 | * Jose Renau : Handle single CPU case. |
| 21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. |
| 22 | * Greg Wright : Fix for kernel stacks panic. |
| 23 | * Erich Boleyn : MP v1.4 and additional changes. |
| 24 | * Matthias Sattler : Changes for 2.1 kernel map. |
| 25 | * Michel Lespinasse : Changes for 2.1 kernel map. |
| 26 | * Michael Chastain : Change trampoline.S to gnu as. |
| 27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine |
| 28 | * Ingo Molnar : Added APIC timers, based on code |
| 29 | * from Jose Renau |
| 30 | * Ingo Molnar : various cleanups and rewrites |
| 31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. |
| 32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs |
| 33 | * Andi Kleen : Changed for SMP boot into long mode. |
| 34 | * Martin J. Bligh : Added support for multi-quad systems |
| 35 | * Dave Jones : Report invalid combinations of Athlon CPUs. |
| 36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
| 37 | * Andi Kleen : Converted to new state machine. |
| 38 | * Ashok Raj : CPU hotplug support |
| 39 | * Glauber Costa : i386 and x86_64 integration |
| 40 | */ |
| 41 | |
| 42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 43 | |
| 44 | #include <linux/init.h> |
| 45 | #include <linux/smp.h> |
| 46 | #include <linux/module.h> |
| 47 | #include <linux/sched.h> |
| 48 | #include <linux/percpu.h> |
| 49 | #include <linux/bootmem.h> |
| 50 | #include <linux/err.h> |
| 51 | #include <linux/nmi.h> |
| 52 | #include <linux/tboot.h> |
| 53 | #include <linux/stackprotector.h> |
| 54 | #include <linux/gfp.h> |
| 55 | #include <linux/cpuidle.h> |
| 56 | |
| 57 | #include <asm/acpi.h> |
| 58 | #include <asm/desc.h> |
| 59 | #include <asm/nmi.h> |
| 60 | #include <asm/irq.h> |
| 61 | #include <asm/idle.h> |
| 62 | #include <asm/realmode.h> |
| 63 | #include <asm/cpu.h> |
| 64 | #include <asm/numa.h> |
| 65 | #include <asm/pgtable.h> |
| 66 | #include <asm/tlbflush.h> |
| 67 | #include <asm/mtrr.h> |
| 68 | #include <asm/mwait.h> |
| 69 | #include <asm/apic.h> |
| 70 | #include <asm/io_apic.h> |
| 71 | #include <asm/setup.h> |
| 72 | #include <asm/uv/uv.h> |
| 73 | #include <linux/mc146818rtc.h> |
| 74 | |
| 75 | #include <asm/smpboot_hooks.h> |
| 76 | #include <asm/i8259.h> |
| 77 | |
| 78 | #include <asm/realmode.h> |
| 79 | |
| 80 | /* State of each CPU */ |
| 81 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; |
| 82 | |
| 83 | #ifdef CONFIG_HOTPLUG_CPU |
| 84 | /* |
| 85 | * We need this for trampoline_base protection from concurrent accesses when |
| 86 | * off- and onlining cores wildly. |
| 87 | */ |
| 88 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); |
| 89 | |
| 90 | void cpu_hotplug_driver_lock(void) |
| 91 | { |
| 92 | mutex_lock(&x86_cpu_hotplug_driver_mutex); |
| 93 | } |
| 94 | |
| 95 | void cpu_hotplug_driver_unlock(void) |
| 96 | { |
| 97 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); |
| 98 | } |
| 99 | |
| 100 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } |
| 101 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } |
| 102 | #endif |
| 103 | |
| 104 | /* Number of siblings per CPU package */ |
| 105 | int smp_num_siblings = 1; |
| 106 | EXPORT_SYMBOL(smp_num_siblings); |
| 107 | |
| 108 | /* Last level cache ID of each logical CPU */ |
| 109 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
| 110 | |
| 111 | /* representing HT siblings of each logical CPU */ |
| 112 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
| 113 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
| 114 | |
| 115 | /* representing HT and core siblings of each logical CPU */ |
| 116 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
| 117 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
| 118 | |
| 119 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
| 120 | |
| 121 | /* Per CPU bogomips and other parameters */ |
| 122 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); |
| 123 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
| 124 | |
| 125 | atomic_t init_deasserted; |
| 126 | |
| 127 | /* |
| 128 | * Report back to the Boot Processor during boot time or to the caller processor |
| 129 | * during CPU online. |
| 130 | */ |
| 131 | static void __cpuinit smp_callin(void) |
| 132 | { |
| 133 | int cpuid, phys_id; |
| 134 | unsigned long timeout; |
| 135 | |
| 136 | /* |
| 137 | * If waken up by an INIT in an 82489DX configuration |
| 138 | * we may get here before an INIT-deassert IPI reaches |
| 139 | * our local APIC. We have to wait for the IPI or we'll |
| 140 | * lock up on an APIC access. |
| 141 | */ |
| 142 | if (apic->wait_for_init_deassert) |
| 143 | apic->wait_for_init_deassert(&init_deasserted); |
| 144 | |
| 145 | /* |
| 146 | * (This works even if the APIC is not enabled.) |
| 147 | */ |
| 148 | phys_id = read_apic_id(); |
| 149 | cpuid = smp_processor_id(); |
| 150 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
| 151 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
| 152 | phys_id, cpuid); |
| 153 | } |
| 154 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
| 155 | |
| 156 | /* |
| 157 | * STARTUP IPIs are fragile beasts as they might sometimes |
| 158 | * trigger some glue motherboard logic. Complete APIC bus |
| 159 | * silence for 1 second, this overestimates the time the |
| 160 | * boot CPU is spending to send the up to 2 STARTUP IPIs |
| 161 | * by a factor of two. This should be enough. |
| 162 | */ |
| 163 | |
| 164 | /* |
| 165 | * Waiting 2s total for startup (udelay is not yet working) |
| 166 | */ |
| 167 | timeout = jiffies + 2*HZ; |
| 168 | while (time_before(jiffies, timeout)) { |
| 169 | /* |
| 170 | * Has the boot CPU finished it's STARTUP sequence? |
| 171 | */ |
| 172 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
| 173 | break; |
| 174 | cpu_relax(); |
| 175 | } |
| 176 | |
| 177 | if (!time_before(jiffies, timeout)) { |
| 178 | panic("%s: CPU%d started up but did not get a callout!\n", |
| 179 | __func__, cpuid); |
| 180 | } |
| 181 | |
| 182 | /* |
| 183 | * the boot CPU has finished the init stage and is spinning |
| 184 | * on callin_map until we finish. We are free to set up this |
| 185 | * CPU, first the APIC. (this is probably redundant on most |
| 186 | * boards) |
| 187 | */ |
| 188 | |
| 189 | pr_debug("CALLIN, before setup_local_APIC()\n"); |
| 190 | if (apic->smp_callin_clear_local_apic) |
| 191 | apic->smp_callin_clear_local_apic(); |
| 192 | setup_local_APIC(); |
| 193 | end_local_APIC_setup(); |
| 194 | |
| 195 | /* |
| 196 | * Need to setup vector mappings before we enable interrupts. |
| 197 | */ |
| 198 | setup_vector_irq(smp_processor_id()); |
| 199 | |
| 200 | /* |
| 201 | * Save our processor parameters. Note: this information |
| 202 | * is needed for clock calibration. |
| 203 | */ |
| 204 | smp_store_cpu_info(cpuid); |
| 205 | |
| 206 | /* |
| 207 | * Get our bogomips. |
| 208 | * Update loops_per_jiffy in cpu_data. Previous call to |
| 209 | * smp_store_cpu_info() stored a value that is close but not as |
| 210 | * accurate as the value just calculated. |
| 211 | */ |
| 212 | calibrate_delay(); |
| 213 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
| 214 | pr_debug("Stack at about %p\n", &cpuid); |
| 215 | |
| 216 | /* |
| 217 | * This must be done before setting cpu_online_mask |
| 218 | * or calling notify_cpu_starting. |
| 219 | */ |
| 220 | set_cpu_sibling_map(raw_smp_processor_id()); |
| 221 | wmb(); |
| 222 | |
| 223 | notify_cpu_starting(cpuid); |
| 224 | |
| 225 | /* |
| 226 | * Allow the master to continue. |
| 227 | */ |
| 228 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * Activate a secondary processor. |
| 233 | */ |
| 234 | notrace static void __cpuinit start_secondary(void *unused) |
| 235 | { |
| 236 | /* |
| 237 | * Don't put *anything* before cpu_init(), SMP booting is too |
| 238 | * fragile that we want to limit the things done here to the |
| 239 | * most necessary things. |
| 240 | */ |
| 241 | cpu_init(); |
| 242 | x86_cpuinit.early_percpu_clock_init(); |
| 243 | preempt_disable(); |
| 244 | smp_callin(); |
| 245 | |
| 246 | #ifdef CONFIG_X86_32 |
| 247 | /* switch away from the initial page table */ |
| 248 | load_cr3(swapper_pg_dir); |
| 249 | __flush_tlb_all(); |
| 250 | #endif |
| 251 | |
| 252 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
| 253 | barrier(); |
| 254 | /* |
| 255 | * Check TSC synchronization with the BP: |
| 256 | */ |
| 257 | check_tsc_sync_target(); |
| 258 | |
| 259 | /* |
| 260 | * We need to hold vector_lock so there the set of online cpus |
| 261 | * does not change while we are assigning vectors to cpus. Holding |
| 262 | * this lock ensures we don't half assign or remove an irq from a cpu. |
| 263 | */ |
| 264 | lock_vector_lock(); |
| 265 | set_cpu_online(smp_processor_id(), true); |
| 266 | unlock_vector_lock(); |
| 267 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
| 268 | x86_platform.nmi_init(); |
| 269 | |
| 270 | /* enable local interrupts */ |
| 271 | local_irq_enable(); |
| 272 | |
| 273 | /* to prevent fake stack check failure in clock setup */ |
| 274 | boot_init_stack_canary(); |
| 275 | |
| 276 | x86_cpuinit.setup_percpu_clockev(); |
| 277 | |
| 278 | wmb(); |
| 279 | cpu_idle(); |
| 280 | } |
| 281 | |
| 282 | void __init smp_store_boot_cpu_info(void) |
| 283 | { |
| 284 | int id = 0; /* CPU 0 */ |
| 285 | struct cpuinfo_x86 *c = &cpu_data(id); |
| 286 | |
| 287 | *c = boot_cpu_data; |
| 288 | c->cpu_index = id; |
| 289 | } |
| 290 | |
| 291 | /* |
| 292 | * The bootstrap kernel entry code has set these up. Save them for |
| 293 | * a given CPU |
| 294 | */ |
| 295 | void __cpuinit smp_store_cpu_info(int id) |
| 296 | { |
| 297 | struct cpuinfo_x86 *c = &cpu_data(id); |
| 298 | |
| 299 | *c = boot_cpu_data; |
| 300 | c->cpu_index = id; |
| 301 | /* |
| 302 | * During boot time, CPU0 has this setup already. Save the info when |
| 303 | * bringing up AP or offlined CPU0. |
| 304 | */ |
| 305 | identify_secondary_cpu(c); |
| 306 | } |
| 307 | |
| 308 | static bool __cpuinit |
| 309 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
| 310 | { |
| 311 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 312 | |
| 313 | return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), |
| 314 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
| 315 | "[node: %d != %d]. Ignoring dependency.\n", |
| 316 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); |
| 317 | } |
| 318 | |
| 319 | #define link_mask(_m, c1, c2) \ |
| 320 | do { \ |
| 321 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ |
| 322 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ |
| 323 | } while (0) |
| 324 | |
| 325 | static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 326 | { |
| 327 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
| 328 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 329 | |
| 330 | if (c->phys_proc_id == o->phys_proc_id && |
| 331 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && |
| 332 | c->compute_unit_id == o->compute_unit_id) |
| 333 | return topology_sane(c, o, "smt"); |
| 334 | |
| 335 | } else if (c->phys_proc_id == o->phys_proc_id && |
| 336 | c->cpu_core_id == o->cpu_core_id) { |
| 337 | return topology_sane(c, o, "smt"); |
| 338 | } |
| 339 | |
| 340 | return false; |
| 341 | } |
| 342 | |
| 343 | static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 344 | { |
| 345 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
| 346 | |
| 347 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && |
| 348 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) |
| 349 | return topology_sane(c, o, "llc"); |
| 350 | |
| 351 | return false; |
| 352 | } |
| 353 | |
| 354 | static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
| 355 | { |
| 356 | if (c->phys_proc_id == o->phys_proc_id) { |
| 357 | if (cpu_has(c, X86_FEATURE_AMD_DCM)) |
| 358 | return true; |
| 359 | |
| 360 | return topology_sane(c, o, "mc"); |
| 361 | } |
| 362 | return false; |
| 363 | } |
| 364 | |
| 365 | void __cpuinit set_cpu_sibling_map(int cpu) |
| 366 | { |
| 367 | bool has_mc = boot_cpu_data.x86_max_cores > 1; |
| 368 | bool has_smt = smp_num_siblings > 1; |
| 369 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
| 370 | struct cpuinfo_x86 *o; |
| 371 | int i; |
| 372 | |
| 373 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
| 374 | |
| 375 | if (!has_smt && !has_mc) { |
| 376 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
| 377 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
| 378 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); |
| 379 | c->booted_cores = 1; |
| 380 | return; |
| 381 | } |
| 382 | |
| 383 | for_each_cpu(i, cpu_sibling_setup_mask) { |
| 384 | o = &cpu_data(i); |
| 385 | |
| 386 | if ((i == cpu) || (has_smt && match_smt(c, o))) |
| 387 | link_mask(sibling, cpu, i); |
| 388 | |
| 389 | if ((i == cpu) || (has_mc && match_llc(c, o))) |
| 390 | link_mask(llc_shared, cpu, i); |
| 391 | |
| 392 | } |
| 393 | |
| 394 | /* |
| 395 | * This needs a separate iteration over the cpus because we rely on all |
| 396 | * cpu_sibling_mask links to be set-up. |
| 397 | */ |
| 398 | for_each_cpu(i, cpu_sibling_setup_mask) { |
| 399 | o = &cpu_data(i); |
| 400 | |
| 401 | if ((i == cpu) || (has_mc && match_mc(c, o))) { |
| 402 | link_mask(core, cpu, i); |
| 403 | |
| 404 | /* |
| 405 | * Does this new cpu bringup a new core? |
| 406 | */ |
| 407 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
| 408 | /* |
| 409 | * for each core in package, increment |
| 410 | * the booted_cores for this new cpu |
| 411 | */ |
| 412 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
| 413 | c->booted_cores++; |
| 414 | /* |
| 415 | * increment the core count for all |
| 416 | * the other cpus in this package |
| 417 | */ |
| 418 | if (i != cpu) |
| 419 | cpu_data(i).booted_cores++; |
| 420 | } else if (i != cpu && !c->booted_cores) |
| 421 | c->booted_cores = cpu_data(i).booted_cores; |
| 422 | } |
| 423 | } |
| 424 | } |
| 425 | |
| 426 | /* maps the cpu to the sched domain representing multi-core */ |
| 427 | const struct cpumask *cpu_coregroup_mask(int cpu) |
| 428 | { |
| 429 | return cpu_llc_shared_mask(cpu); |
| 430 | } |
| 431 | |
| 432 | static void impress_friends(void) |
| 433 | { |
| 434 | int cpu; |
| 435 | unsigned long bogosum = 0; |
| 436 | /* |
| 437 | * Allow the user to impress friends. |
| 438 | */ |
| 439 | pr_debug("Before bogomips\n"); |
| 440 | for_each_possible_cpu(cpu) |
| 441 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
| 442 | bogosum += cpu_data(cpu).loops_per_jiffy; |
| 443 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
| 444 | num_online_cpus(), |
| 445 | bogosum/(500000/HZ), |
| 446 | (bogosum/(5000/HZ))%100); |
| 447 | |
| 448 | pr_debug("Before bogocount - setting activated=1\n"); |
| 449 | } |
| 450 | |
| 451 | void __inquire_remote_apic(int apicid) |
| 452 | { |
| 453 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; |
| 454 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
| 455 | int timeout; |
| 456 | u32 status; |
| 457 | |
| 458 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
| 459 | |
| 460 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
| 461 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
| 462 | |
| 463 | /* |
| 464 | * Wait for idle. |
| 465 | */ |
| 466 | status = safe_apic_wait_icr_idle(); |
| 467 | if (status) |
| 468 | pr_cont("a previous APIC delivery may have failed\n"); |
| 469 | |
| 470 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
| 471 | |
| 472 | timeout = 0; |
| 473 | do { |
| 474 | udelay(100); |
| 475 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; |
| 476 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); |
| 477 | |
| 478 | switch (status) { |
| 479 | case APIC_ICR_RR_VALID: |
| 480 | status = apic_read(APIC_RRR); |
| 481 | pr_cont("%08x\n", status); |
| 482 | break; |
| 483 | default: |
| 484 | pr_cont("failed\n"); |
| 485 | } |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | /* |
| 490 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal |
| 491 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this |
| 492 | * won't ... remember to clear down the APIC, etc later. |
| 493 | */ |
| 494 | int __cpuinit |
| 495 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
| 496 | { |
| 497 | unsigned long send_status, accept_status = 0; |
| 498 | int maxlvt; |
| 499 | |
| 500 | /* Target chip */ |
| 501 | /* Boot on the stack */ |
| 502 | /* Kick the second */ |
| 503 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
| 504 | |
| 505 | pr_debug("Waiting for send to finish...\n"); |
| 506 | send_status = safe_apic_wait_icr_idle(); |
| 507 | |
| 508 | /* |
| 509 | * Give the other CPU some time to accept the IPI. |
| 510 | */ |
| 511 | udelay(200); |
| 512 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 513 | maxlvt = lapic_get_maxlvt(); |
| 514 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 515 | apic_write(APIC_ESR, 0); |
| 516 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
| 517 | } |
| 518 | pr_debug("NMI sent\n"); |
| 519 | |
| 520 | if (send_status) |
| 521 | pr_err("APIC never delivered???\n"); |
| 522 | if (accept_status) |
| 523 | pr_err("APIC delivery error (%lx)\n", accept_status); |
| 524 | |
| 525 | return (send_status | accept_status); |
| 526 | } |
| 527 | |
| 528 | static int __cpuinit |
| 529 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
| 530 | { |
| 531 | unsigned long send_status, accept_status = 0; |
| 532 | int maxlvt, num_starts, j; |
| 533 | |
| 534 | maxlvt = lapic_get_maxlvt(); |
| 535 | |
| 536 | /* |
| 537 | * Be paranoid about clearing APIC errors. |
| 538 | */ |
| 539 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { |
| 540 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 541 | apic_write(APIC_ESR, 0); |
| 542 | apic_read(APIC_ESR); |
| 543 | } |
| 544 | |
| 545 | pr_debug("Asserting INIT\n"); |
| 546 | |
| 547 | /* |
| 548 | * Turn INIT on target chip |
| 549 | */ |
| 550 | /* |
| 551 | * Send IPI |
| 552 | */ |
| 553 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
| 554 | phys_apicid); |
| 555 | |
| 556 | pr_debug("Waiting for send to finish...\n"); |
| 557 | send_status = safe_apic_wait_icr_idle(); |
| 558 | |
| 559 | mdelay(10); |
| 560 | |
| 561 | pr_debug("Deasserting INIT\n"); |
| 562 | |
| 563 | /* Target chip */ |
| 564 | /* Send IPI */ |
| 565 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
| 566 | |
| 567 | pr_debug("Waiting for send to finish...\n"); |
| 568 | send_status = safe_apic_wait_icr_idle(); |
| 569 | |
| 570 | mb(); |
| 571 | atomic_set(&init_deasserted, 1); |
| 572 | |
| 573 | /* |
| 574 | * Should we send STARTUP IPIs ? |
| 575 | * |
| 576 | * Determine this based on the APIC version. |
| 577 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. |
| 578 | */ |
| 579 | if (APIC_INTEGRATED(apic_version[phys_apicid])) |
| 580 | num_starts = 2; |
| 581 | else |
| 582 | num_starts = 0; |
| 583 | |
| 584 | /* |
| 585 | * Paravirt / VMI wants a startup IPI hook here to set up the |
| 586 | * target processor state. |
| 587 | */ |
| 588 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, |
| 589 | stack_start); |
| 590 | |
| 591 | /* |
| 592 | * Run STARTUP IPI loop. |
| 593 | */ |
| 594 | pr_debug("#startup loops: %d\n", num_starts); |
| 595 | |
| 596 | for (j = 1; j <= num_starts; j++) { |
| 597 | pr_debug("Sending STARTUP #%d\n", j); |
| 598 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 599 | apic_write(APIC_ESR, 0); |
| 600 | apic_read(APIC_ESR); |
| 601 | pr_debug("After apic_write\n"); |
| 602 | |
| 603 | /* |
| 604 | * STARTUP IPI |
| 605 | */ |
| 606 | |
| 607 | /* Target chip */ |
| 608 | /* Boot on the stack */ |
| 609 | /* Kick the second */ |
| 610 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
| 611 | phys_apicid); |
| 612 | |
| 613 | /* |
| 614 | * Give the other CPU some time to accept the IPI. |
| 615 | */ |
| 616 | udelay(300); |
| 617 | |
| 618 | pr_debug("Startup point 1\n"); |
| 619 | |
| 620 | pr_debug("Waiting for send to finish...\n"); |
| 621 | send_status = safe_apic_wait_icr_idle(); |
| 622 | |
| 623 | /* |
| 624 | * Give the other CPU some time to accept the IPI. |
| 625 | */ |
| 626 | udelay(200); |
| 627 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 628 | apic_write(APIC_ESR, 0); |
| 629 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
| 630 | if (send_status || accept_status) |
| 631 | break; |
| 632 | } |
| 633 | pr_debug("After Startup\n"); |
| 634 | |
| 635 | if (send_status) |
| 636 | pr_err("APIC never delivered???\n"); |
| 637 | if (accept_status) |
| 638 | pr_err("APIC delivery error (%lx)\n", accept_status); |
| 639 | |
| 640 | return (send_status | accept_status); |
| 641 | } |
| 642 | |
| 643 | /* reduce the number of lines printed when booting a large cpu count system */ |
| 644 | static void __cpuinit announce_cpu(int cpu, int apicid) |
| 645 | { |
| 646 | static int current_node = -1; |
| 647 | int node = early_cpu_to_node(cpu); |
| 648 | |
| 649 | if (system_state == SYSTEM_BOOTING) { |
| 650 | if (node != current_node) { |
| 651 | if (current_node > (-1)) |
| 652 | pr_cont(" OK\n"); |
| 653 | current_node = node; |
| 654 | pr_info("Booting Node %3d, Processors ", node); |
| 655 | } |
| 656 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : ""); |
| 657 | return; |
| 658 | } else |
| 659 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", |
| 660 | node, cpu, apicid); |
| 661 | } |
| 662 | |
| 663 | /* |
| 664 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad |
| 665 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. |
| 666 | * Returns zero if CPU booted OK, else error code from |
| 667 | * ->wakeup_secondary_cpu. |
| 668 | */ |
| 669 | static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
| 670 | { |
| 671 | volatile u32 *trampoline_status = |
| 672 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
| 673 | /* start_ip had better be page-aligned! */ |
| 674 | unsigned long start_ip = real_mode_header->trampoline_start; |
| 675 | |
| 676 | unsigned long boot_error = 0; |
| 677 | int timeout; |
| 678 | |
| 679 | /* Just in case we booted with a single CPU. */ |
| 680 | alternatives_enable_smp(); |
| 681 | |
| 682 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
| 683 | (THREAD_SIZE + task_stack_page(idle))) - 1); |
| 684 | per_cpu(current_task, cpu) = idle; |
| 685 | |
| 686 | #ifdef CONFIG_X86_32 |
| 687 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
| 688 | irq_ctx_init(cpu); |
| 689 | #else |
| 690 | clear_tsk_thread_flag(idle, TIF_FORK); |
| 691 | initial_gs = per_cpu_offset(cpu); |
| 692 | per_cpu(kernel_stack, cpu) = |
| 693 | (unsigned long)task_stack_page(idle) - |
| 694 | KERNEL_STACK_OFFSET + THREAD_SIZE; |
| 695 | #endif |
| 696 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
| 697 | initial_code = (unsigned long)start_secondary; |
| 698 | stack_start = idle->thread.sp; |
| 699 | |
| 700 | /* So we see what's up */ |
| 701 | announce_cpu(cpu, apicid); |
| 702 | |
| 703 | /* |
| 704 | * This grunge runs the startup process for |
| 705 | * the targeted processor. |
| 706 | */ |
| 707 | |
| 708 | atomic_set(&init_deasserted, 0); |
| 709 | |
| 710 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
| 711 | |
| 712 | pr_debug("Setting warm reset code and vector.\n"); |
| 713 | |
| 714 | smpboot_setup_warm_reset_vector(start_ip); |
| 715 | /* |
| 716 | * Be paranoid about clearing APIC errors. |
| 717 | */ |
| 718 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 719 | apic_write(APIC_ESR, 0); |
| 720 | apic_read(APIC_ESR); |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | /* |
| 725 | * Kick the secondary CPU. Use the method in the APIC driver |
| 726 | * if it's defined - or use an INIT boot APIC message otherwise: |
| 727 | */ |
| 728 | if (apic->wakeup_secondary_cpu) |
| 729 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); |
| 730 | else |
| 731 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); |
| 732 | |
| 733 | if (!boot_error) { |
| 734 | /* |
| 735 | * allow APs to start initializing. |
| 736 | */ |
| 737 | pr_debug("Before Callout %d\n", cpu); |
| 738 | cpumask_set_cpu(cpu, cpu_callout_mask); |
| 739 | pr_debug("After Callout %d\n", cpu); |
| 740 | |
| 741 | /* |
| 742 | * Wait 5s total for a response |
| 743 | */ |
| 744 | for (timeout = 0; timeout < 50000; timeout++) { |
| 745 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
| 746 | break; /* It has booted */ |
| 747 | udelay(100); |
| 748 | /* |
| 749 | * Allow other tasks to run while we wait for the |
| 750 | * AP to come online. This also gives a chance |
| 751 | * for the MTRR work(triggered by the AP coming online) |
| 752 | * to be completed in the stop machine context. |
| 753 | */ |
| 754 | schedule(); |
| 755 | } |
| 756 | |
| 757 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
| 758 | print_cpu_msr(&cpu_data(cpu)); |
| 759 | pr_debug("CPU%d: has booted.\n", cpu); |
| 760 | } else { |
| 761 | boot_error = 1; |
| 762 | if (*trampoline_status == 0xA5A5A5A5) |
| 763 | /* trampoline started but...? */ |
| 764 | pr_err("CPU%d: Stuck ??\n", cpu); |
| 765 | else |
| 766 | /* trampoline code not run */ |
| 767 | pr_err("CPU%d: Not responding\n", cpu); |
| 768 | if (apic->inquire_remote_apic) |
| 769 | apic->inquire_remote_apic(apicid); |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | if (boot_error) { |
| 774 | /* Try to put things back the way they were before ... */ |
| 775 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
| 776 | |
| 777 | /* was set by do_boot_cpu() */ |
| 778 | cpumask_clear_cpu(cpu, cpu_callout_mask); |
| 779 | |
| 780 | /* was set by cpu_init() */ |
| 781 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
| 782 | |
| 783 | set_cpu_present(cpu, false); |
| 784 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
| 785 | } |
| 786 | |
| 787 | /* mark "stuck" area as not stuck */ |
| 788 | *trampoline_status = 0; |
| 789 | |
| 790 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
| 791 | /* |
| 792 | * Cleanup possible dangling ends... |
| 793 | */ |
| 794 | smpboot_restore_warm_reset_vector(); |
| 795 | } |
| 796 | return boot_error; |
| 797 | } |
| 798 | |
| 799 | int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
| 800 | { |
| 801 | int apicid = apic->cpu_present_to_apicid(cpu); |
| 802 | unsigned long flags; |
| 803 | int err; |
| 804 | |
| 805 | WARN_ON(irqs_disabled()); |
| 806 | |
| 807 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
| 808 | |
| 809 | if (apicid == BAD_APICID || |
| 810 | !physid_isset(apicid, phys_cpu_present_map) || |
| 811 | !apic->apic_id_valid(apicid)) { |
| 812 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
| 813 | return -EINVAL; |
| 814 | } |
| 815 | |
| 816 | /* |
| 817 | * Already booted CPU? |
| 818 | */ |
| 819 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
| 820 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
| 821 | return -ENOSYS; |
| 822 | } |
| 823 | |
| 824 | /* |
| 825 | * Save current MTRR state in case it was changed since early boot |
| 826 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: |
| 827 | */ |
| 828 | mtrr_save_state(); |
| 829 | |
| 830 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
| 831 | |
| 832 | err = do_boot_cpu(apicid, cpu, tidle); |
| 833 | if (err) { |
| 834 | pr_debug("do_boot_cpu failed %d\n", err); |
| 835 | return -EIO; |
| 836 | } |
| 837 | |
| 838 | /* |
| 839 | * Check TSC synchronization with the AP (keep irqs disabled |
| 840 | * while doing so): |
| 841 | */ |
| 842 | local_irq_save(flags); |
| 843 | check_tsc_sync_source(cpu); |
| 844 | local_irq_restore(flags); |
| 845 | |
| 846 | while (!cpu_online(cpu)) { |
| 847 | cpu_relax(); |
| 848 | touch_nmi_watchdog(); |
| 849 | } |
| 850 | |
| 851 | return 0; |
| 852 | } |
| 853 | |
| 854 | /** |
| 855 | * arch_disable_smp_support() - disables SMP support for x86 at runtime |
| 856 | */ |
| 857 | void arch_disable_smp_support(void) |
| 858 | { |
| 859 | disable_ioapic_support(); |
| 860 | } |
| 861 | |
| 862 | /* |
| 863 | * Fall back to non SMP mode after errors. |
| 864 | * |
| 865 | * RED-PEN audit/test this more. I bet there is more state messed up here. |
| 866 | */ |
| 867 | static __init void disable_smp(void) |
| 868 | { |
| 869 | init_cpu_present(cpumask_of(0)); |
| 870 | init_cpu_possible(cpumask_of(0)); |
| 871 | smpboot_clear_io_apic_irqs(); |
| 872 | |
| 873 | if (smp_found_config) |
| 874 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
| 875 | else |
| 876 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
| 877 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
| 878 | cpumask_set_cpu(0, cpu_core_mask(0)); |
| 879 | } |
| 880 | |
| 881 | /* |
| 882 | * Various sanity checks. |
| 883 | */ |
| 884 | static int __init smp_sanity_check(unsigned max_cpus) |
| 885 | { |
| 886 | preempt_disable(); |
| 887 | |
| 888 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
| 889 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
| 890 | unsigned int cpu; |
| 891 | unsigned nr; |
| 892 | |
| 893 | pr_warn("More than 8 CPUs detected - skipping them\n" |
| 894 | "Use CONFIG_X86_BIGSMP\n"); |
| 895 | |
| 896 | nr = 0; |
| 897 | for_each_present_cpu(cpu) { |
| 898 | if (nr >= 8) |
| 899 | set_cpu_present(cpu, false); |
| 900 | nr++; |
| 901 | } |
| 902 | |
| 903 | nr = 0; |
| 904 | for_each_possible_cpu(cpu) { |
| 905 | if (nr >= 8) |
| 906 | set_cpu_possible(cpu, false); |
| 907 | nr++; |
| 908 | } |
| 909 | |
| 910 | nr_cpu_ids = 8; |
| 911 | } |
| 912 | #endif |
| 913 | |
| 914 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
| 915 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
| 916 | hard_smp_processor_id()); |
| 917 | |
| 918 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
| 919 | } |
| 920 | |
| 921 | /* |
| 922 | * If we couldn't find an SMP configuration at boot time, |
| 923 | * get out of here now! |
| 924 | */ |
| 925 | if (!smp_found_config && !acpi_lapic) { |
| 926 | preempt_enable(); |
| 927 | pr_notice("SMP motherboard not detected\n"); |
| 928 | disable_smp(); |
| 929 | if (APIC_init_uniprocessor()) |
| 930 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
| 931 | return -1; |
| 932 | } |
| 933 | |
| 934 | /* |
| 935 | * Should not be necessary because the MP table should list the boot |
| 936 | * CPU too, but we do it for the sake of robustness anyway. |
| 937 | */ |
| 938 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
| 939 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
| 940 | boot_cpu_physical_apicid); |
| 941 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
| 942 | } |
| 943 | preempt_enable(); |
| 944 | |
| 945 | /* |
| 946 | * If we couldn't find a local APIC, then get out of here now! |
| 947 | */ |
| 948 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && |
| 949 | !cpu_has_apic) { |
| 950 | if (!disable_apic) { |
| 951 | pr_err("BIOS bug, local APIC #%d not detected!...\n", |
| 952 | boot_cpu_physical_apicid); |
| 953 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
| 954 | } |
| 955 | smpboot_clear_io_apic(); |
| 956 | disable_ioapic_support(); |
| 957 | return -1; |
| 958 | } |
| 959 | |
| 960 | verify_local_APIC(); |
| 961 | |
| 962 | /* |
| 963 | * If SMP should be disabled, then really disable it! |
| 964 | */ |
| 965 | if (!max_cpus) { |
| 966 | pr_info("SMP mode deactivated\n"); |
| 967 | smpboot_clear_io_apic(); |
| 968 | |
| 969 | connect_bsp_APIC(); |
| 970 | setup_local_APIC(); |
| 971 | bsp_end_local_APIC_setup(); |
| 972 | return -1; |
| 973 | } |
| 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | static void __init smp_cpu_index_default(void) |
| 979 | { |
| 980 | int i; |
| 981 | struct cpuinfo_x86 *c; |
| 982 | |
| 983 | for_each_possible_cpu(i) { |
| 984 | c = &cpu_data(i); |
| 985 | /* mark all to hotplug */ |
| 986 | c->cpu_index = nr_cpu_ids; |
| 987 | } |
| 988 | } |
| 989 | |
| 990 | /* |
| 991 | * Prepare for SMP bootup. The MP table or ACPI has been read |
| 992 | * earlier. Just do some sanity checking here and enable APIC mode. |
| 993 | */ |
| 994 | void __init native_smp_prepare_cpus(unsigned int max_cpus) |
| 995 | { |
| 996 | unsigned int i; |
| 997 | |
| 998 | preempt_disable(); |
| 999 | smp_cpu_index_default(); |
| 1000 | |
| 1001 | /* |
| 1002 | * Setup boot CPU information |
| 1003 | */ |
| 1004 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
| 1005 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
| 1006 | mb(); |
| 1007 | |
| 1008 | current_thread_info()->cpu = 0; /* needed? */ |
| 1009 | for_each_possible_cpu(i) { |
| 1010 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
| 1011 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); |
| 1012 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
| 1013 | } |
| 1014 | set_cpu_sibling_map(0); |
| 1015 | |
| 1016 | |
| 1017 | if (smp_sanity_check(max_cpus) < 0) { |
| 1018 | pr_info("SMP disabled\n"); |
| 1019 | disable_smp(); |
| 1020 | goto out; |
| 1021 | } |
| 1022 | |
| 1023 | default_setup_apic_routing(); |
| 1024 | |
| 1025 | preempt_disable(); |
| 1026 | if (read_apic_id() != boot_cpu_physical_apicid) { |
| 1027 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
| 1028 | read_apic_id(), boot_cpu_physical_apicid); |
| 1029 | /* Or can we switch back to PIC here? */ |
| 1030 | } |
| 1031 | preempt_enable(); |
| 1032 | |
| 1033 | connect_bsp_APIC(); |
| 1034 | |
| 1035 | /* |
| 1036 | * Switch from PIC to APIC mode. |
| 1037 | */ |
| 1038 | setup_local_APIC(); |
| 1039 | |
| 1040 | /* |
| 1041 | * Enable IO APIC before setting up error vector |
| 1042 | */ |
| 1043 | if (!skip_ioapic_setup && nr_ioapics) |
| 1044 | enable_IO_APIC(); |
| 1045 | |
| 1046 | bsp_end_local_APIC_setup(); |
| 1047 | |
| 1048 | if (apic->setup_portio_remap) |
| 1049 | apic->setup_portio_remap(); |
| 1050 | |
| 1051 | smpboot_setup_io_apic(); |
| 1052 | /* |
| 1053 | * Set up local APIC timer on boot CPU. |
| 1054 | */ |
| 1055 | |
| 1056 | pr_info("CPU%d: ", 0); |
| 1057 | print_cpu_info(&cpu_data(0)); |
| 1058 | x86_init.timers.setup_percpu_clockev(); |
| 1059 | |
| 1060 | if (is_uv_system()) |
| 1061 | uv_system_init(); |
| 1062 | |
| 1063 | set_mtrr_aps_delayed_init(); |
| 1064 | out: |
| 1065 | preempt_enable(); |
| 1066 | } |
| 1067 | |
| 1068 | void arch_enable_nonboot_cpus_begin(void) |
| 1069 | { |
| 1070 | set_mtrr_aps_delayed_init(); |
| 1071 | } |
| 1072 | |
| 1073 | void arch_enable_nonboot_cpus_end(void) |
| 1074 | { |
| 1075 | mtrr_aps_init(); |
| 1076 | } |
| 1077 | |
| 1078 | /* |
| 1079 | * Early setup to make printk work. |
| 1080 | */ |
| 1081 | void __init native_smp_prepare_boot_cpu(void) |
| 1082 | { |
| 1083 | int me = smp_processor_id(); |
| 1084 | switch_to_new_gdt(me); |
| 1085 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
| 1086 | cpumask_set_cpu(me, cpu_callout_mask); |
| 1087 | per_cpu(cpu_state, me) = CPU_ONLINE; |
| 1088 | } |
| 1089 | |
| 1090 | void __init native_smp_cpus_done(unsigned int max_cpus) |
| 1091 | { |
| 1092 | pr_debug("Boot done\n"); |
| 1093 | |
| 1094 | nmi_selftest(); |
| 1095 | impress_friends(); |
| 1096 | #ifdef CONFIG_X86_IO_APIC |
| 1097 | setup_ioapic_dest(); |
| 1098 | #endif |
| 1099 | mtrr_aps_init(); |
| 1100 | } |
| 1101 | |
| 1102 | static int __initdata setup_possible_cpus = -1; |
| 1103 | static int __init _setup_possible_cpus(char *str) |
| 1104 | { |
| 1105 | get_option(&str, &setup_possible_cpus); |
| 1106 | return 0; |
| 1107 | } |
| 1108 | early_param("possible_cpus", _setup_possible_cpus); |
| 1109 | |
| 1110 | |
| 1111 | /* |
| 1112 | * cpu_possible_mask should be static, it cannot change as cpu's |
| 1113 | * are onlined, or offlined. The reason is per-cpu data-structures |
| 1114 | * are allocated by some modules at init time, and dont expect to |
| 1115 | * do this dynamically on cpu arrival/departure. |
| 1116 | * cpu_present_mask on the other hand can change dynamically. |
| 1117 | * In case when cpu_hotplug is not compiled, then we resort to current |
| 1118 | * behaviour, which is cpu_possible == cpu_present. |
| 1119 | * - Ashok Raj |
| 1120 | * |
| 1121 | * Three ways to find out the number of additional hotplug CPUs: |
| 1122 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. |
| 1123 | * - The user can overwrite it with possible_cpus=NUM |
| 1124 | * - Otherwise don't reserve additional CPUs. |
| 1125 | * We do this because additional CPUs waste a lot of memory. |
| 1126 | * -AK |
| 1127 | */ |
| 1128 | __init void prefill_possible_map(void) |
| 1129 | { |
| 1130 | int i, possible; |
| 1131 | |
| 1132 | /* no processor from mptable or madt */ |
| 1133 | if (!num_processors) |
| 1134 | num_processors = 1; |
| 1135 | |
| 1136 | i = setup_max_cpus ?: 1; |
| 1137 | if (setup_possible_cpus == -1) { |
| 1138 | possible = num_processors; |
| 1139 | #ifdef CONFIG_HOTPLUG_CPU |
| 1140 | if (setup_max_cpus) |
| 1141 | possible += disabled_cpus; |
| 1142 | #else |
| 1143 | if (possible > i) |
| 1144 | possible = i; |
| 1145 | #endif |
| 1146 | } else |
| 1147 | possible = setup_possible_cpus; |
| 1148 | |
| 1149 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
| 1150 | |
| 1151 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
| 1152 | if (possible > nr_cpu_ids) { |
| 1153 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
| 1154 | possible, nr_cpu_ids); |
| 1155 | possible = nr_cpu_ids; |
| 1156 | } |
| 1157 | |
| 1158 | #ifdef CONFIG_HOTPLUG_CPU |
| 1159 | if (!setup_max_cpus) |
| 1160 | #endif |
| 1161 | if (possible > i) { |
| 1162 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
| 1163 | possible, setup_max_cpus); |
| 1164 | possible = i; |
| 1165 | } |
| 1166 | |
| 1167 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
| 1168 | possible, max_t(int, possible - num_processors, 0)); |
| 1169 | |
| 1170 | for (i = 0; i < possible; i++) |
| 1171 | set_cpu_possible(i, true); |
| 1172 | for (; i < NR_CPUS; i++) |
| 1173 | set_cpu_possible(i, false); |
| 1174 | |
| 1175 | nr_cpu_ids = possible; |
| 1176 | } |
| 1177 | |
| 1178 | #ifdef CONFIG_HOTPLUG_CPU |
| 1179 | |
| 1180 | static void remove_siblinginfo(int cpu) |
| 1181 | { |
| 1182 | int sibling; |
| 1183 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
| 1184 | |
| 1185 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
| 1186 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); |
| 1187 | /*/ |
| 1188 | * last thread sibling in this cpu core going down |
| 1189 | */ |
| 1190 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
| 1191 | cpu_data(sibling).booted_cores--; |
| 1192 | } |
| 1193 | |
| 1194 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
| 1195 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); |
| 1196 | cpumask_clear(cpu_sibling_mask(cpu)); |
| 1197 | cpumask_clear(cpu_core_mask(cpu)); |
| 1198 | c->phys_proc_id = 0; |
| 1199 | c->cpu_core_id = 0; |
| 1200 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
| 1201 | } |
| 1202 | |
| 1203 | static void __ref remove_cpu_from_maps(int cpu) |
| 1204 | { |
| 1205 | set_cpu_online(cpu, false); |
| 1206 | cpumask_clear_cpu(cpu, cpu_callout_mask); |
| 1207 | cpumask_clear_cpu(cpu, cpu_callin_mask); |
| 1208 | /* was set by cpu_init() */ |
| 1209 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
| 1210 | numa_remove_cpu(cpu); |
| 1211 | } |
| 1212 | |
| 1213 | void cpu_disable_common(void) |
| 1214 | { |
| 1215 | int cpu = smp_processor_id(); |
| 1216 | |
| 1217 | remove_siblinginfo(cpu); |
| 1218 | |
| 1219 | /* It's now safe to remove this processor from the online map */ |
| 1220 | lock_vector_lock(); |
| 1221 | remove_cpu_from_maps(cpu); |
| 1222 | unlock_vector_lock(); |
| 1223 | fixup_irqs(); |
| 1224 | } |
| 1225 | |
| 1226 | int native_cpu_disable(void) |
| 1227 | { |
| 1228 | clear_local_APIC(); |
| 1229 | |
| 1230 | cpu_disable_common(); |
| 1231 | return 0; |
| 1232 | } |
| 1233 | |
| 1234 | void native_cpu_die(unsigned int cpu) |
| 1235 | { |
| 1236 | /* We don't do anything here: idle task is faking death itself. */ |
| 1237 | unsigned int i; |
| 1238 | |
| 1239 | for (i = 0; i < 10; i++) { |
| 1240 | /* They ack this in play_dead by setting CPU_DEAD */ |
| 1241 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
| 1242 | if (system_state == SYSTEM_RUNNING) |
| 1243 | pr_info("CPU %u is now offline\n", cpu); |
| 1244 | return; |
| 1245 | } |
| 1246 | msleep(100); |
| 1247 | } |
| 1248 | pr_err("CPU %u didn't die...\n", cpu); |
| 1249 | } |
| 1250 | |
| 1251 | void play_dead_common(void) |
| 1252 | { |
| 1253 | idle_task_exit(); |
| 1254 | reset_lazy_tlbstate(); |
| 1255 | amd_e400_remove_cpu(raw_smp_processor_id()); |
| 1256 | |
| 1257 | mb(); |
| 1258 | /* Ack it */ |
| 1259 | __this_cpu_write(cpu_state, CPU_DEAD); |
| 1260 | |
| 1261 | /* |
| 1262 | * With physical CPU hotplug, we should halt the cpu |
| 1263 | */ |
| 1264 | local_irq_disable(); |
| 1265 | } |
| 1266 | |
| 1267 | /* |
| 1268 | * We need to flush the caches before going to sleep, lest we have |
| 1269 | * dirty data in our caches when we come back up. |
| 1270 | */ |
| 1271 | static inline void mwait_play_dead(void) |
| 1272 | { |
| 1273 | unsigned int eax, ebx, ecx, edx; |
| 1274 | unsigned int highest_cstate = 0; |
| 1275 | unsigned int highest_subcstate = 0; |
| 1276 | int i; |
| 1277 | void *mwait_ptr; |
| 1278 | struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); |
| 1279 | |
| 1280 | if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) |
| 1281 | return; |
| 1282 | if (!this_cpu_has(X86_FEATURE_CLFLSH)) |
| 1283 | return; |
| 1284 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
| 1285 | return; |
| 1286 | |
| 1287 | eax = CPUID_MWAIT_LEAF; |
| 1288 | ecx = 0; |
| 1289 | native_cpuid(&eax, &ebx, &ecx, &edx); |
| 1290 | |
| 1291 | /* |
| 1292 | * eax will be 0 if EDX enumeration is not valid. |
| 1293 | * Initialized below to cstate, sub_cstate value when EDX is valid. |
| 1294 | */ |
| 1295 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { |
| 1296 | eax = 0; |
| 1297 | } else { |
| 1298 | edx >>= MWAIT_SUBSTATE_SIZE; |
| 1299 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { |
| 1300 | if (edx & MWAIT_SUBSTATE_MASK) { |
| 1301 | highest_cstate = i; |
| 1302 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; |
| 1303 | } |
| 1304 | } |
| 1305 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | |
| 1306 | (highest_subcstate - 1); |
| 1307 | } |
| 1308 | |
| 1309 | /* |
| 1310 | * This should be a memory location in a cache line which is |
| 1311 | * unlikely to be touched by other processors. The actual |
| 1312 | * content is immaterial as it is not actually modified in any way. |
| 1313 | */ |
| 1314 | mwait_ptr = ¤t_thread_info()->flags; |
| 1315 | |
| 1316 | wbinvd(); |
| 1317 | |
| 1318 | while (1) { |
| 1319 | /* |
| 1320 | * The CLFLUSH is a workaround for erratum AAI65 for |
| 1321 | * the Xeon 7400 series. It's not clear it is actually |
| 1322 | * needed, but it should be harmless in either case. |
| 1323 | * The WBINVD is insufficient due to the spurious-wakeup |
| 1324 | * case where we return around the loop. |
| 1325 | */ |
| 1326 | clflush(mwait_ptr); |
| 1327 | __monitor(mwait_ptr, 0, 0); |
| 1328 | mb(); |
| 1329 | __mwait(eax, 0); |
| 1330 | } |
| 1331 | } |
| 1332 | |
| 1333 | static inline void hlt_play_dead(void) |
| 1334 | { |
| 1335 | if (__this_cpu_read(cpu_info.x86) >= 4) |
| 1336 | wbinvd(); |
| 1337 | |
| 1338 | while (1) { |
| 1339 | native_halt(); |
| 1340 | } |
| 1341 | } |
| 1342 | |
| 1343 | void native_play_dead(void) |
| 1344 | { |
| 1345 | play_dead_common(); |
| 1346 | tboot_shutdown(TB_SHUTDOWN_WFS); |
| 1347 | |
| 1348 | mwait_play_dead(); /* Only returns on failure */ |
| 1349 | if (cpuidle_play_dead()) |
| 1350 | hlt_play_dead(); |
| 1351 | } |
| 1352 | |
| 1353 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
| 1354 | int native_cpu_disable(void) |
| 1355 | { |
| 1356 | return -ENOSYS; |
| 1357 | } |
| 1358 | |
| 1359 | void native_cpu_die(unsigned int cpu) |
| 1360 | { |
| 1361 | /* We said "no" in __cpu_disable */ |
| 1362 | BUG(); |
| 1363 | } |
| 1364 | |
| 1365 | void native_play_dead(void) |
| 1366 | { |
| 1367 | BUG(); |
| 1368 | } |
| 1369 | |
| 1370 | #endif |