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KVM: emulator: Use linearize() when fetching instructions
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
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CommitLineData
1/******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#include <linux/kvm_host.h>
24#include "kvm_cache_regs.h"
25#include <linux/module.h>
26#include <asm/kvm_emulate.h>
27
28#include "x86.h"
29#include "tss.h"
30
31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
41#define ByteOp (1<<0) /* 8-bit operands. */
42/* Destination operand type. */
43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50#define DstMask (7<<1)
51/* Source operand type. */
52#define SrcNone (0<<4) /* No source operand. */
53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59#define SrcOne (7<<4) /* Implied '1' */
60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65#define SrcAcc (0xd<<4) /* Source Accumulator */
66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67#define SrcMask (0xf<<4)
68/* Generic ModRM decode. */
69#define ModRM (1<<8)
70/* Destination is only written; never read. */
71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79#define Sse (1<<17) /* SSE Vector instruction */
80#define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
81/* Misc flags */
82#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
83#define VendorSpecific (1<<22) /* Vendor specific instruction */
84#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
85#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
86#define Undefined (1<<25) /* No Such Instruction */
87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89#define No64 (1<<28)
90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
95#define Src2Imm (4<<29)
96#define Src2Mask (7<<29)
97
98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
106
107struct opcode {
108 u32 flags;
109 u8 intercept;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 struct gprefix *gprefix;
115 } u;
116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122};
123
124struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129};
130
131/* EFLAGS bit definitions. */
132#define EFLG_ID (1<<21)
133#define EFLG_VIP (1<<20)
134#define EFLG_VIF (1<<19)
135#define EFLG_AC (1<<18)
136#define EFLG_VM (1<<17)
137#define EFLG_RF (1<<16)
138#define EFLG_IOPL (3<<12)
139#define EFLG_NT (1<<14)
140#define EFLG_OF (1<<11)
141#define EFLG_DF (1<<10)
142#define EFLG_IF (1<<9)
143#define EFLG_TF (1<<8)
144#define EFLG_SF (1<<7)
145#define EFLG_ZF (1<<6)
146#define EFLG_AF (1<<4)
147#define EFLG_PF (1<<2)
148#define EFLG_CF (1<<0)
149
150#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151#define EFLG_RESERVED_ONE_MASK 2
152
153/*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
160#if defined(CONFIG_X86_64)
161#define _LO32 "k" /* force 32-bit operand */
162#define _STK "%%rsp" /* stack pointer */
163#elif defined(__i386__)
164#define _LO32 "" /* force 32-bit operand */
165#define _STK "%%esp" /* stack pointer */
166#endif
167
168/*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174/* Before executing instruction: restore necessary bits in EFLAGS. */
175#define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
190
191/* After executing instruction: write-back necessary bits in EFLAGS. */
192#define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
199#ifdef CONFIG_X86_64
200#define ON64(x) x
201#else
202#define ON64(x)
203#endif
204
205#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
214 } while (0)
215
216
217/* Raw emulation: instruction has two explicit operands. */
218#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 break; \
226 case 4: \
227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 break; \
229 case 8: \
230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
231 break; \
232 } \
233 } while (0)
234
235#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
237 unsigned long _tmp; \
238 switch ((_dst).bytes) { \
239 case 1: \
240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249/* Source operand is byte-sized and may be restricted to just %cl. */
250#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254/* Source operand is byte, word, long or quad sized. */
255#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259/* Source operand is word, long or quad sized. */
260#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
264/* Instruction has three operands and one operand is stored in ECX register */
265#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
303#define __emulate_1op(_op, _dst, _eflags, _suffix) \
304 do { \
305 unsigned long _tmp; \
306 \
307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316/* Instruction has only one explicit operand (no source operand). */
317#define emulate_1op(_op, _dst, _eflags) \
318 do { \
319 switch ((_dst).bytes) { \
320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
324 } \
325 } while (0)
326
327#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
341#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
362/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
367 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
368 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
369 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
370 } \
371 } while (0)
372
373#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
374 do { \
375 switch((_src).bytes) { \
376 case 1: \
377 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
378 _eflags, "b", _ex); \
379 break; \
380 case 2: \
381 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
382 _eflags, "w", _ex); \
383 break; \
384 case 4: \
385 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
386 _eflags, "l", _ex); \
387 break; \
388 case 8: ON64( \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "q", _ex)); \
391 break; \
392 } \
393 } while (0)
394
395/* Fetch next part of the instruction being emulated. */
396#define insn_fetch(_type, _size, _eip) \
397({ unsigned long _x; \
398 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
399 if (rc != X86EMUL_CONTINUE) \
400 goto done; \
401 (_eip) += (_size); \
402 (_type)_x; \
403})
404
405#define insn_fetch_arr(_arr, _size, _eip) \
406({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
407 if (rc != X86EMUL_CONTINUE) \
408 goto done; \
409 (_eip) += (_size); \
410})
411
412static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
413 enum x86_intercept intercept,
414 enum x86_intercept_stage stage)
415{
416 struct x86_instruction_info info = {
417 .intercept = intercept,
418 .rep_prefix = ctxt->decode.rep_prefix,
419 .modrm_mod = ctxt->decode.modrm_mod,
420 .modrm_reg = ctxt->decode.modrm_reg,
421 .modrm_rm = ctxt->decode.modrm_rm,
422 .src_val = ctxt->decode.src.val64,
423 .src_bytes = ctxt->decode.src.bytes,
424 .dst_bytes = ctxt->decode.dst.bytes,
425 .ad_bytes = ctxt->decode.ad_bytes,
426 .next_rip = ctxt->eip,
427 };
428
429 return ctxt->ops->intercept(ctxt->vcpu, &info, stage);
430}
431
432static inline unsigned long ad_mask(struct decode_cache *c)
433{
434 return (1UL << (c->ad_bytes << 3)) - 1;
435}
436
437/* Access/update address held in a register, based on addressing mode. */
438static inline unsigned long
439address_mask(struct decode_cache *c, unsigned long reg)
440{
441 if (c->ad_bytes == sizeof(unsigned long))
442 return reg;
443 else
444 return reg & ad_mask(c);
445}
446
447static inline unsigned long
448register_address(struct decode_cache *c, unsigned long reg)
449{
450 return address_mask(c, reg);
451}
452
453static inline void
454register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
455{
456 if (c->ad_bytes == sizeof(unsigned long))
457 *reg += inc;
458 else
459 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
460}
461
462static inline void jmp_rel(struct decode_cache *c, int rel)
463{
464 register_address_increment(c, &c->eip, rel);
465}
466
467static u32 desc_limit_scaled(struct desc_struct *desc)
468{
469 u32 limit = get_desc_limit(desc);
470
471 return desc->g ? (limit << 12) | 0xfff : limit;
472}
473
474static void set_seg_override(struct decode_cache *c, int seg)
475{
476 c->has_seg_override = true;
477 c->seg_override = seg;
478}
479
480static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
481 struct x86_emulate_ops *ops, int seg)
482{
483 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
484 return 0;
485
486 return ops->get_cached_segment_base(seg, ctxt->vcpu);
487}
488
489static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
490 struct x86_emulate_ops *ops,
491 struct decode_cache *c)
492{
493 if (!c->has_seg_override)
494 return 0;
495
496 return c->seg_override;
497}
498
499static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
500 u32 error, bool valid)
501{
502 ctxt->exception.vector = vec;
503 ctxt->exception.error_code = error;
504 ctxt->exception.error_code_valid = valid;
505 return X86EMUL_PROPAGATE_FAULT;
506}
507
508static int emulate_db(struct x86_emulate_ctxt *ctxt)
509{
510 return emulate_exception(ctxt, DB_VECTOR, 0, false);
511}
512
513static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
514{
515 return emulate_exception(ctxt, GP_VECTOR, err, true);
516}
517
518static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
519{
520 return emulate_exception(ctxt, SS_VECTOR, err, true);
521}
522
523static int emulate_ud(struct x86_emulate_ctxt *ctxt)
524{
525 return emulate_exception(ctxt, UD_VECTOR, 0, false);
526}
527
528static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
529{
530 return emulate_exception(ctxt, TS_VECTOR, err, true);
531}
532
533static int emulate_de(struct x86_emulate_ctxt *ctxt)
534{
535 return emulate_exception(ctxt, DE_VECTOR, 0, false);
536}
537
538static int emulate_nm(struct x86_emulate_ctxt *ctxt)
539{
540 return emulate_exception(ctxt, NM_VECTOR, 0, false);
541}
542
543static int __linearize(struct x86_emulate_ctxt *ctxt,
544 struct segmented_address addr,
545 unsigned size, bool write, bool fetch,
546 ulong *linear)
547{
548 struct decode_cache *c = &ctxt->decode;
549 struct desc_struct desc;
550 bool usable;
551 ulong la;
552 u32 lim;
553 unsigned cpl, rpl;
554
555 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
556 switch (ctxt->mode) {
557 case X86EMUL_MODE_REAL:
558 break;
559 case X86EMUL_MODE_PROT64:
560 if (((signed long)la << 16) >> 16 != la)
561 return emulate_gp(ctxt, 0);
562 break;
563 default:
564 usable = ctxt->ops->get_cached_descriptor(&desc, NULL, addr.seg,
565 ctxt->vcpu);
566 if (!usable)
567 goto bad;
568 /* code segment or read-only data segment */
569 if (((desc.type & 8) || !(desc.type & 2)) && write)
570 goto bad;
571 /* unreadable code segment */
572 if (!fetch && (desc.type & 8) && !(desc.type & 2))
573 goto bad;
574 lim = desc_limit_scaled(&desc);
575 if ((desc.type & 8) || !(desc.type & 4)) {
576 /* expand-up segment */
577 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
578 goto bad;
579 } else {
580 /* exapand-down segment */
581 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
582 goto bad;
583 lim = desc.d ? 0xffffffff : 0xffff;
584 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
585 goto bad;
586 }
587 cpl = ctxt->ops->cpl(ctxt->vcpu);
588 rpl = ctxt->ops->get_segment_selector(addr.seg, ctxt->vcpu) & 3;
589 cpl = max(cpl, rpl);
590 if (!(desc.type & 8)) {
591 /* data segment */
592 if (cpl > desc.dpl)
593 goto bad;
594 } else if ((desc.type & 8) && !(desc.type & 4)) {
595 /* nonconforming code segment */
596 if (cpl != desc.dpl)
597 goto bad;
598 } else if ((desc.type & 8) && (desc.type & 4)) {
599 /* conforming code segment */
600 if (cpl < desc.dpl)
601 goto bad;
602 }
603 break;
604 }
605 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
606 la &= (u32)-1;
607 *linear = la;
608 return X86EMUL_CONTINUE;
609bad:
610 if (addr.seg == VCPU_SREG_SS)
611 return emulate_ss(ctxt, addr.seg);
612 else
613 return emulate_gp(ctxt, addr.seg);
614}
615
616static int linearize(struct x86_emulate_ctxt *ctxt,
617 struct segmented_address addr,
618 unsigned size, bool write,
619 ulong *linear)
620{
621 return __linearize(ctxt, addr, size, write, false, linear);
622}
623
624
625static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
626 struct segmented_address addr,
627 void *data,
628 unsigned size)
629{
630 int rc;
631 ulong linear;
632
633 rc = linearize(ctxt, addr, size, false, &linear);
634 if (rc != X86EMUL_CONTINUE)
635 return rc;
636 return ctxt->ops->read_std(linear, data, size, ctxt->vcpu,
637 &ctxt->exception);
638}
639
640static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
641 struct x86_emulate_ops *ops,
642 unsigned long eip, u8 *dest)
643{
644 struct fetch_cache *fc = &ctxt->decode.fetch;
645 int rc;
646 int size, cur_size;
647
648 if (eip == fc->end) {
649 unsigned long linear;
650 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
651 cur_size = fc->end - fc->start;
652 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
653 rc = __linearize(ctxt, addr, size, false, true, &linear);
654 if (rc != X86EMUL_CONTINUE)
655 return rc;
656 rc = ops->fetch(linear, fc->data + cur_size,
657 size, ctxt->vcpu, &ctxt->exception);
658 if (rc != X86EMUL_CONTINUE)
659 return rc;
660 fc->end += size;
661 }
662 *dest = fc->data[eip - fc->start];
663 return X86EMUL_CONTINUE;
664}
665
666static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
667 struct x86_emulate_ops *ops,
668 unsigned long eip, void *dest, unsigned size)
669{
670 int rc;
671
672 /* x86 instructions are limited to 15 bytes. */
673 if (eip + size - ctxt->eip > 15)
674 return X86EMUL_UNHANDLEABLE;
675 while (size--) {
676 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
677 if (rc != X86EMUL_CONTINUE)
678 return rc;
679 }
680 return X86EMUL_CONTINUE;
681}
682
683/*
684 * Given the 'reg' portion of a ModRM byte, and a register block, return a
685 * pointer into the block that addresses the relevant register.
686 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
687 */
688static void *decode_register(u8 modrm_reg, unsigned long *regs,
689 int highbyte_regs)
690{
691 void *p;
692
693 p = &regs[modrm_reg];
694 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
695 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
696 return p;
697}
698
699static int read_descriptor(struct x86_emulate_ctxt *ctxt,
700 struct x86_emulate_ops *ops,
701 struct segmented_address addr,
702 u16 *size, unsigned long *address, int op_bytes)
703{
704 int rc;
705
706 if (op_bytes == 2)
707 op_bytes = 3;
708 *address = 0;
709 rc = segmented_read_std(ctxt, addr, size, 2);
710 if (rc != X86EMUL_CONTINUE)
711 return rc;
712 addr.ea += 2;
713 rc = segmented_read_std(ctxt, addr, address, op_bytes);
714 return rc;
715}
716
717static int test_cc(unsigned int condition, unsigned int flags)
718{
719 int rc = 0;
720
721 switch ((condition & 15) >> 1) {
722 case 0: /* o */
723 rc |= (flags & EFLG_OF);
724 break;
725 case 1: /* b/c/nae */
726 rc |= (flags & EFLG_CF);
727 break;
728 case 2: /* z/e */
729 rc |= (flags & EFLG_ZF);
730 break;
731 case 3: /* be/na */
732 rc |= (flags & (EFLG_CF|EFLG_ZF));
733 break;
734 case 4: /* s */
735 rc |= (flags & EFLG_SF);
736 break;
737 case 5: /* p/pe */
738 rc |= (flags & EFLG_PF);
739 break;
740 case 7: /* le/ng */
741 rc |= (flags & EFLG_ZF);
742 /* fall through */
743 case 6: /* l/nge */
744 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
745 break;
746 }
747
748 /* Odd condition identifiers (lsb == 1) have inverted sense. */
749 return (!!rc ^ (condition & 1));
750}
751
752static void fetch_register_operand(struct operand *op)
753{
754 switch (op->bytes) {
755 case 1:
756 op->val = *(u8 *)op->addr.reg;
757 break;
758 case 2:
759 op->val = *(u16 *)op->addr.reg;
760 break;
761 case 4:
762 op->val = *(u32 *)op->addr.reg;
763 break;
764 case 8:
765 op->val = *(u64 *)op->addr.reg;
766 break;
767 }
768}
769
770static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
771{
772 ctxt->ops->get_fpu(ctxt);
773 switch (reg) {
774 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
775 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
776 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
777 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
778 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
779 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
780 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
781 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
782#ifdef CONFIG_X86_64
783 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
784 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
785 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
786 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
787 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
788 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
789 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
790 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
791#endif
792 default: BUG();
793 }
794 ctxt->ops->put_fpu(ctxt);
795}
796
797static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
798 int reg)
799{
800 ctxt->ops->get_fpu(ctxt);
801 switch (reg) {
802 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
803 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
804 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
805 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
806 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
807 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
808 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
809 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
810#ifdef CONFIG_X86_64
811 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
812 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
813 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
814 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
815 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
816 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
817 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
818 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
819#endif
820 default: BUG();
821 }
822 ctxt->ops->put_fpu(ctxt);
823}
824
825static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
826 struct operand *op,
827 struct decode_cache *c,
828 int inhibit_bytereg)
829{
830 unsigned reg = c->modrm_reg;
831 int highbyte_regs = c->rex_prefix == 0;
832
833 if (!(c->d & ModRM))
834 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
835
836 if (c->d & Sse) {
837 op->type = OP_XMM;
838 op->bytes = 16;
839 op->addr.xmm = reg;
840 read_sse_reg(ctxt, &op->vec_val, reg);
841 return;
842 }
843
844 op->type = OP_REG;
845 if ((c->d & ByteOp) && !inhibit_bytereg) {
846 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
847 op->bytes = 1;
848 } else {
849 op->addr.reg = decode_register(reg, c->regs, 0);
850 op->bytes = c->op_bytes;
851 }
852 fetch_register_operand(op);
853 op->orig_val = op->val;
854}
855
856static int decode_modrm(struct x86_emulate_ctxt *ctxt,
857 struct x86_emulate_ops *ops,
858 struct operand *op)
859{
860 struct decode_cache *c = &ctxt->decode;
861 u8 sib;
862 int index_reg = 0, base_reg = 0, scale;
863 int rc = X86EMUL_CONTINUE;
864 ulong modrm_ea = 0;
865
866 if (c->rex_prefix) {
867 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
868 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
869 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
870 }
871
872 c->modrm = insn_fetch(u8, 1, c->eip);
873 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
874 c->modrm_reg |= (c->modrm & 0x38) >> 3;
875 c->modrm_rm |= (c->modrm & 0x07);
876 c->modrm_seg = VCPU_SREG_DS;
877
878 if (c->modrm_mod == 3) {
879 op->type = OP_REG;
880 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
881 op->addr.reg = decode_register(c->modrm_rm,
882 c->regs, c->d & ByteOp);
883 if (c->d & Sse) {
884 op->type = OP_XMM;
885 op->bytes = 16;
886 op->addr.xmm = c->modrm_rm;
887 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
888 return rc;
889 }
890 fetch_register_operand(op);
891 return rc;
892 }
893
894 op->type = OP_MEM;
895
896 if (c->ad_bytes == 2) {
897 unsigned bx = c->regs[VCPU_REGS_RBX];
898 unsigned bp = c->regs[VCPU_REGS_RBP];
899 unsigned si = c->regs[VCPU_REGS_RSI];
900 unsigned di = c->regs[VCPU_REGS_RDI];
901
902 /* 16-bit ModR/M decode. */
903 switch (c->modrm_mod) {
904 case 0:
905 if (c->modrm_rm == 6)
906 modrm_ea += insn_fetch(u16, 2, c->eip);
907 break;
908 case 1:
909 modrm_ea += insn_fetch(s8, 1, c->eip);
910 break;
911 case 2:
912 modrm_ea += insn_fetch(u16, 2, c->eip);
913 break;
914 }
915 switch (c->modrm_rm) {
916 case 0:
917 modrm_ea += bx + si;
918 break;
919 case 1:
920 modrm_ea += bx + di;
921 break;
922 case 2:
923 modrm_ea += bp + si;
924 break;
925 case 3:
926 modrm_ea += bp + di;
927 break;
928 case 4:
929 modrm_ea += si;
930 break;
931 case 5:
932 modrm_ea += di;
933 break;
934 case 6:
935 if (c->modrm_mod != 0)
936 modrm_ea += bp;
937 break;
938 case 7:
939 modrm_ea += bx;
940 break;
941 }
942 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
943 (c->modrm_rm == 6 && c->modrm_mod != 0))
944 c->modrm_seg = VCPU_SREG_SS;
945 modrm_ea = (u16)modrm_ea;
946 } else {
947 /* 32/64-bit ModR/M decode. */
948 if ((c->modrm_rm & 7) == 4) {
949 sib = insn_fetch(u8, 1, c->eip);
950 index_reg |= (sib >> 3) & 7;
951 base_reg |= sib & 7;
952 scale = sib >> 6;
953
954 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
955 modrm_ea += insn_fetch(s32, 4, c->eip);
956 else
957 modrm_ea += c->regs[base_reg];
958 if (index_reg != 4)
959 modrm_ea += c->regs[index_reg] << scale;
960 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
961 if (ctxt->mode == X86EMUL_MODE_PROT64)
962 c->rip_relative = 1;
963 } else
964 modrm_ea += c->regs[c->modrm_rm];
965 switch (c->modrm_mod) {
966 case 0:
967 if (c->modrm_rm == 5)
968 modrm_ea += insn_fetch(s32, 4, c->eip);
969 break;
970 case 1:
971 modrm_ea += insn_fetch(s8, 1, c->eip);
972 break;
973 case 2:
974 modrm_ea += insn_fetch(s32, 4, c->eip);
975 break;
976 }
977 }
978 op->addr.mem.ea = modrm_ea;
979done:
980 return rc;
981}
982
983static int decode_abs(struct x86_emulate_ctxt *ctxt,
984 struct x86_emulate_ops *ops,
985 struct operand *op)
986{
987 struct decode_cache *c = &ctxt->decode;
988 int rc = X86EMUL_CONTINUE;
989
990 op->type = OP_MEM;
991 switch (c->ad_bytes) {
992 case 2:
993 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
994 break;
995 case 4:
996 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
997 break;
998 case 8:
999 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1000 break;
1001 }
1002done:
1003 return rc;
1004}
1005
1006static void fetch_bit_operand(struct decode_cache *c)
1007{
1008 long sv = 0, mask;
1009
1010 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1011 mask = ~(c->dst.bytes * 8 - 1);
1012
1013 if (c->src.bytes == 2)
1014 sv = (s16)c->src.val & (s16)mask;
1015 else if (c->src.bytes == 4)
1016 sv = (s32)c->src.val & (s32)mask;
1017
1018 c->dst.addr.mem.ea += (sv >> 3);
1019 }
1020
1021 /* only subword offset */
1022 c->src.val &= (c->dst.bytes << 3) - 1;
1023}
1024
1025static int read_emulated(struct x86_emulate_ctxt *ctxt,
1026 struct x86_emulate_ops *ops,
1027 unsigned long addr, void *dest, unsigned size)
1028{
1029 int rc;
1030 struct read_cache *mc = &ctxt->decode.mem_read;
1031
1032 while (size) {
1033 int n = min(size, 8u);
1034 size -= n;
1035 if (mc->pos < mc->end)
1036 goto read_cached;
1037
1038 rc = ops->read_emulated(addr, mc->data + mc->end, n,
1039 &ctxt->exception, ctxt->vcpu);
1040 if (rc != X86EMUL_CONTINUE)
1041 return rc;
1042 mc->end += n;
1043
1044 read_cached:
1045 memcpy(dest, mc->data + mc->pos, n);
1046 mc->pos += n;
1047 dest += n;
1048 addr += n;
1049 }
1050 return X86EMUL_CONTINUE;
1051}
1052
1053static int segmented_read(struct x86_emulate_ctxt *ctxt,
1054 struct segmented_address addr,
1055 void *data,
1056 unsigned size)
1057{
1058 int rc;
1059 ulong linear;
1060
1061 rc = linearize(ctxt, addr, size, false, &linear);
1062 if (rc != X86EMUL_CONTINUE)
1063 return rc;
1064 return read_emulated(ctxt, ctxt->ops, linear, data, size);
1065}
1066
1067static int segmented_write(struct x86_emulate_ctxt *ctxt,
1068 struct segmented_address addr,
1069 const void *data,
1070 unsigned size)
1071{
1072 int rc;
1073 ulong linear;
1074
1075 rc = linearize(ctxt, addr, size, true, &linear);
1076 if (rc != X86EMUL_CONTINUE)
1077 return rc;
1078 return ctxt->ops->write_emulated(linear, data, size,
1079 &ctxt->exception, ctxt->vcpu);
1080}
1081
1082static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1083 struct segmented_address addr,
1084 const void *orig_data, const void *data,
1085 unsigned size)
1086{
1087 int rc;
1088 ulong linear;
1089
1090 rc = linearize(ctxt, addr, size, true, &linear);
1091 if (rc != X86EMUL_CONTINUE)
1092 return rc;
1093 return ctxt->ops->cmpxchg_emulated(linear, orig_data, data,
1094 size, &ctxt->exception, ctxt->vcpu);
1095}
1096
1097static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1098 struct x86_emulate_ops *ops,
1099 unsigned int size, unsigned short port,
1100 void *dest)
1101{
1102 struct read_cache *rc = &ctxt->decode.io_read;
1103
1104 if (rc->pos == rc->end) { /* refill pio read ahead */
1105 struct decode_cache *c = &ctxt->decode;
1106 unsigned int in_page, n;
1107 unsigned int count = c->rep_prefix ?
1108 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1109 in_page = (ctxt->eflags & EFLG_DF) ?
1110 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1111 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1112 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1113 count);
1114 if (n == 0)
1115 n = 1;
1116 rc->pos = rc->end = 0;
1117 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1118 return 0;
1119 rc->end = n * size;
1120 }
1121
1122 memcpy(dest, rc->data + rc->pos, size);
1123 rc->pos += size;
1124 return 1;
1125}
1126
1127static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1128 struct x86_emulate_ops *ops,
1129 u16 selector, struct desc_ptr *dt)
1130{
1131 if (selector & 1 << 2) {
1132 struct desc_struct desc;
1133 memset (dt, 0, sizeof *dt);
1134 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
1135 ctxt->vcpu))
1136 return;
1137
1138 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1139 dt->address = get_desc_base(&desc);
1140 } else
1141 ops->get_gdt(dt, ctxt->vcpu);
1142}
1143
1144/* allowed just for 8 bytes segments */
1145static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1146 struct x86_emulate_ops *ops,
1147 u16 selector, struct desc_struct *desc)
1148{
1149 struct desc_ptr dt;
1150 u16 index = selector >> 3;
1151 int ret;
1152 ulong addr;
1153
1154 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1155
1156 if (dt.size < index * 8 + 7)
1157 return emulate_gp(ctxt, selector & 0xfffc);
1158 addr = dt.address + index * 8;
1159 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
1160 &ctxt->exception);
1161
1162 return ret;
1163}
1164
1165/* allowed just for 8 bytes segments */
1166static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1167 struct x86_emulate_ops *ops,
1168 u16 selector, struct desc_struct *desc)
1169{
1170 struct desc_ptr dt;
1171 u16 index = selector >> 3;
1172 ulong addr;
1173 int ret;
1174
1175 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1176
1177 if (dt.size < index * 8 + 7)
1178 return emulate_gp(ctxt, selector & 0xfffc);
1179
1180 addr = dt.address + index * 8;
1181 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
1182 &ctxt->exception);
1183
1184 return ret;
1185}
1186
1187/* Does not support long mode */
1188static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1189 struct x86_emulate_ops *ops,
1190 u16 selector, int seg)
1191{
1192 struct desc_struct seg_desc;
1193 u8 dpl, rpl, cpl;
1194 unsigned err_vec = GP_VECTOR;
1195 u32 err_code = 0;
1196 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1197 int ret;
1198
1199 memset(&seg_desc, 0, sizeof seg_desc);
1200
1201 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1202 || ctxt->mode == X86EMUL_MODE_REAL) {
1203 /* set real mode segment descriptor */
1204 set_desc_base(&seg_desc, selector << 4);
1205 set_desc_limit(&seg_desc, 0xffff);
1206 seg_desc.type = 3;
1207 seg_desc.p = 1;
1208 seg_desc.s = 1;
1209 goto load;
1210 }
1211
1212 /* NULL selector is not valid for TR, CS and SS */
1213 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1214 && null_selector)
1215 goto exception;
1216
1217 /* TR should be in GDT only */
1218 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1219 goto exception;
1220
1221 if (null_selector) /* for NULL selector skip all following checks */
1222 goto load;
1223
1224 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1225 if (ret != X86EMUL_CONTINUE)
1226 return ret;
1227
1228 err_code = selector & 0xfffc;
1229 err_vec = GP_VECTOR;
1230
1231 /* can't load system descriptor into segment selecor */
1232 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1233 goto exception;
1234
1235 if (!seg_desc.p) {
1236 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1237 goto exception;
1238 }
1239
1240 rpl = selector & 3;
1241 dpl = seg_desc.dpl;
1242 cpl = ops->cpl(ctxt->vcpu);
1243
1244 switch (seg) {
1245 case VCPU_SREG_SS:
1246 /*
1247 * segment is not a writable data segment or segment
1248 * selector's RPL != CPL or segment selector's RPL != CPL
1249 */
1250 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1251 goto exception;
1252 break;
1253 case VCPU_SREG_CS:
1254 if (!(seg_desc.type & 8))
1255 goto exception;
1256
1257 if (seg_desc.type & 4) {
1258 /* conforming */
1259 if (dpl > cpl)
1260 goto exception;
1261 } else {
1262 /* nonconforming */
1263 if (rpl > cpl || dpl != cpl)
1264 goto exception;
1265 }
1266 /* CS(RPL) <- CPL */
1267 selector = (selector & 0xfffc) | cpl;
1268 break;
1269 case VCPU_SREG_TR:
1270 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1271 goto exception;
1272 break;
1273 case VCPU_SREG_LDTR:
1274 if (seg_desc.s || seg_desc.type != 2)
1275 goto exception;
1276 break;
1277 default: /* DS, ES, FS, or GS */
1278 /*
1279 * segment is not a data or readable code segment or
1280 * ((segment is a data or nonconforming code segment)
1281 * and (both RPL and CPL > DPL))
1282 */
1283 if ((seg_desc.type & 0xa) == 0x8 ||
1284 (((seg_desc.type & 0xc) != 0xc) &&
1285 (rpl > dpl && cpl > dpl)))
1286 goto exception;
1287 break;
1288 }
1289
1290 if (seg_desc.s) {
1291 /* mark segment as accessed */
1292 seg_desc.type |= 1;
1293 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1294 if (ret != X86EMUL_CONTINUE)
1295 return ret;
1296 }
1297load:
1298 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1299 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
1300 return X86EMUL_CONTINUE;
1301exception:
1302 emulate_exception(ctxt, err_vec, err_code, true);
1303 return X86EMUL_PROPAGATE_FAULT;
1304}
1305
1306static void write_register_operand(struct operand *op)
1307{
1308 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1309 switch (op->bytes) {
1310 case 1:
1311 *(u8 *)op->addr.reg = (u8)op->val;
1312 break;
1313 case 2:
1314 *(u16 *)op->addr.reg = (u16)op->val;
1315 break;
1316 case 4:
1317 *op->addr.reg = (u32)op->val;
1318 break; /* 64b: zero-extend */
1319 case 8:
1320 *op->addr.reg = op->val;
1321 break;
1322 }
1323}
1324
1325static inline int writeback(struct x86_emulate_ctxt *ctxt,
1326 struct x86_emulate_ops *ops)
1327{
1328 int rc;
1329 struct decode_cache *c = &ctxt->decode;
1330
1331 switch (c->dst.type) {
1332 case OP_REG:
1333 write_register_operand(&c->dst);
1334 break;
1335 case OP_MEM:
1336 if (c->lock_prefix)
1337 rc = segmented_cmpxchg(ctxt,
1338 c->dst.addr.mem,
1339 &c->dst.orig_val,
1340 &c->dst.val,
1341 c->dst.bytes);
1342 else
1343 rc = segmented_write(ctxt,
1344 c->dst.addr.mem,
1345 &c->dst.val,
1346 c->dst.bytes);
1347 if (rc != X86EMUL_CONTINUE)
1348 return rc;
1349 break;
1350 case OP_XMM:
1351 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1352 break;
1353 case OP_NONE:
1354 /* no writeback */
1355 break;
1356 default:
1357 break;
1358 }
1359 return X86EMUL_CONTINUE;
1360}
1361
1362static int em_push(struct x86_emulate_ctxt *ctxt)
1363{
1364 struct decode_cache *c = &ctxt->decode;
1365 struct segmented_address addr;
1366
1367 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1368 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1369 addr.seg = VCPU_SREG_SS;
1370
1371 /* Disable writeback. */
1372 c->dst.type = OP_NONE;
1373 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1374}
1375
1376static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1377 struct x86_emulate_ops *ops,
1378 void *dest, int len)
1379{
1380 struct decode_cache *c = &ctxt->decode;
1381 int rc;
1382 struct segmented_address addr;
1383
1384 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1385 addr.seg = VCPU_SREG_SS;
1386 rc = segmented_read(ctxt, addr, dest, len);
1387 if (rc != X86EMUL_CONTINUE)
1388 return rc;
1389
1390 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1391 return rc;
1392}
1393
1394static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1395 struct x86_emulate_ops *ops,
1396 void *dest, int len)
1397{
1398 int rc;
1399 unsigned long val, change_mask;
1400 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1401 int cpl = ops->cpl(ctxt->vcpu);
1402
1403 rc = emulate_pop(ctxt, ops, &val, len);
1404 if (rc != X86EMUL_CONTINUE)
1405 return rc;
1406
1407 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1408 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1409
1410 switch(ctxt->mode) {
1411 case X86EMUL_MODE_PROT64:
1412 case X86EMUL_MODE_PROT32:
1413 case X86EMUL_MODE_PROT16:
1414 if (cpl == 0)
1415 change_mask |= EFLG_IOPL;
1416 if (cpl <= iopl)
1417 change_mask |= EFLG_IF;
1418 break;
1419 case X86EMUL_MODE_VM86:
1420 if (iopl < 3)
1421 return emulate_gp(ctxt, 0);
1422 change_mask |= EFLG_IF;
1423 break;
1424 default: /* real mode */
1425 change_mask |= (EFLG_IOPL | EFLG_IF);
1426 break;
1427 }
1428
1429 *(unsigned long *)dest =
1430 (ctxt->eflags & ~change_mask) | (val & change_mask);
1431
1432 return rc;
1433}
1434
1435static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1436 struct x86_emulate_ops *ops, int seg)
1437{
1438 struct decode_cache *c = &ctxt->decode;
1439
1440 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1441
1442 return em_push(ctxt);
1443}
1444
1445static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1446 struct x86_emulate_ops *ops, int seg)
1447{
1448 struct decode_cache *c = &ctxt->decode;
1449 unsigned long selector;
1450 int rc;
1451
1452 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1453 if (rc != X86EMUL_CONTINUE)
1454 return rc;
1455
1456 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1457 return rc;
1458}
1459
1460static int emulate_pusha(struct x86_emulate_ctxt *ctxt)
1461{
1462 struct decode_cache *c = &ctxt->decode;
1463 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1464 int rc = X86EMUL_CONTINUE;
1465 int reg = VCPU_REGS_RAX;
1466
1467 while (reg <= VCPU_REGS_RDI) {
1468 (reg == VCPU_REGS_RSP) ?
1469 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1470
1471 rc = em_push(ctxt);
1472 if (rc != X86EMUL_CONTINUE)
1473 return rc;
1474
1475 ++reg;
1476 }
1477
1478 return rc;
1479}
1480
1481static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1482 struct x86_emulate_ops *ops)
1483{
1484 struct decode_cache *c = &ctxt->decode;
1485 int rc = X86EMUL_CONTINUE;
1486 int reg = VCPU_REGS_RDI;
1487
1488 while (reg >= VCPU_REGS_RAX) {
1489 if (reg == VCPU_REGS_RSP) {
1490 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1491 c->op_bytes);
1492 --reg;
1493 }
1494
1495 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1496 if (rc != X86EMUL_CONTINUE)
1497 break;
1498 --reg;
1499 }
1500 return rc;
1501}
1502
1503int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1504 struct x86_emulate_ops *ops, int irq)
1505{
1506 struct decode_cache *c = &ctxt->decode;
1507 int rc;
1508 struct desc_ptr dt;
1509 gva_t cs_addr;
1510 gva_t eip_addr;
1511 u16 cs, eip;
1512
1513 /* TODO: Add limit checks */
1514 c->src.val = ctxt->eflags;
1515 rc = em_push(ctxt);
1516 if (rc != X86EMUL_CONTINUE)
1517 return rc;
1518
1519 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1520
1521 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1522 rc = em_push(ctxt);
1523 if (rc != X86EMUL_CONTINUE)
1524 return rc;
1525
1526 c->src.val = c->eip;
1527 rc = em_push(ctxt);
1528 if (rc != X86EMUL_CONTINUE)
1529 return rc;
1530
1531 ops->get_idt(&dt, ctxt->vcpu);
1532
1533 eip_addr = dt.address + (irq << 2);
1534 cs_addr = dt.address + (irq << 2) + 2;
1535
1536 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
1537 if (rc != X86EMUL_CONTINUE)
1538 return rc;
1539
1540 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
1541 if (rc != X86EMUL_CONTINUE)
1542 return rc;
1543
1544 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1545 if (rc != X86EMUL_CONTINUE)
1546 return rc;
1547
1548 c->eip = eip;
1549
1550 return rc;
1551}
1552
1553static int emulate_int(struct x86_emulate_ctxt *ctxt,
1554 struct x86_emulate_ops *ops, int irq)
1555{
1556 switch(ctxt->mode) {
1557 case X86EMUL_MODE_REAL:
1558 return emulate_int_real(ctxt, ops, irq);
1559 case X86EMUL_MODE_VM86:
1560 case X86EMUL_MODE_PROT16:
1561 case X86EMUL_MODE_PROT32:
1562 case X86EMUL_MODE_PROT64:
1563 default:
1564 /* Protected mode interrupts unimplemented yet */
1565 return X86EMUL_UNHANDLEABLE;
1566 }
1567}
1568
1569static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1570 struct x86_emulate_ops *ops)
1571{
1572 struct decode_cache *c = &ctxt->decode;
1573 int rc = X86EMUL_CONTINUE;
1574 unsigned long temp_eip = 0;
1575 unsigned long temp_eflags = 0;
1576 unsigned long cs = 0;
1577 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1578 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1579 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1580 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1581
1582 /* TODO: Add stack limit check */
1583
1584 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1585
1586 if (rc != X86EMUL_CONTINUE)
1587 return rc;
1588
1589 if (temp_eip & ~0xffff)
1590 return emulate_gp(ctxt, 0);
1591
1592 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1593
1594 if (rc != X86EMUL_CONTINUE)
1595 return rc;
1596
1597 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1598
1599 if (rc != X86EMUL_CONTINUE)
1600 return rc;
1601
1602 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1603
1604 if (rc != X86EMUL_CONTINUE)
1605 return rc;
1606
1607 c->eip = temp_eip;
1608
1609
1610 if (c->op_bytes == 4)
1611 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1612 else if (c->op_bytes == 2) {
1613 ctxt->eflags &= ~0xffff;
1614 ctxt->eflags |= temp_eflags;
1615 }
1616
1617 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1618 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1619
1620 return rc;
1621}
1622
1623static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1624 struct x86_emulate_ops* ops)
1625{
1626 switch(ctxt->mode) {
1627 case X86EMUL_MODE_REAL:
1628 return emulate_iret_real(ctxt, ops);
1629 case X86EMUL_MODE_VM86:
1630 case X86EMUL_MODE_PROT16:
1631 case X86EMUL_MODE_PROT32:
1632 case X86EMUL_MODE_PROT64:
1633 default:
1634 /* iret from protected mode unimplemented yet */
1635 return X86EMUL_UNHANDLEABLE;
1636 }
1637}
1638
1639static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1640 struct x86_emulate_ops *ops)
1641{
1642 struct decode_cache *c = &ctxt->decode;
1643
1644 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1645}
1646
1647static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1648{
1649 struct decode_cache *c = &ctxt->decode;
1650 switch (c->modrm_reg) {
1651 case 0: /* rol */
1652 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1653 break;
1654 case 1: /* ror */
1655 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1656 break;
1657 case 2: /* rcl */
1658 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1659 break;
1660 case 3: /* rcr */
1661 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1662 break;
1663 case 4: /* sal/shl */
1664 case 6: /* sal/shl */
1665 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1666 break;
1667 case 5: /* shr */
1668 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1669 break;
1670 case 7: /* sar */
1671 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1672 break;
1673 }
1674}
1675
1676static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1677 struct x86_emulate_ops *ops)
1678{
1679 struct decode_cache *c = &ctxt->decode;
1680 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1681 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1682 u8 de = 0;
1683
1684 switch (c->modrm_reg) {
1685 case 0 ... 1: /* test */
1686 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1687 break;
1688 case 2: /* not */
1689 c->dst.val = ~c->dst.val;
1690 break;
1691 case 3: /* neg */
1692 emulate_1op("neg", c->dst, ctxt->eflags);
1693 break;
1694 case 4: /* mul */
1695 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1696 break;
1697 case 5: /* imul */
1698 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1699 break;
1700 case 6: /* div */
1701 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1702 ctxt->eflags, de);
1703 break;
1704 case 7: /* idiv */
1705 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1706 ctxt->eflags, de);
1707 break;
1708 default:
1709 return X86EMUL_UNHANDLEABLE;
1710 }
1711 if (de)
1712 return emulate_de(ctxt);
1713 return X86EMUL_CONTINUE;
1714}
1715
1716static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
1717{
1718 struct decode_cache *c = &ctxt->decode;
1719 int rc = X86EMUL_CONTINUE;
1720
1721 switch (c->modrm_reg) {
1722 case 0: /* inc */
1723 emulate_1op("inc", c->dst, ctxt->eflags);
1724 break;
1725 case 1: /* dec */
1726 emulate_1op("dec", c->dst, ctxt->eflags);
1727 break;
1728 case 2: /* call near abs */ {
1729 long int old_eip;
1730 old_eip = c->eip;
1731 c->eip = c->src.val;
1732 c->src.val = old_eip;
1733 rc = em_push(ctxt);
1734 break;
1735 }
1736 case 4: /* jmp abs */
1737 c->eip = c->src.val;
1738 break;
1739 case 6: /* push */
1740 rc = em_push(ctxt);
1741 break;
1742 }
1743 return rc;
1744}
1745
1746static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1747 struct x86_emulate_ops *ops)
1748{
1749 struct decode_cache *c = &ctxt->decode;
1750 u64 old = c->dst.orig_val64;
1751
1752 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1753 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1754 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1755 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1756 ctxt->eflags &= ~EFLG_ZF;
1757 } else {
1758 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1759 (u32) c->regs[VCPU_REGS_RBX];
1760
1761 ctxt->eflags |= EFLG_ZF;
1762 }
1763 return X86EMUL_CONTINUE;
1764}
1765
1766static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1767 struct x86_emulate_ops *ops)
1768{
1769 struct decode_cache *c = &ctxt->decode;
1770 int rc;
1771 unsigned long cs;
1772
1773 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1774 if (rc != X86EMUL_CONTINUE)
1775 return rc;
1776 if (c->op_bytes == 4)
1777 c->eip = (u32)c->eip;
1778 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1779 if (rc != X86EMUL_CONTINUE)
1780 return rc;
1781 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1782 return rc;
1783}
1784
1785static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1786 struct x86_emulate_ops *ops, int seg)
1787{
1788 struct decode_cache *c = &ctxt->decode;
1789 unsigned short sel;
1790 int rc;
1791
1792 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1793
1794 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1795 if (rc != X86EMUL_CONTINUE)
1796 return rc;
1797
1798 c->dst.val = c->src.val;
1799 return rc;
1800}
1801
1802static inline void
1803setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1804 struct x86_emulate_ops *ops, struct desc_struct *cs,
1805 struct desc_struct *ss)
1806{
1807 memset(cs, 0, sizeof(struct desc_struct));
1808 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
1809 memset(ss, 0, sizeof(struct desc_struct));
1810
1811 cs->l = 0; /* will be adjusted later */
1812 set_desc_base(cs, 0); /* flat segment */
1813 cs->g = 1; /* 4kb granularity */
1814 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1815 cs->type = 0x0b; /* Read, Execute, Accessed */
1816 cs->s = 1;
1817 cs->dpl = 0; /* will be adjusted later */
1818 cs->p = 1;
1819 cs->d = 1;
1820
1821 set_desc_base(ss, 0); /* flat segment */
1822 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1823 ss->g = 1; /* 4kb granularity */
1824 ss->s = 1;
1825 ss->type = 0x03; /* Read/Write, Accessed */
1826 ss->d = 1; /* 32bit stack segment */
1827 ss->dpl = 0;
1828 ss->p = 1;
1829}
1830
1831static int
1832emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1833{
1834 struct decode_cache *c = &ctxt->decode;
1835 struct desc_struct cs, ss;
1836 u64 msr_data;
1837 u16 cs_sel, ss_sel;
1838
1839 /* syscall is not available in real mode */
1840 if (ctxt->mode == X86EMUL_MODE_REAL ||
1841 ctxt->mode == X86EMUL_MODE_VM86)
1842 return emulate_ud(ctxt);
1843
1844 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1845
1846 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1847 msr_data >>= 32;
1848 cs_sel = (u16)(msr_data & 0xfffc);
1849 ss_sel = (u16)(msr_data + 8);
1850
1851 if (is_long_mode(ctxt->vcpu)) {
1852 cs.d = 0;
1853 cs.l = 1;
1854 }
1855 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
1856 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1857 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
1858 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1859
1860 c->regs[VCPU_REGS_RCX] = c->eip;
1861 if (is_long_mode(ctxt->vcpu)) {
1862#ifdef CONFIG_X86_64
1863 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1864
1865 ops->get_msr(ctxt->vcpu,
1866 ctxt->mode == X86EMUL_MODE_PROT64 ?
1867 MSR_LSTAR : MSR_CSTAR, &msr_data);
1868 c->eip = msr_data;
1869
1870 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1871 ctxt->eflags &= ~(msr_data | EFLG_RF);
1872#endif
1873 } else {
1874 /* legacy mode */
1875 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1876 c->eip = (u32)msr_data;
1877
1878 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1879 }
1880
1881 return X86EMUL_CONTINUE;
1882}
1883
1884static int
1885emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1886{
1887 struct decode_cache *c = &ctxt->decode;
1888 struct desc_struct cs, ss;
1889 u64 msr_data;
1890 u16 cs_sel, ss_sel;
1891
1892 /* inject #GP if in real mode */
1893 if (ctxt->mode == X86EMUL_MODE_REAL)
1894 return emulate_gp(ctxt, 0);
1895
1896 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1897 * Therefore, we inject an #UD.
1898 */
1899 if (ctxt->mode == X86EMUL_MODE_PROT64)
1900 return emulate_ud(ctxt);
1901
1902 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1903
1904 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1905 switch (ctxt->mode) {
1906 case X86EMUL_MODE_PROT32:
1907 if ((msr_data & 0xfffc) == 0x0)
1908 return emulate_gp(ctxt, 0);
1909 break;
1910 case X86EMUL_MODE_PROT64:
1911 if (msr_data == 0x0)
1912 return emulate_gp(ctxt, 0);
1913 break;
1914 }
1915
1916 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1917 cs_sel = (u16)msr_data;
1918 cs_sel &= ~SELECTOR_RPL_MASK;
1919 ss_sel = cs_sel + 8;
1920 ss_sel &= ~SELECTOR_RPL_MASK;
1921 if (ctxt->mode == X86EMUL_MODE_PROT64
1922 || is_long_mode(ctxt->vcpu)) {
1923 cs.d = 0;
1924 cs.l = 1;
1925 }
1926
1927 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
1928 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1929 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
1930 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1931
1932 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1933 c->eip = msr_data;
1934
1935 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1936 c->regs[VCPU_REGS_RSP] = msr_data;
1937
1938 return X86EMUL_CONTINUE;
1939}
1940
1941static int
1942emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1943{
1944 struct decode_cache *c = &ctxt->decode;
1945 struct desc_struct cs, ss;
1946 u64 msr_data;
1947 int usermode;
1948 u16 cs_sel, ss_sel;
1949
1950 /* inject #GP if in real mode or Virtual 8086 mode */
1951 if (ctxt->mode == X86EMUL_MODE_REAL ||
1952 ctxt->mode == X86EMUL_MODE_VM86)
1953 return emulate_gp(ctxt, 0);
1954
1955 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1956
1957 if ((c->rex_prefix & 0x8) != 0x0)
1958 usermode = X86EMUL_MODE_PROT64;
1959 else
1960 usermode = X86EMUL_MODE_PROT32;
1961
1962 cs.dpl = 3;
1963 ss.dpl = 3;
1964 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1965 switch (usermode) {
1966 case X86EMUL_MODE_PROT32:
1967 cs_sel = (u16)(msr_data + 16);
1968 if ((msr_data & 0xfffc) == 0x0)
1969 return emulate_gp(ctxt, 0);
1970 ss_sel = (u16)(msr_data + 24);
1971 break;
1972 case X86EMUL_MODE_PROT64:
1973 cs_sel = (u16)(msr_data + 32);
1974 if (msr_data == 0x0)
1975 return emulate_gp(ctxt, 0);
1976 ss_sel = cs_sel + 8;
1977 cs.d = 0;
1978 cs.l = 1;
1979 break;
1980 }
1981 cs_sel |= SELECTOR_RPL_MASK;
1982 ss_sel |= SELECTOR_RPL_MASK;
1983
1984 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
1985 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1986 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
1987 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1988
1989 c->eip = c->regs[VCPU_REGS_RDX];
1990 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1991
1992 return X86EMUL_CONTINUE;
1993}
1994
1995static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1996 struct x86_emulate_ops *ops)
1997{
1998 int iopl;
1999 if (ctxt->mode == X86EMUL_MODE_REAL)
2000 return false;
2001 if (ctxt->mode == X86EMUL_MODE_VM86)
2002 return true;
2003 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2004 return ops->cpl(ctxt->vcpu) > iopl;
2005}
2006
2007static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2008 struct x86_emulate_ops *ops,
2009 u16 port, u16 len)
2010{
2011 struct desc_struct tr_seg;
2012 u32 base3;
2013 int r;
2014 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
2015 unsigned mask = (1 << len) - 1;
2016 unsigned long base;
2017
2018 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
2019 if (!tr_seg.p)
2020 return false;
2021 if (desc_limit_scaled(&tr_seg) < 103)
2022 return false;
2023 base = get_desc_base(&tr_seg);
2024#ifdef CONFIG_X86_64
2025 base |= ((u64)base3) << 32;
2026#endif
2027 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
2028 if (r != X86EMUL_CONTINUE)
2029 return false;
2030 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2031 return false;
2032 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
2033 NULL);
2034 if (r != X86EMUL_CONTINUE)
2035 return false;
2036 if ((perm >> bit_idx) & mask)
2037 return false;
2038 return true;
2039}
2040
2041static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2042 struct x86_emulate_ops *ops,
2043 u16 port, u16 len)
2044{
2045 if (ctxt->perm_ok)
2046 return true;
2047
2048 if (emulator_bad_iopl(ctxt, ops))
2049 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2050 return false;
2051
2052 ctxt->perm_ok = true;
2053
2054 return true;
2055}
2056
2057static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2058 struct x86_emulate_ops *ops,
2059 struct tss_segment_16 *tss)
2060{
2061 struct decode_cache *c = &ctxt->decode;
2062
2063 tss->ip = c->eip;
2064 tss->flag = ctxt->eflags;
2065 tss->ax = c->regs[VCPU_REGS_RAX];
2066 tss->cx = c->regs[VCPU_REGS_RCX];
2067 tss->dx = c->regs[VCPU_REGS_RDX];
2068 tss->bx = c->regs[VCPU_REGS_RBX];
2069 tss->sp = c->regs[VCPU_REGS_RSP];
2070 tss->bp = c->regs[VCPU_REGS_RBP];
2071 tss->si = c->regs[VCPU_REGS_RSI];
2072 tss->di = c->regs[VCPU_REGS_RDI];
2073
2074 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2075 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2076 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2077 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2078 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2079}
2080
2081static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2082 struct x86_emulate_ops *ops,
2083 struct tss_segment_16 *tss)
2084{
2085 struct decode_cache *c = &ctxt->decode;
2086 int ret;
2087
2088 c->eip = tss->ip;
2089 ctxt->eflags = tss->flag | 2;
2090 c->regs[VCPU_REGS_RAX] = tss->ax;
2091 c->regs[VCPU_REGS_RCX] = tss->cx;
2092 c->regs[VCPU_REGS_RDX] = tss->dx;
2093 c->regs[VCPU_REGS_RBX] = tss->bx;
2094 c->regs[VCPU_REGS_RSP] = tss->sp;
2095 c->regs[VCPU_REGS_RBP] = tss->bp;
2096 c->regs[VCPU_REGS_RSI] = tss->si;
2097 c->regs[VCPU_REGS_RDI] = tss->di;
2098
2099 /*
2100 * SDM says that segment selectors are loaded before segment
2101 * descriptors
2102 */
2103 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2104 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2105 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2106 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2107 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2108
2109 /*
2110 * Now load segment descriptors. If fault happenes at this stage
2111 * it is handled in a context of new task
2112 */
2113 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2114 if (ret != X86EMUL_CONTINUE)
2115 return ret;
2116 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2117 if (ret != X86EMUL_CONTINUE)
2118 return ret;
2119 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2120 if (ret != X86EMUL_CONTINUE)
2121 return ret;
2122 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2123 if (ret != X86EMUL_CONTINUE)
2124 return ret;
2125 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2126 if (ret != X86EMUL_CONTINUE)
2127 return ret;
2128
2129 return X86EMUL_CONTINUE;
2130}
2131
2132static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2133 struct x86_emulate_ops *ops,
2134 u16 tss_selector, u16 old_tss_sel,
2135 ulong old_tss_base, struct desc_struct *new_desc)
2136{
2137 struct tss_segment_16 tss_seg;
2138 int ret;
2139 u32 new_tss_base = get_desc_base(new_desc);
2140
2141 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2142 &ctxt->exception);
2143 if (ret != X86EMUL_CONTINUE)
2144 /* FIXME: need to provide precise fault address */
2145 return ret;
2146
2147 save_state_to_tss16(ctxt, ops, &tss_seg);
2148
2149 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2150 &ctxt->exception);
2151 if (ret != X86EMUL_CONTINUE)
2152 /* FIXME: need to provide precise fault address */
2153 return ret;
2154
2155 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2156 &ctxt->exception);
2157 if (ret != X86EMUL_CONTINUE)
2158 /* FIXME: need to provide precise fault address */
2159 return ret;
2160
2161 if (old_tss_sel != 0xffff) {
2162 tss_seg.prev_task_link = old_tss_sel;
2163
2164 ret = ops->write_std(new_tss_base,
2165 &tss_seg.prev_task_link,
2166 sizeof tss_seg.prev_task_link,
2167 ctxt->vcpu, &ctxt->exception);
2168 if (ret != X86EMUL_CONTINUE)
2169 /* FIXME: need to provide precise fault address */
2170 return ret;
2171 }
2172
2173 return load_state_from_tss16(ctxt, ops, &tss_seg);
2174}
2175
2176static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2177 struct x86_emulate_ops *ops,
2178 struct tss_segment_32 *tss)
2179{
2180 struct decode_cache *c = &ctxt->decode;
2181
2182 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2183 tss->eip = c->eip;
2184 tss->eflags = ctxt->eflags;
2185 tss->eax = c->regs[VCPU_REGS_RAX];
2186 tss->ecx = c->regs[VCPU_REGS_RCX];
2187 tss->edx = c->regs[VCPU_REGS_RDX];
2188 tss->ebx = c->regs[VCPU_REGS_RBX];
2189 tss->esp = c->regs[VCPU_REGS_RSP];
2190 tss->ebp = c->regs[VCPU_REGS_RBP];
2191 tss->esi = c->regs[VCPU_REGS_RSI];
2192 tss->edi = c->regs[VCPU_REGS_RDI];
2193
2194 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2195 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2196 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2197 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2198 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2199 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2200 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2201}
2202
2203static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2204 struct x86_emulate_ops *ops,
2205 struct tss_segment_32 *tss)
2206{
2207 struct decode_cache *c = &ctxt->decode;
2208 int ret;
2209
2210 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
2211 return emulate_gp(ctxt, 0);
2212 c->eip = tss->eip;
2213 ctxt->eflags = tss->eflags | 2;
2214 c->regs[VCPU_REGS_RAX] = tss->eax;
2215 c->regs[VCPU_REGS_RCX] = tss->ecx;
2216 c->regs[VCPU_REGS_RDX] = tss->edx;
2217 c->regs[VCPU_REGS_RBX] = tss->ebx;
2218 c->regs[VCPU_REGS_RSP] = tss->esp;
2219 c->regs[VCPU_REGS_RBP] = tss->ebp;
2220 c->regs[VCPU_REGS_RSI] = tss->esi;
2221 c->regs[VCPU_REGS_RDI] = tss->edi;
2222
2223 /*
2224 * SDM says that segment selectors are loaded before segment
2225 * descriptors
2226 */
2227 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2228 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2229 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2230 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2231 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2232 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2233 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2234
2235 /*
2236 * Now load segment descriptors. If fault happenes at this stage
2237 * it is handled in a context of new task
2238 */
2239 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2240 if (ret != X86EMUL_CONTINUE)
2241 return ret;
2242 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2243 if (ret != X86EMUL_CONTINUE)
2244 return ret;
2245 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2246 if (ret != X86EMUL_CONTINUE)
2247 return ret;
2248 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2249 if (ret != X86EMUL_CONTINUE)
2250 return ret;
2251 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2252 if (ret != X86EMUL_CONTINUE)
2253 return ret;
2254 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2255 if (ret != X86EMUL_CONTINUE)
2256 return ret;
2257 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2258 if (ret != X86EMUL_CONTINUE)
2259 return ret;
2260
2261 return X86EMUL_CONTINUE;
2262}
2263
2264static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2265 struct x86_emulate_ops *ops,
2266 u16 tss_selector, u16 old_tss_sel,
2267 ulong old_tss_base, struct desc_struct *new_desc)
2268{
2269 struct tss_segment_32 tss_seg;
2270 int ret;
2271 u32 new_tss_base = get_desc_base(new_desc);
2272
2273 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2274 &ctxt->exception);
2275 if (ret != X86EMUL_CONTINUE)
2276 /* FIXME: need to provide precise fault address */
2277 return ret;
2278
2279 save_state_to_tss32(ctxt, ops, &tss_seg);
2280
2281 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2282 &ctxt->exception);
2283 if (ret != X86EMUL_CONTINUE)
2284 /* FIXME: need to provide precise fault address */
2285 return ret;
2286
2287 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2288 &ctxt->exception);
2289 if (ret != X86EMUL_CONTINUE)
2290 /* FIXME: need to provide precise fault address */
2291 return ret;
2292
2293 if (old_tss_sel != 0xffff) {
2294 tss_seg.prev_task_link = old_tss_sel;
2295
2296 ret = ops->write_std(new_tss_base,
2297 &tss_seg.prev_task_link,
2298 sizeof tss_seg.prev_task_link,
2299 ctxt->vcpu, &ctxt->exception);
2300 if (ret != X86EMUL_CONTINUE)
2301 /* FIXME: need to provide precise fault address */
2302 return ret;
2303 }
2304
2305 return load_state_from_tss32(ctxt, ops, &tss_seg);
2306}
2307
2308static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2309 struct x86_emulate_ops *ops,
2310 u16 tss_selector, int reason,
2311 bool has_error_code, u32 error_code)
2312{
2313 struct desc_struct curr_tss_desc, next_tss_desc;
2314 int ret;
2315 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2316 ulong old_tss_base =
2317 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2318 u32 desc_limit;
2319
2320 /* FIXME: old_tss_base == ~0 ? */
2321
2322 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2323 if (ret != X86EMUL_CONTINUE)
2324 return ret;
2325 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2326 if (ret != X86EMUL_CONTINUE)
2327 return ret;
2328
2329 /* FIXME: check that next_tss_desc is tss */
2330
2331 if (reason != TASK_SWITCH_IRET) {
2332 if ((tss_selector & 3) > next_tss_desc.dpl ||
2333 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2334 return emulate_gp(ctxt, 0);
2335 }
2336
2337 desc_limit = desc_limit_scaled(&next_tss_desc);
2338 if (!next_tss_desc.p ||
2339 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2340 desc_limit < 0x2b)) {
2341 emulate_ts(ctxt, tss_selector & 0xfffc);
2342 return X86EMUL_PROPAGATE_FAULT;
2343 }
2344
2345 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2346 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2347 write_segment_descriptor(ctxt, ops, old_tss_sel,
2348 &curr_tss_desc);
2349 }
2350
2351 if (reason == TASK_SWITCH_IRET)
2352 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2353
2354 /* set back link to prev task only if NT bit is set in eflags
2355 note that old_tss_sel is not used afetr this point */
2356 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2357 old_tss_sel = 0xffff;
2358
2359 if (next_tss_desc.type & 8)
2360 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2361 old_tss_base, &next_tss_desc);
2362 else
2363 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2364 old_tss_base, &next_tss_desc);
2365 if (ret != X86EMUL_CONTINUE)
2366 return ret;
2367
2368 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2369 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2370
2371 if (reason != TASK_SWITCH_IRET) {
2372 next_tss_desc.type |= (1 << 1); /* set busy flag */
2373 write_segment_descriptor(ctxt, ops, tss_selector,
2374 &next_tss_desc);
2375 }
2376
2377 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2378 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
2379 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2380
2381 if (has_error_code) {
2382 struct decode_cache *c = &ctxt->decode;
2383
2384 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2385 c->lock_prefix = 0;
2386 c->src.val = (unsigned long) error_code;
2387 ret = em_push(ctxt);
2388 }
2389
2390 return ret;
2391}
2392
2393int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2394 u16 tss_selector, int reason,
2395 bool has_error_code, u32 error_code)
2396{
2397 struct x86_emulate_ops *ops = ctxt->ops;
2398 struct decode_cache *c = &ctxt->decode;
2399 int rc;
2400
2401 c->eip = ctxt->eip;
2402 c->dst.type = OP_NONE;
2403
2404 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2405 has_error_code, error_code);
2406
2407 if (rc == X86EMUL_CONTINUE)
2408 ctxt->eip = c->eip;
2409
2410 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2411}
2412
2413static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2414 int reg, struct operand *op)
2415{
2416 struct decode_cache *c = &ctxt->decode;
2417 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2418
2419 register_address_increment(c, &c->regs[reg], df * op->bytes);
2420 op->addr.mem.ea = register_address(c, c->regs[reg]);
2421 op->addr.mem.seg = seg;
2422}
2423
2424static int em_das(struct x86_emulate_ctxt *ctxt)
2425{
2426 struct decode_cache *c = &ctxt->decode;
2427 u8 al, old_al;
2428 bool af, cf, old_cf;
2429
2430 cf = ctxt->eflags & X86_EFLAGS_CF;
2431 al = c->dst.val;
2432
2433 old_al = al;
2434 old_cf = cf;
2435 cf = false;
2436 af = ctxt->eflags & X86_EFLAGS_AF;
2437 if ((al & 0x0f) > 9 || af) {
2438 al -= 6;
2439 cf = old_cf | (al >= 250);
2440 af = true;
2441 } else {
2442 af = false;
2443 }
2444 if (old_al > 0x99 || old_cf) {
2445 al -= 0x60;
2446 cf = true;
2447 }
2448
2449 c->dst.val = al;
2450 /* Set PF, ZF, SF */
2451 c->src.type = OP_IMM;
2452 c->src.val = 0;
2453 c->src.bytes = 1;
2454 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2455 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2456 if (cf)
2457 ctxt->eflags |= X86_EFLAGS_CF;
2458 if (af)
2459 ctxt->eflags |= X86_EFLAGS_AF;
2460 return X86EMUL_CONTINUE;
2461}
2462
2463static int em_call_far(struct x86_emulate_ctxt *ctxt)
2464{
2465 struct decode_cache *c = &ctxt->decode;
2466 u16 sel, old_cs;
2467 ulong old_eip;
2468 int rc;
2469
2470 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2471 old_eip = c->eip;
2472
2473 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2474 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2475 return X86EMUL_CONTINUE;
2476
2477 c->eip = 0;
2478 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2479
2480 c->src.val = old_cs;
2481 rc = em_push(ctxt);
2482 if (rc != X86EMUL_CONTINUE)
2483 return rc;
2484
2485 c->src.val = old_eip;
2486 return em_push(ctxt);
2487}
2488
2489static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2490{
2491 struct decode_cache *c = &ctxt->decode;
2492 int rc;
2493
2494 c->dst.type = OP_REG;
2495 c->dst.addr.reg = &c->eip;
2496 c->dst.bytes = c->op_bytes;
2497 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2498 if (rc != X86EMUL_CONTINUE)
2499 return rc;
2500 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2501 return X86EMUL_CONTINUE;
2502}
2503
2504static int em_imul(struct x86_emulate_ctxt *ctxt)
2505{
2506 struct decode_cache *c = &ctxt->decode;
2507
2508 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2509 return X86EMUL_CONTINUE;
2510}
2511
2512static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2513{
2514 struct decode_cache *c = &ctxt->decode;
2515
2516 c->dst.val = c->src2.val;
2517 return em_imul(ctxt);
2518}
2519
2520static int em_cwd(struct x86_emulate_ctxt *ctxt)
2521{
2522 struct decode_cache *c = &ctxt->decode;
2523
2524 c->dst.type = OP_REG;
2525 c->dst.bytes = c->src.bytes;
2526 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2527 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2528
2529 return X86EMUL_CONTINUE;
2530}
2531
2532static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2533{
2534 struct decode_cache *c = &ctxt->decode;
2535 u64 tsc = 0;
2536
2537 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2538 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2539 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2540 return X86EMUL_CONTINUE;
2541}
2542
2543static int em_mov(struct x86_emulate_ctxt *ctxt)
2544{
2545 struct decode_cache *c = &ctxt->decode;
2546 c->dst.val = c->src.val;
2547 return X86EMUL_CONTINUE;
2548}
2549
2550static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2551{
2552 struct decode_cache *c = &ctxt->decode;
2553 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2554 return X86EMUL_CONTINUE;
2555}
2556
2557static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2558{
2559 struct decode_cache *c = &ctxt->decode;
2560 int rc;
2561 ulong linear;
2562
2563 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2564 if (rc == X86EMUL_CONTINUE)
2565 emulate_invlpg(ctxt->vcpu, linear);
2566 /* Disable writeback. */
2567 c->dst.type = OP_NONE;
2568 return X86EMUL_CONTINUE;
2569}
2570
2571static bool valid_cr(int nr)
2572{
2573 switch (nr) {
2574 case 0:
2575 case 2 ... 4:
2576 case 8:
2577 return true;
2578 default:
2579 return false;
2580 }
2581}
2582
2583static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2584{
2585 struct decode_cache *c = &ctxt->decode;
2586
2587 if (!valid_cr(c->modrm_reg))
2588 return emulate_ud(ctxt);
2589
2590 return X86EMUL_CONTINUE;
2591}
2592
2593static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2594{
2595 struct decode_cache *c = &ctxt->decode;
2596 u64 new_val = c->src.val64;
2597 int cr = c->modrm_reg;
2598
2599 static u64 cr_reserved_bits[] = {
2600 0xffffffff00000000ULL,
2601 0, 0, 0, /* CR3 checked later */
2602 CR4_RESERVED_BITS,
2603 0, 0, 0,
2604 CR8_RESERVED_BITS,
2605 };
2606
2607 if (!valid_cr(cr))
2608 return emulate_ud(ctxt);
2609
2610 if (new_val & cr_reserved_bits[cr])
2611 return emulate_gp(ctxt, 0);
2612
2613 switch (cr) {
2614 case 0: {
2615 u64 cr4, efer;
2616 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2617 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2618 return emulate_gp(ctxt, 0);
2619
2620 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2621 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2622
2623 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2624 !(cr4 & X86_CR4_PAE))
2625 return emulate_gp(ctxt, 0);
2626
2627 break;
2628 }
2629 case 3: {
2630 u64 rsvd = 0;
2631
2632 if (is_long_mode(ctxt->vcpu))
2633 rsvd = CR3_L_MODE_RESERVED_BITS;
2634 else if (is_pae(ctxt->vcpu))
2635 rsvd = CR3_PAE_RESERVED_BITS;
2636 else if (is_paging(ctxt->vcpu))
2637 rsvd = CR3_NONPAE_RESERVED_BITS;
2638
2639 if (new_val & rsvd)
2640 return emulate_gp(ctxt, 0);
2641
2642 break;
2643 }
2644 case 4: {
2645 u64 cr4, efer;
2646
2647 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2648 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2649
2650 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2651 return emulate_gp(ctxt, 0);
2652
2653 break;
2654 }
2655 }
2656
2657 return X86EMUL_CONTINUE;
2658}
2659
2660static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2661{
2662 unsigned long dr7;
2663
2664 ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
2665
2666 /* Check if DR7.Global_Enable is set */
2667 return dr7 & (1 << 13);
2668}
2669
2670static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2671{
2672 struct decode_cache *c = &ctxt->decode;
2673 int dr = c->modrm_reg;
2674 u64 cr4;
2675
2676 if (dr > 7)
2677 return emulate_ud(ctxt);
2678
2679 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2680 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2681 return emulate_ud(ctxt);
2682
2683 if (check_dr7_gd(ctxt))
2684 return emulate_db(ctxt);
2685
2686 return X86EMUL_CONTINUE;
2687}
2688
2689static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2690{
2691 struct decode_cache *c = &ctxt->decode;
2692 u64 new_val = c->src.val64;
2693 int dr = c->modrm_reg;
2694
2695 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2696 return emulate_gp(ctxt, 0);
2697
2698 return check_dr_read(ctxt);
2699}
2700
2701static int check_svme(struct x86_emulate_ctxt *ctxt)
2702{
2703 u64 efer;
2704
2705 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2706
2707 if (!(efer & EFER_SVME))
2708 return emulate_ud(ctxt);
2709
2710 return X86EMUL_CONTINUE;
2711}
2712
2713static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2714{
2715 u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX);
2716
2717 /* Valid physical address? */
2718 if (rax & 0xffff000000000000)
2719 return emulate_gp(ctxt, 0);
2720
2721 return check_svme(ctxt);
2722}
2723
2724static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2725{
2726 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2727
2728 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu))
2729 return emulate_ud(ctxt);
2730
2731 return X86EMUL_CONTINUE;
2732}
2733
2734static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2735{
2736 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2737 u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
2738
2739 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
2740 (rcx > 3))
2741 return emulate_gp(ctxt, 0);
2742
2743 return X86EMUL_CONTINUE;
2744}
2745
2746static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2747{
2748 struct decode_cache *c = &ctxt->decode;
2749
2750 c->dst.bytes = min(c->dst.bytes, 4u);
2751 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2752 return emulate_gp(ctxt, 0);
2753
2754 return X86EMUL_CONTINUE;
2755}
2756
2757static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2758{
2759 struct decode_cache *c = &ctxt->decode;
2760
2761 c->src.bytes = min(c->src.bytes, 4u);
2762 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2763 return emulate_gp(ctxt, 0);
2764
2765 return X86EMUL_CONTINUE;
2766}
2767
2768#define D(_y) { .flags = (_y) }
2769#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2770#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2771 .check_perm = (_p) }
2772#define N D(0)
2773#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2774#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2775#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2776#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2777#define II(_f, _e, _i) \
2778 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2779#define IIP(_f, _e, _i, _p) \
2780 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2781 .check_perm = (_p) }
2782#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2783
2784#define D2bv(_f) D((_f) | ByteOp), D(_f)
2785#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2786#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2787
2788#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2789 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2790 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2791
2792static struct opcode group7_rm1[] = {
2793 DI(SrcNone | ModRM | Priv, monitor),
2794 DI(SrcNone | ModRM | Priv, mwait),
2795 N, N, N, N, N, N,
2796};
2797
2798static struct opcode group7_rm3[] = {
2799 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
2800 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
2801 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2802 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2803 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2804 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2805 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2806 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2807};
2808
2809static struct opcode group7_rm7[] = {
2810 N,
2811 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2812 N, N, N, N, N, N,
2813};
2814static struct opcode group1[] = {
2815 X7(D(Lock)), N
2816};
2817
2818static struct opcode group1A[] = {
2819 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2820};
2821
2822static struct opcode group3[] = {
2823 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2824 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2825 X4(D(SrcMem | ModRM)),
2826};
2827
2828static struct opcode group4[] = {
2829 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2830 N, N, N, N, N, N,
2831};
2832
2833static struct opcode group5[] = {
2834 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2835 D(SrcMem | ModRM | Stack),
2836 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2837 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2838 D(SrcMem | ModRM | Stack), N,
2839};
2840
2841static struct opcode group6[] = {
2842 DI(ModRM | Prot, sldt),
2843 DI(ModRM | Prot, str),
2844 DI(ModRM | Prot | Priv, lldt),
2845 DI(ModRM | Prot | Priv, ltr),
2846 N, N, N, N,
2847};
2848
2849static struct group_dual group7 = { {
2850 DI(ModRM | Mov | DstMem | Priv, sgdt),
2851 DI(ModRM | Mov | DstMem | Priv, sidt),
2852 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
2853 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2854 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2855 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
2856}, {
2857 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
2858 N, EXT(0, group7_rm3),
2859 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2860 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
2861} };
2862
2863static struct opcode group8[] = {
2864 N, N, N, N,
2865 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2866 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2867};
2868
2869static struct group_dual group9 = { {
2870 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2871}, {
2872 N, N, N, N, N, N, N, N,
2873} };
2874
2875static struct opcode group11[] = {
2876 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2877};
2878
2879static struct gprefix pfx_0f_6f_0f_7f = {
2880 N, N, N, I(Sse, em_movdqu),
2881};
2882
2883static struct opcode opcode_table[256] = {
2884 /* 0x00 - 0x07 */
2885 D6ALU(Lock),
2886 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2887 /* 0x08 - 0x0F */
2888 D6ALU(Lock),
2889 D(ImplicitOps | Stack | No64), N,
2890 /* 0x10 - 0x17 */
2891 D6ALU(Lock),
2892 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2893 /* 0x18 - 0x1F */
2894 D6ALU(Lock),
2895 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2896 /* 0x20 - 0x27 */
2897 D6ALU(Lock), N, N,
2898 /* 0x28 - 0x2F */
2899 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
2900 /* 0x30 - 0x37 */
2901 D6ALU(Lock), N, N,
2902 /* 0x38 - 0x3F */
2903 D6ALU(0), N, N,
2904 /* 0x40 - 0x4F */
2905 X16(D(DstReg)),
2906 /* 0x50 - 0x57 */
2907 X8(I(SrcReg | Stack, em_push)),
2908 /* 0x58 - 0x5F */
2909 X8(D(DstReg | Stack)),
2910 /* 0x60 - 0x67 */
2911 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2912 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2913 N, N, N, N,
2914 /* 0x68 - 0x6F */
2915 I(SrcImm | Mov | Stack, em_push),
2916 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
2917 I(SrcImmByte | Mov | Stack, em_push),
2918 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2919 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
2920 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
2921 /* 0x70 - 0x7F */
2922 X16(D(SrcImmByte)),
2923 /* 0x80 - 0x87 */
2924 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2925 G(DstMem | SrcImm | ModRM | Group, group1),
2926 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2927 G(DstMem | SrcImmByte | ModRM | Group, group1),
2928 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
2929 /* 0x88 - 0x8F */
2930 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2931 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
2932 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2933 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2934 /* 0x90 - 0x97 */
2935 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
2936 /* 0x98 - 0x9F */
2937 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
2938 I(SrcImmFAddr | No64, em_call_far), N,
2939 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
2940 /* 0xA0 - 0xA7 */
2941 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2942 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2943 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2944 D2bv(SrcSI | DstDI | String),
2945 /* 0xA8 - 0xAF */
2946 D2bv(DstAcc | SrcImm),
2947 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2948 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
2949 D2bv(SrcAcc | DstDI | String),
2950 /* 0xB0 - 0xB7 */
2951 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
2952 /* 0xB8 - 0xBF */
2953 X8(I(DstReg | SrcImm | Mov, em_mov)),
2954 /* 0xC0 - 0xC7 */
2955 D2bv(DstMem | SrcImmByte | ModRM),
2956 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2957 D(ImplicitOps | Stack),
2958 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
2959 G(ByteOp, group11), G(0, group11),
2960 /* 0xC8 - 0xCF */
2961 N, N, N, D(ImplicitOps | Stack),
2962 D(ImplicitOps), DI(SrcImmByte, intn),
2963 D(ImplicitOps | No64), DI(ImplicitOps, iret),
2964 /* 0xD0 - 0xD7 */
2965 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
2966 N, N, N, N,
2967 /* 0xD8 - 0xDF */
2968 N, N, N, N, N, N, N, N,
2969 /* 0xE0 - 0xE7 */
2970 X4(D(SrcImmByte)),
2971 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
2972 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
2973 /* 0xE8 - 0xEF */
2974 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2975 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2976 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
2977 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
2978 /* 0xF0 - 0xF7 */
2979 N, DI(ImplicitOps, icebp), N, N,
2980 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2981 G(ByteOp, group3), G(0, group3),
2982 /* 0xF8 - 0xFF */
2983 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2984 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2985};
2986
2987static struct opcode twobyte_table[256] = {
2988 /* 0x00 - 0x0F */
2989 G(0, group6), GD(0, &group7), N, N,
2990 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
2991 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
2992 N, D(ImplicitOps | ModRM), N, N,
2993 /* 0x10 - 0x1F */
2994 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2995 /* 0x20 - 0x2F */
2996 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
2997 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
2998 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
2999 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3000 N, N, N, N,
3001 N, N, N, N, N, N, N, N,
3002 /* 0x30 - 0x3F */
3003 DI(ImplicitOps | Priv, wrmsr),
3004 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3005 DI(ImplicitOps | Priv, rdmsr),
3006 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3007 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3008 N, N,
3009 N, N, N, N, N, N, N, N,
3010 /* 0x40 - 0x4F */
3011 X16(D(DstReg | SrcMem | ModRM | Mov)),
3012 /* 0x50 - 0x5F */
3013 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3014 /* 0x60 - 0x6F */
3015 N, N, N, N,
3016 N, N, N, N,
3017 N, N, N, N,
3018 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3019 /* 0x70 - 0x7F */
3020 N, N, N, N,
3021 N, N, N, N,
3022 N, N, N, N,
3023 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3024 /* 0x80 - 0x8F */
3025 X16(D(SrcImm)),
3026 /* 0x90 - 0x9F */
3027 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3028 /* 0xA0 - 0xA7 */
3029 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3030 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3031 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3032 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3033 /* 0xA8 - 0xAF */
3034 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3035 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3036 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3037 D(DstMem | SrcReg | Src2CL | ModRM),
3038 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3039 /* 0xB0 - 0xB7 */
3040 D2bv(DstMem | SrcReg | ModRM | Lock),
3041 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3042 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3043 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3044 /* 0xB8 - 0xBF */
3045 N, N,
3046 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3047 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3048 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3049 /* 0xC0 - 0xCF */
3050 D2bv(DstMem | SrcReg | ModRM | Lock),
3051 N, D(DstMem | SrcReg | ModRM | Mov),
3052 N, N, N, GD(0, &group9),
3053 N, N, N, N, N, N, N, N,
3054 /* 0xD0 - 0xDF */
3055 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3056 /* 0xE0 - 0xEF */
3057 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3058 /* 0xF0 - 0xFF */
3059 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3060};
3061
3062#undef D
3063#undef N
3064#undef G
3065#undef GD
3066#undef I
3067#undef GP
3068#undef EXT
3069
3070#undef D2bv
3071#undef D2bvIP
3072#undef I2bv
3073#undef D6ALU
3074
3075static unsigned imm_size(struct decode_cache *c)
3076{
3077 unsigned size;
3078
3079 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3080 if (size == 8)
3081 size = 4;
3082 return size;
3083}
3084
3085static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3086 unsigned size, bool sign_extension)
3087{
3088 struct decode_cache *c = &ctxt->decode;
3089 struct x86_emulate_ops *ops = ctxt->ops;
3090 int rc = X86EMUL_CONTINUE;
3091
3092 op->type = OP_IMM;
3093 op->bytes = size;
3094 op->addr.mem.ea = c->eip;
3095 /* NB. Immediates are sign-extended as necessary. */
3096 switch (op->bytes) {
3097 case 1:
3098 op->val = insn_fetch(s8, 1, c->eip);
3099 break;
3100 case 2:
3101 op->val = insn_fetch(s16, 2, c->eip);
3102 break;
3103 case 4:
3104 op->val = insn_fetch(s32, 4, c->eip);
3105 break;
3106 }
3107 if (!sign_extension) {
3108 switch (op->bytes) {
3109 case 1:
3110 op->val &= 0xff;
3111 break;
3112 case 2:
3113 op->val &= 0xffff;
3114 break;
3115 case 4:
3116 op->val &= 0xffffffff;
3117 break;
3118 }
3119 }
3120done:
3121 return rc;
3122}
3123
3124int
3125x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3126{
3127 struct x86_emulate_ops *ops = ctxt->ops;
3128 struct decode_cache *c = &ctxt->decode;
3129 int rc = X86EMUL_CONTINUE;
3130 int mode = ctxt->mode;
3131 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3132 bool op_prefix = false;
3133 struct opcode opcode, *g_mod012, *g_mod3;
3134 struct operand memop = { .type = OP_NONE };
3135
3136 c->eip = ctxt->eip;
3137 c->fetch.start = c->eip;
3138 c->fetch.end = c->fetch.start + insn_len;
3139 if (insn_len > 0)
3140 memcpy(c->fetch.data, insn, insn_len);
3141
3142 switch (mode) {
3143 case X86EMUL_MODE_REAL:
3144 case X86EMUL_MODE_VM86:
3145 case X86EMUL_MODE_PROT16:
3146 def_op_bytes = def_ad_bytes = 2;
3147 break;
3148 case X86EMUL_MODE_PROT32:
3149 def_op_bytes = def_ad_bytes = 4;
3150 break;
3151#ifdef CONFIG_X86_64
3152 case X86EMUL_MODE_PROT64:
3153 def_op_bytes = 4;
3154 def_ad_bytes = 8;
3155 break;
3156#endif
3157 default:
3158 return -1;
3159 }
3160
3161 c->op_bytes = def_op_bytes;
3162 c->ad_bytes = def_ad_bytes;
3163
3164 /* Legacy prefixes. */
3165 for (;;) {
3166 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3167 case 0x66: /* operand-size override */
3168 op_prefix = true;
3169 /* switch between 2/4 bytes */
3170 c->op_bytes = def_op_bytes ^ 6;
3171 break;
3172 case 0x67: /* address-size override */
3173 if (mode == X86EMUL_MODE_PROT64)
3174 /* switch between 4/8 bytes */
3175 c->ad_bytes = def_ad_bytes ^ 12;
3176 else
3177 /* switch between 2/4 bytes */
3178 c->ad_bytes = def_ad_bytes ^ 6;
3179 break;
3180 case 0x26: /* ES override */
3181 case 0x2e: /* CS override */
3182 case 0x36: /* SS override */
3183 case 0x3e: /* DS override */
3184 set_seg_override(c, (c->b >> 3) & 3);
3185 break;
3186 case 0x64: /* FS override */
3187 case 0x65: /* GS override */
3188 set_seg_override(c, c->b & 7);
3189 break;
3190 case 0x40 ... 0x4f: /* REX */
3191 if (mode != X86EMUL_MODE_PROT64)
3192 goto done_prefixes;
3193 c->rex_prefix = c->b;
3194 continue;
3195 case 0xf0: /* LOCK */
3196 c->lock_prefix = 1;
3197 break;
3198 case 0xf2: /* REPNE/REPNZ */
3199 case 0xf3: /* REP/REPE/REPZ */
3200 c->rep_prefix = c->b;
3201 break;
3202 default:
3203 goto done_prefixes;
3204 }
3205
3206 /* Any legacy prefix after a REX prefix nullifies its effect. */
3207
3208 c->rex_prefix = 0;
3209 }
3210
3211done_prefixes:
3212
3213 /* REX prefix. */
3214 if (c->rex_prefix & 8)
3215 c->op_bytes = 8; /* REX.W */
3216
3217 /* Opcode byte(s). */
3218 opcode = opcode_table[c->b];
3219 /* Two-byte opcode? */
3220 if (c->b == 0x0f) {
3221 c->twobyte = 1;
3222 c->b = insn_fetch(u8, 1, c->eip);
3223 opcode = twobyte_table[c->b];
3224 }
3225 c->d = opcode.flags;
3226
3227 if (c->d & Group) {
3228 dual = c->d & GroupDual;
3229 c->modrm = insn_fetch(u8, 1, c->eip);
3230 --c->eip;
3231
3232 if (c->d & GroupDual) {
3233 g_mod012 = opcode.u.gdual->mod012;
3234 g_mod3 = opcode.u.gdual->mod3;
3235 } else
3236 g_mod012 = g_mod3 = opcode.u.group;
3237
3238 c->d &= ~(Group | GroupDual);
3239
3240 goffset = (c->modrm >> 3) & 7;
3241
3242 if ((c->modrm >> 6) == 3)
3243 opcode = g_mod3[goffset];
3244 else
3245 opcode = g_mod012[goffset];
3246
3247 if (opcode.flags & RMExt) {
3248 goffset = c->modrm & 7;
3249 opcode = opcode.u.group[goffset];
3250 }
3251
3252 c->d |= opcode.flags;
3253 }
3254
3255 if (c->d & Prefix) {
3256 if (c->rep_prefix && op_prefix)
3257 return X86EMUL_UNHANDLEABLE;
3258 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3259 switch (simd_prefix) {
3260 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3261 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3262 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3263 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3264 }
3265 c->d |= opcode.flags;
3266 }
3267
3268 c->execute = opcode.u.execute;
3269 c->check_perm = opcode.check_perm;
3270 c->intercept = opcode.intercept;
3271
3272 /* Unrecognised? */
3273 if (c->d == 0 || (c->d & Undefined))
3274 return -1;
3275
3276 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3277 return -1;
3278
3279 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3280 c->op_bytes = 8;
3281
3282 if (c->d & Op3264) {
3283 if (mode == X86EMUL_MODE_PROT64)
3284 c->op_bytes = 8;
3285 else
3286 c->op_bytes = 4;
3287 }
3288
3289 if (c->d & Sse)
3290 c->op_bytes = 16;
3291
3292 /* ModRM and SIB bytes. */
3293 if (c->d & ModRM) {
3294 rc = decode_modrm(ctxt, ops, &memop);
3295 if (!c->has_seg_override)
3296 set_seg_override(c, c->modrm_seg);
3297 } else if (c->d & MemAbs)
3298 rc = decode_abs(ctxt, ops, &memop);
3299 if (rc != X86EMUL_CONTINUE)
3300 goto done;
3301
3302 if (!c->has_seg_override)
3303 set_seg_override(c, VCPU_SREG_DS);
3304
3305 memop.addr.mem.seg = seg_override(ctxt, ops, c);
3306
3307 if (memop.type == OP_MEM && c->ad_bytes != 8)
3308 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3309
3310 if (memop.type == OP_MEM && c->rip_relative)
3311 memop.addr.mem.ea += c->eip;
3312
3313 /*
3314 * Decode and fetch the source operand: register, memory
3315 * or immediate.
3316 */
3317 switch (c->d & SrcMask) {
3318 case SrcNone:
3319 break;
3320 case SrcReg:
3321 decode_register_operand(ctxt, &c->src, c, 0);
3322 break;
3323 case SrcMem16:
3324 memop.bytes = 2;
3325 goto srcmem_common;
3326 case SrcMem32:
3327 memop.bytes = 4;
3328 goto srcmem_common;
3329 case SrcMem:
3330 memop.bytes = (c->d & ByteOp) ? 1 :
3331 c->op_bytes;
3332 srcmem_common:
3333 c->src = memop;
3334 break;
3335 case SrcImmU16:
3336 rc = decode_imm(ctxt, &c->src, 2, false);
3337 break;
3338 case SrcImm:
3339 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3340 break;
3341 case SrcImmU:
3342 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3343 break;
3344 case SrcImmByte:
3345 rc = decode_imm(ctxt, &c->src, 1, true);
3346 break;
3347 case SrcImmUByte:
3348 rc = decode_imm(ctxt, &c->src, 1, false);
3349 break;
3350 case SrcAcc:
3351 c->src.type = OP_REG;
3352 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3353 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3354 fetch_register_operand(&c->src);
3355 break;
3356 case SrcOne:
3357 c->src.bytes = 1;
3358 c->src.val = 1;
3359 break;
3360 case SrcSI:
3361 c->src.type = OP_MEM;
3362 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3363 c->src.addr.mem.ea =
3364 register_address(c, c->regs[VCPU_REGS_RSI]);
3365 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
3366 c->src.val = 0;
3367 break;
3368 case SrcImmFAddr:
3369 c->src.type = OP_IMM;
3370 c->src.addr.mem.ea = c->eip;
3371 c->src.bytes = c->op_bytes + 2;
3372 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3373 break;
3374 case SrcMemFAddr:
3375 memop.bytes = c->op_bytes + 2;
3376 goto srcmem_common;
3377 break;
3378 }
3379
3380 if (rc != X86EMUL_CONTINUE)
3381 goto done;
3382
3383 /*
3384 * Decode and fetch the second source operand: register, memory
3385 * or immediate.
3386 */
3387 switch (c->d & Src2Mask) {
3388 case Src2None:
3389 break;
3390 case Src2CL:
3391 c->src2.bytes = 1;
3392 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3393 break;
3394 case Src2ImmByte:
3395 rc = decode_imm(ctxt, &c->src2, 1, true);
3396 break;
3397 case Src2One:
3398 c->src2.bytes = 1;
3399 c->src2.val = 1;
3400 break;
3401 case Src2Imm:
3402 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3403 break;
3404 }
3405
3406 if (rc != X86EMUL_CONTINUE)
3407 goto done;
3408
3409 /* Decode and fetch the destination operand: register or memory. */
3410 switch (c->d & DstMask) {
3411 case DstReg:
3412 decode_register_operand(ctxt, &c->dst, c,
3413 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3414 break;
3415 case DstImmUByte:
3416 c->dst.type = OP_IMM;
3417 c->dst.addr.mem.ea = c->eip;
3418 c->dst.bytes = 1;
3419 c->dst.val = insn_fetch(u8, 1, c->eip);
3420 break;
3421 case DstMem:
3422 case DstMem64:
3423 c->dst = memop;
3424 if ((c->d & DstMask) == DstMem64)
3425 c->dst.bytes = 8;
3426 else
3427 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3428 if (c->d & BitOp)
3429 fetch_bit_operand(c);
3430 c->dst.orig_val = c->dst.val;
3431 break;
3432 case DstAcc:
3433 c->dst.type = OP_REG;
3434 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3435 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3436 fetch_register_operand(&c->dst);
3437 c->dst.orig_val = c->dst.val;
3438 break;
3439 case DstDI:
3440 c->dst.type = OP_MEM;
3441 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3442 c->dst.addr.mem.ea =
3443 register_address(c, c->regs[VCPU_REGS_RDI]);
3444 c->dst.addr.mem.seg = VCPU_SREG_ES;
3445 c->dst.val = 0;
3446 break;
3447 case ImplicitOps:
3448 /* Special instructions do their own operand decoding. */
3449 default:
3450 c->dst.type = OP_NONE; /* Disable writeback. */
3451 return 0;
3452 }
3453
3454done:
3455 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3456}
3457
3458static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3459{
3460 struct decode_cache *c = &ctxt->decode;
3461
3462 /* The second termination condition only applies for REPE
3463 * and REPNE. Test if the repeat string operation prefix is
3464 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3465 * corresponding termination condition according to:
3466 * - if REPE/REPZ and ZF = 0 then done
3467 * - if REPNE/REPNZ and ZF = 1 then done
3468 */
3469 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3470 (c->b == 0xae) || (c->b == 0xaf))
3471 && (((c->rep_prefix == REPE_PREFIX) &&
3472 ((ctxt->eflags & EFLG_ZF) == 0))
3473 || ((c->rep_prefix == REPNE_PREFIX) &&
3474 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3475 return true;
3476
3477 return false;
3478}
3479
3480int
3481x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3482{
3483 struct x86_emulate_ops *ops = ctxt->ops;
3484 u64 msr_data;
3485 struct decode_cache *c = &ctxt->decode;
3486 int rc = X86EMUL_CONTINUE;
3487 int saved_dst_type = c->dst.type;
3488 int irq; /* Used for int 3, int, and into */
3489
3490 ctxt->decode.mem_read.pos = 0;
3491
3492 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3493 rc = emulate_ud(ctxt);
3494 goto done;
3495 }
3496
3497 /* LOCK prefix is allowed only with some instructions */
3498 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3499 rc = emulate_ud(ctxt);
3500 goto done;
3501 }
3502
3503 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3504 rc = emulate_ud(ctxt);
3505 goto done;
3506 }
3507
3508 if ((c->d & Sse)
3509 && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
3510 || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
3511 rc = emulate_ud(ctxt);
3512 goto done;
3513 }
3514
3515 if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
3516 rc = emulate_nm(ctxt);
3517 goto done;
3518 }
3519
3520 if (unlikely(ctxt->guest_mode) && c->intercept) {
3521 rc = emulator_check_intercept(ctxt, c->intercept,
3522 X86_ICPT_PRE_EXCEPT);
3523 if (rc != X86EMUL_CONTINUE)
3524 goto done;
3525 }
3526
3527 /* Privileged instruction can be executed only in CPL=0 */
3528 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
3529 rc = emulate_gp(ctxt, 0);
3530 goto done;
3531 }
3532
3533 /* Instruction can only be executed in protected mode */
3534 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3535 rc = emulate_ud(ctxt);
3536 goto done;
3537 }
3538
3539 /* Do instruction specific permission checks */
3540 if (c->check_perm) {
3541 rc = c->check_perm(ctxt);
3542 if (rc != X86EMUL_CONTINUE)
3543 goto done;
3544 }
3545
3546 if (unlikely(ctxt->guest_mode) && c->intercept) {
3547 rc = emulator_check_intercept(ctxt, c->intercept,
3548 X86_ICPT_POST_EXCEPT);
3549 if (rc != X86EMUL_CONTINUE)
3550 goto done;
3551 }
3552
3553 if (c->rep_prefix && (c->d & String)) {
3554 /* All REP prefixes have the same first termination condition */
3555 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3556 ctxt->eip = c->eip;
3557 goto done;
3558 }
3559 }
3560
3561 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3562 rc = segmented_read(ctxt, c->src.addr.mem,
3563 c->src.valptr, c->src.bytes);
3564 if (rc != X86EMUL_CONTINUE)
3565 goto done;
3566 c->src.orig_val64 = c->src.val64;
3567 }
3568
3569 if (c->src2.type == OP_MEM) {
3570 rc = segmented_read(ctxt, c->src2.addr.mem,
3571 &c->src2.val, c->src2.bytes);
3572 if (rc != X86EMUL_CONTINUE)
3573 goto done;
3574 }
3575
3576 if ((c->d & DstMask) == ImplicitOps)
3577 goto special_insn;
3578
3579
3580 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3581 /* optimisation - avoid slow emulated read if Mov */
3582 rc = segmented_read(ctxt, c->dst.addr.mem,
3583 &c->dst.val, c->dst.bytes);
3584 if (rc != X86EMUL_CONTINUE)
3585 goto done;
3586 }
3587 c->dst.orig_val = c->dst.val;
3588
3589special_insn:
3590
3591 if (unlikely(ctxt->guest_mode) && c->intercept) {
3592 rc = emulator_check_intercept(ctxt, c->intercept,
3593 X86_ICPT_POST_MEMACCESS);
3594 if (rc != X86EMUL_CONTINUE)
3595 goto done;
3596 }
3597
3598 if (c->execute) {
3599 rc = c->execute(ctxt);
3600 if (rc != X86EMUL_CONTINUE)
3601 goto done;
3602 goto writeback;
3603 }
3604
3605 if (c->twobyte)
3606 goto twobyte_insn;
3607
3608 switch (c->b) {
3609 case 0x00 ... 0x05:
3610 add: /* add */
3611 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3612 break;
3613 case 0x06: /* push es */
3614 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3615 break;
3616 case 0x07: /* pop es */
3617 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3618 break;
3619 case 0x08 ... 0x0d:
3620 or: /* or */
3621 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
3622 break;
3623 case 0x0e: /* push cs */
3624 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3625 break;
3626 case 0x10 ... 0x15:
3627 adc: /* adc */
3628 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
3629 break;
3630 case 0x16: /* push ss */
3631 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3632 break;
3633 case 0x17: /* pop ss */
3634 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3635 break;
3636 case 0x18 ... 0x1d:
3637 sbb: /* sbb */
3638 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
3639 break;
3640 case 0x1e: /* push ds */
3641 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3642 break;
3643 case 0x1f: /* pop ds */
3644 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3645 break;
3646 case 0x20 ... 0x25:
3647 and: /* and */
3648 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
3649 break;
3650 case 0x28 ... 0x2d:
3651 sub: /* sub */
3652 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
3653 break;
3654 case 0x30 ... 0x35:
3655 xor: /* xor */
3656 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
3657 break;
3658 case 0x38 ... 0x3d:
3659 cmp: /* cmp */
3660 c->dst.type = OP_NONE; /* Disable writeback. */
3661 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3662 break;
3663 case 0x40 ... 0x47: /* inc r16/r32 */
3664 emulate_1op("inc", c->dst, ctxt->eflags);
3665 break;
3666 case 0x48 ... 0x4f: /* dec r16/r32 */
3667 emulate_1op("dec", c->dst, ctxt->eflags);
3668 break;
3669 case 0x58 ... 0x5f: /* pop reg */
3670 pop_instruction:
3671 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3672 break;
3673 case 0x60: /* pusha */
3674 rc = emulate_pusha(ctxt);
3675 break;
3676 case 0x61: /* popa */
3677 rc = emulate_popa(ctxt, ops);
3678 break;
3679 case 0x63: /* movsxd */
3680 if (ctxt->mode != X86EMUL_MODE_PROT64)
3681 goto cannot_emulate;
3682 c->dst.val = (s32) c->src.val;
3683 break;
3684 case 0x6c: /* insb */
3685 case 0x6d: /* insw/insd */
3686 c->src.val = c->regs[VCPU_REGS_RDX];
3687 goto do_io_in;
3688 case 0x6e: /* outsb */
3689 case 0x6f: /* outsw/outsd */
3690 c->dst.val = c->regs[VCPU_REGS_RDX];
3691 goto do_io_out;
3692 break;
3693 case 0x70 ... 0x7f: /* jcc (short) */
3694 if (test_cc(c->b, ctxt->eflags))
3695 jmp_rel(c, c->src.val);
3696 break;
3697 case 0x80 ... 0x83: /* Grp1 */
3698 switch (c->modrm_reg) {
3699 case 0:
3700 goto add;
3701 case 1:
3702 goto or;
3703 case 2:
3704 goto adc;
3705 case 3:
3706 goto sbb;
3707 case 4:
3708 goto and;
3709 case 5:
3710 goto sub;
3711 case 6:
3712 goto xor;
3713 case 7:
3714 goto cmp;
3715 }
3716 break;
3717 case 0x84 ... 0x85:
3718 test:
3719 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3720 break;
3721 case 0x86 ... 0x87: /* xchg */
3722 xchg:
3723 /* Write back the register source. */
3724 c->src.val = c->dst.val;
3725 write_register_operand(&c->src);
3726 /*
3727 * Write back the memory destination with implicit LOCK
3728 * prefix.
3729 */
3730 c->dst.val = c->src.orig_val;
3731 c->lock_prefix = 1;
3732 break;
3733 case 0x8c: /* mov r/m, sreg */
3734 if (c->modrm_reg > VCPU_SREG_GS) {
3735 rc = emulate_ud(ctxt);
3736 goto done;
3737 }
3738 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3739 break;
3740 case 0x8d: /* lea r16/r32, m */
3741 c->dst.val = c->src.addr.mem.ea;
3742 break;
3743 case 0x8e: { /* mov seg, r/m16 */
3744 uint16_t sel;
3745
3746 sel = c->src.val;
3747
3748 if (c->modrm_reg == VCPU_SREG_CS ||
3749 c->modrm_reg > VCPU_SREG_GS) {
3750 rc = emulate_ud(ctxt);
3751 goto done;
3752 }
3753
3754 if (c->modrm_reg == VCPU_SREG_SS)
3755 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3756
3757 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3758
3759 c->dst.type = OP_NONE; /* Disable writeback. */
3760 break;
3761 }
3762 case 0x8f: /* pop (sole member of Grp1a) */
3763 rc = emulate_grp1a(ctxt, ops);
3764 break;
3765 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3766 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3767 break;
3768 goto xchg;
3769 case 0x98: /* cbw/cwde/cdqe */
3770 switch (c->op_bytes) {
3771 case 2: c->dst.val = (s8)c->dst.val; break;
3772 case 4: c->dst.val = (s16)c->dst.val; break;
3773 case 8: c->dst.val = (s32)c->dst.val; break;
3774 }
3775 break;
3776 case 0x9c: /* pushf */
3777 c->src.val = (unsigned long) ctxt->eflags;
3778 rc = em_push(ctxt);
3779 break;
3780 case 0x9d: /* popf */
3781 c->dst.type = OP_REG;
3782 c->dst.addr.reg = &ctxt->eflags;
3783 c->dst.bytes = c->op_bytes;
3784 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3785 break;
3786 case 0xa6 ... 0xa7: /* cmps */
3787 goto cmp;
3788 case 0xa8 ... 0xa9: /* test ax, imm */
3789 goto test;
3790 case 0xae ... 0xaf: /* scas */
3791 goto cmp;
3792 case 0xc0 ... 0xc1:
3793 emulate_grp2(ctxt);
3794 break;
3795 case 0xc3: /* ret */
3796 c->dst.type = OP_REG;
3797 c->dst.addr.reg = &c->eip;
3798 c->dst.bytes = c->op_bytes;
3799 goto pop_instruction;
3800 case 0xc4: /* les */
3801 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3802 break;
3803 case 0xc5: /* lds */
3804 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3805 break;
3806 case 0xcb: /* ret far */
3807 rc = emulate_ret_far(ctxt, ops);
3808 break;
3809 case 0xcc: /* int3 */
3810 irq = 3;
3811 goto do_interrupt;
3812 case 0xcd: /* int n */
3813 irq = c->src.val;
3814 do_interrupt:
3815 rc = emulate_int(ctxt, ops, irq);
3816 break;
3817 case 0xce: /* into */
3818 if (ctxt->eflags & EFLG_OF) {
3819 irq = 4;
3820 goto do_interrupt;
3821 }
3822 break;
3823 case 0xcf: /* iret */
3824 rc = emulate_iret(ctxt, ops);
3825 break;
3826 case 0xd0 ... 0xd1: /* Grp2 */
3827 emulate_grp2(ctxt);
3828 break;
3829 case 0xd2 ... 0xd3: /* Grp2 */
3830 c->src.val = c->regs[VCPU_REGS_RCX];
3831 emulate_grp2(ctxt);
3832 break;
3833 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3834 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3835 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3836 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3837 jmp_rel(c, c->src.val);
3838 break;
3839 case 0xe3: /* jcxz/jecxz/jrcxz */
3840 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3841 jmp_rel(c, c->src.val);
3842 break;
3843 case 0xe4: /* inb */
3844 case 0xe5: /* in */
3845 goto do_io_in;
3846 case 0xe6: /* outb */
3847 case 0xe7: /* out */
3848 goto do_io_out;
3849 case 0xe8: /* call (near) */ {
3850 long int rel = c->src.val;
3851 c->src.val = (unsigned long) c->eip;
3852 jmp_rel(c, rel);
3853 rc = em_push(ctxt);
3854 break;
3855 }
3856 case 0xe9: /* jmp rel */
3857 goto jmp;
3858 case 0xea: { /* jmp far */
3859 unsigned short sel;
3860 jump_far:
3861 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3862
3863 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3864 goto done;
3865
3866 c->eip = 0;
3867 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3868 break;
3869 }
3870 case 0xeb:
3871 jmp: /* jmp rel short */
3872 jmp_rel(c, c->src.val);
3873 c->dst.type = OP_NONE; /* Disable writeback. */
3874 break;
3875 case 0xec: /* in al,dx */
3876 case 0xed: /* in (e/r)ax,dx */
3877 c->src.val = c->regs[VCPU_REGS_RDX];
3878 do_io_in:
3879 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3880 &c->dst.val))
3881 goto done; /* IO is needed */
3882 break;
3883 case 0xee: /* out dx,al */
3884 case 0xef: /* out dx,(e/r)ax */
3885 c->dst.val = c->regs[VCPU_REGS_RDX];
3886 do_io_out:
3887 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3888 &c->src.val, 1, ctxt->vcpu);
3889 c->dst.type = OP_NONE; /* Disable writeback. */
3890 break;
3891 case 0xf4: /* hlt */
3892 ctxt->vcpu->arch.halt_request = 1;
3893 break;
3894 case 0xf5: /* cmc */
3895 /* complement carry flag from eflags reg */
3896 ctxt->eflags ^= EFLG_CF;
3897 break;
3898 case 0xf6 ... 0xf7: /* Grp3 */
3899 rc = emulate_grp3(ctxt, ops);
3900 break;
3901 case 0xf8: /* clc */
3902 ctxt->eflags &= ~EFLG_CF;
3903 break;
3904 case 0xf9: /* stc */
3905 ctxt->eflags |= EFLG_CF;
3906 break;
3907 case 0xfa: /* cli */
3908 if (emulator_bad_iopl(ctxt, ops)) {
3909 rc = emulate_gp(ctxt, 0);
3910 goto done;
3911 } else
3912 ctxt->eflags &= ~X86_EFLAGS_IF;
3913 break;
3914 case 0xfb: /* sti */
3915 if (emulator_bad_iopl(ctxt, ops)) {
3916 rc = emulate_gp(ctxt, 0);
3917 goto done;
3918 } else {
3919 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3920 ctxt->eflags |= X86_EFLAGS_IF;
3921 }
3922 break;
3923 case 0xfc: /* cld */
3924 ctxt->eflags &= ~EFLG_DF;
3925 break;
3926 case 0xfd: /* std */
3927 ctxt->eflags |= EFLG_DF;
3928 break;
3929 case 0xfe: /* Grp4 */
3930 grp45:
3931 rc = emulate_grp45(ctxt);
3932 break;
3933 case 0xff: /* Grp5 */
3934 if (c->modrm_reg == 5)
3935 goto jump_far;
3936 goto grp45;
3937 default:
3938 goto cannot_emulate;
3939 }
3940
3941 if (rc != X86EMUL_CONTINUE)
3942 goto done;
3943
3944writeback:
3945 rc = writeback(ctxt, ops);
3946 if (rc != X86EMUL_CONTINUE)
3947 goto done;
3948
3949 /*
3950 * restore dst type in case the decoding will be reused
3951 * (happens for string instruction )
3952 */
3953 c->dst.type = saved_dst_type;
3954
3955 if ((c->d & SrcMask) == SrcSI)
3956 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
3957 VCPU_REGS_RSI, &c->src);
3958
3959 if ((c->d & DstMask) == DstDI)
3960 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
3961 &c->dst);
3962
3963 if (c->rep_prefix && (c->d & String)) {
3964 struct read_cache *r = &ctxt->decode.io_read;
3965 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3966
3967 if (!string_insn_completed(ctxt)) {
3968 /*
3969 * Re-enter guest when pio read ahead buffer is empty
3970 * or, if it is not used, after each 1024 iteration.
3971 */
3972 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3973 (r->end == 0 || r->end != r->pos)) {
3974 /*
3975 * Reset read cache. Usually happens before
3976 * decode, but since instruction is restarted
3977 * we have to do it here.
3978 */
3979 ctxt->decode.mem_read.end = 0;
3980 return EMULATION_RESTART;
3981 }
3982 goto done; /* skip rip writeback */
3983 }
3984 }
3985
3986 ctxt->eip = c->eip;
3987
3988done:
3989 if (rc == X86EMUL_PROPAGATE_FAULT)
3990 ctxt->have_exception = true;
3991 if (rc == X86EMUL_INTERCEPTED)
3992 return EMULATION_INTERCEPTED;
3993
3994 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3995
3996twobyte_insn:
3997 switch (c->b) {
3998 case 0x01: /* lgdt, lidt, lmsw */
3999 switch (c->modrm_reg) {
4000 u16 size;
4001 unsigned long address;
4002
4003 case 0: /* vmcall */
4004 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4005 goto cannot_emulate;
4006
4007 rc = kvm_fix_hypercall(ctxt->vcpu);
4008 if (rc != X86EMUL_CONTINUE)
4009 goto done;
4010
4011 /* Let the processor re-execute the fixed hypercall */
4012 c->eip = ctxt->eip;
4013 /* Disable writeback. */
4014 c->dst.type = OP_NONE;
4015 break;
4016 case 2: /* lgdt */
4017 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
4018 &size, &address, c->op_bytes);
4019 if (rc != X86EMUL_CONTINUE)
4020 goto done;
4021 realmode_lgdt(ctxt->vcpu, size, address);
4022 /* Disable writeback. */
4023 c->dst.type = OP_NONE;
4024 break;
4025 case 3: /* lidt/vmmcall */
4026 if (c->modrm_mod == 3) {
4027 switch (c->modrm_rm) {
4028 case 1:
4029 rc = kvm_fix_hypercall(ctxt->vcpu);
4030 break;
4031 default:
4032 goto cannot_emulate;
4033 }
4034 } else {
4035 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
4036 &size, &address,
4037 c->op_bytes);
4038 if (rc != X86EMUL_CONTINUE)
4039 goto done;
4040 realmode_lidt(ctxt->vcpu, size, address);
4041 }
4042 /* Disable writeback. */
4043 c->dst.type = OP_NONE;
4044 break;
4045 case 4: /* smsw */
4046 c->dst.bytes = 2;
4047 c->dst.val = ops->get_cr(0, ctxt->vcpu);
4048 break;
4049 case 6: /* lmsw */
4050 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
4051 (c->src.val & 0x0f), ctxt->vcpu);
4052 c->dst.type = OP_NONE;
4053 break;
4054 case 5: /* not defined */
4055 emulate_ud(ctxt);
4056 rc = X86EMUL_PROPAGATE_FAULT;
4057 goto done;
4058 case 7: /* invlpg*/
4059 rc = em_invlpg(ctxt);
4060 break;
4061 default:
4062 goto cannot_emulate;
4063 }
4064 break;
4065 case 0x05: /* syscall */
4066 rc = emulate_syscall(ctxt, ops);
4067 break;
4068 case 0x06:
4069 emulate_clts(ctxt->vcpu);
4070 break;
4071 case 0x09: /* wbinvd */
4072 kvm_emulate_wbinvd(ctxt->vcpu);
4073 break;
4074 case 0x08: /* invd */
4075 case 0x0d: /* GrpP (prefetch) */
4076 case 0x18: /* Grp16 (prefetch/nop) */
4077 break;
4078 case 0x20: /* mov cr, reg */
4079 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
4080 break;
4081 case 0x21: /* mov from dr to reg */
4082 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
4083 break;
4084 case 0x22: /* mov reg, cr */
4085 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
4086 emulate_gp(ctxt, 0);
4087 rc = X86EMUL_PROPAGATE_FAULT;
4088 goto done;
4089 }
4090 c->dst.type = OP_NONE;
4091 break;
4092 case 0x23: /* mov from reg to dr */
4093 if (ops->set_dr(c->modrm_reg, c->src.val &
4094 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4095 ~0ULL : ~0U), ctxt->vcpu) < 0) {
4096 /* #UD condition is already handled by the code above */
4097 emulate_gp(ctxt, 0);
4098 rc = X86EMUL_PROPAGATE_FAULT;
4099 goto done;
4100 }
4101
4102 c->dst.type = OP_NONE; /* no writeback */
4103 break;
4104 case 0x30:
4105 /* wrmsr */
4106 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4107 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
4108 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
4109 emulate_gp(ctxt, 0);
4110 rc = X86EMUL_PROPAGATE_FAULT;
4111 goto done;
4112 }
4113 rc = X86EMUL_CONTINUE;
4114 break;
4115 case 0x32:
4116 /* rdmsr */
4117 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
4118 emulate_gp(ctxt, 0);
4119 rc = X86EMUL_PROPAGATE_FAULT;
4120 goto done;
4121 } else {
4122 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4123 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4124 }
4125 rc = X86EMUL_CONTINUE;
4126 break;
4127 case 0x34: /* sysenter */
4128 rc = emulate_sysenter(ctxt, ops);
4129 break;
4130 case 0x35: /* sysexit */
4131 rc = emulate_sysexit(ctxt, ops);
4132 break;
4133 case 0x40 ... 0x4f: /* cmov */
4134 c->dst.val = c->dst.orig_val = c->src.val;
4135 if (!test_cc(c->b, ctxt->eflags))
4136 c->dst.type = OP_NONE; /* no writeback */
4137 break;
4138 case 0x80 ... 0x8f: /* jnz rel, etc*/
4139 if (test_cc(c->b, ctxt->eflags))
4140 jmp_rel(c, c->src.val);
4141 break;
4142 case 0x90 ... 0x9f: /* setcc r/m8 */
4143 c->dst.val = test_cc(c->b, ctxt->eflags);
4144 break;
4145 case 0xa0: /* push fs */
4146 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4147 break;
4148 case 0xa1: /* pop fs */
4149 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
4150 break;
4151 case 0xa3:
4152 bt: /* bt */
4153 c->dst.type = OP_NONE;
4154 /* only subword offset */
4155 c->src.val &= (c->dst.bytes << 3) - 1;
4156 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4157 break;
4158 case 0xa4: /* shld imm8, r, r/m */
4159 case 0xa5: /* shld cl, r, r/m */
4160 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4161 break;
4162 case 0xa8: /* push gs */
4163 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4164 break;
4165 case 0xa9: /* pop gs */
4166 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
4167 break;
4168 case 0xab:
4169 bts: /* bts */
4170 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4171 break;
4172 case 0xac: /* shrd imm8, r, r/m */
4173 case 0xad: /* shrd cl, r, r/m */
4174 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4175 break;
4176 case 0xae: /* clflush */
4177 break;
4178 case 0xb0 ... 0xb1: /* cmpxchg */
4179 /*
4180 * Save real source value, then compare EAX against
4181 * destination.
4182 */
4183 c->src.orig_val = c->src.val;
4184 c->src.val = c->regs[VCPU_REGS_RAX];
4185 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4186 if (ctxt->eflags & EFLG_ZF) {
4187 /* Success: write back to memory. */
4188 c->dst.val = c->src.orig_val;
4189 } else {
4190 /* Failure: write the value we saw to EAX. */
4191 c->dst.type = OP_REG;
4192 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
4193 }
4194 break;
4195 case 0xb2: /* lss */
4196 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
4197 break;
4198 case 0xb3:
4199 btr: /* btr */
4200 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
4201 break;
4202 case 0xb4: /* lfs */
4203 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
4204 break;
4205 case 0xb5: /* lgs */
4206 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
4207 break;
4208 case 0xb6 ... 0xb7: /* movzx */
4209 c->dst.bytes = c->op_bytes;
4210 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4211 : (u16) c->src.val;
4212 break;
4213 case 0xba: /* Grp8 */
4214 switch (c->modrm_reg & 3) {
4215 case 0:
4216 goto bt;
4217 case 1:
4218 goto bts;
4219 case 2:
4220 goto btr;
4221 case 3:
4222 goto btc;
4223 }
4224 break;
4225 case 0xbb:
4226 btc: /* btc */
4227 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4228 break;
4229 case 0xbc: { /* bsf */
4230 u8 zf;
4231 __asm__ ("bsf %2, %0; setz %1"
4232 : "=r"(c->dst.val), "=q"(zf)
4233 : "r"(c->src.val));
4234 ctxt->eflags &= ~X86_EFLAGS_ZF;
4235 if (zf) {
4236 ctxt->eflags |= X86_EFLAGS_ZF;
4237 c->dst.type = OP_NONE; /* Disable writeback. */
4238 }
4239 break;
4240 }
4241 case 0xbd: { /* bsr */
4242 u8 zf;
4243 __asm__ ("bsr %2, %0; setz %1"
4244 : "=r"(c->dst.val), "=q"(zf)
4245 : "r"(c->src.val));
4246 ctxt->eflags &= ~X86_EFLAGS_ZF;
4247 if (zf) {
4248 ctxt->eflags |= X86_EFLAGS_ZF;
4249 c->dst.type = OP_NONE; /* Disable writeback. */
4250 }
4251 break;
4252 }
4253 case 0xbe ... 0xbf: /* movsx */
4254 c->dst.bytes = c->op_bytes;
4255 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4256 (s16) c->src.val;
4257 break;
4258 case 0xc0 ... 0xc1: /* xadd */
4259 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4260 /* Write back the register source. */
4261 c->src.val = c->dst.orig_val;
4262 write_register_operand(&c->src);
4263 break;
4264 case 0xc3: /* movnti */
4265 c->dst.bytes = c->op_bytes;
4266 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4267 (u64) c->src.val;
4268 break;
4269 case 0xc7: /* Grp9 (cmpxchg8b) */
4270 rc = emulate_grp9(ctxt, ops);
4271 break;
4272 default:
4273 goto cannot_emulate;
4274 }
4275
4276 if (rc != X86EMUL_CONTINUE)
4277 goto done;
4278
4279 goto writeback;
4280
4281cannot_emulate:
4282 return EMULATION_FAILED;
4283}
Linux kernel - Deliverables
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