projects / deliverable / linux.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
KVM: x86 emulator: Use opcode::execute for POP reg (58-5F)
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
... / ...
CommitLineData
1/******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#include <linux/kvm_host.h>
24#include "kvm_cache_regs.h"
25#include <linux/module.h>
26#include <asm/kvm_emulate.h>
27
28#include "x86.h"
29#include "tss.h"
30
31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
41#define ByteOp (1<<0) /* 8-bit operands. */
42/* Destination operand type. */
43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50#define DstMask (7<<1)
51/* Source operand type. */
52#define SrcNone (0<<4) /* No source operand. */
53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59#define SrcOne (7<<4) /* Implied '1' */
60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65#define SrcAcc (0xd<<4) /* Source Accumulator */
66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67#define SrcMask (0xf<<4)
68/* Generic ModRM decode. */
69#define ModRM (1<<8)
70/* Destination is only written; never read. */
71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79#define Sse (1<<17) /* SSE Vector instruction */
80#define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
81/* Misc flags */
82#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
83#define VendorSpecific (1<<22) /* Vendor specific instruction */
84#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
85#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
86#define Undefined (1<<25) /* No Such Instruction */
87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89#define No64 (1<<28)
90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
95#define Src2Imm (4<<29)
96#define Src2Mask (7<<29)
97
98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
106
107struct opcode {
108 u32 flags;
109 u8 intercept;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 struct gprefix *gprefix;
115 } u;
116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122};
123
124struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129};
130
131/* EFLAGS bit definitions. */
132#define EFLG_ID (1<<21)
133#define EFLG_VIP (1<<20)
134#define EFLG_VIF (1<<19)
135#define EFLG_AC (1<<18)
136#define EFLG_VM (1<<17)
137#define EFLG_RF (1<<16)
138#define EFLG_IOPL (3<<12)
139#define EFLG_NT (1<<14)
140#define EFLG_OF (1<<11)
141#define EFLG_DF (1<<10)
142#define EFLG_IF (1<<9)
143#define EFLG_TF (1<<8)
144#define EFLG_SF (1<<7)
145#define EFLG_ZF (1<<6)
146#define EFLG_AF (1<<4)
147#define EFLG_PF (1<<2)
148#define EFLG_CF (1<<0)
149
150#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151#define EFLG_RESERVED_ONE_MASK 2
152
153/*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
160#if defined(CONFIG_X86_64)
161#define _LO32 "k" /* force 32-bit operand */
162#define _STK "%%rsp" /* stack pointer */
163#elif defined(__i386__)
164#define _LO32 "" /* force 32-bit operand */
165#define _STK "%%esp" /* stack pointer */
166#endif
167
168/*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174/* Before executing instruction: restore necessary bits in EFLAGS. */
175#define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
190
191/* After executing instruction: write-back necessary bits in EFLAGS. */
192#define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
199#ifdef CONFIG_X86_64
200#define ON64(x) x
201#else
202#define ON64(x)
203#endif
204
205#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
214 } while (0)
215
216
217/* Raw emulation: instruction has two explicit operands. */
218#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 break; \
226 case 4: \
227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 break; \
229 case 8: \
230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
231 break; \
232 } \
233 } while (0)
234
235#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
237 unsigned long _tmp; \
238 switch ((_dst).bytes) { \
239 case 1: \
240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249/* Source operand is byte-sized and may be restricted to just %cl. */
250#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254/* Source operand is byte, word, long or quad sized. */
255#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259/* Source operand is word, long or quad sized. */
260#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
264/* Instruction has three operands and one operand is stored in ECX register */
265#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
303#define __emulate_1op(_op, _dst, _eflags, _suffix) \
304 do { \
305 unsigned long _tmp; \
306 \
307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316/* Instruction has only one explicit operand (no source operand). */
317#define emulate_1op(_op, _dst, _eflags) \
318 do { \
319 switch ((_dst).bytes) { \
320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
324 } \
325 } while (0)
326
327#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
341#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
362/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: \
367 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
368 _eflags, "b"); \
369 break; \
370 case 2: \
371 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
372 _eflags, "w"); \
373 break; \
374 case 4: \
375 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
376 _eflags, "l"); \
377 break; \
378 case 8: \
379 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
380 _eflags, "q")); \
381 break; \
382 } \
383 } while (0)
384
385#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
386 do { \
387 switch((_src).bytes) { \
388 case 1: \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "b", _ex); \
391 break; \
392 case 2: \
393 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
394 _eflags, "w", _ex); \
395 break; \
396 case 4: \
397 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
398 _eflags, "l", _ex); \
399 break; \
400 case 8: ON64( \
401 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
402 _eflags, "q", _ex)); \
403 break; \
404 } \
405 } while (0)
406
407/* Fetch next part of the instruction being emulated. */
408#define insn_fetch(_type, _size, _eip) \
409({ unsigned long _x; \
410 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
411 if (rc != X86EMUL_CONTINUE) \
412 goto done; \
413 (_eip) += (_size); \
414 (_type)_x; \
415})
416
417#define insn_fetch_arr(_arr, _size, _eip) \
418({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
419 if (rc != X86EMUL_CONTINUE) \
420 goto done; \
421 (_eip) += (_size); \
422})
423
424static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
425 enum x86_intercept intercept,
426 enum x86_intercept_stage stage)
427{
428 struct x86_instruction_info info = {
429 .intercept = intercept,
430 .rep_prefix = ctxt->decode.rep_prefix,
431 .modrm_mod = ctxt->decode.modrm_mod,
432 .modrm_reg = ctxt->decode.modrm_reg,
433 .modrm_rm = ctxt->decode.modrm_rm,
434 .src_val = ctxt->decode.src.val64,
435 .src_bytes = ctxt->decode.src.bytes,
436 .dst_bytes = ctxt->decode.dst.bytes,
437 .ad_bytes = ctxt->decode.ad_bytes,
438 .next_rip = ctxt->eip,
439 };
440
441 return ctxt->ops->intercept(ctxt, &info, stage);
442}
443
444static inline unsigned long ad_mask(struct decode_cache *c)
445{
446 return (1UL << (c->ad_bytes << 3)) - 1;
447}
448
449/* Access/update address held in a register, based on addressing mode. */
450static inline unsigned long
451address_mask(struct decode_cache *c, unsigned long reg)
452{
453 if (c->ad_bytes == sizeof(unsigned long))
454 return reg;
455 else
456 return reg & ad_mask(c);
457}
458
459static inline unsigned long
460register_address(struct decode_cache *c, unsigned long reg)
461{
462 return address_mask(c, reg);
463}
464
465static inline void
466register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
467{
468 if (c->ad_bytes == sizeof(unsigned long))
469 *reg += inc;
470 else
471 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
472}
473
474static inline void jmp_rel(struct decode_cache *c, int rel)
475{
476 register_address_increment(c, &c->eip, rel);
477}
478
479static u32 desc_limit_scaled(struct desc_struct *desc)
480{
481 u32 limit = get_desc_limit(desc);
482
483 return desc->g ? (limit << 12) | 0xfff : limit;
484}
485
486static void set_seg_override(struct decode_cache *c, int seg)
487{
488 c->has_seg_override = true;
489 c->seg_override = seg;
490}
491
492static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
493 struct x86_emulate_ops *ops, int seg)
494{
495 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
496 return 0;
497
498 return ops->get_cached_segment_base(ctxt, seg);
499}
500
501static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
502 struct x86_emulate_ops *ops,
503 struct decode_cache *c)
504{
505 if (!c->has_seg_override)
506 return 0;
507
508 return c->seg_override;
509}
510
511static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
513{
514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
517 return X86EMUL_PROPAGATE_FAULT;
518}
519
520static int emulate_db(struct x86_emulate_ctxt *ctxt)
521{
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523}
524
525static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
526{
527 return emulate_exception(ctxt, GP_VECTOR, err, true);
528}
529
530static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531{
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533}
534
535static int emulate_ud(struct x86_emulate_ctxt *ctxt)
536{
537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
538}
539
540static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
541{
542 return emulate_exception(ctxt, TS_VECTOR, err, true);
543}
544
545static int emulate_de(struct x86_emulate_ctxt *ctxt)
546{
547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
548}
549
550static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553}
554
555static int __linearize(struct x86_emulate_ctxt *ctxt,
556 struct segmented_address addr,
557 unsigned size, bool write, bool fetch,
558 ulong *linear)
559{
560 struct decode_cache *c = &ctxt->decode;
561 struct desc_struct desc;
562 bool usable;
563 ulong la;
564 u32 lim;
565 unsigned cpl, rpl;
566
567 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
568 switch (ctxt->mode) {
569 case X86EMUL_MODE_REAL:
570 break;
571 case X86EMUL_MODE_PROT64:
572 if (((signed long)la << 16) >> 16 != la)
573 return emulate_gp(ctxt, 0);
574 break;
575 default:
576 usable = ctxt->ops->get_cached_descriptor(ctxt, &desc, NULL,
577 addr.seg);
578 if (!usable)
579 goto bad;
580 /* code segment or read-only data segment */
581 if (((desc.type & 8) || !(desc.type & 2)) && write)
582 goto bad;
583 /* unreadable code segment */
584 if (!fetch && (desc.type & 8) && !(desc.type & 2))
585 goto bad;
586 lim = desc_limit_scaled(&desc);
587 if ((desc.type & 8) || !(desc.type & 4)) {
588 /* expand-up segment */
589 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
590 goto bad;
591 } else {
592 /* exapand-down segment */
593 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
594 goto bad;
595 lim = desc.d ? 0xffffffff : 0xffff;
596 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
597 goto bad;
598 }
599 cpl = ctxt->ops->cpl(ctxt);
600 rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
601 cpl = max(cpl, rpl);
602 if (!(desc.type & 8)) {
603 /* data segment */
604 if (cpl > desc.dpl)
605 goto bad;
606 } else if ((desc.type & 8) && !(desc.type & 4)) {
607 /* nonconforming code segment */
608 if (cpl != desc.dpl)
609 goto bad;
610 } else if ((desc.type & 8) && (desc.type & 4)) {
611 /* conforming code segment */
612 if (cpl < desc.dpl)
613 goto bad;
614 }
615 break;
616 }
617 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
618 la &= (u32)-1;
619 *linear = la;
620 return X86EMUL_CONTINUE;
621bad:
622 if (addr.seg == VCPU_SREG_SS)
623 return emulate_ss(ctxt, addr.seg);
624 else
625 return emulate_gp(ctxt, addr.seg);
626}
627
628static int linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned size, bool write,
631 ulong *linear)
632{
633 return __linearize(ctxt, addr, size, write, false, linear);
634}
635
636
637static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 void *data,
640 unsigned size)
641{
642 int rc;
643 ulong linear;
644
645 rc = linearize(ctxt, addr, size, false, &linear);
646 if (rc != X86EMUL_CONTINUE)
647 return rc;
648 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
649}
650
651static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
652 struct x86_emulate_ops *ops,
653 unsigned long eip, u8 *dest)
654{
655 struct fetch_cache *fc = &ctxt->decode.fetch;
656 int rc;
657 int size, cur_size;
658
659 if (eip == fc->end) {
660 unsigned long linear;
661 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
662 cur_size = fc->end - fc->start;
663 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
664 rc = __linearize(ctxt, addr, size, false, true, &linear);
665 if (rc != X86EMUL_CONTINUE)
666 return rc;
667 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
668 size, &ctxt->exception);
669 if (rc != X86EMUL_CONTINUE)
670 return rc;
671 fc->end += size;
672 }
673 *dest = fc->data[eip - fc->start];
674 return X86EMUL_CONTINUE;
675}
676
677static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
678 struct x86_emulate_ops *ops,
679 unsigned long eip, void *dest, unsigned size)
680{
681 int rc;
682
683 /* x86 instructions are limited to 15 bytes. */
684 if (eip + size - ctxt->eip > 15)
685 return X86EMUL_UNHANDLEABLE;
686 while (size--) {
687 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
688 if (rc != X86EMUL_CONTINUE)
689 return rc;
690 }
691 return X86EMUL_CONTINUE;
692}
693
694/*
695 * Given the 'reg' portion of a ModRM byte, and a register block, return a
696 * pointer into the block that addresses the relevant register.
697 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
698 */
699static void *decode_register(u8 modrm_reg, unsigned long *regs,
700 int highbyte_regs)
701{
702 void *p;
703
704 p = &regs[modrm_reg];
705 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
706 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
707 return p;
708}
709
710static int read_descriptor(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 struct segmented_address addr,
713 u16 *size, unsigned long *address, int op_bytes)
714{
715 int rc;
716
717 if (op_bytes == 2)
718 op_bytes = 3;
719 *address = 0;
720 rc = segmented_read_std(ctxt, addr, size, 2);
721 if (rc != X86EMUL_CONTINUE)
722 return rc;
723 addr.ea += 2;
724 rc = segmented_read_std(ctxt, addr, address, op_bytes);
725 return rc;
726}
727
728static int test_cc(unsigned int condition, unsigned int flags)
729{
730 int rc = 0;
731
732 switch ((condition & 15) >> 1) {
733 case 0: /* o */
734 rc |= (flags & EFLG_OF);
735 break;
736 case 1: /* b/c/nae */
737 rc |= (flags & EFLG_CF);
738 break;
739 case 2: /* z/e */
740 rc |= (flags & EFLG_ZF);
741 break;
742 case 3: /* be/na */
743 rc |= (flags & (EFLG_CF|EFLG_ZF));
744 break;
745 case 4: /* s */
746 rc |= (flags & EFLG_SF);
747 break;
748 case 5: /* p/pe */
749 rc |= (flags & EFLG_PF);
750 break;
751 case 7: /* le/ng */
752 rc |= (flags & EFLG_ZF);
753 /* fall through */
754 case 6: /* l/nge */
755 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
756 break;
757 }
758
759 /* Odd condition identifiers (lsb == 1) have inverted sense. */
760 return (!!rc ^ (condition & 1));
761}
762
763static void fetch_register_operand(struct operand *op)
764{
765 switch (op->bytes) {
766 case 1:
767 op->val = *(u8 *)op->addr.reg;
768 break;
769 case 2:
770 op->val = *(u16 *)op->addr.reg;
771 break;
772 case 4:
773 op->val = *(u32 *)op->addr.reg;
774 break;
775 case 8:
776 op->val = *(u64 *)op->addr.reg;
777 break;
778 }
779}
780
781static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
782{
783 ctxt->ops->get_fpu(ctxt);
784 switch (reg) {
785 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
786 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
787 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
788 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
789 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
790 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
791 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
792 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
793#ifdef CONFIG_X86_64
794 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
795 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
796 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
797 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
798 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
799 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
800 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
801 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
802#endif
803 default: BUG();
804 }
805 ctxt->ops->put_fpu(ctxt);
806}
807
808static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
809 int reg)
810{
811 ctxt->ops->get_fpu(ctxt);
812 switch (reg) {
813 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
814 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
815 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
816 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
817 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
818 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
819 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
820 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
821#ifdef CONFIG_X86_64
822 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
823 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
824 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
825 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
826 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
827 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
828 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
829 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
830#endif
831 default: BUG();
832 }
833 ctxt->ops->put_fpu(ctxt);
834}
835
836static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
837 struct operand *op,
838 struct decode_cache *c,
839 int inhibit_bytereg)
840{
841 unsigned reg = c->modrm_reg;
842 int highbyte_regs = c->rex_prefix == 0;
843
844 if (!(c->d & ModRM))
845 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
846
847 if (c->d & Sse) {
848 op->type = OP_XMM;
849 op->bytes = 16;
850 op->addr.xmm = reg;
851 read_sse_reg(ctxt, &op->vec_val, reg);
852 return;
853 }
854
855 op->type = OP_REG;
856 if ((c->d & ByteOp) && !inhibit_bytereg) {
857 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
858 op->bytes = 1;
859 } else {
860 op->addr.reg = decode_register(reg, c->regs, 0);
861 op->bytes = c->op_bytes;
862 }
863 fetch_register_operand(op);
864 op->orig_val = op->val;
865}
866
867static int decode_modrm(struct x86_emulate_ctxt *ctxt,
868 struct x86_emulate_ops *ops,
869 struct operand *op)
870{
871 struct decode_cache *c = &ctxt->decode;
872 u8 sib;
873 int index_reg = 0, base_reg = 0, scale;
874 int rc = X86EMUL_CONTINUE;
875 ulong modrm_ea = 0;
876
877 if (c->rex_prefix) {
878 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
879 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
880 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
881 }
882
883 c->modrm = insn_fetch(u8, 1, c->eip);
884 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
885 c->modrm_reg |= (c->modrm & 0x38) >> 3;
886 c->modrm_rm |= (c->modrm & 0x07);
887 c->modrm_seg = VCPU_SREG_DS;
888
889 if (c->modrm_mod == 3) {
890 op->type = OP_REG;
891 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
892 op->addr.reg = decode_register(c->modrm_rm,
893 c->regs, c->d & ByteOp);
894 if (c->d & Sse) {
895 op->type = OP_XMM;
896 op->bytes = 16;
897 op->addr.xmm = c->modrm_rm;
898 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
899 return rc;
900 }
901 fetch_register_operand(op);
902 return rc;
903 }
904
905 op->type = OP_MEM;
906
907 if (c->ad_bytes == 2) {
908 unsigned bx = c->regs[VCPU_REGS_RBX];
909 unsigned bp = c->regs[VCPU_REGS_RBP];
910 unsigned si = c->regs[VCPU_REGS_RSI];
911 unsigned di = c->regs[VCPU_REGS_RDI];
912
913 /* 16-bit ModR/M decode. */
914 switch (c->modrm_mod) {
915 case 0:
916 if (c->modrm_rm == 6)
917 modrm_ea += insn_fetch(u16, 2, c->eip);
918 break;
919 case 1:
920 modrm_ea += insn_fetch(s8, 1, c->eip);
921 break;
922 case 2:
923 modrm_ea += insn_fetch(u16, 2, c->eip);
924 break;
925 }
926 switch (c->modrm_rm) {
927 case 0:
928 modrm_ea += bx + si;
929 break;
930 case 1:
931 modrm_ea += bx + di;
932 break;
933 case 2:
934 modrm_ea += bp + si;
935 break;
936 case 3:
937 modrm_ea += bp + di;
938 break;
939 case 4:
940 modrm_ea += si;
941 break;
942 case 5:
943 modrm_ea += di;
944 break;
945 case 6:
946 if (c->modrm_mod != 0)
947 modrm_ea += bp;
948 break;
949 case 7:
950 modrm_ea += bx;
951 break;
952 }
953 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
954 (c->modrm_rm == 6 && c->modrm_mod != 0))
955 c->modrm_seg = VCPU_SREG_SS;
956 modrm_ea = (u16)modrm_ea;
957 } else {
958 /* 32/64-bit ModR/M decode. */
959 if ((c->modrm_rm & 7) == 4) {
960 sib = insn_fetch(u8, 1, c->eip);
961 index_reg |= (sib >> 3) & 7;
962 base_reg |= sib & 7;
963 scale = sib >> 6;
964
965 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
966 modrm_ea += insn_fetch(s32, 4, c->eip);
967 else
968 modrm_ea += c->regs[base_reg];
969 if (index_reg != 4)
970 modrm_ea += c->regs[index_reg] << scale;
971 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
972 if (ctxt->mode == X86EMUL_MODE_PROT64)
973 c->rip_relative = 1;
974 } else
975 modrm_ea += c->regs[c->modrm_rm];
976 switch (c->modrm_mod) {
977 case 0:
978 if (c->modrm_rm == 5)
979 modrm_ea += insn_fetch(s32, 4, c->eip);
980 break;
981 case 1:
982 modrm_ea += insn_fetch(s8, 1, c->eip);
983 break;
984 case 2:
985 modrm_ea += insn_fetch(s32, 4, c->eip);
986 break;
987 }
988 }
989 op->addr.mem.ea = modrm_ea;
990done:
991 return rc;
992}
993
994static int decode_abs(struct x86_emulate_ctxt *ctxt,
995 struct x86_emulate_ops *ops,
996 struct operand *op)
997{
998 struct decode_cache *c = &ctxt->decode;
999 int rc = X86EMUL_CONTINUE;
1000
1001 op->type = OP_MEM;
1002 switch (c->ad_bytes) {
1003 case 2:
1004 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1005 break;
1006 case 4:
1007 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1008 break;
1009 case 8:
1010 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1011 break;
1012 }
1013done:
1014 return rc;
1015}
1016
1017static void fetch_bit_operand(struct decode_cache *c)
1018{
1019 long sv = 0, mask;
1020
1021 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1022 mask = ~(c->dst.bytes * 8 - 1);
1023
1024 if (c->src.bytes == 2)
1025 sv = (s16)c->src.val & (s16)mask;
1026 else if (c->src.bytes == 4)
1027 sv = (s32)c->src.val & (s32)mask;
1028
1029 c->dst.addr.mem.ea += (sv >> 3);
1030 }
1031
1032 /* only subword offset */
1033 c->src.val &= (c->dst.bytes << 3) - 1;
1034}
1035
1036static int read_emulated(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 unsigned long addr, void *dest, unsigned size)
1039{
1040 int rc;
1041 struct read_cache *mc = &ctxt->decode.mem_read;
1042
1043 while (size) {
1044 int n = min(size, 8u);
1045 size -= n;
1046 if (mc->pos < mc->end)
1047 goto read_cached;
1048
1049 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1050 &ctxt->exception);
1051 if (rc != X86EMUL_CONTINUE)
1052 return rc;
1053 mc->end += n;
1054
1055 read_cached:
1056 memcpy(dest, mc->data + mc->pos, n);
1057 mc->pos += n;
1058 dest += n;
1059 addr += n;
1060 }
1061 return X86EMUL_CONTINUE;
1062}
1063
1064static int segmented_read(struct x86_emulate_ctxt *ctxt,
1065 struct segmented_address addr,
1066 void *data,
1067 unsigned size)
1068{
1069 int rc;
1070 ulong linear;
1071
1072 rc = linearize(ctxt, addr, size, false, &linear);
1073 if (rc != X86EMUL_CONTINUE)
1074 return rc;
1075 return read_emulated(ctxt, ctxt->ops, linear, data, size);
1076}
1077
1078static int segmented_write(struct x86_emulate_ctxt *ctxt,
1079 struct segmented_address addr,
1080 const void *data,
1081 unsigned size)
1082{
1083 int rc;
1084 ulong linear;
1085
1086 rc = linearize(ctxt, addr, size, true, &linear);
1087 if (rc != X86EMUL_CONTINUE)
1088 return rc;
1089 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1090 &ctxt->exception);
1091}
1092
1093static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1094 struct segmented_address addr,
1095 const void *orig_data, const void *data,
1096 unsigned size)
1097{
1098 int rc;
1099 ulong linear;
1100
1101 rc = linearize(ctxt, addr, size, true, &linear);
1102 if (rc != X86EMUL_CONTINUE)
1103 return rc;
1104 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1105 size, &ctxt->exception);
1106}
1107
1108static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1109 struct x86_emulate_ops *ops,
1110 unsigned int size, unsigned short port,
1111 void *dest)
1112{
1113 struct read_cache *rc = &ctxt->decode.io_read;
1114
1115 if (rc->pos == rc->end) { /* refill pio read ahead */
1116 struct decode_cache *c = &ctxt->decode;
1117 unsigned int in_page, n;
1118 unsigned int count = c->rep_prefix ?
1119 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1120 in_page = (ctxt->eflags & EFLG_DF) ?
1121 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1122 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1123 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1124 count);
1125 if (n == 0)
1126 n = 1;
1127 rc->pos = rc->end = 0;
1128 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1129 return 0;
1130 rc->end = n * size;
1131 }
1132
1133 memcpy(dest, rc->data + rc->pos, size);
1134 rc->pos += size;
1135 return 1;
1136}
1137
1138static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops,
1140 u16 selector, struct desc_ptr *dt)
1141{
1142 if (selector & 1 << 2) {
1143 struct desc_struct desc;
1144 memset (dt, 0, sizeof *dt);
1145 if (!ops->get_cached_descriptor(ctxt, &desc, NULL,
1146 VCPU_SREG_LDTR))
1147 return;
1148
1149 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1150 dt->address = get_desc_base(&desc);
1151 } else
1152 ops->get_gdt(ctxt, dt);
1153}
1154
1155/* allowed just for 8 bytes segments */
1156static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1157 struct x86_emulate_ops *ops,
1158 u16 selector, struct desc_struct *desc)
1159{
1160 struct desc_ptr dt;
1161 u16 index = selector >> 3;
1162 int ret;
1163 ulong addr;
1164
1165 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1166
1167 if (dt.size < index * 8 + 7)
1168 return emulate_gp(ctxt, selector & 0xfffc);
1169 addr = dt.address + index * 8;
1170 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1171
1172 return ret;
1173}
1174
1175/* allowed just for 8 bytes segments */
1176static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1177 struct x86_emulate_ops *ops,
1178 u16 selector, struct desc_struct *desc)
1179{
1180 struct desc_ptr dt;
1181 u16 index = selector >> 3;
1182 ulong addr;
1183 int ret;
1184
1185 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1186
1187 if (dt.size < index * 8 + 7)
1188 return emulate_gp(ctxt, selector & 0xfffc);
1189
1190 addr = dt.address + index * 8;
1191 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1192
1193 return ret;
1194}
1195
1196/* Does not support long mode */
1197static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, int seg)
1200{
1201 struct desc_struct seg_desc;
1202 u8 dpl, rpl, cpl;
1203 unsigned err_vec = GP_VECTOR;
1204 u32 err_code = 0;
1205 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1206 int ret;
1207
1208 memset(&seg_desc, 0, sizeof seg_desc);
1209
1210 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1211 || ctxt->mode == X86EMUL_MODE_REAL) {
1212 /* set real mode segment descriptor */
1213 set_desc_base(&seg_desc, selector << 4);
1214 set_desc_limit(&seg_desc, 0xffff);
1215 seg_desc.type = 3;
1216 seg_desc.p = 1;
1217 seg_desc.s = 1;
1218 goto load;
1219 }
1220
1221 /* NULL selector is not valid for TR, CS and SS */
1222 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1223 && null_selector)
1224 goto exception;
1225
1226 /* TR should be in GDT only */
1227 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1228 goto exception;
1229
1230 if (null_selector) /* for NULL selector skip all following checks */
1231 goto load;
1232
1233 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1234 if (ret != X86EMUL_CONTINUE)
1235 return ret;
1236
1237 err_code = selector & 0xfffc;
1238 err_vec = GP_VECTOR;
1239
1240 /* can't load system descriptor into segment selecor */
1241 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1242 goto exception;
1243
1244 if (!seg_desc.p) {
1245 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1246 goto exception;
1247 }
1248
1249 rpl = selector & 3;
1250 dpl = seg_desc.dpl;
1251 cpl = ops->cpl(ctxt);
1252
1253 switch (seg) {
1254 case VCPU_SREG_SS:
1255 /*
1256 * segment is not a writable data segment or segment
1257 * selector's RPL != CPL or segment selector's RPL != CPL
1258 */
1259 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1260 goto exception;
1261 break;
1262 case VCPU_SREG_CS:
1263 if (!(seg_desc.type & 8))
1264 goto exception;
1265
1266 if (seg_desc.type & 4) {
1267 /* conforming */
1268 if (dpl > cpl)
1269 goto exception;
1270 } else {
1271 /* nonconforming */
1272 if (rpl > cpl || dpl != cpl)
1273 goto exception;
1274 }
1275 /* CS(RPL) <- CPL */
1276 selector = (selector & 0xfffc) | cpl;
1277 break;
1278 case VCPU_SREG_TR:
1279 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1280 goto exception;
1281 break;
1282 case VCPU_SREG_LDTR:
1283 if (seg_desc.s || seg_desc.type != 2)
1284 goto exception;
1285 break;
1286 default: /* DS, ES, FS, or GS */
1287 /*
1288 * segment is not a data or readable code segment or
1289 * ((segment is a data or nonconforming code segment)
1290 * and (both RPL and CPL > DPL))
1291 */
1292 if ((seg_desc.type & 0xa) == 0x8 ||
1293 (((seg_desc.type & 0xc) != 0xc) &&
1294 (rpl > dpl && cpl > dpl)))
1295 goto exception;
1296 break;
1297 }
1298
1299 if (seg_desc.s) {
1300 /* mark segment as accessed */
1301 seg_desc.type |= 1;
1302 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1303 if (ret != X86EMUL_CONTINUE)
1304 return ret;
1305 }
1306load:
1307 ops->set_segment_selector(ctxt, selector, seg);
1308 ops->set_cached_descriptor(ctxt, &seg_desc, 0, seg);
1309 return X86EMUL_CONTINUE;
1310exception:
1311 emulate_exception(ctxt, err_vec, err_code, true);
1312 return X86EMUL_PROPAGATE_FAULT;
1313}
1314
1315static void write_register_operand(struct operand *op)
1316{
1317 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1318 switch (op->bytes) {
1319 case 1:
1320 *(u8 *)op->addr.reg = (u8)op->val;
1321 break;
1322 case 2:
1323 *(u16 *)op->addr.reg = (u16)op->val;
1324 break;
1325 case 4:
1326 *op->addr.reg = (u32)op->val;
1327 break; /* 64b: zero-extend */
1328 case 8:
1329 *op->addr.reg = op->val;
1330 break;
1331 }
1332}
1333
1334static inline int writeback(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops)
1336{
1337 int rc;
1338 struct decode_cache *c = &ctxt->decode;
1339
1340 switch (c->dst.type) {
1341 case OP_REG:
1342 write_register_operand(&c->dst);
1343 break;
1344 case OP_MEM:
1345 if (c->lock_prefix)
1346 rc = segmented_cmpxchg(ctxt,
1347 c->dst.addr.mem,
1348 &c->dst.orig_val,
1349 &c->dst.val,
1350 c->dst.bytes);
1351 else
1352 rc = segmented_write(ctxt,
1353 c->dst.addr.mem,
1354 &c->dst.val,
1355 c->dst.bytes);
1356 if (rc != X86EMUL_CONTINUE)
1357 return rc;
1358 break;
1359 case OP_XMM:
1360 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1361 break;
1362 case OP_NONE:
1363 /* no writeback */
1364 break;
1365 default:
1366 break;
1367 }
1368 return X86EMUL_CONTINUE;
1369}
1370
1371static int em_push(struct x86_emulate_ctxt *ctxt)
1372{
1373 struct decode_cache *c = &ctxt->decode;
1374 struct segmented_address addr;
1375
1376 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1377 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1378 addr.seg = VCPU_SREG_SS;
1379
1380 /* Disable writeback. */
1381 c->dst.type = OP_NONE;
1382 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1383}
1384
1385static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1386 struct x86_emulate_ops *ops,
1387 void *dest, int len)
1388{
1389 struct decode_cache *c = &ctxt->decode;
1390 int rc;
1391 struct segmented_address addr;
1392
1393 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1394 addr.seg = VCPU_SREG_SS;
1395 rc = segmented_read(ctxt, addr, dest, len);
1396 if (rc != X86EMUL_CONTINUE)
1397 return rc;
1398
1399 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1400 return rc;
1401}
1402
1403static int em_pop(struct x86_emulate_ctxt *ctxt)
1404{
1405 struct decode_cache *c = &ctxt->decode;
1406
1407 return emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1408}
1409
1410static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1411 struct x86_emulate_ops *ops,
1412 void *dest, int len)
1413{
1414 int rc;
1415 unsigned long val, change_mask;
1416 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1417 int cpl = ops->cpl(ctxt);
1418
1419 rc = emulate_pop(ctxt, ops, &val, len);
1420 if (rc != X86EMUL_CONTINUE)
1421 return rc;
1422
1423 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1424 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1425
1426 switch(ctxt->mode) {
1427 case X86EMUL_MODE_PROT64:
1428 case X86EMUL_MODE_PROT32:
1429 case X86EMUL_MODE_PROT16:
1430 if (cpl == 0)
1431 change_mask |= EFLG_IOPL;
1432 if (cpl <= iopl)
1433 change_mask |= EFLG_IF;
1434 break;
1435 case X86EMUL_MODE_VM86:
1436 if (iopl < 3)
1437 return emulate_gp(ctxt, 0);
1438 change_mask |= EFLG_IF;
1439 break;
1440 default: /* real mode */
1441 change_mask |= (EFLG_IOPL | EFLG_IF);
1442 break;
1443 }
1444
1445 *(unsigned long *)dest =
1446 (ctxt->eflags & ~change_mask) | (val & change_mask);
1447
1448 return rc;
1449}
1450
1451static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1452 struct x86_emulate_ops *ops, int seg)
1453{
1454 struct decode_cache *c = &ctxt->decode;
1455
1456 c->src.val = ops->get_segment_selector(ctxt, seg);
1457
1458 return em_push(ctxt);
1459}
1460
1461static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1462 struct x86_emulate_ops *ops, int seg)
1463{
1464 struct decode_cache *c = &ctxt->decode;
1465 unsigned long selector;
1466 int rc;
1467
1468 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1469 if (rc != X86EMUL_CONTINUE)
1470 return rc;
1471
1472 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1473 return rc;
1474}
1475
1476static int emulate_pusha(struct x86_emulate_ctxt *ctxt)
1477{
1478 struct decode_cache *c = &ctxt->decode;
1479 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1480 int rc = X86EMUL_CONTINUE;
1481 int reg = VCPU_REGS_RAX;
1482
1483 while (reg <= VCPU_REGS_RDI) {
1484 (reg == VCPU_REGS_RSP) ?
1485 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1486
1487 rc = em_push(ctxt);
1488 if (rc != X86EMUL_CONTINUE)
1489 return rc;
1490
1491 ++reg;
1492 }
1493
1494 return rc;
1495}
1496
1497static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1498 struct x86_emulate_ops *ops)
1499{
1500 struct decode_cache *c = &ctxt->decode;
1501 int rc = X86EMUL_CONTINUE;
1502 int reg = VCPU_REGS_RDI;
1503
1504 while (reg >= VCPU_REGS_RAX) {
1505 if (reg == VCPU_REGS_RSP) {
1506 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1507 c->op_bytes);
1508 --reg;
1509 }
1510
1511 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1512 if (rc != X86EMUL_CONTINUE)
1513 break;
1514 --reg;
1515 }
1516 return rc;
1517}
1518
1519int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1520 struct x86_emulate_ops *ops, int irq)
1521{
1522 struct decode_cache *c = &ctxt->decode;
1523 int rc;
1524 struct desc_ptr dt;
1525 gva_t cs_addr;
1526 gva_t eip_addr;
1527 u16 cs, eip;
1528
1529 /* TODO: Add limit checks */
1530 c->src.val = ctxt->eflags;
1531 rc = em_push(ctxt);
1532 if (rc != X86EMUL_CONTINUE)
1533 return rc;
1534
1535 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1536
1537 c->src.val = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
1538 rc = em_push(ctxt);
1539 if (rc != X86EMUL_CONTINUE)
1540 return rc;
1541
1542 c->src.val = c->eip;
1543 rc = em_push(ctxt);
1544 if (rc != X86EMUL_CONTINUE)
1545 return rc;
1546
1547 ops->get_idt(ctxt, &dt);
1548
1549 eip_addr = dt.address + (irq << 2);
1550 cs_addr = dt.address + (irq << 2) + 2;
1551
1552 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1553 if (rc != X86EMUL_CONTINUE)
1554 return rc;
1555
1556 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1557 if (rc != X86EMUL_CONTINUE)
1558 return rc;
1559
1560 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1561 if (rc != X86EMUL_CONTINUE)
1562 return rc;
1563
1564 c->eip = eip;
1565
1566 return rc;
1567}
1568
1569static int emulate_int(struct x86_emulate_ctxt *ctxt,
1570 struct x86_emulate_ops *ops, int irq)
1571{
1572 switch(ctxt->mode) {
1573 case X86EMUL_MODE_REAL:
1574 return emulate_int_real(ctxt, ops, irq);
1575 case X86EMUL_MODE_VM86:
1576 case X86EMUL_MODE_PROT16:
1577 case X86EMUL_MODE_PROT32:
1578 case X86EMUL_MODE_PROT64:
1579 default:
1580 /* Protected mode interrupts unimplemented yet */
1581 return X86EMUL_UNHANDLEABLE;
1582 }
1583}
1584
1585static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1586 struct x86_emulate_ops *ops)
1587{
1588 struct decode_cache *c = &ctxt->decode;
1589 int rc = X86EMUL_CONTINUE;
1590 unsigned long temp_eip = 0;
1591 unsigned long temp_eflags = 0;
1592 unsigned long cs = 0;
1593 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1594 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1595 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1596 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1597
1598 /* TODO: Add stack limit check */
1599
1600 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1601
1602 if (rc != X86EMUL_CONTINUE)
1603 return rc;
1604
1605 if (temp_eip & ~0xffff)
1606 return emulate_gp(ctxt, 0);
1607
1608 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1609
1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
1612
1613 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1614
1615 if (rc != X86EMUL_CONTINUE)
1616 return rc;
1617
1618 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1619
1620 if (rc != X86EMUL_CONTINUE)
1621 return rc;
1622
1623 c->eip = temp_eip;
1624
1625
1626 if (c->op_bytes == 4)
1627 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1628 else if (c->op_bytes == 2) {
1629 ctxt->eflags &= ~0xffff;
1630 ctxt->eflags |= temp_eflags;
1631 }
1632
1633 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1634 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1635
1636 return rc;
1637}
1638
1639static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1640 struct x86_emulate_ops* ops)
1641{
1642 switch(ctxt->mode) {
1643 case X86EMUL_MODE_REAL:
1644 return emulate_iret_real(ctxt, ops);
1645 case X86EMUL_MODE_VM86:
1646 case X86EMUL_MODE_PROT16:
1647 case X86EMUL_MODE_PROT32:
1648 case X86EMUL_MODE_PROT64:
1649 default:
1650 /* iret from protected mode unimplemented yet */
1651 return X86EMUL_UNHANDLEABLE;
1652 }
1653}
1654
1655static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1656 struct x86_emulate_ops *ops)
1657{
1658 struct decode_cache *c = &ctxt->decode;
1659
1660 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1661}
1662
1663static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1664{
1665 struct decode_cache *c = &ctxt->decode;
1666 switch (c->modrm_reg) {
1667 case 0: /* rol */
1668 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1669 break;
1670 case 1: /* ror */
1671 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1672 break;
1673 case 2: /* rcl */
1674 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1675 break;
1676 case 3: /* rcr */
1677 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1678 break;
1679 case 4: /* sal/shl */
1680 case 6: /* sal/shl */
1681 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1682 break;
1683 case 5: /* shr */
1684 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1685 break;
1686 case 7: /* sar */
1687 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1688 break;
1689 }
1690}
1691
1692static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1693 struct x86_emulate_ops *ops)
1694{
1695 struct decode_cache *c = &ctxt->decode;
1696 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1697 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1698 u8 de = 0;
1699
1700 switch (c->modrm_reg) {
1701 case 0 ... 1: /* test */
1702 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1703 break;
1704 case 2: /* not */
1705 c->dst.val = ~c->dst.val;
1706 break;
1707 case 3: /* neg */
1708 emulate_1op("neg", c->dst, ctxt->eflags);
1709 break;
1710 case 4: /* mul */
1711 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1712 break;
1713 case 5: /* imul */
1714 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1715 break;
1716 case 6: /* div */
1717 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1718 ctxt->eflags, de);
1719 break;
1720 case 7: /* idiv */
1721 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1722 ctxt->eflags, de);
1723 break;
1724 default:
1725 return X86EMUL_UNHANDLEABLE;
1726 }
1727 if (de)
1728 return emulate_de(ctxt);
1729 return X86EMUL_CONTINUE;
1730}
1731
1732static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
1733{
1734 struct decode_cache *c = &ctxt->decode;
1735 int rc = X86EMUL_CONTINUE;
1736
1737 switch (c->modrm_reg) {
1738 case 0: /* inc */
1739 emulate_1op("inc", c->dst, ctxt->eflags);
1740 break;
1741 case 1: /* dec */
1742 emulate_1op("dec", c->dst, ctxt->eflags);
1743 break;
1744 case 2: /* call near abs */ {
1745 long int old_eip;
1746 old_eip = c->eip;
1747 c->eip = c->src.val;
1748 c->src.val = old_eip;
1749 rc = em_push(ctxt);
1750 break;
1751 }
1752 case 4: /* jmp abs */
1753 c->eip = c->src.val;
1754 break;
1755 case 6: /* push */
1756 rc = em_push(ctxt);
1757 break;
1758 }
1759 return rc;
1760}
1761
1762static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1763 struct x86_emulate_ops *ops)
1764{
1765 struct decode_cache *c = &ctxt->decode;
1766 u64 old = c->dst.orig_val64;
1767
1768 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1769 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1770 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1771 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1772 ctxt->eflags &= ~EFLG_ZF;
1773 } else {
1774 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1775 (u32) c->regs[VCPU_REGS_RBX];
1776
1777 ctxt->eflags |= EFLG_ZF;
1778 }
1779 return X86EMUL_CONTINUE;
1780}
1781
1782static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1783 struct x86_emulate_ops *ops)
1784{
1785 struct decode_cache *c = &ctxt->decode;
1786 int rc;
1787 unsigned long cs;
1788
1789 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1790 if (rc != X86EMUL_CONTINUE)
1791 return rc;
1792 if (c->op_bytes == 4)
1793 c->eip = (u32)c->eip;
1794 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1795 if (rc != X86EMUL_CONTINUE)
1796 return rc;
1797 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1798 return rc;
1799}
1800
1801static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1802 struct x86_emulate_ops *ops, int seg)
1803{
1804 struct decode_cache *c = &ctxt->decode;
1805 unsigned short sel;
1806 int rc;
1807
1808 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1809
1810 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1811 if (rc != X86EMUL_CONTINUE)
1812 return rc;
1813
1814 c->dst.val = c->src.val;
1815 return rc;
1816}
1817
1818static inline void
1819setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1820 struct x86_emulate_ops *ops, struct desc_struct *cs,
1821 struct desc_struct *ss)
1822{
1823 memset(cs, 0, sizeof(struct desc_struct));
1824 ops->get_cached_descriptor(ctxt, cs, NULL, VCPU_SREG_CS);
1825 memset(ss, 0, sizeof(struct desc_struct));
1826
1827 cs->l = 0; /* will be adjusted later */
1828 set_desc_base(cs, 0); /* flat segment */
1829 cs->g = 1; /* 4kb granularity */
1830 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1831 cs->type = 0x0b; /* Read, Execute, Accessed */
1832 cs->s = 1;
1833 cs->dpl = 0; /* will be adjusted later */
1834 cs->p = 1;
1835 cs->d = 1;
1836
1837 set_desc_base(ss, 0); /* flat segment */
1838 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1839 ss->g = 1; /* 4kb granularity */
1840 ss->s = 1;
1841 ss->type = 0x03; /* Read/Write, Accessed */
1842 ss->d = 1; /* 32bit stack segment */
1843 ss->dpl = 0;
1844 ss->p = 1;
1845}
1846
1847static int
1848emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1849{
1850 struct decode_cache *c = &ctxt->decode;
1851 struct desc_struct cs, ss;
1852 u64 msr_data;
1853 u16 cs_sel, ss_sel;
1854 u64 efer = 0;
1855
1856 /* syscall is not available in real mode */
1857 if (ctxt->mode == X86EMUL_MODE_REAL ||
1858 ctxt->mode == X86EMUL_MODE_VM86)
1859 return emulate_ud(ctxt);
1860
1861 ops->get_msr(ctxt, MSR_EFER, &efer);
1862 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1863
1864 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1865 msr_data >>= 32;
1866 cs_sel = (u16)(msr_data & 0xfffc);
1867 ss_sel = (u16)(msr_data + 8);
1868
1869 if (efer & EFER_LMA) {
1870 cs.d = 0;
1871 cs.l = 1;
1872 }
1873 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1874 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1875 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1876 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1877
1878 c->regs[VCPU_REGS_RCX] = c->eip;
1879 if (efer & EFER_LMA) {
1880#ifdef CONFIG_X86_64
1881 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1882
1883 ops->get_msr(ctxt,
1884 ctxt->mode == X86EMUL_MODE_PROT64 ?
1885 MSR_LSTAR : MSR_CSTAR, &msr_data);
1886 c->eip = msr_data;
1887
1888 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1889 ctxt->eflags &= ~(msr_data | EFLG_RF);
1890#endif
1891 } else {
1892 /* legacy mode */
1893 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1894 c->eip = (u32)msr_data;
1895
1896 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1897 }
1898
1899 return X86EMUL_CONTINUE;
1900}
1901
1902static int
1903emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1904{
1905 struct decode_cache *c = &ctxt->decode;
1906 struct desc_struct cs, ss;
1907 u64 msr_data;
1908 u16 cs_sel, ss_sel;
1909 u64 efer = 0;
1910
1911 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1912 /* inject #GP if in real mode */
1913 if (ctxt->mode == X86EMUL_MODE_REAL)
1914 return emulate_gp(ctxt, 0);
1915
1916 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1917 * Therefore, we inject an #UD.
1918 */
1919 if (ctxt->mode == X86EMUL_MODE_PROT64)
1920 return emulate_ud(ctxt);
1921
1922 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1923
1924 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1925 switch (ctxt->mode) {
1926 case X86EMUL_MODE_PROT32:
1927 if ((msr_data & 0xfffc) == 0x0)
1928 return emulate_gp(ctxt, 0);
1929 break;
1930 case X86EMUL_MODE_PROT64:
1931 if (msr_data == 0x0)
1932 return emulate_gp(ctxt, 0);
1933 break;
1934 }
1935
1936 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1937 cs_sel = (u16)msr_data;
1938 cs_sel &= ~SELECTOR_RPL_MASK;
1939 ss_sel = cs_sel + 8;
1940 ss_sel &= ~SELECTOR_RPL_MASK;
1941 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1942 cs.d = 0;
1943 cs.l = 1;
1944 }
1945
1946 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1947 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1948 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1949 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1950
1951 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1952 c->eip = msr_data;
1953
1954 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1955 c->regs[VCPU_REGS_RSP] = msr_data;
1956
1957 return X86EMUL_CONTINUE;
1958}
1959
1960static int
1961emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1962{
1963 struct decode_cache *c = &ctxt->decode;
1964 struct desc_struct cs, ss;
1965 u64 msr_data;
1966 int usermode;
1967 u16 cs_sel, ss_sel;
1968
1969 /* inject #GP if in real mode or Virtual 8086 mode */
1970 if (ctxt->mode == X86EMUL_MODE_REAL ||
1971 ctxt->mode == X86EMUL_MODE_VM86)
1972 return emulate_gp(ctxt, 0);
1973
1974 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1975
1976 if ((c->rex_prefix & 0x8) != 0x0)
1977 usermode = X86EMUL_MODE_PROT64;
1978 else
1979 usermode = X86EMUL_MODE_PROT32;
1980
1981 cs.dpl = 3;
1982 ss.dpl = 3;
1983 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1984 switch (usermode) {
1985 case X86EMUL_MODE_PROT32:
1986 cs_sel = (u16)(msr_data + 16);
1987 if ((msr_data & 0xfffc) == 0x0)
1988 return emulate_gp(ctxt, 0);
1989 ss_sel = (u16)(msr_data + 24);
1990 break;
1991 case X86EMUL_MODE_PROT64:
1992 cs_sel = (u16)(msr_data + 32);
1993 if (msr_data == 0x0)
1994 return emulate_gp(ctxt, 0);
1995 ss_sel = cs_sel + 8;
1996 cs.d = 0;
1997 cs.l = 1;
1998 break;
1999 }
2000 cs_sel |= SELECTOR_RPL_MASK;
2001 ss_sel |= SELECTOR_RPL_MASK;
2002
2003 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
2004 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
2005 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
2006 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
2007
2008 c->eip = c->regs[VCPU_REGS_RDX];
2009 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2010
2011 return X86EMUL_CONTINUE;
2012}
2013
2014static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2015 struct x86_emulate_ops *ops)
2016{
2017 int iopl;
2018 if (ctxt->mode == X86EMUL_MODE_REAL)
2019 return false;
2020 if (ctxt->mode == X86EMUL_MODE_VM86)
2021 return true;
2022 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2023 return ops->cpl(ctxt) > iopl;
2024}
2025
2026static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2027 struct x86_emulate_ops *ops,
2028 u16 port, u16 len)
2029{
2030 struct desc_struct tr_seg;
2031 u32 base3;
2032 int r;
2033 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
2034 unsigned mask = (1 << len) - 1;
2035 unsigned long base;
2036
2037 ops->get_cached_descriptor(ctxt, &tr_seg, &base3, VCPU_SREG_TR);
2038 if (!tr_seg.p)
2039 return false;
2040 if (desc_limit_scaled(&tr_seg) < 103)
2041 return false;
2042 base = get_desc_base(&tr_seg);
2043#ifdef CONFIG_X86_64
2044 base |= ((u64)base3) << 32;
2045#endif
2046 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2047 if (r != X86EMUL_CONTINUE)
2048 return false;
2049 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2050 return false;
2051 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2052 if (r != X86EMUL_CONTINUE)
2053 return false;
2054 if ((perm >> bit_idx) & mask)
2055 return false;
2056 return true;
2057}
2058
2059static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2060 struct x86_emulate_ops *ops,
2061 u16 port, u16 len)
2062{
2063 if (ctxt->perm_ok)
2064 return true;
2065
2066 if (emulator_bad_iopl(ctxt, ops))
2067 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2068 return false;
2069
2070 ctxt->perm_ok = true;
2071
2072 return true;
2073}
2074
2075static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2076 struct x86_emulate_ops *ops,
2077 struct tss_segment_16 *tss)
2078{
2079 struct decode_cache *c = &ctxt->decode;
2080
2081 tss->ip = c->eip;
2082 tss->flag = ctxt->eflags;
2083 tss->ax = c->regs[VCPU_REGS_RAX];
2084 tss->cx = c->regs[VCPU_REGS_RCX];
2085 tss->dx = c->regs[VCPU_REGS_RDX];
2086 tss->bx = c->regs[VCPU_REGS_RBX];
2087 tss->sp = c->regs[VCPU_REGS_RSP];
2088 tss->bp = c->regs[VCPU_REGS_RBP];
2089 tss->si = c->regs[VCPU_REGS_RSI];
2090 tss->di = c->regs[VCPU_REGS_RDI];
2091
2092 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2093 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2094 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2095 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2096 tss->ldt = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2097}
2098
2099static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2100 struct x86_emulate_ops *ops,
2101 struct tss_segment_16 *tss)
2102{
2103 struct decode_cache *c = &ctxt->decode;
2104 int ret;
2105
2106 c->eip = tss->ip;
2107 ctxt->eflags = tss->flag | 2;
2108 c->regs[VCPU_REGS_RAX] = tss->ax;
2109 c->regs[VCPU_REGS_RCX] = tss->cx;
2110 c->regs[VCPU_REGS_RDX] = tss->dx;
2111 c->regs[VCPU_REGS_RBX] = tss->bx;
2112 c->regs[VCPU_REGS_RSP] = tss->sp;
2113 c->regs[VCPU_REGS_RBP] = tss->bp;
2114 c->regs[VCPU_REGS_RSI] = tss->si;
2115 c->regs[VCPU_REGS_RDI] = tss->di;
2116
2117 /*
2118 * SDM says that segment selectors are loaded before segment
2119 * descriptors
2120 */
2121 ops->set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2122 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2123 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2124 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2125 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2126
2127 /*
2128 * Now load segment descriptors. If fault happenes at this stage
2129 * it is handled in a context of new task
2130 */
2131 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2132 if (ret != X86EMUL_CONTINUE)
2133 return ret;
2134 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2135 if (ret != X86EMUL_CONTINUE)
2136 return ret;
2137 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2138 if (ret != X86EMUL_CONTINUE)
2139 return ret;
2140 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2141 if (ret != X86EMUL_CONTINUE)
2142 return ret;
2143 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2144 if (ret != X86EMUL_CONTINUE)
2145 return ret;
2146
2147 return X86EMUL_CONTINUE;
2148}
2149
2150static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2151 struct x86_emulate_ops *ops,
2152 u16 tss_selector, u16 old_tss_sel,
2153 ulong old_tss_base, struct desc_struct *new_desc)
2154{
2155 struct tss_segment_16 tss_seg;
2156 int ret;
2157 u32 new_tss_base = get_desc_base(new_desc);
2158
2159 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2160 &ctxt->exception);
2161 if (ret != X86EMUL_CONTINUE)
2162 /* FIXME: need to provide precise fault address */
2163 return ret;
2164
2165 save_state_to_tss16(ctxt, ops, &tss_seg);
2166
2167 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2168 &ctxt->exception);
2169 if (ret != X86EMUL_CONTINUE)
2170 /* FIXME: need to provide precise fault address */
2171 return ret;
2172
2173 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2174 &ctxt->exception);
2175 if (ret != X86EMUL_CONTINUE)
2176 /* FIXME: need to provide precise fault address */
2177 return ret;
2178
2179 if (old_tss_sel != 0xffff) {
2180 tss_seg.prev_task_link = old_tss_sel;
2181
2182 ret = ops->write_std(ctxt, new_tss_base,
2183 &tss_seg.prev_task_link,
2184 sizeof tss_seg.prev_task_link,
2185 &ctxt->exception);
2186 if (ret != X86EMUL_CONTINUE)
2187 /* FIXME: need to provide precise fault address */
2188 return ret;
2189 }
2190
2191 return load_state_from_tss16(ctxt, ops, &tss_seg);
2192}
2193
2194static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2195 struct x86_emulate_ops *ops,
2196 struct tss_segment_32 *tss)
2197{
2198 struct decode_cache *c = &ctxt->decode;
2199
2200 tss->cr3 = ops->get_cr(ctxt, 3);
2201 tss->eip = c->eip;
2202 tss->eflags = ctxt->eflags;
2203 tss->eax = c->regs[VCPU_REGS_RAX];
2204 tss->ecx = c->regs[VCPU_REGS_RCX];
2205 tss->edx = c->regs[VCPU_REGS_RDX];
2206 tss->ebx = c->regs[VCPU_REGS_RBX];
2207 tss->esp = c->regs[VCPU_REGS_RSP];
2208 tss->ebp = c->regs[VCPU_REGS_RBP];
2209 tss->esi = c->regs[VCPU_REGS_RSI];
2210 tss->edi = c->regs[VCPU_REGS_RDI];
2211
2212 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2213 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2214 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2215 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2216 tss->fs = ops->get_segment_selector(ctxt, VCPU_SREG_FS);
2217 tss->gs = ops->get_segment_selector(ctxt, VCPU_SREG_GS);
2218 tss->ldt_selector = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2219}
2220
2221static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2222 struct x86_emulate_ops *ops,
2223 struct tss_segment_32 *tss)
2224{
2225 struct decode_cache *c = &ctxt->decode;
2226 int ret;
2227
2228 if (ops->set_cr(ctxt, 3, tss->cr3))
2229 return emulate_gp(ctxt, 0);
2230 c->eip = tss->eip;
2231 ctxt->eflags = tss->eflags | 2;
2232 c->regs[VCPU_REGS_RAX] = tss->eax;
2233 c->regs[VCPU_REGS_RCX] = tss->ecx;
2234 c->regs[VCPU_REGS_RDX] = tss->edx;
2235 c->regs[VCPU_REGS_RBX] = tss->ebx;
2236 c->regs[VCPU_REGS_RSP] = tss->esp;
2237 c->regs[VCPU_REGS_RBP] = tss->ebp;
2238 c->regs[VCPU_REGS_RSI] = tss->esi;
2239 c->regs[VCPU_REGS_RDI] = tss->edi;
2240
2241 /*
2242 * SDM says that segment selectors are loaded before segment
2243 * descriptors
2244 */
2245 ops->set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2246 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2247 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2248 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2249 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2250 ops->set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2251 ops->set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2252
2253 /*
2254 * Now load segment descriptors. If fault happenes at this stage
2255 * it is handled in a context of new task
2256 */
2257 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2258 if (ret != X86EMUL_CONTINUE)
2259 return ret;
2260 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2261 if (ret != X86EMUL_CONTINUE)
2262 return ret;
2263 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2264 if (ret != X86EMUL_CONTINUE)
2265 return ret;
2266 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2267 if (ret != X86EMUL_CONTINUE)
2268 return ret;
2269 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2270 if (ret != X86EMUL_CONTINUE)
2271 return ret;
2272 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2273 if (ret != X86EMUL_CONTINUE)
2274 return ret;
2275 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2276 if (ret != X86EMUL_CONTINUE)
2277 return ret;
2278
2279 return X86EMUL_CONTINUE;
2280}
2281
2282static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2283 struct x86_emulate_ops *ops,
2284 u16 tss_selector, u16 old_tss_sel,
2285 ulong old_tss_base, struct desc_struct *new_desc)
2286{
2287 struct tss_segment_32 tss_seg;
2288 int ret;
2289 u32 new_tss_base = get_desc_base(new_desc);
2290
2291 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2292 &ctxt->exception);
2293 if (ret != X86EMUL_CONTINUE)
2294 /* FIXME: need to provide precise fault address */
2295 return ret;
2296
2297 save_state_to_tss32(ctxt, ops, &tss_seg);
2298
2299 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2300 &ctxt->exception);
2301 if (ret != X86EMUL_CONTINUE)
2302 /* FIXME: need to provide precise fault address */
2303 return ret;
2304
2305 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2306 &ctxt->exception);
2307 if (ret != X86EMUL_CONTINUE)
2308 /* FIXME: need to provide precise fault address */
2309 return ret;
2310
2311 if (old_tss_sel != 0xffff) {
2312 tss_seg.prev_task_link = old_tss_sel;
2313
2314 ret = ops->write_std(ctxt, new_tss_base,
2315 &tss_seg.prev_task_link,
2316 sizeof tss_seg.prev_task_link,
2317 &ctxt->exception);
2318 if (ret != X86EMUL_CONTINUE)
2319 /* FIXME: need to provide precise fault address */
2320 return ret;
2321 }
2322
2323 return load_state_from_tss32(ctxt, ops, &tss_seg);
2324}
2325
2326static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2327 struct x86_emulate_ops *ops,
2328 u16 tss_selector, int reason,
2329 bool has_error_code, u32 error_code)
2330{
2331 struct desc_struct curr_tss_desc, next_tss_desc;
2332 int ret;
2333 u16 old_tss_sel = ops->get_segment_selector(ctxt, VCPU_SREG_TR);
2334 ulong old_tss_base =
2335 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2336 u32 desc_limit;
2337
2338 /* FIXME: old_tss_base == ~0 ? */
2339
2340 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2341 if (ret != X86EMUL_CONTINUE)
2342 return ret;
2343 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2344 if (ret != X86EMUL_CONTINUE)
2345 return ret;
2346
2347 /* FIXME: check that next_tss_desc is tss */
2348
2349 if (reason != TASK_SWITCH_IRET) {
2350 if ((tss_selector & 3) > next_tss_desc.dpl ||
2351 ops->cpl(ctxt) > next_tss_desc.dpl)
2352 return emulate_gp(ctxt, 0);
2353 }
2354
2355 desc_limit = desc_limit_scaled(&next_tss_desc);
2356 if (!next_tss_desc.p ||
2357 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2358 desc_limit < 0x2b)) {
2359 emulate_ts(ctxt, tss_selector & 0xfffc);
2360 return X86EMUL_PROPAGATE_FAULT;
2361 }
2362
2363 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2364 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2365 write_segment_descriptor(ctxt, ops, old_tss_sel,
2366 &curr_tss_desc);
2367 }
2368
2369 if (reason == TASK_SWITCH_IRET)
2370 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2371
2372 /* set back link to prev task only if NT bit is set in eflags
2373 note that old_tss_sel is not used afetr this point */
2374 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2375 old_tss_sel = 0xffff;
2376
2377 if (next_tss_desc.type & 8)
2378 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2379 old_tss_base, &next_tss_desc);
2380 else
2381 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2382 old_tss_base, &next_tss_desc);
2383 if (ret != X86EMUL_CONTINUE)
2384 return ret;
2385
2386 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2387 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2388
2389 if (reason != TASK_SWITCH_IRET) {
2390 next_tss_desc.type |= (1 << 1); /* set busy flag */
2391 write_segment_descriptor(ctxt, ops, tss_selector,
2392 &next_tss_desc);
2393 }
2394
2395 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2396 ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
2397 ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
2398
2399 if (has_error_code) {
2400 struct decode_cache *c = &ctxt->decode;
2401
2402 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2403 c->lock_prefix = 0;
2404 c->src.val = (unsigned long) error_code;
2405 ret = em_push(ctxt);
2406 }
2407
2408 return ret;
2409}
2410
2411int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2412 u16 tss_selector, int reason,
2413 bool has_error_code, u32 error_code)
2414{
2415 struct x86_emulate_ops *ops = ctxt->ops;
2416 struct decode_cache *c = &ctxt->decode;
2417 int rc;
2418
2419 c->eip = ctxt->eip;
2420 c->dst.type = OP_NONE;
2421
2422 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2423 has_error_code, error_code);
2424
2425 if (rc == X86EMUL_CONTINUE)
2426 ctxt->eip = c->eip;
2427
2428 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2429}
2430
2431static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2432 int reg, struct operand *op)
2433{
2434 struct decode_cache *c = &ctxt->decode;
2435 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2436
2437 register_address_increment(c, &c->regs[reg], df * op->bytes);
2438 op->addr.mem.ea = register_address(c, c->regs[reg]);
2439 op->addr.mem.seg = seg;
2440}
2441
2442static int em_das(struct x86_emulate_ctxt *ctxt)
2443{
2444 struct decode_cache *c = &ctxt->decode;
2445 u8 al, old_al;
2446 bool af, cf, old_cf;
2447
2448 cf = ctxt->eflags & X86_EFLAGS_CF;
2449 al = c->dst.val;
2450
2451 old_al = al;
2452 old_cf = cf;
2453 cf = false;
2454 af = ctxt->eflags & X86_EFLAGS_AF;
2455 if ((al & 0x0f) > 9 || af) {
2456 al -= 6;
2457 cf = old_cf | (al >= 250);
2458 af = true;
2459 } else {
2460 af = false;
2461 }
2462 if (old_al > 0x99 || old_cf) {
2463 al -= 0x60;
2464 cf = true;
2465 }
2466
2467 c->dst.val = al;
2468 /* Set PF, ZF, SF */
2469 c->src.type = OP_IMM;
2470 c->src.val = 0;
2471 c->src.bytes = 1;
2472 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2473 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2474 if (cf)
2475 ctxt->eflags |= X86_EFLAGS_CF;
2476 if (af)
2477 ctxt->eflags |= X86_EFLAGS_AF;
2478 return X86EMUL_CONTINUE;
2479}
2480
2481static int em_call_far(struct x86_emulate_ctxt *ctxt)
2482{
2483 struct decode_cache *c = &ctxt->decode;
2484 u16 sel, old_cs;
2485 ulong old_eip;
2486 int rc;
2487
2488 old_cs = ctxt->ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2489 old_eip = c->eip;
2490
2491 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2492 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2493 return X86EMUL_CONTINUE;
2494
2495 c->eip = 0;
2496 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2497
2498 c->src.val = old_cs;
2499 rc = em_push(ctxt);
2500 if (rc != X86EMUL_CONTINUE)
2501 return rc;
2502
2503 c->src.val = old_eip;
2504 return em_push(ctxt);
2505}
2506
2507static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2508{
2509 struct decode_cache *c = &ctxt->decode;
2510 int rc;
2511
2512 c->dst.type = OP_REG;
2513 c->dst.addr.reg = &c->eip;
2514 c->dst.bytes = c->op_bytes;
2515 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2516 if (rc != X86EMUL_CONTINUE)
2517 return rc;
2518 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2519 return X86EMUL_CONTINUE;
2520}
2521
2522static int em_add(struct x86_emulate_ctxt *ctxt)
2523{
2524 struct decode_cache *c = &ctxt->decode;
2525
2526 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2527 return X86EMUL_CONTINUE;
2528}
2529
2530static int em_or(struct x86_emulate_ctxt *ctxt)
2531{
2532 struct decode_cache *c = &ctxt->decode;
2533
2534 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2535 return X86EMUL_CONTINUE;
2536}
2537
2538static int em_adc(struct x86_emulate_ctxt *ctxt)
2539{
2540 struct decode_cache *c = &ctxt->decode;
2541
2542 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2543 return X86EMUL_CONTINUE;
2544}
2545
2546static int em_sbb(struct x86_emulate_ctxt *ctxt)
2547{
2548 struct decode_cache *c = &ctxt->decode;
2549
2550 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2551 return X86EMUL_CONTINUE;
2552}
2553
2554static int em_and(struct x86_emulate_ctxt *ctxt)
2555{
2556 struct decode_cache *c = &ctxt->decode;
2557
2558 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2559 return X86EMUL_CONTINUE;
2560}
2561
2562static int em_sub(struct x86_emulate_ctxt *ctxt)
2563{
2564 struct decode_cache *c = &ctxt->decode;
2565
2566 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2567 return X86EMUL_CONTINUE;
2568}
2569
2570static int em_xor(struct x86_emulate_ctxt *ctxt)
2571{
2572 struct decode_cache *c = &ctxt->decode;
2573
2574 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2575 return X86EMUL_CONTINUE;
2576}
2577
2578static int em_cmp(struct x86_emulate_ctxt *ctxt)
2579{
2580 struct decode_cache *c = &ctxt->decode;
2581
2582 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2583 /* Disable writeback. */
2584 c->dst.type = OP_NONE;
2585 return X86EMUL_CONTINUE;
2586}
2587
2588static int em_imul(struct x86_emulate_ctxt *ctxt)
2589{
2590 struct decode_cache *c = &ctxt->decode;
2591
2592 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2593 return X86EMUL_CONTINUE;
2594}
2595
2596static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2597{
2598 struct decode_cache *c = &ctxt->decode;
2599
2600 c->dst.val = c->src2.val;
2601 return em_imul(ctxt);
2602}
2603
2604static int em_cwd(struct x86_emulate_ctxt *ctxt)
2605{
2606 struct decode_cache *c = &ctxt->decode;
2607
2608 c->dst.type = OP_REG;
2609 c->dst.bytes = c->src.bytes;
2610 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2611 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2612
2613 return X86EMUL_CONTINUE;
2614}
2615
2616static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2617{
2618 struct decode_cache *c = &ctxt->decode;
2619 u64 tsc = 0;
2620
2621 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2622 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2623 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2624 return X86EMUL_CONTINUE;
2625}
2626
2627static int em_mov(struct x86_emulate_ctxt *ctxt)
2628{
2629 struct decode_cache *c = &ctxt->decode;
2630 c->dst.val = c->src.val;
2631 return X86EMUL_CONTINUE;
2632}
2633
2634static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2635{
2636 struct decode_cache *c = &ctxt->decode;
2637 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2638 return X86EMUL_CONTINUE;
2639}
2640
2641static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2642{
2643 struct decode_cache *c = &ctxt->decode;
2644 int rc;
2645 ulong linear;
2646
2647 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2648 if (rc == X86EMUL_CONTINUE)
2649 ctxt->ops->invlpg(ctxt, linear);
2650 /* Disable writeback. */
2651 c->dst.type = OP_NONE;
2652 return X86EMUL_CONTINUE;
2653}
2654
2655static int em_clts(struct x86_emulate_ctxt *ctxt)
2656{
2657 ulong cr0;
2658
2659 cr0 = ctxt->ops->get_cr(ctxt, 0);
2660 cr0 &= ~X86_CR0_TS;
2661 ctxt->ops->set_cr(ctxt, 0, cr0);
2662 return X86EMUL_CONTINUE;
2663}
2664
2665static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2666{
2667 struct decode_cache *c = &ctxt->decode;
2668 int rc;
2669
2670 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2671 return X86EMUL_UNHANDLEABLE;
2672
2673 rc = ctxt->ops->fix_hypercall(ctxt);
2674 if (rc != X86EMUL_CONTINUE)
2675 return rc;
2676
2677 /* Let the processor re-execute the fixed hypercall */
2678 c->eip = ctxt->eip;
2679 /* Disable writeback. */
2680 c->dst.type = OP_NONE;
2681 return X86EMUL_CONTINUE;
2682}
2683
2684static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2685{
2686 struct decode_cache *c = &ctxt->decode;
2687 struct desc_ptr desc_ptr;
2688 int rc;
2689
2690 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2691 &desc_ptr.size, &desc_ptr.address,
2692 c->op_bytes);
2693 if (rc != X86EMUL_CONTINUE)
2694 return rc;
2695 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2696 /* Disable writeback. */
2697 c->dst.type = OP_NONE;
2698 return X86EMUL_CONTINUE;
2699}
2700
2701static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2702{
2703 struct decode_cache *c = &ctxt->decode;
2704 int rc;
2705
2706 rc = ctxt->ops->fix_hypercall(ctxt);
2707
2708 /* Disable writeback. */
2709 c->dst.type = OP_NONE;
2710 return rc;
2711}
2712
2713static int em_lidt(struct x86_emulate_ctxt *ctxt)
2714{
2715 struct decode_cache *c = &ctxt->decode;
2716 struct desc_ptr desc_ptr;
2717 int rc;
2718
2719 rc = read_descriptor(ctxt, ctxt->ops, c->src.addr.mem,
2720 &desc_ptr.size,
2721 &desc_ptr.address,
2722 c->op_bytes);
2723 if (rc != X86EMUL_CONTINUE)
2724 return rc;
2725 ctxt->ops->set_idt(ctxt, &desc_ptr);
2726 /* Disable writeback. */
2727 c->dst.type = OP_NONE;
2728 return X86EMUL_CONTINUE;
2729}
2730
2731static int em_smsw(struct x86_emulate_ctxt *ctxt)
2732{
2733 struct decode_cache *c = &ctxt->decode;
2734
2735 c->dst.bytes = 2;
2736 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2737 return X86EMUL_CONTINUE;
2738}
2739
2740static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2741{
2742 struct decode_cache *c = &ctxt->decode;
2743 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2744 | (c->src.val & 0x0f));
2745 c->dst.type = OP_NONE;
2746 return X86EMUL_CONTINUE;
2747}
2748
2749static bool valid_cr(int nr)
2750{
2751 switch (nr) {
2752 case 0:
2753 case 2 ... 4:
2754 case 8:
2755 return true;
2756 default:
2757 return false;
2758 }
2759}
2760
2761static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2762{
2763 struct decode_cache *c = &ctxt->decode;
2764
2765 if (!valid_cr(c->modrm_reg))
2766 return emulate_ud(ctxt);
2767
2768 return X86EMUL_CONTINUE;
2769}
2770
2771static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2772{
2773 struct decode_cache *c = &ctxt->decode;
2774 u64 new_val = c->src.val64;
2775 int cr = c->modrm_reg;
2776 u64 efer = 0;
2777
2778 static u64 cr_reserved_bits[] = {
2779 0xffffffff00000000ULL,
2780 0, 0, 0, /* CR3 checked later */
2781 CR4_RESERVED_BITS,
2782 0, 0, 0,
2783 CR8_RESERVED_BITS,
2784 };
2785
2786 if (!valid_cr(cr))
2787 return emulate_ud(ctxt);
2788
2789 if (new_val & cr_reserved_bits[cr])
2790 return emulate_gp(ctxt, 0);
2791
2792 switch (cr) {
2793 case 0: {
2794 u64 cr4;
2795 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2796 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2797 return emulate_gp(ctxt, 0);
2798
2799 cr4 = ctxt->ops->get_cr(ctxt, 4);
2800 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2801
2802 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2803 !(cr4 & X86_CR4_PAE))
2804 return emulate_gp(ctxt, 0);
2805
2806 break;
2807 }
2808 case 3: {
2809 u64 rsvd = 0;
2810
2811 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2812 if (efer & EFER_LMA)
2813 rsvd = CR3_L_MODE_RESERVED_BITS;
2814 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2815 rsvd = CR3_PAE_RESERVED_BITS;
2816 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2817 rsvd = CR3_NONPAE_RESERVED_BITS;
2818
2819 if (new_val & rsvd)
2820 return emulate_gp(ctxt, 0);
2821
2822 break;
2823 }
2824 case 4: {
2825 u64 cr4;
2826
2827 cr4 = ctxt->ops->get_cr(ctxt, 4);
2828 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2829
2830 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2831 return emulate_gp(ctxt, 0);
2832
2833 break;
2834 }
2835 }
2836
2837 return X86EMUL_CONTINUE;
2838}
2839
2840static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2841{
2842 unsigned long dr7;
2843
2844 ctxt->ops->get_dr(ctxt, 7, &dr7);
2845
2846 /* Check if DR7.Global_Enable is set */
2847 return dr7 & (1 << 13);
2848}
2849
2850static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2851{
2852 struct decode_cache *c = &ctxt->decode;
2853 int dr = c->modrm_reg;
2854 u64 cr4;
2855
2856 if (dr > 7)
2857 return emulate_ud(ctxt);
2858
2859 cr4 = ctxt->ops->get_cr(ctxt, 4);
2860 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2861 return emulate_ud(ctxt);
2862
2863 if (check_dr7_gd(ctxt))
2864 return emulate_db(ctxt);
2865
2866 return X86EMUL_CONTINUE;
2867}
2868
2869static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2870{
2871 struct decode_cache *c = &ctxt->decode;
2872 u64 new_val = c->src.val64;
2873 int dr = c->modrm_reg;
2874
2875 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2876 return emulate_gp(ctxt, 0);
2877
2878 return check_dr_read(ctxt);
2879}
2880
2881static int check_svme(struct x86_emulate_ctxt *ctxt)
2882{
2883 u64 efer;
2884
2885 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2886
2887 if (!(efer & EFER_SVME))
2888 return emulate_ud(ctxt);
2889
2890 return X86EMUL_CONTINUE;
2891}
2892
2893static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2894{
2895 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
2896
2897 /* Valid physical address? */
2898 if (rax & 0xffff000000000000ULL)
2899 return emulate_gp(ctxt, 0);
2900
2901 return check_svme(ctxt);
2902}
2903
2904static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2905{
2906 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2907
2908 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2909 return emulate_ud(ctxt);
2910
2911 return X86EMUL_CONTINUE;
2912}
2913
2914static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2915{
2916 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2917 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
2918
2919 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2920 (rcx > 3))
2921 return emulate_gp(ctxt, 0);
2922
2923 return X86EMUL_CONTINUE;
2924}
2925
2926static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2927{
2928 struct decode_cache *c = &ctxt->decode;
2929
2930 c->dst.bytes = min(c->dst.bytes, 4u);
2931 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2932 return emulate_gp(ctxt, 0);
2933
2934 return X86EMUL_CONTINUE;
2935}
2936
2937static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2938{
2939 struct decode_cache *c = &ctxt->decode;
2940
2941 c->src.bytes = min(c->src.bytes, 4u);
2942 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2943 return emulate_gp(ctxt, 0);
2944
2945 return X86EMUL_CONTINUE;
2946}
2947
2948#define D(_y) { .flags = (_y) }
2949#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2950#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2951 .check_perm = (_p) }
2952#define N D(0)
2953#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2954#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2955#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2956#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2957#define II(_f, _e, _i) \
2958 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2959#define IIP(_f, _e, _i, _p) \
2960 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2961 .check_perm = (_p) }
2962#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2963
2964#define D2bv(_f) D((_f) | ByteOp), D(_f)
2965#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2966#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2967
2968#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2969 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2970 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
2971
2972static struct opcode group7_rm1[] = {
2973 DI(SrcNone | ModRM | Priv, monitor),
2974 DI(SrcNone | ModRM | Priv, mwait),
2975 N, N, N, N, N, N,
2976};
2977
2978static struct opcode group7_rm3[] = {
2979 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
2980 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
2981 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2982 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2983 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2984 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2985 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2986 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2987};
2988
2989static struct opcode group7_rm7[] = {
2990 N,
2991 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2992 N, N, N, N, N, N,
2993};
2994
2995static struct opcode group1[] = {
2996 I(Lock, em_add),
2997 I(Lock, em_or),
2998 I(Lock, em_adc),
2999 I(Lock, em_sbb),
3000 I(Lock, em_and),
3001 I(Lock, em_sub),
3002 I(Lock, em_xor),
3003 I(0, em_cmp),
3004};
3005
3006static struct opcode group1A[] = {
3007 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3008};
3009
3010static struct opcode group3[] = {
3011 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3012 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3013 X4(D(SrcMem | ModRM)),
3014};
3015
3016static struct opcode group4[] = {
3017 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3018 N, N, N, N, N, N,
3019};
3020
3021static struct opcode group5[] = {
3022 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3023 D(SrcMem | ModRM | Stack),
3024 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
3025 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3026 D(SrcMem | ModRM | Stack), N,
3027};
3028
3029static struct opcode group6[] = {
3030 DI(ModRM | Prot, sldt),
3031 DI(ModRM | Prot, str),
3032 DI(ModRM | Prot | Priv, lldt),
3033 DI(ModRM | Prot | Priv, ltr),
3034 N, N, N, N,
3035};
3036
3037static struct group_dual group7 = { {
3038 DI(ModRM | Mov | DstMem | Priv, sgdt),
3039 DI(ModRM | Mov | DstMem | Priv, sidt),
3040 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3041 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3042 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3043 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3044 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3045}, {
3046 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3047 EXT(0, group7_rm1),
3048 N, EXT(0, group7_rm3),
3049 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3050 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
3051} };
3052
3053static struct opcode group8[] = {
3054 N, N, N, N,
3055 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3056 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3057};
3058
3059static struct group_dual group9 = { {
3060 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3061}, {
3062 N, N, N, N, N, N, N, N,
3063} };
3064
3065static struct opcode group11[] = {
3066 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3067};
3068
3069static struct gprefix pfx_0f_6f_0f_7f = {
3070 N, N, N, I(Sse, em_movdqu),
3071};
3072
3073static struct opcode opcode_table[256] = {
3074 /* 0x00 - 0x07 */
3075 I6ALU(Lock, em_add),
3076 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3077 /* 0x08 - 0x0F */
3078 I6ALU(Lock, em_or),
3079 D(ImplicitOps | Stack | No64), N,
3080 /* 0x10 - 0x17 */
3081 I6ALU(Lock, em_adc),
3082 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3083 /* 0x18 - 0x1F */
3084 I6ALU(Lock, em_sbb),
3085 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3086 /* 0x20 - 0x27 */
3087 I6ALU(Lock, em_and), N, N,
3088 /* 0x28 - 0x2F */
3089 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3090 /* 0x30 - 0x37 */
3091 I6ALU(Lock, em_xor), N, N,
3092 /* 0x38 - 0x3F */
3093 I6ALU(0, em_cmp), N, N,
3094 /* 0x40 - 0x4F */
3095 X16(D(DstReg)),
3096 /* 0x50 - 0x57 */
3097 X8(I(SrcReg | Stack, em_push)),
3098 /* 0x58 - 0x5F */
3099 X8(I(DstReg | Stack, em_pop)),
3100 /* 0x60 - 0x67 */
3101 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3102 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3103 N, N, N, N,
3104 /* 0x68 - 0x6F */
3105 I(SrcImm | Mov | Stack, em_push),
3106 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3107 I(SrcImmByte | Mov | Stack, em_push),
3108 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3109 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3110 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
3111 /* 0x70 - 0x7F */
3112 X16(D(SrcImmByte)),
3113 /* 0x80 - 0x87 */
3114 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3115 G(DstMem | SrcImm | ModRM | Group, group1),
3116 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3117 G(DstMem | SrcImmByte | ModRM | Group, group1),
3118 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
3119 /* 0x88 - 0x8F */
3120 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3121 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3122 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
3123 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3124 /* 0x90 - 0x97 */
3125 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3126 /* 0x98 - 0x9F */
3127 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3128 I(SrcImmFAddr | No64, em_call_far), N,
3129 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
3130 /* 0xA0 - 0xA7 */
3131 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3132 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3133 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3134 I2bv(SrcSI | DstDI | String, em_cmp),
3135 /* 0xA8 - 0xAF */
3136 D2bv(DstAcc | SrcImm),
3137 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3138 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3139 I2bv(SrcAcc | DstDI | String, em_cmp),
3140 /* 0xB0 - 0xB7 */
3141 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3142 /* 0xB8 - 0xBF */
3143 X8(I(DstReg | SrcImm | Mov, em_mov)),
3144 /* 0xC0 - 0xC7 */
3145 D2bv(DstMem | SrcImmByte | ModRM),
3146 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3147 D(ImplicitOps | Stack),
3148 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3149 G(ByteOp, group11), G(0, group11),
3150 /* 0xC8 - 0xCF */
3151 N, N, N, D(ImplicitOps | Stack),
3152 D(ImplicitOps), DI(SrcImmByte, intn),
3153 D(ImplicitOps | No64), DI(ImplicitOps, iret),
3154 /* 0xD0 - 0xD7 */
3155 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3156 N, N, N, N,
3157 /* 0xD8 - 0xDF */
3158 N, N, N, N, N, N, N, N,
3159 /* 0xE0 - 0xE7 */
3160 X4(D(SrcImmByte)),
3161 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3162 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3163 /* 0xE8 - 0xEF */
3164 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3165 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
3166 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3167 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
3168 /* 0xF0 - 0xF7 */
3169 N, DI(ImplicitOps, icebp), N, N,
3170 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3171 G(ByteOp, group3), G(0, group3),
3172 /* 0xF8 - 0xFF */
3173 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
3174 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3175};
3176
3177static struct opcode twobyte_table[256] = {
3178 /* 0x00 - 0x0F */
3179 G(0, group6), GD(0, &group7), N, N,
3180 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3181 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3182 N, D(ImplicitOps | ModRM), N, N,
3183 /* 0x10 - 0x1F */
3184 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3185 /* 0x20 - 0x2F */
3186 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3187 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3188 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3189 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3190 N, N, N, N,
3191 N, N, N, N, N, N, N, N,
3192 /* 0x30 - 0x3F */
3193 DI(ImplicitOps | Priv, wrmsr),
3194 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3195 DI(ImplicitOps | Priv, rdmsr),
3196 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3197 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3198 N, N,
3199 N, N, N, N, N, N, N, N,
3200 /* 0x40 - 0x4F */
3201 X16(D(DstReg | SrcMem | ModRM | Mov)),
3202 /* 0x50 - 0x5F */
3203 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3204 /* 0x60 - 0x6F */
3205 N, N, N, N,
3206 N, N, N, N,
3207 N, N, N, N,
3208 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3209 /* 0x70 - 0x7F */
3210 N, N, N, N,
3211 N, N, N, N,
3212 N, N, N, N,
3213 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3214 /* 0x80 - 0x8F */
3215 X16(D(SrcImm)),
3216 /* 0x90 - 0x9F */
3217 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3218 /* 0xA0 - 0xA7 */
3219 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3220 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3221 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3222 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3223 /* 0xA8 - 0xAF */
3224 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3225 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3226 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3227 D(DstMem | SrcReg | Src2CL | ModRM),
3228 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3229 /* 0xB0 - 0xB7 */
3230 D2bv(DstMem | SrcReg | ModRM | Lock),
3231 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3232 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3233 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3234 /* 0xB8 - 0xBF */
3235 N, N,
3236 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3237 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3238 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3239 /* 0xC0 - 0xCF */
3240 D2bv(DstMem | SrcReg | ModRM | Lock),
3241 N, D(DstMem | SrcReg | ModRM | Mov),
3242 N, N, N, GD(0, &group9),
3243 N, N, N, N, N, N, N, N,
3244 /* 0xD0 - 0xDF */
3245 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3246 /* 0xE0 - 0xEF */
3247 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3248 /* 0xF0 - 0xFF */
3249 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3250};
3251
3252#undef D
3253#undef N
3254#undef G
3255#undef GD
3256#undef I
3257#undef GP
3258#undef EXT
3259
3260#undef D2bv
3261#undef D2bvIP
3262#undef I2bv
3263#undef I6ALU
3264
3265static unsigned imm_size(struct decode_cache *c)
3266{
3267 unsigned size;
3268
3269 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3270 if (size == 8)
3271 size = 4;
3272 return size;
3273}
3274
3275static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3276 unsigned size, bool sign_extension)
3277{
3278 struct decode_cache *c = &ctxt->decode;
3279 struct x86_emulate_ops *ops = ctxt->ops;
3280 int rc = X86EMUL_CONTINUE;
3281
3282 op->type = OP_IMM;
3283 op->bytes = size;
3284 op->addr.mem.ea = c->eip;
3285 /* NB. Immediates are sign-extended as necessary. */
3286 switch (op->bytes) {
3287 case 1:
3288 op->val = insn_fetch(s8, 1, c->eip);
3289 break;
3290 case 2:
3291 op->val = insn_fetch(s16, 2, c->eip);
3292 break;
3293 case 4:
3294 op->val = insn_fetch(s32, 4, c->eip);
3295 break;
3296 }
3297 if (!sign_extension) {
3298 switch (op->bytes) {
3299 case 1:
3300 op->val &= 0xff;
3301 break;
3302 case 2:
3303 op->val &= 0xffff;
3304 break;
3305 case 4:
3306 op->val &= 0xffffffff;
3307 break;
3308 }
3309 }
3310done:
3311 return rc;
3312}
3313
3314int
3315x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3316{
3317 struct x86_emulate_ops *ops = ctxt->ops;
3318 struct decode_cache *c = &ctxt->decode;
3319 int rc = X86EMUL_CONTINUE;
3320 int mode = ctxt->mode;
3321 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3322 bool op_prefix = false;
3323 struct opcode opcode, *g_mod012, *g_mod3;
3324 struct operand memop = { .type = OP_NONE };
3325
3326 c->eip = ctxt->eip;
3327 c->fetch.start = c->eip;
3328 c->fetch.end = c->fetch.start + insn_len;
3329 if (insn_len > 0)
3330 memcpy(c->fetch.data, insn, insn_len);
3331
3332 switch (mode) {
3333 case X86EMUL_MODE_REAL:
3334 case X86EMUL_MODE_VM86:
3335 case X86EMUL_MODE_PROT16:
3336 def_op_bytes = def_ad_bytes = 2;
3337 break;
3338 case X86EMUL_MODE_PROT32:
3339 def_op_bytes = def_ad_bytes = 4;
3340 break;
3341#ifdef CONFIG_X86_64
3342 case X86EMUL_MODE_PROT64:
3343 def_op_bytes = 4;
3344 def_ad_bytes = 8;
3345 break;
3346#endif
3347 default:
3348 return -1;
3349 }
3350
3351 c->op_bytes = def_op_bytes;
3352 c->ad_bytes = def_ad_bytes;
3353
3354 /* Legacy prefixes. */
3355 for (;;) {
3356 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3357 case 0x66: /* operand-size override */
3358 op_prefix = true;
3359 /* switch between 2/4 bytes */
3360 c->op_bytes = def_op_bytes ^ 6;
3361 break;
3362 case 0x67: /* address-size override */
3363 if (mode == X86EMUL_MODE_PROT64)
3364 /* switch between 4/8 bytes */
3365 c->ad_bytes = def_ad_bytes ^ 12;
3366 else
3367 /* switch between 2/4 bytes */
3368 c->ad_bytes = def_ad_bytes ^ 6;
3369 break;
3370 case 0x26: /* ES override */
3371 case 0x2e: /* CS override */
3372 case 0x36: /* SS override */
3373 case 0x3e: /* DS override */
3374 set_seg_override(c, (c->b >> 3) & 3);
3375 break;
3376 case 0x64: /* FS override */
3377 case 0x65: /* GS override */
3378 set_seg_override(c, c->b & 7);
3379 break;
3380 case 0x40 ... 0x4f: /* REX */
3381 if (mode != X86EMUL_MODE_PROT64)
3382 goto done_prefixes;
3383 c->rex_prefix = c->b;
3384 continue;
3385 case 0xf0: /* LOCK */
3386 c->lock_prefix = 1;
3387 break;
3388 case 0xf2: /* REPNE/REPNZ */
3389 case 0xf3: /* REP/REPE/REPZ */
3390 c->rep_prefix = c->b;
3391 break;
3392 default:
3393 goto done_prefixes;
3394 }
3395
3396 /* Any legacy prefix after a REX prefix nullifies its effect. */
3397
3398 c->rex_prefix = 0;
3399 }
3400
3401done_prefixes:
3402
3403 /* REX prefix. */
3404 if (c->rex_prefix & 8)
3405 c->op_bytes = 8; /* REX.W */
3406
3407 /* Opcode byte(s). */
3408 opcode = opcode_table[c->b];
3409 /* Two-byte opcode? */
3410 if (c->b == 0x0f) {
3411 c->twobyte = 1;
3412 c->b = insn_fetch(u8, 1, c->eip);
3413 opcode = twobyte_table[c->b];
3414 }
3415 c->d = opcode.flags;
3416
3417 if (c->d & Group) {
3418 dual = c->d & GroupDual;
3419 c->modrm = insn_fetch(u8, 1, c->eip);
3420 --c->eip;
3421
3422 if (c->d & GroupDual) {
3423 g_mod012 = opcode.u.gdual->mod012;
3424 g_mod3 = opcode.u.gdual->mod3;
3425 } else
3426 g_mod012 = g_mod3 = opcode.u.group;
3427
3428 c->d &= ~(Group | GroupDual);
3429
3430 goffset = (c->modrm >> 3) & 7;
3431
3432 if ((c->modrm >> 6) == 3)
3433 opcode = g_mod3[goffset];
3434 else
3435 opcode = g_mod012[goffset];
3436
3437 if (opcode.flags & RMExt) {
3438 goffset = c->modrm & 7;
3439 opcode = opcode.u.group[goffset];
3440 }
3441
3442 c->d |= opcode.flags;
3443 }
3444
3445 if (c->d & Prefix) {
3446 if (c->rep_prefix && op_prefix)
3447 return X86EMUL_UNHANDLEABLE;
3448 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3449 switch (simd_prefix) {
3450 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3451 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3452 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3453 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3454 }
3455 c->d |= opcode.flags;
3456 }
3457
3458 c->execute = opcode.u.execute;
3459 c->check_perm = opcode.check_perm;
3460 c->intercept = opcode.intercept;
3461
3462 /* Unrecognised? */
3463 if (c->d == 0 || (c->d & Undefined))
3464 return -1;
3465
3466 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3467 return -1;
3468
3469 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3470 c->op_bytes = 8;
3471
3472 if (c->d & Op3264) {
3473 if (mode == X86EMUL_MODE_PROT64)
3474 c->op_bytes = 8;
3475 else
3476 c->op_bytes = 4;
3477 }
3478
3479 if (c->d & Sse)
3480 c->op_bytes = 16;
3481
3482 /* ModRM and SIB bytes. */
3483 if (c->d & ModRM) {
3484 rc = decode_modrm(ctxt, ops, &memop);
3485 if (!c->has_seg_override)
3486 set_seg_override(c, c->modrm_seg);
3487 } else if (c->d & MemAbs)
3488 rc = decode_abs(ctxt, ops, &memop);
3489 if (rc != X86EMUL_CONTINUE)
3490 goto done;
3491
3492 if (!c->has_seg_override)
3493 set_seg_override(c, VCPU_SREG_DS);
3494
3495 memop.addr.mem.seg = seg_override(ctxt, ops, c);
3496
3497 if (memop.type == OP_MEM && c->ad_bytes != 8)
3498 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3499
3500 if (memop.type == OP_MEM && c->rip_relative)
3501 memop.addr.mem.ea += c->eip;
3502
3503 /*
3504 * Decode and fetch the source operand: register, memory
3505 * or immediate.
3506 */
3507 switch (c->d & SrcMask) {
3508 case SrcNone:
3509 break;
3510 case SrcReg:
3511 decode_register_operand(ctxt, &c->src, c, 0);
3512 break;
3513 case SrcMem16:
3514 memop.bytes = 2;
3515 goto srcmem_common;
3516 case SrcMem32:
3517 memop.bytes = 4;
3518 goto srcmem_common;
3519 case SrcMem:
3520 memop.bytes = (c->d & ByteOp) ? 1 :
3521 c->op_bytes;
3522 srcmem_common:
3523 c->src = memop;
3524 break;
3525 case SrcImmU16:
3526 rc = decode_imm(ctxt, &c->src, 2, false);
3527 break;
3528 case SrcImm:
3529 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3530 break;
3531 case SrcImmU:
3532 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3533 break;
3534 case SrcImmByte:
3535 rc = decode_imm(ctxt, &c->src, 1, true);
3536 break;
3537 case SrcImmUByte:
3538 rc = decode_imm(ctxt, &c->src, 1, false);
3539 break;
3540 case SrcAcc:
3541 c->src.type = OP_REG;
3542 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3543 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3544 fetch_register_operand(&c->src);
3545 break;
3546 case SrcOne:
3547 c->src.bytes = 1;
3548 c->src.val = 1;
3549 break;
3550 case SrcSI:
3551 c->src.type = OP_MEM;
3552 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3553 c->src.addr.mem.ea =
3554 register_address(c, c->regs[VCPU_REGS_RSI]);
3555 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
3556 c->src.val = 0;
3557 break;
3558 case SrcImmFAddr:
3559 c->src.type = OP_IMM;
3560 c->src.addr.mem.ea = c->eip;
3561 c->src.bytes = c->op_bytes + 2;
3562 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3563 break;
3564 case SrcMemFAddr:
3565 memop.bytes = c->op_bytes + 2;
3566 goto srcmem_common;
3567 break;
3568 }
3569
3570 if (rc != X86EMUL_CONTINUE)
3571 goto done;
3572
3573 /*
3574 * Decode and fetch the second source operand: register, memory
3575 * or immediate.
3576 */
3577 switch (c->d & Src2Mask) {
3578 case Src2None:
3579 break;
3580 case Src2CL:
3581 c->src2.bytes = 1;
3582 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3583 break;
3584 case Src2ImmByte:
3585 rc = decode_imm(ctxt, &c->src2, 1, true);
3586 break;
3587 case Src2One:
3588 c->src2.bytes = 1;
3589 c->src2.val = 1;
3590 break;
3591 case Src2Imm:
3592 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3593 break;
3594 }
3595
3596 if (rc != X86EMUL_CONTINUE)
3597 goto done;
3598
3599 /* Decode and fetch the destination operand: register or memory. */
3600 switch (c->d & DstMask) {
3601 case DstReg:
3602 decode_register_operand(ctxt, &c->dst, c,
3603 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3604 break;
3605 case DstImmUByte:
3606 c->dst.type = OP_IMM;
3607 c->dst.addr.mem.ea = c->eip;
3608 c->dst.bytes = 1;
3609 c->dst.val = insn_fetch(u8, 1, c->eip);
3610 break;
3611 case DstMem:
3612 case DstMem64:
3613 c->dst = memop;
3614 if ((c->d & DstMask) == DstMem64)
3615 c->dst.bytes = 8;
3616 else
3617 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3618 if (c->d & BitOp)
3619 fetch_bit_operand(c);
3620 c->dst.orig_val = c->dst.val;
3621 break;
3622 case DstAcc:
3623 c->dst.type = OP_REG;
3624 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3625 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3626 fetch_register_operand(&c->dst);
3627 c->dst.orig_val = c->dst.val;
3628 break;
3629 case DstDI:
3630 c->dst.type = OP_MEM;
3631 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3632 c->dst.addr.mem.ea =
3633 register_address(c, c->regs[VCPU_REGS_RDI]);
3634 c->dst.addr.mem.seg = VCPU_SREG_ES;
3635 c->dst.val = 0;
3636 break;
3637 case ImplicitOps:
3638 /* Special instructions do their own operand decoding. */
3639 default:
3640 c->dst.type = OP_NONE; /* Disable writeback. */
3641 return 0;
3642 }
3643
3644done:
3645 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3646}
3647
3648static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3649{
3650 struct decode_cache *c = &ctxt->decode;
3651
3652 /* The second termination condition only applies for REPE
3653 * and REPNE. Test if the repeat string operation prefix is
3654 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3655 * corresponding termination condition according to:
3656 * - if REPE/REPZ and ZF = 0 then done
3657 * - if REPNE/REPNZ and ZF = 1 then done
3658 */
3659 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3660 (c->b == 0xae) || (c->b == 0xaf))
3661 && (((c->rep_prefix == REPE_PREFIX) &&
3662 ((ctxt->eflags & EFLG_ZF) == 0))
3663 || ((c->rep_prefix == REPNE_PREFIX) &&
3664 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3665 return true;
3666
3667 return false;
3668}
3669
3670int
3671x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3672{
3673 struct x86_emulate_ops *ops = ctxt->ops;
3674 u64 msr_data;
3675 struct decode_cache *c = &ctxt->decode;
3676 int rc = X86EMUL_CONTINUE;
3677 int saved_dst_type = c->dst.type;
3678 int irq; /* Used for int 3, int, and into */
3679
3680 ctxt->decode.mem_read.pos = 0;
3681
3682 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3683 rc = emulate_ud(ctxt);
3684 goto done;
3685 }
3686
3687 /* LOCK prefix is allowed only with some instructions */
3688 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3689 rc = emulate_ud(ctxt);
3690 goto done;
3691 }
3692
3693 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3694 rc = emulate_ud(ctxt);
3695 goto done;
3696 }
3697
3698 if ((c->d & Sse)
3699 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3700 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
3701 rc = emulate_ud(ctxt);
3702 goto done;
3703 }
3704
3705 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
3706 rc = emulate_nm(ctxt);
3707 goto done;
3708 }
3709
3710 if (unlikely(ctxt->guest_mode) && c->intercept) {
3711 rc = emulator_check_intercept(ctxt, c->intercept,
3712 X86_ICPT_PRE_EXCEPT);
3713 if (rc != X86EMUL_CONTINUE)
3714 goto done;
3715 }
3716
3717 /* Privileged instruction can be executed only in CPL=0 */
3718 if ((c->d & Priv) && ops->cpl(ctxt)) {
3719 rc = emulate_gp(ctxt, 0);
3720 goto done;
3721 }
3722
3723 /* Instruction can only be executed in protected mode */
3724 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3725 rc = emulate_ud(ctxt);
3726 goto done;
3727 }
3728
3729 /* Do instruction specific permission checks */
3730 if (c->check_perm) {
3731 rc = c->check_perm(ctxt);
3732 if (rc != X86EMUL_CONTINUE)
3733 goto done;
3734 }
3735
3736 if (unlikely(ctxt->guest_mode) && c->intercept) {
3737 rc = emulator_check_intercept(ctxt, c->intercept,
3738 X86_ICPT_POST_EXCEPT);
3739 if (rc != X86EMUL_CONTINUE)
3740 goto done;
3741 }
3742
3743 if (c->rep_prefix && (c->d & String)) {
3744 /* All REP prefixes have the same first termination condition */
3745 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3746 ctxt->eip = c->eip;
3747 goto done;
3748 }
3749 }
3750
3751 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3752 rc = segmented_read(ctxt, c->src.addr.mem,
3753 c->src.valptr, c->src.bytes);
3754 if (rc != X86EMUL_CONTINUE)
3755 goto done;
3756 c->src.orig_val64 = c->src.val64;
3757 }
3758
3759 if (c->src2.type == OP_MEM) {
3760 rc = segmented_read(ctxt, c->src2.addr.mem,
3761 &c->src2.val, c->src2.bytes);
3762 if (rc != X86EMUL_CONTINUE)
3763 goto done;
3764 }
3765
3766 if ((c->d & DstMask) == ImplicitOps)
3767 goto special_insn;
3768
3769
3770 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3771 /* optimisation - avoid slow emulated read if Mov */
3772 rc = segmented_read(ctxt, c->dst.addr.mem,
3773 &c->dst.val, c->dst.bytes);
3774 if (rc != X86EMUL_CONTINUE)
3775 goto done;
3776 }
3777 c->dst.orig_val = c->dst.val;
3778
3779special_insn:
3780
3781 if (unlikely(ctxt->guest_mode) && c->intercept) {
3782 rc = emulator_check_intercept(ctxt, c->intercept,
3783 X86_ICPT_POST_MEMACCESS);
3784 if (rc != X86EMUL_CONTINUE)
3785 goto done;
3786 }
3787
3788 if (c->execute) {
3789 rc = c->execute(ctxt);
3790 if (rc != X86EMUL_CONTINUE)
3791 goto done;
3792 goto writeback;
3793 }
3794
3795 if (c->twobyte)
3796 goto twobyte_insn;
3797
3798 switch (c->b) {
3799 case 0x06: /* push es */
3800 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3801 break;
3802 case 0x07: /* pop es */
3803 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3804 break;
3805 case 0x0e: /* push cs */
3806 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3807 break;
3808 case 0x16: /* push ss */
3809 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3810 break;
3811 case 0x17: /* pop ss */
3812 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3813 break;
3814 case 0x1e: /* push ds */
3815 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3816 break;
3817 case 0x1f: /* pop ds */
3818 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3819 break;
3820 case 0x40 ... 0x47: /* inc r16/r32 */
3821 emulate_1op("inc", c->dst, ctxt->eflags);
3822 break;
3823 case 0x48 ... 0x4f: /* dec r16/r32 */
3824 emulate_1op("dec", c->dst, ctxt->eflags);
3825 break;
3826 case 0x60: /* pusha */
3827 rc = emulate_pusha(ctxt);
3828 break;
3829 case 0x61: /* popa */
3830 rc = emulate_popa(ctxt, ops);
3831 break;
3832 case 0x63: /* movsxd */
3833 if (ctxt->mode != X86EMUL_MODE_PROT64)
3834 goto cannot_emulate;
3835 c->dst.val = (s32) c->src.val;
3836 break;
3837 case 0x6c: /* insb */
3838 case 0x6d: /* insw/insd */
3839 c->src.val = c->regs[VCPU_REGS_RDX];
3840 goto do_io_in;
3841 case 0x6e: /* outsb */
3842 case 0x6f: /* outsw/outsd */
3843 c->dst.val = c->regs[VCPU_REGS_RDX];
3844 goto do_io_out;
3845 break;
3846 case 0x70 ... 0x7f: /* jcc (short) */
3847 if (test_cc(c->b, ctxt->eflags))
3848 jmp_rel(c, c->src.val);
3849 break;
3850 case 0x84 ... 0x85:
3851 test:
3852 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3853 break;
3854 case 0x86 ... 0x87: /* xchg */
3855 xchg:
3856 /* Write back the register source. */
3857 c->src.val = c->dst.val;
3858 write_register_operand(&c->src);
3859 /*
3860 * Write back the memory destination with implicit LOCK
3861 * prefix.
3862 */
3863 c->dst.val = c->src.orig_val;
3864 c->lock_prefix = 1;
3865 break;
3866 case 0x8c: /* mov r/m, sreg */
3867 if (c->modrm_reg > VCPU_SREG_GS) {
3868 rc = emulate_ud(ctxt);
3869 goto done;
3870 }
3871 c->dst.val = ops->get_segment_selector(ctxt, c->modrm_reg);
3872 break;
3873 case 0x8d: /* lea r16/r32, m */
3874 c->dst.val = c->src.addr.mem.ea;
3875 break;
3876 case 0x8e: { /* mov seg, r/m16 */
3877 uint16_t sel;
3878
3879 sel = c->src.val;
3880
3881 if (c->modrm_reg == VCPU_SREG_CS ||
3882 c->modrm_reg > VCPU_SREG_GS) {
3883 rc = emulate_ud(ctxt);
3884 goto done;
3885 }
3886
3887 if (c->modrm_reg == VCPU_SREG_SS)
3888 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3889
3890 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3891
3892 c->dst.type = OP_NONE; /* Disable writeback. */
3893 break;
3894 }
3895 case 0x8f: /* pop (sole member of Grp1a) */
3896 rc = emulate_grp1a(ctxt, ops);
3897 break;
3898 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3899 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3900 break;
3901 goto xchg;
3902 case 0x98: /* cbw/cwde/cdqe */
3903 switch (c->op_bytes) {
3904 case 2: c->dst.val = (s8)c->dst.val; break;
3905 case 4: c->dst.val = (s16)c->dst.val; break;
3906 case 8: c->dst.val = (s32)c->dst.val; break;
3907 }
3908 break;
3909 case 0x9c: /* pushf */
3910 c->src.val = (unsigned long) ctxt->eflags;
3911 rc = em_push(ctxt);
3912 break;
3913 case 0x9d: /* popf */
3914 c->dst.type = OP_REG;
3915 c->dst.addr.reg = &ctxt->eflags;
3916 c->dst.bytes = c->op_bytes;
3917 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3918 break;
3919 case 0xa8 ... 0xa9: /* test ax, imm */
3920 goto test;
3921 case 0xc0 ... 0xc1:
3922 emulate_grp2(ctxt);
3923 break;
3924 case 0xc3: /* ret */
3925 c->dst.type = OP_REG;
3926 c->dst.addr.reg = &c->eip;
3927 c->dst.bytes = c->op_bytes;
3928 rc = em_pop(ctxt);
3929 break;
3930 case 0xc4: /* les */
3931 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3932 break;
3933 case 0xc5: /* lds */
3934 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3935 break;
3936 case 0xcb: /* ret far */
3937 rc = emulate_ret_far(ctxt, ops);
3938 break;
3939 case 0xcc: /* int3 */
3940 irq = 3;
3941 goto do_interrupt;
3942 case 0xcd: /* int n */
3943 irq = c->src.val;
3944 do_interrupt:
3945 rc = emulate_int(ctxt, ops, irq);
3946 break;
3947 case 0xce: /* into */
3948 if (ctxt->eflags & EFLG_OF) {
3949 irq = 4;
3950 goto do_interrupt;
3951 }
3952 break;
3953 case 0xcf: /* iret */
3954 rc = emulate_iret(ctxt, ops);
3955 break;
3956 case 0xd0 ... 0xd1: /* Grp2 */
3957 emulate_grp2(ctxt);
3958 break;
3959 case 0xd2 ... 0xd3: /* Grp2 */
3960 c->src.val = c->regs[VCPU_REGS_RCX];
3961 emulate_grp2(ctxt);
3962 break;
3963 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3964 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3965 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3966 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3967 jmp_rel(c, c->src.val);
3968 break;
3969 case 0xe3: /* jcxz/jecxz/jrcxz */
3970 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3971 jmp_rel(c, c->src.val);
3972 break;
3973 case 0xe4: /* inb */
3974 case 0xe5: /* in */
3975 goto do_io_in;
3976 case 0xe6: /* outb */
3977 case 0xe7: /* out */
3978 goto do_io_out;
3979 case 0xe8: /* call (near) */ {
3980 long int rel = c->src.val;
3981 c->src.val = (unsigned long) c->eip;
3982 jmp_rel(c, rel);
3983 rc = em_push(ctxt);
3984 break;
3985 }
3986 case 0xe9: /* jmp rel */
3987 goto jmp;
3988 case 0xea: { /* jmp far */
3989 unsigned short sel;
3990 jump_far:
3991 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3992
3993 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3994 goto done;
3995
3996 c->eip = 0;
3997 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3998 break;
3999 }
4000 case 0xeb:
4001 jmp: /* jmp rel short */
4002 jmp_rel(c, c->src.val);
4003 c->dst.type = OP_NONE; /* Disable writeback. */
4004 break;
4005 case 0xec: /* in al,dx */
4006 case 0xed: /* in (e/r)ax,dx */
4007 c->src.val = c->regs[VCPU_REGS_RDX];
4008 do_io_in:
4009 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4010 &c->dst.val))
4011 goto done; /* IO is needed */
4012 break;
4013 case 0xee: /* out dx,al */
4014 case 0xef: /* out dx,(e/r)ax */
4015 c->dst.val = c->regs[VCPU_REGS_RDX];
4016 do_io_out:
4017 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4018 &c->src.val, 1);
4019 c->dst.type = OP_NONE; /* Disable writeback. */
4020 break;
4021 case 0xf4: /* hlt */
4022 ctxt->ops->halt(ctxt);
4023 break;
4024 case 0xf5: /* cmc */
4025 /* complement carry flag from eflags reg */
4026 ctxt->eflags ^= EFLG_CF;
4027 break;
4028 case 0xf6 ... 0xf7: /* Grp3 */
4029 rc = emulate_grp3(ctxt, ops);
4030 break;
4031 case 0xf8: /* clc */
4032 ctxt->eflags &= ~EFLG_CF;
4033 break;
4034 case 0xf9: /* stc */
4035 ctxt->eflags |= EFLG_CF;
4036 break;
4037 case 0xfa: /* cli */
4038 if (emulator_bad_iopl(ctxt, ops)) {
4039 rc = emulate_gp(ctxt, 0);
4040 goto done;
4041 } else
4042 ctxt->eflags &= ~X86_EFLAGS_IF;
4043 break;
4044 case 0xfb: /* sti */
4045 if (emulator_bad_iopl(ctxt, ops)) {
4046 rc = emulate_gp(ctxt, 0);
4047 goto done;
4048 } else {
4049 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
4050 ctxt->eflags |= X86_EFLAGS_IF;
4051 }
4052 break;
4053 case 0xfc: /* cld */
4054 ctxt->eflags &= ~EFLG_DF;
4055 break;
4056 case 0xfd: /* std */
4057 ctxt->eflags |= EFLG_DF;
4058 break;
4059 case 0xfe: /* Grp4 */
4060 grp45:
4061 rc = emulate_grp45(ctxt);
4062 break;
4063 case 0xff: /* Grp5 */
4064 if (c->modrm_reg == 5)
4065 goto jump_far;
4066 goto grp45;
4067 default:
4068 goto cannot_emulate;
4069 }
4070
4071 if (rc != X86EMUL_CONTINUE)
4072 goto done;
4073
4074writeback:
4075 rc = writeback(ctxt, ops);
4076 if (rc != X86EMUL_CONTINUE)
4077 goto done;
4078
4079 /*
4080 * restore dst type in case the decoding will be reused
4081 * (happens for string instruction )
4082 */
4083 c->dst.type = saved_dst_type;
4084
4085 if ((c->d & SrcMask) == SrcSI)
4086 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
4087 VCPU_REGS_RSI, &c->src);
4088
4089 if ((c->d & DstMask) == DstDI)
4090 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4091 &c->dst);
4092
4093 if (c->rep_prefix && (c->d & String)) {
4094 struct read_cache *r = &ctxt->decode.io_read;
4095 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
4096
4097 if (!string_insn_completed(ctxt)) {
4098 /*
4099 * Re-enter guest when pio read ahead buffer is empty
4100 * or, if it is not used, after each 1024 iteration.
4101 */
4102 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4103 (r->end == 0 || r->end != r->pos)) {
4104 /*
4105 * Reset read cache. Usually happens before
4106 * decode, but since instruction is restarted
4107 * we have to do it here.
4108 */
4109 ctxt->decode.mem_read.end = 0;
4110 return EMULATION_RESTART;
4111 }
4112 goto done; /* skip rip writeback */
4113 }
4114 }
4115
4116 ctxt->eip = c->eip;
4117
4118done:
4119 if (rc == X86EMUL_PROPAGATE_FAULT)
4120 ctxt->have_exception = true;
4121 if (rc == X86EMUL_INTERCEPTED)
4122 return EMULATION_INTERCEPTED;
4123
4124 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4125
4126twobyte_insn:
4127 switch (c->b) {
4128 case 0x05: /* syscall */
4129 rc = emulate_syscall(ctxt, ops);
4130 break;
4131 case 0x06:
4132 rc = em_clts(ctxt);
4133 break;
4134 case 0x09: /* wbinvd */
4135 (ctxt->ops->wbinvd)(ctxt);
4136 break;
4137 case 0x08: /* invd */
4138 case 0x0d: /* GrpP (prefetch) */
4139 case 0x18: /* Grp16 (prefetch/nop) */
4140 break;
4141 case 0x20: /* mov cr, reg */
4142 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
4143 break;
4144 case 0x21: /* mov from dr to reg */
4145 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
4146 break;
4147 case 0x22: /* mov reg, cr */
4148 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
4149 emulate_gp(ctxt, 0);
4150 rc = X86EMUL_PROPAGATE_FAULT;
4151 goto done;
4152 }
4153 c->dst.type = OP_NONE;
4154 break;
4155 case 0x23: /* mov from reg to dr */
4156 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
4157 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4158 ~0ULL : ~0U)) < 0) {
4159 /* #UD condition is already handled by the code above */
4160 emulate_gp(ctxt, 0);
4161 rc = X86EMUL_PROPAGATE_FAULT;
4162 goto done;
4163 }
4164
4165 c->dst.type = OP_NONE; /* no writeback */
4166 break;
4167 case 0x30:
4168 /* wrmsr */
4169 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4170 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
4171 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
4172 emulate_gp(ctxt, 0);
4173 rc = X86EMUL_PROPAGATE_FAULT;
4174 goto done;
4175 }
4176 rc = X86EMUL_CONTINUE;
4177 break;
4178 case 0x32:
4179 /* rdmsr */
4180 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
4181 emulate_gp(ctxt, 0);
4182 rc = X86EMUL_PROPAGATE_FAULT;
4183 goto done;
4184 } else {
4185 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4186 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4187 }
4188 rc = X86EMUL_CONTINUE;
4189 break;
4190 case 0x34: /* sysenter */
4191 rc = emulate_sysenter(ctxt, ops);
4192 break;
4193 case 0x35: /* sysexit */
4194 rc = emulate_sysexit(ctxt, ops);
4195 break;
4196 case 0x40 ... 0x4f: /* cmov */
4197 c->dst.val = c->dst.orig_val = c->src.val;
4198 if (!test_cc(c->b, ctxt->eflags))
4199 c->dst.type = OP_NONE; /* no writeback */
4200 break;
4201 case 0x80 ... 0x8f: /* jnz rel, etc*/
4202 if (test_cc(c->b, ctxt->eflags))
4203 jmp_rel(c, c->src.val);
4204 break;
4205 case 0x90 ... 0x9f: /* setcc r/m8 */
4206 c->dst.val = test_cc(c->b, ctxt->eflags);
4207 break;
4208 case 0xa0: /* push fs */
4209 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4210 break;
4211 case 0xa1: /* pop fs */
4212 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
4213 break;
4214 case 0xa3:
4215 bt: /* bt */
4216 c->dst.type = OP_NONE;
4217 /* only subword offset */
4218 c->src.val &= (c->dst.bytes << 3) - 1;
4219 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4220 break;
4221 case 0xa4: /* shld imm8, r, r/m */
4222 case 0xa5: /* shld cl, r, r/m */
4223 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4224 break;
4225 case 0xa8: /* push gs */
4226 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4227 break;
4228 case 0xa9: /* pop gs */
4229 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
4230 break;
4231 case 0xab:
4232 bts: /* bts */
4233 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4234 break;
4235 case 0xac: /* shrd imm8, r, r/m */
4236 case 0xad: /* shrd cl, r, r/m */
4237 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4238 break;
4239 case 0xae: /* clflush */
4240 break;
4241 case 0xb0 ... 0xb1: /* cmpxchg */
4242 /*
4243 * Save real source value, then compare EAX against
4244 * destination.
4245 */
4246 c->src.orig_val = c->src.val;
4247 c->src.val = c->regs[VCPU_REGS_RAX];
4248 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4249 if (ctxt->eflags & EFLG_ZF) {
4250 /* Success: write back to memory. */
4251 c->dst.val = c->src.orig_val;
4252 } else {
4253 /* Failure: write the value we saw to EAX. */
4254 c->dst.type = OP_REG;
4255 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
4256 }
4257 break;
4258 case 0xb2: /* lss */
4259 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
4260 break;
4261 case 0xb3:
4262 btr: /* btr */
4263 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
4264 break;
4265 case 0xb4: /* lfs */
4266 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
4267 break;
4268 case 0xb5: /* lgs */
4269 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
4270 break;
4271 case 0xb6 ... 0xb7: /* movzx */
4272 c->dst.bytes = c->op_bytes;
4273 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4274 : (u16) c->src.val;
4275 break;
4276 case 0xba: /* Grp8 */
4277 switch (c->modrm_reg & 3) {
4278 case 0:
4279 goto bt;
4280 case 1:
4281 goto bts;
4282 case 2:
4283 goto btr;
4284 case 3:
4285 goto btc;
4286 }
4287 break;
4288 case 0xbb:
4289 btc: /* btc */
4290 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4291 break;
4292 case 0xbc: { /* bsf */
4293 u8 zf;
4294 __asm__ ("bsf %2, %0; setz %1"
4295 : "=r"(c->dst.val), "=q"(zf)
4296 : "r"(c->src.val));
4297 ctxt->eflags &= ~X86_EFLAGS_ZF;
4298 if (zf) {
4299 ctxt->eflags |= X86_EFLAGS_ZF;
4300 c->dst.type = OP_NONE; /* Disable writeback. */
4301 }
4302 break;
4303 }
4304 case 0xbd: { /* bsr */
4305 u8 zf;
4306 __asm__ ("bsr %2, %0; setz %1"
4307 : "=r"(c->dst.val), "=q"(zf)
4308 : "r"(c->src.val));
4309 ctxt->eflags &= ~X86_EFLAGS_ZF;
4310 if (zf) {
4311 ctxt->eflags |= X86_EFLAGS_ZF;
4312 c->dst.type = OP_NONE; /* Disable writeback. */
4313 }
4314 break;
4315 }
4316 case 0xbe ... 0xbf: /* movsx */
4317 c->dst.bytes = c->op_bytes;
4318 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4319 (s16) c->src.val;
4320 break;
4321 case 0xc0 ... 0xc1: /* xadd */
4322 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4323 /* Write back the register source. */
4324 c->src.val = c->dst.orig_val;
4325 write_register_operand(&c->src);
4326 break;
4327 case 0xc3: /* movnti */
4328 c->dst.bytes = c->op_bytes;
4329 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4330 (u64) c->src.val;
4331 break;
4332 case 0xc7: /* Grp9 (cmpxchg8b) */
4333 rc = emulate_grp9(ctxt, ops);
4334 break;
4335 default:
4336 goto cannot_emulate;
4337 }
4338
4339 if (rc != X86EMUL_CONTINUE)
4340 goto done;
4341
4342 goto writeback;
4343
4344cannot_emulate:
4345 return EMULATION_FAILED;
4346}
Linux kernel - Deliverables
This page took 0.039802 seconds and 5 git commands to generate.