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KVM: x86: deliver phys lowest-prio
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
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1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21#include <linux/kvm_host.h>
22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/math64.h>
30#include <linux/slab.h>
31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
36#include <linux/atomic.h>
37#include <linux/jump_label.h>
38#include "kvm_cache_regs.h"
39#include "irq.h"
40#include "trace.h"
41#include "x86.h"
42#include "cpuid.h"
43
44#ifndef CONFIG_X86_64
45#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46#else
47#define mod_64(x, y) ((x) % (y))
48#endif
49
50#define PRId64 "d"
51#define PRIx64 "llx"
52#define PRIu64 "u"
53#define PRIo64 "o"
54
55#define APIC_BUS_CYCLE_NS 1
56
57/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58#define apic_debug(fmt, arg...)
59
60#define APIC_LVT_NUM 6
61/* 14 is the version for Xeon and Pentium 8.4.8*/
62#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63#define LAPIC_MMIO_LENGTH (1 << 12)
64/* followed define is not in apicdef.h */
65#define APIC_SHORT_MASK 0xc0000
66#define APIC_DEST_NOSHORT 0x0
67#define APIC_DEST_MASK 0x800
68#define MAX_APIC_VECTOR 256
69#define APIC_VECTORS_PER_REG 32
70
71#define APIC_BROADCAST 0xFF
72#define X2APIC_BROADCAST 0xFFFFFFFFul
73
74#define VEC_POS(v) ((v) & (32 - 1))
75#define REG_POS(v) (((v) >> 5) << 4)
76
77static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78{
79 *((u32 *) (apic->regs + reg_off)) = val;
80}
81
82static inline int apic_test_vector(int vec, void *bitmap)
83{
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85}
86
87bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
88{
89 struct kvm_lapic *apic = vcpu->arch.apic;
90
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
93}
94
95static inline void apic_set_vector(int vec, void *bitmap)
96{
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98}
99
100static inline void apic_clear_vector(int vec, void *bitmap)
101{
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103}
104
105static inline int __apic_test_and_set_vector(int vec, void *bitmap)
106{
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
108}
109
110static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
111{
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
113}
114
115struct static_key_deferred apic_hw_disabled __read_mostly;
116struct static_key_deferred apic_sw_disabled __read_mostly;
117
118static inline int apic_enabled(struct kvm_lapic *apic)
119{
120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
121}
122
123#define LVT_MASK \
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
125
126#define LINT_MASK \
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
129
130static inline int kvm_apic_id(struct kvm_lapic *apic)
131{
132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
133}
134
135#define KVM_X2APIC_CID_BITS 0
136
137static void recalculate_apic_map(struct kvm *kvm)
138{
139 struct kvm_apic_map *new, *old = NULL;
140 struct kvm_vcpu *vcpu;
141 int i;
142
143 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
144
145 mutex_lock(&kvm->arch.apic_map_lock);
146
147 if (!new)
148 goto out;
149
150 new->ldr_bits = 8;
151 /* flat mode is default */
152 new->cid_shift = 8;
153 new->cid_mask = 0;
154 new->lid_mask = 0xff;
155 new->broadcast = APIC_BROADCAST;
156
157 kvm_for_each_vcpu(i, vcpu, kvm) {
158 struct kvm_lapic *apic = vcpu->arch.apic;
159
160 if (!kvm_apic_present(vcpu))
161 continue;
162
163 if (apic_x2apic_mode(apic)) {
164 new->ldr_bits = 32;
165 new->cid_shift = 16;
166 new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
167 new->lid_mask = 0xffff;
168 new->broadcast = X2APIC_BROADCAST;
169 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
170 if (kvm_apic_get_reg(apic, APIC_DFR) ==
171 APIC_DFR_CLUSTER) {
172 new->cid_shift = 4;
173 new->cid_mask = 0xf;
174 new->lid_mask = 0xf;
175 } else {
176 new->cid_shift = 8;
177 new->cid_mask = 0;
178 new->lid_mask = 0xff;
179 }
180 }
181
182 /*
183 * All APICs have to be configured in the same mode by an OS.
184 * We take advatage of this while building logical id loockup
185 * table. After reset APICs are in software disabled mode, so if
186 * we find apic with different setting we assume this is the mode
187 * OS wants all apics to be in; build lookup table accordingly.
188 */
189 if (kvm_apic_sw_enabled(apic))
190 break;
191 }
192
193 kvm_for_each_vcpu(i, vcpu, kvm) {
194 struct kvm_lapic *apic = vcpu->arch.apic;
195 u16 cid, lid;
196 u32 ldr;
197
198 new->phys_map[kvm_apic_id(apic)] = apic;
199
200 ldr = kvm_apic_get_reg(apic, APIC_LDR);
201 cid = apic_cluster_id(new, ldr);
202 lid = apic_logical_id(new, ldr);
203
204 if (lid)
205 new->logical_map[cid][ffs(lid) - 1] = apic;
206 }
207out:
208 old = rcu_dereference_protected(kvm->arch.apic_map,
209 lockdep_is_held(&kvm->arch.apic_map_lock));
210 rcu_assign_pointer(kvm->arch.apic_map, new);
211 mutex_unlock(&kvm->arch.apic_map_lock);
212
213 if (old)
214 kfree_rcu(old, rcu);
215
216 kvm_vcpu_request_scan_ioapic(kvm);
217}
218
219static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
220{
221 bool enabled = val & APIC_SPIV_APIC_ENABLED;
222
223 apic_set_reg(apic, APIC_SPIV, val);
224
225 if (enabled != apic->sw_enabled) {
226 apic->sw_enabled = enabled;
227 if (enabled) {
228 static_key_slow_dec_deferred(&apic_sw_disabled);
229 recalculate_apic_map(apic->vcpu->kvm);
230 } else
231 static_key_slow_inc(&apic_sw_disabled.key);
232 }
233}
234
235static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
236{
237 apic_set_reg(apic, APIC_ID, id << 24);
238 recalculate_apic_map(apic->vcpu->kvm);
239}
240
241static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
242{
243 apic_set_reg(apic, APIC_LDR, id);
244 recalculate_apic_map(apic->vcpu->kvm);
245}
246
247static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
248{
249 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
250}
251
252static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
253{
254 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
255}
256
257static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
258{
259 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
260}
261
262static inline int apic_lvtt_period(struct kvm_lapic *apic)
263{
264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
265}
266
267static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
268{
269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
270}
271
272static inline int apic_lvt_nmi_mode(u32 lvt_val)
273{
274 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
275}
276
277void kvm_apic_set_version(struct kvm_vcpu *vcpu)
278{
279 struct kvm_lapic *apic = vcpu->arch.apic;
280 struct kvm_cpuid_entry2 *feat;
281 u32 v = APIC_VERSION;
282
283 if (!kvm_vcpu_has_lapic(vcpu))
284 return;
285
286 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
287 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
288 v |= APIC_LVR_DIRECTED_EOI;
289 apic_set_reg(apic, APIC_LVR, v);
290}
291
292static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
293 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
294 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
295 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
296 LINT_MASK, LINT_MASK, /* LVT0-1 */
297 LVT_MASK /* LVTERR */
298};
299
300static int find_highest_vector(void *bitmap)
301{
302 int vec;
303 u32 *reg;
304
305 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
306 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
307 reg = bitmap + REG_POS(vec);
308 if (*reg)
309 return fls(*reg) - 1 + vec;
310 }
311
312 return -1;
313}
314
315static u8 count_vectors(void *bitmap)
316{
317 int vec;
318 u32 *reg;
319 u8 count = 0;
320
321 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
322 reg = bitmap + REG_POS(vec);
323 count += hweight32(*reg);
324 }
325
326 return count;
327}
328
329void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
330{
331 u32 i, pir_val;
332 struct kvm_lapic *apic = vcpu->arch.apic;
333
334 for (i = 0; i <= 7; i++) {
335 pir_val = xchg(&pir[i], 0);
336 if (pir_val)
337 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
338 }
339}
340EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
341
342static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
343{
344 apic_set_vector(vec, apic->regs + APIC_IRR);
345 /*
346 * irr_pending must be true if any interrupt is pending; set it after
347 * APIC_IRR to avoid race with apic_clear_irr
348 */
349 apic->irr_pending = true;
350}
351
352static inline int apic_search_irr(struct kvm_lapic *apic)
353{
354 return find_highest_vector(apic->regs + APIC_IRR);
355}
356
357static inline int apic_find_highest_irr(struct kvm_lapic *apic)
358{
359 int result;
360
361 /*
362 * Note that irr_pending is just a hint. It will be always
363 * true with virtual interrupt delivery enabled.
364 */
365 if (!apic->irr_pending)
366 return -1;
367
368 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
369 result = apic_search_irr(apic);
370 ASSERT(result == -1 || result >= 16);
371
372 return result;
373}
374
375static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
376{
377 struct kvm_vcpu *vcpu;
378
379 vcpu = apic->vcpu;
380
381 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
382 /* try to update RVI */
383 apic_clear_vector(vec, apic->regs + APIC_IRR);
384 kvm_make_request(KVM_REQ_EVENT, vcpu);
385 } else {
386 apic->irr_pending = false;
387 apic_clear_vector(vec, apic->regs + APIC_IRR);
388 if (apic_search_irr(apic) != -1)
389 apic->irr_pending = true;
390 }
391}
392
393static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
394{
395 struct kvm_vcpu *vcpu;
396
397 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
398 return;
399
400 vcpu = apic->vcpu;
401
402 /*
403 * With APIC virtualization enabled, all caching is disabled
404 * because the processor can modify ISR under the hood. Instead
405 * just set SVI.
406 */
407 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
408 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
409 else {
410 ++apic->isr_count;
411 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
412 /*
413 * ISR (in service register) bit is set when injecting an interrupt.
414 * The highest vector is injected. Thus the latest bit set matches
415 * the highest bit in ISR.
416 */
417 apic->highest_isr_cache = vec;
418 }
419}
420
421static inline int apic_find_highest_isr(struct kvm_lapic *apic)
422{
423 int result;
424
425 /*
426 * Note that isr_count is always 1, and highest_isr_cache
427 * is always -1, with APIC virtualization enabled.
428 */
429 if (!apic->isr_count)
430 return -1;
431 if (likely(apic->highest_isr_cache != -1))
432 return apic->highest_isr_cache;
433
434 result = find_highest_vector(apic->regs + APIC_ISR);
435 ASSERT(result == -1 || result >= 16);
436
437 return result;
438}
439
440static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
441{
442 struct kvm_vcpu *vcpu;
443 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
444 return;
445
446 vcpu = apic->vcpu;
447
448 /*
449 * We do get here for APIC virtualization enabled if the guest
450 * uses the Hyper-V APIC enlightenment. In this case we may need
451 * to trigger a new interrupt delivery by writing the SVI field;
452 * on the other hand isr_count and highest_isr_cache are unused
453 * and must be left alone.
454 */
455 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
456 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
457 apic_find_highest_isr(apic));
458 else {
459 --apic->isr_count;
460 BUG_ON(apic->isr_count < 0);
461 apic->highest_isr_cache = -1;
462 }
463}
464
465int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
466{
467 int highest_irr;
468
469 /* This may race with setting of irr in __apic_accept_irq() and
470 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
471 * will cause vmexit immediately and the value will be recalculated
472 * on the next vmentry.
473 */
474 if (!kvm_vcpu_has_lapic(vcpu))
475 return 0;
476 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
477
478 return highest_irr;
479}
480
481static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
482 int vector, int level, int trig_mode,
483 unsigned long *dest_map);
484
485int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
486 unsigned long *dest_map)
487{
488 struct kvm_lapic *apic = vcpu->arch.apic;
489
490 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
491 irq->level, irq->trig_mode, dest_map);
492}
493
494static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
495{
496
497 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
498 sizeof(val));
499}
500
501static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
502{
503
504 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
505 sizeof(*val));
506}
507
508static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
509{
510 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
511}
512
513static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
514{
515 u8 val;
516 if (pv_eoi_get_user(vcpu, &val) < 0)
517 apic_debug("Can't read EOI MSR value: 0x%llx\n",
518 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
519 return val & 0x1;
520}
521
522static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
523{
524 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
525 apic_debug("Can't set EOI MSR value: 0x%llx\n",
526 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
527 return;
528 }
529 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
530}
531
532static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
533{
534 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
535 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
536 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
537 return;
538 }
539 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
540}
541
542void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
543{
544 struct kvm_lapic *apic = vcpu->arch.apic;
545 int i;
546
547 for (i = 0; i < 8; i++)
548 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
549}
550
551static void apic_update_ppr(struct kvm_lapic *apic)
552{
553 u32 tpr, isrv, ppr, old_ppr;
554 int isr;
555
556 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
557 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
558 isr = apic_find_highest_isr(apic);
559 isrv = (isr != -1) ? isr : 0;
560
561 if ((tpr & 0xf0) >= (isrv & 0xf0))
562 ppr = tpr & 0xff;
563 else
564 ppr = isrv & 0xf0;
565
566 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
567 apic, ppr, isr, isrv);
568
569 if (old_ppr != ppr) {
570 apic_set_reg(apic, APIC_PROCPRI, ppr);
571 if (ppr < old_ppr)
572 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
573 }
574}
575
576static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
577{
578 apic_set_reg(apic, APIC_TASKPRI, tpr);
579 apic_update_ppr(apic);
580}
581
582static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
583{
584 return dest == (apic_x2apic_mode(apic) ?
585 X2APIC_BROADCAST : APIC_BROADCAST);
586}
587
588int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
589{
590 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
591}
592
593int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
594{
595 int result = 0;
596 u32 logical_id;
597
598 if (kvm_apic_broadcast(apic, mda))
599 return 1;
600
601 if (apic_x2apic_mode(apic)) {
602 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
603 return logical_id & mda;
604 }
605
606 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
607
608 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
609 case APIC_DFR_FLAT:
610 if (logical_id & mda)
611 result = 1;
612 break;
613 case APIC_DFR_CLUSTER:
614 if (((logical_id >> 4) == (mda >> 0x4))
615 && (logical_id & mda & 0xf))
616 result = 1;
617 break;
618 default:
619 apic_debug("Bad DFR vcpu %d: %08x\n",
620 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
621 break;
622 }
623
624 return result;
625}
626
627int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
628 int short_hand, unsigned int dest, int dest_mode)
629{
630 int result = 0;
631 struct kvm_lapic *target = vcpu->arch.apic;
632
633 apic_debug("target %p, source %p, dest 0x%x, "
634 "dest_mode 0x%x, short_hand 0x%x\n",
635 target, source, dest, dest_mode, short_hand);
636
637 ASSERT(target);
638 switch (short_hand) {
639 case APIC_DEST_NOSHORT:
640 if (dest_mode == 0)
641 /* Physical mode. */
642 result = kvm_apic_match_physical_addr(target, dest);
643 else
644 /* Logical mode. */
645 result = kvm_apic_match_logical_addr(target, dest);
646 break;
647 case APIC_DEST_SELF:
648 result = (target == source);
649 break;
650 case APIC_DEST_ALLINC:
651 result = 1;
652 break;
653 case APIC_DEST_ALLBUT:
654 result = (target != source);
655 break;
656 default:
657 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
658 short_hand);
659 break;
660 }
661
662 return result;
663}
664
665bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
666 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
667{
668 struct kvm_apic_map *map;
669 unsigned long bitmap = 1;
670 struct kvm_lapic **dst;
671 int i;
672 bool ret = false;
673
674 *r = -1;
675
676 if (irq->shorthand == APIC_DEST_SELF) {
677 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
678 return true;
679 }
680
681 if (irq->shorthand)
682 return false;
683
684 rcu_read_lock();
685 map = rcu_dereference(kvm->arch.apic_map);
686
687 if (!map)
688 goto out;
689
690 if (irq->dest_id == map->broadcast)
691 goto out;
692
693 ret = true;
694
695 if (irq->dest_mode == 0) { /* physical mode */
696 dst = &map->phys_map[irq->dest_id & 0xff];
697 } else {
698 u32 mda = irq->dest_id << (32 - map->ldr_bits);
699
700 dst = map->logical_map[apic_cluster_id(map, mda)];
701
702 bitmap = apic_logical_id(map, mda);
703
704 if (irq->delivery_mode == APIC_DM_LOWEST) {
705 int l = -1;
706 for_each_set_bit(i, &bitmap, 16) {
707 if (!dst[i])
708 continue;
709 if (l < 0)
710 l = i;
711 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
712 l = i;
713 }
714
715 bitmap = (l >= 0) ? 1 << l : 0;
716 }
717 }
718
719 for_each_set_bit(i, &bitmap, 16) {
720 if (!dst[i])
721 continue;
722 if (*r < 0)
723 *r = 0;
724 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
725 }
726out:
727 rcu_read_unlock();
728 return ret;
729}
730
731/*
732 * Add a pending IRQ into lapic.
733 * Return 1 if successfully added and 0 if discarded.
734 */
735static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
736 int vector, int level, int trig_mode,
737 unsigned long *dest_map)
738{
739 int result = 0;
740 struct kvm_vcpu *vcpu = apic->vcpu;
741
742 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
743 trig_mode, vector);
744 switch (delivery_mode) {
745 case APIC_DM_LOWEST:
746 vcpu->arch.apic_arb_prio++;
747 case APIC_DM_FIXED:
748 /* FIXME add logic for vcpu on reset */
749 if (unlikely(!apic_enabled(apic)))
750 break;
751
752 result = 1;
753
754 if (dest_map)
755 __set_bit(vcpu->vcpu_id, dest_map);
756
757 if (kvm_x86_ops->deliver_posted_interrupt)
758 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
759 else {
760 apic_set_irr(vector, apic);
761
762 kvm_make_request(KVM_REQ_EVENT, vcpu);
763 kvm_vcpu_kick(vcpu);
764 }
765 break;
766
767 case APIC_DM_REMRD:
768 result = 1;
769 vcpu->arch.pv.pv_unhalted = 1;
770 kvm_make_request(KVM_REQ_EVENT, vcpu);
771 kvm_vcpu_kick(vcpu);
772 break;
773
774 case APIC_DM_SMI:
775 apic_debug("Ignoring guest SMI\n");
776 break;
777
778 case APIC_DM_NMI:
779 result = 1;
780 kvm_inject_nmi(vcpu);
781 kvm_vcpu_kick(vcpu);
782 break;
783
784 case APIC_DM_INIT:
785 if (!trig_mode || level) {
786 result = 1;
787 /* assumes that there are only KVM_APIC_INIT/SIPI */
788 apic->pending_events = (1UL << KVM_APIC_INIT);
789 /* make sure pending_events is visible before sending
790 * the request */
791 smp_wmb();
792 kvm_make_request(KVM_REQ_EVENT, vcpu);
793 kvm_vcpu_kick(vcpu);
794 } else {
795 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
796 vcpu->vcpu_id);
797 }
798 break;
799
800 case APIC_DM_STARTUP:
801 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
802 vcpu->vcpu_id, vector);
803 result = 1;
804 apic->sipi_vector = vector;
805 /* make sure sipi_vector is visible for the receiver */
806 smp_wmb();
807 set_bit(KVM_APIC_SIPI, &apic->pending_events);
808 kvm_make_request(KVM_REQ_EVENT, vcpu);
809 kvm_vcpu_kick(vcpu);
810 break;
811
812 case APIC_DM_EXTINT:
813 /*
814 * Should only be called by kvm_apic_local_deliver() with LVT0,
815 * before NMI watchdog was enabled. Already handled by
816 * kvm_apic_accept_pic_intr().
817 */
818 break;
819
820 default:
821 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
822 delivery_mode);
823 break;
824 }
825 return result;
826}
827
828int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
829{
830 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
831}
832
833static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
834{
835 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
836 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
837 int trigger_mode;
838 if (apic_test_vector(vector, apic->regs + APIC_TMR))
839 trigger_mode = IOAPIC_LEVEL_TRIG;
840 else
841 trigger_mode = IOAPIC_EDGE_TRIG;
842 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
843 }
844}
845
846static int apic_set_eoi(struct kvm_lapic *apic)
847{
848 int vector = apic_find_highest_isr(apic);
849
850 trace_kvm_eoi(apic, vector);
851
852 /*
853 * Not every write EOI will has corresponding ISR,
854 * one example is when Kernel check timer on setup_IO_APIC
855 */
856 if (vector == -1)
857 return vector;
858
859 apic_clear_isr(vector, apic);
860 apic_update_ppr(apic);
861
862 kvm_ioapic_send_eoi(apic, vector);
863 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
864 return vector;
865}
866
867/*
868 * this interface assumes a trap-like exit, which has already finished
869 * desired side effect including vISR and vPPR update.
870 */
871void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
872{
873 struct kvm_lapic *apic = vcpu->arch.apic;
874
875 trace_kvm_eoi(apic, vector);
876
877 kvm_ioapic_send_eoi(apic, vector);
878 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
879}
880EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
881
882static void apic_send_ipi(struct kvm_lapic *apic)
883{
884 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
885 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
886 struct kvm_lapic_irq irq;
887
888 irq.vector = icr_low & APIC_VECTOR_MASK;
889 irq.delivery_mode = icr_low & APIC_MODE_MASK;
890 irq.dest_mode = icr_low & APIC_DEST_MASK;
891 irq.level = icr_low & APIC_INT_ASSERT;
892 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
893 irq.shorthand = icr_low & APIC_SHORT_MASK;
894 if (apic_x2apic_mode(apic))
895 irq.dest_id = icr_high;
896 else
897 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
898
899 trace_kvm_apic_ipi(icr_low, irq.dest_id);
900
901 apic_debug("icr_high 0x%x, icr_low 0x%x, "
902 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
903 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
904 icr_high, icr_low, irq.shorthand, irq.dest_id,
905 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
906 irq.vector);
907
908 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
909}
910
911static u32 apic_get_tmcct(struct kvm_lapic *apic)
912{
913 ktime_t remaining;
914 s64 ns;
915 u32 tmcct;
916
917 ASSERT(apic != NULL);
918
919 /* if initial count is 0, current count should also be 0 */
920 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
921 apic->lapic_timer.period == 0)
922 return 0;
923
924 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
925 if (ktime_to_ns(remaining) < 0)
926 remaining = ktime_set(0, 0);
927
928 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
929 tmcct = div64_u64(ns,
930 (APIC_BUS_CYCLE_NS * apic->divide_count));
931
932 return tmcct;
933}
934
935static void __report_tpr_access(struct kvm_lapic *apic, bool write)
936{
937 struct kvm_vcpu *vcpu = apic->vcpu;
938 struct kvm_run *run = vcpu->run;
939
940 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
941 run->tpr_access.rip = kvm_rip_read(vcpu);
942 run->tpr_access.is_write = write;
943}
944
945static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
946{
947 if (apic->vcpu->arch.tpr_access_reporting)
948 __report_tpr_access(apic, write);
949}
950
951static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
952{
953 u32 val = 0;
954
955 if (offset >= LAPIC_MMIO_LENGTH)
956 return 0;
957
958 switch (offset) {
959 case APIC_ID:
960 if (apic_x2apic_mode(apic))
961 val = kvm_apic_id(apic);
962 else
963 val = kvm_apic_id(apic) << 24;
964 break;
965 case APIC_ARBPRI:
966 apic_debug("Access APIC ARBPRI register which is for P6\n");
967 break;
968
969 case APIC_TMCCT: /* Timer CCR */
970 if (apic_lvtt_tscdeadline(apic))
971 return 0;
972
973 val = apic_get_tmcct(apic);
974 break;
975 case APIC_PROCPRI:
976 apic_update_ppr(apic);
977 val = kvm_apic_get_reg(apic, offset);
978 break;
979 case APIC_TASKPRI:
980 report_tpr_access(apic, false);
981 /* fall thru */
982 default:
983 val = kvm_apic_get_reg(apic, offset);
984 break;
985 }
986
987 return val;
988}
989
990static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
991{
992 return container_of(dev, struct kvm_lapic, dev);
993}
994
995static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
996 void *data)
997{
998 unsigned char alignment = offset & 0xf;
999 u32 result;
1000 /* this bitmask has a bit cleared for each reserved register */
1001 static const u64 rmask = 0x43ff01ffffffe70cULL;
1002
1003 if ((alignment + len) > 4) {
1004 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1005 offset, len);
1006 return 1;
1007 }
1008
1009 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1010 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1011 offset);
1012 return 1;
1013 }
1014
1015 result = __apic_read(apic, offset & ~0xf);
1016
1017 trace_kvm_apic_read(offset, result);
1018
1019 switch (len) {
1020 case 1:
1021 case 2:
1022 case 4:
1023 memcpy(data, (char *)&result + alignment, len);
1024 break;
1025 default:
1026 printk(KERN_ERR "Local APIC read with len = %x, "
1027 "should be 1,2, or 4 instead\n", len);
1028 break;
1029 }
1030 return 0;
1031}
1032
1033static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1034{
1035 return kvm_apic_hw_enabled(apic) &&
1036 addr >= apic->base_address &&
1037 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1038}
1039
1040static int apic_mmio_read(struct kvm_io_device *this,
1041 gpa_t address, int len, void *data)
1042{
1043 struct kvm_lapic *apic = to_lapic(this);
1044 u32 offset = address - apic->base_address;
1045
1046 if (!apic_mmio_in_range(apic, address))
1047 return -EOPNOTSUPP;
1048
1049 apic_reg_read(apic, offset, len, data);
1050
1051 return 0;
1052}
1053
1054static void update_divide_count(struct kvm_lapic *apic)
1055{
1056 u32 tmp1, tmp2, tdcr;
1057
1058 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1059 tmp1 = tdcr & 0xf;
1060 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1061 apic->divide_count = 0x1 << (tmp2 & 0x7);
1062
1063 apic_debug("timer divide count is 0x%x\n",
1064 apic->divide_count);
1065}
1066
1067static void apic_timer_expired(struct kvm_lapic *apic)
1068{
1069 struct kvm_vcpu *vcpu = apic->vcpu;
1070 wait_queue_head_t *q = &vcpu->wq;
1071
1072 /*
1073 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1074 * vcpu_enter_guest.
1075 */
1076 if (atomic_read(&apic->lapic_timer.pending))
1077 return;
1078
1079 atomic_inc(&apic->lapic_timer.pending);
1080 /* FIXME: this code should not know anything about vcpus */
1081 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1082
1083 if (waitqueue_active(q))
1084 wake_up_interruptible(q);
1085}
1086
1087static void start_apic_timer(struct kvm_lapic *apic)
1088{
1089 ktime_t now;
1090 atomic_set(&apic->lapic_timer.pending, 0);
1091
1092 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1093 /* lapic timer in oneshot or periodic mode */
1094 now = apic->lapic_timer.timer.base->get_time();
1095 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1096 * APIC_BUS_CYCLE_NS * apic->divide_count;
1097
1098 if (!apic->lapic_timer.period)
1099 return;
1100 /*
1101 * Do not allow the guest to program periodic timers with small
1102 * interval, since the hrtimers are not throttled by the host
1103 * scheduler.
1104 */
1105 if (apic_lvtt_period(apic)) {
1106 s64 min_period = min_timer_period_us * 1000LL;
1107
1108 if (apic->lapic_timer.period < min_period) {
1109 pr_info_ratelimited(
1110 "kvm: vcpu %i: requested %lld ns "
1111 "lapic timer period limited to %lld ns\n",
1112 apic->vcpu->vcpu_id,
1113 apic->lapic_timer.period, min_period);
1114 apic->lapic_timer.period = min_period;
1115 }
1116 }
1117
1118 hrtimer_start(&apic->lapic_timer.timer,
1119 ktime_add_ns(now, apic->lapic_timer.period),
1120 HRTIMER_MODE_ABS);
1121
1122 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1123 PRIx64 ", "
1124 "timer initial count 0x%x, period %lldns, "
1125 "expire @ 0x%016" PRIx64 ".\n", __func__,
1126 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1127 kvm_apic_get_reg(apic, APIC_TMICT),
1128 apic->lapic_timer.period,
1129 ktime_to_ns(ktime_add_ns(now,
1130 apic->lapic_timer.period)));
1131 } else if (apic_lvtt_tscdeadline(apic)) {
1132 /* lapic timer in tsc deadline mode */
1133 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1134 u64 ns = 0;
1135 struct kvm_vcpu *vcpu = apic->vcpu;
1136 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1137 unsigned long flags;
1138
1139 if (unlikely(!tscdeadline || !this_tsc_khz))
1140 return;
1141
1142 local_irq_save(flags);
1143
1144 now = apic->lapic_timer.timer.base->get_time();
1145 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1146 if (likely(tscdeadline > guest_tsc)) {
1147 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1148 do_div(ns, this_tsc_khz);
1149 hrtimer_start(&apic->lapic_timer.timer,
1150 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1151 } else
1152 apic_timer_expired(apic);
1153
1154 local_irq_restore(flags);
1155 }
1156}
1157
1158static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1159{
1160 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1161
1162 if (apic_lvt_nmi_mode(lvt0_val)) {
1163 if (!nmi_wd_enabled) {
1164 apic_debug("Receive NMI setting on APIC_LVT0 "
1165 "for cpu %d\n", apic->vcpu->vcpu_id);
1166 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1167 }
1168 } else if (nmi_wd_enabled)
1169 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1170}
1171
1172static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1173{
1174 int ret = 0;
1175
1176 trace_kvm_apic_write(reg, val);
1177
1178 switch (reg) {
1179 case APIC_ID: /* Local APIC ID */
1180 if (!apic_x2apic_mode(apic))
1181 kvm_apic_set_id(apic, val >> 24);
1182 else
1183 ret = 1;
1184 break;
1185
1186 case APIC_TASKPRI:
1187 report_tpr_access(apic, true);
1188 apic_set_tpr(apic, val & 0xff);
1189 break;
1190
1191 case APIC_EOI:
1192 apic_set_eoi(apic);
1193 break;
1194
1195 case APIC_LDR:
1196 if (!apic_x2apic_mode(apic))
1197 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1198 else
1199 ret = 1;
1200 break;
1201
1202 case APIC_DFR:
1203 if (!apic_x2apic_mode(apic)) {
1204 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1205 recalculate_apic_map(apic->vcpu->kvm);
1206 } else
1207 ret = 1;
1208 break;
1209
1210 case APIC_SPIV: {
1211 u32 mask = 0x3ff;
1212 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1213 mask |= APIC_SPIV_DIRECTED_EOI;
1214 apic_set_spiv(apic, val & mask);
1215 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1216 int i;
1217 u32 lvt_val;
1218
1219 for (i = 0; i < APIC_LVT_NUM; i++) {
1220 lvt_val = kvm_apic_get_reg(apic,
1221 APIC_LVTT + 0x10 * i);
1222 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1223 lvt_val | APIC_LVT_MASKED);
1224 }
1225 atomic_set(&apic->lapic_timer.pending, 0);
1226
1227 }
1228 break;
1229 }
1230 case APIC_ICR:
1231 /* No delay here, so we always clear the pending bit */
1232 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1233 apic_send_ipi(apic);
1234 break;
1235
1236 case APIC_ICR2:
1237 if (!apic_x2apic_mode(apic))
1238 val &= 0xff000000;
1239 apic_set_reg(apic, APIC_ICR2, val);
1240 break;
1241
1242 case APIC_LVT0:
1243 apic_manage_nmi_watchdog(apic, val);
1244 case APIC_LVTTHMR:
1245 case APIC_LVTPC:
1246 case APIC_LVT1:
1247 case APIC_LVTERR:
1248 /* TODO: Check vector */
1249 if (!kvm_apic_sw_enabled(apic))
1250 val |= APIC_LVT_MASKED;
1251
1252 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1253 apic_set_reg(apic, reg, val);
1254
1255 break;
1256
1257 case APIC_LVTT: {
1258 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1259
1260 if (apic->lapic_timer.timer_mode != timer_mode) {
1261 apic->lapic_timer.timer_mode = timer_mode;
1262 hrtimer_cancel(&apic->lapic_timer.timer);
1263 }
1264
1265 if (!kvm_apic_sw_enabled(apic))
1266 val |= APIC_LVT_MASKED;
1267 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1268 apic_set_reg(apic, APIC_LVTT, val);
1269 break;
1270 }
1271
1272 case APIC_TMICT:
1273 if (apic_lvtt_tscdeadline(apic))
1274 break;
1275
1276 hrtimer_cancel(&apic->lapic_timer.timer);
1277 apic_set_reg(apic, APIC_TMICT, val);
1278 start_apic_timer(apic);
1279 break;
1280
1281 case APIC_TDCR:
1282 if (val & 4)
1283 apic_debug("KVM_WRITE:TDCR %x\n", val);
1284 apic_set_reg(apic, APIC_TDCR, val);
1285 update_divide_count(apic);
1286 break;
1287
1288 case APIC_ESR:
1289 if (apic_x2apic_mode(apic) && val != 0) {
1290 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1291 ret = 1;
1292 }
1293 break;
1294
1295 case APIC_SELF_IPI:
1296 if (apic_x2apic_mode(apic)) {
1297 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1298 } else
1299 ret = 1;
1300 break;
1301 default:
1302 ret = 1;
1303 break;
1304 }
1305 if (ret)
1306 apic_debug("Local APIC Write to read-only register %x\n", reg);
1307 return ret;
1308}
1309
1310static int apic_mmio_write(struct kvm_io_device *this,
1311 gpa_t address, int len, const void *data)
1312{
1313 struct kvm_lapic *apic = to_lapic(this);
1314 unsigned int offset = address - apic->base_address;
1315 u32 val;
1316
1317 if (!apic_mmio_in_range(apic, address))
1318 return -EOPNOTSUPP;
1319
1320 /*
1321 * APIC register must be aligned on 128-bits boundary.
1322 * 32/64/128 bits registers must be accessed thru 32 bits.
1323 * Refer SDM 8.4.1
1324 */
1325 if (len != 4 || (offset & 0xf)) {
1326 /* Don't shout loud, $infamous_os would cause only noise. */
1327 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1328 return 0;
1329 }
1330
1331 val = *(u32*)data;
1332
1333 /* too common printing */
1334 if (offset != APIC_EOI)
1335 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1336 "0x%x\n", __func__, offset, len, val);
1337
1338 apic_reg_write(apic, offset & 0xff0, val);
1339
1340 return 0;
1341}
1342
1343void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1344{
1345 if (kvm_vcpu_has_lapic(vcpu))
1346 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1347}
1348EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1349
1350/* emulate APIC access in a trap manner */
1351void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1352{
1353 u32 val = 0;
1354
1355 /* hw has done the conditional check and inst decode */
1356 offset &= 0xff0;
1357
1358 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1359
1360 /* TODO: optimize to just emulate side effect w/o one more write */
1361 apic_reg_write(vcpu->arch.apic, offset, val);
1362}
1363EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1364
1365void kvm_free_lapic(struct kvm_vcpu *vcpu)
1366{
1367 struct kvm_lapic *apic = vcpu->arch.apic;
1368
1369 if (!vcpu->arch.apic)
1370 return;
1371
1372 hrtimer_cancel(&apic->lapic_timer.timer);
1373
1374 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1375 static_key_slow_dec_deferred(&apic_hw_disabled);
1376
1377 if (!apic->sw_enabled)
1378 static_key_slow_dec_deferred(&apic_sw_disabled);
1379
1380 if (apic->regs)
1381 free_page((unsigned long)apic->regs);
1382
1383 kfree(apic);
1384}
1385
1386/*
1387 *----------------------------------------------------------------------
1388 * LAPIC interface
1389 *----------------------------------------------------------------------
1390 */
1391
1392u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1393{
1394 struct kvm_lapic *apic = vcpu->arch.apic;
1395
1396 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1397 apic_lvtt_period(apic))
1398 return 0;
1399
1400 return apic->lapic_timer.tscdeadline;
1401}
1402
1403void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1404{
1405 struct kvm_lapic *apic = vcpu->arch.apic;
1406
1407 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1408 apic_lvtt_period(apic))
1409 return;
1410
1411 hrtimer_cancel(&apic->lapic_timer.timer);
1412 apic->lapic_timer.tscdeadline = data;
1413 start_apic_timer(apic);
1414}
1415
1416void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1417{
1418 struct kvm_lapic *apic = vcpu->arch.apic;
1419
1420 if (!kvm_vcpu_has_lapic(vcpu))
1421 return;
1422
1423 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1424 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1425}
1426
1427u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1428{
1429 u64 tpr;
1430
1431 if (!kvm_vcpu_has_lapic(vcpu))
1432 return 0;
1433
1434 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1435
1436 return (tpr & 0xf0) >> 4;
1437}
1438
1439void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1440{
1441 u64 old_value = vcpu->arch.apic_base;
1442 struct kvm_lapic *apic = vcpu->arch.apic;
1443
1444 if (!apic) {
1445 value |= MSR_IA32_APICBASE_BSP;
1446 vcpu->arch.apic_base = value;
1447 return;
1448 }
1449
1450 if (!kvm_vcpu_is_bsp(apic->vcpu))
1451 value &= ~MSR_IA32_APICBASE_BSP;
1452 vcpu->arch.apic_base = value;
1453
1454 /* update jump label if enable bit changes */
1455 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1456 if (value & MSR_IA32_APICBASE_ENABLE)
1457 static_key_slow_dec_deferred(&apic_hw_disabled);
1458 else
1459 static_key_slow_inc(&apic_hw_disabled.key);
1460 recalculate_apic_map(vcpu->kvm);
1461 }
1462
1463 if ((old_value ^ value) & X2APIC_ENABLE) {
1464 if (value & X2APIC_ENABLE) {
1465 u32 id = kvm_apic_id(apic);
1466 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1467 kvm_apic_set_ldr(apic, ldr);
1468 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1469 } else
1470 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1471 }
1472
1473 apic->base_address = apic->vcpu->arch.apic_base &
1474 MSR_IA32_APICBASE_BASE;
1475
1476 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1477 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1478 pr_warn_once("APIC base relocation is unsupported by KVM");
1479
1480 /* with FSB delivery interrupt, we can restart APIC functionality */
1481 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1482 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1483
1484}
1485
1486void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1487{
1488 struct kvm_lapic *apic;
1489 int i;
1490
1491 apic_debug("%s\n", __func__);
1492
1493 ASSERT(vcpu);
1494 apic = vcpu->arch.apic;
1495 ASSERT(apic != NULL);
1496
1497 /* Stop the timer in case it's a reset to an active apic */
1498 hrtimer_cancel(&apic->lapic_timer.timer);
1499
1500 kvm_apic_set_id(apic, vcpu->vcpu_id);
1501 kvm_apic_set_version(apic->vcpu);
1502
1503 for (i = 0; i < APIC_LVT_NUM; i++)
1504 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1505 apic->lapic_timer.timer_mode = 0;
1506 apic_set_reg(apic, APIC_LVT0,
1507 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1508
1509 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1510 apic_set_spiv(apic, 0xff);
1511 apic_set_reg(apic, APIC_TASKPRI, 0);
1512 kvm_apic_set_ldr(apic, 0);
1513 apic_set_reg(apic, APIC_ESR, 0);
1514 apic_set_reg(apic, APIC_ICR, 0);
1515 apic_set_reg(apic, APIC_ICR2, 0);
1516 apic_set_reg(apic, APIC_TDCR, 0);
1517 apic_set_reg(apic, APIC_TMICT, 0);
1518 for (i = 0; i < 8; i++) {
1519 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1520 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1521 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1522 }
1523 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1524 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1525 apic->highest_isr_cache = -1;
1526 update_divide_count(apic);
1527 atomic_set(&apic->lapic_timer.pending, 0);
1528 if (kvm_vcpu_is_bsp(vcpu))
1529 kvm_lapic_set_base(vcpu,
1530 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1531 vcpu->arch.pv_eoi.msr_val = 0;
1532 apic_update_ppr(apic);
1533
1534 vcpu->arch.apic_arb_prio = 0;
1535 vcpu->arch.apic_attention = 0;
1536
1537 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1538 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1539 vcpu, kvm_apic_id(apic),
1540 vcpu->arch.apic_base, apic->base_address);
1541}
1542
1543/*
1544 *----------------------------------------------------------------------
1545 * timer interface
1546 *----------------------------------------------------------------------
1547 */
1548
1549static bool lapic_is_periodic(struct kvm_lapic *apic)
1550{
1551 return apic_lvtt_period(apic);
1552}
1553
1554int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1555{
1556 struct kvm_lapic *apic = vcpu->arch.apic;
1557
1558 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1559 apic_lvt_enabled(apic, APIC_LVTT))
1560 return atomic_read(&apic->lapic_timer.pending);
1561
1562 return 0;
1563}
1564
1565int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1566{
1567 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1568 int vector, mode, trig_mode;
1569
1570 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1571 vector = reg & APIC_VECTOR_MASK;
1572 mode = reg & APIC_MODE_MASK;
1573 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1574 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1575 NULL);
1576 }
1577 return 0;
1578}
1579
1580void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1581{
1582 struct kvm_lapic *apic = vcpu->arch.apic;
1583
1584 if (apic)
1585 kvm_apic_local_deliver(apic, APIC_LVT0);
1586}
1587
1588static const struct kvm_io_device_ops apic_mmio_ops = {
1589 .read = apic_mmio_read,
1590 .write = apic_mmio_write,
1591};
1592
1593static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1594{
1595 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1596 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1597
1598 apic_timer_expired(apic);
1599
1600 if (lapic_is_periodic(apic)) {
1601 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1602 return HRTIMER_RESTART;
1603 } else
1604 return HRTIMER_NORESTART;
1605}
1606
1607int kvm_create_lapic(struct kvm_vcpu *vcpu)
1608{
1609 struct kvm_lapic *apic;
1610
1611 ASSERT(vcpu != NULL);
1612 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1613
1614 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1615 if (!apic)
1616 goto nomem;
1617
1618 vcpu->arch.apic = apic;
1619
1620 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1621 if (!apic->regs) {
1622 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1623 vcpu->vcpu_id);
1624 goto nomem_free_apic;
1625 }
1626 apic->vcpu = vcpu;
1627
1628 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1629 HRTIMER_MODE_ABS);
1630 apic->lapic_timer.timer.function = apic_timer_fn;
1631
1632 /*
1633 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1634 * thinking that APIC satet has changed.
1635 */
1636 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1637 kvm_lapic_set_base(vcpu,
1638 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1639
1640 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1641 kvm_lapic_reset(vcpu);
1642 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1643
1644 return 0;
1645nomem_free_apic:
1646 kfree(apic);
1647nomem:
1648 return -ENOMEM;
1649}
1650
1651int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1652{
1653 struct kvm_lapic *apic = vcpu->arch.apic;
1654 int highest_irr;
1655
1656 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1657 return -1;
1658
1659 apic_update_ppr(apic);
1660 highest_irr = apic_find_highest_irr(apic);
1661 if ((highest_irr == -1) ||
1662 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1663 return -1;
1664 return highest_irr;
1665}
1666
1667int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1668{
1669 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1670 int r = 0;
1671
1672 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1673 r = 1;
1674 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1675 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1676 r = 1;
1677 return r;
1678}
1679
1680void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1681{
1682 struct kvm_lapic *apic = vcpu->arch.apic;
1683
1684 if (!kvm_vcpu_has_lapic(vcpu))
1685 return;
1686
1687 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1688 kvm_apic_local_deliver(apic, APIC_LVTT);
1689 if (apic_lvtt_tscdeadline(apic))
1690 apic->lapic_timer.tscdeadline = 0;
1691 atomic_set(&apic->lapic_timer.pending, 0);
1692 }
1693}
1694
1695int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1696{
1697 int vector = kvm_apic_has_interrupt(vcpu);
1698 struct kvm_lapic *apic = vcpu->arch.apic;
1699
1700 if (vector == -1)
1701 return -1;
1702
1703 /*
1704 * We get here even with APIC virtualization enabled, if doing
1705 * nested virtualization and L1 runs with the "acknowledge interrupt
1706 * on exit" mode. Then we cannot inject the interrupt via RVI,
1707 * because the process would deliver it through the IDT.
1708 */
1709
1710 apic_set_isr(vector, apic);
1711 apic_update_ppr(apic);
1712 apic_clear_irr(vector, apic);
1713 return vector;
1714}
1715
1716void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1717 struct kvm_lapic_state *s)
1718{
1719 struct kvm_lapic *apic = vcpu->arch.apic;
1720
1721 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1722 /* set SPIV separately to get count of SW disabled APICs right */
1723 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1724 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1725 /* call kvm_apic_set_id() to put apic into apic_map */
1726 kvm_apic_set_id(apic, kvm_apic_id(apic));
1727 kvm_apic_set_version(vcpu);
1728
1729 apic_update_ppr(apic);
1730 hrtimer_cancel(&apic->lapic_timer.timer);
1731 update_divide_count(apic);
1732 start_apic_timer(apic);
1733 apic->irr_pending = true;
1734 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1735 1 : count_vectors(apic->regs + APIC_ISR);
1736 apic->highest_isr_cache = -1;
1737 if (kvm_x86_ops->hwapic_irr_update)
1738 kvm_x86_ops->hwapic_irr_update(vcpu,
1739 apic_find_highest_irr(apic));
1740 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1741 kvm_make_request(KVM_REQ_EVENT, vcpu);
1742 kvm_rtc_eoi_tracking_restore_one(vcpu);
1743}
1744
1745void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1746{
1747 struct hrtimer *timer;
1748
1749 if (!kvm_vcpu_has_lapic(vcpu))
1750 return;
1751
1752 timer = &vcpu->arch.apic->lapic_timer.timer;
1753 if (hrtimer_cancel(timer))
1754 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1755}
1756
1757/*
1758 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1759 *
1760 * Detect whether guest triggered PV EOI since the
1761 * last entry. If yes, set EOI on guests's behalf.
1762 * Clear PV EOI in guest memory in any case.
1763 */
1764static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1765 struct kvm_lapic *apic)
1766{
1767 bool pending;
1768 int vector;
1769 /*
1770 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1771 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1772 *
1773 * KVM_APIC_PV_EOI_PENDING is unset:
1774 * -> host disabled PV EOI.
1775 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1776 * -> host enabled PV EOI, guest did not execute EOI yet.
1777 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1778 * -> host enabled PV EOI, guest executed EOI.
1779 */
1780 BUG_ON(!pv_eoi_enabled(vcpu));
1781 pending = pv_eoi_get_pending(vcpu);
1782 /*
1783 * Clear pending bit in any case: it will be set again on vmentry.
1784 * While this might not be ideal from performance point of view,
1785 * this makes sure pv eoi is only enabled when we know it's safe.
1786 */
1787 pv_eoi_clr_pending(vcpu);
1788 if (pending)
1789 return;
1790 vector = apic_set_eoi(apic);
1791 trace_kvm_pv_eoi(apic, vector);
1792}
1793
1794void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1795{
1796 u32 data;
1797
1798 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1799 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1800
1801 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1802 return;
1803
1804 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1805 sizeof(u32));
1806
1807 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1808}
1809
1810/*
1811 * apic_sync_pv_eoi_to_guest - called before vmentry
1812 *
1813 * Detect whether it's safe to enable PV EOI and
1814 * if yes do so.
1815 */
1816static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1817 struct kvm_lapic *apic)
1818{
1819 if (!pv_eoi_enabled(vcpu) ||
1820 /* IRR set or many bits in ISR: could be nested. */
1821 apic->irr_pending ||
1822 /* Cache not set: could be safe but we don't bother. */
1823 apic->highest_isr_cache == -1 ||
1824 /* Need EOI to update ioapic. */
1825 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1826 /*
1827 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1828 * so we need not do anything here.
1829 */
1830 return;
1831 }
1832
1833 pv_eoi_set_pending(apic->vcpu);
1834}
1835
1836void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1837{
1838 u32 data, tpr;
1839 int max_irr, max_isr;
1840 struct kvm_lapic *apic = vcpu->arch.apic;
1841
1842 apic_sync_pv_eoi_to_guest(vcpu, apic);
1843
1844 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1845 return;
1846
1847 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1848 max_irr = apic_find_highest_irr(apic);
1849 if (max_irr < 0)
1850 max_irr = 0;
1851 max_isr = apic_find_highest_isr(apic);
1852 if (max_isr < 0)
1853 max_isr = 0;
1854 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1855
1856 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1857 sizeof(u32));
1858}
1859
1860int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1861{
1862 if (vapic_addr) {
1863 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1864 &vcpu->arch.apic->vapic_cache,
1865 vapic_addr, sizeof(u32)))
1866 return -EINVAL;
1867 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1868 } else {
1869 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1870 }
1871
1872 vcpu->arch.apic->vapic_addr = vapic_addr;
1873 return 0;
1874}
1875
1876int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1877{
1878 struct kvm_lapic *apic = vcpu->arch.apic;
1879 u32 reg = (msr - APIC_BASE_MSR) << 4;
1880
1881 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1882 return 1;
1883
1884 if (reg == APIC_ICR2)
1885 return 1;
1886
1887 /* if this is ICR write vector before command */
1888 if (reg == APIC_ICR)
1889 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1890 return apic_reg_write(apic, reg, (u32)data);
1891}
1892
1893int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1894{
1895 struct kvm_lapic *apic = vcpu->arch.apic;
1896 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1897
1898 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1899 return 1;
1900
1901 if (reg == APIC_DFR || reg == APIC_ICR2) {
1902 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1903 reg);
1904 return 1;
1905 }
1906
1907 if (apic_reg_read(apic, reg, 4, &low))
1908 return 1;
1909 if (reg == APIC_ICR)
1910 apic_reg_read(apic, APIC_ICR2, 4, &high);
1911
1912 *data = (((u64)high) << 32) | low;
1913
1914 return 0;
1915}
1916
1917int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1918{
1919 struct kvm_lapic *apic = vcpu->arch.apic;
1920
1921 if (!kvm_vcpu_has_lapic(vcpu))
1922 return 1;
1923
1924 /* if this is ICR write vector before command */
1925 if (reg == APIC_ICR)
1926 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1927 return apic_reg_write(apic, reg, (u32)data);
1928}
1929
1930int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1931{
1932 struct kvm_lapic *apic = vcpu->arch.apic;
1933 u32 low, high = 0;
1934
1935 if (!kvm_vcpu_has_lapic(vcpu))
1936 return 1;
1937
1938 if (apic_reg_read(apic, reg, 4, &low))
1939 return 1;
1940 if (reg == APIC_ICR)
1941 apic_reg_read(apic, APIC_ICR2, 4, &high);
1942
1943 *data = (((u64)high) << 32) | low;
1944
1945 return 0;
1946}
1947
1948int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1949{
1950 u64 addr = data & ~KVM_MSR_ENABLED;
1951 if (!IS_ALIGNED(addr, 4))
1952 return 1;
1953
1954 vcpu->arch.pv_eoi.msr_val = data;
1955 if (!pv_eoi_enabled(vcpu))
1956 return 0;
1957 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1958 addr, sizeof(u8));
1959}
1960
1961void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1962{
1963 struct kvm_lapic *apic = vcpu->arch.apic;
1964 u8 sipi_vector;
1965 unsigned long pe;
1966
1967 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1968 return;
1969
1970 pe = xchg(&apic->pending_events, 0);
1971
1972 if (test_bit(KVM_APIC_INIT, &pe)) {
1973 kvm_lapic_reset(vcpu);
1974 kvm_vcpu_reset(vcpu);
1975 if (kvm_vcpu_is_bsp(apic->vcpu))
1976 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1977 else
1978 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1979 }
1980 if (test_bit(KVM_APIC_SIPI, &pe) &&
1981 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1982 /* evaluate pending_events before reading the vector */
1983 smp_rmb();
1984 sipi_vector = apic->sipi_vector;
1985 apic_debug("vcpu %d received sipi with vector # %x\n",
1986 vcpu->vcpu_id, sipi_vector);
1987 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1988 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1989 }
1990}
1991
1992void kvm_lapic_init(void)
1993{
1994 /* do not patch jump label more than once per second */
1995 jump_label_rate_limit(&apic_hw_disabled, HZ);
1996 jump_label_rate_limit(&apic_sw_disabled, HZ);
1997}
Linux kernel - Deliverables
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