[deliverable/linux.git] / arch / x86 / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 * Copyright 2010 Red Hat, Inc. and/or its affilates.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
	#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#define CMPXCHG cmpxchg
	#else
	#define CMPXCHG cmpxchg64
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
	#define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
	#define CMPXCHG cmpxchg
#else
	#error Invalid PTTYPE value
#endif

#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
	unsigned pt_access;
	unsigned pte_access;
	gfn_t gfn;
	u32 error_code;
};

static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
{
	return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
}

static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
			 gfn_t table_gfn, unsigned index,
			 pt_element_t orig_pte, pt_element_t new_pte)
{
	pt_element_t ret;
	pt_element_t *table;
	struct page *page;

	page = gfn_to_page(kvm, table_gfn);

	table = kmap_atomic(page, KM_USER0);
	ret = CMPXCHG(&table[index], orig_pte, new_pte);
	kunmap_atomic(table, KM_USER0);

	kvm_release_page_dirty(page);

	return (ret != orig_pte);
}

static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
{
	unsigned access;

	access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
#if PTTYPE == 64
	if (is_nx(vcpu))
		access &= ~(gpte >> PT64_NX_SHIFT);
#endif
	return access;
}

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index, pt_access, pte_access;
	gpa_t pte_gpa;
	int rsvd_fault = 0;

	trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
				     fetch_fault);
walk:
	walker->level = vcpu->arch.mmu.root_level;
	pte = vcpu->arch.cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
		trace_kvm_mmu_paging_element(pte, walker->level);
		if (!is_present_gpte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	pt_access = ACC_ALL;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = gpte_to_gfn(pte);
		pte_gpa = gfn_to_gpa(table_gfn);
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		walker->pte_gpa[walker->level - 1] = pte_gpa;

		if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
			goto not_present;

		trace_kvm_mmu_paging_element(pte, walker->level);

		if (!is_present_gpte(pte))
			goto not_present;

		rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
		if (rsvd_fault)
			goto access_error;

		if (write_fault && !is_writable_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			trace_kvm_mmu_set_accessed_bit(table_gfn, index,
						       sizeof(pte));
			if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
			    index, pte, pte|PT_ACCESSED_MASK))
				goto walk;
			mark_page_dirty(vcpu->kvm, table_gfn);
			pte |= PT_ACCESSED_MASK;
		}

		pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);

		walker->ptes[walker->level - 1] = pte;

		if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
		    ((walker->level == PT_DIRECTORY_LEVEL) &&
				is_large_pte(pte) &&
				(PTTYPE == 64 || is_pse(vcpu))) ||
		    ((walker->level == PT_PDPE_LEVEL) &&
				is_large_pte(pte) &&
				is_long_mode(vcpu))) {
			int lvl = walker->level;

			walker->gfn = gpte_to_gfn_lvl(pte, lvl);
			walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
					>> PAGE_SHIFT;

			if (PTTYPE == 32 &&
			    walker->level == PT_DIRECTORY_LEVEL &&
			    is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);

			break;
		}

		pt_access = pte_access;
		--walker->level;
	}

	if (write_fault && !is_dirty_gpte(pte)) {
		bool ret;

		trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
		ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
			    pte|PT_DIRTY_MASK);
		if (ret)
			goto walk;
		mark_page_dirty(vcpu->kvm, table_gfn);
		pte |= PT_DIRTY_MASK;
		walker->ptes[walker->level - 1] = pte;
	}

	walker->pt_access = pt_access;
	walker->pte_access = pte_access;
	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
		 __func__, (u64)pte, pte_access, pt_access);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	if (rsvd_fault)
		walker->error_code |= PFERR_RSVD_MASK;
	trace_kvm_mmu_walker_error(walker->error_code);
	return 0;
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte)
{
	pt_element_t gpte;
	unsigned pte_access;
	pfn_t pfn;
	u64 new_spte;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!is_present_gpte(gpte)) {
			if (page->unsync)
				new_spte = shadow_trap_nonpresent_pte;
			else
				new_spte = shadow_notrap_nonpresent_pte;
			__set_spte(spte, new_spte);
		}
		return;
	}
	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
		return;
	pfn = vcpu->arch.update_pte.pfn;
	if (is_error_pfn(pfn))
		return;
	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
		return;
	kvm_get_pfn(pfn);
	/*
	 * we call mmu_set_spte() with reset_host_protection = true beacuse that
	 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
	 */
	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
		     gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
		     gpte_to_gfn(gpte), pfn, true, true);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *gw,
			 int user_fault, int write_fault, int hlevel,
			 int *ptwrite, pfn_t pfn)
{
	unsigned access = gw->pt_access;
	struct kvm_mmu_page *shadow_page;
	u64 spte, *sptep = NULL;
	int direct;
	gfn_t table_gfn;
	int r;
	int level;
	pt_element_t curr_pte;
	struct kvm_shadow_walk_iterator iterator;

	if (!is_present_gpte(gw->ptes[gw->level - 1]))
		return NULL;

	for_each_shadow_entry(vcpu, addr, iterator) {
		level = iterator.level;
		sptep = iterator.sptep;
		if (iterator.level == hlevel) {
			mmu_set_spte(vcpu, sptep, access,
				     gw->pte_access & access,
				     user_fault, write_fault,
				     gw->ptes[gw->level-1] & PT_DIRTY_MASK,
				     ptwrite, level,
				     gw->gfn, pfn, false, true);
			break;
		}

		if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
			continue;

		if (is_large_pte(*sptep)) {
			rmap_remove(vcpu->kvm, sptep);
			__set_spte(sptep, shadow_trap_nonpresent_pte);
			kvm_flush_remote_tlbs(vcpu->kvm);
		}

		if (level <= gw->level) {
			int delta = level - gw->level + 1;
			direct = 1;
			if (!is_dirty_gpte(gw->ptes[level - delta]))
				access &= ~ACC_WRITE_MASK;
			/*
			 * It is a large guest pages backed by small host pages,
			 * So we set @direct(@shadow_page->role.direct)=1, and
			 * set @table_gfn(@shadow_page->gfn)=the base page frame
			 * for linear translations.
			 */
			table_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
			access &= gw->pte_access;
		} else {
			direct = 0;
			table_gfn = gw->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       direct, access, sptep);
		if (!direct) {
			r = kvm_read_guest_atomic(vcpu->kvm,
						  gw->pte_gpa[level - 2],
						  &curr_pte, sizeof(curr_pte));
			if (r || curr_pte != gw->ptes[level - 2]) {
				kvm_mmu_put_page(shadow_page, sptep);
				kvm_release_pfn_clean(pfn);
				sptep = NULL;
				break;
			}
		}

		spte = __pa(shadow_page->spt)
			| PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*sptep = spte;
	}

	return sptep;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *sptep;
	int write_pt = 0;
	int r;
	pfn_t pfn;
	int level = PT_PAGE_TABLE_LEVEL;
	unsigned long mmu_seq;

	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the guest pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __func__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	if (walker.level >= PT_DIRECTORY_LEVEL) {
		level = min(walker.level, mapping_level(vcpu, walker.gfn));
		walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
	}

	mmu_seq = vcpu->kvm->mmu_notifier_seq;
	smp_rmb();
	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);

	/* mmio */
	if (is_error_pfn(pfn))
		return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);

	spin_lock(&vcpu->kvm->mmu_lock);
	if (mmu_notifier_retry(vcpu, mmu_seq))
		goto out_unlock;
	kvm_mmu_free_some_pages(vcpu);
	sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
			     level, &write_pt, pfn);
	(void)sptep;
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
		 sptep, *sptep, write_pt);

	if (!write_pt)
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");
	spin_unlock(&vcpu->kvm->mmu_lock);

	return write_pt;

out_unlock:
	spin_unlock(&vcpu->kvm->mmu_lock);
	kvm_release_pfn_clean(pfn);
	return 0;
}

static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
{
	struct kvm_shadow_walk_iterator iterator;
	struct kvm_mmu_page *sp;
	gpa_t pte_gpa = -1;
	int level;
	u64 *sptep;
	int need_flush = 0;

	spin_lock(&vcpu->kvm->mmu_lock);

	for_each_shadow_entry(vcpu, gva, iterator) {
		level = iterator.level;
		sptep = iterator.sptep;

		sp = page_header(__pa(sptep));
		if (is_last_spte(*sptep, level)) {
			int offset, shift;

			if (!sp->unsync)
				break;

			shift = PAGE_SHIFT -
				  (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
			offset = sp->role.quadrant << shift;

			pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
			pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);

			if (is_shadow_present_pte(*sptep)) {
				rmap_remove(vcpu->kvm, sptep);
				if (is_large_pte(*sptep))
					--vcpu->kvm->stat.lpages;
				need_flush = 1;
			}
			__set_spte(sptep, shadow_trap_nonpresent_pte);
			break;
		}

		if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
			break;
	}

	if (need_flush)
		kvm_flush_remote_tlbs(vcpu->kvm);

	atomic_inc(&vcpu->kvm->arch.invlpg_counter);

	spin_unlock(&vcpu->kvm->mmu_lock);

	if (pte_gpa == -1)
		return;

	if (mmu_topup_memory_caches(vcpu))
		return;
	kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
			       u32 *error)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr,
			     !!(access & PFERR_WRITE_MASK),
			     !!(access & PFERR_USER_MASK),
			     !!(access & PFERR_FETCH_MASK));

	if (r) {
		gpa = gfn_to_gpa(walker.gfn);
		gpa |= vaddr & ~PAGE_MASK;
	} else if (error)
		*error = walker.error_code;

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i, j, offset, r;
	pt_element_t pt[256 / sizeof(pt_element_t)];
	gpa_t pte_gpa;

	if (sp->role.direct
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	pte_gpa = gfn_to_gpa(sp->gfn);
	if (PTTYPE == 32) {
		offset = sp->role.quadrant << PT64_LEVEL_BITS;
		pte_gpa += offset * sizeof(pt_element_t);
	}

	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
		r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
		pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
		for (j = 0; j < ARRAY_SIZE(pt); ++j)
			if (r || is_present_gpte(pt[j]))
				sp->spt[i+j] = shadow_trap_nonpresent_pte;
			else
				sp->spt[i+j] = shadow_notrap_nonpresent_pte;
	}
}

/*
 * Using the cached information from sp->gfns is safe because:
 * - The spte has a reference to the struct page, so the pfn for a given gfn
 *   can't change unless all sptes pointing to it are nuked first.
 * - Alias changes zap the entire shadow cache.
 */
static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
{
	int i, offset, nr_present;
	bool reset_host_protection;
	gpa_t first_pte_gpa;

	offset = nr_present = 0;

	/* direct kvm_mmu_page can not be unsync. */
	BUG_ON(sp->role.direct);

	if (PTTYPE == 32)
		offset = sp->role.quadrant << PT64_LEVEL_BITS;

	first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);

	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
		unsigned pte_access;
		pt_element_t gpte;
		gpa_t pte_gpa;
		gfn_t gfn;

		if (!is_shadow_present_pte(sp->spt[i]))
			continue;

		pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);

		if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
					  sizeof(pt_element_t)))
			return -EINVAL;

		gfn = gpte_to_gfn(gpte);
		if (unalias_gfn(vcpu->kvm, gfn) != sp->gfns[i] ||
		      !is_present_gpte(gpte) || !(gpte & PT_ACCESSED_MASK)) {
			u64 nonpresent;

			rmap_remove(vcpu->kvm, &sp->spt[i]);
			if (is_present_gpte(gpte))
				nonpresent = shadow_trap_nonpresent_pte;
			else
				nonpresent = shadow_notrap_nonpresent_pte;
			__set_spte(&sp->spt[i], nonpresent);
			continue;
		}

		nr_present++;
		pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
		if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
			pte_access &= ~ACC_WRITE_MASK;
			reset_host_protection = 0;
		} else {
			reset_host_protection = 1;
		}
		set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
			 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
			 spte_to_pfn(sp->spt[i]), true, false,
			 reset_host_protection);
	}

	return !nr_present;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_LVL_ADDR_MASK
#undef PT_LVL_OFFSET_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
#undef gpte_to_gfn
#undef gpte_to_gfn_lvl
#undef CMPXCHG
Commit	Line	Data
	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	* Copyright 2010 Red Hat, Inc. and/or its affilates.
	11	*
	12	* Authors:
	13	* Yaniv Kamay <yaniv@qumranet.com>
	14	* Avi Kivity <avi@qumranet.com>
	15	*
	16	* This work is licensed under the terms of the GNU GPL, version 2. See
	17	* the COPYING file in the top-level directory.
	18	*
	19	*/
	20
	21	/*
	22	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	23	* so the code in this file is compiled twice, once per pte size.
	24	*/
	25
	26	#if PTTYPE == 64
	27	#define pt_element_t u64
	28	#define guest_walker guest_walker64
	29	#define FNAME(name) paging##64_##name
	30	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	31	#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
	32	#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
	33	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	34	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	35	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	36	#ifdef CONFIG_X86_64
	37	#define PT_MAX_FULL_LEVELS 4
	38	#define CMPXCHG cmpxchg
	39	#else
	40	#define CMPXCHG cmpxchg64
	41	#define PT_MAX_FULL_LEVELS 2
	42	#endif
	43	#elif PTTYPE == 32
	44	#define pt_element_t u32
	45	#define guest_walker guest_walker32
	46	#define FNAME(name) paging##32_##name
	47	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	48	#define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
	49	#define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
	50	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	51	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	52	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	53	#define PT_MAX_FULL_LEVELS 2
	54	#define CMPXCHG cmpxchg
	55	#else
	56	#error Invalid PTTYPE value
	57	#endif
	58
	59	#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
	60	#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
	61
	62	/*
	63	* The guest_walker structure emulates the behavior of the hardware page
	64	* table walker.
	65	*/
	66	struct guest_walker {
	67	int level;
	68	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	69	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	70	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
	71	unsigned pt_access;
	72	unsigned pte_access;
	73	gfn_t gfn;
	74	u32 error_code;
	75	};
	76
	77	static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
	78	{
	79	return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
	80	}
	81
	82	static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
	83	gfn_t table_gfn, unsigned index,
	84	pt_element_t orig_pte, pt_element_t new_pte)
	85	{
	86	pt_element_t ret;
	87	pt_element_t *table;
	88	struct page *page;
	89
	90	page = gfn_to_page(kvm, table_gfn);
	91
	92	table = kmap_atomic(page, KM_USER0);
	93	ret = CMPXCHG(&table[index], orig_pte, new_pte);
	94	kunmap_atomic(table, KM_USER0);
	95
	96	kvm_release_page_dirty(page);
	97
	98	return (ret != orig_pte);
	99	}
	100
	101	static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
	102	{
	103	unsigned access;
	104
	105	access = (gpte & (PT_WRITABLE_MASK \| PT_USER_MASK)) \| ACC_EXEC_MASK;
	106	#if PTTYPE == 64
	107	if (is_nx(vcpu))
	108	access &= ~(gpte >> PT64_NX_SHIFT);
	109	#endif
	110	return access;
	111	}
	112
	113	/*
	114	* Fetch a guest pte for a guest virtual address
	115	*/
	116	static int FNAME(walk_addr)(struct guest_walker *walker,
	117	struct kvm_vcpu *vcpu, gva_t addr,
	118	int write_fault, int user_fault, int fetch_fault)
	119	{
	120	pt_element_t pte;
	121	gfn_t table_gfn;
	122	unsigned index, pt_access, pte_access;
	123	gpa_t pte_gpa;
	124	int rsvd_fault = 0;
	125
	126	trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
	127	fetch_fault);
	128	walk:
	129	walker->level = vcpu->arch.mmu.root_level;
	130	pte = vcpu->arch.cr3;
	131	#if PTTYPE == 64
	132	if (!is_long_mode(vcpu)) {
	133	pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
	134	trace_kvm_mmu_paging_element(pte, walker->level);
	135	if (!is_present_gpte(pte))
	136	goto not_present;
	137	--walker->level;
	138	}
	139	#endif
	140	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
	141	(vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
	142
	143	pt_access = ACC_ALL;
	144
	145	for (;;) {
	146	index = PT_INDEX(addr, walker->level);
	147
	148	table_gfn = gpte_to_gfn(pte);
	149	pte_gpa = gfn_to_gpa(table_gfn);
	150	pte_gpa += index * sizeof(pt_element_t);
	151	walker->table_gfn[walker->level - 1] = table_gfn;
	152	walker->pte_gpa[walker->level - 1] = pte_gpa;
	153
	154	if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
	155	goto not_present;
	156
	157	trace_kvm_mmu_paging_element(pte, walker->level);
	158
	159	if (!is_present_gpte(pte))
	160	goto not_present;
	161
	162	rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
	163	if (rsvd_fault)
	164	goto access_error;
	165
	166	if (write_fault && !is_writable_pte(pte))
	167	if (user_fault \|\| is_write_protection(vcpu))
	168	goto access_error;
	169
	170	if (user_fault && !(pte & PT_USER_MASK))
	171	goto access_error;
	172
	173	#if PTTYPE == 64
	174	if (fetch_fault && (pte & PT64_NX_MASK))
	175	goto access_error;
	176	#endif
	177
	178	if (!(pte & PT_ACCESSED_MASK)) {
	179	trace_kvm_mmu_set_accessed_bit(table_gfn, index,
	180	sizeof(pte));
	181	if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
	182	index, pte, pte\|PT_ACCESSED_MASK))
	183	goto walk;
	184	mark_page_dirty(vcpu->kvm, table_gfn);
	185	pte \|= PT_ACCESSED_MASK;
	186	}
	187
	188	pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
	189
	190	walker->ptes[walker->level - 1] = pte;
	191
	192	if ((walker->level == PT_PAGE_TABLE_LEVEL) \|\|
	193	((walker->level == PT_DIRECTORY_LEVEL) &&
	194	is_large_pte(pte) &&
	195	(PTTYPE == 64 \|\| is_pse(vcpu))) \|\|
	196	((walker->level == PT_PDPE_LEVEL) &&
	197	is_large_pte(pte) &&
	198	is_long_mode(vcpu))) {
	199	int lvl = walker->level;
	200
	201	walker->gfn = gpte_to_gfn_lvl(pte, lvl);
	202	walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
	203	>> PAGE_SHIFT;
	204
	205	if (PTTYPE == 32 &&
	206	walker->level == PT_DIRECTORY_LEVEL &&
	207	is_cpuid_PSE36())
	208	walker->gfn += pse36_gfn_delta(pte);
	209
	210	break;
	211	}
	212
	213	pt_access = pte_access;
	214	--walker->level;
	215	}
	216
	217	if (write_fault && !is_dirty_gpte(pte)) {
	218	bool ret;
	219
	220	trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
	221	ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
	222	pte\|PT_DIRTY_MASK);
	223	if (ret)
	224	goto walk;
	225	mark_page_dirty(vcpu->kvm, table_gfn);
	226	pte \|= PT_DIRTY_MASK;
	227	walker->ptes[walker->level - 1] = pte;
	228	}
	229
	230	walker->pt_access = pt_access;
	231	walker->pte_access = pte_access;
	232	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
	233	__func__, (u64)pte, pte_access, pt_access);
	234	return 1;
	235
	236	not_present:
	237	walker->error_code = 0;
	238	goto err;
	239
	240	access_error:
	241	walker->error_code = PFERR_PRESENT_MASK;
	242
	243	err:
	244	if (write_fault)
	245	walker->error_code \|= PFERR_WRITE_MASK;
	246	if (user_fault)
	247	walker->error_code \|= PFERR_USER_MASK;
	248	if (fetch_fault)
	249	walker->error_code \|= PFERR_FETCH_MASK;
	250	if (rsvd_fault)
	251	walker->error_code \|= PFERR_RSVD_MASK;
	252	trace_kvm_mmu_walker_error(walker->error_code);
	253	return 0;
	254	}
	255
	256	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
	257	u64 spte, const void pte)
	258	{
	259	pt_element_t gpte;
	260	unsigned pte_access;
	261	pfn_t pfn;
	262	u64 new_spte;
	263
	264	gpte = (const pt_element_t )pte;
	265	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
	266	if (!is_present_gpte(gpte)) {
	267	if (page->unsync)
	268	new_spte = shadow_trap_nonpresent_pte;
	269	else
	270	new_spte = shadow_notrap_nonpresent_pte;
	271	__set_spte(spte, new_spte);
	272	}
	273	return;
	274	}
	275	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
	276	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
	277	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
	278	return;
	279	pfn = vcpu->arch.update_pte.pfn;
	280	if (is_error_pfn(pfn))
	281	return;
	282	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
	283	return;
	284	kvm_get_pfn(pfn);
	285	/*
	286	* we call mmu_set_spte() with reset_host_protection = true beacuse that
	287	* vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
	288	*/
	289	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
	290	gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
	291	gpte_to_gfn(gpte), pfn, true, true);
	292	}
	293
	294	/*
	295	* Fetch a shadow pte for a specific level in the paging hierarchy.
	296	*/
	297	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
	298	struct guest_walker *gw,
	299	int user_fault, int write_fault, int hlevel,
	300	int *ptwrite, pfn_t pfn)
	301	{
	302	unsigned access = gw->pt_access;
	303	struct kvm_mmu_page *shadow_page;
	304	u64 spte, *sptep = NULL;
	305	int direct;
	306	gfn_t table_gfn;
	307	int r;
	308	int level;
	309	pt_element_t curr_pte;
	310	struct kvm_shadow_walk_iterator iterator;
	311
	312	if (!is_present_gpte(gw->ptes[gw->level - 1]))
	313	return NULL;
	314
	315	for_each_shadow_entry(vcpu, addr, iterator) {
	316	level = iterator.level;
	317	sptep = iterator.sptep;
	318	if (iterator.level == hlevel) {
	319	mmu_set_spte(vcpu, sptep, access,
	320	gw->pte_access & access,
	321	user_fault, write_fault,
	322	gw->ptes[gw->level-1] & PT_DIRTY_MASK,
	323	ptwrite, level,
	324	gw->gfn, pfn, false, true);
	325	break;
	326	}
	327
	328	if (is_shadow_present_pte(sptep) && !is_large_pte(sptep))
	329	continue;
	330
	331	if (is_large_pte(*sptep)) {
	332	rmap_remove(vcpu->kvm, sptep);
	333	__set_spte(sptep, shadow_trap_nonpresent_pte);
	334	kvm_flush_remote_tlbs(vcpu->kvm);
	335	}
	336
	337	if (level <= gw->level) {
	338	int delta = level - gw->level + 1;
	339	direct = 1;
	340	if (!is_dirty_gpte(gw->ptes[level - delta]))
	341	access &= ~ACC_WRITE_MASK;
	342	/*
	343	* It is a large guest pages backed by small host pages,
	344	* So we set @direct(@shadow_page->role.direct)=1, and
	345	* set @table_gfn(@shadow_page->gfn)=the base page frame
	346	* for linear translations.
	347	*/
	348	table_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
	349	access &= gw->pte_access;
	350	} else {
	351	direct = 0;
	352	table_gfn = gw->table_gfn[level - 2];
	353	}
	354	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
	355	direct, access, sptep);
	356	if (!direct) {
	357	r = kvm_read_guest_atomic(vcpu->kvm,
	358	gw->pte_gpa[level - 2],
	359	&curr_pte, sizeof(curr_pte));
	360	if (r \|\| curr_pte != gw->ptes[level - 2]) {
	361	kvm_mmu_put_page(shadow_page, sptep);
	362	kvm_release_pfn_clean(pfn);
	363	sptep = NULL;
	364	break;
	365	}
	366	}
	367
	368	spte = __pa(shadow_page->spt)
	369	\| PT_PRESENT_MASK \| PT_ACCESSED_MASK
	370	\| PT_WRITABLE_MASK \| PT_USER_MASK;
	371	*sptep = spte;
	372	}
	373
	374	return sptep;
	375	}
	376
	377	/*
	378	* Page fault handler. There are several causes for a page fault:
	379	* - there is no shadow pte for the guest pte
	380	* - write access through a shadow pte marked read only so that we can set
	381	* the dirty bit
	382	* - write access to a shadow pte marked read only so we can update the page
	383	* dirty bitmap, when userspace requests it
	384	* - mmio access; in this case we will never install a present shadow pte
	385	* - normal guest page fault due to the guest pte marked not present, not
	386	* writable, or not executable
	387	*
	388	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
	389	* a negative value on error.
	390	*/
	391	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	392	u32 error_code)
	393	{
	394	int write_fault = error_code & PFERR_WRITE_MASK;
	395	int user_fault = error_code & PFERR_USER_MASK;
	396	int fetch_fault = error_code & PFERR_FETCH_MASK;
	397	struct guest_walker walker;
	398	u64 *sptep;
	399	int write_pt = 0;
	400	int r;
	401	pfn_t pfn;
	402	int level = PT_PAGE_TABLE_LEVEL;
	403	unsigned long mmu_seq;
	404
	405	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
	406	kvm_mmu_audit(vcpu, "pre page fault");
	407
	408	r = mmu_topup_memory_caches(vcpu);
	409	if (r)
	410	return r;
	411
	412	/*
	413	* Look up the guest pte for the faulting address.
	414	*/
	415	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
	416	fetch_fault);
	417
	418	/*
	419	* The page is not mapped by the guest. Let the guest handle it.
	420	*/
	421	if (!r) {
	422	pgprintk("%s: guest page fault\n", __func__);
	423	inject_page_fault(vcpu, addr, walker.error_code);
	424	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
	425	return 0;
	426	}
	427
	428	if (walker.level >= PT_DIRECTORY_LEVEL) {
	429	level = min(walker.level, mapping_level(vcpu, walker.gfn));
	430	walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
	431	}
	432
	433	mmu_seq = vcpu->kvm->mmu_notifier_seq;
	434	smp_rmb();
	435	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
	436
	437	/* mmio */
	438	if (is_error_pfn(pfn))
	439	return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
	440
	441	spin_lock(&vcpu->kvm->mmu_lock);
	442	if (mmu_notifier_retry(vcpu, mmu_seq))
	443	goto out_unlock;
	444	kvm_mmu_free_some_pages(vcpu);
	445	sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	446	level, &write_pt, pfn);
	447	(void)sptep;
	448	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
	449	sptep, *sptep, write_pt);
	450
	451	if (!write_pt)
	452	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
	453
	454	++vcpu->stat.pf_fixed;
	455	kvm_mmu_audit(vcpu, "post page fault (fixed)");
	456	spin_unlock(&vcpu->kvm->mmu_lock);
	457
	458	return write_pt;
	459
	460	out_unlock:
	461	spin_unlock(&vcpu->kvm->mmu_lock);
	462	kvm_release_pfn_clean(pfn);
	463	return 0;
	464	}
	465
	466	static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
	467	{
	468	struct kvm_shadow_walk_iterator iterator;
	469	struct kvm_mmu_page *sp;
	470	gpa_t pte_gpa = -1;
	471	int level;
	472	u64 *sptep;
	473	int need_flush = 0;
	474
	475	spin_lock(&vcpu->kvm->mmu_lock);
	476
	477	for_each_shadow_entry(vcpu, gva, iterator) {
	478	level = iterator.level;
	479	sptep = iterator.sptep;
	480
	481	sp = page_header(__pa(sptep));
	482	if (is_last_spte(*sptep, level)) {
	483	int offset, shift;
	484
	485	if (!sp->unsync)
	486	break;
	487
	488	shift = PAGE_SHIFT -
	489	(PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
	490	offset = sp->role.quadrant << shift;
	491
	492	pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
	493	pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
	494
	495	if (is_shadow_present_pte(*sptep)) {
	496	rmap_remove(vcpu->kvm, sptep);
	497	if (is_large_pte(*sptep))
	498	--vcpu->kvm->stat.lpages;
	499	need_flush = 1;
	500	}
	501	__set_spte(sptep, shadow_trap_nonpresent_pte);
	502	break;
	503	}
	504
	505	if (!is_shadow_present_pte(*sptep) \|\| !sp->unsync_children)
	506	break;
	507	}
	508
	509	if (need_flush)
	510	kvm_flush_remote_tlbs(vcpu->kvm);
	511
	512	atomic_inc(&vcpu->kvm->arch.invlpg_counter);
	513
	514	spin_unlock(&vcpu->kvm->mmu_lock);
	515
	516	if (pte_gpa == -1)
	517	return;
	518
	519	if (mmu_topup_memory_caches(vcpu))
	520	return;
	521	kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
	522	}
	523
	524	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
	525	u32 *error)
	526	{
	527	struct guest_walker walker;
	528	gpa_t gpa = UNMAPPED_GVA;
	529	int r;
	530
	531	r = FNAME(walk_addr)(&walker, vcpu, vaddr,
	532	!!(access & PFERR_WRITE_MASK),
	533	!!(access & PFERR_USER_MASK),
	534	!!(access & PFERR_FETCH_MASK));
	535
	536	if (r) {
	537	gpa = gfn_to_gpa(walker.gfn);
	538	gpa \|= vaddr & ~PAGE_MASK;
	539	} else if (error)
	540	*error = walker.error_code;
	541
	542	return gpa;
	543	}
	544
	545	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	546	struct kvm_mmu_page *sp)
	547	{
	548	int i, j, offset, r;
	549	pt_element_t pt[256 / sizeof(pt_element_t)];
	550	gpa_t pte_gpa;
	551
	552	if (sp->role.direct
	553	\|\| (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
	554	nonpaging_prefetch_page(vcpu, sp);
	555	return;
	556	}
	557
	558	pte_gpa = gfn_to_gpa(sp->gfn);
	559	if (PTTYPE == 32) {
	560	offset = sp->role.quadrant << PT64_LEVEL_BITS;
	561	pte_gpa += offset * sizeof(pt_element_t);
	562	}
	563
	564	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
	565	r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
	566	pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
	567	for (j = 0; j < ARRAY_SIZE(pt); ++j)
	568	if (r \|\| is_present_gpte(pt[j]))
	569	sp->spt[i+j] = shadow_trap_nonpresent_pte;
	570	else
	571	sp->spt[i+j] = shadow_notrap_nonpresent_pte;
	572	}
	573	}
	574
	575	/*
	576	* Using the cached information from sp->gfns is safe because:
	577	* - The spte has a reference to the struct page, so the pfn for a given gfn
	578	* can't change unless all sptes pointing to it are nuked first.
	579	* - Alias changes zap the entire shadow cache.
	580	*/
	581	static int FNAME(sync_page)(struct kvm_vcpu vcpu, struct kvm_mmu_page sp)
	582	{
	583	int i, offset, nr_present;
	584	bool reset_host_protection;
	585	gpa_t first_pte_gpa;
	586
	587	offset = nr_present = 0;
	588
	589	/* direct kvm_mmu_page can not be unsync. */
	590	BUG_ON(sp->role.direct);
	591
	592	if (PTTYPE == 32)
	593	offset = sp->role.quadrant << PT64_LEVEL_BITS;
	594
	595	first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
	596
	597	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
	598	unsigned pte_access;
	599	pt_element_t gpte;
	600	gpa_t pte_gpa;
	601	gfn_t gfn;
	602
	603	if (!is_shadow_present_pte(sp->spt[i]))
	604	continue;
	605
	606	pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
	607
	608	if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
	609	sizeof(pt_element_t)))
	610	return -EINVAL;
	611
	612	gfn = gpte_to_gfn(gpte);
	613	if (unalias_gfn(vcpu->kvm, gfn) != sp->gfns[i] \|\|
	614	!is_present_gpte(gpte) \|\| !(gpte & PT_ACCESSED_MASK)) {
	615	u64 nonpresent;
	616
	617	rmap_remove(vcpu->kvm, &sp->spt[i]);
	618	if (is_present_gpte(gpte))
	619	nonpresent = shadow_trap_nonpresent_pte;
	620	else
	621	nonpresent = shadow_notrap_nonpresent_pte;
	622	__set_spte(&sp->spt[i], nonpresent);
	623	continue;
	624	}
	625
	626	nr_present++;
	627	pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
	628	if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
	629	pte_access &= ~ACC_WRITE_MASK;
	630	reset_host_protection = 0;
	631	} else {
	632	reset_host_protection = 1;
	633	}
	634	set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
	635	is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
	636	spte_to_pfn(sp->spt[i]), true, false,
	637	reset_host_protection);
	638	}
	639
	640	return !nr_present;
	641	}
	642
	643	#undef pt_element_t
	644	#undef guest_walker
	645	#undef FNAME
	646	#undef PT_BASE_ADDR_MASK
	647	#undef PT_INDEX
	648	#undef PT_LEVEL_MASK
	649	#undef PT_LVL_ADDR_MASK
	650	#undef PT_LVL_OFFSET_MASK
	651	#undef PT_LEVEL_BITS
	652	#undef PT_MAX_FULL_LEVELS
	653	#undef gpte_to_gfn
	654	#undef gpte_to_gfn_lvl
	655	#undef CMPXCHG