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KVM: nVMX: Fix setting of CR0 and CR4 in guest mode
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19#include "irq.h"
20#include "mmu.h"
21#include "cpuid.h"
22
23#include <linux/kvm_host.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/sched.h>
29#include <linux/moduleparam.h>
30#include <linux/mod_devicetable.h>
31#include <linux/ftrace_event.h>
32#include <linux/slab.h>
33#include <linux/tboot.h>
34#include "kvm_cache_regs.h"
35#include "x86.h"
36
37#include <asm/io.h>
38#include <asm/desc.h>
39#include <asm/vmx.h>
40#include <asm/virtext.h>
41#include <asm/mce.h>
42#include <asm/i387.h>
43#include <asm/xcr.h>
44#include <asm/perf_event.h>
45#include <asm/kexec.h>
46
47#include "trace.h"
48
49#define __ex(x) __kvm_handle_fault_on_reboot(x)
50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52
53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
62static bool __read_mostly enable_vpid = 1;
63module_param_named(vpid, enable_vpid, bool, 0444);
64
65static bool __read_mostly flexpriority_enabled = 1;
66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67
68static bool __read_mostly enable_ept = 1;
69module_param_named(ept, enable_ept, bool, S_IRUGO);
70
71static bool __read_mostly enable_unrestricted_guest = 1;
72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
78static bool __read_mostly emulate_invalid_guest_state = true;
79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80
81static bool __read_mostly vmm_exclusive = 1;
82module_param(vmm_exclusive, bool, S_IRUGO);
83
84static bool __read_mostly fasteoi = 1;
85module_param(fasteoi, bool, S_IRUGO);
86
87static bool __read_mostly enable_apicv_reg_vid;
88
89/*
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
93 */
94static bool __read_mostly nested = 0;
95module_param(nested, bool, S_IRUGO);
96
97#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
99#define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
101#define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
104
105#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
107
108#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
109
110/*
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
114 * According to test, this time is usually smaller than 128 cycles.
115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
120 */
121#define KVM_VMX_DEFAULT_PLE_GAP 128
122#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
124module_param(ple_gap, int, S_IRUGO);
125
126static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
127module_param(ple_window, int, S_IRUGO);
128
129extern const ulong vmx_return;
130
131#define NR_AUTOLOAD_MSRS 8
132#define VMCS02_POOL_SIZE 1
133
134struct vmcs {
135 u32 revision_id;
136 u32 abort;
137 char data[0];
138};
139
140/*
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
144 */
145struct loaded_vmcs {
146 struct vmcs *vmcs;
147 int cpu;
148 int launched;
149 struct list_head loaded_vmcss_on_cpu_link;
150};
151
152struct shared_msr_entry {
153 unsigned index;
154 u64 data;
155 u64 mask;
156};
157
158/*
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 */
171typedef u64 natural_width;
172struct __packed vmcs12 {
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
175 */
176 u32 revision_id;
177 u32 abort;
178
179 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding[7]; /* room for future expansion */
181
182 u64 io_bitmap_a;
183 u64 io_bitmap_b;
184 u64 msr_bitmap;
185 u64 vm_exit_msr_store_addr;
186 u64 vm_exit_msr_load_addr;
187 u64 vm_entry_msr_load_addr;
188 u64 tsc_offset;
189 u64 virtual_apic_page_addr;
190 u64 apic_access_addr;
191 u64 ept_pointer;
192 u64 guest_physical_address;
193 u64 vmcs_link_pointer;
194 u64 guest_ia32_debugctl;
195 u64 guest_ia32_pat;
196 u64 guest_ia32_efer;
197 u64 guest_ia32_perf_global_ctrl;
198 u64 guest_pdptr0;
199 u64 guest_pdptr1;
200 u64 guest_pdptr2;
201 u64 guest_pdptr3;
202 u64 host_ia32_pat;
203 u64 host_ia32_efer;
204 u64 host_ia32_perf_global_ctrl;
205 u64 padding64[8]; /* room for future expansion */
206 /*
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
211 */
212 natural_width cr0_guest_host_mask;
213 natural_width cr4_guest_host_mask;
214 natural_width cr0_read_shadow;
215 natural_width cr4_read_shadow;
216 natural_width cr3_target_value0;
217 natural_width cr3_target_value1;
218 natural_width cr3_target_value2;
219 natural_width cr3_target_value3;
220 natural_width exit_qualification;
221 natural_width guest_linear_address;
222 natural_width guest_cr0;
223 natural_width guest_cr3;
224 natural_width guest_cr4;
225 natural_width guest_es_base;
226 natural_width guest_cs_base;
227 natural_width guest_ss_base;
228 natural_width guest_ds_base;
229 natural_width guest_fs_base;
230 natural_width guest_gs_base;
231 natural_width guest_ldtr_base;
232 natural_width guest_tr_base;
233 natural_width guest_gdtr_base;
234 natural_width guest_idtr_base;
235 natural_width guest_dr7;
236 natural_width guest_rsp;
237 natural_width guest_rip;
238 natural_width guest_rflags;
239 natural_width guest_pending_dbg_exceptions;
240 natural_width guest_sysenter_esp;
241 natural_width guest_sysenter_eip;
242 natural_width host_cr0;
243 natural_width host_cr3;
244 natural_width host_cr4;
245 natural_width host_fs_base;
246 natural_width host_gs_base;
247 natural_width host_tr_base;
248 natural_width host_gdtr_base;
249 natural_width host_idtr_base;
250 natural_width host_ia32_sysenter_esp;
251 natural_width host_ia32_sysenter_eip;
252 natural_width host_rsp;
253 natural_width host_rip;
254 natural_width paddingl[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control;
256 u32 cpu_based_vm_exec_control;
257 u32 exception_bitmap;
258 u32 page_fault_error_code_mask;
259 u32 page_fault_error_code_match;
260 u32 cr3_target_count;
261 u32 vm_exit_controls;
262 u32 vm_exit_msr_store_count;
263 u32 vm_exit_msr_load_count;
264 u32 vm_entry_controls;
265 u32 vm_entry_msr_load_count;
266 u32 vm_entry_intr_info_field;
267 u32 vm_entry_exception_error_code;
268 u32 vm_entry_instruction_len;
269 u32 tpr_threshold;
270 u32 secondary_vm_exec_control;
271 u32 vm_instruction_error;
272 u32 vm_exit_reason;
273 u32 vm_exit_intr_info;
274 u32 vm_exit_intr_error_code;
275 u32 idt_vectoring_info_field;
276 u32 idt_vectoring_error_code;
277 u32 vm_exit_instruction_len;
278 u32 vmx_instruction_info;
279 u32 guest_es_limit;
280 u32 guest_cs_limit;
281 u32 guest_ss_limit;
282 u32 guest_ds_limit;
283 u32 guest_fs_limit;
284 u32 guest_gs_limit;
285 u32 guest_ldtr_limit;
286 u32 guest_tr_limit;
287 u32 guest_gdtr_limit;
288 u32 guest_idtr_limit;
289 u32 guest_es_ar_bytes;
290 u32 guest_cs_ar_bytes;
291 u32 guest_ss_ar_bytes;
292 u32 guest_ds_ar_bytes;
293 u32 guest_fs_ar_bytes;
294 u32 guest_gs_ar_bytes;
295 u32 guest_ldtr_ar_bytes;
296 u32 guest_tr_ar_bytes;
297 u32 guest_interruptibility_info;
298 u32 guest_activity_state;
299 u32 guest_sysenter_cs;
300 u32 host_ia32_sysenter_cs;
301 u32 padding32[8]; /* room for future expansion */
302 u16 virtual_processor_id;
303 u16 guest_es_selector;
304 u16 guest_cs_selector;
305 u16 guest_ss_selector;
306 u16 guest_ds_selector;
307 u16 guest_fs_selector;
308 u16 guest_gs_selector;
309 u16 guest_ldtr_selector;
310 u16 guest_tr_selector;
311 u16 host_es_selector;
312 u16 host_cs_selector;
313 u16 host_ss_selector;
314 u16 host_ds_selector;
315 u16 host_fs_selector;
316 u16 host_gs_selector;
317 u16 host_tr_selector;
318};
319
320/*
321 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
322 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
323 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
324 */
325#define VMCS12_REVISION 0x11e57ed0
326
327/*
328 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
329 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
330 * current implementation, 4K are reserved to avoid future complications.
331 */
332#define VMCS12_SIZE 0x1000
333
334/* Used to remember the last vmcs02 used for some recently used vmcs12s */
335struct vmcs02_list {
336 struct list_head list;
337 gpa_t vmptr;
338 struct loaded_vmcs vmcs02;
339};
340
341/*
342 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
343 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
344 */
345struct nested_vmx {
346 /* Has the level1 guest done vmxon? */
347 bool vmxon;
348
349 /* The guest-physical address of the current VMCS L1 keeps for L2 */
350 gpa_t current_vmptr;
351 /* The host-usable pointer to the above */
352 struct page *current_vmcs12_page;
353 struct vmcs12 *current_vmcs12;
354
355 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
356 struct list_head vmcs02_pool;
357 int vmcs02_num;
358 u64 vmcs01_tsc_offset;
359 /* L2 must run next, and mustn't decide to exit to L1. */
360 bool nested_run_pending;
361 /*
362 * Guest pages referred to in vmcs02 with host-physical pointers, so
363 * we must keep them pinned while L2 runs.
364 */
365 struct page *apic_access_page;
366};
367
368struct vcpu_vmx {
369 struct kvm_vcpu vcpu;
370 unsigned long host_rsp;
371 u8 fail;
372 u8 cpl;
373 bool nmi_known_unmasked;
374 u32 exit_intr_info;
375 u32 idt_vectoring_info;
376 ulong rflags;
377 struct shared_msr_entry *guest_msrs;
378 int nmsrs;
379 int save_nmsrs;
380#ifdef CONFIG_X86_64
381 u64 msr_host_kernel_gs_base;
382 u64 msr_guest_kernel_gs_base;
383#endif
384 /*
385 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
386 * non-nested (L1) guest, it always points to vmcs01. For a nested
387 * guest (L2), it points to a different VMCS.
388 */
389 struct loaded_vmcs vmcs01;
390 struct loaded_vmcs *loaded_vmcs;
391 bool __launched; /* temporary, used in vmx_vcpu_run */
392 struct msr_autoload {
393 unsigned nr;
394 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
395 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
396 } msr_autoload;
397 struct {
398 int loaded;
399 u16 fs_sel, gs_sel, ldt_sel;
400#ifdef CONFIG_X86_64
401 u16 ds_sel, es_sel;
402#endif
403 int gs_ldt_reload_needed;
404 int fs_reload_needed;
405 } host_state;
406 struct {
407 int vm86_active;
408 ulong save_rflags;
409 struct kvm_segment segs[8];
410 } rmode;
411 struct {
412 u32 bitmask; /* 4 bits per segment (1 bit per field) */
413 struct kvm_save_segment {
414 u16 selector;
415 unsigned long base;
416 u32 limit;
417 u32 ar;
418 } seg[8];
419 } segment_cache;
420 int vpid;
421 bool emulation_required;
422
423 /* Support for vnmi-less CPUs */
424 int soft_vnmi_blocked;
425 ktime_t entry_time;
426 s64 vnmi_blocked_time;
427 u32 exit_reason;
428
429 bool rdtscp_enabled;
430
431 /* Support for a guest hypervisor (nested VMX) */
432 struct nested_vmx nested;
433};
434
435enum segment_cache_field {
436 SEG_FIELD_SEL = 0,
437 SEG_FIELD_BASE = 1,
438 SEG_FIELD_LIMIT = 2,
439 SEG_FIELD_AR = 3,
440
441 SEG_FIELD_NR = 4
442};
443
444static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
445{
446 return container_of(vcpu, struct vcpu_vmx, vcpu);
447}
448
449#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
450#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
451#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
452 [number##_HIGH] = VMCS12_OFFSET(name)+4
453
454static const unsigned short vmcs_field_to_offset_table[] = {
455 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
456 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
457 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
458 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
459 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
460 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
461 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
462 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
463 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
464 FIELD(HOST_ES_SELECTOR, host_es_selector),
465 FIELD(HOST_CS_SELECTOR, host_cs_selector),
466 FIELD(HOST_SS_SELECTOR, host_ss_selector),
467 FIELD(HOST_DS_SELECTOR, host_ds_selector),
468 FIELD(HOST_FS_SELECTOR, host_fs_selector),
469 FIELD(HOST_GS_SELECTOR, host_gs_selector),
470 FIELD(HOST_TR_SELECTOR, host_tr_selector),
471 FIELD64(IO_BITMAP_A, io_bitmap_a),
472 FIELD64(IO_BITMAP_B, io_bitmap_b),
473 FIELD64(MSR_BITMAP, msr_bitmap),
474 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
475 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
476 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
477 FIELD64(TSC_OFFSET, tsc_offset),
478 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
479 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
480 FIELD64(EPT_POINTER, ept_pointer),
481 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
482 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
483 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
484 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
485 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
486 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
487 FIELD64(GUEST_PDPTR0, guest_pdptr0),
488 FIELD64(GUEST_PDPTR1, guest_pdptr1),
489 FIELD64(GUEST_PDPTR2, guest_pdptr2),
490 FIELD64(GUEST_PDPTR3, guest_pdptr3),
491 FIELD64(HOST_IA32_PAT, host_ia32_pat),
492 FIELD64(HOST_IA32_EFER, host_ia32_efer),
493 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
494 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
495 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
496 FIELD(EXCEPTION_BITMAP, exception_bitmap),
497 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
498 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
499 FIELD(CR3_TARGET_COUNT, cr3_target_count),
500 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
501 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
502 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
503 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
504 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
505 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
506 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
507 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
508 FIELD(TPR_THRESHOLD, tpr_threshold),
509 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
510 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
511 FIELD(VM_EXIT_REASON, vm_exit_reason),
512 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
513 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
514 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
515 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
516 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
517 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
518 FIELD(GUEST_ES_LIMIT, guest_es_limit),
519 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
520 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
521 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
522 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
523 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
524 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
525 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
526 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
527 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
528 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
529 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
530 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
531 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
532 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
533 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
534 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
535 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
536 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
537 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
538 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
539 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
540 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
541 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
542 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
543 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
544 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
545 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
546 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
547 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
548 FIELD(EXIT_QUALIFICATION, exit_qualification),
549 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
550 FIELD(GUEST_CR0, guest_cr0),
551 FIELD(GUEST_CR3, guest_cr3),
552 FIELD(GUEST_CR4, guest_cr4),
553 FIELD(GUEST_ES_BASE, guest_es_base),
554 FIELD(GUEST_CS_BASE, guest_cs_base),
555 FIELD(GUEST_SS_BASE, guest_ss_base),
556 FIELD(GUEST_DS_BASE, guest_ds_base),
557 FIELD(GUEST_FS_BASE, guest_fs_base),
558 FIELD(GUEST_GS_BASE, guest_gs_base),
559 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
560 FIELD(GUEST_TR_BASE, guest_tr_base),
561 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
562 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
563 FIELD(GUEST_DR7, guest_dr7),
564 FIELD(GUEST_RSP, guest_rsp),
565 FIELD(GUEST_RIP, guest_rip),
566 FIELD(GUEST_RFLAGS, guest_rflags),
567 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
568 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
569 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
570 FIELD(HOST_CR0, host_cr0),
571 FIELD(HOST_CR3, host_cr3),
572 FIELD(HOST_CR4, host_cr4),
573 FIELD(HOST_FS_BASE, host_fs_base),
574 FIELD(HOST_GS_BASE, host_gs_base),
575 FIELD(HOST_TR_BASE, host_tr_base),
576 FIELD(HOST_GDTR_BASE, host_gdtr_base),
577 FIELD(HOST_IDTR_BASE, host_idtr_base),
578 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
579 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
580 FIELD(HOST_RSP, host_rsp),
581 FIELD(HOST_RIP, host_rip),
582};
583static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
584
585static inline short vmcs_field_to_offset(unsigned long field)
586{
587 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
588 return -1;
589 return vmcs_field_to_offset_table[field];
590}
591
592static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
593{
594 return to_vmx(vcpu)->nested.current_vmcs12;
595}
596
597static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
598{
599 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
600 if (is_error_page(page))
601 return NULL;
602
603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
616static u64 construct_eptp(unsigned long root_hpa);
617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
621static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625static bool guest_state_valid(struct kvm_vcpu *vcpu);
626static u32 vmx_segment_access_rights(struct kvm_segment *var);
627
628static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
630/*
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 */
634static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
635static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
636
637static unsigned long *vmx_io_bitmap_a;
638static unsigned long *vmx_io_bitmap_b;
639static unsigned long *vmx_msr_bitmap_legacy;
640static unsigned long *vmx_msr_bitmap_longmode;
641static unsigned long *vmx_msr_bitmap_legacy_x2apic;
642static unsigned long *vmx_msr_bitmap_longmode_x2apic;
643
644static bool cpu_has_load_ia32_efer;
645static bool cpu_has_load_perf_global_ctrl;
646
647static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648static DEFINE_SPINLOCK(vmx_vpid_lock);
649
650static struct vmcs_config {
651 int size;
652 int order;
653 u32 revision_id;
654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
656 u32 cpu_based_2nd_exec_ctrl;
657 u32 vmexit_ctrl;
658 u32 vmentry_ctrl;
659} vmcs_config;
660
661static struct vmx_capability {
662 u32 ept;
663 u32 vpid;
664} vmx_capability;
665
666#define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
672 }
673
674static const struct kvm_vmx_segment_field {
675 unsigned selector;
676 unsigned base;
677 unsigned limit;
678 unsigned ar_bytes;
679} kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
688};
689
690static u64 host_efer;
691
692static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
693
694/*
695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
696 * away by decrementing the array size.
697 */
698static const u32 vmx_msr_index[] = {
699#ifdef CONFIG_X86_64
700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
701#endif
702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
703};
704#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
705
706static inline bool is_page_fault(u32 intr_info)
707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
711}
712
713static inline bool is_no_device(u32 intr_info)
714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
718}
719
720static inline bool is_invalid_opcode(u32 intr_info)
721{
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
725}
726
727static inline bool is_external_interrupt(u32 intr_info)
728{
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
731}
732
733static inline bool is_machine_check(u32 intr_info)
734{
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
738}
739
740static inline bool cpu_has_vmx_msr_bitmap(void)
741{
742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
743}
744
745static inline bool cpu_has_vmx_tpr_shadow(void)
746{
747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
748}
749
750static inline bool vm_need_tpr_shadow(struct kvm *kvm)
751{
752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
753}
754
755static inline bool cpu_has_secondary_exec_ctrls(void)
756{
757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
759}
760
761static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
762{
763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
765}
766
767static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
768{
769 return vmcs_config.cpu_based_2nd_exec_ctrl &
770 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
771}
772
773static inline bool cpu_has_vmx_apic_register_virt(void)
774{
775 return vmcs_config.cpu_based_2nd_exec_ctrl &
776 SECONDARY_EXEC_APIC_REGISTER_VIRT;
777}
778
779static inline bool cpu_has_vmx_virtual_intr_delivery(void)
780{
781 return vmcs_config.cpu_based_2nd_exec_ctrl &
782 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
783}
784
785static inline bool cpu_has_vmx_flexpriority(void)
786{
787 return cpu_has_vmx_tpr_shadow() &&
788 cpu_has_vmx_virtualize_apic_accesses();
789}
790
791static inline bool cpu_has_vmx_ept_execute_only(void)
792{
793 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
794}
795
796static inline bool cpu_has_vmx_eptp_uncacheable(void)
797{
798 return vmx_capability.ept & VMX_EPTP_UC_BIT;
799}
800
801static inline bool cpu_has_vmx_eptp_writeback(void)
802{
803 return vmx_capability.ept & VMX_EPTP_WB_BIT;
804}
805
806static inline bool cpu_has_vmx_ept_2m_page(void)
807{
808 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
809}
810
811static inline bool cpu_has_vmx_ept_1g_page(void)
812{
813 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
814}
815
816static inline bool cpu_has_vmx_ept_4levels(void)
817{
818 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
819}
820
821static inline bool cpu_has_vmx_ept_ad_bits(void)
822{
823 return vmx_capability.ept & VMX_EPT_AD_BIT;
824}
825
826static inline bool cpu_has_vmx_invept_context(void)
827{
828 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
829}
830
831static inline bool cpu_has_vmx_invept_global(void)
832{
833 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
834}
835
836static inline bool cpu_has_vmx_invvpid_single(void)
837{
838 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
839}
840
841static inline bool cpu_has_vmx_invvpid_global(void)
842{
843 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
844}
845
846static inline bool cpu_has_vmx_ept(void)
847{
848 return vmcs_config.cpu_based_2nd_exec_ctrl &
849 SECONDARY_EXEC_ENABLE_EPT;
850}
851
852static inline bool cpu_has_vmx_unrestricted_guest(void)
853{
854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_UNRESTRICTED_GUEST;
856}
857
858static inline bool cpu_has_vmx_ple(void)
859{
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
862}
863
864static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
865{
866 return flexpriority_enabled && irqchip_in_kernel(kvm);
867}
868
869static inline bool cpu_has_vmx_vpid(void)
870{
871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_ENABLE_VPID;
873}
874
875static inline bool cpu_has_vmx_rdtscp(void)
876{
877 return vmcs_config.cpu_based_2nd_exec_ctrl &
878 SECONDARY_EXEC_RDTSCP;
879}
880
881static inline bool cpu_has_vmx_invpcid(void)
882{
883 return vmcs_config.cpu_based_2nd_exec_ctrl &
884 SECONDARY_EXEC_ENABLE_INVPCID;
885}
886
887static inline bool cpu_has_virtual_nmis(void)
888{
889 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
890}
891
892static inline bool cpu_has_vmx_wbinvd_exit(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_WBINVD_EXITING;
896}
897
898static inline bool report_flexpriority(void)
899{
900 return flexpriority_enabled;
901}
902
903static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
904{
905 return vmcs12->cpu_based_vm_exec_control & bit;
906}
907
908static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
909{
910 return (vmcs12->cpu_based_vm_exec_control &
911 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
912 (vmcs12->secondary_vm_exec_control & bit);
913}
914
915static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
916 struct kvm_vcpu *vcpu)
917{
918 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
919}
920
921static inline bool is_exception(u32 intr_info)
922{
923 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
924 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
925}
926
927static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
928static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
929 struct vmcs12 *vmcs12,
930 u32 reason, unsigned long qualification);
931
932static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
933{
934 int i;
935
936 for (i = 0; i < vmx->nmsrs; ++i)
937 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
938 return i;
939 return -1;
940}
941
942static inline void __invvpid(int ext, u16 vpid, gva_t gva)
943{
944 struct {
945 u64 vpid : 16;
946 u64 rsvd : 48;
947 u64 gva;
948 } operand = { vpid, 0, gva };
949
950 asm volatile (__ex(ASM_VMX_INVVPID)
951 /* CF==1 or ZF==1 --> rc = -1 */
952 "; ja 1f ; ud2 ; 1:"
953 : : "a"(&operand), "c"(ext) : "cc", "memory");
954}
955
956static inline void __invept(int ext, u64 eptp, gpa_t gpa)
957{
958 struct {
959 u64 eptp, gpa;
960 } operand = {eptp, gpa};
961
962 asm volatile (__ex(ASM_VMX_INVEPT)
963 /* CF==1 or ZF==1 --> rc = -1 */
964 "; ja 1f ; ud2 ; 1:\n"
965 : : "a" (&operand), "c" (ext) : "cc", "memory");
966}
967
968static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
969{
970 int i;
971
972 i = __find_msr_index(vmx, msr);
973 if (i >= 0)
974 return &vmx->guest_msrs[i];
975 return NULL;
976}
977
978static void vmcs_clear(struct vmcs *vmcs)
979{
980 u64 phys_addr = __pa(vmcs);
981 u8 error;
982
983 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
985 : "cc", "memory");
986 if (error)
987 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
988 vmcs, phys_addr);
989}
990
991static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
992{
993 vmcs_clear(loaded_vmcs->vmcs);
994 loaded_vmcs->cpu = -1;
995 loaded_vmcs->launched = 0;
996}
997
998static void vmcs_load(struct vmcs *vmcs)
999{
1000 u64 phys_addr = __pa(vmcs);
1001 u8 error;
1002
1003 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1004 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1005 : "cc", "memory");
1006 if (error)
1007 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1008 vmcs, phys_addr);
1009}
1010
1011#ifdef CONFIG_KEXEC
1012/*
1013 * This bitmap is used to indicate whether the vmclear
1014 * operation is enabled on all cpus. All disabled by
1015 * default.
1016 */
1017static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1018
1019static inline void crash_enable_local_vmclear(int cpu)
1020{
1021 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1022}
1023
1024static inline void crash_disable_local_vmclear(int cpu)
1025{
1026 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1027}
1028
1029static inline int crash_local_vmclear_enabled(int cpu)
1030{
1031 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1032}
1033
1034static void crash_vmclear_local_loaded_vmcss(void)
1035{
1036 int cpu = raw_smp_processor_id();
1037 struct loaded_vmcs *v;
1038
1039 if (!crash_local_vmclear_enabled(cpu))
1040 return;
1041
1042 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1043 loaded_vmcss_on_cpu_link)
1044 vmcs_clear(v->vmcs);
1045}
1046#else
1047static inline void crash_enable_local_vmclear(int cpu) { }
1048static inline void crash_disable_local_vmclear(int cpu) { }
1049#endif /* CONFIG_KEXEC */
1050
1051static void __loaded_vmcs_clear(void *arg)
1052{
1053 struct loaded_vmcs *loaded_vmcs = arg;
1054 int cpu = raw_smp_processor_id();
1055
1056 if (loaded_vmcs->cpu != cpu)
1057 return; /* vcpu migration can race with cpu offline */
1058 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1059 per_cpu(current_vmcs, cpu) = NULL;
1060 crash_disable_local_vmclear(cpu);
1061 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1062
1063 /*
1064 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1065 * is before setting loaded_vmcs->vcpu to -1 which is done in
1066 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1067 * then adds the vmcs into percpu list before it is deleted.
1068 */
1069 smp_wmb();
1070
1071 loaded_vmcs_init(loaded_vmcs);
1072 crash_enable_local_vmclear(cpu);
1073}
1074
1075static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1076{
1077 int cpu = loaded_vmcs->cpu;
1078
1079 if (cpu != -1)
1080 smp_call_function_single(cpu,
1081 __loaded_vmcs_clear, loaded_vmcs, 1);
1082}
1083
1084static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1085{
1086 if (vmx->vpid == 0)
1087 return;
1088
1089 if (cpu_has_vmx_invvpid_single())
1090 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1091}
1092
1093static inline void vpid_sync_vcpu_global(void)
1094{
1095 if (cpu_has_vmx_invvpid_global())
1096 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1097}
1098
1099static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1100{
1101 if (cpu_has_vmx_invvpid_single())
1102 vpid_sync_vcpu_single(vmx);
1103 else
1104 vpid_sync_vcpu_global();
1105}
1106
1107static inline void ept_sync_global(void)
1108{
1109 if (cpu_has_vmx_invept_global())
1110 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1111}
1112
1113static inline void ept_sync_context(u64 eptp)
1114{
1115 if (enable_ept) {
1116 if (cpu_has_vmx_invept_context())
1117 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1118 else
1119 ept_sync_global();
1120 }
1121}
1122
1123static __always_inline unsigned long vmcs_readl(unsigned long field)
1124{
1125 unsigned long value;
1126
1127 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1128 : "=a"(value) : "d"(field) : "cc");
1129 return value;
1130}
1131
1132static __always_inline u16 vmcs_read16(unsigned long field)
1133{
1134 return vmcs_readl(field);
1135}
1136
1137static __always_inline u32 vmcs_read32(unsigned long field)
1138{
1139 return vmcs_readl(field);
1140}
1141
1142static __always_inline u64 vmcs_read64(unsigned long field)
1143{
1144#ifdef CONFIG_X86_64
1145 return vmcs_readl(field);
1146#else
1147 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1148#endif
1149}
1150
1151static noinline void vmwrite_error(unsigned long field, unsigned long value)
1152{
1153 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1154 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1155 dump_stack();
1156}
1157
1158static void vmcs_writel(unsigned long field, unsigned long value)
1159{
1160 u8 error;
1161
1162 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1163 : "=q"(error) : "a"(value), "d"(field) : "cc");
1164 if (unlikely(error))
1165 vmwrite_error(field, value);
1166}
1167
1168static void vmcs_write16(unsigned long field, u16 value)
1169{
1170 vmcs_writel(field, value);
1171}
1172
1173static void vmcs_write32(unsigned long field, u32 value)
1174{
1175 vmcs_writel(field, value);
1176}
1177
1178static void vmcs_write64(unsigned long field, u64 value)
1179{
1180 vmcs_writel(field, value);
1181#ifndef CONFIG_X86_64
1182 asm volatile ("");
1183 vmcs_writel(field+1, value >> 32);
1184#endif
1185}
1186
1187static void vmcs_clear_bits(unsigned long field, u32 mask)
1188{
1189 vmcs_writel(field, vmcs_readl(field) & ~mask);
1190}
1191
1192static void vmcs_set_bits(unsigned long field, u32 mask)
1193{
1194 vmcs_writel(field, vmcs_readl(field) | mask);
1195}
1196
1197static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1198{
1199 vmx->segment_cache.bitmask = 0;
1200}
1201
1202static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1203 unsigned field)
1204{
1205 bool ret;
1206 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1207
1208 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1209 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1210 vmx->segment_cache.bitmask = 0;
1211 }
1212 ret = vmx->segment_cache.bitmask & mask;
1213 vmx->segment_cache.bitmask |= mask;
1214 return ret;
1215}
1216
1217static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1218{
1219 u16 *p = &vmx->segment_cache.seg[seg].selector;
1220
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1222 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1223 return *p;
1224}
1225
1226static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1227{
1228 ulong *p = &vmx->segment_cache.seg[seg].base;
1229
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1231 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1232 return *p;
1233}
1234
1235static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1236{
1237 u32 *p = &vmx->segment_cache.seg[seg].limit;
1238
1239 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1240 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1241 return *p;
1242}
1243
1244static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1245{
1246 u32 *p = &vmx->segment_cache.seg[seg].ar;
1247
1248 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1249 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1250 return *p;
1251}
1252
1253static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1254{
1255 u32 eb;
1256
1257 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1258 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1259 if ((vcpu->guest_debug &
1260 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1261 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1262 eb |= 1u << BP_VECTOR;
1263 if (to_vmx(vcpu)->rmode.vm86_active)
1264 eb = ~0;
1265 if (enable_ept)
1266 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1267 if (vcpu->fpu_active)
1268 eb &= ~(1u << NM_VECTOR);
1269
1270 /* When we are running a nested L2 guest and L1 specified for it a
1271 * certain exception bitmap, we must trap the same exceptions and pass
1272 * them to L1. When running L2, we will only handle the exceptions
1273 * specified above if L1 did not want them.
1274 */
1275 if (is_guest_mode(vcpu))
1276 eb |= get_vmcs12(vcpu)->exception_bitmap;
1277
1278 vmcs_write32(EXCEPTION_BITMAP, eb);
1279}
1280
1281static void clear_atomic_switch_msr_special(unsigned long entry,
1282 unsigned long exit)
1283{
1284 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1285 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1286}
1287
1288static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1289{
1290 unsigned i;
1291 struct msr_autoload *m = &vmx->msr_autoload;
1292
1293 switch (msr) {
1294 case MSR_EFER:
1295 if (cpu_has_load_ia32_efer) {
1296 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER);
1298 return;
1299 }
1300 break;
1301 case MSR_CORE_PERF_GLOBAL_CTRL:
1302 if (cpu_has_load_perf_global_ctrl) {
1303 clear_atomic_switch_msr_special(
1304 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1305 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1306 return;
1307 }
1308 break;
1309 }
1310
1311 for (i = 0; i < m->nr; ++i)
1312 if (m->guest[i].index == msr)
1313 break;
1314
1315 if (i == m->nr)
1316 return;
1317 --m->nr;
1318 m->guest[i] = m->guest[m->nr];
1319 m->host[i] = m->host[m->nr];
1320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1321 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1322}
1323
1324static void add_atomic_switch_msr_special(unsigned long entry,
1325 unsigned long exit, unsigned long guest_val_vmcs,
1326 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1327{
1328 vmcs_write64(guest_val_vmcs, guest_val);
1329 vmcs_write64(host_val_vmcs, host_val);
1330 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1331 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1332}
1333
1334static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1335 u64 guest_val, u64 host_val)
1336{
1337 unsigned i;
1338 struct msr_autoload *m = &vmx->msr_autoload;
1339
1340 switch (msr) {
1341 case MSR_EFER:
1342 if (cpu_has_load_ia32_efer) {
1343 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1344 VM_EXIT_LOAD_IA32_EFER,
1345 GUEST_IA32_EFER,
1346 HOST_IA32_EFER,
1347 guest_val, host_val);
1348 return;
1349 }
1350 break;
1351 case MSR_CORE_PERF_GLOBAL_CTRL:
1352 if (cpu_has_load_perf_global_ctrl) {
1353 add_atomic_switch_msr_special(
1354 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1355 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1356 GUEST_IA32_PERF_GLOBAL_CTRL,
1357 HOST_IA32_PERF_GLOBAL_CTRL,
1358 guest_val, host_val);
1359 return;
1360 }
1361 break;
1362 }
1363
1364 for (i = 0; i < m->nr; ++i)
1365 if (m->guest[i].index == msr)
1366 break;
1367
1368 if (i == NR_AUTOLOAD_MSRS) {
1369 printk_once(KERN_WARNING"Not enough mst switch entries. "
1370 "Can't add msr %x\n", msr);
1371 return;
1372 } else if (i == m->nr) {
1373 ++m->nr;
1374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1376 }
1377
1378 m->guest[i].index = msr;
1379 m->guest[i].value = guest_val;
1380 m->host[i].index = msr;
1381 m->host[i].value = host_val;
1382}
1383
1384static void reload_tss(void)
1385{
1386 /*
1387 * VT restores TR but not its size. Useless.
1388 */
1389 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1390 struct desc_struct *descs;
1391
1392 descs = (void *)gdt->address;
1393 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1394 load_TR_desc();
1395}
1396
1397static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1398{
1399 u64 guest_efer;
1400 u64 ignore_bits;
1401
1402 guest_efer = vmx->vcpu.arch.efer;
1403
1404 /*
1405 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1406 * outside long mode
1407 */
1408 ignore_bits = EFER_NX | EFER_SCE;
1409#ifdef CONFIG_X86_64
1410 ignore_bits |= EFER_LMA | EFER_LME;
1411 /* SCE is meaningful only in long mode on Intel */
1412 if (guest_efer & EFER_LMA)
1413 ignore_bits &= ~(u64)EFER_SCE;
1414#endif
1415 guest_efer &= ~ignore_bits;
1416 guest_efer |= host_efer & ignore_bits;
1417 vmx->guest_msrs[efer_offset].data = guest_efer;
1418 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1419
1420 clear_atomic_switch_msr(vmx, MSR_EFER);
1421 /* On ept, can't emulate nx, and must switch nx atomically */
1422 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1423 guest_efer = vmx->vcpu.arch.efer;
1424 if (!(guest_efer & EFER_LMA))
1425 guest_efer &= ~EFER_LME;
1426 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1427 return false;
1428 }
1429
1430 return true;
1431}
1432
1433static unsigned long segment_base(u16 selector)
1434{
1435 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1436 struct desc_struct *d;
1437 unsigned long table_base;
1438 unsigned long v;
1439
1440 if (!(selector & ~3))
1441 return 0;
1442
1443 table_base = gdt->address;
1444
1445 if (selector & 4) { /* from ldt */
1446 u16 ldt_selector = kvm_read_ldt();
1447
1448 if (!(ldt_selector & ~3))
1449 return 0;
1450
1451 table_base = segment_base(ldt_selector);
1452 }
1453 d = (struct desc_struct *)(table_base + (selector & ~7));
1454 v = get_desc_base(d);
1455#ifdef CONFIG_X86_64
1456 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1457 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1458#endif
1459 return v;
1460}
1461
1462static inline unsigned long kvm_read_tr_base(void)
1463{
1464 u16 tr;
1465 asm("str %0" : "=g"(tr));
1466 return segment_base(tr);
1467}
1468
1469static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1470{
1471 struct vcpu_vmx *vmx = to_vmx(vcpu);
1472 int i;
1473
1474 if (vmx->host_state.loaded)
1475 return;
1476
1477 vmx->host_state.loaded = 1;
1478 /*
1479 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1480 * allow segment selectors with cpl > 0 or ti == 1.
1481 */
1482 vmx->host_state.ldt_sel = kvm_read_ldt();
1483 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1484 savesegment(fs, vmx->host_state.fs_sel);
1485 if (!(vmx->host_state.fs_sel & 7)) {
1486 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1487 vmx->host_state.fs_reload_needed = 0;
1488 } else {
1489 vmcs_write16(HOST_FS_SELECTOR, 0);
1490 vmx->host_state.fs_reload_needed = 1;
1491 }
1492 savesegment(gs, vmx->host_state.gs_sel);
1493 if (!(vmx->host_state.gs_sel & 7))
1494 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1495 else {
1496 vmcs_write16(HOST_GS_SELECTOR, 0);
1497 vmx->host_state.gs_ldt_reload_needed = 1;
1498 }
1499
1500#ifdef CONFIG_X86_64
1501 savesegment(ds, vmx->host_state.ds_sel);
1502 savesegment(es, vmx->host_state.es_sel);
1503#endif
1504
1505#ifdef CONFIG_X86_64
1506 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1507 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1508#else
1509 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1510 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1511#endif
1512
1513#ifdef CONFIG_X86_64
1514 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1515 if (is_long_mode(&vmx->vcpu))
1516 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1517#endif
1518 for (i = 0; i < vmx->save_nmsrs; ++i)
1519 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1520 vmx->guest_msrs[i].data,
1521 vmx->guest_msrs[i].mask);
1522}
1523
1524static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1525{
1526 if (!vmx->host_state.loaded)
1527 return;
1528
1529 ++vmx->vcpu.stat.host_state_reload;
1530 vmx->host_state.loaded = 0;
1531#ifdef CONFIG_X86_64
1532 if (is_long_mode(&vmx->vcpu))
1533 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1534#endif
1535 if (vmx->host_state.gs_ldt_reload_needed) {
1536 kvm_load_ldt(vmx->host_state.ldt_sel);
1537#ifdef CONFIG_X86_64
1538 load_gs_index(vmx->host_state.gs_sel);
1539#else
1540 loadsegment(gs, vmx->host_state.gs_sel);
1541#endif
1542 }
1543 if (vmx->host_state.fs_reload_needed)
1544 loadsegment(fs, vmx->host_state.fs_sel);
1545#ifdef CONFIG_X86_64
1546 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1547 loadsegment(ds, vmx->host_state.ds_sel);
1548 loadsegment(es, vmx->host_state.es_sel);
1549 }
1550#endif
1551 reload_tss();
1552#ifdef CONFIG_X86_64
1553 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1554#endif
1555 /*
1556 * If the FPU is not active (through the host task or
1557 * the guest vcpu), then restore the cr0.TS bit.
1558 */
1559 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1560 stts();
1561 load_gdt(&__get_cpu_var(host_gdt));
1562}
1563
1564static void vmx_load_host_state(struct vcpu_vmx *vmx)
1565{
1566 preempt_disable();
1567 __vmx_load_host_state(vmx);
1568 preempt_enable();
1569}
1570
1571/*
1572 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1573 * vcpu mutex is already taken.
1574 */
1575static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1576{
1577 struct vcpu_vmx *vmx = to_vmx(vcpu);
1578 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1579
1580 if (!vmm_exclusive)
1581 kvm_cpu_vmxon(phys_addr);
1582 else if (vmx->loaded_vmcs->cpu != cpu)
1583 loaded_vmcs_clear(vmx->loaded_vmcs);
1584
1585 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1586 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1587 vmcs_load(vmx->loaded_vmcs->vmcs);
1588 }
1589
1590 if (vmx->loaded_vmcs->cpu != cpu) {
1591 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1592 unsigned long sysenter_esp;
1593
1594 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1595 local_irq_disable();
1596 crash_disable_local_vmclear(cpu);
1597
1598 /*
1599 * Read loaded_vmcs->cpu should be before fetching
1600 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1601 * See the comments in __loaded_vmcs_clear().
1602 */
1603 smp_rmb();
1604
1605 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1606 &per_cpu(loaded_vmcss_on_cpu, cpu));
1607 crash_enable_local_vmclear(cpu);
1608 local_irq_enable();
1609
1610 /*
1611 * Linux uses per-cpu TSS and GDT, so set these when switching
1612 * processors.
1613 */
1614 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1615 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1616
1617 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1618 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1619 vmx->loaded_vmcs->cpu = cpu;
1620 }
1621}
1622
1623static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1624{
1625 __vmx_load_host_state(to_vmx(vcpu));
1626 if (!vmm_exclusive) {
1627 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1628 vcpu->cpu = -1;
1629 kvm_cpu_vmxoff();
1630 }
1631}
1632
1633static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1634{
1635 ulong cr0;
1636
1637 if (vcpu->fpu_active)
1638 return;
1639 vcpu->fpu_active = 1;
1640 cr0 = vmcs_readl(GUEST_CR0);
1641 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1642 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1643 vmcs_writel(GUEST_CR0, cr0);
1644 update_exception_bitmap(vcpu);
1645 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1646 if (is_guest_mode(vcpu))
1647 vcpu->arch.cr0_guest_owned_bits &=
1648 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1649 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1650}
1651
1652static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1653
1654/*
1655 * Return the cr0 value that a nested guest would read. This is a combination
1656 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1657 * its hypervisor (cr0_read_shadow).
1658 */
1659static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1660{
1661 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1662 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1663}
1664static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1665{
1666 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1667 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1668}
1669
1670static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1671{
1672 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1673 * set this *before* calling this function.
1674 */
1675 vmx_decache_cr0_guest_bits(vcpu);
1676 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1677 update_exception_bitmap(vcpu);
1678 vcpu->arch.cr0_guest_owned_bits = 0;
1679 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1680 if (is_guest_mode(vcpu)) {
1681 /*
1682 * L1's specified read shadow might not contain the TS bit,
1683 * so now that we turned on shadowing of this bit, we need to
1684 * set this bit of the shadow. Like in nested_vmx_run we need
1685 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1686 * up-to-date here because we just decached cr0.TS (and we'll
1687 * only update vmcs12->guest_cr0 on nested exit).
1688 */
1689 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1690 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1691 (vcpu->arch.cr0 & X86_CR0_TS);
1692 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1693 } else
1694 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1695}
1696
1697static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1698{
1699 unsigned long rflags, save_rflags;
1700
1701 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1702 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1703 rflags = vmcs_readl(GUEST_RFLAGS);
1704 if (to_vmx(vcpu)->rmode.vm86_active) {
1705 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1706 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1707 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1708 }
1709 to_vmx(vcpu)->rflags = rflags;
1710 }
1711 return to_vmx(vcpu)->rflags;
1712}
1713
1714static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1715{
1716 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1717 to_vmx(vcpu)->rflags = rflags;
1718 if (to_vmx(vcpu)->rmode.vm86_active) {
1719 to_vmx(vcpu)->rmode.save_rflags = rflags;
1720 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1721 }
1722 vmcs_writel(GUEST_RFLAGS, rflags);
1723}
1724
1725static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1726{
1727 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1728 int ret = 0;
1729
1730 if (interruptibility & GUEST_INTR_STATE_STI)
1731 ret |= KVM_X86_SHADOW_INT_STI;
1732 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1733 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1734
1735 return ret & mask;
1736}
1737
1738static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1739{
1740 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1741 u32 interruptibility = interruptibility_old;
1742
1743 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1744
1745 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1746 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1747 else if (mask & KVM_X86_SHADOW_INT_STI)
1748 interruptibility |= GUEST_INTR_STATE_STI;
1749
1750 if ((interruptibility != interruptibility_old))
1751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1752}
1753
1754static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1755{
1756 unsigned long rip;
1757
1758 rip = kvm_rip_read(vcpu);
1759 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1760 kvm_rip_write(vcpu, rip);
1761
1762 /* skipping an emulated instruction also counts */
1763 vmx_set_interrupt_shadow(vcpu, 0);
1764}
1765
1766/*
1767 * KVM wants to inject page-faults which it got to the guest. This function
1768 * checks whether in a nested guest, we need to inject them to L1 or L2.
1769 * This function assumes it is called with the exit reason in vmcs02 being
1770 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1771 * is running).
1772 */
1773static int nested_pf_handled(struct kvm_vcpu *vcpu)
1774{
1775 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1776
1777 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1778 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1779 return 0;
1780
1781 nested_vmx_vmexit(vcpu);
1782 return 1;
1783}
1784
1785static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1786 bool has_error_code, u32 error_code,
1787 bool reinject)
1788{
1789 struct vcpu_vmx *vmx = to_vmx(vcpu);
1790 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1791
1792 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1793 nested_pf_handled(vcpu))
1794 return;
1795
1796 if (has_error_code) {
1797 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1798 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1799 }
1800
1801 if (vmx->rmode.vm86_active) {
1802 int inc_eip = 0;
1803 if (kvm_exception_is_soft(nr))
1804 inc_eip = vcpu->arch.event_exit_inst_len;
1805 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1806 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1807 return;
1808 }
1809
1810 if (kvm_exception_is_soft(nr)) {
1811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1812 vmx->vcpu.arch.event_exit_inst_len);
1813 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1814 } else
1815 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1816
1817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1818}
1819
1820static bool vmx_rdtscp_supported(void)
1821{
1822 return cpu_has_vmx_rdtscp();
1823}
1824
1825static bool vmx_invpcid_supported(void)
1826{
1827 return cpu_has_vmx_invpcid() && enable_ept;
1828}
1829
1830/*
1831 * Swap MSR entry in host/guest MSR entry array.
1832 */
1833static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1834{
1835 struct shared_msr_entry tmp;
1836
1837 tmp = vmx->guest_msrs[to];
1838 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1839 vmx->guest_msrs[from] = tmp;
1840}
1841
1842static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1843{
1844 unsigned long *msr_bitmap;
1845
1846 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1847 if (is_long_mode(vcpu))
1848 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1849 else
1850 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1851 } else {
1852 if (is_long_mode(vcpu))
1853 msr_bitmap = vmx_msr_bitmap_longmode;
1854 else
1855 msr_bitmap = vmx_msr_bitmap_legacy;
1856 }
1857
1858 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1859}
1860
1861/*
1862 * Set up the vmcs to automatically save and restore system
1863 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1864 * mode, as fiddling with msrs is very expensive.
1865 */
1866static void setup_msrs(struct vcpu_vmx *vmx)
1867{
1868 int save_nmsrs, index;
1869
1870 save_nmsrs = 0;
1871#ifdef CONFIG_X86_64
1872 if (is_long_mode(&vmx->vcpu)) {
1873 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1874 if (index >= 0)
1875 move_msr_up(vmx, index, save_nmsrs++);
1876 index = __find_msr_index(vmx, MSR_LSTAR);
1877 if (index >= 0)
1878 move_msr_up(vmx, index, save_nmsrs++);
1879 index = __find_msr_index(vmx, MSR_CSTAR);
1880 if (index >= 0)
1881 move_msr_up(vmx, index, save_nmsrs++);
1882 index = __find_msr_index(vmx, MSR_TSC_AUX);
1883 if (index >= 0 && vmx->rdtscp_enabled)
1884 move_msr_up(vmx, index, save_nmsrs++);
1885 /*
1886 * MSR_STAR is only needed on long mode guests, and only
1887 * if efer.sce is enabled.
1888 */
1889 index = __find_msr_index(vmx, MSR_STAR);
1890 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1891 move_msr_up(vmx, index, save_nmsrs++);
1892 }
1893#endif
1894 index = __find_msr_index(vmx, MSR_EFER);
1895 if (index >= 0 && update_transition_efer(vmx, index))
1896 move_msr_up(vmx, index, save_nmsrs++);
1897
1898 vmx->save_nmsrs = save_nmsrs;
1899
1900 if (cpu_has_vmx_msr_bitmap())
1901 vmx_set_msr_bitmap(&vmx->vcpu);
1902}
1903
1904/*
1905 * reads and returns guest's timestamp counter "register"
1906 * guest_tsc = host_tsc + tsc_offset -- 21.3
1907 */
1908static u64 guest_read_tsc(void)
1909{
1910 u64 host_tsc, tsc_offset;
1911
1912 rdtscll(host_tsc);
1913 tsc_offset = vmcs_read64(TSC_OFFSET);
1914 return host_tsc + tsc_offset;
1915}
1916
1917/*
1918 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1919 * counter, even if a nested guest (L2) is currently running.
1920 */
1921u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1922{
1923 u64 tsc_offset;
1924
1925 tsc_offset = is_guest_mode(vcpu) ?
1926 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1927 vmcs_read64(TSC_OFFSET);
1928 return host_tsc + tsc_offset;
1929}
1930
1931/*
1932 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1933 * software catchup for faster rates on slower CPUs.
1934 */
1935static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1936{
1937 if (!scale)
1938 return;
1939
1940 if (user_tsc_khz > tsc_khz) {
1941 vcpu->arch.tsc_catchup = 1;
1942 vcpu->arch.tsc_always_catchup = 1;
1943 } else
1944 WARN(1, "user requested TSC rate below hardware speed\n");
1945}
1946
1947static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1948{
1949 return vmcs_read64(TSC_OFFSET);
1950}
1951
1952/*
1953 * writes 'offset' into guest's timestamp counter offset register
1954 */
1955static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1956{
1957 if (is_guest_mode(vcpu)) {
1958 /*
1959 * We're here if L1 chose not to trap WRMSR to TSC. According
1960 * to the spec, this should set L1's TSC; The offset that L1
1961 * set for L2 remains unchanged, and still needs to be added
1962 * to the newly set TSC to get L2's TSC.
1963 */
1964 struct vmcs12 *vmcs12;
1965 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1966 /* recalculate vmcs02.TSC_OFFSET: */
1967 vmcs12 = get_vmcs12(vcpu);
1968 vmcs_write64(TSC_OFFSET, offset +
1969 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1970 vmcs12->tsc_offset : 0));
1971 } else {
1972 vmcs_write64(TSC_OFFSET, offset);
1973 }
1974}
1975
1976static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1977{
1978 u64 offset = vmcs_read64(TSC_OFFSET);
1979 vmcs_write64(TSC_OFFSET, offset + adjustment);
1980 if (is_guest_mode(vcpu)) {
1981 /* Even when running L2, the adjustment needs to apply to L1 */
1982 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1983 }
1984}
1985
1986static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1987{
1988 return target_tsc - native_read_tsc();
1989}
1990
1991static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1992{
1993 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1994 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1995}
1996
1997/*
1998 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1999 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2000 * all guests if the "nested" module option is off, and can also be disabled
2001 * for a single guest by disabling its VMX cpuid bit.
2002 */
2003static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2004{
2005 return nested && guest_cpuid_has_vmx(vcpu);
2006}
2007
2008/*
2009 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2010 * returned for the various VMX controls MSRs when nested VMX is enabled.
2011 * The same values should also be used to verify that vmcs12 control fields are
2012 * valid during nested entry from L1 to L2.
2013 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2014 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2015 * bit in the high half is on if the corresponding bit in the control field
2016 * may be on. See also vmx_control_verify().
2017 * TODO: allow these variables to be modified (downgraded) by module options
2018 * or other means.
2019 */
2020static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2021static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2022static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2023static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2024static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2025static __init void nested_vmx_setup_ctls_msrs(void)
2026{
2027 /*
2028 * Note that as a general rule, the high half of the MSRs (bits in
2029 * the control fields which may be 1) should be initialized by the
2030 * intersection of the underlying hardware's MSR (i.e., features which
2031 * can be supported) and the list of features we want to expose -
2032 * because they are known to be properly supported in our code.
2033 * Also, usually, the low half of the MSRs (bits which must be 1) can
2034 * be set to 0, meaning that L1 may turn off any of these bits. The
2035 * reason is that if one of these bits is necessary, it will appear
2036 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2037 * fields of vmcs01 and vmcs02, will turn these bits off - and
2038 * nested_vmx_exit_handled() will not pass related exits to L1.
2039 * These rules have exceptions below.
2040 */
2041
2042 /* pin-based controls */
2043 /*
2044 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2045 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2046 */
2047 nested_vmx_pinbased_ctls_low = 0x16 ;
2048 nested_vmx_pinbased_ctls_high = 0x16 |
2049 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2050 PIN_BASED_VIRTUAL_NMIS;
2051
2052 /*
2053 * Exit controls
2054 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2055 * 17 must be 1.
2056 */
2057 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2058 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2059#ifdef CONFIG_X86_64
2060 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2061#else
2062 nested_vmx_exit_ctls_high = 0;
2063#endif
2064 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2065
2066 /* entry controls */
2067 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2068 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2069 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2070 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2071 nested_vmx_entry_ctls_high &=
2072 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2073 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2074
2075 /* cpu-based controls */
2076 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2077 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2078 nested_vmx_procbased_ctls_low = 0;
2079 nested_vmx_procbased_ctls_high &=
2080 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2081 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2082 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2083 CPU_BASED_CR3_STORE_EXITING |
2084#ifdef CONFIG_X86_64
2085 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2086#endif
2087 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2088 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2089 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2090 CPU_BASED_PAUSE_EXITING |
2091 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2092 /*
2093 * We can allow some features even when not supported by the
2094 * hardware. For example, L1 can specify an MSR bitmap - and we
2095 * can use it to avoid exits to L1 - even when L0 runs L2
2096 * without MSR bitmaps.
2097 */
2098 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2099
2100 /* secondary cpu-based controls */
2101 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2102 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2103 nested_vmx_secondary_ctls_low = 0;
2104 nested_vmx_secondary_ctls_high &=
2105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2106 SECONDARY_EXEC_WBINVD_EXITING;
2107}
2108
2109static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2110{
2111 /*
2112 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2113 */
2114 return ((control & high) | low) == control;
2115}
2116
2117static inline u64 vmx_control_msr(u32 low, u32 high)
2118{
2119 return low | ((u64)high << 32);
2120}
2121
2122/*
2123 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2124 * also let it use VMX-specific MSRs.
2125 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2126 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2127 * like all other MSRs).
2128 */
2129static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2130{
2131 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2132 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2133 /*
2134 * According to the spec, processors which do not support VMX
2135 * should throw a #GP(0) when VMX capability MSRs are read.
2136 */
2137 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2138 return 1;
2139 }
2140
2141 switch (msr_index) {
2142 case MSR_IA32_FEATURE_CONTROL:
2143 *pdata = 0;
2144 break;
2145 case MSR_IA32_VMX_BASIC:
2146 /*
2147 * This MSR reports some information about VMX support. We
2148 * should return information about the VMX we emulate for the
2149 * guest, and the VMCS structure we give it - not about the
2150 * VMX support of the underlying hardware.
2151 */
2152 *pdata = VMCS12_REVISION |
2153 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2154 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2155 break;
2156 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2157 case MSR_IA32_VMX_PINBASED_CTLS:
2158 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2159 nested_vmx_pinbased_ctls_high);
2160 break;
2161 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2162 case MSR_IA32_VMX_PROCBASED_CTLS:
2163 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2164 nested_vmx_procbased_ctls_high);
2165 break;
2166 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2167 case MSR_IA32_VMX_EXIT_CTLS:
2168 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2169 nested_vmx_exit_ctls_high);
2170 break;
2171 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2172 case MSR_IA32_VMX_ENTRY_CTLS:
2173 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2174 nested_vmx_entry_ctls_high);
2175 break;
2176 case MSR_IA32_VMX_MISC:
2177 *pdata = 0;
2178 break;
2179 /*
2180 * These MSRs specify bits which the guest must keep fixed (on or off)
2181 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2182 * We picked the standard core2 setting.
2183 */
2184#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2185#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2186 case MSR_IA32_VMX_CR0_FIXED0:
2187 *pdata = VMXON_CR0_ALWAYSON;
2188 break;
2189 case MSR_IA32_VMX_CR0_FIXED1:
2190 *pdata = -1ULL;
2191 break;
2192 case MSR_IA32_VMX_CR4_FIXED0:
2193 *pdata = VMXON_CR4_ALWAYSON;
2194 break;
2195 case MSR_IA32_VMX_CR4_FIXED1:
2196 *pdata = -1ULL;
2197 break;
2198 case MSR_IA32_VMX_VMCS_ENUM:
2199 *pdata = 0x1f;
2200 break;
2201 case MSR_IA32_VMX_PROCBASED_CTLS2:
2202 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2203 nested_vmx_secondary_ctls_high);
2204 break;
2205 case MSR_IA32_VMX_EPT_VPID_CAP:
2206 /* Currently, no nested ept or nested vpid */
2207 *pdata = 0;
2208 break;
2209 default:
2210 return 0;
2211 }
2212
2213 return 1;
2214}
2215
2216static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2217{
2218 if (!nested_vmx_allowed(vcpu))
2219 return 0;
2220
2221 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2222 /* TODO: the right thing. */
2223 return 1;
2224 /*
2225 * No need to treat VMX capability MSRs specially: If we don't handle
2226 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2227 */
2228 return 0;
2229}
2230
2231/*
2232 * Reads an msr value (of 'msr_index') into 'pdata'.
2233 * Returns 0 on success, non-0 otherwise.
2234 * Assumes vcpu_load() was already called.
2235 */
2236static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2237{
2238 u64 data;
2239 struct shared_msr_entry *msr;
2240
2241 if (!pdata) {
2242 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2243 return -EINVAL;
2244 }
2245
2246 switch (msr_index) {
2247#ifdef CONFIG_X86_64
2248 case MSR_FS_BASE:
2249 data = vmcs_readl(GUEST_FS_BASE);
2250 break;
2251 case MSR_GS_BASE:
2252 data = vmcs_readl(GUEST_GS_BASE);
2253 break;
2254 case MSR_KERNEL_GS_BASE:
2255 vmx_load_host_state(to_vmx(vcpu));
2256 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2257 break;
2258#endif
2259 case MSR_EFER:
2260 return kvm_get_msr_common(vcpu, msr_index, pdata);
2261 case MSR_IA32_TSC:
2262 data = guest_read_tsc();
2263 break;
2264 case MSR_IA32_SYSENTER_CS:
2265 data = vmcs_read32(GUEST_SYSENTER_CS);
2266 break;
2267 case MSR_IA32_SYSENTER_EIP:
2268 data = vmcs_readl(GUEST_SYSENTER_EIP);
2269 break;
2270 case MSR_IA32_SYSENTER_ESP:
2271 data = vmcs_readl(GUEST_SYSENTER_ESP);
2272 break;
2273 case MSR_TSC_AUX:
2274 if (!to_vmx(vcpu)->rdtscp_enabled)
2275 return 1;
2276 /* Otherwise falls through */
2277 default:
2278 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2279 return 0;
2280 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2281 if (msr) {
2282 data = msr->data;
2283 break;
2284 }
2285 return kvm_get_msr_common(vcpu, msr_index, pdata);
2286 }
2287
2288 *pdata = data;
2289 return 0;
2290}
2291
2292/*
2293 * Writes msr value into into the appropriate "register".
2294 * Returns 0 on success, non-0 otherwise.
2295 * Assumes vcpu_load() was already called.
2296 */
2297static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2298{
2299 struct vcpu_vmx *vmx = to_vmx(vcpu);
2300 struct shared_msr_entry *msr;
2301 int ret = 0;
2302 u32 msr_index = msr_info->index;
2303 u64 data = msr_info->data;
2304
2305 switch (msr_index) {
2306 case MSR_EFER:
2307 ret = kvm_set_msr_common(vcpu, msr_info);
2308 break;
2309#ifdef CONFIG_X86_64
2310 case MSR_FS_BASE:
2311 vmx_segment_cache_clear(vmx);
2312 vmcs_writel(GUEST_FS_BASE, data);
2313 break;
2314 case MSR_GS_BASE:
2315 vmx_segment_cache_clear(vmx);
2316 vmcs_writel(GUEST_GS_BASE, data);
2317 break;
2318 case MSR_KERNEL_GS_BASE:
2319 vmx_load_host_state(vmx);
2320 vmx->msr_guest_kernel_gs_base = data;
2321 break;
2322#endif
2323 case MSR_IA32_SYSENTER_CS:
2324 vmcs_write32(GUEST_SYSENTER_CS, data);
2325 break;
2326 case MSR_IA32_SYSENTER_EIP:
2327 vmcs_writel(GUEST_SYSENTER_EIP, data);
2328 break;
2329 case MSR_IA32_SYSENTER_ESP:
2330 vmcs_writel(GUEST_SYSENTER_ESP, data);
2331 break;
2332 case MSR_IA32_TSC:
2333 kvm_write_tsc(vcpu, msr_info);
2334 break;
2335 case MSR_IA32_CR_PAT:
2336 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2337 vmcs_write64(GUEST_IA32_PAT, data);
2338 vcpu->arch.pat = data;
2339 break;
2340 }
2341 ret = kvm_set_msr_common(vcpu, msr_info);
2342 break;
2343 case MSR_IA32_TSC_ADJUST:
2344 ret = kvm_set_msr_common(vcpu, msr_info);
2345 break;
2346 case MSR_TSC_AUX:
2347 if (!vmx->rdtscp_enabled)
2348 return 1;
2349 /* Check reserved bit, higher 32 bits should be zero */
2350 if ((data >> 32) != 0)
2351 return 1;
2352 /* Otherwise falls through */
2353 default:
2354 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2355 break;
2356 msr = find_msr_entry(vmx, msr_index);
2357 if (msr) {
2358 msr->data = data;
2359 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2360 preempt_disable();
2361 kvm_set_shared_msr(msr->index, msr->data,
2362 msr->mask);
2363 preempt_enable();
2364 }
2365 break;
2366 }
2367 ret = kvm_set_msr_common(vcpu, msr_info);
2368 }
2369
2370 return ret;
2371}
2372
2373static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2374{
2375 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2376 switch (reg) {
2377 case VCPU_REGS_RSP:
2378 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2379 break;
2380 case VCPU_REGS_RIP:
2381 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2382 break;
2383 case VCPU_EXREG_PDPTR:
2384 if (enable_ept)
2385 ept_save_pdptrs(vcpu);
2386 break;
2387 default:
2388 break;
2389 }
2390}
2391
2392static __init int cpu_has_kvm_support(void)
2393{
2394 return cpu_has_vmx();
2395}
2396
2397static __init int vmx_disabled_by_bios(void)
2398{
2399 u64 msr;
2400
2401 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2402 if (msr & FEATURE_CONTROL_LOCKED) {
2403 /* launched w/ TXT and VMX disabled */
2404 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2405 && tboot_enabled())
2406 return 1;
2407 /* launched w/o TXT and VMX only enabled w/ TXT */
2408 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2409 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2410 && !tboot_enabled()) {
2411 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2412 "activate TXT before enabling KVM\n");
2413 return 1;
2414 }
2415 /* launched w/o TXT and VMX disabled */
2416 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2417 && !tboot_enabled())
2418 return 1;
2419 }
2420
2421 return 0;
2422}
2423
2424static void kvm_cpu_vmxon(u64 addr)
2425{
2426 asm volatile (ASM_VMX_VMXON_RAX
2427 : : "a"(&addr), "m"(addr)
2428 : "memory", "cc");
2429}
2430
2431static int hardware_enable(void *garbage)
2432{
2433 int cpu = raw_smp_processor_id();
2434 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2435 u64 old, test_bits;
2436
2437 if (read_cr4() & X86_CR4_VMXE)
2438 return -EBUSY;
2439
2440 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2441
2442 /*
2443 * Now we can enable the vmclear operation in kdump
2444 * since the loaded_vmcss_on_cpu list on this cpu
2445 * has been initialized.
2446 *
2447 * Though the cpu is not in VMX operation now, there
2448 * is no problem to enable the vmclear operation
2449 * for the loaded_vmcss_on_cpu list is empty!
2450 */
2451 crash_enable_local_vmclear(cpu);
2452
2453 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2454
2455 test_bits = FEATURE_CONTROL_LOCKED;
2456 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2457 if (tboot_enabled())
2458 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2459
2460 if ((old & test_bits) != test_bits) {
2461 /* enable and lock */
2462 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2463 }
2464 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2465
2466 if (vmm_exclusive) {
2467 kvm_cpu_vmxon(phys_addr);
2468 ept_sync_global();
2469 }
2470
2471 store_gdt(&__get_cpu_var(host_gdt));
2472
2473 return 0;
2474}
2475
2476static void vmclear_local_loaded_vmcss(void)
2477{
2478 int cpu = raw_smp_processor_id();
2479 struct loaded_vmcs *v, *n;
2480
2481 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2482 loaded_vmcss_on_cpu_link)
2483 __loaded_vmcs_clear(v);
2484}
2485
2486
2487/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2488 * tricks.
2489 */
2490static void kvm_cpu_vmxoff(void)
2491{
2492 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2493}
2494
2495static void hardware_disable(void *garbage)
2496{
2497 if (vmm_exclusive) {
2498 vmclear_local_loaded_vmcss();
2499 kvm_cpu_vmxoff();
2500 }
2501 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2502}
2503
2504static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2505 u32 msr, u32 *result)
2506{
2507 u32 vmx_msr_low, vmx_msr_high;
2508 u32 ctl = ctl_min | ctl_opt;
2509
2510 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2511
2512 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2513 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2514
2515 /* Ensure minimum (required) set of control bits are supported. */
2516 if (ctl_min & ~ctl)
2517 return -EIO;
2518
2519 *result = ctl;
2520 return 0;
2521}
2522
2523static __init bool allow_1_setting(u32 msr, u32 ctl)
2524{
2525 u32 vmx_msr_low, vmx_msr_high;
2526
2527 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2528 return vmx_msr_high & ctl;
2529}
2530
2531static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2532{
2533 u32 vmx_msr_low, vmx_msr_high;
2534 u32 min, opt, min2, opt2;
2535 u32 _pin_based_exec_control = 0;
2536 u32 _cpu_based_exec_control = 0;
2537 u32 _cpu_based_2nd_exec_control = 0;
2538 u32 _vmexit_control = 0;
2539 u32 _vmentry_control = 0;
2540
2541 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2542 opt = PIN_BASED_VIRTUAL_NMIS;
2543 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2544 &_pin_based_exec_control) < 0)
2545 return -EIO;
2546
2547 min = CPU_BASED_HLT_EXITING |
2548#ifdef CONFIG_X86_64
2549 CPU_BASED_CR8_LOAD_EXITING |
2550 CPU_BASED_CR8_STORE_EXITING |
2551#endif
2552 CPU_BASED_CR3_LOAD_EXITING |
2553 CPU_BASED_CR3_STORE_EXITING |
2554 CPU_BASED_USE_IO_BITMAPS |
2555 CPU_BASED_MOV_DR_EXITING |
2556 CPU_BASED_USE_TSC_OFFSETING |
2557 CPU_BASED_MWAIT_EXITING |
2558 CPU_BASED_MONITOR_EXITING |
2559 CPU_BASED_INVLPG_EXITING |
2560 CPU_BASED_RDPMC_EXITING;
2561
2562 opt = CPU_BASED_TPR_SHADOW |
2563 CPU_BASED_USE_MSR_BITMAPS |
2564 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2565 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2566 &_cpu_based_exec_control) < 0)
2567 return -EIO;
2568#ifdef CONFIG_X86_64
2569 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2570 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2571 ~CPU_BASED_CR8_STORE_EXITING;
2572#endif
2573 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2574 min2 = 0;
2575 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2576 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2577 SECONDARY_EXEC_WBINVD_EXITING |
2578 SECONDARY_EXEC_ENABLE_VPID |
2579 SECONDARY_EXEC_ENABLE_EPT |
2580 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2581 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2582 SECONDARY_EXEC_RDTSCP |
2583 SECONDARY_EXEC_ENABLE_INVPCID |
2584 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2585 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
2586 if (adjust_vmx_controls(min2, opt2,
2587 MSR_IA32_VMX_PROCBASED_CTLS2,
2588 &_cpu_based_2nd_exec_control) < 0)
2589 return -EIO;
2590 }
2591#ifndef CONFIG_X86_64
2592 if (!(_cpu_based_2nd_exec_control &
2593 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2594 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2595#endif
2596
2597 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2598 _cpu_based_2nd_exec_control &= ~(
2599 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2600 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2601 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2602
2603 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2604 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2605 enabled */
2606 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2607 CPU_BASED_CR3_STORE_EXITING |
2608 CPU_BASED_INVLPG_EXITING);
2609 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2610 vmx_capability.ept, vmx_capability.vpid);
2611 }
2612
2613 min = 0;
2614#ifdef CONFIG_X86_64
2615 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2616#endif
2617 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2618 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2619 &_vmexit_control) < 0)
2620 return -EIO;
2621
2622 min = 0;
2623 opt = VM_ENTRY_LOAD_IA32_PAT;
2624 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2625 &_vmentry_control) < 0)
2626 return -EIO;
2627
2628 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2629
2630 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2631 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2632 return -EIO;
2633
2634#ifdef CONFIG_X86_64
2635 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2636 if (vmx_msr_high & (1u<<16))
2637 return -EIO;
2638#endif
2639
2640 /* Require Write-Back (WB) memory type for VMCS accesses. */
2641 if (((vmx_msr_high >> 18) & 15) != 6)
2642 return -EIO;
2643
2644 vmcs_conf->size = vmx_msr_high & 0x1fff;
2645 vmcs_conf->order = get_order(vmcs_config.size);
2646 vmcs_conf->revision_id = vmx_msr_low;
2647
2648 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2649 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2650 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2651 vmcs_conf->vmexit_ctrl = _vmexit_control;
2652 vmcs_conf->vmentry_ctrl = _vmentry_control;
2653
2654 cpu_has_load_ia32_efer =
2655 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2656 VM_ENTRY_LOAD_IA32_EFER)
2657 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2658 VM_EXIT_LOAD_IA32_EFER);
2659
2660 cpu_has_load_perf_global_ctrl =
2661 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2662 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2663 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2664 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2665
2666 /*
2667 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2668 * but due to arrata below it can't be used. Workaround is to use
2669 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2670 *
2671 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2672 *
2673 * AAK155 (model 26)
2674 * AAP115 (model 30)
2675 * AAT100 (model 37)
2676 * BC86,AAY89,BD102 (model 44)
2677 * BA97 (model 46)
2678 *
2679 */
2680 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2681 switch (boot_cpu_data.x86_model) {
2682 case 26:
2683 case 30:
2684 case 37:
2685 case 44:
2686 case 46:
2687 cpu_has_load_perf_global_ctrl = false;
2688 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2689 "does not work properly. Using workaround\n");
2690 break;
2691 default:
2692 break;
2693 }
2694 }
2695
2696 return 0;
2697}
2698
2699static struct vmcs *alloc_vmcs_cpu(int cpu)
2700{
2701 int node = cpu_to_node(cpu);
2702 struct page *pages;
2703 struct vmcs *vmcs;
2704
2705 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2706 if (!pages)
2707 return NULL;
2708 vmcs = page_address(pages);
2709 memset(vmcs, 0, vmcs_config.size);
2710 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2711 return vmcs;
2712}
2713
2714static struct vmcs *alloc_vmcs(void)
2715{
2716 return alloc_vmcs_cpu(raw_smp_processor_id());
2717}
2718
2719static void free_vmcs(struct vmcs *vmcs)
2720{
2721 free_pages((unsigned long)vmcs, vmcs_config.order);
2722}
2723
2724/*
2725 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2726 */
2727static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2728{
2729 if (!loaded_vmcs->vmcs)
2730 return;
2731 loaded_vmcs_clear(loaded_vmcs);
2732 free_vmcs(loaded_vmcs->vmcs);
2733 loaded_vmcs->vmcs = NULL;
2734}
2735
2736static void free_kvm_area(void)
2737{
2738 int cpu;
2739
2740 for_each_possible_cpu(cpu) {
2741 free_vmcs(per_cpu(vmxarea, cpu));
2742 per_cpu(vmxarea, cpu) = NULL;
2743 }
2744}
2745
2746static __init int alloc_kvm_area(void)
2747{
2748 int cpu;
2749
2750 for_each_possible_cpu(cpu) {
2751 struct vmcs *vmcs;
2752
2753 vmcs = alloc_vmcs_cpu(cpu);
2754 if (!vmcs) {
2755 free_kvm_area();
2756 return -ENOMEM;
2757 }
2758
2759 per_cpu(vmxarea, cpu) = vmcs;
2760 }
2761 return 0;
2762}
2763
2764static __init int hardware_setup(void)
2765{
2766 if (setup_vmcs_config(&vmcs_config) < 0)
2767 return -EIO;
2768
2769 if (boot_cpu_has(X86_FEATURE_NX))
2770 kvm_enable_efer_bits(EFER_NX);
2771
2772 if (!cpu_has_vmx_vpid())
2773 enable_vpid = 0;
2774
2775 if (!cpu_has_vmx_ept() ||
2776 !cpu_has_vmx_ept_4levels()) {
2777 enable_ept = 0;
2778 enable_unrestricted_guest = 0;
2779 enable_ept_ad_bits = 0;
2780 }
2781
2782 if (!cpu_has_vmx_ept_ad_bits())
2783 enable_ept_ad_bits = 0;
2784
2785 if (!cpu_has_vmx_unrestricted_guest())
2786 enable_unrestricted_guest = 0;
2787
2788 if (!cpu_has_vmx_flexpriority())
2789 flexpriority_enabled = 0;
2790
2791 if (!cpu_has_vmx_tpr_shadow())
2792 kvm_x86_ops->update_cr8_intercept = NULL;
2793
2794 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2795 kvm_disable_largepages();
2796
2797 if (!cpu_has_vmx_ple())
2798 ple_gap = 0;
2799
2800 if (!cpu_has_vmx_apic_register_virt() ||
2801 !cpu_has_vmx_virtual_intr_delivery())
2802 enable_apicv_reg_vid = 0;
2803
2804 if (enable_apicv_reg_vid)
2805 kvm_x86_ops->update_cr8_intercept = NULL;
2806 else
2807 kvm_x86_ops->hwapic_irr_update = NULL;
2808
2809 if (nested)
2810 nested_vmx_setup_ctls_msrs();
2811
2812 return alloc_kvm_area();
2813}
2814
2815static __exit void hardware_unsetup(void)
2816{
2817 free_kvm_area();
2818}
2819
2820static bool emulation_required(struct kvm_vcpu *vcpu)
2821{
2822 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2823}
2824
2825static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
2826 struct kvm_segment *save)
2827{
2828 if (!emulate_invalid_guest_state) {
2829 /*
2830 * CS and SS RPL should be equal during guest entry according
2831 * to VMX spec, but in reality it is not always so. Since vcpu
2832 * is in the middle of the transition from real mode to
2833 * protected mode it is safe to assume that RPL 0 is a good
2834 * default value.
2835 */
2836 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2837 save->selector &= ~SELECTOR_RPL_MASK;
2838 save->dpl = save->selector & SELECTOR_RPL_MASK;
2839 save->s = 1;
2840 }
2841 vmx_set_segment(vcpu, save, seg);
2842}
2843
2844static void enter_pmode(struct kvm_vcpu *vcpu)
2845{
2846 unsigned long flags;
2847 struct vcpu_vmx *vmx = to_vmx(vcpu);
2848
2849 /*
2850 * Update real mode segment cache. It may be not up-to-date if sement
2851 * register was written while vcpu was in a guest mode.
2852 */
2853 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2859
2860 vmx->rmode.vm86_active = 0;
2861
2862 vmx_segment_cache_clear(vmx);
2863
2864 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2865
2866 flags = vmcs_readl(GUEST_RFLAGS);
2867 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2868 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2869 vmcs_writel(GUEST_RFLAGS, flags);
2870
2871 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2872 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2873
2874 update_exception_bitmap(vcpu);
2875
2876 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2877 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2878 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2879 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2880 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2881 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2882
2883 /* CPL is always 0 when CPU enters protected mode */
2884 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2885 vmx->cpl = 0;
2886}
2887
2888static gva_t rmode_tss_base(struct kvm *kvm)
2889{
2890 if (!kvm->arch.tss_addr) {
2891 struct kvm_memslots *slots;
2892 struct kvm_memory_slot *slot;
2893 gfn_t base_gfn;
2894
2895 slots = kvm_memslots(kvm);
2896 slot = id_to_memslot(slots, 0);
2897 base_gfn = slot->base_gfn + slot->npages - 3;
2898
2899 return base_gfn << PAGE_SHIFT;
2900 }
2901 return kvm->arch.tss_addr;
2902}
2903
2904static void fix_rmode_seg(int seg, struct kvm_segment *save)
2905{
2906 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2907 struct kvm_segment var = *save;
2908
2909 var.dpl = 0x3;
2910 if (seg == VCPU_SREG_CS)
2911 var.type = 0x3;
2912
2913 if (!emulate_invalid_guest_state) {
2914 var.selector = var.base >> 4;
2915 var.base = var.base & 0xffff0;
2916 var.limit = 0xffff;
2917 var.g = 0;
2918 var.db = 0;
2919 var.present = 1;
2920 var.s = 1;
2921 var.l = 0;
2922 var.unusable = 0;
2923 var.type = 0x3;
2924 var.avl = 0;
2925 if (save->base & 0xf)
2926 printk_once(KERN_WARNING "kvm: segment base is not "
2927 "paragraph aligned when entering "
2928 "protected mode (seg=%d)", seg);
2929 }
2930
2931 vmcs_write16(sf->selector, var.selector);
2932 vmcs_write32(sf->base, var.base);
2933 vmcs_write32(sf->limit, var.limit);
2934 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
2935}
2936
2937static void enter_rmode(struct kvm_vcpu *vcpu)
2938{
2939 unsigned long flags;
2940 struct vcpu_vmx *vmx = to_vmx(vcpu);
2941
2942 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2943 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2944 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2945 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2947 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2948 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2949
2950 vmx->rmode.vm86_active = 1;
2951
2952 /*
2953 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2954 * vcpu. Call it here with phys address pointing 16M below 4G.
2955 */
2956 if (!vcpu->kvm->arch.tss_addr) {
2957 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2958 "called before entering vcpu\n");
2959 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2960 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2961 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2962 }
2963
2964 vmx_segment_cache_clear(vmx);
2965
2966 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2967 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2968 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2969
2970 flags = vmcs_readl(GUEST_RFLAGS);
2971 vmx->rmode.save_rflags = flags;
2972
2973 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2974
2975 vmcs_writel(GUEST_RFLAGS, flags);
2976 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2977 update_exception_bitmap(vcpu);
2978
2979 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2980 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2981 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2982 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2983 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2984 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2985
2986 kvm_mmu_reset_context(vcpu);
2987}
2988
2989static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2990{
2991 struct vcpu_vmx *vmx = to_vmx(vcpu);
2992 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2993
2994 if (!msr)
2995 return;
2996
2997 /*
2998 * Force kernel_gs_base reloading before EFER changes, as control
2999 * of this msr depends on is_long_mode().
3000 */
3001 vmx_load_host_state(to_vmx(vcpu));
3002 vcpu->arch.efer = efer;
3003 if (efer & EFER_LMA) {
3004 vmcs_write32(VM_ENTRY_CONTROLS,
3005 vmcs_read32(VM_ENTRY_CONTROLS) |
3006 VM_ENTRY_IA32E_MODE);
3007 msr->data = efer;
3008 } else {
3009 vmcs_write32(VM_ENTRY_CONTROLS,
3010 vmcs_read32(VM_ENTRY_CONTROLS) &
3011 ~VM_ENTRY_IA32E_MODE);
3012
3013 msr->data = efer & ~EFER_LME;
3014 }
3015 setup_msrs(vmx);
3016}
3017
3018#ifdef CONFIG_X86_64
3019
3020static void enter_lmode(struct kvm_vcpu *vcpu)
3021{
3022 u32 guest_tr_ar;
3023
3024 vmx_segment_cache_clear(to_vmx(vcpu));
3025
3026 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3027 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3028 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3029 __func__);
3030 vmcs_write32(GUEST_TR_AR_BYTES,
3031 (guest_tr_ar & ~AR_TYPE_MASK)
3032 | AR_TYPE_BUSY_64_TSS);
3033 }
3034 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3035}
3036
3037static void exit_lmode(struct kvm_vcpu *vcpu)
3038{
3039 vmcs_write32(VM_ENTRY_CONTROLS,
3040 vmcs_read32(VM_ENTRY_CONTROLS)
3041 & ~VM_ENTRY_IA32E_MODE);
3042 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3043}
3044
3045#endif
3046
3047static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3048{
3049 vpid_sync_context(to_vmx(vcpu));
3050 if (enable_ept) {
3051 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3052 return;
3053 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3054 }
3055}
3056
3057static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3058{
3059 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3060
3061 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3062 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3063}
3064
3065static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3066{
3067 if (enable_ept && is_paging(vcpu))
3068 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3069 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3070}
3071
3072static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3073{
3074 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3075
3076 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3077 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3078}
3079
3080static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3081{
3082 if (!test_bit(VCPU_EXREG_PDPTR,
3083 (unsigned long *)&vcpu->arch.regs_dirty))
3084 return;
3085
3086 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3087 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3088 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3089 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3090 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3091 }
3092}
3093
3094static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3095{
3096 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3097 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3098 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3099 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3100 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3101 }
3102
3103 __set_bit(VCPU_EXREG_PDPTR,
3104 (unsigned long *)&vcpu->arch.regs_avail);
3105 __set_bit(VCPU_EXREG_PDPTR,
3106 (unsigned long *)&vcpu->arch.regs_dirty);
3107}
3108
3109static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3110
3111static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3112 unsigned long cr0,
3113 struct kvm_vcpu *vcpu)
3114{
3115 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3116 vmx_decache_cr3(vcpu);
3117 if (!(cr0 & X86_CR0_PG)) {
3118 /* From paging/starting to nonpaging */
3119 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3120 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3121 (CPU_BASED_CR3_LOAD_EXITING |
3122 CPU_BASED_CR3_STORE_EXITING));
3123 vcpu->arch.cr0 = cr0;
3124 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3125 } else if (!is_paging(vcpu)) {
3126 /* From nonpaging to paging */
3127 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3128 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3129 ~(CPU_BASED_CR3_LOAD_EXITING |
3130 CPU_BASED_CR3_STORE_EXITING));
3131 vcpu->arch.cr0 = cr0;
3132 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3133 }
3134
3135 if (!(cr0 & X86_CR0_WP))
3136 *hw_cr0 &= ~X86_CR0_WP;
3137}
3138
3139static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3140{
3141 struct vcpu_vmx *vmx = to_vmx(vcpu);
3142 unsigned long hw_cr0;
3143
3144 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3145 if (enable_unrestricted_guest)
3146 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3147 else {
3148 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3149
3150 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3151 enter_pmode(vcpu);
3152
3153 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3154 enter_rmode(vcpu);
3155 }
3156
3157#ifdef CONFIG_X86_64
3158 if (vcpu->arch.efer & EFER_LME) {
3159 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3160 enter_lmode(vcpu);
3161 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3162 exit_lmode(vcpu);
3163 }
3164#endif
3165
3166 if (enable_ept)
3167 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3168
3169 if (!vcpu->fpu_active)
3170 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3171
3172 vmcs_writel(CR0_READ_SHADOW, cr0);
3173 vmcs_writel(GUEST_CR0, hw_cr0);
3174 vcpu->arch.cr0 = cr0;
3175
3176 /* depends on vcpu->arch.cr0 to be set to a new value */
3177 vmx->emulation_required = emulation_required(vcpu);
3178}
3179
3180static u64 construct_eptp(unsigned long root_hpa)
3181{
3182 u64 eptp;
3183
3184 /* TODO write the value reading from MSR */
3185 eptp = VMX_EPT_DEFAULT_MT |
3186 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3187 if (enable_ept_ad_bits)
3188 eptp |= VMX_EPT_AD_ENABLE_BIT;
3189 eptp |= (root_hpa & PAGE_MASK);
3190
3191 return eptp;
3192}
3193
3194static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3195{
3196 unsigned long guest_cr3;
3197 u64 eptp;
3198
3199 guest_cr3 = cr3;
3200 if (enable_ept) {
3201 eptp = construct_eptp(cr3);
3202 vmcs_write64(EPT_POINTER, eptp);
3203 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3204 vcpu->kvm->arch.ept_identity_map_addr;
3205 ept_load_pdptrs(vcpu);
3206 }
3207
3208 vmx_flush_tlb(vcpu);
3209 vmcs_writel(GUEST_CR3, guest_cr3);
3210}
3211
3212static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3213{
3214 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3215 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3216
3217 if (cr4 & X86_CR4_VMXE) {
3218 /*
3219 * To use VMXON (and later other VMX instructions), a guest
3220 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3221 * So basically the check on whether to allow nested VMX
3222 * is here.
3223 */
3224 if (!nested_vmx_allowed(vcpu))
3225 return 1;
3226 }
3227 if (to_vmx(vcpu)->nested.vmxon &&
3228 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3229 return 1;
3230
3231 vcpu->arch.cr4 = cr4;
3232 if (enable_ept) {
3233 if (!is_paging(vcpu)) {
3234 hw_cr4 &= ~X86_CR4_PAE;
3235 hw_cr4 |= X86_CR4_PSE;
3236 /*
3237 * SMEP is disabled if CPU is in non-paging mode in
3238 * hardware. However KVM always uses paging mode to
3239 * emulate guest non-paging mode with TDP.
3240 * To emulate this behavior, SMEP needs to be manually
3241 * disabled when guest switches to non-paging mode.
3242 */
3243 hw_cr4 &= ~X86_CR4_SMEP;
3244 } else if (!(cr4 & X86_CR4_PAE)) {
3245 hw_cr4 &= ~X86_CR4_PAE;
3246 }
3247 }
3248
3249 vmcs_writel(CR4_READ_SHADOW, cr4);
3250 vmcs_writel(GUEST_CR4, hw_cr4);
3251 return 0;
3252}
3253
3254static void vmx_get_segment(struct kvm_vcpu *vcpu,
3255 struct kvm_segment *var, int seg)
3256{
3257 struct vcpu_vmx *vmx = to_vmx(vcpu);
3258 u32 ar;
3259
3260 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3261 *var = vmx->rmode.segs[seg];
3262 if (seg == VCPU_SREG_TR
3263 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3264 return;
3265 var->base = vmx_read_guest_seg_base(vmx, seg);
3266 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3267 return;
3268 }
3269 var->base = vmx_read_guest_seg_base(vmx, seg);
3270 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3271 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3272 ar = vmx_read_guest_seg_ar(vmx, seg);
3273 var->type = ar & 15;
3274 var->s = (ar >> 4) & 1;
3275 var->dpl = (ar >> 5) & 3;
3276 var->present = (ar >> 7) & 1;
3277 var->avl = (ar >> 12) & 1;
3278 var->l = (ar >> 13) & 1;
3279 var->db = (ar >> 14) & 1;
3280 var->g = (ar >> 15) & 1;
3281 var->unusable = (ar >> 16) & 1;
3282}
3283
3284static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3285{
3286 struct kvm_segment s;
3287
3288 if (to_vmx(vcpu)->rmode.vm86_active) {
3289 vmx_get_segment(vcpu, &s, seg);
3290 return s.base;
3291 }
3292 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3293}
3294
3295static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3296{
3297 struct vcpu_vmx *vmx = to_vmx(vcpu);
3298
3299 if (!is_protmode(vcpu))
3300 return 0;
3301
3302 if (!is_long_mode(vcpu)
3303 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3304 return 3;
3305
3306 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3307 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3308 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3309 }
3310
3311 return vmx->cpl;
3312}
3313
3314
3315static u32 vmx_segment_access_rights(struct kvm_segment *var)
3316{
3317 u32 ar;
3318
3319 if (var->unusable || !var->present)
3320 ar = 1 << 16;
3321 else {
3322 ar = var->type & 15;
3323 ar |= (var->s & 1) << 4;
3324 ar |= (var->dpl & 3) << 5;
3325 ar |= (var->present & 1) << 7;
3326 ar |= (var->avl & 1) << 12;
3327 ar |= (var->l & 1) << 13;
3328 ar |= (var->db & 1) << 14;
3329 ar |= (var->g & 1) << 15;
3330 }
3331
3332 return ar;
3333}
3334
3335static void vmx_set_segment(struct kvm_vcpu *vcpu,
3336 struct kvm_segment *var, int seg)
3337{
3338 struct vcpu_vmx *vmx = to_vmx(vcpu);
3339 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3340
3341 vmx_segment_cache_clear(vmx);
3342 if (seg == VCPU_SREG_CS)
3343 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3344
3345 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3346 vmx->rmode.segs[seg] = *var;
3347 if (seg == VCPU_SREG_TR)
3348 vmcs_write16(sf->selector, var->selector);
3349 else if (var->s)
3350 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3351 goto out;
3352 }
3353
3354 vmcs_writel(sf->base, var->base);
3355 vmcs_write32(sf->limit, var->limit);
3356 vmcs_write16(sf->selector, var->selector);
3357
3358 /*
3359 * Fix the "Accessed" bit in AR field of segment registers for older
3360 * qemu binaries.
3361 * IA32 arch specifies that at the time of processor reset the
3362 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3363 * is setting it to 0 in the userland code. This causes invalid guest
3364 * state vmexit when "unrestricted guest" mode is turned on.
3365 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3366 * tree. Newer qemu binaries with that qemu fix would not need this
3367 * kvm hack.
3368 */
3369 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3370 var->type |= 0x1; /* Accessed */
3371
3372 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3373
3374out:
3375 vmx->emulation_required |= emulation_required(vcpu);
3376}
3377
3378static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3379{
3380 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3381
3382 *db = (ar >> 14) & 1;
3383 *l = (ar >> 13) & 1;
3384}
3385
3386static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3387{
3388 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3389 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3390}
3391
3392static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3393{
3394 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3395 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3396}
3397
3398static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3399{
3400 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3401 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3402}
3403
3404static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3405{
3406 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3407 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3408}
3409
3410static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3411{
3412 struct kvm_segment var;
3413 u32 ar;
3414
3415 vmx_get_segment(vcpu, &var, seg);
3416 var.dpl = 0x3;
3417 if (seg == VCPU_SREG_CS)
3418 var.type = 0x3;
3419 ar = vmx_segment_access_rights(&var);
3420
3421 if (var.base != (var.selector << 4))
3422 return false;
3423 if (var.limit != 0xffff)
3424 return false;
3425 if (ar != 0xf3)
3426 return false;
3427
3428 return true;
3429}
3430
3431static bool code_segment_valid(struct kvm_vcpu *vcpu)
3432{
3433 struct kvm_segment cs;
3434 unsigned int cs_rpl;
3435
3436 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3437 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3438
3439 if (cs.unusable)
3440 return false;
3441 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3442 return false;
3443 if (!cs.s)
3444 return false;
3445 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3446 if (cs.dpl > cs_rpl)
3447 return false;
3448 } else {
3449 if (cs.dpl != cs_rpl)
3450 return false;
3451 }
3452 if (!cs.present)
3453 return false;
3454
3455 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3456 return true;
3457}
3458
3459static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3460{
3461 struct kvm_segment ss;
3462 unsigned int ss_rpl;
3463
3464 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3465 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3466
3467 if (ss.unusable)
3468 return true;
3469 if (ss.type != 3 && ss.type != 7)
3470 return false;
3471 if (!ss.s)
3472 return false;
3473 if (ss.dpl != ss_rpl) /* DPL != RPL */
3474 return false;
3475 if (!ss.present)
3476 return false;
3477
3478 return true;
3479}
3480
3481static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3482{
3483 struct kvm_segment var;
3484 unsigned int rpl;
3485
3486 vmx_get_segment(vcpu, &var, seg);
3487 rpl = var.selector & SELECTOR_RPL_MASK;
3488
3489 if (var.unusable)
3490 return true;
3491 if (!var.s)
3492 return false;
3493 if (!var.present)
3494 return false;
3495 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3496 if (var.dpl < rpl) /* DPL < RPL */
3497 return false;
3498 }
3499
3500 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3501 * rights flags
3502 */
3503 return true;
3504}
3505
3506static bool tr_valid(struct kvm_vcpu *vcpu)
3507{
3508 struct kvm_segment tr;
3509
3510 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3511
3512 if (tr.unusable)
3513 return false;
3514 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3515 return false;
3516 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3517 return false;
3518 if (!tr.present)
3519 return false;
3520
3521 return true;
3522}
3523
3524static bool ldtr_valid(struct kvm_vcpu *vcpu)
3525{
3526 struct kvm_segment ldtr;
3527
3528 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3529
3530 if (ldtr.unusable)
3531 return true;
3532 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3533 return false;
3534 if (ldtr.type != 2)
3535 return false;
3536 if (!ldtr.present)
3537 return false;
3538
3539 return true;
3540}
3541
3542static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3543{
3544 struct kvm_segment cs, ss;
3545
3546 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3547 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3548
3549 return ((cs.selector & SELECTOR_RPL_MASK) ==
3550 (ss.selector & SELECTOR_RPL_MASK));
3551}
3552
3553/*
3554 * Check if guest state is valid. Returns true if valid, false if
3555 * not.
3556 * We assume that registers are always usable
3557 */
3558static bool guest_state_valid(struct kvm_vcpu *vcpu)
3559{
3560 if (enable_unrestricted_guest)
3561 return true;
3562
3563 /* real mode guest state checks */
3564 if (!is_protmode(vcpu)) {
3565 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3566 return false;
3567 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3568 return false;
3569 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3570 return false;
3571 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3572 return false;
3573 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3574 return false;
3575 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3576 return false;
3577 } else {
3578 /* protected mode guest state checks */
3579 if (!cs_ss_rpl_check(vcpu))
3580 return false;
3581 if (!code_segment_valid(vcpu))
3582 return false;
3583 if (!stack_segment_valid(vcpu))
3584 return false;
3585 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3586 return false;
3587 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3588 return false;
3589 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3590 return false;
3591 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3592 return false;
3593 if (!tr_valid(vcpu))
3594 return false;
3595 if (!ldtr_valid(vcpu))
3596 return false;
3597 }
3598 /* TODO:
3599 * - Add checks on RIP
3600 * - Add checks on RFLAGS
3601 */
3602
3603 return true;
3604}
3605
3606static int init_rmode_tss(struct kvm *kvm)
3607{
3608 gfn_t fn;
3609 u16 data = 0;
3610 int r, idx, ret = 0;
3611
3612 idx = srcu_read_lock(&kvm->srcu);
3613 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3614 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3615 if (r < 0)
3616 goto out;
3617 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3618 r = kvm_write_guest_page(kvm, fn++, &data,
3619 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3620 if (r < 0)
3621 goto out;
3622 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3623 if (r < 0)
3624 goto out;
3625 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3626 if (r < 0)
3627 goto out;
3628 data = ~0;
3629 r = kvm_write_guest_page(kvm, fn, &data,
3630 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3631 sizeof(u8));
3632 if (r < 0)
3633 goto out;
3634
3635 ret = 1;
3636out:
3637 srcu_read_unlock(&kvm->srcu, idx);
3638 return ret;
3639}
3640
3641static int init_rmode_identity_map(struct kvm *kvm)
3642{
3643 int i, idx, r, ret;
3644 pfn_t identity_map_pfn;
3645 u32 tmp;
3646
3647 if (!enable_ept)
3648 return 1;
3649 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3650 printk(KERN_ERR "EPT: identity-mapping pagetable "
3651 "haven't been allocated!\n");
3652 return 0;
3653 }
3654 if (likely(kvm->arch.ept_identity_pagetable_done))
3655 return 1;
3656 ret = 0;
3657 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3658 idx = srcu_read_lock(&kvm->srcu);
3659 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3660 if (r < 0)
3661 goto out;
3662 /* Set up identity-mapping pagetable for EPT in real mode */
3663 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3664 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3665 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3666 r = kvm_write_guest_page(kvm, identity_map_pfn,
3667 &tmp, i * sizeof(tmp), sizeof(tmp));
3668 if (r < 0)
3669 goto out;
3670 }
3671 kvm->arch.ept_identity_pagetable_done = true;
3672 ret = 1;
3673out:
3674 srcu_read_unlock(&kvm->srcu, idx);
3675 return ret;
3676}
3677
3678static void seg_setup(int seg)
3679{
3680 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3681 unsigned int ar;
3682
3683 vmcs_write16(sf->selector, 0);
3684 vmcs_writel(sf->base, 0);
3685 vmcs_write32(sf->limit, 0xffff);
3686 ar = 0x93;
3687 if (seg == VCPU_SREG_CS)
3688 ar |= 0x08; /* code segment */
3689
3690 vmcs_write32(sf->ar_bytes, ar);
3691}
3692
3693static int alloc_apic_access_page(struct kvm *kvm)
3694{
3695 struct page *page;
3696 struct kvm_userspace_memory_region kvm_userspace_mem;
3697 int r = 0;
3698
3699 mutex_lock(&kvm->slots_lock);
3700 if (kvm->arch.apic_access_page)
3701 goto out;
3702 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3703 kvm_userspace_mem.flags = 0;
3704 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3705 kvm_userspace_mem.memory_size = PAGE_SIZE;
3706 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3707 if (r)
3708 goto out;
3709
3710 page = gfn_to_page(kvm, 0xfee00);
3711 if (is_error_page(page)) {
3712 r = -EFAULT;
3713 goto out;
3714 }
3715
3716 kvm->arch.apic_access_page = page;
3717out:
3718 mutex_unlock(&kvm->slots_lock);
3719 return r;
3720}
3721
3722static int alloc_identity_pagetable(struct kvm *kvm)
3723{
3724 struct page *page;
3725 struct kvm_userspace_memory_region kvm_userspace_mem;
3726 int r = 0;
3727
3728 mutex_lock(&kvm->slots_lock);
3729 if (kvm->arch.ept_identity_pagetable)
3730 goto out;
3731 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3732 kvm_userspace_mem.flags = 0;
3733 kvm_userspace_mem.guest_phys_addr =
3734 kvm->arch.ept_identity_map_addr;
3735 kvm_userspace_mem.memory_size = PAGE_SIZE;
3736 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3737 if (r)
3738 goto out;
3739
3740 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3741 if (is_error_page(page)) {
3742 r = -EFAULT;
3743 goto out;
3744 }
3745
3746 kvm->arch.ept_identity_pagetable = page;
3747out:
3748 mutex_unlock(&kvm->slots_lock);
3749 return r;
3750}
3751
3752static void allocate_vpid(struct vcpu_vmx *vmx)
3753{
3754 int vpid;
3755
3756 vmx->vpid = 0;
3757 if (!enable_vpid)
3758 return;
3759 spin_lock(&vmx_vpid_lock);
3760 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3761 if (vpid < VMX_NR_VPIDS) {
3762 vmx->vpid = vpid;
3763 __set_bit(vpid, vmx_vpid_bitmap);
3764 }
3765 spin_unlock(&vmx_vpid_lock);
3766}
3767
3768static void free_vpid(struct vcpu_vmx *vmx)
3769{
3770 if (!enable_vpid)
3771 return;
3772 spin_lock(&vmx_vpid_lock);
3773 if (vmx->vpid != 0)
3774 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3775 spin_unlock(&vmx_vpid_lock);
3776}
3777
3778#define MSR_TYPE_R 1
3779#define MSR_TYPE_W 2
3780static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3781 u32 msr, int type)
3782{
3783 int f = sizeof(unsigned long);
3784
3785 if (!cpu_has_vmx_msr_bitmap())
3786 return;
3787
3788 /*
3789 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3790 * have the write-low and read-high bitmap offsets the wrong way round.
3791 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3792 */
3793 if (msr <= 0x1fff) {
3794 if (type & MSR_TYPE_R)
3795 /* read-low */
3796 __clear_bit(msr, msr_bitmap + 0x000 / f);
3797
3798 if (type & MSR_TYPE_W)
3799 /* write-low */
3800 __clear_bit(msr, msr_bitmap + 0x800 / f);
3801
3802 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3803 msr &= 0x1fff;
3804 if (type & MSR_TYPE_R)
3805 /* read-high */
3806 __clear_bit(msr, msr_bitmap + 0x400 / f);
3807
3808 if (type & MSR_TYPE_W)
3809 /* write-high */
3810 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3811
3812 }
3813}
3814
3815static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3816 u32 msr, int type)
3817{
3818 int f = sizeof(unsigned long);
3819
3820 if (!cpu_has_vmx_msr_bitmap())
3821 return;
3822
3823 /*
3824 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3825 * have the write-low and read-high bitmap offsets the wrong way round.
3826 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3827 */
3828 if (msr <= 0x1fff) {
3829 if (type & MSR_TYPE_R)
3830 /* read-low */
3831 __set_bit(msr, msr_bitmap + 0x000 / f);
3832
3833 if (type & MSR_TYPE_W)
3834 /* write-low */
3835 __set_bit(msr, msr_bitmap + 0x800 / f);
3836
3837 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3838 msr &= 0x1fff;
3839 if (type & MSR_TYPE_R)
3840 /* read-high */
3841 __set_bit(msr, msr_bitmap + 0x400 / f);
3842
3843 if (type & MSR_TYPE_W)
3844 /* write-high */
3845 __set_bit(msr, msr_bitmap + 0xc00 / f);
3846
3847 }
3848}
3849
3850static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3851{
3852 if (!longmode_only)
3853 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3854 msr, MSR_TYPE_R | MSR_TYPE_W);
3855 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3856 msr, MSR_TYPE_R | MSR_TYPE_W);
3857}
3858
3859static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3860{
3861 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3862 msr, MSR_TYPE_R);
3863 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3864 msr, MSR_TYPE_R);
3865}
3866
3867static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3868{
3869 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3870 msr, MSR_TYPE_R);
3871 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3872 msr, MSR_TYPE_R);
3873}
3874
3875static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3876{
3877 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3878 msr, MSR_TYPE_W);
3879 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3880 msr, MSR_TYPE_W);
3881}
3882
3883/*
3884 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3885 * will not change in the lifetime of the guest.
3886 * Note that host-state that does change is set elsewhere. E.g., host-state
3887 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3888 */
3889static void vmx_set_constant_host_state(void)
3890{
3891 u32 low32, high32;
3892 unsigned long tmpl;
3893 struct desc_ptr dt;
3894
3895 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
3896 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3897 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3898
3899 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3900#ifdef CONFIG_X86_64
3901 /*
3902 * Load null selectors, so we can avoid reloading them in
3903 * __vmx_load_host_state(), in case userspace uses the null selectors
3904 * too (the expected case).
3905 */
3906 vmcs_write16(HOST_DS_SELECTOR, 0);
3907 vmcs_write16(HOST_ES_SELECTOR, 0);
3908#else
3909 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3910 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3911#endif
3912 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3913 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3914
3915 native_store_idt(&dt);
3916 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3917
3918 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3919
3920 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3921 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3922 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3923 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3924
3925 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3926 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3927 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3928 }
3929}
3930
3931static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3932{
3933 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3934 if (enable_ept)
3935 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3936 if (is_guest_mode(&vmx->vcpu))
3937 vmx->vcpu.arch.cr4_guest_owned_bits &=
3938 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3939 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3940}
3941
3942static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3943{
3944 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3945 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3946 exec_control &= ~CPU_BASED_TPR_SHADOW;
3947#ifdef CONFIG_X86_64
3948 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3949 CPU_BASED_CR8_LOAD_EXITING;
3950#endif
3951 }
3952 if (!enable_ept)
3953 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3954 CPU_BASED_CR3_LOAD_EXITING |
3955 CPU_BASED_INVLPG_EXITING;
3956 return exec_control;
3957}
3958
3959static int vmx_vm_has_apicv(struct kvm *kvm)
3960{
3961 return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3962}
3963
3964static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3965{
3966 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3967 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3968 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3969 if (vmx->vpid == 0)
3970 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3971 if (!enable_ept) {
3972 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3973 enable_unrestricted_guest = 0;
3974 /* Enable INVPCID for non-ept guests may cause performance regression. */
3975 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3976 }
3977 if (!enable_unrestricted_guest)
3978 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3979 if (!ple_gap)
3980 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3981 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3982 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3983 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3984 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
3985 return exec_control;
3986}
3987
3988static void ept_set_mmio_spte_mask(void)
3989{
3990 /*
3991 * EPT Misconfigurations can be generated if the value of bits 2:0
3992 * of an EPT paging-structure entry is 110b (write/execute).
3993 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3994 * spte.
3995 */
3996 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3997}
3998
3999/*
4000 * Sets up the vmcs for emulated real mode.
4001 */
4002static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4003{
4004#ifdef CONFIG_X86_64
4005 unsigned long a;
4006#endif
4007 int i;
4008
4009 /* I/O */
4010 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4011 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4012
4013 if (cpu_has_vmx_msr_bitmap())
4014 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4015
4016 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4017
4018 /* Control */
4019 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4020 vmcs_config.pin_based_exec_ctrl);
4021
4022 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4023
4024 if (cpu_has_secondary_exec_ctrls()) {
4025 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4026 vmx_secondary_exec_control(vmx));
4027 }
4028
4029 if (enable_apicv_reg_vid) {
4030 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4031 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4032 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4033 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4034
4035 vmcs_write16(GUEST_INTR_STATUS, 0);
4036 }
4037
4038 if (ple_gap) {
4039 vmcs_write32(PLE_GAP, ple_gap);
4040 vmcs_write32(PLE_WINDOW, ple_window);
4041 }
4042
4043 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4044 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4045 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4046
4047 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4048 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4049 vmx_set_constant_host_state();
4050#ifdef CONFIG_X86_64
4051 rdmsrl(MSR_FS_BASE, a);
4052 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4053 rdmsrl(MSR_GS_BASE, a);
4054 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4055#else
4056 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4057 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4058#endif
4059
4060 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4061 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4062 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4063 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4064 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4065
4066 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4067 u32 msr_low, msr_high;
4068 u64 host_pat;
4069 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4070 host_pat = msr_low | ((u64) msr_high << 32);
4071 /* Write the default value follow host pat */
4072 vmcs_write64(GUEST_IA32_PAT, host_pat);
4073 /* Keep arch.pat sync with GUEST_IA32_PAT */
4074 vmx->vcpu.arch.pat = host_pat;
4075 }
4076
4077 for (i = 0; i < NR_VMX_MSR; ++i) {
4078 u32 index = vmx_msr_index[i];
4079 u32 data_low, data_high;
4080 int j = vmx->nmsrs;
4081
4082 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4083 continue;
4084 if (wrmsr_safe(index, data_low, data_high) < 0)
4085 continue;
4086 vmx->guest_msrs[j].index = i;
4087 vmx->guest_msrs[j].data = 0;
4088 vmx->guest_msrs[j].mask = -1ull;
4089 ++vmx->nmsrs;
4090 }
4091
4092 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
4093
4094 /* 22.2.1, 20.8.1 */
4095 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4096
4097 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4098 set_cr4_guest_host_mask(vmx);
4099
4100 return 0;
4101}
4102
4103static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4104{
4105 struct vcpu_vmx *vmx = to_vmx(vcpu);
4106 u64 msr;
4107 int ret;
4108
4109 vmx->rmode.vm86_active = 0;
4110
4111 vmx->soft_vnmi_blocked = 0;
4112
4113 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4114 kvm_set_cr8(&vmx->vcpu, 0);
4115 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4116 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4117 msr |= MSR_IA32_APICBASE_BSP;
4118 kvm_set_apic_base(&vmx->vcpu, msr);
4119
4120 vmx_segment_cache_clear(vmx);
4121
4122 seg_setup(VCPU_SREG_CS);
4123 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4124 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4125 else {
4126 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4127 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
4128 }
4129
4130 seg_setup(VCPU_SREG_DS);
4131 seg_setup(VCPU_SREG_ES);
4132 seg_setup(VCPU_SREG_FS);
4133 seg_setup(VCPU_SREG_GS);
4134 seg_setup(VCPU_SREG_SS);
4135
4136 vmcs_write16(GUEST_TR_SELECTOR, 0);
4137 vmcs_writel(GUEST_TR_BASE, 0);
4138 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4139 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4140
4141 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4142 vmcs_writel(GUEST_LDTR_BASE, 0);
4143 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4144 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4145
4146 vmcs_write32(GUEST_SYSENTER_CS, 0);
4147 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4148 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4149
4150 vmcs_writel(GUEST_RFLAGS, 0x02);
4151 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4152 kvm_rip_write(vcpu, 0xfff0);
4153 else
4154 kvm_rip_write(vcpu, 0);
4155
4156 vmcs_writel(GUEST_GDTR_BASE, 0);
4157 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4158
4159 vmcs_writel(GUEST_IDTR_BASE, 0);
4160 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4161
4162 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4163 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4164 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4165
4166 /* Special registers */
4167 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4168
4169 setup_msrs(vmx);
4170
4171 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4172
4173 if (cpu_has_vmx_tpr_shadow()) {
4174 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4175 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4176 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4177 __pa(vmx->vcpu.arch.apic->regs));
4178 vmcs_write32(TPR_THRESHOLD, 0);
4179 }
4180
4181 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4182 vmcs_write64(APIC_ACCESS_ADDR,
4183 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4184
4185 if (vmx->vpid != 0)
4186 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4187
4188 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4189 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4190 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4191 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4192 vmx_set_cr4(&vmx->vcpu, 0);
4193 vmx_set_efer(&vmx->vcpu, 0);
4194 vmx_fpu_activate(&vmx->vcpu);
4195 update_exception_bitmap(&vmx->vcpu);
4196
4197 vpid_sync_context(vmx);
4198
4199 ret = 0;
4200
4201 return ret;
4202}
4203
4204/*
4205 * In nested virtualization, check if L1 asked to exit on external interrupts.
4206 * For most existing hypervisors, this will always return true.
4207 */
4208static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4209{
4210 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4211 PIN_BASED_EXT_INTR_MASK;
4212}
4213
4214static void enable_irq_window(struct kvm_vcpu *vcpu)
4215{
4216 u32 cpu_based_vm_exec_control;
4217 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4218 /*
4219 * We get here if vmx_interrupt_allowed() said we can't
4220 * inject to L1 now because L2 must run. Ask L2 to exit
4221 * right after entry, so we can inject to L1 more promptly.
4222 */
4223 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4224 return;
4225 }
4226
4227 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4228 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4230}
4231
4232static void enable_nmi_window(struct kvm_vcpu *vcpu)
4233{
4234 u32 cpu_based_vm_exec_control;
4235
4236 if (!cpu_has_virtual_nmis()) {
4237 enable_irq_window(vcpu);
4238 return;
4239 }
4240
4241 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4242 enable_irq_window(vcpu);
4243 return;
4244 }
4245 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4246 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4247 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4248}
4249
4250static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4251{
4252 struct vcpu_vmx *vmx = to_vmx(vcpu);
4253 uint32_t intr;
4254 int irq = vcpu->arch.interrupt.nr;
4255
4256 trace_kvm_inj_virq(irq);
4257
4258 ++vcpu->stat.irq_injections;
4259 if (vmx->rmode.vm86_active) {
4260 int inc_eip = 0;
4261 if (vcpu->arch.interrupt.soft)
4262 inc_eip = vcpu->arch.event_exit_inst_len;
4263 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4264 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4265 return;
4266 }
4267 intr = irq | INTR_INFO_VALID_MASK;
4268 if (vcpu->arch.interrupt.soft) {
4269 intr |= INTR_TYPE_SOFT_INTR;
4270 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4271 vmx->vcpu.arch.event_exit_inst_len);
4272 } else
4273 intr |= INTR_TYPE_EXT_INTR;
4274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4275}
4276
4277static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4278{
4279 struct vcpu_vmx *vmx = to_vmx(vcpu);
4280
4281 if (is_guest_mode(vcpu))
4282 return;
4283
4284 if (!cpu_has_virtual_nmis()) {
4285 /*
4286 * Tracking the NMI-blocked state in software is built upon
4287 * finding the next open IRQ window. This, in turn, depends on
4288 * well-behaving guests: They have to keep IRQs disabled at
4289 * least as long as the NMI handler runs. Otherwise we may
4290 * cause NMI nesting, maybe breaking the guest. But as this is
4291 * highly unlikely, we can live with the residual risk.
4292 */
4293 vmx->soft_vnmi_blocked = 1;
4294 vmx->vnmi_blocked_time = 0;
4295 }
4296
4297 ++vcpu->stat.nmi_injections;
4298 vmx->nmi_known_unmasked = false;
4299 if (vmx->rmode.vm86_active) {
4300 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4302 return;
4303 }
4304 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4305 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4306}
4307
4308static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4309{
4310 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4311 return 0;
4312
4313 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4314 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4315 | GUEST_INTR_STATE_NMI));
4316}
4317
4318static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4319{
4320 if (!cpu_has_virtual_nmis())
4321 return to_vmx(vcpu)->soft_vnmi_blocked;
4322 if (to_vmx(vcpu)->nmi_known_unmasked)
4323 return false;
4324 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4325}
4326
4327static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4328{
4329 struct vcpu_vmx *vmx = to_vmx(vcpu);
4330
4331 if (!cpu_has_virtual_nmis()) {
4332 if (vmx->soft_vnmi_blocked != masked) {
4333 vmx->soft_vnmi_blocked = masked;
4334 vmx->vnmi_blocked_time = 0;
4335 }
4336 } else {
4337 vmx->nmi_known_unmasked = !masked;
4338 if (masked)
4339 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4340 GUEST_INTR_STATE_NMI);
4341 else
4342 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4343 GUEST_INTR_STATE_NMI);
4344 }
4345}
4346
4347static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4348{
4349 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4350 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4351 if (to_vmx(vcpu)->nested.nested_run_pending ||
4352 (vmcs12->idt_vectoring_info_field &
4353 VECTORING_INFO_VALID_MASK))
4354 return 0;
4355 nested_vmx_vmexit(vcpu);
4356 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4357 vmcs12->vm_exit_intr_info = 0;
4358 /* fall through to normal code, but now in L1, not L2 */
4359 }
4360
4361 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4362 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4363 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4364}
4365
4366static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4367{
4368 int ret;
4369 struct kvm_userspace_memory_region tss_mem = {
4370 .slot = TSS_PRIVATE_MEMSLOT,
4371 .guest_phys_addr = addr,
4372 .memory_size = PAGE_SIZE * 3,
4373 .flags = 0,
4374 };
4375
4376 ret = kvm_set_memory_region(kvm, &tss_mem);
4377 if (ret)
4378 return ret;
4379 kvm->arch.tss_addr = addr;
4380 if (!init_rmode_tss(kvm))
4381 return -ENOMEM;
4382
4383 return 0;
4384}
4385
4386static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4387{
4388 switch (vec) {
4389 case BP_VECTOR:
4390 /*
4391 * Update instruction length as we may reinject the exception
4392 * from user space while in guest debugging mode.
4393 */
4394 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4395 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4396 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4397 return false;
4398 /* fall through */
4399 case DB_VECTOR:
4400 if (vcpu->guest_debug &
4401 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4402 return false;
4403 /* fall through */
4404 case DE_VECTOR:
4405 case OF_VECTOR:
4406 case BR_VECTOR:
4407 case UD_VECTOR:
4408 case DF_VECTOR:
4409 case SS_VECTOR:
4410 case GP_VECTOR:
4411 case MF_VECTOR:
4412 return true;
4413 break;
4414 }
4415 return false;
4416}
4417
4418static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4419 int vec, u32 err_code)
4420{
4421 /*
4422 * Instruction with address size override prefix opcode 0x67
4423 * Cause the #SS fault with 0 error code in VM86 mode.
4424 */
4425 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4426 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4427 if (vcpu->arch.halt_request) {
4428 vcpu->arch.halt_request = 0;
4429 return kvm_emulate_halt(vcpu);
4430 }
4431 return 1;
4432 }
4433 return 0;
4434 }
4435
4436 /*
4437 * Forward all other exceptions that are valid in real mode.
4438 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4439 * the required debugging infrastructure rework.
4440 */
4441 kvm_queue_exception(vcpu, vec);
4442 return 1;
4443}
4444
4445/*
4446 * Trigger machine check on the host. We assume all the MSRs are already set up
4447 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4448 * We pass a fake environment to the machine check handler because we want
4449 * the guest to be always treated like user space, no matter what context
4450 * it used internally.
4451 */
4452static void kvm_machine_check(void)
4453{
4454#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4455 struct pt_regs regs = {
4456 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4457 .flags = X86_EFLAGS_IF,
4458 };
4459
4460 do_machine_check(&regs, 0);
4461#endif
4462}
4463
4464static int handle_machine_check(struct kvm_vcpu *vcpu)
4465{
4466 /* already handled by vcpu_run */
4467 return 1;
4468}
4469
4470static int handle_exception(struct kvm_vcpu *vcpu)
4471{
4472 struct vcpu_vmx *vmx = to_vmx(vcpu);
4473 struct kvm_run *kvm_run = vcpu->run;
4474 u32 intr_info, ex_no, error_code;
4475 unsigned long cr2, rip, dr6;
4476 u32 vect_info;
4477 enum emulation_result er;
4478
4479 vect_info = vmx->idt_vectoring_info;
4480 intr_info = vmx->exit_intr_info;
4481
4482 if (is_machine_check(intr_info))
4483 return handle_machine_check(vcpu);
4484
4485 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4486 return 1; /* already handled by vmx_vcpu_run() */
4487
4488 if (is_no_device(intr_info)) {
4489 vmx_fpu_activate(vcpu);
4490 return 1;
4491 }
4492
4493 if (is_invalid_opcode(intr_info)) {
4494 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4495 if (er != EMULATE_DONE)
4496 kvm_queue_exception(vcpu, UD_VECTOR);
4497 return 1;
4498 }
4499
4500 error_code = 0;
4501 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4502 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4503
4504 /*
4505 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4506 * MMIO, it is better to report an internal error.
4507 * See the comments in vmx_handle_exit.
4508 */
4509 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4510 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4511 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4512 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4513 vcpu->run->internal.ndata = 2;
4514 vcpu->run->internal.data[0] = vect_info;
4515 vcpu->run->internal.data[1] = intr_info;
4516 return 0;
4517 }
4518
4519 if (is_page_fault(intr_info)) {
4520 /* EPT won't cause page fault directly */
4521 BUG_ON(enable_ept);
4522 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4523 trace_kvm_page_fault(cr2, error_code);
4524
4525 if (kvm_event_needs_reinjection(vcpu))
4526 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4527 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4528 }
4529
4530 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4531
4532 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4533 return handle_rmode_exception(vcpu, ex_no, error_code);
4534
4535 switch (ex_no) {
4536 case DB_VECTOR:
4537 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4538 if (!(vcpu->guest_debug &
4539 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4540 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4541 kvm_queue_exception(vcpu, DB_VECTOR);
4542 return 1;
4543 }
4544 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4545 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4546 /* fall through */
4547 case BP_VECTOR:
4548 /*
4549 * Update instruction length as we may reinject #BP from
4550 * user space while in guest debugging mode. Reading it for
4551 * #DB as well causes no harm, it is not used in that case.
4552 */
4553 vmx->vcpu.arch.event_exit_inst_len =
4554 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4555 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4556 rip = kvm_rip_read(vcpu);
4557 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4558 kvm_run->debug.arch.exception = ex_no;
4559 break;
4560 default:
4561 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4562 kvm_run->ex.exception = ex_no;
4563 kvm_run->ex.error_code = error_code;
4564 break;
4565 }
4566 return 0;
4567}
4568
4569static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4570{
4571 ++vcpu->stat.irq_exits;
4572 return 1;
4573}
4574
4575static int handle_triple_fault(struct kvm_vcpu *vcpu)
4576{
4577 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4578 return 0;
4579}
4580
4581static int handle_io(struct kvm_vcpu *vcpu)
4582{
4583 unsigned long exit_qualification;
4584 int size, in, string;
4585 unsigned port;
4586
4587 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4588 string = (exit_qualification & 16) != 0;
4589 in = (exit_qualification & 8) != 0;
4590
4591 ++vcpu->stat.io_exits;
4592
4593 if (string || in)
4594 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4595
4596 port = exit_qualification >> 16;
4597 size = (exit_qualification & 7) + 1;
4598 skip_emulated_instruction(vcpu);
4599
4600 return kvm_fast_pio_out(vcpu, size, port);
4601}
4602
4603static void
4604vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4605{
4606 /*
4607 * Patch in the VMCALL instruction:
4608 */
4609 hypercall[0] = 0x0f;
4610 hypercall[1] = 0x01;
4611 hypercall[2] = 0xc1;
4612}
4613
4614/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4615static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4616{
4617 if (is_guest_mode(vcpu)) {
4618 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4619 unsigned long orig_val = val;
4620
4621 /*
4622 * We get here when L2 changed cr0 in a way that did not change
4623 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4624 * but did change L0 shadowed bits. So we first calculate the
4625 * effective cr0 value that L1 would like to write into the
4626 * hardware. It consists of the L2-owned bits from the new
4627 * value combined with the L1-owned bits from L1's guest_cr0.
4628 */
4629 val = (val & ~vmcs12->cr0_guest_host_mask) |
4630 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4631
4632 /* TODO: will have to take unrestricted guest mode into
4633 * account */
4634 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
4635 return 1;
4636
4637 if (kvm_set_cr0(vcpu, val))
4638 return 1;
4639 vmcs_writel(CR0_READ_SHADOW, orig_val);
4640 return 0;
4641 } else {
4642 if (to_vmx(vcpu)->nested.vmxon &&
4643 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4644 return 1;
4645 return kvm_set_cr0(vcpu, val);
4646 }
4647}
4648
4649static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4650{
4651 if (is_guest_mode(vcpu)) {
4652 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4653 unsigned long orig_val = val;
4654
4655 /* analogously to handle_set_cr0 */
4656 val = (val & ~vmcs12->cr4_guest_host_mask) |
4657 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4658 if (kvm_set_cr4(vcpu, val))
4659 return 1;
4660 vmcs_writel(CR4_READ_SHADOW, orig_val);
4661 return 0;
4662 } else
4663 return kvm_set_cr4(vcpu, val);
4664}
4665
4666/* called to set cr0 as approriate for clts instruction exit. */
4667static void handle_clts(struct kvm_vcpu *vcpu)
4668{
4669 if (is_guest_mode(vcpu)) {
4670 /*
4671 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4672 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4673 * just pretend it's off (also in arch.cr0 for fpu_activate).
4674 */
4675 vmcs_writel(CR0_READ_SHADOW,
4676 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4677 vcpu->arch.cr0 &= ~X86_CR0_TS;
4678 } else
4679 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4680}
4681
4682static int handle_cr(struct kvm_vcpu *vcpu)
4683{
4684 unsigned long exit_qualification, val;
4685 int cr;
4686 int reg;
4687 int err;
4688
4689 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4690 cr = exit_qualification & 15;
4691 reg = (exit_qualification >> 8) & 15;
4692 switch ((exit_qualification >> 4) & 3) {
4693 case 0: /* mov to cr */
4694 val = kvm_register_read(vcpu, reg);
4695 trace_kvm_cr_write(cr, val);
4696 switch (cr) {
4697 case 0:
4698 err = handle_set_cr0(vcpu, val);
4699 kvm_complete_insn_gp(vcpu, err);
4700 return 1;
4701 case 3:
4702 err = kvm_set_cr3(vcpu, val);
4703 kvm_complete_insn_gp(vcpu, err);
4704 return 1;
4705 case 4:
4706 err = handle_set_cr4(vcpu, val);
4707 kvm_complete_insn_gp(vcpu, err);
4708 return 1;
4709 case 8: {
4710 u8 cr8_prev = kvm_get_cr8(vcpu);
4711 u8 cr8 = kvm_register_read(vcpu, reg);
4712 err = kvm_set_cr8(vcpu, cr8);
4713 kvm_complete_insn_gp(vcpu, err);
4714 if (irqchip_in_kernel(vcpu->kvm))
4715 return 1;
4716 if (cr8_prev <= cr8)
4717 return 1;
4718 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4719 return 0;
4720 }
4721 }
4722 break;
4723 case 2: /* clts */
4724 handle_clts(vcpu);
4725 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4726 skip_emulated_instruction(vcpu);
4727 vmx_fpu_activate(vcpu);
4728 return 1;
4729 case 1: /*mov from cr*/
4730 switch (cr) {
4731 case 3:
4732 val = kvm_read_cr3(vcpu);
4733 kvm_register_write(vcpu, reg, val);
4734 trace_kvm_cr_read(cr, val);
4735 skip_emulated_instruction(vcpu);
4736 return 1;
4737 case 8:
4738 val = kvm_get_cr8(vcpu);
4739 kvm_register_write(vcpu, reg, val);
4740 trace_kvm_cr_read(cr, val);
4741 skip_emulated_instruction(vcpu);
4742 return 1;
4743 }
4744 break;
4745 case 3: /* lmsw */
4746 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4747 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4748 kvm_lmsw(vcpu, val);
4749
4750 skip_emulated_instruction(vcpu);
4751 return 1;
4752 default:
4753 break;
4754 }
4755 vcpu->run->exit_reason = 0;
4756 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4757 (int)(exit_qualification >> 4) & 3, cr);
4758 return 0;
4759}
4760
4761static int handle_dr(struct kvm_vcpu *vcpu)
4762{
4763 unsigned long exit_qualification;
4764 int dr, reg;
4765
4766 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4767 if (!kvm_require_cpl(vcpu, 0))
4768 return 1;
4769 dr = vmcs_readl(GUEST_DR7);
4770 if (dr & DR7_GD) {
4771 /*
4772 * As the vm-exit takes precedence over the debug trap, we
4773 * need to emulate the latter, either for the host or the
4774 * guest debugging itself.
4775 */
4776 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4777 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4778 vcpu->run->debug.arch.dr7 = dr;
4779 vcpu->run->debug.arch.pc =
4780 vmcs_readl(GUEST_CS_BASE) +
4781 vmcs_readl(GUEST_RIP);
4782 vcpu->run->debug.arch.exception = DB_VECTOR;
4783 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4784 return 0;
4785 } else {
4786 vcpu->arch.dr7 &= ~DR7_GD;
4787 vcpu->arch.dr6 |= DR6_BD;
4788 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4789 kvm_queue_exception(vcpu, DB_VECTOR);
4790 return 1;
4791 }
4792 }
4793
4794 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4795 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4796 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4797 if (exit_qualification & TYPE_MOV_FROM_DR) {
4798 unsigned long val;
4799 if (!kvm_get_dr(vcpu, dr, &val))
4800 kvm_register_write(vcpu, reg, val);
4801 } else
4802 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4803 skip_emulated_instruction(vcpu);
4804 return 1;
4805}
4806
4807static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4808{
4809 vmcs_writel(GUEST_DR7, val);
4810}
4811
4812static int handle_cpuid(struct kvm_vcpu *vcpu)
4813{
4814 kvm_emulate_cpuid(vcpu);
4815 return 1;
4816}
4817
4818static int handle_rdmsr(struct kvm_vcpu *vcpu)
4819{
4820 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4821 u64 data;
4822
4823 if (vmx_get_msr(vcpu, ecx, &data)) {
4824 trace_kvm_msr_read_ex(ecx);
4825 kvm_inject_gp(vcpu, 0);
4826 return 1;
4827 }
4828
4829 trace_kvm_msr_read(ecx, data);
4830
4831 /* FIXME: handling of bits 32:63 of rax, rdx */
4832 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4833 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4834 skip_emulated_instruction(vcpu);
4835 return 1;
4836}
4837
4838static int handle_wrmsr(struct kvm_vcpu *vcpu)
4839{
4840 struct msr_data msr;
4841 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4842 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4843 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4844
4845 msr.data = data;
4846 msr.index = ecx;
4847 msr.host_initiated = false;
4848 if (vmx_set_msr(vcpu, &msr) != 0) {
4849 trace_kvm_msr_write_ex(ecx, data);
4850 kvm_inject_gp(vcpu, 0);
4851 return 1;
4852 }
4853
4854 trace_kvm_msr_write(ecx, data);
4855 skip_emulated_instruction(vcpu);
4856 return 1;
4857}
4858
4859static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4860{
4861 kvm_make_request(KVM_REQ_EVENT, vcpu);
4862 return 1;
4863}
4864
4865static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4866{
4867 u32 cpu_based_vm_exec_control;
4868
4869 /* clear pending irq */
4870 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4871 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4872 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4873
4874 kvm_make_request(KVM_REQ_EVENT, vcpu);
4875
4876 ++vcpu->stat.irq_window_exits;
4877
4878 /*
4879 * If the user space waits to inject interrupts, exit as soon as
4880 * possible
4881 */
4882 if (!irqchip_in_kernel(vcpu->kvm) &&
4883 vcpu->run->request_interrupt_window &&
4884 !kvm_cpu_has_interrupt(vcpu)) {
4885 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4886 return 0;
4887 }
4888 return 1;
4889}
4890
4891static int handle_halt(struct kvm_vcpu *vcpu)
4892{
4893 skip_emulated_instruction(vcpu);
4894 return kvm_emulate_halt(vcpu);
4895}
4896
4897static int handle_vmcall(struct kvm_vcpu *vcpu)
4898{
4899 skip_emulated_instruction(vcpu);
4900 kvm_emulate_hypercall(vcpu);
4901 return 1;
4902}
4903
4904static int handle_invd(struct kvm_vcpu *vcpu)
4905{
4906 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4907}
4908
4909static int handle_invlpg(struct kvm_vcpu *vcpu)
4910{
4911 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4912
4913 kvm_mmu_invlpg(vcpu, exit_qualification);
4914 skip_emulated_instruction(vcpu);
4915 return 1;
4916}
4917
4918static int handle_rdpmc(struct kvm_vcpu *vcpu)
4919{
4920 int err;
4921
4922 err = kvm_rdpmc(vcpu);
4923 kvm_complete_insn_gp(vcpu, err);
4924
4925 return 1;
4926}
4927
4928static int handle_wbinvd(struct kvm_vcpu *vcpu)
4929{
4930 skip_emulated_instruction(vcpu);
4931 kvm_emulate_wbinvd(vcpu);
4932 return 1;
4933}
4934
4935static int handle_xsetbv(struct kvm_vcpu *vcpu)
4936{
4937 u64 new_bv = kvm_read_edx_eax(vcpu);
4938 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4939
4940 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4941 skip_emulated_instruction(vcpu);
4942 return 1;
4943}
4944
4945static int handle_apic_access(struct kvm_vcpu *vcpu)
4946{
4947 if (likely(fasteoi)) {
4948 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4949 int access_type, offset;
4950
4951 access_type = exit_qualification & APIC_ACCESS_TYPE;
4952 offset = exit_qualification & APIC_ACCESS_OFFSET;
4953 /*
4954 * Sane guest uses MOV to write EOI, with written value
4955 * not cared. So make a short-circuit here by avoiding
4956 * heavy instruction emulation.
4957 */
4958 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4959 (offset == APIC_EOI)) {
4960 kvm_lapic_set_eoi(vcpu);
4961 skip_emulated_instruction(vcpu);
4962 return 1;
4963 }
4964 }
4965 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4966}
4967
4968static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4969{
4970 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4971 int vector = exit_qualification & 0xff;
4972
4973 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4974 kvm_apic_set_eoi_accelerated(vcpu, vector);
4975 return 1;
4976}
4977
4978static int handle_apic_write(struct kvm_vcpu *vcpu)
4979{
4980 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4981 u32 offset = exit_qualification & 0xfff;
4982
4983 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4984 kvm_apic_write_nodecode(vcpu, offset);
4985 return 1;
4986}
4987
4988static int handle_task_switch(struct kvm_vcpu *vcpu)
4989{
4990 struct vcpu_vmx *vmx = to_vmx(vcpu);
4991 unsigned long exit_qualification;
4992 bool has_error_code = false;
4993 u32 error_code = 0;
4994 u16 tss_selector;
4995 int reason, type, idt_v, idt_index;
4996
4997 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4998 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4999 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5000
5001 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5002
5003 reason = (u32)exit_qualification >> 30;
5004 if (reason == TASK_SWITCH_GATE && idt_v) {
5005 switch (type) {
5006 case INTR_TYPE_NMI_INTR:
5007 vcpu->arch.nmi_injected = false;
5008 vmx_set_nmi_mask(vcpu, true);
5009 break;
5010 case INTR_TYPE_EXT_INTR:
5011 case INTR_TYPE_SOFT_INTR:
5012 kvm_clear_interrupt_queue(vcpu);
5013 break;
5014 case INTR_TYPE_HARD_EXCEPTION:
5015 if (vmx->idt_vectoring_info &
5016 VECTORING_INFO_DELIVER_CODE_MASK) {
5017 has_error_code = true;
5018 error_code =
5019 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5020 }
5021 /* fall through */
5022 case INTR_TYPE_SOFT_EXCEPTION:
5023 kvm_clear_exception_queue(vcpu);
5024 break;
5025 default:
5026 break;
5027 }
5028 }
5029 tss_selector = exit_qualification;
5030
5031 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5032 type != INTR_TYPE_EXT_INTR &&
5033 type != INTR_TYPE_NMI_INTR))
5034 skip_emulated_instruction(vcpu);
5035
5036 if (kvm_task_switch(vcpu, tss_selector,
5037 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5038 has_error_code, error_code) == EMULATE_FAIL) {
5039 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5040 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5041 vcpu->run->internal.ndata = 0;
5042 return 0;
5043 }
5044
5045 /* clear all local breakpoint enable flags */
5046 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5047
5048 /*
5049 * TODO: What about debug traps on tss switch?
5050 * Are we supposed to inject them and update dr6?
5051 */
5052
5053 return 1;
5054}
5055
5056static int handle_ept_violation(struct kvm_vcpu *vcpu)
5057{
5058 unsigned long exit_qualification;
5059 gpa_t gpa;
5060 u32 error_code;
5061 int gla_validity;
5062
5063 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5064
5065 gla_validity = (exit_qualification >> 7) & 0x3;
5066 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5067 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5068 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5069 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5070 vmcs_readl(GUEST_LINEAR_ADDRESS));
5071 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5072 (long unsigned int)exit_qualification);
5073 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5074 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5075 return 0;
5076 }
5077
5078 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5079 trace_kvm_page_fault(gpa, exit_qualification);
5080
5081 /* It is a write fault? */
5082 error_code = exit_qualification & (1U << 1);
5083 /* ept page table is present? */
5084 error_code |= (exit_qualification >> 3) & 0x1;
5085
5086 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5087}
5088
5089static u64 ept_rsvd_mask(u64 spte, int level)
5090{
5091 int i;
5092 u64 mask = 0;
5093
5094 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5095 mask |= (1ULL << i);
5096
5097 if (level > 2)
5098 /* bits 7:3 reserved */
5099 mask |= 0xf8;
5100 else if (level == 2) {
5101 if (spte & (1ULL << 7))
5102 /* 2MB ref, bits 20:12 reserved */
5103 mask |= 0x1ff000;
5104 else
5105 /* bits 6:3 reserved */
5106 mask |= 0x78;
5107 }
5108
5109 return mask;
5110}
5111
5112static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5113 int level)
5114{
5115 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5116
5117 /* 010b (write-only) */
5118 WARN_ON((spte & 0x7) == 0x2);
5119
5120 /* 110b (write/execute) */
5121 WARN_ON((spte & 0x7) == 0x6);
5122
5123 /* 100b (execute-only) and value not supported by logical processor */
5124 if (!cpu_has_vmx_ept_execute_only())
5125 WARN_ON((spte & 0x7) == 0x4);
5126
5127 /* not 000b */
5128 if ((spte & 0x7)) {
5129 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5130
5131 if (rsvd_bits != 0) {
5132 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5133 __func__, rsvd_bits);
5134 WARN_ON(1);
5135 }
5136
5137 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5138 u64 ept_mem_type = (spte & 0x38) >> 3;
5139
5140 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5141 ept_mem_type == 7) {
5142 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5143 __func__, ept_mem_type);
5144 WARN_ON(1);
5145 }
5146 }
5147 }
5148}
5149
5150static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5151{
5152 u64 sptes[4];
5153 int nr_sptes, i, ret;
5154 gpa_t gpa;
5155
5156 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5157
5158 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5159 if (likely(ret == 1))
5160 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5161 EMULATE_DONE;
5162 if (unlikely(!ret))
5163 return 1;
5164
5165 /* It is the real ept misconfig */
5166 printk(KERN_ERR "EPT: Misconfiguration.\n");
5167 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5168
5169 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5170
5171 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5172 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5173
5174 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5175 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5176
5177 return 0;
5178}
5179
5180static int handle_nmi_window(struct kvm_vcpu *vcpu)
5181{
5182 u32 cpu_based_vm_exec_control;
5183
5184 /* clear pending NMI */
5185 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5186 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5187 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5188 ++vcpu->stat.nmi_window_exits;
5189 kvm_make_request(KVM_REQ_EVENT, vcpu);
5190
5191 return 1;
5192}
5193
5194static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5195{
5196 struct vcpu_vmx *vmx = to_vmx(vcpu);
5197 enum emulation_result err = EMULATE_DONE;
5198 int ret = 1;
5199 u32 cpu_exec_ctrl;
5200 bool intr_window_requested;
5201 unsigned count = 130;
5202
5203 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5204 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5205
5206 while (!guest_state_valid(vcpu) && count-- != 0) {
5207 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5208 return handle_interrupt_window(&vmx->vcpu);
5209
5210 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5211 return 1;
5212
5213 err = emulate_instruction(vcpu, 0);
5214
5215 if (err == EMULATE_DO_MMIO) {
5216 ret = 0;
5217 goto out;
5218 }
5219
5220 if (err != EMULATE_DONE) {
5221 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5222 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5223 vcpu->run->internal.ndata = 0;
5224 return 0;
5225 }
5226
5227 if (signal_pending(current))
5228 goto out;
5229 if (need_resched())
5230 schedule();
5231 }
5232
5233 vmx->emulation_required = emulation_required(vcpu);
5234out:
5235 return ret;
5236}
5237
5238/*
5239 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5240 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5241 */
5242static int handle_pause(struct kvm_vcpu *vcpu)
5243{
5244 skip_emulated_instruction(vcpu);
5245 kvm_vcpu_on_spin(vcpu);
5246
5247 return 1;
5248}
5249
5250static int handle_invalid_op(struct kvm_vcpu *vcpu)
5251{
5252 kvm_queue_exception(vcpu, UD_VECTOR);
5253 return 1;
5254}
5255
5256/*
5257 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5258 * We could reuse a single VMCS for all the L2 guests, but we also want the
5259 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5260 * allows keeping them loaded on the processor, and in the future will allow
5261 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5262 * every entry if they never change.
5263 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5264 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5265 *
5266 * The following functions allocate and free a vmcs02 in this pool.
5267 */
5268
5269/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5270static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5271{
5272 struct vmcs02_list *item;
5273 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5274 if (item->vmptr == vmx->nested.current_vmptr) {
5275 list_move(&item->list, &vmx->nested.vmcs02_pool);
5276 return &item->vmcs02;
5277 }
5278
5279 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5280 /* Recycle the least recently used VMCS. */
5281 item = list_entry(vmx->nested.vmcs02_pool.prev,
5282 struct vmcs02_list, list);
5283 item->vmptr = vmx->nested.current_vmptr;
5284 list_move(&item->list, &vmx->nested.vmcs02_pool);
5285 return &item->vmcs02;
5286 }
5287
5288 /* Create a new VMCS */
5289 item = (struct vmcs02_list *)
5290 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5291 if (!item)
5292 return NULL;
5293 item->vmcs02.vmcs = alloc_vmcs();
5294 if (!item->vmcs02.vmcs) {
5295 kfree(item);
5296 return NULL;
5297 }
5298 loaded_vmcs_init(&item->vmcs02);
5299 item->vmptr = vmx->nested.current_vmptr;
5300 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5301 vmx->nested.vmcs02_num++;
5302 return &item->vmcs02;
5303}
5304
5305/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5306static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5307{
5308 struct vmcs02_list *item;
5309 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5310 if (item->vmptr == vmptr) {
5311 free_loaded_vmcs(&item->vmcs02);
5312 list_del(&item->list);
5313 kfree(item);
5314 vmx->nested.vmcs02_num--;
5315 return;
5316 }
5317}
5318
5319/*
5320 * Free all VMCSs saved for this vcpu, except the one pointed by
5321 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5322 * currently used, if running L2), and vmcs01 when running L2.
5323 */
5324static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5325{
5326 struct vmcs02_list *item, *n;
5327 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5328 if (vmx->loaded_vmcs != &item->vmcs02)
5329 free_loaded_vmcs(&item->vmcs02);
5330 list_del(&item->list);
5331 kfree(item);
5332 }
5333 vmx->nested.vmcs02_num = 0;
5334
5335 if (vmx->loaded_vmcs != &vmx->vmcs01)
5336 free_loaded_vmcs(&vmx->vmcs01);
5337}
5338
5339/*
5340 * Emulate the VMXON instruction.
5341 * Currently, we just remember that VMX is active, and do not save or even
5342 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5343 * do not currently need to store anything in that guest-allocated memory
5344 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5345 * argument is different from the VMXON pointer (which the spec says they do).
5346 */
5347static int handle_vmon(struct kvm_vcpu *vcpu)
5348{
5349 struct kvm_segment cs;
5350 struct vcpu_vmx *vmx = to_vmx(vcpu);
5351
5352 /* The Intel VMX Instruction Reference lists a bunch of bits that
5353 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5354 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5355 * Otherwise, we should fail with #UD. We test these now:
5356 */
5357 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5358 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5359 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5360 kvm_queue_exception(vcpu, UD_VECTOR);
5361 return 1;
5362 }
5363
5364 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5365 if (is_long_mode(vcpu) && !cs.l) {
5366 kvm_queue_exception(vcpu, UD_VECTOR);
5367 return 1;
5368 }
5369
5370 if (vmx_get_cpl(vcpu)) {
5371 kvm_inject_gp(vcpu, 0);
5372 return 1;
5373 }
5374
5375 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5376 vmx->nested.vmcs02_num = 0;
5377
5378 vmx->nested.vmxon = true;
5379
5380 skip_emulated_instruction(vcpu);
5381 return 1;
5382}
5383
5384/*
5385 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5386 * for running VMX instructions (except VMXON, whose prerequisites are
5387 * slightly different). It also specifies what exception to inject otherwise.
5388 */
5389static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5390{
5391 struct kvm_segment cs;
5392 struct vcpu_vmx *vmx = to_vmx(vcpu);
5393
5394 if (!vmx->nested.vmxon) {
5395 kvm_queue_exception(vcpu, UD_VECTOR);
5396 return 0;
5397 }
5398
5399 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5400 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5401 (is_long_mode(vcpu) && !cs.l)) {
5402 kvm_queue_exception(vcpu, UD_VECTOR);
5403 return 0;
5404 }
5405
5406 if (vmx_get_cpl(vcpu)) {
5407 kvm_inject_gp(vcpu, 0);
5408 return 0;
5409 }
5410
5411 return 1;
5412}
5413
5414/*
5415 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5416 * just stops using VMX.
5417 */
5418static void free_nested(struct vcpu_vmx *vmx)
5419{
5420 if (!vmx->nested.vmxon)
5421 return;
5422 vmx->nested.vmxon = false;
5423 if (vmx->nested.current_vmptr != -1ull) {
5424 kunmap(vmx->nested.current_vmcs12_page);
5425 nested_release_page(vmx->nested.current_vmcs12_page);
5426 vmx->nested.current_vmptr = -1ull;
5427 vmx->nested.current_vmcs12 = NULL;
5428 }
5429 /* Unpin physical memory we referred to in current vmcs02 */
5430 if (vmx->nested.apic_access_page) {
5431 nested_release_page(vmx->nested.apic_access_page);
5432 vmx->nested.apic_access_page = 0;
5433 }
5434
5435 nested_free_all_saved_vmcss(vmx);
5436}
5437
5438/* Emulate the VMXOFF instruction */
5439static int handle_vmoff(struct kvm_vcpu *vcpu)
5440{
5441 if (!nested_vmx_check_permission(vcpu))
5442 return 1;
5443 free_nested(to_vmx(vcpu));
5444 skip_emulated_instruction(vcpu);
5445 return 1;
5446}
5447
5448/*
5449 * Decode the memory-address operand of a vmx instruction, as recorded on an
5450 * exit caused by such an instruction (run by a guest hypervisor).
5451 * On success, returns 0. When the operand is invalid, returns 1 and throws
5452 * #UD or #GP.
5453 */
5454static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5455 unsigned long exit_qualification,
5456 u32 vmx_instruction_info, gva_t *ret)
5457{
5458 /*
5459 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5460 * Execution", on an exit, vmx_instruction_info holds most of the
5461 * addressing components of the operand. Only the displacement part
5462 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5463 * For how an actual address is calculated from all these components,
5464 * refer to Vol. 1, "Operand Addressing".
5465 */
5466 int scaling = vmx_instruction_info & 3;
5467 int addr_size = (vmx_instruction_info >> 7) & 7;
5468 bool is_reg = vmx_instruction_info & (1u << 10);
5469 int seg_reg = (vmx_instruction_info >> 15) & 7;
5470 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5471 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5472 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5473 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5474
5475 if (is_reg) {
5476 kvm_queue_exception(vcpu, UD_VECTOR);
5477 return 1;
5478 }
5479
5480 /* Addr = segment_base + offset */
5481 /* offset = base + [index * scale] + displacement */
5482 *ret = vmx_get_segment_base(vcpu, seg_reg);
5483 if (base_is_valid)
5484 *ret += kvm_register_read(vcpu, base_reg);
5485 if (index_is_valid)
5486 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5487 *ret += exit_qualification; /* holds the displacement */
5488
5489 if (addr_size == 1) /* 32 bit */
5490 *ret &= 0xffffffff;
5491
5492 /*
5493 * TODO: throw #GP (and return 1) in various cases that the VM*
5494 * instructions require it - e.g., offset beyond segment limit,
5495 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5496 * address, and so on. Currently these are not checked.
5497 */
5498 return 0;
5499}
5500
5501/*
5502 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5503 * set the success or error code of an emulated VMX instruction, as specified
5504 * by Vol 2B, VMX Instruction Reference, "Conventions".
5505 */
5506static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5507{
5508 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5509 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5510 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5511}
5512
5513static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5514{
5515 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5516 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5517 X86_EFLAGS_SF | X86_EFLAGS_OF))
5518 | X86_EFLAGS_CF);
5519}
5520
5521static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5522 u32 vm_instruction_error)
5523{
5524 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5525 /*
5526 * failValid writes the error number to the current VMCS, which
5527 * can't be done there isn't a current VMCS.
5528 */
5529 nested_vmx_failInvalid(vcpu);
5530 return;
5531 }
5532 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5533 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5534 X86_EFLAGS_SF | X86_EFLAGS_OF))
5535 | X86_EFLAGS_ZF);
5536 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5537}
5538
5539/* Emulate the VMCLEAR instruction */
5540static int handle_vmclear(struct kvm_vcpu *vcpu)
5541{
5542 struct vcpu_vmx *vmx = to_vmx(vcpu);
5543 gva_t gva;
5544 gpa_t vmptr;
5545 struct vmcs12 *vmcs12;
5546 struct page *page;
5547 struct x86_exception e;
5548
5549 if (!nested_vmx_check_permission(vcpu))
5550 return 1;
5551
5552 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5553 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5554 return 1;
5555
5556 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5557 sizeof(vmptr), &e)) {
5558 kvm_inject_page_fault(vcpu, &e);
5559 return 1;
5560 }
5561
5562 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5563 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5564 skip_emulated_instruction(vcpu);
5565 return 1;
5566 }
5567
5568 if (vmptr == vmx->nested.current_vmptr) {
5569 kunmap(vmx->nested.current_vmcs12_page);
5570 nested_release_page(vmx->nested.current_vmcs12_page);
5571 vmx->nested.current_vmptr = -1ull;
5572 vmx->nested.current_vmcs12 = NULL;
5573 }
5574
5575 page = nested_get_page(vcpu, vmptr);
5576 if (page == NULL) {
5577 /*
5578 * For accurate processor emulation, VMCLEAR beyond available
5579 * physical memory should do nothing at all. However, it is
5580 * possible that a nested vmx bug, not a guest hypervisor bug,
5581 * resulted in this case, so let's shut down before doing any
5582 * more damage:
5583 */
5584 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5585 return 1;
5586 }
5587 vmcs12 = kmap(page);
5588 vmcs12->launch_state = 0;
5589 kunmap(page);
5590 nested_release_page(page);
5591
5592 nested_free_vmcs02(vmx, vmptr);
5593
5594 skip_emulated_instruction(vcpu);
5595 nested_vmx_succeed(vcpu);
5596 return 1;
5597}
5598
5599static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5600
5601/* Emulate the VMLAUNCH instruction */
5602static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5603{
5604 return nested_vmx_run(vcpu, true);
5605}
5606
5607/* Emulate the VMRESUME instruction */
5608static int handle_vmresume(struct kvm_vcpu *vcpu)
5609{
5610
5611 return nested_vmx_run(vcpu, false);
5612}
5613
5614enum vmcs_field_type {
5615 VMCS_FIELD_TYPE_U16 = 0,
5616 VMCS_FIELD_TYPE_U64 = 1,
5617 VMCS_FIELD_TYPE_U32 = 2,
5618 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5619};
5620
5621static inline int vmcs_field_type(unsigned long field)
5622{
5623 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5624 return VMCS_FIELD_TYPE_U32;
5625 return (field >> 13) & 0x3 ;
5626}
5627
5628static inline int vmcs_field_readonly(unsigned long field)
5629{
5630 return (((field >> 10) & 0x3) == 1);
5631}
5632
5633/*
5634 * Read a vmcs12 field. Since these can have varying lengths and we return
5635 * one type, we chose the biggest type (u64) and zero-extend the return value
5636 * to that size. Note that the caller, handle_vmread, might need to use only
5637 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5638 * 64-bit fields are to be returned).
5639 */
5640static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5641 unsigned long field, u64 *ret)
5642{
5643 short offset = vmcs_field_to_offset(field);
5644 char *p;
5645
5646 if (offset < 0)
5647 return 0;
5648
5649 p = ((char *)(get_vmcs12(vcpu))) + offset;
5650
5651 switch (vmcs_field_type(field)) {
5652 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5653 *ret = *((natural_width *)p);
5654 return 1;
5655 case VMCS_FIELD_TYPE_U16:
5656 *ret = *((u16 *)p);
5657 return 1;
5658 case VMCS_FIELD_TYPE_U32:
5659 *ret = *((u32 *)p);
5660 return 1;
5661 case VMCS_FIELD_TYPE_U64:
5662 *ret = *((u64 *)p);
5663 return 1;
5664 default:
5665 return 0; /* can never happen. */
5666 }
5667}
5668
5669/*
5670 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5671 * used before) all generate the same failure when it is missing.
5672 */
5673static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5674{
5675 struct vcpu_vmx *vmx = to_vmx(vcpu);
5676 if (vmx->nested.current_vmptr == -1ull) {
5677 nested_vmx_failInvalid(vcpu);
5678 skip_emulated_instruction(vcpu);
5679 return 0;
5680 }
5681 return 1;
5682}
5683
5684static int handle_vmread(struct kvm_vcpu *vcpu)
5685{
5686 unsigned long field;
5687 u64 field_value;
5688 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5689 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5690 gva_t gva = 0;
5691
5692 if (!nested_vmx_check_permission(vcpu) ||
5693 !nested_vmx_check_vmcs12(vcpu))
5694 return 1;
5695
5696 /* Decode instruction info and find the field to read */
5697 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5698 /* Read the field, zero-extended to a u64 field_value */
5699 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5700 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5701 skip_emulated_instruction(vcpu);
5702 return 1;
5703 }
5704 /*
5705 * Now copy part of this value to register or memory, as requested.
5706 * Note that the number of bits actually copied is 32 or 64 depending
5707 * on the guest's mode (32 or 64 bit), not on the given field's length.
5708 */
5709 if (vmx_instruction_info & (1u << 10)) {
5710 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5711 field_value);
5712 } else {
5713 if (get_vmx_mem_address(vcpu, exit_qualification,
5714 vmx_instruction_info, &gva))
5715 return 1;
5716 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5717 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5718 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5719 }
5720
5721 nested_vmx_succeed(vcpu);
5722 skip_emulated_instruction(vcpu);
5723 return 1;
5724}
5725
5726
5727static int handle_vmwrite(struct kvm_vcpu *vcpu)
5728{
5729 unsigned long field;
5730 gva_t gva;
5731 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5732 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5733 char *p;
5734 short offset;
5735 /* The value to write might be 32 or 64 bits, depending on L1's long
5736 * mode, and eventually we need to write that into a field of several
5737 * possible lengths. The code below first zero-extends the value to 64
5738 * bit (field_value), and then copies only the approriate number of
5739 * bits into the vmcs12 field.
5740 */
5741 u64 field_value = 0;
5742 struct x86_exception e;
5743
5744 if (!nested_vmx_check_permission(vcpu) ||
5745 !nested_vmx_check_vmcs12(vcpu))
5746 return 1;
5747
5748 if (vmx_instruction_info & (1u << 10))
5749 field_value = kvm_register_read(vcpu,
5750 (((vmx_instruction_info) >> 3) & 0xf));
5751 else {
5752 if (get_vmx_mem_address(vcpu, exit_qualification,
5753 vmx_instruction_info, &gva))
5754 return 1;
5755 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5756 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5757 kvm_inject_page_fault(vcpu, &e);
5758 return 1;
5759 }
5760 }
5761
5762
5763 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5764 if (vmcs_field_readonly(field)) {
5765 nested_vmx_failValid(vcpu,
5766 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5767 skip_emulated_instruction(vcpu);
5768 return 1;
5769 }
5770
5771 offset = vmcs_field_to_offset(field);
5772 if (offset < 0) {
5773 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5774 skip_emulated_instruction(vcpu);
5775 return 1;
5776 }
5777 p = ((char *) get_vmcs12(vcpu)) + offset;
5778
5779 switch (vmcs_field_type(field)) {
5780 case VMCS_FIELD_TYPE_U16:
5781 *(u16 *)p = field_value;
5782 break;
5783 case VMCS_FIELD_TYPE_U32:
5784 *(u32 *)p = field_value;
5785 break;
5786 case VMCS_FIELD_TYPE_U64:
5787 *(u64 *)p = field_value;
5788 break;
5789 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5790 *(natural_width *)p = field_value;
5791 break;
5792 default:
5793 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5794 skip_emulated_instruction(vcpu);
5795 return 1;
5796 }
5797
5798 nested_vmx_succeed(vcpu);
5799 skip_emulated_instruction(vcpu);
5800 return 1;
5801}
5802
5803/* Emulate the VMPTRLD instruction */
5804static int handle_vmptrld(struct kvm_vcpu *vcpu)
5805{
5806 struct vcpu_vmx *vmx = to_vmx(vcpu);
5807 gva_t gva;
5808 gpa_t vmptr;
5809 struct x86_exception e;
5810
5811 if (!nested_vmx_check_permission(vcpu))
5812 return 1;
5813
5814 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5815 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5816 return 1;
5817
5818 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5819 sizeof(vmptr), &e)) {
5820 kvm_inject_page_fault(vcpu, &e);
5821 return 1;
5822 }
5823
5824 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5825 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5826 skip_emulated_instruction(vcpu);
5827 return 1;
5828 }
5829
5830 if (vmx->nested.current_vmptr != vmptr) {
5831 struct vmcs12 *new_vmcs12;
5832 struct page *page;
5833 page = nested_get_page(vcpu, vmptr);
5834 if (page == NULL) {
5835 nested_vmx_failInvalid(vcpu);
5836 skip_emulated_instruction(vcpu);
5837 return 1;
5838 }
5839 new_vmcs12 = kmap(page);
5840 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5841 kunmap(page);
5842 nested_release_page_clean(page);
5843 nested_vmx_failValid(vcpu,
5844 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5845 skip_emulated_instruction(vcpu);
5846 return 1;
5847 }
5848 if (vmx->nested.current_vmptr != -1ull) {
5849 kunmap(vmx->nested.current_vmcs12_page);
5850 nested_release_page(vmx->nested.current_vmcs12_page);
5851 }
5852
5853 vmx->nested.current_vmptr = vmptr;
5854 vmx->nested.current_vmcs12 = new_vmcs12;
5855 vmx->nested.current_vmcs12_page = page;
5856 }
5857
5858 nested_vmx_succeed(vcpu);
5859 skip_emulated_instruction(vcpu);
5860 return 1;
5861}
5862
5863/* Emulate the VMPTRST instruction */
5864static int handle_vmptrst(struct kvm_vcpu *vcpu)
5865{
5866 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5867 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5868 gva_t vmcs_gva;
5869 struct x86_exception e;
5870
5871 if (!nested_vmx_check_permission(vcpu))
5872 return 1;
5873
5874 if (get_vmx_mem_address(vcpu, exit_qualification,
5875 vmx_instruction_info, &vmcs_gva))
5876 return 1;
5877 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5878 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5879 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5880 sizeof(u64), &e)) {
5881 kvm_inject_page_fault(vcpu, &e);
5882 return 1;
5883 }
5884 nested_vmx_succeed(vcpu);
5885 skip_emulated_instruction(vcpu);
5886 return 1;
5887}
5888
5889/*
5890 * The exit handlers return 1 if the exit was handled fully and guest execution
5891 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5892 * to be done to userspace and return 0.
5893 */
5894static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5895 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5896 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5897 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5898 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5899 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5900 [EXIT_REASON_CR_ACCESS] = handle_cr,
5901 [EXIT_REASON_DR_ACCESS] = handle_dr,
5902 [EXIT_REASON_CPUID] = handle_cpuid,
5903 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5904 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5905 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5906 [EXIT_REASON_HLT] = handle_halt,
5907 [EXIT_REASON_INVD] = handle_invd,
5908 [EXIT_REASON_INVLPG] = handle_invlpg,
5909 [EXIT_REASON_RDPMC] = handle_rdpmc,
5910 [EXIT_REASON_VMCALL] = handle_vmcall,
5911 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5912 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5913 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5914 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5915 [EXIT_REASON_VMREAD] = handle_vmread,
5916 [EXIT_REASON_VMRESUME] = handle_vmresume,
5917 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5918 [EXIT_REASON_VMOFF] = handle_vmoff,
5919 [EXIT_REASON_VMON] = handle_vmon,
5920 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5921 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5922 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5923 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5924 [EXIT_REASON_WBINVD] = handle_wbinvd,
5925 [EXIT_REASON_XSETBV] = handle_xsetbv,
5926 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5927 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5928 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5929 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5930 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5931 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5932 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5933};
5934
5935static const int kvm_vmx_max_exit_handlers =
5936 ARRAY_SIZE(kvm_vmx_exit_handlers);
5937
5938static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5939 struct vmcs12 *vmcs12)
5940{
5941 unsigned long exit_qualification;
5942 gpa_t bitmap, last_bitmap;
5943 unsigned int port;
5944 int size;
5945 u8 b;
5946
5947 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5948 return 1;
5949
5950 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5951 return 0;
5952
5953 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5954
5955 port = exit_qualification >> 16;
5956 size = (exit_qualification & 7) + 1;
5957
5958 last_bitmap = (gpa_t)-1;
5959 b = -1;
5960
5961 while (size > 0) {
5962 if (port < 0x8000)
5963 bitmap = vmcs12->io_bitmap_a;
5964 else if (port < 0x10000)
5965 bitmap = vmcs12->io_bitmap_b;
5966 else
5967 return 1;
5968 bitmap += (port & 0x7fff) / 8;
5969
5970 if (last_bitmap != bitmap)
5971 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5972 return 1;
5973 if (b & (1 << (port & 7)))
5974 return 1;
5975
5976 port++;
5977 size--;
5978 last_bitmap = bitmap;
5979 }
5980
5981 return 0;
5982}
5983
5984/*
5985 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5986 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5987 * disinterest in the current event (read or write a specific MSR) by using an
5988 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5989 */
5990static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5991 struct vmcs12 *vmcs12, u32 exit_reason)
5992{
5993 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5994 gpa_t bitmap;
5995
5996 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
5997 return 1;
5998
5999 /*
6000 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6001 * for the four combinations of read/write and low/high MSR numbers.
6002 * First we need to figure out which of the four to use:
6003 */
6004 bitmap = vmcs12->msr_bitmap;
6005 if (exit_reason == EXIT_REASON_MSR_WRITE)
6006 bitmap += 2048;
6007 if (msr_index >= 0xc0000000) {
6008 msr_index -= 0xc0000000;
6009 bitmap += 1024;
6010 }
6011
6012 /* Then read the msr_index'th bit from this bitmap: */
6013 if (msr_index < 1024*8) {
6014 unsigned char b;
6015 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6016 return 1;
6017 return 1 & (b >> (msr_index & 7));
6018 } else
6019 return 1; /* let L1 handle the wrong parameter */
6020}
6021
6022/*
6023 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6024 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6025 * intercept (via guest_host_mask etc.) the current event.
6026 */
6027static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6028 struct vmcs12 *vmcs12)
6029{
6030 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6031 int cr = exit_qualification & 15;
6032 int reg = (exit_qualification >> 8) & 15;
6033 unsigned long val = kvm_register_read(vcpu, reg);
6034
6035 switch ((exit_qualification >> 4) & 3) {
6036 case 0: /* mov to cr */
6037 switch (cr) {
6038 case 0:
6039 if (vmcs12->cr0_guest_host_mask &
6040 (val ^ vmcs12->cr0_read_shadow))
6041 return 1;
6042 break;
6043 case 3:
6044 if ((vmcs12->cr3_target_count >= 1 &&
6045 vmcs12->cr3_target_value0 == val) ||
6046 (vmcs12->cr3_target_count >= 2 &&
6047 vmcs12->cr3_target_value1 == val) ||
6048 (vmcs12->cr3_target_count >= 3 &&
6049 vmcs12->cr3_target_value2 == val) ||
6050 (vmcs12->cr3_target_count >= 4 &&
6051 vmcs12->cr3_target_value3 == val))
6052 return 0;
6053 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6054 return 1;
6055 break;
6056 case 4:
6057 if (vmcs12->cr4_guest_host_mask &
6058 (vmcs12->cr4_read_shadow ^ val))
6059 return 1;
6060 break;
6061 case 8:
6062 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6063 return 1;
6064 break;
6065 }
6066 break;
6067 case 2: /* clts */
6068 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6069 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6070 return 1;
6071 break;
6072 case 1: /* mov from cr */
6073 switch (cr) {
6074 case 3:
6075 if (vmcs12->cpu_based_vm_exec_control &
6076 CPU_BASED_CR3_STORE_EXITING)
6077 return 1;
6078 break;
6079 case 8:
6080 if (vmcs12->cpu_based_vm_exec_control &
6081 CPU_BASED_CR8_STORE_EXITING)
6082 return 1;
6083 break;
6084 }
6085 break;
6086 case 3: /* lmsw */
6087 /*
6088 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6089 * cr0. Other attempted changes are ignored, with no exit.
6090 */
6091 if (vmcs12->cr0_guest_host_mask & 0xe &
6092 (val ^ vmcs12->cr0_read_shadow))
6093 return 1;
6094 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6095 !(vmcs12->cr0_read_shadow & 0x1) &&
6096 (val & 0x1))
6097 return 1;
6098 break;
6099 }
6100 return 0;
6101}
6102
6103/*
6104 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6105 * should handle it ourselves in L0 (and then continue L2). Only call this
6106 * when in is_guest_mode (L2).
6107 */
6108static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6109{
6110 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6111 struct vcpu_vmx *vmx = to_vmx(vcpu);
6112 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6113 u32 exit_reason = vmx->exit_reason;
6114
6115 if (vmx->nested.nested_run_pending)
6116 return 0;
6117
6118 if (unlikely(vmx->fail)) {
6119 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6120 vmcs_read32(VM_INSTRUCTION_ERROR));
6121 return 1;
6122 }
6123
6124 switch (exit_reason) {
6125 case EXIT_REASON_EXCEPTION_NMI:
6126 if (!is_exception(intr_info))
6127 return 0;
6128 else if (is_page_fault(intr_info))
6129 return enable_ept;
6130 return vmcs12->exception_bitmap &
6131 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6132 case EXIT_REASON_EXTERNAL_INTERRUPT:
6133 return 0;
6134 case EXIT_REASON_TRIPLE_FAULT:
6135 return 1;
6136 case EXIT_REASON_PENDING_INTERRUPT:
6137 case EXIT_REASON_NMI_WINDOW:
6138 /*
6139 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6140 * (aka Interrupt Window Exiting) only when L1 turned it on,
6141 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6142 * Same for NMI Window Exiting.
6143 */
6144 return 1;
6145 case EXIT_REASON_TASK_SWITCH:
6146 return 1;
6147 case EXIT_REASON_CPUID:
6148 return 1;
6149 case EXIT_REASON_HLT:
6150 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6151 case EXIT_REASON_INVD:
6152 return 1;
6153 case EXIT_REASON_INVLPG:
6154 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6155 case EXIT_REASON_RDPMC:
6156 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6157 case EXIT_REASON_RDTSC:
6158 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6159 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6160 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6161 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6162 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6163 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6164 /*
6165 * VMX instructions trap unconditionally. This allows L1 to
6166 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6167 */
6168 return 1;
6169 case EXIT_REASON_CR_ACCESS:
6170 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6171 case EXIT_REASON_DR_ACCESS:
6172 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6173 case EXIT_REASON_IO_INSTRUCTION:
6174 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6175 case EXIT_REASON_MSR_READ:
6176 case EXIT_REASON_MSR_WRITE:
6177 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6178 case EXIT_REASON_INVALID_STATE:
6179 return 1;
6180 case EXIT_REASON_MWAIT_INSTRUCTION:
6181 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6182 case EXIT_REASON_MONITOR_INSTRUCTION:
6183 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6184 case EXIT_REASON_PAUSE_INSTRUCTION:
6185 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6186 nested_cpu_has2(vmcs12,
6187 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6188 case EXIT_REASON_MCE_DURING_VMENTRY:
6189 return 0;
6190 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6191 return 1;
6192 case EXIT_REASON_APIC_ACCESS:
6193 return nested_cpu_has2(vmcs12,
6194 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6195 case EXIT_REASON_EPT_VIOLATION:
6196 case EXIT_REASON_EPT_MISCONFIG:
6197 return 0;
6198 case EXIT_REASON_WBINVD:
6199 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6200 case EXIT_REASON_XSETBV:
6201 return 1;
6202 default:
6203 return 1;
6204 }
6205}
6206
6207static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6208{
6209 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6210 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6211}
6212
6213/*
6214 * The guest has exited. See if we can fix it or if we need userspace
6215 * assistance.
6216 */
6217static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6218{
6219 struct vcpu_vmx *vmx = to_vmx(vcpu);
6220 u32 exit_reason = vmx->exit_reason;
6221 u32 vectoring_info = vmx->idt_vectoring_info;
6222
6223 /* If guest state is invalid, start emulating */
6224 if (vmx->emulation_required)
6225 return handle_invalid_guest_state(vcpu);
6226
6227 /*
6228 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6229 * we did not inject a still-pending event to L1 now because of
6230 * nested_run_pending, we need to re-enable this bit.
6231 */
6232 if (vmx->nested.nested_run_pending)
6233 kvm_make_request(KVM_REQ_EVENT, vcpu);
6234
6235 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6236 exit_reason == EXIT_REASON_VMRESUME))
6237 vmx->nested.nested_run_pending = 1;
6238 else
6239 vmx->nested.nested_run_pending = 0;
6240
6241 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6242 nested_vmx_vmexit(vcpu);
6243 return 1;
6244 }
6245
6246 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6247 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6248 vcpu->run->fail_entry.hardware_entry_failure_reason
6249 = exit_reason;
6250 return 0;
6251 }
6252
6253 if (unlikely(vmx->fail)) {
6254 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6255 vcpu->run->fail_entry.hardware_entry_failure_reason
6256 = vmcs_read32(VM_INSTRUCTION_ERROR);
6257 return 0;
6258 }
6259
6260 /*
6261 * Note:
6262 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6263 * delivery event since it indicates guest is accessing MMIO.
6264 * The vm-exit can be triggered again after return to guest that
6265 * will cause infinite loop.
6266 */
6267 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6268 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6269 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6270 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6271 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6272 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6273 vcpu->run->internal.ndata = 2;
6274 vcpu->run->internal.data[0] = vectoring_info;
6275 vcpu->run->internal.data[1] = exit_reason;
6276 return 0;
6277 }
6278
6279 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6280 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6281 get_vmcs12(vcpu), vcpu)))) {
6282 if (vmx_interrupt_allowed(vcpu)) {
6283 vmx->soft_vnmi_blocked = 0;
6284 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6285 vcpu->arch.nmi_pending) {
6286 /*
6287 * This CPU don't support us in finding the end of an
6288 * NMI-blocked window if the guest runs with IRQs
6289 * disabled. So we pull the trigger after 1 s of
6290 * futile waiting, but inform the user about this.
6291 */
6292 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6293 "state on VCPU %d after 1 s timeout\n",
6294 __func__, vcpu->vcpu_id);
6295 vmx->soft_vnmi_blocked = 0;
6296 }
6297 }
6298
6299 if (exit_reason < kvm_vmx_max_exit_handlers
6300 && kvm_vmx_exit_handlers[exit_reason])
6301 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6302 else {
6303 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6304 vcpu->run->hw.hardware_exit_reason = exit_reason;
6305 }
6306 return 0;
6307}
6308
6309static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6310{
6311 if (irr == -1 || tpr < irr) {
6312 vmcs_write32(TPR_THRESHOLD, 0);
6313 return;
6314 }
6315
6316 vmcs_write32(TPR_THRESHOLD, irr);
6317}
6318
6319static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6320{
6321 u32 sec_exec_control;
6322
6323 /*
6324 * There is not point to enable virtualize x2apic without enable
6325 * apicv
6326 */
6327 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6328 !vmx_vm_has_apicv(vcpu->kvm))
6329 return;
6330
6331 if (!vm_need_tpr_shadow(vcpu->kvm))
6332 return;
6333
6334 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6335
6336 if (set) {
6337 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6338 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6339 } else {
6340 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6341 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6342 }
6343 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6344
6345 vmx_set_msr_bitmap(vcpu);
6346}
6347
6348static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6349{
6350 u16 status;
6351 u8 old;
6352
6353 if (!vmx_vm_has_apicv(kvm))
6354 return;
6355
6356 if (isr == -1)
6357 isr = 0;
6358
6359 status = vmcs_read16(GUEST_INTR_STATUS);
6360 old = status >> 8;
6361 if (isr != old) {
6362 status &= 0xff;
6363 status |= isr << 8;
6364 vmcs_write16(GUEST_INTR_STATUS, status);
6365 }
6366}
6367
6368static void vmx_set_rvi(int vector)
6369{
6370 u16 status;
6371 u8 old;
6372
6373 status = vmcs_read16(GUEST_INTR_STATUS);
6374 old = (u8)status & 0xff;
6375 if ((u8)vector != old) {
6376 status &= ~0xff;
6377 status |= (u8)vector;
6378 vmcs_write16(GUEST_INTR_STATUS, status);
6379 }
6380}
6381
6382static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6383{
6384 if (max_irr == -1)
6385 return;
6386
6387 vmx_set_rvi(max_irr);
6388}
6389
6390static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6391{
6392 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6393 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6394 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6395 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6396}
6397
6398static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6399{
6400 u32 exit_intr_info;
6401
6402 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6403 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6404 return;
6405
6406 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6407 exit_intr_info = vmx->exit_intr_info;
6408
6409 /* Handle machine checks before interrupts are enabled */
6410 if (is_machine_check(exit_intr_info))
6411 kvm_machine_check();
6412
6413 /* We need to handle NMIs before interrupts are enabled */
6414 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6415 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6416 kvm_before_handle_nmi(&vmx->vcpu);
6417 asm("int $2");
6418 kvm_after_handle_nmi(&vmx->vcpu);
6419 }
6420}
6421
6422static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6423{
6424 u32 exit_intr_info;
6425 bool unblock_nmi;
6426 u8 vector;
6427 bool idtv_info_valid;
6428
6429 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6430
6431 if (cpu_has_virtual_nmis()) {
6432 if (vmx->nmi_known_unmasked)
6433 return;
6434 /*
6435 * Can't use vmx->exit_intr_info since we're not sure what
6436 * the exit reason is.
6437 */
6438 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6439 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6440 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6441 /*
6442 * SDM 3: 27.7.1.2 (September 2008)
6443 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6444 * a guest IRET fault.
6445 * SDM 3: 23.2.2 (September 2008)
6446 * Bit 12 is undefined in any of the following cases:
6447 * If the VM exit sets the valid bit in the IDT-vectoring
6448 * information field.
6449 * If the VM exit is due to a double fault.
6450 */
6451 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6452 vector != DF_VECTOR && !idtv_info_valid)
6453 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6454 GUEST_INTR_STATE_NMI);
6455 else
6456 vmx->nmi_known_unmasked =
6457 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6458 & GUEST_INTR_STATE_NMI);
6459 } else if (unlikely(vmx->soft_vnmi_blocked))
6460 vmx->vnmi_blocked_time +=
6461 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6462}
6463
6464static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
6465 u32 idt_vectoring_info,
6466 int instr_len_field,
6467 int error_code_field)
6468{
6469 u8 vector;
6470 int type;
6471 bool idtv_info_valid;
6472
6473 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6474
6475 vcpu->arch.nmi_injected = false;
6476 kvm_clear_exception_queue(vcpu);
6477 kvm_clear_interrupt_queue(vcpu);
6478
6479 if (!idtv_info_valid)
6480 return;
6481
6482 kvm_make_request(KVM_REQ_EVENT, vcpu);
6483
6484 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6485 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6486
6487 switch (type) {
6488 case INTR_TYPE_NMI_INTR:
6489 vcpu->arch.nmi_injected = true;
6490 /*
6491 * SDM 3: 27.7.1.2 (September 2008)
6492 * Clear bit "block by NMI" before VM entry if a NMI
6493 * delivery faulted.
6494 */
6495 vmx_set_nmi_mask(vcpu, false);
6496 break;
6497 case INTR_TYPE_SOFT_EXCEPTION:
6498 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6499 /* fall through */
6500 case INTR_TYPE_HARD_EXCEPTION:
6501 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6502 u32 err = vmcs_read32(error_code_field);
6503 kvm_queue_exception_e(vcpu, vector, err);
6504 } else
6505 kvm_queue_exception(vcpu, vector);
6506 break;
6507 case INTR_TYPE_SOFT_INTR:
6508 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6509 /* fall through */
6510 case INTR_TYPE_EXT_INTR:
6511 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6512 break;
6513 default:
6514 break;
6515 }
6516}
6517
6518static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6519{
6520 if (is_guest_mode(&vmx->vcpu))
6521 return;
6522 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
6523 VM_EXIT_INSTRUCTION_LEN,
6524 IDT_VECTORING_ERROR_CODE);
6525}
6526
6527static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6528{
6529 if (is_guest_mode(vcpu))
6530 return;
6531 __vmx_complete_interrupts(vcpu,
6532 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6533 VM_ENTRY_INSTRUCTION_LEN,
6534 VM_ENTRY_EXCEPTION_ERROR_CODE);
6535
6536 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6537}
6538
6539static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6540{
6541 int i, nr_msrs;
6542 struct perf_guest_switch_msr *msrs;
6543
6544 msrs = perf_guest_get_msrs(&nr_msrs);
6545
6546 if (!msrs)
6547 return;
6548
6549 for (i = 0; i < nr_msrs; i++)
6550 if (msrs[i].host == msrs[i].guest)
6551 clear_atomic_switch_msr(vmx, msrs[i].msr);
6552 else
6553 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6554 msrs[i].host);
6555}
6556
6557static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6558{
6559 struct vcpu_vmx *vmx = to_vmx(vcpu);
6560 unsigned long debugctlmsr;
6561
6562 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6563 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6564 if (vmcs12->idt_vectoring_info_field &
6565 VECTORING_INFO_VALID_MASK) {
6566 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6567 vmcs12->idt_vectoring_info_field);
6568 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6569 vmcs12->vm_exit_instruction_len);
6570 if (vmcs12->idt_vectoring_info_field &
6571 VECTORING_INFO_DELIVER_CODE_MASK)
6572 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6573 vmcs12->idt_vectoring_error_code);
6574 }
6575 }
6576
6577 /* Record the guest's net vcpu time for enforced NMI injections. */
6578 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6579 vmx->entry_time = ktime_get();
6580
6581 /* Don't enter VMX if guest state is invalid, let the exit handler
6582 start emulation until we arrive back to a valid state */
6583 if (vmx->emulation_required)
6584 return;
6585
6586 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6587 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6588 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6589 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6590
6591 /* When single-stepping over STI and MOV SS, we must clear the
6592 * corresponding interruptibility bits in the guest state. Otherwise
6593 * vmentry fails as it then expects bit 14 (BS) in pending debug
6594 * exceptions being set, but that's not correct for the guest debugging
6595 * case. */
6596 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6597 vmx_set_interrupt_shadow(vcpu, 0);
6598
6599 atomic_switch_perf_msrs(vmx);
6600 debugctlmsr = get_debugctlmsr();
6601
6602 vmx->__launched = vmx->loaded_vmcs->launched;
6603 asm(
6604 /* Store host registers */
6605 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6606 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6607 "push %%" _ASM_CX " \n\t"
6608 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6609 "je 1f \n\t"
6610 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6611 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6612 "1: \n\t"
6613 /* Reload cr2 if changed */
6614 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6615 "mov %%cr2, %%" _ASM_DX " \n\t"
6616 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6617 "je 2f \n\t"
6618 "mov %%" _ASM_AX", %%cr2 \n\t"
6619 "2: \n\t"
6620 /* Check if vmlaunch of vmresume is needed */
6621 "cmpl $0, %c[launched](%0) \n\t"
6622 /* Load guest registers. Don't clobber flags. */
6623 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6624 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6625 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6626 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6627 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6628 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6629#ifdef CONFIG_X86_64
6630 "mov %c[r8](%0), %%r8 \n\t"
6631 "mov %c[r9](%0), %%r9 \n\t"
6632 "mov %c[r10](%0), %%r10 \n\t"
6633 "mov %c[r11](%0), %%r11 \n\t"
6634 "mov %c[r12](%0), %%r12 \n\t"
6635 "mov %c[r13](%0), %%r13 \n\t"
6636 "mov %c[r14](%0), %%r14 \n\t"
6637 "mov %c[r15](%0), %%r15 \n\t"
6638#endif
6639 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6640
6641 /* Enter guest mode */
6642 "jne 1f \n\t"
6643 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6644 "jmp 2f \n\t"
6645 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6646 "2: "
6647 /* Save guest registers, load host registers, keep flags */
6648 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6649 "pop %0 \n\t"
6650 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6651 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6652 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6653 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6654 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6655 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6656 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6657#ifdef CONFIG_X86_64
6658 "mov %%r8, %c[r8](%0) \n\t"
6659 "mov %%r9, %c[r9](%0) \n\t"
6660 "mov %%r10, %c[r10](%0) \n\t"
6661 "mov %%r11, %c[r11](%0) \n\t"
6662 "mov %%r12, %c[r12](%0) \n\t"
6663 "mov %%r13, %c[r13](%0) \n\t"
6664 "mov %%r14, %c[r14](%0) \n\t"
6665 "mov %%r15, %c[r15](%0) \n\t"
6666#endif
6667 "mov %%cr2, %%" _ASM_AX " \n\t"
6668 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6669
6670 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
6671 "setbe %c[fail](%0) \n\t"
6672 ".pushsection .rodata \n\t"
6673 ".global vmx_return \n\t"
6674 "vmx_return: " _ASM_PTR " 2b \n\t"
6675 ".popsection"
6676 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6677 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6678 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6679 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6680 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6681 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6682 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6683 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6684 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6685 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6686 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6687#ifdef CONFIG_X86_64
6688 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6689 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6690 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6691 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6692 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6693 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6694 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6695 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6696#endif
6697 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6698 [wordsize]"i"(sizeof(ulong))
6699 : "cc", "memory"
6700#ifdef CONFIG_X86_64
6701 , "rax", "rbx", "rdi", "rsi"
6702 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6703#else
6704 , "eax", "ebx", "edi", "esi"
6705#endif
6706 );
6707
6708 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6709 if (debugctlmsr)
6710 update_debugctlmsr(debugctlmsr);
6711
6712#ifndef CONFIG_X86_64
6713 /*
6714 * The sysexit path does not restore ds/es, so we must set them to
6715 * a reasonable value ourselves.
6716 *
6717 * We can't defer this to vmx_load_host_state() since that function
6718 * may be executed in interrupt context, which saves and restore segments
6719 * around it, nullifying its effect.
6720 */
6721 loadsegment(ds, __USER_DS);
6722 loadsegment(es, __USER_DS);
6723#endif
6724
6725 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6726 | (1 << VCPU_EXREG_RFLAGS)
6727 | (1 << VCPU_EXREG_CPL)
6728 | (1 << VCPU_EXREG_PDPTR)
6729 | (1 << VCPU_EXREG_SEGMENTS)
6730 | (1 << VCPU_EXREG_CR3));
6731 vcpu->arch.regs_dirty = 0;
6732
6733 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6734
6735 if (is_guest_mode(vcpu)) {
6736 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6737 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6738 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6739 vmcs12->idt_vectoring_error_code =
6740 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6741 vmcs12->vm_exit_instruction_len =
6742 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6743 }
6744 }
6745
6746 vmx->loaded_vmcs->launched = 1;
6747
6748 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6749 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6750
6751 vmx_complete_atomic_exit(vmx);
6752 vmx_recover_nmi_blocking(vmx);
6753 vmx_complete_interrupts(vmx);
6754}
6755
6756static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6757{
6758 struct vcpu_vmx *vmx = to_vmx(vcpu);
6759
6760 free_vpid(vmx);
6761 free_nested(vmx);
6762 free_loaded_vmcs(vmx->loaded_vmcs);
6763 kfree(vmx->guest_msrs);
6764 kvm_vcpu_uninit(vcpu);
6765 kmem_cache_free(kvm_vcpu_cache, vmx);
6766}
6767
6768static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6769{
6770 int err;
6771 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6772 int cpu;
6773
6774 if (!vmx)
6775 return ERR_PTR(-ENOMEM);
6776
6777 allocate_vpid(vmx);
6778
6779 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6780 if (err)
6781 goto free_vcpu;
6782
6783 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6784 err = -ENOMEM;
6785 if (!vmx->guest_msrs) {
6786 goto uninit_vcpu;
6787 }
6788
6789 vmx->loaded_vmcs = &vmx->vmcs01;
6790 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6791 if (!vmx->loaded_vmcs->vmcs)
6792 goto free_msrs;
6793 if (!vmm_exclusive)
6794 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6795 loaded_vmcs_init(vmx->loaded_vmcs);
6796 if (!vmm_exclusive)
6797 kvm_cpu_vmxoff();
6798
6799 cpu = get_cpu();
6800 vmx_vcpu_load(&vmx->vcpu, cpu);
6801 vmx->vcpu.cpu = cpu;
6802 err = vmx_vcpu_setup(vmx);
6803 vmx_vcpu_put(&vmx->vcpu);
6804 put_cpu();
6805 if (err)
6806 goto free_vmcs;
6807 if (vm_need_virtualize_apic_accesses(kvm))
6808 err = alloc_apic_access_page(kvm);
6809 if (err)
6810 goto free_vmcs;
6811
6812 if (enable_ept) {
6813 if (!kvm->arch.ept_identity_map_addr)
6814 kvm->arch.ept_identity_map_addr =
6815 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6816 err = -ENOMEM;
6817 if (alloc_identity_pagetable(kvm) != 0)
6818 goto free_vmcs;
6819 if (!init_rmode_identity_map(kvm))
6820 goto free_vmcs;
6821 }
6822
6823 vmx->nested.current_vmptr = -1ull;
6824 vmx->nested.current_vmcs12 = NULL;
6825
6826 return &vmx->vcpu;
6827
6828free_vmcs:
6829 free_loaded_vmcs(vmx->loaded_vmcs);
6830free_msrs:
6831 kfree(vmx->guest_msrs);
6832uninit_vcpu:
6833 kvm_vcpu_uninit(&vmx->vcpu);
6834free_vcpu:
6835 free_vpid(vmx);
6836 kmem_cache_free(kvm_vcpu_cache, vmx);
6837 return ERR_PTR(err);
6838}
6839
6840static void __init vmx_check_processor_compat(void *rtn)
6841{
6842 struct vmcs_config vmcs_conf;
6843
6844 *(int *)rtn = 0;
6845 if (setup_vmcs_config(&vmcs_conf) < 0)
6846 *(int *)rtn = -EIO;
6847 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6848 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6849 smp_processor_id());
6850 *(int *)rtn = -EIO;
6851 }
6852}
6853
6854static int get_ept_level(void)
6855{
6856 return VMX_EPT_DEFAULT_GAW + 1;
6857}
6858
6859static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6860{
6861 u64 ret;
6862
6863 /* For VT-d and EPT combination
6864 * 1. MMIO: always map as UC
6865 * 2. EPT with VT-d:
6866 * a. VT-d without snooping control feature: can't guarantee the
6867 * result, try to trust guest.
6868 * b. VT-d with snooping control feature: snooping control feature of
6869 * VT-d engine can guarantee the cache correctness. Just set it
6870 * to WB to keep consistent with host. So the same as item 3.
6871 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6872 * consistent with host MTRR
6873 */
6874 if (is_mmio)
6875 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6876 else if (vcpu->kvm->arch.iommu_domain &&
6877 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6878 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6879 VMX_EPT_MT_EPTE_SHIFT;
6880 else
6881 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6882 | VMX_EPT_IPAT_BIT;
6883
6884 return ret;
6885}
6886
6887static int vmx_get_lpage_level(void)
6888{
6889 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6890 return PT_DIRECTORY_LEVEL;
6891 else
6892 /* For shadow and EPT supported 1GB page */
6893 return PT_PDPE_LEVEL;
6894}
6895
6896static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6897{
6898 struct kvm_cpuid_entry2 *best;
6899 struct vcpu_vmx *vmx = to_vmx(vcpu);
6900 u32 exec_control;
6901
6902 vmx->rdtscp_enabled = false;
6903 if (vmx_rdtscp_supported()) {
6904 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6905 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6906 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6907 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6908 vmx->rdtscp_enabled = true;
6909 else {
6910 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6911 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6912 exec_control);
6913 }
6914 }
6915 }
6916
6917 /* Exposing INVPCID only when PCID is exposed */
6918 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6919 if (vmx_invpcid_supported() &&
6920 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6921 guest_cpuid_has_pcid(vcpu)) {
6922 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6923 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6924 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6925 exec_control);
6926 } else {
6927 if (cpu_has_secondary_exec_ctrls()) {
6928 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6929 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6930 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6931 exec_control);
6932 }
6933 if (best)
6934 best->ebx &= ~bit(X86_FEATURE_INVPCID);
6935 }
6936}
6937
6938static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6939{
6940 if (func == 1 && nested)
6941 entry->ecx |= bit(X86_FEATURE_VMX);
6942}
6943
6944/*
6945 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6946 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6947 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6948 * guest in a way that will both be appropriate to L1's requests, and our
6949 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6950 * function also has additional necessary side-effects, like setting various
6951 * vcpu->arch fields.
6952 */
6953static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6954{
6955 struct vcpu_vmx *vmx = to_vmx(vcpu);
6956 u32 exec_control;
6957
6958 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6959 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6960 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6961 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6962 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6963 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6964 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6965 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6966 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6967 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6968 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6969 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6970 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6971 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6972 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6973 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6974 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6975 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6976 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6977 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6978 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6979 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6980 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6981 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6982 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6983 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6984 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6985 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6986 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6987 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6988 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6989 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6990 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6991 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6992 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6993 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6994
6995 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6996 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6997 vmcs12->vm_entry_intr_info_field);
6998 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6999 vmcs12->vm_entry_exception_error_code);
7000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7001 vmcs12->vm_entry_instruction_len);
7002 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7003 vmcs12->guest_interruptibility_info);
7004 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
7005 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7006 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7007 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7008 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7009 vmcs12->guest_pending_dbg_exceptions);
7010 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7011 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7012
7013 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7014
7015 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7016 (vmcs_config.pin_based_exec_ctrl |
7017 vmcs12->pin_based_vm_exec_control));
7018
7019 /*
7020 * Whether page-faults are trapped is determined by a combination of
7021 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7022 * If enable_ept, L0 doesn't care about page faults and we should
7023 * set all of these to L1's desires. However, if !enable_ept, L0 does
7024 * care about (at least some) page faults, and because it is not easy
7025 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7026 * to exit on each and every L2 page fault. This is done by setting
7027 * MASK=MATCH=0 and (see below) EB.PF=1.
7028 * Note that below we don't need special code to set EB.PF beyond the
7029 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7030 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7031 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7032 *
7033 * A problem with this approach (when !enable_ept) is that L1 may be
7034 * injected with more page faults than it asked for. This could have
7035 * caused problems, but in practice existing hypervisors don't care.
7036 * To fix this, we will need to emulate the PFEC checking (on the L1
7037 * page tables), using walk_addr(), when injecting PFs to L1.
7038 */
7039 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7040 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7041 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7042 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7043
7044 if (cpu_has_secondary_exec_ctrls()) {
7045 u32 exec_control = vmx_secondary_exec_control(vmx);
7046 if (!vmx->rdtscp_enabled)
7047 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7048 /* Take the following fields only from vmcs12 */
7049 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7050 if (nested_cpu_has(vmcs12,
7051 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7052 exec_control |= vmcs12->secondary_vm_exec_control;
7053
7054 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7055 /*
7056 * Translate L1 physical address to host physical
7057 * address for vmcs02. Keep the page pinned, so this
7058 * physical address remains valid. We keep a reference
7059 * to it so we can release it later.
7060 */
7061 if (vmx->nested.apic_access_page) /* shouldn't happen */
7062 nested_release_page(vmx->nested.apic_access_page);
7063 vmx->nested.apic_access_page =
7064 nested_get_page(vcpu, vmcs12->apic_access_addr);
7065 /*
7066 * If translation failed, no matter: This feature asks
7067 * to exit when accessing the given address, and if it
7068 * can never be accessed, this feature won't do
7069 * anything anyway.
7070 */
7071 if (!vmx->nested.apic_access_page)
7072 exec_control &=
7073 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7074 else
7075 vmcs_write64(APIC_ACCESS_ADDR,
7076 page_to_phys(vmx->nested.apic_access_page));
7077 }
7078
7079 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7080 }
7081
7082
7083 /*
7084 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7085 * Some constant fields are set here by vmx_set_constant_host_state().
7086 * Other fields are different per CPU, and will be set later when
7087 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7088 */
7089 vmx_set_constant_host_state();
7090
7091 /*
7092 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7093 * entry, but only if the current (host) sp changed from the value
7094 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7095 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7096 * here we just force the write to happen on entry.
7097 */
7098 vmx->host_rsp = 0;
7099
7100 exec_control = vmx_exec_control(vmx); /* L0's desires */
7101 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7102 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7103 exec_control &= ~CPU_BASED_TPR_SHADOW;
7104 exec_control |= vmcs12->cpu_based_vm_exec_control;
7105 /*
7106 * Merging of IO and MSR bitmaps not currently supported.
7107 * Rather, exit every time.
7108 */
7109 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7110 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7111 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7112
7113 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7114
7115 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7116 * bitwise-or of what L1 wants to trap for L2, and what we want to
7117 * trap. Note that CR0.TS also needs updating - we do this later.
7118 */
7119 update_exception_bitmap(vcpu);
7120 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7121 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7122
7123 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7124 vmcs_write32(VM_EXIT_CONTROLS,
7125 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7126 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7127 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7128
7129 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7130 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7131 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7132 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7133
7134
7135 set_cr4_guest_host_mask(vmx);
7136
7137 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7138 vmcs_write64(TSC_OFFSET,
7139 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7140 else
7141 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7142
7143 if (enable_vpid) {
7144 /*
7145 * Trivially support vpid by letting L2s share their parent
7146 * L1's vpid. TODO: move to a more elaborate solution, giving
7147 * each L2 its own vpid and exposing the vpid feature to L1.
7148 */
7149 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7150 vmx_flush_tlb(vcpu);
7151 }
7152
7153 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7154 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7155 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7156 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7157 else
7158 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7159 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7160 vmx_set_efer(vcpu, vcpu->arch.efer);
7161
7162 /*
7163 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7164 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7165 * The CR0_READ_SHADOW is what L2 should have expected to read given
7166 * the specifications by L1; It's not enough to take
7167 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7168 * have more bits than L1 expected.
7169 */
7170 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7171 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7172
7173 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7174 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7175
7176 /* shadow page tables on either EPT or shadow page tables */
7177 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7178 kvm_mmu_reset_context(vcpu);
7179
7180 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7181 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7182}
7183
7184/*
7185 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7186 * for running an L2 nested guest.
7187 */
7188static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7189{
7190 struct vmcs12 *vmcs12;
7191 struct vcpu_vmx *vmx = to_vmx(vcpu);
7192 int cpu;
7193 struct loaded_vmcs *vmcs02;
7194
7195 if (!nested_vmx_check_permission(vcpu) ||
7196 !nested_vmx_check_vmcs12(vcpu))
7197 return 1;
7198
7199 skip_emulated_instruction(vcpu);
7200 vmcs12 = get_vmcs12(vcpu);
7201
7202 /*
7203 * The nested entry process starts with enforcing various prerequisites
7204 * on vmcs12 as required by the Intel SDM, and act appropriately when
7205 * they fail: As the SDM explains, some conditions should cause the
7206 * instruction to fail, while others will cause the instruction to seem
7207 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7208 * To speed up the normal (success) code path, we should avoid checking
7209 * for misconfigurations which will anyway be caught by the processor
7210 * when using the merged vmcs02.
7211 */
7212 if (vmcs12->launch_state == launch) {
7213 nested_vmx_failValid(vcpu,
7214 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7215 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7216 return 1;
7217 }
7218
7219 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7220 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7221 /*TODO: Also verify bits beyond physical address width are 0*/
7222 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7223 return 1;
7224 }
7225
7226 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7227 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7228 /*TODO: Also verify bits beyond physical address width are 0*/
7229 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7230 return 1;
7231 }
7232
7233 if (vmcs12->vm_entry_msr_load_count > 0 ||
7234 vmcs12->vm_exit_msr_load_count > 0 ||
7235 vmcs12->vm_exit_msr_store_count > 0) {
7236 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7237 __func__);
7238 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7239 return 1;
7240 }
7241
7242 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7243 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7244 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7245 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7246 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7247 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7248 !vmx_control_verify(vmcs12->vm_exit_controls,
7249 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7250 !vmx_control_verify(vmcs12->vm_entry_controls,
7251 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7252 {
7253 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7254 return 1;
7255 }
7256
7257 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7258 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7259 nested_vmx_failValid(vcpu,
7260 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7261 return 1;
7262 }
7263
7264 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7265 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7266 nested_vmx_entry_failure(vcpu, vmcs12,
7267 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7268 return 1;
7269 }
7270 if (vmcs12->vmcs_link_pointer != -1ull) {
7271 nested_vmx_entry_failure(vcpu, vmcs12,
7272 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7273 return 1;
7274 }
7275
7276 /*
7277 * We're finally done with prerequisite checking, and can start with
7278 * the nested entry.
7279 */
7280
7281 vmcs02 = nested_get_current_vmcs02(vmx);
7282 if (!vmcs02)
7283 return -ENOMEM;
7284
7285 enter_guest_mode(vcpu);
7286
7287 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7288
7289 cpu = get_cpu();
7290 vmx->loaded_vmcs = vmcs02;
7291 vmx_vcpu_put(vcpu);
7292 vmx_vcpu_load(vcpu, cpu);
7293 vcpu->cpu = cpu;
7294 put_cpu();
7295
7296 vmx_segment_cache_clear(vmx);
7297
7298 vmcs12->launch_state = 1;
7299
7300 prepare_vmcs02(vcpu, vmcs12);
7301
7302 /*
7303 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7304 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7305 * returned as far as L1 is concerned. It will only return (and set
7306 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7307 */
7308 return 1;
7309}
7310
7311/*
7312 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7313 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7314 * This function returns the new value we should put in vmcs12.guest_cr0.
7315 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7316 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7317 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7318 * didn't trap the bit, because if L1 did, so would L0).
7319 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7320 * been modified by L2, and L1 knows it. So just leave the old value of
7321 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7322 * isn't relevant, because if L0 traps this bit it can set it to anything.
7323 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7324 * changed these bits, and therefore they need to be updated, but L0
7325 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7326 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7327 */
7328static inline unsigned long
7329vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7330{
7331 return
7332 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7333 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7334 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7335 vcpu->arch.cr0_guest_owned_bits));
7336}
7337
7338static inline unsigned long
7339vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7340{
7341 return
7342 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7343 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7344 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7345 vcpu->arch.cr4_guest_owned_bits));
7346}
7347
7348/*
7349 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7350 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7351 * and this function updates it to reflect the changes to the guest state while
7352 * L2 was running (and perhaps made some exits which were handled directly by L0
7353 * without going back to L1), and to reflect the exit reason.
7354 * Note that we do not have to copy here all VMCS fields, just those that
7355 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7356 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7357 * which already writes to vmcs12 directly.
7358 */
7359static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7360{
7361 /* update guest state fields: */
7362 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7363 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7364
7365 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7366 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7367 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7368 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7369
7370 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7371 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7372 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7373 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7374 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7375 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7376 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7377 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7378 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7379 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7380 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7381 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7382 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7383 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7384 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7385 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7386 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7387 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7388 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7389 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7390 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7391 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7392 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7393 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7394 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7395 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7396 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7397 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7398 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7399 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7400 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7401 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7402 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7403 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7404 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7405 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7406
7407 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7408 vmcs12->guest_interruptibility_info =
7409 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7410 vmcs12->guest_pending_dbg_exceptions =
7411 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7412
7413 /* TODO: These cannot have changed unless we have MSR bitmaps and
7414 * the relevant bit asks not to trap the change */
7415 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7416 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7417 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7418 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7419 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7420 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7421
7422 /* update exit information fields: */
7423
7424 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
7425 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7426
7427 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7428 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7429 vmcs12->idt_vectoring_info_field = to_vmx(vcpu)->idt_vectoring_info;
7430 vmcs12->idt_vectoring_error_code =
7431 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7432 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7433 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7434
7435 /* clear vm-entry fields which are to be cleared on exit */
7436 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7437 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7438}
7439
7440/*
7441 * A part of what we need to when the nested L2 guest exits and we want to
7442 * run its L1 parent, is to reset L1's guest state to the host state specified
7443 * in vmcs12.
7444 * This function is to be called not only on normal nested exit, but also on
7445 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7446 * Failures During or After Loading Guest State").
7447 * This function should be called when the active VMCS is L1's (vmcs01).
7448 */
7449static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7450 struct vmcs12 *vmcs12)
7451{
7452 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7453 vcpu->arch.efer = vmcs12->host_ia32_efer;
7454 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7455 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7456 else
7457 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7458 vmx_set_efer(vcpu, vcpu->arch.efer);
7459
7460 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7461 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7462 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
7463 /*
7464 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7465 * actually changed, because it depends on the current state of
7466 * fpu_active (which may have changed).
7467 * Note that vmx_set_cr0 refers to efer set above.
7468 */
7469 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7470 /*
7471 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7472 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7473 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7474 */
7475 update_exception_bitmap(vcpu);
7476 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7477 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7478
7479 /*
7480 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7481 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7482 */
7483 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7484 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7485
7486 /* shadow page tables on either EPT or shadow page tables */
7487 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7488 kvm_mmu_reset_context(vcpu);
7489
7490 if (enable_vpid) {
7491 /*
7492 * Trivially support vpid by letting L2s share their parent
7493 * L1's vpid. TODO: move to a more elaborate solution, giving
7494 * each L2 its own vpid and exposing the vpid feature to L1.
7495 */
7496 vmx_flush_tlb(vcpu);
7497 }
7498
7499
7500 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7501 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7502 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7503 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7504 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7505 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7506 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7507 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7508 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7509 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7510 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7511 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7512 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7513 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7514 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7515
7516 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7517 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7518 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7519 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7520 vmcs12->host_ia32_perf_global_ctrl);
7521
7522 kvm_set_dr(vcpu, 7, 0x400);
7523 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
7524}
7525
7526/*
7527 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7528 * and modify vmcs12 to make it see what it would expect to see there if
7529 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7530 */
7531static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7532{
7533 struct vcpu_vmx *vmx = to_vmx(vcpu);
7534 int cpu;
7535 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7536
7537 leave_guest_mode(vcpu);
7538 prepare_vmcs12(vcpu, vmcs12);
7539
7540 cpu = get_cpu();
7541 vmx->loaded_vmcs = &vmx->vmcs01;
7542 vmx_vcpu_put(vcpu);
7543 vmx_vcpu_load(vcpu, cpu);
7544 vcpu->cpu = cpu;
7545 put_cpu();
7546
7547 vmx_segment_cache_clear(vmx);
7548
7549 /* if no vmcs02 cache requested, remove the one we used */
7550 if (VMCS02_POOL_SIZE == 0)
7551 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7552
7553 load_vmcs12_host_state(vcpu, vmcs12);
7554
7555 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7556 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7557
7558 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7559 vmx->host_rsp = 0;
7560
7561 /* Unpin physical memory we referred to in vmcs02 */
7562 if (vmx->nested.apic_access_page) {
7563 nested_release_page(vmx->nested.apic_access_page);
7564 vmx->nested.apic_access_page = 0;
7565 }
7566
7567 /*
7568 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7569 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7570 * success or failure flag accordingly.
7571 */
7572 if (unlikely(vmx->fail)) {
7573 vmx->fail = 0;
7574 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7575 } else
7576 nested_vmx_succeed(vcpu);
7577}
7578
7579/*
7580 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7581 * 23.7 "VM-entry failures during or after loading guest state" (this also
7582 * lists the acceptable exit-reason and exit-qualification parameters).
7583 * It should only be called before L2 actually succeeded to run, and when
7584 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7585 */
7586static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7587 struct vmcs12 *vmcs12,
7588 u32 reason, unsigned long qualification)
7589{
7590 load_vmcs12_host_state(vcpu, vmcs12);
7591 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7592 vmcs12->exit_qualification = qualification;
7593 nested_vmx_succeed(vcpu);
7594}
7595
7596static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7597 struct x86_instruction_info *info,
7598 enum x86_intercept_stage stage)
7599{
7600 return X86EMUL_CONTINUE;
7601}
7602
7603static struct kvm_x86_ops vmx_x86_ops = {
7604 .cpu_has_kvm_support = cpu_has_kvm_support,
7605 .disabled_by_bios = vmx_disabled_by_bios,
7606 .hardware_setup = hardware_setup,
7607 .hardware_unsetup = hardware_unsetup,
7608 .check_processor_compatibility = vmx_check_processor_compat,
7609 .hardware_enable = hardware_enable,
7610 .hardware_disable = hardware_disable,
7611 .cpu_has_accelerated_tpr = report_flexpriority,
7612
7613 .vcpu_create = vmx_create_vcpu,
7614 .vcpu_free = vmx_free_vcpu,
7615 .vcpu_reset = vmx_vcpu_reset,
7616
7617 .prepare_guest_switch = vmx_save_host_state,
7618 .vcpu_load = vmx_vcpu_load,
7619 .vcpu_put = vmx_vcpu_put,
7620
7621 .update_db_bp_intercept = update_exception_bitmap,
7622 .get_msr = vmx_get_msr,
7623 .set_msr = vmx_set_msr,
7624 .get_segment_base = vmx_get_segment_base,
7625 .get_segment = vmx_get_segment,
7626 .set_segment = vmx_set_segment,
7627 .get_cpl = vmx_get_cpl,
7628 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7629 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7630 .decache_cr3 = vmx_decache_cr3,
7631 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7632 .set_cr0 = vmx_set_cr0,
7633 .set_cr3 = vmx_set_cr3,
7634 .set_cr4 = vmx_set_cr4,
7635 .set_efer = vmx_set_efer,
7636 .get_idt = vmx_get_idt,
7637 .set_idt = vmx_set_idt,
7638 .get_gdt = vmx_get_gdt,
7639 .set_gdt = vmx_set_gdt,
7640 .set_dr7 = vmx_set_dr7,
7641 .cache_reg = vmx_cache_reg,
7642 .get_rflags = vmx_get_rflags,
7643 .set_rflags = vmx_set_rflags,
7644 .fpu_activate = vmx_fpu_activate,
7645 .fpu_deactivate = vmx_fpu_deactivate,
7646
7647 .tlb_flush = vmx_flush_tlb,
7648
7649 .run = vmx_vcpu_run,
7650 .handle_exit = vmx_handle_exit,
7651 .skip_emulated_instruction = skip_emulated_instruction,
7652 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7653 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7654 .patch_hypercall = vmx_patch_hypercall,
7655 .set_irq = vmx_inject_irq,
7656 .set_nmi = vmx_inject_nmi,
7657 .queue_exception = vmx_queue_exception,
7658 .cancel_injection = vmx_cancel_injection,
7659 .interrupt_allowed = vmx_interrupt_allowed,
7660 .nmi_allowed = vmx_nmi_allowed,
7661 .get_nmi_mask = vmx_get_nmi_mask,
7662 .set_nmi_mask = vmx_set_nmi_mask,
7663 .enable_nmi_window = enable_nmi_window,
7664 .enable_irq_window = enable_irq_window,
7665 .update_cr8_intercept = update_cr8_intercept,
7666 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
7667 .vm_has_apicv = vmx_vm_has_apicv,
7668 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7669 .hwapic_irr_update = vmx_hwapic_irr_update,
7670 .hwapic_isr_update = vmx_hwapic_isr_update,
7671
7672 .set_tss_addr = vmx_set_tss_addr,
7673 .get_tdp_level = get_ept_level,
7674 .get_mt_mask = vmx_get_mt_mask,
7675
7676 .get_exit_info = vmx_get_exit_info,
7677
7678 .get_lpage_level = vmx_get_lpage_level,
7679
7680 .cpuid_update = vmx_cpuid_update,
7681
7682 .rdtscp_supported = vmx_rdtscp_supported,
7683 .invpcid_supported = vmx_invpcid_supported,
7684
7685 .set_supported_cpuid = vmx_set_supported_cpuid,
7686
7687 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7688
7689 .set_tsc_khz = vmx_set_tsc_khz,
7690 .read_tsc_offset = vmx_read_tsc_offset,
7691 .write_tsc_offset = vmx_write_tsc_offset,
7692 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7693 .compute_tsc_offset = vmx_compute_tsc_offset,
7694 .read_l1_tsc = vmx_read_l1_tsc,
7695
7696 .set_tdp_cr3 = vmx_set_cr3,
7697
7698 .check_intercept = vmx_check_intercept,
7699};
7700
7701static int __init vmx_init(void)
7702{
7703 int r, i, msr;
7704
7705 rdmsrl_safe(MSR_EFER, &host_efer);
7706
7707 for (i = 0; i < NR_VMX_MSR; ++i)
7708 kvm_define_shared_msr(i, vmx_msr_index[i]);
7709
7710 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7711 if (!vmx_io_bitmap_a)
7712 return -ENOMEM;
7713
7714 r = -ENOMEM;
7715
7716 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7717 if (!vmx_io_bitmap_b)
7718 goto out;
7719
7720 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7721 if (!vmx_msr_bitmap_legacy)
7722 goto out1;
7723
7724 vmx_msr_bitmap_legacy_x2apic =
7725 (unsigned long *)__get_free_page(GFP_KERNEL);
7726 if (!vmx_msr_bitmap_legacy_x2apic)
7727 goto out2;
7728
7729 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7730 if (!vmx_msr_bitmap_longmode)
7731 goto out3;
7732
7733 vmx_msr_bitmap_longmode_x2apic =
7734 (unsigned long *)__get_free_page(GFP_KERNEL);
7735 if (!vmx_msr_bitmap_longmode_x2apic)
7736 goto out4;
7737
7738 /*
7739 * Allow direct access to the PC debug port (it is often used for I/O
7740 * delays, but the vmexits simply slow things down).
7741 */
7742 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7743 clear_bit(0x80, vmx_io_bitmap_a);
7744
7745 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7746
7747 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7748 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7749
7750 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7751
7752 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7753 __alignof__(struct vcpu_vmx), THIS_MODULE);
7754 if (r)
7755 goto out3;
7756
7757#ifdef CONFIG_KEXEC
7758 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7759 crash_vmclear_local_loaded_vmcss);
7760#endif
7761
7762 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7763 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7764 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7765 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7766 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7767 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7768 memcpy(vmx_msr_bitmap_legacy_x2apic,
7769 vmx_msr_bitmap_legacy, PAGE_SIZE);
7770 memcpy(vmx_msr_bitmap_longmode_x2apic,
7771 vmx_msr_bitmap_longmode, PAGE_SIZE);
7772
7773 if (enable_apicv_reg_vid) {
7774 for (msr = 0x800; msr <= 0x8ff; msr++)
7775 vmx_disable_intercept_msr_read_x2apic(msr);
7776
7777 /* According SDM, in x2apic mode, the whole id reg is used.
7778 * But in KVM, it only use the highest eight bits. Need to
7779 * intercept it */
7780 vmx_enable_intercept_msr_read_x2apic(0x802);
7781 /* TMCCT */
7782 vmx_enable_intercept_msr_read_x2apic(0x839);
7783 /* TPR */
7784 vmx_disable_intercept_msr_write_x2apic(0x808);
7785 /* EOI */
7786 vmx_disable_intercept_msr_write_x2apic(0x80b);
7787 /* SELF-IPI */
7788 vmx_disable_intercept_msr_write_x2apic(0x83f);
7789 }
7790
7791 if (enable_ept) {
7792 kvm_mmu_set_mask_ptes(0ull,
7793 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7794 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7795 0ull, VMX_EPT_EXECUTABLE_MASK);
7796 ept_set_mmio_spte_mask();
7797 kvm_enable_tdp();
7798 } else
7799 kvm_disable_tdp();
7800
7801 return 0;
7802
7803out4:
7804 free_page((unsigned long)vmx_msr_bitmap_longmode);
7805out3:
7806 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7807out2:
7808 free_page((unsigned long)vmx_msr_bitmap_legacy);
7809out1:
7810 free_page((unsigned long)vmx_io_bitmap_b);
7811out:
7812 free_page((unsigned long)vmx_io_bitmap_a);
7813 return r;
7814}
7815
7816static void __exit vmx_exit(void)
7817{
7818 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7819 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
7820 free_page((unsigned long)vmx_msr_bitmap_legacy);
7821 free_page((unsigned long)vmx_msr_bitmap_longmode);
7822 free_page((unsigned long)vmx_io_bitmap_b);
7823 free_page((unsigned long)vmx_io_bitmap_a);
7824
7825#ifdef CONFIG_KEXEC
7826 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7827 synchronize_rcu();
7828#endif
7829
7830 kvm_exit();
7831}
7832
7833module_init(vmx_init)
7834module_exit(vmx_exit)
Linux kernel - Deliverables
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