| 1 | /* Xtensa configuration-specific ISA information. |
| 2 | Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of BFD, the Binary File Descriptor library. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or |
| 7 | modify it under the terms of the GNU General Public License as |
| 8 | published by the Free Software Foundation; either version 3 of the |
| 9 | License, or (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ |
| 20 | |
| 21 | #include "ansidecl.h" |
| 22 | #include <xtensa-isa.h> |
| 23 | #include "xtensa-isa-internal.h" |
| 24 | |
| 25 | \f |
| 26 | /* Sysregs. */ |
| 27 | |
| 28 | static xtensa_sysreg_internal sysregs[] = { |
| 29 | { "LBEG", 0, 0 }, |
| 30 | { "LEND", 1, 0 }, |
| 31 | { "LCOUNT", 2, 0 }, |
| 32 | { "PTEVADDR", 83, 0 }, |
| 33 | { "MMID", 89, 0 }, |
| 34 | { "DDR", 104, 0 }, |
| 35 | { "176", 176, 0 }, |
| 36 | { "208", 208, 0 }, |
| 37 | { "INTERRUPT", 226, 0 }, |
| 38 | { "INTCLEAR", 227, 0 }, |
| 39 | { "CCOUNT", 234, 0 }, |
| 40 | { "PRID", 235, 0 }, |
| 41 | { "ICOUNT", 236, 0 }, |
| 42 | { "CCOMPARE0", 240, 0 }, |
| 43 | { "CCOMPARE1", 241, 0 }, |
| 44 | { "CCOMPARE2", 242, 0 }, |
| 45 | { "VECBASE", 231, 0 }, |
| 46 | { "EPC1", 177, 0 }, |
| 47 | { "EPC2", 178, 0 }, |
| 48 | { "EPC3", 179, 0 }, |
| 49 | { "EPC4", 180, 0 }, |
| 50 | { "EPC5", 181, 0 }, |
| 51 | { "EPC6", 182, 0 }, |
| 52 | { "EPC7", 183, 0 }, |
| 53 | { "EXCSAVE1", 209, 0 }, |
| 54 | { "EXCSAVE2", 210, 0 }, |
| 55 | { "EXCSAVE3", 211, 0 }, |
| 56 | { "EXCSAVE4", 212, 0 }, |
| 57 | { "EXCSAVE5", 213, 0 }, |
| 58 | { "EXCSAVE6", 214, 0 }, |
| 59 | { "EXCSAVE7", 215, 0 }, |
| 60 | { "EPS2", 194, 0 }, |
| 61 | { "EPS3", 195, 0 }, |
| 62 | { "EPS4", 196, 0 }, |
| 63 | { "EPS5", 197, 0 }, |
| 64 | { "EPS6", 198, 0 }, |
| 65 | { "EPS7", 199, 0 }, |
| 66 | { "EXCCAUSE", 232, 0 }, |
| 67 | { "DEPC", 192, 0 }, |
| 68 | { "EXCVADDR", 238, 0 }, |
| 69 | { "WINDOWBASE", 72, 0 }, |
| 70 | { "WINDOWSTART", 73, 0 }, |
| 71 | { "SAR", 3, 0 }, |
| 72 | { "LITBASE", 5, 0 }, |
| 73 | { "PS", 230, 0 }, |
| 74 | { "MISC0", 244, 0 }, |
| 75 | { "MISC1", 245, 0 }, |
| 76 | { "INTENABLE", 228, 0 }, |
| 77 | { "DBREAKA0", 144, 0 }, |
| 78 | { "DBREAKC0", 160, 0 }, |
| 79 | { "DBREAKA1", 145, 0 }, |
| 80 | { "DBREAKC1", 161, 0 }, |
| 81 | { "IBREAKA0", 128, 0 }, |
| 82 | { "IBREAKA1", 129, 0 }, |
| 83 | { "IBREAKENABLE", 96, 0 }, |
| 84 | { "ICOUNTLEVEL", 237, 0 }, |
| 85 | { "DEBUGCAUSE", 233, 0 }, |
| 86 | { "RASID", 90, 0 }, |
| 87 | { "ITLBCFG", 91, 0 }, |
| 88 | { "DTLBCFG", 92, 0 }, |
| 89 | { "CPENABLE", 224, 0 }, |
| 90 | { "SCOMPARE1", 12, 0 }, |
| 91 | { "THREADPTR", 231, 1 } |
| 92 | }; |
| 93 | |
| 94 | #define NUM_SYSREGS 63 |
| 95 | #define MAX_SPECIAL_REG 245 |
| 96 | #define MAX_USER_REG 231 |
| 97 | |
| 98 | \f |
| 99 | /* Processor states. */ |
| 100 | |
| 101 | static xtensa_state_internal states[] = { |
| 102 | { "LCOUNT", 32, 0 }, |
| 103 | { "PC", 32, 0 }, |
| 104 | { "ICOUNT", 32, 0 }, |
| 105 | { "DDR", 32, 0 }, |
| 106 | { "INTERRUPT", 22, 0 }, |
| 107 | { "CCOUNT", 32, 0 }, |
| 108 | { "XTSYNC", 1, 0 }, |
| 109 | { "VECBASE", 22, 0 }, |
| 110 | { "EPC1", 32, 0 }, |
| 111 | { "EPC2", 32, 0 }, |
| 112 | { "EPC3", 32, 0 }, |
| 113 | { "EPC4", 32, 0 }, |
| 114 | { "EPC5", 32, 0 }, |
| 115 | { "EPC6", 32, 0 }, |
| 116 | { "EPC7", 32, 0 }, |
| 117 | { "EXCSAVE1", 32, 0 }, |
| 118 | { "EXCSAVE2", 32, 0 }, |
| 119 | { "EXCSAVE3", 32, 0 }, |
| 120 | { "EXCSAVE4", 32, 0 }, |
| 121 | { "EXCSAVE5", 32, 0 }, |
| 122 | { "EXCSAVE6", 32, 0 }, |
| 123 | { "EXCSAVE7", 32, 0 }, |
| 124 | { "EPS2", 15, 0 }, |
| 125 | { "EPS3", 15, 0 }, |
| 126 | { "EPS4", 15, 0 }, |
| 127 | { "EPS5", 15, 0 }, |
| 128 | { "EPS6", 15, 0 }, |
| 129 | { "EPS7", 15, 0 }, |
| 130 | { "EXCCAUSE", 6, 0 }, |
| 131 | { "PSINTLEVEL", 4, 0 }, |
| 132 | { "PSUM", 1, 0 }, |
| 133 | { "PSWOE", 1, 0 }, |
| 134 | { "PSRING", 2, 0 }, |
| 135 | { "PSEXCM", 1, 0 }, |
| 136 | { "DEPC", 32, 0 }, |
| 137 | { "EXCVADDR", 32, 0 }, |
| 138 | { "WindowBase", 3, 0 }, |
| 139 | { "WindowStart", 8, 0 }, |
| 140 | { "PSCALLINC", 2, 0 }, |
| 141 | { "PSOWB", 4, 0 }, |
| 142 | { "LBEG", 32, 0 }, |
| 143 | { "LEND", 32, 0 }, |
| 144 | { "SAR", 6, 0 }, |
| 145 | { "THREADPTR", 32, 0 }, |
| 146 | { "LITBADDR", 20, 0 }, |
| 147 | { "LITBEN", 1, 0 }, |
| 148 | { "MISC0", 32, 0 }, |
| 149 | { "MISC1", 32, 0 }, |
| 150 | { "InOCDMode", 1, 0 }, |
| 151 | { "INTENABLE", 22, 0 }, |
| 152 | { "DBREAKA0", 32, 0 }, |
| 153 | { "DBREAKC0", 8, 0 }, |
| 154 | { "DBREAKA1", 32, 0 }, |
| 155 | { "DBREAKC1", 8, 0 }, |
| 156 | { "IBREAKA0", 32, 0 }, |
| 157 | { "IBREAKA1", 32, 0 }, |
| 158 | { "IBREAKENABLE", 2, 0 }, |
| 159 | { "ICOUNTLEVEL", 4, 0 }, |
| 160 | { "DEBUGCAUSE", 6, 0 }, |
| 161 | { "DBNUM", 4, 0 }, |
| 162 | { "CCOMPARE0", 32, 0 }, |
| 163 | { "CCOMPARE1", 32, 0 }, |
| 164 | { "CCOMPARE2", 32, 0 }, |
| 165 | { "ASID3", 8, 0 }, |
| 166 | { "ASID2", 8, 0 }, |
| 167 | { "ASID1", 8, 0 }, |
| 168 | { "INSTPGSZID4", 2, 0 }, |
| 169 | { "DATAPGSZID4", 2, 0 }, |
| 170 | { "PTBASE", 10, 0 }, |
| 171 | { "CPENABLE", 8, 0 }, |
| 172 | { "SCOMPARE1", 32, 0 } |
| 173 | }; |
| 174 | |
| 175 | #define NUM_STATES 71 |
| 176 | |
| 177 | enum xtensa_state_id { |
| 178 | STATE_LCOUNT, |
| 179 | STATE_PC, |
| 180 | STATE_ICOUNT, |
| 181 | STATE_DDR, |
| 182 | STATE_INTERRUPT, |
| 183 | STATE_CCOUNT, |
| 184 | STATE_XTSYNC, |
| 185 | STATE_VECBASE, |
| 186 | STATE_EPC1, |
| 187 | STATE_EPC2, |
| 188 | STATE_EPC3, |
| 189 | STATE_EPC4, |
| 190 | STATE_EPC5, |
| 191 | STATE_EPC6, |
| 192 | STATE_EPC7, |
| 193 | STATE_EXCSAVE1, |
| 194 | STATE_EXCSAVE2, |
| 195 | STATE_EXCSAVE3, |
| 196 | STATE_EXCSAVE4, |
| 197 | STATE_EXCSAVE5, |
| 198 | STATE_EXCSAVE6, |
| 199 | STATE_EXCSAVE7, |
| 200 | STATE_EPS2, |
| 201 | STATE_EPS3, |
| 202 | STATE_EPS4, |
| 203 | STATE_EPS5, |
| 204 | STATE_EPS6, |
| 205 | STATE_EPS7, |
| 206 | STATE_EXCCAUSE, |
| 207 | STATE_PSINTLEVEL, |
| 208 | STATE_PSUM, |
| 209 | STATE_PSWOE, |
| 210 | STATE_PSRING, |
| 211 | STATE_PSEXCM, |
| 212 | STATE_DEPC, |
| 213 | STATE_EXCVADDR, |
| 214 | STATE_WindowBase, |
| 215 | STATE_WindowStart, |
| 216 | STATE_PSCALLINC, |
| 217 | STATE_PSOWB, |
| 218 | STATE_LBEG, |
| 219 | STATE_LEND, |
| 220 | STATE_SAR, |
| 221 | STATE_THREADPTR, |
| 222 | STATE_LITBADDR, |
| 223 | STATE_LITBEN, |
| 224 | STATE_MISC0, |
| 225 | STATE_MISC1, |
| 226 | STATE_InOCDMode, |
| 227 | STATE_INTENABLE, |
| 228 | STATE_DBREAKA0, |
| 229 | STATE_DBREAKC0, |
| 230 | STATE_DBREAKA1, |
| 231 | STATE_DBREAKC1, |
| 232 | STATE_IBREAKA0, |
| 233 | STATE_IBREAKA1, |
| 234 | STATE_IBREAKENABLE, |
| 235 | STATE_ICOUNTLEVEL, |
| 236 | STATE_DEBUGCAUSE, |
| 237 | STATE_DBNUM, |
| 238 | STATE_CCOMPARE0, |
| 239 | STATE_CCOMPARE1, |
| 240 | STATE_CCOMPARE2, |
| 241 | STATE_ASID3, |
| 242 | STATE_ASID2, |
| 243 | STATE_ASID1, |
| 244 | STATE_INSTPGSZID4, |
| 245 | STATE_DATAPGSZID4, |
| 246 | STATE_PTBASE, |
| 247 | STATE_CPENABLE, |
| 248 | STATE_SCOMPARE1 |
| 249 | }; |
| 250 | |
| 251 | \f |
| 252 | /* Field definitions. */ |
| 253 | |
| 254 | static unsigned |
| 255 | Field_t_Slot_inst_get (const xtensa_insnbuf insn) |
| 256 | { |
| 257 | unsigned tie_t = 0; |
| 258 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 259 | return tie_t; |
| 260 | } |
| 261 | |
| 262 | static void |
| 263 | Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 264 | { |
| 265 | uint32 tie_t; |
| 266 | tie_t = (val << 28) >> 28; |
| 267 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 268 | } |
| 269 | |
| 270 | static unsigned |
| 271 | Field_s_Slot_inst_get (const xtensa_insnbuf insn) |
| 272 | { |
| 273 | unsigned tie_t = 0; |
| 274 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 275 | return tie_t; |
| 276 | } |
| 277 | |
| 278 | static void |
| 279 | Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 280 | { |
| 281 | uint32 tie_t; |
| 282 | tie_t = (val << 28) >> 28; |
| 283 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 284 | } |
| 285 | |
| 286 | static unsigned |
| 287 | Field_r_Slot_inst_get (const xtensa_insnbuf insn) |
| 288 | { |
| 289 | unsigned tie_t = 0; |
| 290 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 291 | return tie_t; |
| 292 | } |
| 293 | |
| 294 | static void |
| 295 | Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 296 | { |
| 297 | uint32 tie_t; |
| 298 | tie_t = (val << 28) >> 28; |
| 299 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 300 | } |
| 301 | |
| 302 | static unsigned |
| 303 | Field_op2_Slot_inst_get (const xtensa_insnbuf insn) |
| 304 | { |
| 305 | unsigned tie_t = 0; |
| 306 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 307 | return tie_t; |
| 308 | } |
| 309 | |
| 310 | static void |
| 311 | Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 312 | { |
| 313 | uint32 tie_t; |
| 314 | tie_t = (val << 28) >> 28; |
| 315 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 316 | } |
| 317 | |
| 318 | static unsigned |
| 319 | Field_op1_Slot_inst_get (const xtensa_insnbuf insn) |
| 320 | { |
| 321 | unsigned tie_t = 0; |
| 322 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 323 | return tie_t; |
| 324 | } |
| 325 | |
| 326 | static void |
| 327 | Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 328 | { |
| 329 | uint32 tie_t; |
| 330 | tie_t = (val << 28) >> 28; |
| 331 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 332 | } |
| 333 | |
| 334 | static unsigned |
| 335 | Field_op0_Slot_inst_get (const xtensa_insnbuf insn) |
| 336 | { |
| 337 | unsigned tie_t = 0; |
| 338 | tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); |
| 339 | return tie_t; |
| 340 | } |
| 341 | |
| 342 | static void |
| 343 | Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 344 | { |
| 345 | uint32 tie_t; |
| 346 | tie_t = (val << 28) >> 28; |
| 347 | insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); |
| 348 | } |
| 349 | |
| 350 | static unsigned |
| 351 | Field_n_Slot_inst_get (const xtensa_insnbuf insn) |
| 352 | { |
| 353 | unsigned tie_t = 0; |
| 354 | tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); |
| 355 | return tie_t; |
| 356 | } |
| 357 | |
| 358 | static void |
| 359 | Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 360 | { |
| 361 | uint32 tie_t; |
| 362 | tie_t = (val << 30) >> 30; |
| 363 | insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); |
| 364 | } |
| 365 | |
| 366 | static unsigned |
| 367 | Field_m_Slot_inst_get (const xtensa_insnbuf insn) |
| 368 | { |
| 369 | unsigned tie_t = 0; |
| 370 | tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); |
| 371 | return tie_t; |
| 372 | } |
| 373 | |
| 374 | static void |
| 375 | Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 376 | { |
| 377 | uint32 tie_t; |
| 378 | tie_t = (val << 30) >> 30; |
| 379 | insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); |
| 380 | } |
| 381 | |
| 382 | static unsigned |
| 383 | Field_sr_Slot_inst_get (const xtensa_insnbuf insn) |
| 384 | { |
| 385 | unsigned tie_t = 0; |
| 386 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 387 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 388 | return tie_t; |
| 389 | } |
| 390 | |
| 391 | static void |
| 392 | Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 393 | { |
| 394 | uint32 tie_t; |
| 395 | tie_t = (val << 28) >> 28; |
| 396 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 397 | tie_t = (val << 24) >> 28; |
| 398 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 399 | } |
| 400 | |
| 401 | static unsigned |
| 402 | Field_st_Slot_inst_get (const xtensa_insnbuf insn) |
| 403 | { |
| 404 | unsigned tie_t = 0; |
| 405 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 406 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 407 | return tie_t; |
| 408 | } |
| 409 | |
| 410 | static void |
| 411 | Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 412 | { |
| 413 | uint32 tie_t; |
| 414 | tie_t = (val << 28) >> 28; |
| 415 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 416 | tie_t = (val << 24) >> 28; |
| 417 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 418 | } |
| 419 | |
| 420 | static unsigned |
| 421 | Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) |
| 422 | { |
| 423 | unsigned tie_t = 0; |
| 424 | tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); |
| 425 | return tie_t; |
| 426 | } |
| 427 | |
| 428 | static void |
| 429 | Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 430 | { |
| 431 | uint32 tie_t; |
| 432 | tie_t = (val << 29) >> 29; |
| 433 | insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); |
| 434 | } |
| 435 | |
| 436 | static unsigned |
| 437 | Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 438 | { |
| 439 | unsigned tie_t = 0; |
| 440 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 441 | return tie_t; |
| 442 | } |
| 443 | |
| 444 | static void |
| 445 | Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 446 | { |
| 447 | uint32 tie_t; |
| 448 | tie_t = (val << 28) >> 28; |
| 449 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 450 | } |
| 451 | |
| 452 | static unsigned |
| 453 | Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 454 | { |
| 455 | unsigned tie_t = 0; |
| 456 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 457 | return tie_t; |
| 458 | } |
| 459 | |
| 460 | static void |
| 461 | Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 462 | { |
| 463 | uint32 tie_t; |
| 464 | tie_t = (val << 28) >> 28; |
| 465 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 466 | } |
| 467 | |
| 468 | static unsigned |
| 469 | Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 470 | { |
| 471 | unsigned tie_t = 0; |
| 472 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 473 | return tie_t; |
| 474 | } |
| 475 | |
| 476 | static void |
| 477 | Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 478 | { |
| 479 | uint32 tie_t; |
| 480 | tie_t = (val << 28) >> 28; |
| 481 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 482 | } |
| 483 | |
| 484 | static unsigned |
| 485 | Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 486 | { |
| 487 | unsigned tie_t = 0; |
| 488 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 489 | return tie_t; |
| 490 | } |
| 491 | |
| 492 | static void |
| 493 | Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 494 | { |
| 495 | uint32 tie_t; |
| 496 | tie_t = (val << 28) >> 28; |
| 497 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 498 | } |
| 499 | |
| 500 | static unsigned |
| 501 | Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 502 | { |
| 503 | unsigned tie_t = 0; |
| 504 | tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); |
| 505 | return tie_t; |
| 506 | } |
| 507 | |
| 508 | static void |
| 509 | Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 510 | { |
| 511 | uint32 tie_t; |
| 512 | tie_t = (val << 31) >> 31; |
| 513 | insn[0] = (insn[0] & ~0x400) | (tie_t << 10); |
| 514 | } |
| 515 | |
| 516 | static unsigned |
| 517 | Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 518 | { |
| 519 | unsigned tie_t = 0; |
| 520 | tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); |
| 521 | return tie_t; |
| 522 | } |
| 523 | |
| 524 | static void |
| 525 | Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 526 | { |
| 527 | uint32 tie_t; |
| 528 | tie_t = (val << 31) >> 31; |
| 529 | insn[0] = (insn[0] & ~0x800) | (tie_t << 11); |
| 530 | } |
| 531 | |
| 532 | static unsigned |
| 533 | Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 534 | { |
| 535 | unsigned tie_t = 0; |
| 536 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 537 | return tie_t; |
| 538 | } |
| 539 | |
| 540 | static void |
| 541 | Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 542 | { |
| 543 | uint32 tie_t; |
| 544 | tie_t = (val << 28) >> 28; |
| 545 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 546 | } |
| 547 | |
| 548 | static unsigned |
| 549 | Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 550 | { |
| 551 | unsigned tie_t = 0; |
| 552 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 553 | return tie_t; |
| 554 | } |
| 555 | |
| 556 | static void |
| 557 | Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 558 | { |
| 559 | uint32 tie_t; |
| 560 | tie_t = (val << 28) >> 28; |
| 561 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 562 | } |
| 563 | |
| 564 | static unsigned |
| 565 | Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) |
| 566 | { |
| 567 | unsigned tie_t = 0; |
| 568 | tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); |
| 569 | return tie_t; |
| 570 | } |
| 571 | |
| 572 | static void |
| 573 | Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 574 | { |
| 575 | uint32 tie_t; |
| 576 | tie_t = (val << 31) >> 31; |
| 577 | insn[0] = (insn[0] & ~0x100) | (tie_t << 8); |
| 578 | } |
| 579 | |
| 580 | static unsigned |
| 581 | Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) |
| 582 | { |
| 583 | unsigned tie_t = 0; |
| 584 | tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); |
| 585 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 586 | return tie_t; |
| 587 | } |
| 588 | |
| 589 | static void |
| 590 | Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 591 | { |
| 592 | uint32 tie_t; |
| 593 | tie_t = (val << 28) >> 28; |
| 594 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 595 | tie_t = (val << 27) >> 31; |
| 596 | insn[0] = (insn[0] & ~0x100) | (tie_t << 8); |
| 597 | } |
| 598 | |
| 599 | static unsigned |
| 600 | Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) |
| 601 | { |
| 602 | unsigned tie_t = 0; |
| 603 | tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); |
| 604 | return tie_t; |
| 605 | } |
| 606 | |
| 607 | static void |
| 608 | Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 609 | { |
| 610 | uint32 tie_t; |
| 611 | tie_t = (val << 20) >> 20; |
| 612 | insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); |
| 613 | } |
| 614 | |
| 615 | static unsigned |
| 616 | Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) |
| 617 | { |
| 618 | unsigned tie_t = 0; |
| 619 | tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); |
| 620 | return tie_t; |
| 621 | } |
| 622 | |
| 623 | static void |
| 624 | Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 625 | { |
| 626 | uint32 tie_t; |
| 627 | tie_t = (val << 24) >> 24; |
| 628 | insn[0] = (insn[0] & ~0xff) | (tie_t << 0); |
| 629 | } |
| 630 | |
| 631 | static unsigned |
| 632 | Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 633 | { |
| 634 | unsigned tie_t = 0; |
| 635 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 636 | return tie_t; |
| 637 | } |
| 638 | |
| 639 | static void |
| 640 | Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 641 | { |
| 642 | uint32 tie_t; |
| 643 | tie_t = (val << 28) >> 28; |
| 644 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 645 | } |
| 646 | |
| 647 | static unsigned |
| 648 | Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) |
| 649 | { |
| 650 | unsigned tie_t = 0; |
| 651 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 652 | tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); |
| 653 | return tie_t; |
| 654 | } |
| 655 | |
| 656 | static void |
| 657 | Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 658 | { |
| 659 | uint32 tie_t; |
| 660 | tie_t = (val << 24) >> 24; |
| 661 | insn[0] = (insn[0] & ~0xff) | (tie_t << 0); |
| 662 | tie_t = (val << 20) >> 28; |
| 663 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 664 | } |
| 665 | |
| 666 | static unsigned |
| 667 | Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) |
| 668 | { |
| 669 | unsigned tie_t = 0; |
| 670 | tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); |
| 671 | return tie_t; |
| 672 | } |
| 673 | |
| 674 | static void |
| 675 | Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 676 | { |
| 677 | uint32 tie_t; |
| 678 | tie_t = (val << 16) >> 16; |
| 679 | insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); |
| 680 | } |
| 681 | |
| 682 | static unsigned |
| 683 | Field_offset_Slot_inst_get (const xtensa_insnbuf insn) |
| 684 | { |
| 685 | unsigned tie_t = 0; |
| 686 | tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); |
| 687 | return tie_t; |
| 688 | } |
| 689 | |
| 690 | static void |
| 691 | Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 692 | { |
| 693 | uint32 tie_t; |
| 694 | tie_t = (val << 14) >> 14; |
| 695 | insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); |
| 696 | } |
| 697 | |
| 698 | static unsigned |
| 699 | Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 700 | { |
| 701 | unsigned tie_t = 0; |
| 702 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 703 | return tie_t; |
| 704 | } |
| 705 | |
| 706 | static void |
| 707 | Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 708 | { |
| 709 | uint32 tie_t; |
| 710 | tie_t = (val << 28) >> 28; |
| 711 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 712 | } |
| 713 | |
| 714 | static unsigned |
| 715 | Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) |
| 716 | { |
| 717 | unsigned tie_t = 0; |
| 718 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); |
| 719 | return tie_t; |
| 720 | } |
| 721 | |
| 722 | static void |
| 723 | Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 724 | { |
| 725 | uint32 tie_t; |
| 726 | tie_t = (val << 31) >> 31; |
| 727 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); |
| 728 | } |
| 729 | |
| 730 | static unsigned |
| 731 | Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) |
| 732 | { |
| 733 | unsigned tie_t = 0; |
| 734 | tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); |
| 735 | return tie_t; |
| 736 | } |
| 737 | |
| 738 | static void |
| 739 | Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 740 | { |
| 741 | uint32 tie_t; |
| 742 | tie_t = (val << 31) >> 31; |
| 743 | insn[0] = (insn[0] & ~0x10) | (tie_t << 4); |
| 744 | } |
| 745 | |
| 746 | static unsigned |
| 747 | Field_sae_Slot_inst_get (const xtensa_insnbuf insn) |
| 748 | { |
| 749 | unsigned tie_t = 0; |
| 750 | tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); |
| 751 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 752 | return tie_t; |
| 753 | } |
| 754 | |
| 755 | static void |
| 756 | Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 757 | { |
| 758 | uint32 tie_t; |
| 759 | tie_t = (val << 28) >> 28; |
| 760 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 761 | tie_t = (val << 27) >> 31; |
| 762 | insn[0] = (insn[0] & ~0x10) | (tie_t << 4); |
| 763 | } |
| 764 | |
| 765 | static unsigned |
| 766 | Field_sal_Slot_inst_get (const xtensa_insnbuf insn) |
| 767 | { |
| 768 | unsigned tie_t = 0; |
| 769 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); |
| 770 | tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); |
| 771 | return tie_t; |
| 772 | } |
| 773 | |
| 774 | static void |
| 775 | Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 776 | { |
| 777 | uint32 tie_t; |
| 778 | tie_t = (val << 28) >> 28; |
| 779 | insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); |
| 780 | tie_t = (val << 27) >> 31; |
| 781 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); |
| 782 | } |
| 783 | |
| 784 | static unsigned |
| 785 | Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) |
| 786 | { |
| 787 | unsigned tie_t = 0; |
| 788 | tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); |
| 789 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 790 | return tie_t; |
| 791 | } |
| 792 | |
| 793 | static void |
| 794 | Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 795 | { |
| 796 | uint32 tie_t; |
| 797 | tie_t = (val << 28) >> 28; |
| 798 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 799 | tie_t = (val << 27) >> 31; |
| 800 | insn[0] = (insn[0] & ~0x1) | (tie_t << 0); |
| 801 | } |
| 802 | |
| 803 | static unsigned |
| 804 | Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) |
| 805 | { |
| 806 | unsigned tie_t = 0; |
| 807 | tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); |
| 808 | return tie_t; |
| 809 | } |
| 810 | |
| 811 | static void |
| 812 | Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 813 | { |
| 814 | uint32 tie_t; |
| 815 | tie_t = (val << 31) >> 31; |
| 816 | insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); |
| 817 | } |
| 818 | |
| 819 | static unsigned |
| 820 | Field_sas_Slot_inst_get (const xtensa_insnbuf insn) |
| 821 | { |
| 822 | unsigned tie_t = 0; |
| 823 | tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); |
| 824 | tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); |
| 825 | return tie_t; |
| 826 | } |
| 827 | |
| 828 | static void |
| 829 | Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 830 | { |
| 831 | uint32 tie_t; |
| 832 | tie_t = (val << 28) >> 28; |
| 833 | insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); |
| 834 | tie_t = (val << 27) >> 31; |
| 835 | insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); |
| 836 | } |
| 837 | |
| 838 | static unsigned |
| 839 | Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 840 | { |
| 841 | unsigned tie_t = 0; |
| 842 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 843 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 844 | return tie_t; |
| 845 | } |
| 846 | |
| 847 | static void |
| 848 | Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 849 | { |
| 850 | uint32 tie_t; |
| 851 | tie_t = (val << 28) >> 28; |
| 852 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 853 | tie_t = (val << 24) >> 28; |
| 854 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 855 | } |
| 856 | |
| 857 | static unsigned |
| 858 | Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 859 | { |
| 860 | unsigned tie_t = 0; |
| 861 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 862 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 863 | return tie_t; |
| 864 | } |
| 865 | |
| 866 | static void |
| 867 | Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 868 | { |
| 869 | uint32 tie_t; |
| 870 | tie_t = (val << 28) >> 28; |
| 871 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 872 | tie_t = (val << 24) >> 28; |
| 873 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 874 | } |
| 875 | |
| 876 | static unsigned |
| 877 | Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 878 | { |
| 879 | unsigned tie_t = 0; |
| 880 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 881 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 882 | return tie_t; |
| 883 | } |
| 884 | |
| 885 | static void |
| 886 | Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 887 | { |
| 888 | uint32 tie_t; |
| 889 | tie_t = (val << 28) >> 28; |
| 890 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 891 | tie_t = (val << 24) >> 28; |
| 892 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 893 | } |
| 894 | |
| 895 | static unsigned |
| 896 | Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 897 | { |
| 898 | unsigned tie_t = 0; |
| 899 | tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); |
| 900 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 901 | return tie_t; |
| 902 | } |
| 903 | |
| 904 | static void |
| 905 | Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 906 | { |
| 907 | uint32 tie_t; |
| 908 | tie_t = (val << 28) >> 28; |
| 909 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 910 | tie_t = (val << 24) >> 28; |
| 911 | insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); |
| 912 | } |
| 913 | |
| 914 | static unsigned |
| 915 | Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) |
| 916 | { |
| 917 | unsigned tie_t = 0; |
| 918 | tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); |
| 919 | return tie_t; |
| 920 | } |
| 921 | |
| 922 | static void |
| 923 | Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 924 | { |
| 925 | uint32 tie_t; |
| 926 | tie_t = (val << 28) >> 28; |
| 927 | insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); |
| 928 | } |
| 929 | |
| 930 | static unsigned |
| 931 | Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 932 | { |
| 933 | unsigned tie_t = 0; |
| 934 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 935 | return tie_t; |
| 936 | } |
| 937 | |
| 938 | static void |
| 939 | Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 940 | { |
| 941 | uint32 tie_t; |
| 942 | tie_t = (val << 28) >> 28; |
| 943 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 944 | } |
| 945 | |
| 946 | static unsigned |
| 947 | Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 948 | { |
| 949 | unsigned tie_t = 0; |
| 950 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 951 | return tie_t; |
| 952 | } |
| 953 | |
| 954 | static void |
| 955 | Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 956 | { |
| 957 | uint32 tie_t; |
| 958 | tie_t = (val << 28) >> 28; |
| 959 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 960 | } |
| 961 | |
| 962 | static unsigned |
| 963 | Field_mn_Slot_inst_get (const xtensa_insnbuf insn) |
| 964 | { |
| 965 | unsigned tie_t = 0; |
| 966 | tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); |
| 967 | tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); |
| 968 | return tie_t; |
| 969 | } |
| 970 | |
| 971 | static void |
| 972 | Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 973 | { |
| 974 | uint32 tie_t; |
| 975 | tie_t = (val << 30) >> 30; |
| 976 | insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); |
| 977 | tie_t = (val << 28) >> 30; |
| 978 | insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); |
| 979 | } |
| 980 | |
| 981 | static unsigned |
| 982 | Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 983 | { |
| 984 | unsigned tie_t = 0; |
| 985 | tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); |
| 986 | return tie_t; |
| 987 | } |
| 988 | |
| 989 | static void |
| 990 | Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 991 | { |
| 992 | uint32 tie_t; |
| 993 | tie_t = (val << 31) >> 31; |
| 994 | insn[0] = (insn[0] & ~0x800) | (tie_t << 11); |
| 995 | } |
| 996 | |
| 997 | static unsigned |
| 998 | Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 999 | { |
| 1000 | unsigned tie_t = 0; |
| 1001 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1002 | return tie_t; |
| 1003 | } |
| 1004 | |
| 1005 | static void |
| 1006 | Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1007 | { |
| 1008 | uint32 tie_t; |
| 1009 | tie_t = (val << 28) >> 28; |
| 1010 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1011 | } |
| 1012 | |
| 1013 | static unsigned |
| 1014 | Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1015 | { |
| 1016 | unsigned tie_t = 0; |
| 1017 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1018 | return tie_t; |
| 1019 | } |
| 1020 | |
| 1021 | static void |
| 1022 | Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1023 | { |
| 1024 | uint32 tie_t; |
| 1025 | tie_t = (val << 28) >> 28; |
| 1026 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1027 | } |
| 1028 | |
| 1029 | static unsigned |
| 1030 | Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1031 | { |
| 1032 | unsigned tie_t = 0; |
| 1033 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1034 | return tie_t; |
| 1035 | } |
| 1036 | |
| 1037 | static void |
| 1038 | Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1039 | { |
| 1040 | uint32 tie_t; |
| 1041 | tie_t = (val << 30) >> 30; |
| 1042 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1043 | } |
| 1044 | |
| 1045 | static unsigned |
| 1046 | Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1047 | { |
| 1048 | unsigned tie_t = 0; |
| 1049 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1050 | return tie_t; |
| 1051 | } |
| 1052 | |
| 1053 | static void |
| 1054 | Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1055 | { |
| 1056 | uint32 tie_t; |
| 1057 | tie_t = (val << 30) >> 30; |
| 1058 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1059 | } |
| 1060 | |
| 1061 | static unsigned |
| 1062 | Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1063 | { |
| 1064 | unsigned tie_t = 0; |
| 1065 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1066 | return tie_t; |
| 1067 | } |
| 1068 | |
| 1069 | static void |
| 1070 | Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1071 | { |
| 1072 | uint32 tie_t; |
| 1073 | tie_t = (val << 28) >> 28; |
| 1074 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1075 | } |
| 1076 | |
| 1077 | static unsigned |
| 1078 | Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1079 | { |
| 1080 | unsigned tie_t = 0; |
| 1081 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1082 | return tie_t; |
| 1083 | } |
| 1084 | |
| 1085 | static void |
| 1086 | Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1087 | { |
| 1088 | uint32 tie_t; |
| 1089 | tie_t = (val << 28) >> 28; |
| 1090 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1091 | } |
| 1092 | |
| 1093 | static unsigned |
| 1094 | Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1095 | { |
| 1096 | unsigned tie_t = 0; |
| 1097 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1098 | return tie_t; |
| 1099 | } |
| 1100 | |
| 1101 | static void |
| 1102 | Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1103 | { |
| 1104 | uint32 tie_t; |
| 1105 | tie_t = (val << 29) >> 29; |
| 1106 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1107 | } |
| 1108 | |
| 1109 | static unsigned |
| 1110 | Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1111 | { |
| 1112 | unsigned tie_t = 0; |
| 1113 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1114 | return tie_t; |
| 1115 | } |
| 1116 | |
| 1117 | static void |
| 1118 | Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1119 | { |
| 1120 | uint32 tie_t; |
| 1121 | tie_t = (val << 29) >> 29; |
| 1122 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1123 | } |
| 1124 | |
| 1125 | static unsigned |
| 1126 | Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1127 | { |
| 1128 | unsigned tie_t = 0; |
| 1129 | tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); |
| 1130 | return tie_t; |
| 1131 | } |
| 1132 | |
| 1133 | static void |
| 1134 | Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1135 | { |
| 1136 | uint32 tie_t; |
| 1137 | tie_t = (val << 31) >> 31; |
| 1138 | insn[0] = (insn[0] & ~0x400) | (tie_t << 10); |
| 1139 | } |
| 1140 | |
| 1141 | static unsigned |
| 1142 | Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1143 | { |
| 1144 | unsigned tie_t = 0; |
| 1145 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1146 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1147 | return tie_t; |
| 1148 | } |
| 1149 | |
| 1150 | static void |
| 1151 | Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1152 | { |
| 1153 | uint32 tie_t; |
| 1154 | tie_t = (val << 28) >> 28; |
| 1155 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1156 | tie_t = (val << 26) >> 30; |
| 1157 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1158 | } |
| 1159 | |
| 1160 | static unsigned |
| 1161 | Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1162 | { |
| 1163 | unsigned tie_t = 0; |
| 1164 | tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); |
| 1165 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1166 | return tie_t; |
| 1167 | } |
| 1168 | |
| 1169 | static void |
| 1170 | Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1171 | { |
| 1172 | uint32 tie_t; |
| 1173 | tie_t = (val << 28) >> 28; |
| 1174 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1175 | tie_t = (val << 26) >> 30; |
| 1176 | insn[0] = (insn[0] & ~0x300) | (tie_t << 8); |
| 1177 | } |
| 1178 | |
| 1179 | static unsigned |
| 1180 | Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) |
| 1181 | { |
| 1182 | unsigned tie_t = 0; |
| 1183 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1184 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1185 | return tie_t; |
| 1186 | } |
| 1187 | |
| 1188 | static void |
| 1189 | Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) |
| 1190 | { |
| 1191 | uint32 tie_t; |
| 1192 | tie_t = (val << 28) >> 28; |
| 1193 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1194 | tie_t = (val << 25) >> 29; |
| 1195 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1196 | } |
| 1197 | |
| 1198 | static unsigned |
| 1199 | Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) |
| 1200 | { |
| 1201 | unsigned tie_t = 0; |
| 1202 | tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); |
| 1203 | tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); |
| 1204 | return tie_t; |
| 1205 | } |
| 1206 | |
| 1207 | static void |
| 1208 | Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) |
| 1209 | { |
| 1210 | uint32 tie_t; |
| 1211 | tie_t = (val << 28) >> 28; |
| 1212 | insn[0] = (insn[0] & ~0xf) | (tie_t << 0); |
| 1213 | tie_t = (val << 25) >> 29; |
| 1214 | insn[0] = (insn[0] & ~0x700) | (tie_t << 8); |
| 1215 | } |
| 1216 | |
| 1217 | static unsigned |
| 1218 | Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) |
| 1219 | { |
| 1220 | unsigned tie_t = 0; |
| 1221 | tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); |
| 1222 | return tie_t; |
| 1223 | } |
| 1224 | |
| 1225 | static void |
| 1226 | Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 1227 | { |
| 1228 | uint32 tie_t; |
| 1229 | tie_t = (val << 17) >> 17; |
| 1230 | insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); |
| 1231 | } |
| 1232 | |
| 1233 | static unsigned |
| 1234 | Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) |
| 1235 | { |
| 1236 | unsigned tie_t = 0; |
| 1237 | tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); |
| 1238 | return tie_t; |
| 1239 | } |
| 1240 | |
| 1241 | static void |
| 1242 | Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) |
| 1243 | { |
| 1244 | uint32 tie_t; |
| 1245 | tie_t = (val << 14) >> 14; |
| 1246 | insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); |
| 1247 | } |
| 1248 | |
| 1249 | static void |
| 1250 | Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, |
| 1251 | uint32 val ATTRIBUTE_UNUSED) |
| 1252 | { |
| 1253 | /* Do nothing. */ |
| 1254 | } |
| 1255 | |
| 1256 | static unsigned |
| 1257 | Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1258 | { |
| 1259 | return 0; |
| 1260 | } |
| 1261 | |
| 1262 | static unsigned |
| 1263 | Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1264 | { |
| 1265 | return 4; |
| 1266 | } |
| 1267 | |
| 1268 | static unsigned |
| 1269 | Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1270 | { |
| 1271 | return 8; |
| 1272 | } |
| 1273 | |
| 1274 | static unsigned |
| 1275 | Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) |
| 1276 | { |
| 1277 | return 12; |
| 1278 | } |
| 1279 | |
| 1280 | enum xtensa_field_id { |
| 1281 | FIELD_t, |
| 1282 | FIELD_bbi4, |
| 1283 | FIELD_bbi, |
| 1284 | FIELD_imm12, |
| 1285 | FIELD_imm8, |
| 1286 | FIELD_s, |
| 1287 | FIELD_imm12b, |
| 1288 | FIELD_imm16, |
| 1289 | FIELD_m, |
| 1290 | FIELD_n, |
| 1291 | FIELD_offset, |
| 1292 | FIELD_op0, |
| 1293 | FIELD_op1, |
| 1294 | FIELD_op2, |
| 1295 | FIELD_r, |
| 1296 | FIELD_sa4, |
| 1297 | FIELD_sae4, |
| 1298 | FIELD_sae, |
| 1299 | FIELD_sal, |
| 1300 | FIELD_sargt, |
| 1301 | FIELD_sas4, |
| 1302 | FIELD_sas, |
| 1303 | FIELD_sr, |
| 1304 | FIELD_st, |
| 1305 | FIELD_thi3, |
| 1306 | FIELD_imm4, |
| 1307 | FIELD_mn, |
| 1308 | FIELD_i, |
| 1309 | FIELD_imm6lo, |
| 1310 | FIELD_imm6hi, |
| 1311 | FIELD_imm7lo, |
| 1312 | FIELD_imm7hi, |
| 1313 | FIELD_z, |
| 1314 | FIELD_imm6, |
| 1315 | FIELD_imm7, |
| 1316 | FIELD_xt_wbr15_imm, |
| 1317 | FIELD_xt_wbr18_imm, |
| 1318 | FIELD__ar0, |
| 1319 | FIELD__ar4, |
| 1320 | FIELD__ar8, |
| 1321 | FIELD__ar12 |
| 1322 | }; |
| 1323 | |
| 1324 | \f |
| 1325 | /* Functional units. */ |
| 1326 | |
| 1327 | static xtensa_funcUnit_internal funcUnits[] = { |
| 1328 | |
| 1329 | }; |
| 1330 | |
| 1331 | \f |
| 1332 | /* Register files. */ |
| 1333 | |
| 1334 | enum xtensa_regfile_id { |
| 1335 | REGFILE_AR |
| 1336 | }; |
| 1337 | |
| 1338 | static xtensa_regfile_internal regfiles[] = { |
| 1339 | { "AR", "a", REGFILE_AR, 32, 32 } |
| 1340 | }; |
| 1341 | |
| 1342 | \f |
| 1343 | /* Interfaces. */ |
| 1344 | |
| 1345 | static xtensa_interface_internal interfaces[] = { |
| 1346 | |
| 1347 | }; |
| 1348 | |
| 1349 | \f |
| 1350 | /* Constant tables. */ |
| 1351 | |
| 1352 | /* constant table ai4c */ |
| 1353 | static const unsigned CONST_TBL_ai4c_0[] = { |
| 1354 | 0xffffffff, |
| 1355 | 0x1, |
| 1356 | 0x2, |
| 1357 | 0x3, |
| 1358 | 0x4, |
| 1359 | 0x5, |
| 1360 | 0x6, |
| 1361 | 0x7, |
| 1362 | 0x8, |
| 1363 | 0x9, |
| 1364 | 0xa, |
| 1365 | 0xb, |
| 1366 | 0xc, |
| 1367 | 0xd, |
| 1368 | 0xe, |
| 1369 | 0xf, |
| 1370 | 0 |
| 1371 | }; |
| 1372 | |
| 1373 | /* constant table b4c */ |
| 1374 | static const unsigned CONST_TBL_b4c_0[] = { |
| 1375 | 0xffffffff, |
| 1376 | 0x1, |
| 1377 | 0x2, |
| 1378 | 0x3, |
| 1379 | 0x4, |
| 1380 | 0x5, |
| 1381 | 0x6, |
| 1382 | 0x7, |
| 1383 | 0x8, |
| 1384 | 0xa, |
| 1385 | 0xc, |
| 1386 | 0x10, |
| 1387 | 0x20, |
| 1388 | 0x40, |
| 1389 | 0x80, |
| 1390 | 0x100, |
| 1391 | 0 |
| 1392 | }; |
| 1393 | |
| 1394 | /* constant table b4cu */ |
| 1395 | static const unsigned CONST_TBL_b4cu_0[] = { |
| 1396 | 0x8000, |
| 1397 | 0x10000, |
| 1398 | 0x2, |
| 1399 | 0x3, |
| 1400 | 0x4, |
| 1401 | 0x5, |
| 1402 | 0x6, |
| 1403 | 0x7, |
| 1404 | 0x8, |
| 1405 | 0xa, |
| 1406 | 0xc, |
| 1407 | 0x10, |
| 1408 | 0x20, |
| 1409 | 0x40, |
| 1410 | 0x80, |
| 1411 | 0x100, |
| 1412 | 0 |
| 1413 | }; |
| 1414 | |
| 1415 | \f |
| 1416 | /* Instruction operands. */ |
| 1417 | |
| 1418 | static int |
| 1419 | Operand_soffsetx4_decode (uint32 *valp) |
| 1420 | { |
| 1421 | unsigned soffsetx4_0, offset_0; |
| 1422 | offset_0 = *valp & 0x3ffff; |
| 1423 | soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); |
| 1424 | *valp = soffsetx4_0; |
| 1425 | return 0; |
| 1426 | } |
| 1427 | |
| 1428 | static int |
| 1429 | Operand_soffsetx4_encode (uint32 *valp) |
| 1430 | { |
| 1431 | unsigned offset_0, soffsetx4_0; |
| 1432 | soffsetx4_0 = *valp; |
| 1433 | offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; |
| 1434 | *valp = offset_0; |
| 1435 | return 0; |
| 1436 | } |
| 1437 | |
| 1438 | static int |
| 1439 | Operand_soffsetx4_ator (uint32 *valp, uint32 pc) |
| 1440 | { |
| 1441 | *valp -= (pc & ~0x3); |
| 1442 | return 0; |
| 1443 | } |
| 1444 | |
| 1445 | static int |
| 1446 | Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) |
| 1447 | { |
| 1448 | *valp += (pc & ~0x3); |
| 1449 | return 0; |
| 1450 | } |
| 1451 | |
| 1452 | static int |
| 1453 | Operand_uimm12x8_decode (uint32 *valp) |
| 1454 | { |
| 1455 | unsigned uimm12x8_0, imm12_0; |
| 1456 | imm12_0 = *valp & 0xfff; |
| 1457 | uimm12x8_0 = imm12_0 << 3; |
| 1458 | *valp = uimm12x8_0; |
| 1459 | return 0; |
| 1460 | } |
| 1461 | |
| 1462 | static int |
| 1463 | Operand_uimm12x8_encode (uint32 *valp) |
| 1464 | { |
| 1465 | unsigned imm12_0, uimm12x8_0; |
| 1466 | uimm12x8_0 = *valp; |
| 1467 | imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); |
| 1468 | *valp = imm12_0; |
| 1469 | return 0; |
| 1470 | } |
| 1471 | |
| 1472 | static int |
| 1473 | Operand_simm4_decode (uint32 *valp) |
| 1474 | { |
| 1475 | unsigned simm4_0, mn_0; |
| 1476 | mn_0 = *valp & 0xf; |
| 1477 | simm4_0 = ((int) mn_0 << 28) >> 28; |
| 1478 | *valp = simm4_0; |
| 1479 | return 0; |
| 1480 | } |
| 1481 | |
| 1482 | static int |
| 1483 | Operand_simm4_encode (uint32 *valp) |
| 1484 | { |
| 1485 | unsigned mn_0, simm4_0; |
| 1486 | simm4_0 = *valp; |
| 1487 | mn_0 = (simm4_0 & 0xf); |
| 1488 | *valp = mn_0; |
| 1489 | return 0; |
| 1490 | } |
| 1491 | |
| 1492 | static int |
| 1493 | Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1494 | { |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | static int |
| 1499 | Operand_arr_encode (uint32 *valp) |
| 1500 | { |
| 1501 | int error; |
| 1502 | error = (*valp & ~0xf) != 0; |
| 1503 | return error; |
| 1504 | } |
| 1505 | |
| 1506 | static int |
| 1507 | Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1508 | { |
| 1509 | return 0; |
| 1510 | } |
| 1511 | |
| 1512 | static int |
| 1513 | Operand_ars_encode (uint32 *valp) |
| 1514 | { |
| 1515 | int error; |
| 1516 | error = (*valp & ~0xf) != 0; |
| 1517 | return error; |
| 1518 | } |
| 1519 | |
| 1520 | static int |
| 1521 | Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1522 | { |
| 1523 | return 0; |
| 1524 | } |
| 1525 | |
| 1526 | static int |
| 1527 | Operand_art_encode (uint32 *valp) |
| 1528 | { |
| 1529 | int error; |
| 1530 | error = (*valp & ~0xf) != 0; |
| 1531 | return error; |
| 1532 | } |
| 1533 | |
| 1534 | static int |
| 1535 | Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1536 | { |
| 1537 | return 0; |
| 1538 | } |
| 1539 | |
| 1540 | static int |
| 1541 | Operand_ar0_encode (uint32 *valp) |
| 1542 | { |
| 1543 | int error; |
| 1544 | error = (*valp & ~0x1f) != 0; |
| 1545 | return error; |
| 1546 | } |
| 1547 | |
| 1548 | static int |
| 1549 | Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1550 | { |
| 1551 | return 0; |
| 1552 | } |
| 1553 | |
| 1554 | static int |
| 1555 | Operand_ar4_encode (uint32 *valp) |
| 1556 | { |
| 1557 | int error; |
| 1558 | error = (*valp & ~0x1f) != 0; |
| 1559 | return error; |
| 1560 | } |
| 1561 | |
| 1562 | static int |
| 1563 | Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1564 | { |
| 1565 | return 0; |
| 1566 | } |
| 1567 | |
| 1568 | static int |
| 1569 | Operand_ar8_encode (uint32 *valp) |
| 1570 | { |
| 1571 | int error; |
| 1572 | error = (*valp & ~0x1f) != 0; |
| 1573 | return error; |
| 1574 | } |
| 1575 | |
| 1576 | static int |
| 1577 | Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1578 | { |
| 1579 | return 0; |
| 1580 | } |
| 1581 | |
| 1582 | static int |
| 1583 | Operand_ar12_encode (uint32 *valp) |
| 1584 | { |
| 1585 | int error; |
| 1586 | error = (*valp & ~0x1f) != 0; |
| 1587 | return error; |
| 1588 | } |
| 1589 | |
| 1590 | static int |
| 1591 | Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) |
| 1592 | { |
| 1593 | return 0; |
| 1594 | } |
| 1595 | |
| 1596 | static int |
| 1597 | Operand_ars_entry_encode (uint32 *valp) |
| 1598 | { |
| 1599 | int error; |
| 1600 | error = (*valp & ~0x1f) != 0; |
| 1601 | return error; |
| 1602 | } |
| 1603 | |
| 1604 | static int |
| 1605 | Operand_immrx4_decode (uint32 *valp) |
| 1606 | { |
| 1607 | unsigned immrx4_0, r_0; |
| 1608 | r_0 = *valp & 0xf; |
| 1609 | immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; |
| 1610 | *valp = immrx4_0; |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
| 1614 | static int |
| 1615 | Operand_immrx4_encode (uint32 *valp) |
| 1616 | { |
| 1617 | unsigned r_0, immrx4_0; |
| 1618 | immrx4_0 = *valp; |
| 1619 | r_0 = ((immrx4_0 >> 2) & 0xf); |
| 1620 | *valp = r_0; |
| 1621 | return 0; |
| 1622 | } |
| 1623 | |
| 1624 | static int |
| 1625 | Operand_lsi4x4_decode (uint32 *valp) |
| 1626 | { |
| 1627 | unsigned lsi4x4_0, r_0; |
| 1628 | r_0 = *valp & 0xf; |
| 1629 | lsi4x4_0 = r_0 << 2; |
| 1630 | *valp = lsi4x4_0; |
| 1631 | return 0; |
| 1632 | } |
| 1633 | |
| 1634 | static int |
| 1635 | Operand_lsi4x4_encode (uint32 *valp) |
| 1636 | { |
| 1637 | unsigned r_0, lsi4x4_0; |
| 1638 | lsi4x4_0 = *valp; |
| 1639 | r_0 = ((lsi4x4_0 >> 2) & 0xf); |
| 1640 | *valp = r_0; |
| 1641 | return 0; |
| 1642 | } |
| 1643 | |
| 1644 | static int |
| 1645 | Operand_simm7_decode (uint32 *valp) |
| 1646 | { |
| 1647 | unsigned simm7_0, imm7_0; |
| 1648 | imm7_0 = *valp & 0x7f; |
| 1649 | simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; |
| 1650 | *valp = simm7_0; |
| 1651 | return 0; |
| 1652 | } |
| 1653 | |
| 1654 | static int |
| 1655 | Operand_simm7_encode (uint32 *valp) |
| 1656 | { |
| 1657 | unsigned imm7_0, simm7_0; |
| 1658 | simm7_0 = *valp; |
| 1659 | imm7_0 = (simm7_0 & 0x7f); |
| 1660 | *valp = imm7_0; |
| 1661 | return 0; |
| 1662 | } |
| 1663 | |
| 1664 | static int |
| 1665 | Operand_uimm6_decode (uint32 *valp) |
| 1666 | { |
| 1667 | unsigned uimm6_0, imm6_0; |
| 1668 | imm6_0 = *valp & 0x3f; |
| 1669 | uimm6_0 = 0x4 + (((0) << 6) | imm6_0); |
| 1670 | *valp = uimm6_0; |
| 1671 | return 0; |
| 1672 | } |
| 1673 | |
| 1674 | static int |
| 1675 | Operand_uimm6_encode (uint32 *valp) |
| 1676 | { |
| 1677 | unsigned imm6_0, uimm6_0; |
| 1678 | uimm6_0 = *valp; |
| 1679 | imm6_0 = (uimm6_0 - 0x4) & 0x3f; |
| 1680 | *valp = imm6_0; |
| 1681 | return 0; |
| 1682 | } |
| 1683 | |
| 1684 | static int |
| 1685 | Operand_uimm6_ator (uint32 *valp, uint32 pc) |
| 1686 | { |
| 1687 | *valp -= pc; |
| 1688 | return 0; |
| 1689 | } |
| 1690 | |
| 1691 | static int |
| 1692 | Operand_uimm6_rtoa (uint32 *valp, uint32 pc) |
| 1693 | { |
| 1694 | *valp += pc; |
| 1695 | return 0; |
| 1696 | } |
| 1697 | |
| 1698 | static int |
| 1699 | Operand_ai4const_decode (uint32 *valp) |
| 1700 | { |
| 1701 | unsigned ai4const_0, t_0; |
| 1702 | t_0 = *valp & 0xf; |
| 1703 | ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; |
| 1704 | *valp = ai4const_0; |
| 1705 | return 0; |
| 1706 | } |
| 1707 | |
| 1708 | static int |
| 1709 | Operand_ai4const_encode (uint32 *valp) |
| 1710 | { |
| 1711 | unsigned t_0, ai4const_0; |
| 1712 | ai4const_0 = *valp; |
| 1713 | switch (ai4const_0) |
| 1714 | { |
| 1715 | case 0xffffffff: t_0 = 0; break; |
| 1716 | case 0x1: t_0 = 0x1; break; |
| 1717 | case 0x2: t_0 = 0x2; break; |
| 1718 | case 0x3: t_0 = 0x3; break; |
| 1719 | case 0x4: t_0 = 0x4; break; |
| 1720 | case 0x5: t_0 = 0x5; break; |
| 1721 | case 0x6: t_0 = 0x6; break; |
| 1722 | case 0x7: t_0 = 0x7; break; |
| 1723 | case 0x8: t_0 = 0x8; break; |
| 1724 | case 0x9: t_0 = 0x9; break; |
| 1725 | case 0xa: t_0 = 0xa; break; |
| 1726 | case 0xb: t_0 = 0xb; break; |
| 1727 | case 0xc: t_0 = 0xc; break; |
| 1728 | case 0xd: t_0 = 0xd; break; |
| 1729 | case 0xe: t_0 = 0xe; break; |
| 1730 | default: t_0 = 0xf; break; |
| 1731 | } |
| 1732 | *valp = t_0; |
| 1733 | return 0; |
| 1734 | } |
| 1735 | |
| 1736 | static int |
| 1737 | Operand_b4const_decode (uint32 *valp) |
| 1738 | { |
| 1739 | unsigned b4const_0, r_0; |
| 1740 | r_0 = *valp & 0xf; |
| 1741 | b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; |
| 1742 | *valp = b4const_0; |
| 1743 | return 0; |
| 1744 | } |
| 1745 | |
| 1746 | static int |
| 1747 | Operand_b4const_encode (uint32 *valp) |
| 1748 | { |
| 1749 | unsigned r_0, b4const_0; |
| 1750 | b4const_0 = *valp; |
| 1751 | switch (b4const_0) |
| 1752 | { |
| 1753 | case 0xffffffff: r_0 = 0; break; |
| 1754 | case 0x1: r_0 = 0x1; break; |
| 1755 | case 0x2: r_0 = 0x2; break; |
| 1756 | case 0x3: r_0 = 0x3; break; |
| 1757 | case 0x4: r_0 = 0x4; break; |
| 1758 | case 0x5: r_0 = 0x5; break; |
| 1759 | case 0x6: r_0 = 0x6; break; |
| 1760 | case 0x7: r_0 = 0x7; break; |
| 1761 | case 0x8: r_0 = 0x8; break; |
| 1762 | case 0xa: r_0 = 0x9; break; |
| 1763 | case 0xc: r_0 = 0xa; break; |
| 1764 | case 0x10: r_0 = 0xb; break; |
| 1765 | case 0x20: r_0 = 0xc; break; |
| 1766 | case 0x40: r_0 = 0xd; break; |
| 1767 | case 0x80: r_0 = 0xe; break; |
| 1768 | default: r_0 = 0xf; break; |
| 1769 | } |
| 1770 | *valp = r_0; |
| 1771 | return 0; |
| 1772 | } |
| 1773 | |
| 1774 | static int |
| 1775 | Operand_b4constu_decode (uint32 *valp) |
| 1776 | { |
| 1777 | unsigned b4constu_0, r_0; |
| 1778 | r_0 = *valp & 0xf; |
| 1779 | b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; |
| 1780 | *valp = b4constu_0; |
| 1781 | return 0; |
| 1782 | } |
| 1783 | |
| 1784 | static int |
| 1785 | Operand_b4constu_encode (uint32 *valp) |
| 1786 | { |
| 1787 | unsigned r_0, b4constu_0; |
| 1788 | b4constu_0 = *valp; |
| 1789 | switch (b4constu_0) |
| 1790 | { |
| 1791 | case 0x8000: r_0 = 0; break; |
| 1792 | case 0x10000: r_0 = 0x1; break; |
| 1793 | case 0x2: r_0 = 0x2; break; |
| 1794 | case 0x3: r_0 = 0x3; break; |
| 1795 | case 0x4: r_0 = 0x4; break; |
| 1796 | case 0x5: r_0 = 0x5; break; |
| 1797 | case 0x6: r_0 = 0x6; break; |
| 1798 | case 0x7: r_0 = 0x7; break; |
| 1799 | case 0x8: r_0 = 0x8; break; |
| 1800 | case 0xa: r_0 = 0x9; break; |
| 1801 | case 0xc: r_0 = 0xa; break; |
| 1802 | case 0x10: r_0 = 0xb; break; |
| 1803 | case 0x20: r_0 = 0xc; break; |
| 1804 | case 0x40: r_0 = 0xd; break; |
| 1805 | case 0x80: r_0 = 0xe; break; |
| 1806 | default: r_0 = 0xf; break; |
| 1807 | } |
| 1808 | *valp = r_0; |
| 1809 | return 0; |
| 1810 | } |
| 1811 | |
| 1812 | static int |
| 1813 | Operand_uimm8_decode (uint32 *valp) |
| 1814 | { |
| 1815 | unsigned uimm8_0, imm8_0; |
| 1816 | imm8_0 = *valp & 0xff; |
| 1817 | uimm8_0 = imm8_0; |
| 1818 | *valp = uimm8_0; |
| 1819 | return 0; |
| 1820 | } |
| 1821 | |
| 1822 | static int |
| 1823 | Operand_uimm8_encode (uint32 *valp) |
| 1824 | { |
| 1825 | unsigned imm8_0, uimm8_0; |
| 1826 | uimm8_0 = *valp; |
| 1827 | imm8_0 = (uimm8_0 & 0xff); |
| 1828 | *valp = imm8_0; |
| 1829 | return 0; |
| 1830 | } |
| 1831 | |
| 1832 | static int |
| 1833 | Operand_uimm8x2_decode (uint32 *valp) |
| 1834 | { |
| 1835 | unsigned uimm8x2_0, imm8_0; |
| 1836 | imm8_0 = *valp & 0xff; |
| 1837 | uimm8x2_0 = imm8_0 << 1; |
| 1838 | *valp = uimm8x2_0; |
| 1839 | return 0; |
| 1840 | } |
| 1841 | |
| 1842 | static int |
| 1843 | Operand_uimm8x2_encode (uint32 *valp) |
| 1844 | { |
| 1845 | unsigned imm8_0, uimm8x2_0; |
| 1846 | uimm8x2_0 = *valp; |
| 1847 | imm8_0 = ((uimm8x2_0 >> 1) & 0xff); |
| 1848 | *valp = imm8_0; |
| 1849 | return 0; |
| 1850 | } |
| 1851 | |
| 1852 | static int |
| 1853 | Operand_uimm8x4_decode (uint32 *valp) |
| 1854 | { |
| 1855 | unsigned uimm8x4_0, imm8_0; |
| 1856 | imm8_0 = *valp & 0xff; |
| 1857 | uimm8x4_0 = imm8_0 << 2; |
| 1858 | *valp = uimm8x4_0; |
| 1859 | return 0; |
| 1860 | } |
| 1861 | |
| 1862 | static int |
| 1863 | Operand_uimm8x4_encode (uint32 *valp) |
| 1864 | { |
| 1865 | unsigned imm8_0, uimm8x4_0; |
| 1866 | uimm8x4_0 = *valp; |
| 1867 | imm8_0 = ((uimm8x4_0 >> 2) & 0xff); |
| 1868 | *valp = imm8_0; |
| 1869 | return 0; |
| 1870 | } |
| 1871 | |
| 1872 | static int |
| 1873 | Operand_uimm4x16_decode (uint32 *valp) |
| 1874 | { |
| 1875 | unsigned uimm4x16_0, op2_0; |
| 1876 | op2_0 = *valp & 0xf; |
| 1877 | uimm4x16_0 = op2_0 << 4; |
| 1878 | *valp = uimm4x16_0; |
| 1879 | return 0; |
| 1880 | } |
| 1881 | |
| 1882 | static int |
| 1883 | Operand_uimm4x16_encode (uint32 *valp) |
| 1884 | { |
| 1885 | unsigned op2_0, uimm4x16_0; |
| 1886 | uimm4x16_0 = *valp; |
| 1887 | op2_0 = ((uimm4x16_0 >> 4) & 0xf); |
| 1888 | *valp = op2_0; |
| 1889 | return 0; |
| 1890 | } |
| 1891 | |
| 1892 | static int |
| 1893 | Operand_simm8_decode (uint32 *valp) |
| 1894 | { |
| 1895 | unsigned simm8_0, imm8_0; |
| 1896 | imm8_0 = *valp & 0xff; |
| 1897 | simm8_0 = ((int) imm8_0 << 24) >> 24; |
| 1898 | *valp = simm8_0; |
| 1899 | return 0; |
| 1900 | } |
| 1901 | |
| 1902 | static int |
| 1903 | Operand_simm8_encode (uint32 *valp) |
| 1904 | { |
| 1905 | unsigned imm8_0, simm8_0; |
| 1906 | simm8_0 = *valp; |
| 1907 | imm8_0 = (simm8_0 & 0xff); |
| 1908 | *valp = imm8_0; |
| 1909 | return 0; |
| 1910 | } |
| 1911 | |
| 1912 | static int |
| 1913 | Operand_simm8x256_decode (uint32 *valp) |
| 1914 | { |
| 1915 | unsigned simm8x256_0, imm8_0; |
| 1916 | imm8_0 = *valp & 0xff; |
| 1917 | simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; |
| 1918 | *valp = simm8x256_0; |
| 1919 | return 0; |
| 1920 | } |
| 1921 | |
| 1922 | static int |
| 1923 | Operand_simm8x256_encode (uint32 *valp) |
| 1924 | { |
| 1925 | unsigned imm8_0, simm8x256_0; |
| 1926 | simm8x256_0 = *valp; |
| 1927 | imm8_0 = ((simm8x256_0 >> 8) & 0xff); |
| 1928 | *valp = imm8_0; |
| 1929 | return 0; |
| 1930 | } |
| 1931 | |
| 1932 | static int |
| 1933 | Operand_simm12b_decode (uint32 *valp) |
| 1934 | { |
| 1935 | unsigned simm12b_0, imm12b_0; |
| 1936 | imm12b_0 = *valp & 0xfff; |
| 1937 | simm12b_0 = ((int) imm12b_0 << 20) >> 20; |
| 1938 | *valp = simm12b_0; |
| 1939 | return 0; |
| 1940 | } |
| 1941 | |
| 1942 | static int |
| 1943 | Operand_simm12b_encode (uint32 *valp) |
| 1944 | { |
| 1945 | unsigned imm12b_0, simm12b_0; |
| 1946 | simm12b_0 = *valp; |
| 1947 | imm12b_0 = (simm12b_0 & 0xfff); |
| 1948 | *valp = imm12b_0; |
| 1949 | return 0; |
| 1950 | } |
| 1951 | |
| 1952 | static int |
| 1953 | Operand_msalp32_decode (uint32 *valp) |
| 1954 | { |
| 1955 | unsigned msalp32_0, sal_0; |
| 1956 | sal_0 = *valp & 0x1f; |
| 1957 | msalp32_0 = 0x20 - sal_0; |
| 1958 | *valp = msalp32_0; |
| 1959 | return 0; |
| 1960 | } |
| 1961 | |
| 1962 | static int |
| 1963 | Operand_msalp32_encode (uint32 *valp) |
| 1964 | { |
| 1965 | unsigned sal_0, msalp32_0; |
| 1966 | msalp32_0 = *valp; |
| 1967 | sal_0 = (0x20 - msalp32_0) & 0x1f; |
| 1968 | *valp = sal_0; |
| 1969 | return 0; |
| 1970 | } |
| 1971 | |
| 1972 | static int |
| 1973 | Operand_op2p1_decode (uint32 *valp) |
| 1974 | { |
| 1975 | unsigned op2p1_0, op2_0; |
| 1976 | op2_0 = *valp & 0xf; |
| 1977 | op2p1_0 = op2_0 + 0x1; |
| 1978 | *valp = op2p1_0; |
| 1979 | return 0; |
| 1980 | } |
| 1981 | |
| 1982 | static int |
| 1983 | Operand_op2p1_encode (uint32 *valp) |
| 1984 | { |
| 1985 | unsigned op2_0, op2p1_0; |
| 1986 | op2p1_0 = *valp; |
| 1987 | op2_0 = (op2p1_0 - 0x1) & 0xf; |
| 1988 | *valp = op2_0; |
| 1989 | return 0; |
| 1990 | } |
| 1991 | |
| 1992 | static int |
| 1993 | Operand_label8_decode (uint32 *valp) |
| 1994 | { |
| 1995 | unsigned label8_0, imm8_0; |
| 1996 | imm8_0 = *valp & 0xff; |
| 1997 | label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); |
| 1998 | *valp = label8_0; |
| 1999 | return 0; |
| 2000 | } |
| 2001 | |
| 2002 | static int |
| 2003 | Operand_label8_encode (uint32 *valp) |
| 2004 | { |
| 2005 | unsigned imm8_0, label8_0; |
| 2006 | label8_0 = *valp; |
| 2007 | imm8_0 = (label8_0 - 0x4) & 0xff; |
| 2008 | *valp = imm8_0; |
| 2009 | return 0; |
| 2010 | } |
| 2011 | |
| 2012 | static int |
| 2013 | Operand_label8_ator (uint32 *valp, uint32 pc) |
| 2014 | { |
| 2015 | *valp -= pc; |
| 2016 | return 0; |
| 2017 | } |
| 2018 | |
| 2019 | static int |
| 2020 | Operand_label8_rtoa (uint32 *valp, uint32 pc) |
| 2021 | { |
| 2022 | *valp += pc; |
| 2023 | return 0; |
| 2024 | } |
| 2025 | |
| 2026 | static int |
| 2027 | Operand_ulabel8_decode (uint32 *valp) |
| 2028 | { |
| 2029 | unsigned ulabel8_0, imm8_0; |
| 2030 | imm8_0 = *valp & 0xff; |
| 2031 | ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); |
| 2032 | *valp = ulabel8_0; |
| 2033 | return 0; |
| 2034 | } |
| 2035 | |
| 2036 | static int |
| 2037 | Operand_ulabel8_encode (uint32 *valp) |
| 2038 | { |
| 2039 | unsigned imm8_0, ulabel8_0; |
| 2040 | ulabel8_0 = *valp; |
| 2041 | imm8_0 = (ulabel8_0 - 0x4) & 0xff; |
| 2042 | *valp = imm8_0; |
| 2043 | return 0; |
| 2044 | } |
| 2045 | |
| 2046 | static int |
| 2047 | Operand_ulabel8_ator (uint32 *valp, uint32 pc) |
| 2048 | { |
| 2049 | *valp -= pc; |
| 2050 | return 0; |
| 2051 | } |
| 2052 | |
| 2053 | static int |
| 2054 | Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) |
| 2055 | { |
| 2056 | *valp += pc; |
| 2057 | return 0; |
| 2058 | } |
| 2059 | |
| 2060 | static int |
| 2061 | Operand_label12_decode (uint32 *valp) |
| 2062 | { |
| 2063 | unsigned label12_0, imm12_0; |
| 2064 | imm12_0 = *valp & 0xfff; |
| 2065 | label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); |
| 2066 | *valp = label12_0; |
| 2067 | return 0; |
| 2068 | } |
| 2069 | |
| 2070 | static int |
| 2071 | Operand_label12_encode (uint32 *valp) |
| 2072 | { |
| 2073 | unsigned imm12_0, label12_0; |
| 2074 | label12_0 = *valp; |
| 2075 | imm12_0 = (label12_0 - 0x4) & 0xfff; |
| 2076 | *valp = imm12_0; |
| 2077 | return 0; |
| 2078 | } |
| 2079 | |
| 2080 | static int |
| 2081 | Operand_label12_ator (uint32 *valp, uint32 pc) |
| 2082 | { |
| 2083 | *valp -= pc; |
| 2084 | return 0; |
| 2085 | } |
| 2086 | |
| 2087 | static int |
| 2088 | Operand_label12_rtoa (uint32 *valp, uint32 pc) |
| 2089 | { |
| 2090 | *valp += pc; |
| 2091 | return 0; |
| 2092 | } |
| 2093 | |
| 2094 | static int |
| 2095 | Operand_soffset_decode (uint32 *valp) |
| 2096 | { |
| 2097 | unsigned soffset_0, offset_0; |
| 2098 | offset_0 = *valp & 0x3ffff; |
| 2099 | soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); |
| 2100 | *valp = soffset_0; |
| 2101 | return 0; |
| 2102 | } |
| 2103 | |
| 2104 | static int |
| 2105 | Operand_soffset_encode (uint32 *valp) |
| 2106 | { |
| 2107 | unsigned offset_0, soffset_0; |
| 2108 | soffset_0 = *valp; |
| 2109 | offset_0 = (soffset_0 - 0x4) & 0x3ffff; |
| 2110 | *valp = offset_0; |
| 2111 | return 0; |
| 2112 | } |
| 2113 | |
| 2114 | static int |
| 2115 | Operand_soffset_ator (uint32 *valp, uint32 pc) |
| 2116 | { |
| 2117 | *valp -= pc; |
| 2118 | return 0; |
| 2119 | } |
| 2120 | |
| 2121 | static int |
| 2122 | Operand_soffset_rtoa (uint32 *valp, uint32 pc) |
| 2123 | { |
| 2124 | *valp += pc; |
| 2125 | return 0; |
| 2126 | } |
| 2127 | |
| 2128 | static int |
| 2129 | Operand_uimm16x4_decode (uint32 *valp) |
| 2130 | { |
| 2131 | unsigned uimm16x4_0, imm16_0; |
| 2132 | imm16_0 = *valp & 0xffff; |
| 2133 | uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; |
| 2134 | *valp = uimm16x4_0; |
| 2135 | return 0; |
| 2136 | } |
| 2137 | |
| 2138 | static int |
| 2139 | Operand_uimm16x4_encode (uint32 *valp) |
| 2140 | { |
| 2141 | unsigned imm16_0, uimm16x4_0; |
| 2142 | uimm16x4_0 = *valp; |
| 2143 | imm16_0 = (uimm16x4_0 >> 2) & 0xffff; |
| 2144 | *valp = imm16_0; |
| 2145 | return 0; |
| 2146 | } |
| 2147 | |
| 2148 | static int |
| 2149 | Operand_uimm16x4_ator (uint32 *valp, uint32 pc) |
| 2150 | { |
| 2151 | *valp -= ((pc + 3) & ~0x3); |
| 2152 | return 0; |
| 2153 | } |
| 2154 | |
| 2155 | static int |
| 2156 | Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) |
| 2157 | { |
| 2158 | *valp += ((pc + 3) & ~0x3); |
| 2159 | return 0; |
| 2160 | } |
| 2161 | |
| 2162 | static int |
| 2163 | Operand_immt_decode (uint32 *valp) |
| 2164 | { |
| 2165 | unsigned immt_0, t_0; |
| 2166 | t_0 = *valp & 0xf; |
| 2167 | immt_0 = t_0; |
| 2168 | *valp = immt_0; |
| 2169 | return 0; |
| 2170 | } |
| 2171 | |
| 2172 | static int |
| 2173 | Operand_immt_encode (uint32 *valp) |
| 2174 | { |
| 2175 | unsigned t_0, immt_0; |
| 2176 | immt_0 = *valp; |
| 2177 | t_0 = immt_0 & 0xf; |
| 2178 | *valp = t_0; |
| 2179 | return 0; |
| 2180 | } |
| 2181 | |
| 2182 | static int |
| 2183 | Operand_imms_decode (uint32 *valp) |
| 2184 | { |
| 2185 | unsigned imms_0, s_0; |
| 2186 | s_0 = *valp & 0xf; |
| 2187 | imms_0 = s_0; |
| 2188 | *valp = imms_0; |
| 2189 | return 0; |
| 2190 | } |
| 2191 | |
| 2192 | static int |
| 2193 | Operand_imms_encode (uint32 *valp) |
| 2194 | { |
| 2195 | unsigned s_0, imms_0; |
| 2196 | imms_0 = *valp; |
| 2197 | s_0 = imms_0 & 0xf; |
| 2198 | *valp = s_0; |
| 2199 | return 0; |
| 2200 | } |
| 2201 | |
| 2202 | static int |
| 2203 | Operand_tp7_decode (uint32 *valp) |
| 2204 | { |
| 2205 | unsigned tp7_0, t_0; |
| 2206 | t_0 = *valp & 0xf; |
| 2207 | tp7_0 = t_0 + 0x7; |
| 2208 | *valp = tp7_0; |
| 2209 | return 0; |
| 2210 | } |
| 2211 | |
| 2212 | static int |
| 2213 | Operand_tp7_encode (uint32 *valp) |
| 2214 | { |
| 2215 | unsigned t_0, tp7_0; |
| 2216 | tp7_0 = *valp; |
| 2217 | t_0 = (tp7_0 - 0x7) & 0xf; |
| 2218 | *valp = t_0; |
| 2219 | return 0; |
| 2220 | } |
| 2221 | |
| 2222 | static int |
| 2223 | Operand_xt_wbr15_label_decode (uint32 *valp) |
| 2224 | { |
| 2225 | unsigned xt_wbr15_label_0, xt_wbr15_imm_0; |
| 2226 | xt_wbr15_imm_0 = *valp & 0x7fff; |
| 2227 | xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); |
| 2228 | *valp = xt_wbr15_label_0; |
| 2229 | return 0; |
| 2230 | } |
| 2231 | |
| 2232 | static int |
| 2233 | Operand_xt_wbr15_label_encode (uint32 *valp) |
| 2234 | { |
| 2235 | unsigned xt_wbr15_imm_0, xt_wbr15_label_0; |
| 2236 | xt_wbr15_label_0 = *valp; |
| 2237 | xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; |
| 2238 | *valp = xt_wbr15_imm_0; |
| 2239 | return 0; |
| 2240 | } |
| 2241 | |
| 2242 | static int |
| 2243 | Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) |
| 2244 | { |
| 2245 | *valp -= pc; |
| 2246 | return 0; |
| 2247 | } |
| 2248 | |
| 2249 | static int |
| 2250 | Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) |
| 2251 | { |
| 2252 | *valp += pc; |
| 2253 | return 0; |
| 2254 | } |
| 2255 | |
| 2256 | static int |
| 2257 | Operand_xt_wbr18_label_decode (uint32 *valp) |
| 2258 | { |
| 2259 | unsigned xt_wbr18_label_0, xt_wbr18_imm_0; |
| 2260 | xt_wbr18_imm_0 = *valp & 0x3ffff; |
| 2261 | xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); |
| 2262 | *valp = xt_wbr18_label_0; |
| 2263 | return 0; |
| 2264 | } |
| 2265 | |
| 2266 | static int |
| 2267 | Operand_xt_wbr18_label_encode (uint32 *valp) |
| 2268 | { |
| 2269 | unsigned xt_wbr18_imm_0, xt_wbr18_label_0; |
| 2270 | xt_wbr18_label_0 = *valp; |
| 2271 | xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; |
| 2272 | *valp = xt_wbr18_imm_0; |
| 2273 | return 0; |
| 2274 | } |
| 2275 | |
| 2276 | static int |
| 2277 | Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) |
| 2278 | { |
| 2279 | *valp -= pc; |
| 2280 | return 0; |
| 2281 | } |
| 2282 | |
| 2283 | static int |
| 2284 | Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) |
| 2285 | { |
| 2286 | *valp += pc; |
| 2287 | return 0; |
| 2288 | } |
| 2289 | |
| 2290 | static xtensa_operand_internal operands[] = { |
| 2291 | { "soffsetx4", FIELD_offset, -1, 0, |
| 2292 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2293 | Operand_soffsetx4_encode, Operand_soffsetx4_decode, |
| 2294 | Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, |
| 2295 | { "uimm12x8", FIELD_imm12, -1, 0, |
| 2296 | 0, |
| 2297 | Operand_uimm12x8_encode, Operand_uimm12x8_decode, |
| 2298 | 0, 0 }, |
| 2299 | { "simm4", FIELD_mn, -1, 0, |
| 2300 | 0, |
| 2301 | Operand_simm4_encode, Operand_simm4_decode, |
| 2302 | 0, 0 }, |
| 2303 | { "arr", FIELD_r, REGFILE_AR, 1, |
| 2304 | XTENSA_OPERAND_IS_REGISTER, |
| 2305 | Operand_arr_encode, Operand_arr_decode, |
| 2306 | 0, 0 }, |
| 2307 | { "ars", FIELD_s, REGFILE_AR, 1, |
| 2308 | XTENSA_OPERAND_IS_REGISTER, |
| 2309 | Operand_ars_encode, Operand_ars_decode, |
| 2310 | 0, 0 }, |
| 2311 | { "*ars_invisible", FIELD_s, REGFILE_AR, 1, |
| 2312 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2313 | Operand_ars_encode, Operand_ars_decode, |
| 2314 | 0, 0 }, |
| 2315 | { "art", FIELD_t, REGFILE_AR, 1, |
| 2316 | XTENSA_OPERAND_IS_REGISTER, |
| 2317 | Operand_art_encode, Operand_art_decode, |
| 2318 | 0, 0 }, |
| 2319 | { "ar0", FIELD__ar0, REGFILE_AR, 1, |
| 2320 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2321 | Operand_ar0_encode, Operand_ar0_decode, |
| 2322 | 0, 0 }, |
| 2323 | { "ar4", FIELD__ar4, REGFILE_AR, 1, |
| 2324 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2325 | Operand_ar4_encode, Operand_ar4_decode, |
| 2326 | 0, 0 }, |
| 2327 | { "ar8", FIELD__ar8, REGFILE_AR, 1, |
| 2328 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2329 | Operand_ar8_encode, Operand_ar8_decode, |
| 2330 | 0, 0 }, |
| 2331 | { "ar12", FIELD__ar12, REGFILE_AR, 1, |
| 2332 | XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, |
| 2333 | Operand_ar12_encode, Operand_ar12_decode, |
| 2334 | 0, 0 }, |
| 2335 | { "ars_entry", FIELD_s, REGFILE_AR, 1, |
| 2336 | XTENSA_OPERAND_IS_REGISTER, |
| 2337 | Operand_ars_entry_encode, Operand_ars_entry_decode, |
| 2338 | 0, 0 }, |
| 2339 | { "immrx4", FIELD_r, -1, 0, |
| 2340 | 0, |
| 2341 | Operand_immrx4_encode, Operand_immrx4_decode, |
| 2342 | 0, 0 }, |
| 2343 | { "lsi4x4", FIELD_r, -1, 0, |
| 2344 | 0, |
| 2345 | Operand_lsi4x4_encode, Operand_lsi4x4_decode, |
| 2346 | 0, 0 }, |
| 2347 | { "simm7", FIELD_imm7, -1, 0, |
| 2348 | 0, |
| 2349 | Operand_simm7_encode, Operand_simm7_decode, |
| 2350 | 0, 0 }, |
| 2351 | { "uimm6", FIELD_imm6, -1, 0, |
| 2352 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2353 | Operand_uimm6_encode, Operand_uimm6_decode, |
| 2354 | Operand_uimm6_ator, Operand_uimm6_rtoa }, |
| 2355 | { "ai4const", FIELD_t, -1, 0, |
| 2356 | 0, |
| 2357 | Operand_ai4const_encode, Operand_ai4const_decode, |
| 2358 | 0, 0 }, |
| 2359 | { "b4const", FIELD_r, -1, 0, |
| 2360 | 0, |
| 2361 | Operand_b4const_encode, Operand_b4const_decode, |
| 2362 | 0, 0 }, |
| 2363 | { "b4constu", FIELD_r, -1, 0, |
| 2364 | 0, |
| 2365 | Operand_b4constu_encode, Operand_b4constu_decode, |
| 2366 | 0, 0 }, |
| 2367 | { "uimm8", FIELD_imm8, -1, 0, |
| 2368 | 0, |
| 2369 | Operand_uimm8_encode, Operand_uimm8_decode, |
| 2370 | 0, 0 }, |
| 2371 | { "uimm8x2", FIELD_imm8, -1, 0, |
| 2372 | 0, |
| 2373 | Operand_uimm8x2_encode, Operand_uimm8x2_decode, |
| 2374 | 0, 0 }, |
| 2375 | { "uimm8x4", FIELD_imm8, -1, 0, |
| 2376 | 0, |
| 2377 | Operand_uimm8x4_encode, Operand_uimm8x4_decode, |
| 2378 | 0, 0 }, |
| 2379 | { "uimm4x16", FIELD_op2, -1, 0, |
| 2380 | 0, |
| 2381 | Operand_uimm4x16_encode, Operand_uimm4x16_decode, |
| 2382 | 0, 0 }, |
| 2383 | { "simm8", FIELD_imm8, -1, 0, |
| 2384 | 0, |
| 2385 | Operand_simm8_encode, Operand_simm8_decode, |
| 2386 | 0, 0 }, |
| 2387 | { "simm8x256", FIELD_imm8, -1, 0, |
| 2388 | 0, |
| 2389 | Operand_simm8x256_encode, Operand_simm8x256_decode, |
| 2390 | 0, 0 }, |
| 2391 | { "simm12b", FIELD_imm12b, -1, 0, |
| 2392 | 0, |
| 2393 | Operand_simm12b_encode, Operand_simm12b_decode, |
| 2394 | 0, 0 }, |
| 2395 | { "msalp32", FIELD_sal, -1, 0, |
| 2396 | 0, |
| 2397 | Operand_msalp32_encode, Operand_msalp32_decode, |
| 2398 | 0, 0 }, |
| 2399 | { "op2p1", FIELD_op2, -1, 0, |
| 2400 | 0, |
| 2401 | Operand_op2p1_encode, Operand_op2p1_decode, |
| 2402 | 0, 0 }, |
| 2403 | { "label8", FIELD_imm8, -1, 0, |
| 2404 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2405 | Operand_label8_encode, Operand_label8_decode, |
| 2406 | Operand_label8_ator, Operand_label8_rtoa }, |
| 2407 | { "ulabel8", FIELD_imm8, -1, 0, |
| 2408 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2409 | Operand_ulabel8_encode, Operand_ulabel8_decode, |
| 2410 | Operand_ulabel8_ator, Operand_ulabel8_rtoa }, |
| 2411 | { "label12", FIELD_imm12, -1, 0, |
| 2412 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2413 | Operand_label12_encode, Operand_label12_decode, |
| 2414 | Operand_label12_ator, Operand_label12_rtoa }, |
| 2415 | { "soffset", FIELD_offset, -1, 0, |
| 2416 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2417 | Operand_soffset_encode, Operand_soffset_decode, |
| 2418 | Operand_soffset_ator, Operand_soffset_rtoa }, |
| 2419 | { "uimm16x4", FIELD_imm16, -1, 0, |
| 2420 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2421 | Operand_uimm16x4_encode, Operand_uimm16x4_decode, |
| 2422 | Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, |
| 2423 | { "immt", FIELD_t, -1, 0, |
| 2424 | 0, |
| 2425 | Operand_immt_encode, Operand_immt_decode, |
| 2426 | 0, 0 }, |
| 2427 | { "imms", FIELD_s, -1, 0, |
| 2428 | 0, |
| 2429 | Operand_imms_encode, Operand_imms_decode, |
| 2430 | 0, 0 }, |
| 2431 | { "tp7", FIELD_t, -1, 0, |
| 2432 | 0, |
| 2433 | Operand_tp7_encode, Operand_tp7_decode, |
| 2434 | 0, 0 }, |
| 2435 | { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, |
| 2436 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2437 | Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, |
| 2438 | Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, |
| 2439 | { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, |
| 2440 | XTENSA_OPERAND_IS_PCRELATIVE, |
| 2441 | Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, |
| 2442 | Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, |
| 2443 | { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, |
| 2444 | { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, |
| 2445 | { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, |
| 2446 | { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, |
| 2447 | { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, |
| 2448 | { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, |
| 2449 | { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, |
| 2450 | { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, |
| 2451 | { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, |
| 2452 | { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, |
| 2453 | { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, |
| 2454 | { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, |
| 2455 | { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, |
| 2456 | { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, |
| 2457 | { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, |
| 2458 | { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, |
| 2459 | { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, |
| 2460 | { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, |
| 2461 | { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, |
| 2462 | { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, |
| 2463 | { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, |
| 2464 | { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, |
| 2465 | { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, |
| 2466 | { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, |
| 2467 | { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, |
| 2468 | { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, |
| 2469 | { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, |
| 2470 | { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, |
| 2471 | { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, |
| 2472 | { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, |
| 2473 | { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, |
| 2474 | { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, |
| 2475 | { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, |
| 2476 | { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, |
| 2477 | { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, |
| 2478 | { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, |
| 2479 | { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 } |
| 2480 | }; |
| 2481 | |
| 2482 | enum xtensa_operand_id { |
| 2483 | OPERAND_soffsetx4, |
| 2484 | OPERAND_uimm12x8, |
| 2485 | OPERAND_simm4, |
| 2486 | OPERAND_arr, |
| 2487 | OPERAND_ars, |
| 2488 | OPERAND__ars_invisible, |
| 2489 | OPERAND_art, |
| 2490 | OPERAND_ar0, |
| 2491 | OPERAND_ar4, |
| 2492 | OPERAND_ar8, |
| 2493 | OPERAND_ar12, |
| 2494 | OPERAND_ars_entry, |
| 2495 | OPERAND_immrx4, |
| 2496 | OPERAND_lsi4x4, |
| 2497 | OPERAND_simm7, |
| 2498 | OPERAND_uimm6, |
| 2499 | OPERAND_ai4const, |
| 2500 | OPERAND_b4const, |
| 2501 | OPERAND_b4constu, |
| 2502 | OPERAND_uimm8, |
| 2503 | OPERAND_uimm8x2, |
| 2504 | OPERAND_uimm8x4, |
| 2505 | OPERAND_uimm4x16, |
| 2506 | OPERAND_simm8, |
| 2507 | OPERAND_simm8x256, |
| 2508 | OPERAND_simm12b, |
| 2509 | OPERAND_msalp32, |
| 2510 | OPERAND_op2p1, |
| 2511 | OPERAND_label8, |
| 2512 | OPERAND_ulabel8, |
| 2513 | OPERAND_label12, |
| 2514 | OPERAND_soffset, |
| 2515 | OPERAND_uimm16x4, |
| 2516 | OPERAND_immt, |
| 2517 | OPERAND_imms, |
| 2518 | OPERAND_tp7, |
| 2519 | OPERAND_xt_wbr15_label, |
| 2520 | OPERAND_xt_wbr18_label, |
| 2521 | OPERAND_t, |
| 2522 | OPERAND_bbi4, |
| 2523 | OPERAND_bbi, |
| 2524 | OPERAND_imm12, |
| 2525 | OPERAND_imm8, |
| 2526 | OPERAND_s, |
| 2527 | OPERAND_imm12b, |
| 2528 | OPERAND_imm16, |
| 2529 | OPERAND_m, |
| 2530 | OPERAND_n, |
| 2531 | OPERAND_offset, |
| 2532 | OPERAND_op0, |
| 2533 | OPERAND_op1, |
| 2534 | OPERAND_op2, |
| 2535 | OPERAND_r, |
| 2536 | OPERAND_sa4, |
| 2537 | OPERAND_sae4, |
| 2538 | OPERAND_sae, |
| 2539 | OPERAND_sal, |
| 2540 | OPERAND_sargt, |
| 2541 | OPERAND_sas4, |
| 2542 | OPERAND_sas, |
| 2543 | OPERAND_sr, |
| 2544 | OPERAND_st, |
| 2545 | OPERAND_thi3, |
| 2546 | OPERAND_imm4, |
| 2547 | OPERAND_mn, |
| 2548 | OPERAND_i, |
| 2549 | OPERAND_imm6lo, |
| 2550 | OPERAND_imm6hi, |
| 2551 | OPERAND_imm7lo, |
| 2552 | OPERAND_imm7hi, |
| 2553 | OPERAND_z, |
| 2554 | OPERAND_imm6, |
| 2555 | OPERAND_imm7, |
| 2556 | OPERAND_xt_wbr15_imm, |
| 2557 | OPERAND_xt_wbr18_imm |
| 2558 | }; |
| 2559 | |
| 2560 | \f |
| 2561 | /* Iclass table. */ |
| 2562 | |
| 2563 | static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { |
| 2564 | { { STATE_PSRING }, 'i' }, |
| 2565 | { { STATE_PSEXCM }, 'm' }, |
| 2566 | { { STATE_EPC1 }, 'i' } |
| 2567 | }; |
| 2568 | |
| 2569 | static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { |
| 2570 | { { STATE_PSEXCM }, 'i' }, |
| 2571 | { { STATE_PSRING }, 'i' }, |
| 2572 | { { STATE_DEPC }, 'i' } |
| 2573 | }; |
| 2574 | |
| 2575 | static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { |
| 2576 | { { OPERAND_soffsetx4 }, 'i' }, |
| 2577 | { { OPERAND_ar12 }, 'o' } |
| 2578 | }; |
| 2579 | |
| 2580 | static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { |
| 2581 | { { STATE_PSCALLINC }, 'o' } |
| 2582 | }; |
| 2583 | |
| 2584 | static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { |
| 2585 | { { OPERAND_soffsetx4 }, 'i' }, |
| 2586 | { { OPERAND_ar8 }, 'o' } |
| 2587 | }; |
| 2588 | |
| 2589 | static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { |
| 2590 | { { STATE_PSCALLINC }, 'o' } |
| 2591 | }; |
| 2592 | |
| 2593 | static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { |
| 2594 | { { OPERAND_soffsetx4 }, 'i' }, |
| 2595 | { { OPERAND_ar4 }, 'o' } |
| 2596 | }; |
| 2597 | |
| 2598 | static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { |
| 2599 | { { STATE_PSCALLINC }, 'o' } |
| 2600 | }; |
| 2601 | |
| 2602 | static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { |
| 2603 | { { OPERAND_ars }, 'i' }, |
| 2604 | { { OPERAND_ar12 }, 'o' } |
| 2605 | }; |
| 2606 | |
| 2607 | static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { |
| 2608 | { { STATE_PSCALLINC }, 'o' } |
| 2609 | }; |
| 2610 | |
| 2611 | static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { |
| 2612 | { { OPERAND_ars }, 'i' }, |
| 2613 | { { OPERAND_ar8 }, 'o' } |
| 2614 | }; |
| 2615 | |
| 2616 | static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { |
| 2617 | { { STATE_PSCALLINC }, 'o' } |
| 2618 | }; |
| 2619 | |
| 2620 | static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { |
| 2621 | { { OPERAND_ars }, 'i' }, |
| 2622 | { { OPERAND_ar4 }, 'o' } |
| 2623 | }; |
| 2624 | |
| 2625 | static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { |
| 2626 | { { STATE_PSCALLINC }, 'o' } |
| 2627 | }; |
| 2628 | |
| 2629 | static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { |
| 2630 | { { OPERAND_ars_entry }, 's' }, |
| 2631 | { { OPERAND_ars }, 'i' }, |
| 2632 | { { OPERAND_uimm12x8 }, 'i' } |
| 2633 | }; |
| 2634 | |
| 2635 | static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { |
| 2636 | { { STATE_PSCALLINC }, 'i' }, |
| 2637 | { { STATE_PSEXCM }, 'i' }, |
| 2638 | { { STATE_PSWOE }, 'i' }, |
| 2639 | { { STATE_WindowBase }, 'm' }, |
| 2640 | { { STATE_WindowStart }, 'm' } |
| 2641 | }; |
| 2642 | |
| 2643 | static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { |
| 2644 | { { OPERAND_art }, 'o' }, |
| 2645 | { { OPERAND_ars }, 'i' } |
| 2646 | }; |
| 2647 | |
| 2648 | static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { |
| 2649 | { { STATE_WindowBase }, 'i' }, |
| 2650 | { { STATE_WindowStart }, 'i' } |
| 2651 | }; |
| 2652 | |
| 2653 | static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { |
| 2654 | { { OPERAND_simm4 }, 'i' } |
| 2655 | }; |
| 2656 | |
| 2657 | static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { |
| 2658 | { { STATE_PSEXCM }, 'i' }, |
| 2659 | { { STATE_PSRING }, 'i' }, |
| 2660 | { { STATE_WindowBase }, 'm' } |
| 2661 | }; |
| 2662 | |
| 2663 | static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { |
| 2664 | { { OPERAND__ars_invisible }, 'i' } |
| 2665 | }; |
| 2666 | |
| 2667 | static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { |
| 2668 | { { STATE_WindowBase }, 'm' }, |
| 2669 | { { STATE_WindowStart }, 'm' }, |
| 2670 | { { STATE_PSEXCM }, 'i' }, |
| 2671 | { { STATE_PSWOE }, 'i' } |
| 2672 | }; |
| 2673 | |
| 2674 | static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { |
| 2675 | { { STATE_EPC1 }, 'i' }, |
| 2676 | { { STATE_PSEXCM }, 'm' }, |
| 2677 | { { STATE_PSRING }, 'i' }, |
| 2678 | { { STATE_WindowBase }, 'm' }, |
| 2679 | { { STATE_WindowStart }, 'm' }, |
| 2680 | { { STATE_PSOWB }, 'i' } |
| 2681 | }; |
| 2682 | |
| 2683 | static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { |
| 2684 | { { OPERAND_art }, 'o' }, |
| 2685 | { { OPERAND_ars }, 'i' }, |
| 2686 | { { OPERAND_immrx4 }, 'i' } |
| 2687 | }; |
| 2688 | |
| 2689 | static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { |
| 2690 | { { STATE_PSEXCM }, 'i' }, |
| 2691 | { { STATE_PSRING }, 'i' } |
| 2692 | }; |
| 2693 | |
| 2694 | static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { |
| 2695 | { { OPERAND_art }, 'i' }, |
| 2696 | { { OPERAND_ars }, 'i' }, |
| 2697 | { { OPERAND_immrx4 }, 'i' } |
| 2698 | }; |
| 2699 | |
| 2700 | static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { |
| 2701 | { { STATE_PSEXCM }, 'i' }, |
| 2702 | { { STATE_PSRING }, 'i' } |
| 2703 | }; |
| 2704 | |
| 2705 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { |
| 2706 | { { OPERAND_art }, 'o' } |
| 2707 | }; |
| 2708 | |
| 2709 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { |
| 2710 | { { STATE_PSEXCM }, 'i' }, |
| 2711 | { { STATE_PSRING }, 'i' }, |
| 2712 | { { STATE_WindowBase }, 'i' } |
| 2713 | }; |
| 2714 | |
| 2715 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { |
| 2716 | { { OPERAND_art }, 'i' } |
| 2717 | }; |
| 2718 | |
| 2719 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { |
| 2720 | { { STATE_PSEXCM }, 'i' }, |
| 2721 | { { STATE_PSRING }, 'i' }, |
| 2722 | { { STATE_WindowBase }, 'o' } |
| 2723 | }; |
| 2724 | |
| 2725 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { |
| 2726 | { { OPERAND_art }, 'm' } |
| 2727 | }; |
| 2728 | |
| 2729 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { |
| 2730 | { { STATE_PSEXCM }, 'i' }, |
| 2731 | { { STATE_PSRING }, 'i' }, |
| 2732 | { { STATE_WindowBase }, 'm' } |
| 2733 | }; |
| 2734 | |
| 2735 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { |
| 2736 | { { OPERAND_art }, 'o' } |
| 2737 | }; |
| 2738 | |
| 2739 | static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { |
| 2740 | { { STATE_PSEXCM }, 'i' }, |
| 2741 | { { STATE_PSRING }, 'i' }, |
| 2742 | { { STATE_WindowStart }, 'i' } |
| 2743 | }; |
| 2744 | |
| 2745 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { |
| 2746 | { { OPERAND_art }, 'i' } |
| 2747 | }; |
| 2748 | |
| 2749 | static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { |
| 2750 | { { STATE_PSEXCM }, 'i' }, |
| 2751 | { { STATE_PSRING }, 'i' }, |
| 2752 | { { STATE_WindowStart }, 'o' } |
| 2753 | }; |
| 2754 | |
| 2755 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { |
| 2756 | { { OPERAND_art }, 'm' } |
| 2757 | }; |
| 2758 | |
| 2759 | static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { |
| 2760 | { { STATE_PSEXCM }, 'i' }, |
| 2761 | { { STATE_PSRING }, 'i' }, |
| 2762 | { { STATE_WindowStart }, 'm' } |
| 2763 | }; |
| 2764 | |
| 2765 | static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { |
| 2766 | { { OPERAND_arr }, 'o' }, |
| 2767 | { { OPERAND_ars }, 'i' }, |
| 2768 | { { OPERAND_art }, 'i' } |
| 2769 | }; |
| 2770 | |
| 2771 | static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { |
| 2772 | { { OPERAND_arr }, 'o' }, |
| 2773 | { { OPERAND_ars }, 'i' }, |
| 2774 | { { OPERAND_ai4const }, 'i' } |
| 2775 | }; |
| 2776 | |
| 2777 | static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { |
| 2778 | { { OPERAND_ars }, 'i' }, |
| 2779 | { { OPERAND_uimm6 }, 'i' } |
| 2780 | }; |
| 2781 | |
| 2782 | static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { |
| 2783 | { { OPERAND_art }, 'o' }, |
| 2784 | { { OPERAND_ars }, 'i' }, |
| 2785 | { { OPERAND_lsi4x4 }, 'i' } |
| 2786 | }; |
| 2787 | |
| 2788 | static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { |
| 2789 | { { OPERAND_art }, 'o' }, |
| 2790 | { { OPERAND_ars }, 'i' } |
| 2791 | }; |
| 2792 | |
| 2793 | static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { |
| 2794 | { { OPERAND_ars }, 'o' }, |
| 2795 | { { OPERAND_simm7 }, 'i' } |
| 2796 | }; |
| 2797 | |
| 2798 | static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { |
| 2799 | { { OPERAND__ars_invisible }, 'i' } |
| 2800 | }; |
| 2801 | |
| 2802 | static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { |
| 2803 | { { OPERAND_art }, 'i' }, |
| 2804 | { { OPERAND_ars }, 'i' }, |
| 2805 | { { OPERAND_lsi4x4 }, 'i' } |
| 2806 | }; |
| 2807 | |
| 2808 | static xtensa_arg_internal Iclass_rur_threadptr_args[] = { |
| 2809 | { { OPERAND_arr }, 'o' } |
| 2810 | }; |
| 2811 | |
| 2812 | static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { |
| 2813 | { { STATE_THREADPTR }, 'i' } |
| 2814 | }; |
| 2815 | |
| 2816 | static xtensa_arg_internal Iclass_wur_threadptr_args[] = { |
| 2817 | { { OPERAND_art }, 'i' } |
| 2818 | }; |
| 2819 | |
| 2820 | static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { |
| 2821 | { { STATE_THREADPTR }, 'o' } |
| 2822 | }; |
| 2823 | |
| 2824 | static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { |
| 2825 | { { OPERAND_art }, 'o' }, |
| 2826 | { { OPERAND_ars }, 'i' }, |
| 2827 | { { OPERAND_simm8 }, 'i' } |
| 2828 | }; |
| 2829 | |
| 2830 | static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { |
| 2831 | { { OPERAND_art }, 'o' }, |
| 2832 | { { OPERAND_ars }, 'i' }, |
| 2833 | { { OPERAND_simm8x256 }, 'i' } |
| 2834 | }; |
| 2835 | |
| 2836 | static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { |
| 2837 | { { OPERAND_arr }, 'o' }, |
| 2838 | { { OPERAND_ars }, 'i' }, |
| 2839 | { { OPERAND_art }, 'i' } |
| 2840 | }; |
| 2841 | |
| 2842 | static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { |
| 2843 | { { OPERAND_arr }, 'o' }, |
| 2844 | { { OPERAND_ars }, 'i' }, |
| 2845 | { { OPERAND_art }, 'i' } |
| 2846 | }; |
| 2847 | |
| 2848 | static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { |
| 2849 | { { OPERAND_ars }, 'i' }, |
| 2850 | { { OPERAND_b4const }, 'i' }, |
| 2851 | { { OPERAND_label8 }, 'i' } |
| 2852 | }; |
| 2853 | |
| 2854 | static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { |
| 2855 | { { OPERAND_ars }, 'i' }, |
| 2856 | { { OPERAND_bbi }, 'i' }, |
| 2857 | { { OPERAND_label8 }, 'i' } |
| 2858 | }; |
| 2859 | |
| 2860 | static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { |
| 2861 | { { OPERAND_ars }, 'i' }, |
| 2862 | { { OPERAND_b4constu }, 'i' }, |
| 2863 | { { OPERAND_label8 }, 'i' } |
| 2864 | }; |
| 2865 | |
| 2866 | static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { |
| 2867 | { { OPERAND_ars }, 'i' }, |
| 2868 | { { OPERAND_art }, 'i' }, |
| 2869 | { { OPERAND_label8 }, 'i' } |
| 2870 | }; |
| 2871 | |
| 2872 | static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { |
| 2873 | { { OPERAND_ars }, 'i' }, |
| 2874 | { { OPERAND_label12 }, 'i' } |
| 2875 | }; |
| 2876 | |
| 2877 | static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { |
| 2878 | { { OPERAND_soffsetx4 }, 'i' }, |
| 2879 | { { OPERAND_ar0 }, 'o' } |
| 2880 | }; |
| 2881 | |
| 2882 | static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { |
| 2883 | { { OPERAND_ars }, 'i' }, |
| 2884 | { { OPERAND_ar0 }, 'o' } |
| 2885 | }; |
| 2886 | |
| 2887 | static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { |
| 2888 | { { OPERAND_arr }, 'o' }, |
| 2889 | { { OPERAND_art }, 'i' }, |
| 2890 | { { OPERAND_sae }, 'i' }, |
| 2891 | { { OPERAND_op2p1 }, 'i' } |
| 2892 | }; |
| 2893 | |
| 2894 | static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { |
| 2895 | { { OPERAND_soffset }, 'i' } |
| 2896 | }; |
| 2897 | |
| 2898 | static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { |
| 2899 | { { OPERAND_ars }, 'i' } |
| 2900 | }; |
| 2901 | |
| 2902 | static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { |
| 2903 | { { OPERAND_art }, 'o' }, |
| 2904 | { { OPERAND_ars }, 'i' }, |
| 2905 | { { OPERAND_uimm8x2 }, 'i' } |
| 2906 | }; |
| 2907 | |
| 2908 | static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { |
| 2909 | { { OPERAND_art }, 'o' }, |
| 2910 | { { OPERAND_ars }, 'i' }, |
| 2911 | { { OPERAND_uimm8x2 }, 'i' } |
| 2912 | }; |
| 2913 | |
| 2914 | static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { |
| 2915 | { { OPERAND_art }, 'o' }, |
| 2916 | { { OPERAND_ars }, 'i' }, |
| 2917 | { { OPERAND_uimm8x4 }, 'i' } |
| 2918 | }; |
| 2919 | |
| 2920 | static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { |
| 2921 | { { OPERAND_art }, 'o' }, |
| 2922 | { { OPERAND_uimm16x4 }, 'i' } |
| 2923 | }; |
| 2924 | |
| 2925 | static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { |
| 2926 | { { STATE_LITBADDR }, 'i' }, |
| 2927 | { { STATE_LITBEN }, 'i' } |
| 2928 | }; |
| 2929 | |
| 2930 | static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { |
| 2931 | { { OPERAND_art }, 'o' }, |
| 2932 | { { OPERAND_ars }, 'i' }, |
| 2933 | { { OPERAND_uimm8 }, 'i' } |
| 2934 | }; |
| 2935 | |
| 2936 | static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { |
| 2937 | { { OPERAND_ars }, 'i' }, |
| 2938 | { { OPERAND_ulabel8 }, 'i' } |
| 2939 | }; |
| 2940 | |
| 2941 | static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { |
| 2942 | { { STATE_LBEG }, 'o' }, |
| 2943 | { { STATE_LEND }, 'o' }, |
| 2944 | { { STATE_LCOUNT }, 'o' } |
| 2945 | }; |
| 2946 | |
| 2947 | static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { |
| 2948 | { { OPERAND_ars }, 'i' }, |
| 2949 | { { OPERAND_ulabel8 }, 'i' } |
| 2950 | }; |
| 2951 | |
| 2952 | static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { |
| 2953 | { { STATE_LBEG }, 'o' }, |
| 2954 | { { STATE_LEND }, 'o' }, |
| 2955 | { { STATE_LCOUNT }, 'o' } |
| 2956 | }; |
| 2957 | |
| 2958 | static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { |
| 2959 | { { OPERAND_art }, 'o' }, |
| 2960 | { { OPERAND_simm12b }, 'i' } |
| 2961 | }; |
| 2962 | |
| 2963 | static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { |
| 2964 | { { OPERAND_arr }, 'm' }, |
| 2965 | { { OPERAND_ars }, 'i' }, |
| 2966 | { { OPERAND_art }, 'i' } |
| 2967 | }; |
| 2968 | |
| 2969 | static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { |
| 2970 | { { OPERAND_arr }, 'o' }, |
| 2971 | { { OPERAND_art }, 'i' } |
| 2972 | }; |
| 2973 | |
| 2974 | static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { |
| 2975 | { { OPERAND__ars_invisible }, 'i' } |
| 2976 | }; |
| 2977 | |
| 2978 | static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { |
| 2979 | { { OPERAND_art }, 'i' }, |
| 2980 | { { OPERAND_ars }, 'i' }, |
| 2981 | { { OPERAND_uimm8x2 }, 'i' } |
| 2982 | }; |
| 2983 | |
| 2984 | static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { |
| 2985 | { { OPERAND_art }, 'i' }, |
| 2986 | { { OPERAND_ars }, 'i' }, |
| 2987 | { { OPERAND_uimm8x4 }, 'i' } |
| 2988 | }; |
| 2989 | |
| 2990 | static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { |
| 2991 | { { OPERAND_art }, 'i' }, |
| 2992 | { { OPERAND_ars }, 'i' }, |
| 2993 | { { OPERAND_uimm8 }, 'i' } |
| 2994 | }; |
| 2995 | |
| 2996 | static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { |
| 2997 | { { OPERAND_ars }, 'i' } |
| 2998 | }; |
| 2999 | |
| 3000 | static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { |
| 3001 | { { STATE_SAR }, 'o' } |
| 3002 | }; |
| 3003 | |
| 3004 | static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { |
| 3005 | { { OPERAND_sas }, 'i' } |
| 3006 | }; |
| 3007 | |
| 3008 | static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { |
| 3009 | { { STATE_SAR }, 'o' } |
| 3010 | }; |
| 3011 | |
| 3012 | static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { |
| 3013 | { { OPERAND_arr }, 'o' }, |
| 3014 | { { OPERAND_ars }, 'i' } |
| 3015 | }; |
| 3016 | |
| 3017 | static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { |
| 3018 | { { STATE_SAR }, 'i' } |
| 3019 | }; |
| 3020 | |
| 3021 | static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { |
| 3022 | { { OPERAND_arr }, 'o' }, |
| 3023 | { { OPERAND_ars }, 'i' }, |
| 3024 | { { OPERAND_art }, 'i' } |
| 3025 | }; |
| 3026 | |
| 3027 | static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { |
| 3028 | { { STATE_SAR }, 'i' } |
| 3029 | }; |
| 3030 | |
| 3031 | static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { |
| 3032 | { { OPERAND_arr }, 'o' }, |
| 3033 | { { OPERAND_art }, 'i' } |
| 3034 | }; |
| 3035 | |
| 3036 | static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { |
| 3037 | { { STATE_SAR }, 'i' } |
| 3038 | }; |
| 3039 | |
| 3040 | static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { |
| 3041 | { { OPERAND_arr }, 'o' }, |
| 3042 | { { OPERAND_ars }, 'i' }, |
| 3043 | { { OPERAND_msalp32 }, 'i' } |
| 3044 | }; |
| 3045 | |
| 3046 | static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { |
| 3047 | { { OPERAND_arr }, 'o' }, |
| 3048 | { { OPERAND_art }, 'i' }, |
| 3049 | { { OPERAND_sargt }, 'i' } |
| 3050 | }; |
| 3051 | |
| 3052 | static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { |
| 3053 | { { OPERAND_arr }, 'o' }, |
| 3054 | { { OPERAND_art }, 'i' }, |
| 3055 | { { OPERAND_s }, 'i' } |
| 3056 | }; |
| 3057 | |
| 3058 | static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { |
| 3059 | { { STATE_XTSYNC }, 'i' } |
| 3060 | }; |
| 3061 | |
| 3062 | static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { |
| 3063 | { { OPERAND_art }, 'o' }, |
| 3064 | { { OPERAND_s }, 'i' } |
| 3065 | }; |
| 3066 | |
| 3067 | static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { |
| 3068 | { { STATE_PSWOE }, 'i' }, |
| 3069 | { { STATE_PSCALLINC }, 'i' }, |
| 3070 | { { STATE_PSOWB }, 'i' }, |
| 3071 | { { STATE_PSRING }, 'i' }, |
| 3072 | { { STATE_PSUM }, 'i' }, |
| 3073 | { { STATE_PSEXCM }, 'i' }, |
| 3074 | { { STATE_PSINTLEVEL }, 'm' } |
| 3075 | }; |
| 3076 | |
| 3077 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { |
| 3078 | { { OPERAND_art }, 'o' } |
| 3079 | }; |
| 3080 | |
| 3081 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { |
| 3082 | { { STATE_LEND }, 'i' } |
| 3083 | }; |
| 3084 | |
| 3085 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { |
| 3086 | { { OPERAND_art }, 'i' } |
| 3087 | }; |
| 3088 | |
| 3089 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { |
| 3090 | { { STATE_LEND }, 'o' } |
| 3091 | }; |
| 3092 | |
| 3093 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { |
| 3094 | { { OPERAND_art }, 'm' } |
| 3095 | }; |
| 3096 | |
| 3097 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { |
| 3098 | { { STATE_LEND }, 'm' } |
| 3099 | }; |
| 3100 | |
| 3101 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { |
| 3102 | { { OPERAND_art }, 'o' } |
| 3103 | }; |
| 3104 | |
| 3105 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { |
| 3106 | { { STATE_LCOUNT }, 'i' } |
| 3107 | }; |
| 3108 | |
| 3109 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { |
| 3110 | { { OPERAND_art }, 'i' } |
| 3111 | }; |
| 3112 | |
| 3113 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { |
| 3114 | { { STATE_XTSYNC }, 'o' }, |
| 3115 | { { STATE_LCOUNT }, 'o' } |
| 3116 | }; |
| 3117 | |
| 3118 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { |
| 3119 | { { OPERAND_art }, 'm' } |
| 3120 | }; |
| 3121 | |
| 3122 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { |
| 3123 | { { STATE_XTSYNC }, 'o' }, |
| 3124 | { { STATE_LCOUNT }, 'm' } |
| 3125 | }; |
| 3126 | |
| 3127 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { |
| 3128 | { { OPERAND_art }, 'o' } |
| 3129 | }; |
| 3130 | |
| 3131 | static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { |
| 3132 | { { STATE_LBEG }, 'i' } |
| 3133 | }; |
| 3134 | |
| 3135 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { |
| 3136 | { { OPERAND_art }, 'i' } |
| 3137 | }; |
| 3138 | |
| 3139 | static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { |
| 3140 | { { STATE_LBEG }, 'o' } |
| 3141 | }; |
| 3142 | |
| 3143 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { |
| 3144 | { { OPERAND_art }, 'm' } |
| 3145 | }; |
| 3146 | |
| 3147 | static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { |
| 3148 | { { STATE_LBEG }, 'm' } |
| 3149 | }; |
| 3150 | |
| 3151 | static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { |
| 3152 | { { OPERAND_art }, 'o' } |
| 3153 | }; |
| 3154 | |
| 3155 | static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { |
| 3156 | { { STATE_SAR }, 'i' } |
| 3157 | }; |
| 3158 | |
| 3159 | static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { |
| 3160 | { { OPERAND_art }, 'i' } |
| 3161 | }; |
| 3162 | |
| 3163 | static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { |
| 3164 | { { STATE_SAR }, 'o' }, |
| 3165 | { { STATE_XTSYNC }, 'o' } |
| 3166 | }; |
| 3167 | |
| 3168 | static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { |
| 3169 | { { OPERAND_art }, 'm' } |
| 3170 | }; |
| 3171 | |
| 3172 | static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { |
| 3173 | { { STATE_SAR }, 'm' } |
| 3174 | }; |
| 3175 | |
| 3176 | static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { |
| 3177 | { { OPERAND_art }, 'o' } |
| 3178 | }; |
| 3179 | |
| 3180 | static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { |
| 3181 | { { STATE_LITBADDR }, 'i' }, |
| 3182 | { { STATE_LITBEN }, 'i' } |
| 3183 | }; |
| 3184 | |
| 3185 | static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { |
| 3186 | { { OPERAND_art }, 'i' } |
| 3187 | }; |
| 3188 | |
| 3189 | static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { |
| 3190 | { { STATE_LITBADDR }, 'o' }, |
| 3191 | { { STATE_LITBEN }, 'o' } |
| 3192 | }; |
| 3193 | |
| 3194 | static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { |
| 3195 | { { OPERAND_art }, 'm' } |
| 3196 | }; |
| 3197 | |
| 3198 | static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { |
| 3199 | { { STATE_LITBADDR }, 'm' }, |
| 3200 | { { STATE_LITBEN }, 'm' } |
| 3201 | }; |
| 3202 | |
| 3203 | static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { |
| 3204 | { { OPERAND_art }, 'o' } |
| 3205 | }; |
| 3206 | |
| 3207 | static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { |
| 3208 | { { STATE_PSEXCM }, 'i' }, |
| 3209 | { { STATE_PSRING }, 'i' } |
| 3210 | }; |
| 3211 | |
| 3212 | static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { |
| 3213 | { { OPERAND_art }, 'i' } |
| 3214 | }; |
| 3215 | |
| 3216 | static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = { |
| 3217 | { { STATE_PSEXCM }, 'i' }, |
| 3218 | { { STATE_PSRING }, 'i' } |
| 3219 | }; |
| 3220 | |
| 3221 | static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { |
| 3222 | { { OPERAND_art }, 'o' } |
| 3223 | }; |
| 3224 | |
| 3225 | static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { |
| 3226 | { { STATE_PSEXCM }, 'i' }, |
| 3227 | { { STATE_PSRING }, 'i' } |
| 3228 | }; |
| 3229 | |
| 3230 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { |
| 3231 | { { OPERAND_art }, 'o' } |
| 3232 | }; |
| 3233 | |
| 3234 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { |
| 3235 | { { STATE_PSWOE }, 'i' }, |
| 3236 | { { STATE_PSCALLINC }, 'i' }, |
| 3237 | { { STATE_PSOWB }, 'i' }, |
| 3238 | { { STATE_PSRING }, 'i' }, |
| 3239 | { { STATE_PSUM }, 'i' }, |
| 3240 | { { STATE_PSEXCM }, 'i' }, |
| 3241 | { { STATE_PSINTLEVEL }, 'i' } |
| 3242 | }; |
| 3243 | |
| 3244 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { |
| 3245 | { { OPERAND_art }, 'i' } |
| 3246 | }; |
| 3247 | |
| 3248 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { |
| 3249 | { { STATE_PSWOE }, 'o' }, |
| 3250 | { { STATE_PSCALLINC }, 'o' }, |
| 3251 | { { STATE_PSOWB }, 'o' }, |
| 3252 | { { STATE_PSRING }, 'm' }, |
| 3253 | { { STATE_PSUM }, 'o' }, |
| 3254 | { { STATE_PSEXCM }, 'm' }, |
| 3255 | { { STATE_PSINTLEVEL }, 'o' } |
| 3256 | }; |
| 3257 | |
| 3258 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { |
| 3259 | { { OPERAND_art }, 'm' } |
| 3260 | }; |
| 3261 | |
| 3262 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { |
| 3263 | { { STATE_PSWOE }, 'm' }, |
| 3264 | { { STATE_PSCALLINC }, 'm' }, |
| 3265 | { { STATE_PSOWB }, 'm' }, |
| 3266 | { { STATE_PSRING }, 'm' }, |
| 3267 | { { STATE_PSUM }, 'm' }, |
| 3268 | { { STATE_PSEXCM }, 'm' }, |
| 3269 | { { STATE_PSINTLEVEL }, 'm' } |
| 3270 | }; |
| 3271 | |
| 3272 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { |
| 3273 | { { OPERAND_art }, 'o' } |
| 3274 | }; |
| 3275 | |
| 3276 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { |
| 3277 | { { STATE_PSEXCM }, 'i' }, |
| 3278 | { { STATE_PSRING }, 'i' }, |
| 3279 | { { STATE_EPC1 }, 'i' } |
| 3280 | }; |
| 3281 | |
| 3282 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { |
| 3283 | { { OPERAND_art }, 'i' } |
| 3284 | }; |
| 3285 | |
| 3286 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { |
| 3287 | { { STATE_PSEXCM }, 'i' }, |
| 3288 | { { STATE_PSRING }, 'i' }, |
| 3289 | { { STATE_EPC1 }, 'o' } |
| 3290 | }; |
| 3291 | |
| 3292 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { |
| 3293 | { { OPERAND_art }, 'm' } |
| 3294 | }; |
| 3295 | |
| 3296 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { |
| 3297 | { { STATE_PSEXCM }, 'i' }, |
| 3298 | { { STATE_PSRING }, 'i' }, |
| 3299 | { { STATE_EPC1 }, 'm' } |
| 3300 | }; |
| 3301 | |
| 3302 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { |
| 3303 | { { OPERAND_art }, 'o' } |
| 3304 | }; |
| 3305 | |
| 3306 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { |
| 3307 | { { STATE_PSEXCM }, 'i' }, |
| 3308 | { { STATE_PSRING }, 'i' }, |
| 3309 | { { STATE_EXCSAVE1 }, 'i' } |
| 3310 | }; |
| 3311 | |
| 3312 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { |
| 3313 | { { OPERAND_art }, 'i' } |
| 3314 | }; |
| 3315 | |
| 3316 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { |
| 3317 | { { STATE_PSEXCM }, 'i' }, |
| 3318 | { { STATE_PSRING }, 'i' }, |
| 3319 | { { STATE_EXCSAVE1 }, 'o' } |
| 3320 | }; |
| 3321 | |
| 3322 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { |
| 3323 | { { OPERAND_art }, 'm' } |
| 3324 | }; |
| 3325 | |
| 3326 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { |
| 3327 | { { STATE_PSEXCM }, 'i' }, |
| 3328 | { { STATE_PSRING }, 'i' }, |
| 3329 | { { STATE_EXCSAVE1 }, 'm' } |
| 3330 | }; |
| 3331 | |
| 3332 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { |
| 3333 | { { OPERAND_art }, 'o' } |
| 3334 | }; |
| 3335 | |
| 3336 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { |
| 3337 | { { STATE_PSEXCM }, 'i' }, |
| 3338 | { { STATE_PSRING }, 'i' }, |
| 3339 | { { STATE_EPC2 }, 'i' } |
| 3340 | }; |
| 3341 | |
| 3342 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { |
| 3343 | { { OPERAND_art }, 'i' } |
| 3344 | }; |
| 3345 | |
| 3346 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { |
| 3347 | { { STATE_PSEXCM }, 'i' }, |
| 3348 | { { STATE_PSRING }, 'i' }, |
| 3349 | { { STATE_EPC2 }, 'o' } |
| 3350 | }; |
| 3351 | |
| 3352 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { |
| 3353 | { { OPERAND_art }, 'm' } |
| 3354 | }; |
| 3355 | |
| 3356 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { |
| 3357 | { { STATE_PSEXCM }, 'i' }, |
| 3358 | { { STATE_PSRING }, 'i' }, |
| 3359 | { { STATE_EPC2 }, 'm' } |
| 3360 | }; |
| 3361 | |
| 3362 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { |
| 3363 | { { OPERAND_art }, 'o' } |
| 3364 | }; |
| 3365 | |
| 3366 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { |
| 3367 | { { STATE_PSEXCM }, 'i' }, |
| 3368 | { { STATE_PSRING }, 'i' }, |
| 3369 | { { STATE_EXCSAVE2 }, 'i' } |
| 3370 | }; |
| 3371 | |
| 3372 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { |
| 3373 | { { OPERAND_art }, 'i' } |
| 3374 | }; |
| 3375 | |
| 3376 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { |
| 3377 | { { STATE_PSEXCM }, 'i' }, |
| 3378 | { { STATE_PSRING }, 'i' }, |
| 3379 | { { STATE_EXCSAVE2 }, 'o' } |
| 3380 | }; |
| 3381 | |
| 3382 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { |
| 3383 | { { OPERAND_art }, 'm' } |
| 3384 | }; |
| 3385 | |
| 3386 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { |
| 3387 | { { STATE_PSEXCM }, 'i' }, |
| 3388 | { { STATE_PSRING }, 'i' }, |
| 3389 | { { STATE_EXCSAVE2 }, 'm' } |
| 3390 | }; |
| 3391 | |
| 3392 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { |
| 3393 | { { OPERAND_art }, 'o' } |
| 3394 | }; |
| 3395 | |
| 3396 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { |
| 3397 | { { STATE_PSEXCM }, 'i' }, |
| 3398 | { { STATE_PSRING }, 'i' }, |
| 3399 | { { STATE_EPC3 }, 'i' } |
| 3400 | }; |
| 3401 | |
| 3402 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { |
| 3403 | { { OPERAND_art }, 'i' } |
| 3404 | }; |
| 3405 | |
| 3406 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { |
| 3407 | { { STATE_PSEXCM }, 'i' }, |
| 3408 | { { STATE_PSRING }, 'i' }, |
| 3409 | { { STATE_EPC3 }, 'o' } |
| 3410 | }; |
| 3411 | |
| 3412 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { |
| 3413 | { { OPERAND_art }, 'm' } |
| 3414 | }; |
| 3415 | |
| 3416 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { |
| 3417 | { { STATE_PSEXCM }, 'i' }, |
| 3418 | { { STATE_PSRING }, 'i' }, |
| 3419 | { { STATE_EPC3 }, 'm' } |
| 3420 | }; |
| 3421 | |
| 3422 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { |
| 3423 | { { OPERAND_art }, 'o' } |
| 3424 | }; |
| 3425 | |
| 3426 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { |
| 3427 | { { STATE_PSEXCM }, 'i' }, |
| 3428 | { { STATE_PSRING }, 'i' }, |
| 3429 | { { STATE_EXCSAVE3 }, 'i' } |
| 3430 | }; |
| 3431 | |
| 3432 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { |
| 3433 | { { OPERAND_art }, 'i' } |
| 3434 | }; |
| 3435 | |
| 3436 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { |
| 3437 | { { STATE_PSEXCM }, 'i' }, |
| 3438 | { { STATE_PSRING }, 'i' }, |
| 3439 | { { STATE_EXCSAVE3 }, 'o' } |
| 3440 | }; |
| 3441 | |
| 3442 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { |
| 3443 | { { OPERAND_art }, 'm' } |
| 3444 | }; |
| 3445 | |
| 3446 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { |
| 3447 | { { STATE_PSEXCM }, 'i' }, |
| 3448 | { { STATE_PSRING }, 'i' }, |
| 3449 | { { STATE_EXCSAVE3 }, 'm' } |
| 3450 | }; |
| 3451 | |
| 3452 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { |
| 3453 | { { OPERAND_art }, 'o' } |
| 3454 | }; |
| 3455 | |
| 3456 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { |
| 3457 | { { STATE_PSEXCM }, 'i' }, |
| 3458 | { { STATE_PSRING }, 'i' }, |
| 3459 | { { STATE_EPC4 }, 'i' } |
| 3460 | }; |
| 3461 | |
| 3462 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { |
| 3463 | { { OPERAND_art }, 'i' } |
| 3464 | }; |
| 3465 | |
| 3466 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { |
| 3467 | { { STATE_PSEXCM }, 'i' }, |
| 3468 | { { STATE_PSRING }, 'i' }, |
| 3469 | { { STATE_EPC4 }, 'o' } |
| 3470 | }; |
| 3471 | |
| 3472 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { |
| 3473 | { { OPERAND_art }, 'm' } |
| 3474 | }; |
| 3475 | |
| 3476 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { |
| 3477 | { { STATE_PSEXCM }, 'i' }, |
| 3478 | { { STATE_PSRING }, 'i' }, |
| 3479 | { { STATE_EPC4 }, 'm' } |
| 3480 | }; |
| 3481 | |
| 3482 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { |
| 3483 | { { OPERAND_art }, 'o' } |
| 3484 | }; |
| 3485 | |
| 3486 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { |
| 3487 | { { STATE_PSEXCM }, 'i' }, |
| 3488 | { { STATE_PSRING }, 'i' }, |
| 3489 | { { STATE_EXCSAVE4 }, 'i' } |
| 3490 | }; |
| 3491 | |
| 3492 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { |
| 3493 | { { OPERAND_art }, 'i' } |
| 3494 | }; |
| 3495 | |
| 3496 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { |
| 3497 | { { STATE_PSEXCM }, 'i' }, |
| 3498 | { { STATE_PSRING }, 'i' }, |
| 3499 | { { STATE_EXCSAVE4 }, 'o' } |
| 3500 | }; |
| 3501 | |
| 3502 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { |
| 3503 | { { OPERAND_art }, 'm' } |
| 3504 | }; |
| 3505 | |
| 3506 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { |
| 3507 | { { STATE_PSEXCM }, 'i' }, |
| 3508 | { { STATE_PSRING }, 'i' }, |
| 3509 | { { STATE_EXCSAVE4 }, 'm' } |
| 3510 | }; |
| 3511 | |
| 3512 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { |
| 3513 | { { OPERAND_art }, 'o' } |
| 3514 | }; |
| 3515 | |
| 3516 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { |
| 3517 | { { STATE_PSEXCM }, 'i' }, |
| 3518 | { { STATE_PSRING }, 'i' }, |
| 3519 | { { STATE_EPC5 }, 'i' } |
| 3520 | }; |
| 3521 | |
| 3522 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { |
| 3523 | { { OPERAND_art }, 'i' } |
| 3524 | }; |
| 3525 | |
| 3526 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { |
| 3527 | { { STATE_PSEXCM }, 'i' }, |
| 3528 | { { STATE_PSRING }, 'i' }, |
| 3529 | { { STATE_EPC5 }, 'o' } |
| 3530 | }; |
| 3531 | |
| 3532 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { |
| 3533 | { { OPERAND_art }, 'm' } |
| 3534 | }; |
| 3535 | |
| 3536 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { |
| 3537 | { { STATE_PSEXCM }, 'i' }, |
| 3538 | { { STATE_PSRING }, 'i' }, |
| 3539 | { { STATE_EPC5 }, 'm' } |
| 3540 | }; |
| 3541 | |
| 3542 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { |
| 3543 | { { OPERAND_art }, 'o' } |
| 3544 | }; |
| 3545 | |
| 3546 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { |
| 3547 | { { STATE_PSEXCM }, 'i' }, |
| 3548 | { { STATE_PSRING }, 'i' }, |
| 3549 | { { STATE_EXCSAVE5 }, 'i' } |
| 3550 | }; |
| 3551 | |
| 3552 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { |
| 3553 | { { OPERAND_art }, 'i' } |
| 3554 | }; |
| 3555 | |
| 3556 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { |
| 3557 | { { STATE_PSEXCM }, 'i' }, |
| 3558 | { { STATE_PSRING }, 'i' }, |
| 3559 | { { STATE_EXCSAVE5 }, 'o' } |
| 3560 | }; |
| 3561 | |
| 3562 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { |
| 3563 | { { OPERAND_art }, 'm' } |
| 3564 | }; |
| 3565 | |
| 3566 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { |
| 3567 | { { STATE_PSEXCM }, 'i' }, |
| 3568 | { { STATE_PSRING }, 'i' }, |
| 3569 | { { STATE_EXCSAVE5 }, 'm' } |
| 3570 | }; |
| 3571 | |
| 3572 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { |
| 3573 | { { OPERAND_art }, 'o' } |
| 3574 | }; |
| 3575 | |
| 3576 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { |
| 3577 | { { STATE_PSEXCM }, 'i' }, |
| 3578 | { { STATE_PSRING }, 'i' }, |
| 3579 | { { STATE_EPC6 }, 'i' } |
| 3580 | }; |
| 3581 | |
| 3582 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { |
| 3583 | { { OPERAND_art }, 'i' } |
| 3584 | }; |
| 3585 | |
| 3586 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { |
| 3587 | { { STATE_PSEXCM }, 'i' }, |
| 3588 | { { STATE_PSRING }, 'i' }, |
| 3589 | { { STATE_EPC6 }, 'o' } |
| 3590 | }; |
| 3591 | |
| 3592 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { |
| 3593 | { { OPERAND_art }, 'm' } |
| 3594 | }; |
| 3595 | |
| 3596 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { |
| 3597 | { { STATE_PSEXCM }, 'i' }, |
| 3598 | { { STATE_PSRING }, 'i' }, |
| 3599 | { { STATE_EPC6 }, 'm' } |
| 3600 | }; |
| 3601 | |
| 3602 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { |
| 3603 | { { OPERAND_art }, 'o' } |
| 3604 | }; |
| 3605 | |
| 3606 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { |
| 3607 | { { STATE_PSEXCM }, 'i' }, |
| 3608 | { { STATE_PSRING }, 'i' }, |
| 3609 | { { STATE_EXCSAVE6 }, 'i' } |
| 3610 | }; |
| 3611 | |
| 3612 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { |
| 3613 | { { OPERAND_art }, 'i' } |
| 3614 | }; |
| 3615 | |
| 3616 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { |
| 3617 | { { STATE_PSEXCM }, 'i' }, |
| 3618 | { { STATE_PSRING }, 'i' }, |
| 3619 | { { STATE_EXCSAVE6 }, 'o' } |
| 3620 | }; |
| 3621 | |
| 3622 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { |
| 3623 | { { OPERAND_art }, 'm' } |
| 3624 | }; |
| 3625 | |
| 3626 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { |
| 3627 | { { STATE_PSEXCM }, 'i' }, |
| 3628 | { { STATE_PSRING }, 'i' }, |
| 3629 | { { STATE_EXCSAVE6 }, 'm' } |
| 3630 | }; |
| 3631 | |
| 3632 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { |
| 3633 | { { OPERAND_art }, 'o' } |
| 3634 | }; |
| 3635 | |
| 3636 | static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { |
| 3637 | { { STATE_PSEXCM }, 'i' }, |
| 3638 | { { STATE_PSRING }, 'i' }, |
| 3639 | { { STATE_EPC7 }, 'i' } |
| 3640 | }; |
| 3641 | |
| 3642 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { |
| 3643 | { { OPERAND_art }, 'i' } |
| 3644 | }; |
| 3645 | |
| 3646 | static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { |
| 3647 | { { STATE_PSEXCM }, 'i' }, |
| 3648 | { { STATE_PSRING }, 'i' }, |
| 3649 | { { STATE_EPC7 }, 'o' } |
| 3650 | }; |
| 3651 | |
| 3652 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { |
| 3653 | { { OPERAND_art }, 'm' } |
| 3654 | }; |
| 3655 | |
| 3656 | static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { |
| 3657 | { { STATE_PSEXCM }, 'i' }, |
| 3658 | { { STATE_PSRING }, 'i' }, |
| 3659 | { { STATE_EPC7 }, 'm' } |
| 3660 | }; |
| 3661 | |
| 3662 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { |
| 3663 | { { OPERAND_art }, 'o' } |
| 3664 | }; |
| 3665 | |
| 3666 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { |
| 3667 | { { STATE_PSEXCM }, 'i' }, |
| 3668 | { { STATE_PSRING }, 'i' }, |
| 3669 | { { STATE_EXCSAVE7 }, 'i' } |
| 3670 | }; |
| 3671 | |
| 3672 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { |
| 3673 | { { OPERAND_art }, 'i' } |
| 3674 | }; |
| 3675 | |
| 3676 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { |
| 3677 | { { STATE_PSEXCM }, 'i' }, |
| 3678 | { { STATE_PSRING }, 'i' }, |
| 3679 | { { STATE_EXCSAVE7 }, 'o' } |
| 3680 | }; |
| 3681 | |
| 3682 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { |
| 3683 | { { OPERAND_art }, 'm' } |
| 3684 | }; |
| 3685 | |
| 3686 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { |
| 3687 | { { STATE_PSEXCM }, 'i' }, |
| 3688 | { { STATE_PSRING }, 'i' }, |
| 3689 | { { STATE_EXCSAVE7 }, 'm' } |
| 3690 | }; |
| 3691 | |
| 3692 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { |
| 3693 | { { OPERAND_art }, 'o' } |
| 3694 | }; |
| 3695 | |
| 3696 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { |
| 3697 | { { STATE_PSEXCM }, 'i' }, |
| 3698 | { { STATE_PSRING }, 'i' }, |
| 3699 | { { STATE_EPS2 }, 'i' } |
| 3700 | }; |
| 3701 | |
| 3702 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { |
| 3703 | { { OPERAND_art }, 'i' } |
| 3704 | }; |
| 3705 | |
| 3706 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { |
| 3707 | { { STATE_PSEXCM }, 'i' }, |
| 3708 | { { STATE_PSRING }, 'i' }, |
| 3709 | { { STATE_EPS2 }, 'o' } |
| 3710 | }; |
| 3711 | |
| 3712 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { |
| 3713 | { { OPERAND_art }, 'm' } |
| 3714 | }; |
| 3715 | |
| 3716 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { |
| 3717 | { { STATE_PSEXCM }, 'i' }, |
| 3718 | { { STATE_PSRING }, 'i' }, |
| 3719 | { { STATE_EPS2 }, 'm' } |
| 3720 | }; |
| 3721 | |
| 3722 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { |
| 3723 | { { OPERAND_art }, 'o' } |
| 3724 | }; |
| 3725 | |
| 3726 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { |
| 3727 | { { STATE_PSEXCM }, 'i' }, |
| 3728 | { { STATE_PSRING }, 'i' }, |
| 3729 | { { STATE_EPS3 }, 'i' } |
| 3730 | }; |
| 3731 | |
| 3732 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { |
| 3733 | { { OPERAND_art }, 'i' } |
| 3734 | }; |
| 3735 | |
| 3736 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { |
| 3737 | { { STATE_PSEXCM }, 'i' }, |
| 3738 | { { STATE_PSRING }, 'i' }, |
| 3739 | { { STATE_EPS3 }, 'o' } |
| 3740 | }; |
| 3741 | |
| 3742 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { |
| 3743 | { { OPERAND_art }, 'm' } |
| 3744 | }; |
| 3745 | |
| 3746 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { |
| 3747 | { { STATE_PSEXCM }, 'i' }, |
| 3748 | { { STATE_PSRING }, 'i' }, |
| 3749 | { { STATE_EPS3 }, 'm' } |
| 3750 | }; |
| 3751 | |
| 3752 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { |
| 3753 | { { OPERAND_art }, 'o' } |
| 3754 | }; |
| 3755 | |
| 3756 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { |
| 3757 | { { STATE_PSEXCM }, 'i' }, |
| 3758 | { { STATE_PSRING }, 'i' }, |
| 3759 | { { STATE_EPS4 }, 'i' } |
| 3760 | }; |
| 3761 | |
| 3762 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { |
| 3763 | { { OPERAND_art }, 'i' } |
| 3764 | }; |
| 3765 | |
| 3766 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { |
| 3767 | { { STATE_PSEXCM }, 'i' }, |
| 3768 | { { STATE_PSRING }, 'i' }, |
| 3769 | { { STATE_EPS4 }, 'o' } |
| 3770 | }; |
| 3771 | |
| 3772 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { |
| 3773 | { { OPERAND_art }, 'm' } |
| 3774 | }; |
| 3775 | |
| 3776 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { |
| 3777 | { { STATE_PSEXCM }, 'i' }, |
| 3778 | { { STATE_PSRING }, 'i' }, |
| 3779 | { { STATE_EPS4 }, 'm' } |
| 3780 | }; |
| 3781 | |
| 3782 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { |
| 3783 | { { OPERAND_art }, 'o' } |
| 3784 | }; |
| 3785 | |
| 3786 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { |
| 3787 | { { STATE_PSEXCM }, 'i' }, |
| 3788 | { { STATE_PSRING }, 'i' }, |
| 3789 | { { STATE_EPS5 }, 'i' } |
| 3790 | }; |
| 3791 | |
| 3792 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { |
| 3793 | { { OPERAND_art }, 'i' } |
| 3794 | }; |
| 3795 | |
| 3796 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { |
| 3797 | { { STATE_PSEXCM }, 'i' }, |
| 3798 | { { STATE_PSRING }, 'i' }, |
| 3799 | { { STATE_EPS5 }, 'o' } |
| 3800 | }; |
| 3801 | |
| 3802 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { |
| 3803 | { { OPERAND_art }, 'm' } |
| 3804 | }; |
| 3805 | |
| 3806 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { |
| 3807 | { { STATE_PSEXCM }, 'i' }, |
| 3808 | { { STATE_PSRING }, 'i' }, |
| 3809 | { { STATE_EPS5 }, 'm' } |
| 3810 | }; |
| 3811 | |
| 3812 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { |
| 3813 | { { OPERAND_art }, 'o' } |
| 3814 | }; |
| 3815 | |
| 3816 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { |
| 3817 | { { STATE_PSEXCM }, 'i' }, |
| 3818 | { { STATE_PSRING }, 'i' }, |
| 3819 | { { STATE_EPS6 }, 'i' } |
| 3820 | }; |
| 3821 | |
| 3822 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { |
| 3823 | { { OPERAND_art }, 'i' } |
| 3824 | }; |
| 3825 | |
| 3826 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { |
| 3827 | { { STATE_PSEXCM }, 'i' }, |
| 3828 | { { STATE_PSRING }, 'i' }, |
| 3829 | { { STATE_EPS6 }, 'o' } |
| 3830 | }; |
| 3831 | |
| 3832 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { |
| 3833 | { { OPERAND_art }, 'm' } |
| 3834 | }; |
| 3835 | |
| 3836 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { |
| 3837 | { { STATE_PSEXCM }, 'i' }, |
| 3838 | { { STATE_PSRING }, 'i' }, |
| 3839 | { { STATE_EPS6 }, 'm' } |
| 3840 | }; |
| 3841 | |
| 3842 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { |
| 3843 | { { OPERAND_art }, 'o' } |
| 3844 | }; |
| 3845 | |
| 3846 | static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { |
| 3847 | { { STATE_PSEXCM }, 'i' }, |
| 3848 | { { STATE_PSRING }, 'i' }, |
| 3849 | { { STATE_EPS7 }, 'i' } |
| 3850 | }; |
| 3851 | |
| 3852 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { |
| 3853 | { { OPERAND_art }, 'i' } |
| 3854 | }; |
| 3855 | |
| 3856 | static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { |
| 3857 | { { STATE_PSEXCM }, 'i' }, |
| 3858 | { { STATE_PSRING }, 'i' }, |
| 3859 | { { STATE_EPS7 }, 'o' } |
| 3860 | }; |
| 3861 | |
| 3862 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { |
| 3863 | { { OPERAND_art }, 'm' } |
| 3864 | }; |
| 3865 | |
| 3866 | static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { |
| 3867 | { { STATE_PSEXCM }, 'i' }, |
| 3868 | { { STATE_PSRING }, 'i' }, |
| 3869 | { { STATE_EPS7 }, 'm' } |
| 3870 | }; |
| 3871 | |
| 3872 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { |
| 3873 | { { OPERAND_art }, 'o' } |
| 3874 | }; |
| 3875 | |
| 3876 | static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { |
| 3877 | { { STATE_PSEXCM }, 'i' }, |
| 3878 | { { STATE_PSRING }, 'i' }, |
| 3879 | { { STATE_EXCVADDR }, 'i' } |
| 3880 | }; |
| 3881 | |
| 3882 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { |
| 3883 | { { OPERAND_art }, 'i' } |
| 3884 | }; |
| 3885 | |
| 3886 | static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { |
| 3887 | { { STATE_PSEXCM }, 'i' }, |
| 3888 | { { STATE_PSRING }, 'i' }, |
| 3889 | { { STATE_EXCVADDR }, 'o' } |
| 3890 | }; |
| 3891 | |
| 3892 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { |
| 3893 | { { OPERAND_art }, 'm' } |
| 3894 | }; |
| 3895 | |
| 3896 | static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { |
| 3897 | { { STATE_PSEXCM }, 'i' }, |
| 3898 | { { STATE_PSRING }, 'i' }, |
| 3899 | { { STATE_EXCVADDR }, 'm' } |
| 3900 | }; |
| 3901 | |
| 3902 | static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { |
| 3903 | { { OPERAND_art }, 'o' } |
| 3904 | }; |
| 3905 | |
| 3906 | static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { |
| 3907 | { { STATE_PSEXCM }, 'i' }, |
| 3908 | { { STATE_PSRING }, 'i' }, |
| 3909 | { { STATE_DEPC }, 'i' } |
| 3910 | }; |
| 3911 | |
| 3912 | static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { |
| 3913 | { { OPERAND_art }, 'i' } |
| 3914 | }; |
| 3915 | |
| 3916 | static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { |
| 3917 | { { STATE_PSEXCM }, 'i' }, |
| 3918 | { { STATE_PSRING }, 'i' }, |
| 3919 | { { STATE_DEPC }, 'o' } |
| 3920 | }; |
| 3921 | |
| 3922 | static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { |
| 3923 | { { OPERAND_art }, 'm' } |
| 3924 | }; |
| 3925 | |
| 3926 | static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { |
| 3927 | { { STATE_PSEXCM }, 'i' }, |
| 3928 | { { STATE_PSRING }, 'i' }, |
| 3929 | { { STATE_DEPC }, 'm' } |
| 3930 | }; |
| 3931 | |
| 3932 | static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { |
| 3933 | { { OPERAND_art }, 'o' } |
| 3934 | }; |
| 3935 | |
| 3936 | static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { |
| 3937 | { { STATE_PSEXCM }, 'i' }, |
| 3938 | { { STATE_PSRING }, 'i' }, |
| 3939 | { { STATE_EXCCAUSE }, 'i' }, |
| 3940 | { { STATE_XTSYNC }, 'i' } |
| 3941 | }; |
| 3942 | |
| 3943 | static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { |
| 3944 | { { OPERAND_art }, 'i' } |
| 3945 | }; |
| 3946 | |
| 3947 | static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { |
| 3948 | { { STATE_PSEXCM }, 'i' }, |
| 3949 | { { STATE_PSRING }, 'i' }, |
| 3950 | { { STATE_EXCCAUSE }, 'o' } |
| 3951 | }; |
| 3952 | |
| 3953 | static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { |
| 3954 | { { OPERAND_art }, 'm' } |
| 3955 | }; |
| 3956 | |
| 3957 | static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { |
| 3958 | { { STATE_PSEXCM }, 'i' }, |
| 3959 | { { STATE_PSRING }, 'i' }, |
| 3960 | { { STATE_EXCCAUSE }, 'm' } |
| 3961 | }; |
| 3962 | |
| 3963 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { |
| 3964 | { { OPERAND_art }, 'o' } |
| 3965 | }; |
| 3966 | |
| 3967 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { |
| 3968 | { { STATE_PSEXCM }, 'i' }, |
| 3969 | { { STATE_PSRING }, 'i' }, |
| 3970 | { { STATE_MISC0 }, 'i' } |
| 3971 | }; |
| 3972 | |
| 3973 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { |
| 3974 | { { OPERAND_art }, 'i' } |
| 3975 | }; |
| 3976 | |
| 3977 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { |
| 3978 | { { STATE_PSEXCM }, 'i' }, |
| 3979 | { { STATE_PSRING }, 'i' }, |
| 3980 | { { STATE_MISC0 }, 'o' } |
| 3981 | }; |
| 3982 | |
| 3983 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { |
| 3984 | { { OPERAND_art }, 'm' } |
| 3985 | }; |
| 3986 | |
| 3987 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { |
| 3988 | { { STATE_PSEXCM }, 'i' }, |
| 3989 | { { STATE_PSRING }, 'i' }, |
| 3990 | { { STATE_MISC0 }, 'm' } |
| 3991 | }; |
| 3992 | |
| 3993 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { |
| 3994 | { { OPERAND_art }, 'o' } |
| 3995 | }; |
| 3996 | |
| 3997 | static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { |
| 3998 | { { STATE_PSEXCM }, 'i' }, |
| 3999 | { { STATE_PSRING }, 'i' }, |
| 4000 | { { STATE_MISC1 }, 'i' } |
| 4001 | }; |
| 4002 | |
| 4003 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { |
| 4004 | { { OPERAND_art }, 'i' } |
| 4005 | }; |
| 4006 | |
| 4007 | static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { |
| 4008 | { { STATE_PSEXCM }, 'i' }, |
| 4009 | { { STATE_PSRING }, 'i' }, |
| 4010 | { { STATE_MISC1 }, 'o' } |
| 4011 | }; |
| 4012 | |
| 4013 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { |
| 4014 | { { OPERAND_art }, 'm' } |
| 4015 | }; |
| 4016 | |
| 4017 | static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { |
| 4018 | { { STATE_PSEXCM }, 'i' }, |
| 4019 | { { STATE_PSRING }, 'i' }, |
| 4020 | { { STATE_MISC1 }, 'm' } |
| 4021 | }; |
| 4022 | |
| 4023 | static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { |
| 4024 | { { OPERAND_art }, 'o' } |
| 4025 | }; |
| 4026 | |
| 4027 | static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { |
| 4028 | { { STATE_PSEXCM }, 'i' }, |
| 4029 | { { STATE_PSRING }, 'i' } |
| 4030 | }; |
| 4031 | |
| 4032 | static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { |
| 4033 | { { OPERAND_art }, 'o' } |
| 4034 | }; |
| 4035 | |
| 4036 | static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { |
| 4037 | { { STATE_PSEXCM }, 'i' }, |
| 4038 | { { STATE_PSRING }, 'i' }, |
| 4039 | { { STATE_VECBASE }, 'i' } |
| 4040 | }; |
| 4041 | |
| 4042 | static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { |
| 4043 | { { OPERAND_art }, 'i' } |
| 4044 | }; |
| 4045 | |
| 4046 | static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { |
| 4047 | { { STATE_PSEXCM }, 'i' }, |
| 4048 | { { STATE_PSRING }, 'i' }, |
| 4049 | { { STATE_VECBASE }, 'o' } |
| 4050 | }; |
| 4051 | |
| 4052 | static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { |
| 4053 | { { OPERAND_art }, 'm' } |
| 4054 | }; |
| 4055 | |
| 4056 | static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { |
| 4057 | { { STATE_PSEXCM }, 'i' }, |
| 4058 | { { STATE_PSRING }, 'i' }, |
| 4059 | { { STATE_VECBASE }, 'm' } |
| 4060 | }; |
| 4061 | |
| 4062 | static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { |
| 4063 | { { OPERAND_arr }, 'o' }, |
| 4064 | { { OPERAND_ars }, 'i' }, |
| 4065 | { { OPERAND_art }, 'i' } |
| 4066 | }; |
| 4067 | |
| 4068 | static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { |
| 4069 | { { OPERAND_s }, 'i' } |
| 4070 | }; |
| 4071 | |
| 4072 | static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { |
| 4073 | { { STATE_PSWOE }, 'o' }, |
| 4074 | { { STATE_PSCALLINC }, 'o' }, |
| 4075 | { { STATE_PSOWB }, 'o' }, |
| 4076 | { { STATE_PSRING }, 'm' }, |
| 4077 | { { STATE_PSUM }, 'o' }, |
| 4078 | { { STATE_PSEXCM }, 'm' }, |
| 4079 | { { STATE_PSINTLEVEL }, 'o' }, |
| 4080 | { { STATE_EPC1 }, 'i' }, |
| 4081 | { { STATE_EPC2 }, 'i' }, |
| 4082 | { { STATE_EPC3 }, 'i' }, |
| 4083 | { { STATE_EPC4 }, 'i' }, |
| 4084 | { { STATE_EPC5 }, 'i' }, |
| 4085 | { { STATE_EPC6 }, 'i' }, |
| 4086 | { { STATE_EPC7 }, 'i' }, |
| 4087 | { { STATE_EPS2 }, 'i' }, |
| 4088 | { { STATE_EPS3 }, 'i' }, |
| 4089 | { { STATE_EPS4 }, 'i' }, |
| 4090 | { { STATE_EPS5 }, 'i' }, |
| 4091 | { { STATE_EPS6 }, 'i' }, |
| 4092 | { { STATE_EPS7 }, 'i' }, |
| 4093 | { { STATE_InOCDMode }, 'm' } |
| 4094 | }; |
| 4095 | |
| 4096 | static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { |
| 4097 | { { OPERAND_s }, 'i' } |
| 4098 | }; |
| 4099 | |
| 4100 | static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { |
| 4101 | { { STATE_PSEXCM }, 'i' }, |
| 4102 | { { STATE_PSRING }, 'i' }, |
| 4103 | { { STATE_PSINTLEVEL }, 'o' } |
| 4104 | }; |
| 4105 | |
| 4106 | static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { |
| 4107 | { { OPERAND_art }, 'o' } |
| 4108 | }; |
| 4109 | |
| 4110 | static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { |
| 4111 | { { STATE_PSEXCM }, 'i' }, |
| 4112 | { { STATE_PSRING }, 'i' }, |
| 4113 | { { STATE_INTERRUPT }, 'i' } |
| 4114 | }; |
| 4115 | |
| 4116 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { |
| 4117 | { { OPERAND_art }, 'i' } |
| 4118 | }; |
| 4119 | |
| 4120 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { |
| 4121 | { { STATE_PSEXCM }, 'i' }, |
| 4122 | { { STATE_PSRING }, 'i' }, |
| 4123 | { { STATE_XTSYNC }, 'o' }, |
| 4124 | { { STATE_INTERRUPT }, 'm' } |
| 4125 | }; |
| 4126 | |
| 4127 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { |
| 4128 | { { OPERAND_art }, 'i' } |
| 4129 | }; |
| 4130 | |
| 4131 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { |
| 4132 | { { STATE_PSEXCM }, 'i' }, |
| 4133 | { { STATE_PSRING }, 'i' }, |
| 4134 | { { STATE_XTSYNC }, 'o' }, |
| 4135 | { { STATE_INTERRUPT }, 'm' } |
| 4136 | }; |
| 4137 | |
| 4138 | static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { |
| 4139 | { { OPERAND_art }, 'o' } |
| 4140 | }; |
| 4141 | |
| 4142 | static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { |
| 4143 | { { STATE_PSEXCM }, 'i' }, |
| 4144 | { { STATE_PSRING }, 'i' }, |
| 4145 | { { STATE_INTENABLE }, 'i' } |
| 4146 | }; |
| 4147 | |
| 4148 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { |
| 4149 | { { OPERAND_art }, 'i' } |
| 4150 | }; |
| 4151 | |
| 4152 | static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { |
| 4153 | { { STATE_PSEXCM }, 'i' }, |
| 4154 | { { STATE_PSRING }, 'i' }, |
| 4155 | { { STATE_INTENABLE }, 'o' } |
| 4156 | }; |
| 4157 | |
| 4158 | static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { |
| 4159 | { { OPERAND_art }, 'm' } |
| 4160 | }; |
| 4161 | |
| 4162 | static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { |
| 4163 | { { STATE_PSEXCM }, 'i' }, |
| 4164 | { { STATE_PSRING }, 'i' }, |
| 4165 | { { STATE_INTENABLE }, 'm' } |
| 4166 | }; |
| 4167 | |
| 4168 | static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { |
| 4169 | { { OPERAND_imms }, 'i' }, |
| 4170 | { { OPERAND_immt }, 'i' } |
| 4171 | }; |
| 4172 | |
| 4173 | static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { |
| 4174 | { { STATE_PSEXCM }, 'i' }, |
| 4175 | { { STATE_PSINTLEVEL }, 'i' } |
| 4176 | }; |
| 4177 | |
| 4178 | static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { |
| 4179 | { { OPERAND_imms }, 'i' } |
| 4180 | }; |
| 4181 | |
| 4182 | static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { |
| 4183 | { { STATE_PSEXCM }, 'i' }, |
| 4184 | { { STATE_PSINTLEVEL }, 'i' } |
| 4185 | }; |
| 4186 | |
| 4187 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { |
| 4188 | { { OPERAND_art }, 'o' } |
| 4189 | }; |
| 4190 | |
| 4191 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { |
| 4192 | { { STATE_PSEXCM }, 'i' }, |
| 4193 | { { STATE_PSRING }, 'i' }, |
| 4194 | { { STATE_DBREAKA0 }, 'i' } |
| 4195 | }; |
| 4196 | |
| 4197 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { |
| 4198 | { { OPERAND_art }, 'i' } |
| 4199 | }; |
| 4200 | |
| 4201 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { |
| 4202 | { { STATE_PSEXCM }, 'i' }, |
| 4203 | { { STATE_PSRING }, 'i' }, |
| 4204 | { { STATE_DBREAKA0 }, 'o' }, |
| 4205 | { { STATE_XTSYNC }, 'o' } |
| 4206 | }; |
| 4207 | |
| 4208 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { |
| 4209 | { { OPERAND_art }, 'm' } |
| 4210 | }; |
| 4211 | |
| 4212 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { |
| 4213 | { { STATE_PSEXCM }, 'i' }, |
| 4214 | { { STATE_PSRING }, 'i' }, |
| 4215 | { { STATE_DBREAKA0 }, 'm' }, |
| 4216 | { { STATE_XTSYNC }, 'o' } |
| 4217 | }; |
| 4218 | |
| 4219 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { |
| 4220 | { { OPERAND_art }, 'o' } |
| 4221 | }; |
| 4222 | |
| 4223 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { |
| 4224 | { { STATE_PSEXCM }, 'i' }, |
| 4225 | { { STATE_PSRING }, 'i' }, |
| 4226 | { { STATE_DBREAKC0 }, 'i' } |
| 4227 | }; |
| 4228 | |
| 4229 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { |
| 4230 | { { OPERAND_art }, 'i' } |
| 4231 | }; |
| 4232 | |
| 4233 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { |
| 4234 | { { STATE_PSEXCM }, 'i' }, |
| 4235 | { { STATE_PSRING }, 'i' }, |
| 4236 | { { STATE_DBREAKC0 }, 'o' }, |
| 4237 | { { STATE_XTSYNC }, 'o' } |
| 4238 | }; |
| 4239 | |
| 4240 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { |
| 4241 | { { OPERAND_art }, 'm' } |
| 4242 | }; |
| 4243 | |
| 4244 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { |
| 4245 | { { STATE_PSEXCM }, 'i' }, |
| 4246 | { { STATE_PSRING }, 'i' }, |
| 4247 | { { STATE_DBREAKC0 }, 'm' }, |
| 4248 | { { STATE_XTSYNC }, 'o' } |
| 4249 | }; |
| 4250 | |
| 4251 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { |
| 4252 | { { OPERAND_art }, 'o' } |
| 4253 | }; |
| 4254 | |
| 4255 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { |
| 4256 | { { STATE_PSEXCM }, 'i' }, |
| 4257 | { { STATE_PSRING }, 'i' }, |
| 4258 | { { STATE_DBREAKA1 }, 'i' } |
| 4259 | }; |
| 4260 | |
| 4261 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { |
| 4262 | { { OPERAND_art }, 'i' } |
| 4263 | }; |
| 4264 | |
| 4265 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { |
| 4266 | { { STATE_PSEXCM }, 'i' }, |
| 4267 | { { STATE_PSRING }, 'i' }, |
| 4268 | { { STATE_DBREAKA1 }, 'o' }, |
| 4269 | { { STATE_XTSYNC }, 'o' } |
| 4270 | }; |
| 4271 | |
| 4272 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { |
| 4273 | { { OPERAND_art }, 'm' } |
| 4274 | }; |
| 4275 | |
| 4276 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { |
| 4277 | { { STATE_PSEXCM }, 'i' }, |
| 4278 | { { STATE_PSRING }, 'i' }, |
| 4279 | { { STATE_DBREAKA1 }, 'm' }, |
| 4280 | { { STATE_XTSYNC }, 'o' } |
| 4281 | }; |
| 4282 | |
| 4283 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { |
| 4284 | { { OPERAND_art }, 'o' } |
| 4285 | }; |
| 4286 | |
| 4287 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { |
| 4288 | { { STATE_PSEXCM }, 'i' }, |
| 4289 | { { STATE_PSRING }, 'i' }, |
| 4290 | { { STATE_DBREAKC1 }, 'i' } |
| 4291 | }; |
| 4292 | |
| 4293 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { |
| 4294 | { { OPERAND_art }, 'i' } |
| 4295 | }; |
| 4296 | |
| 4297 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { |
| 4298 | { { STATE_PSEXCM }, 'i' }, |
| 4299 | { { STATE_PSRING }, 'i' }, |
| 4300 | { { STATE_DBREAKC1 }, 'o' }, |
| 4301 | { { STATE_XTSYNC }, 'o' } |
| 4302 | }; |
| 4303 | |
| 4304 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { |
| 4305 | { { OPERAND_art }, 'm' } |
| 4306 | }; |
| 4307 | |
| 4308 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { |
| 4309 | { { STATE_PSEXCM }, 'i' }, |
| 4310 | { { STATE_PSRING }, 'i' }, |
| 4311 | { { STATE_DBREAKC1 }, 'm' }, |
| 4312 | { { STATE_XTSYNC }, 'o' } |
| 4313 | }; |
| 4314 | |
| 4315 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { |
| 4316 | { { OPERAND_art }, 'o' } |
| 4317 | }; |
| 4318 | |
| 4319 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { |
| 4320 | { { STATE_PSEXCM }, 'i' }, |
| 4321 | { { STATE_PSRING }, 'i' }, |
| 4322 | { { STATE_IBREAKA0 }, 'i' } |
| 4323 | }; |
| 4324 | |
| 4325 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { |
| 4326 | { { OPERAND_art }, 'i' } |
| 4327 | }; |
| 4328 | |
| 4329 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { |
| 4330 | { { STATE_PSEXCM }, 'i' }, |
| 4331 | { { STATE_PSRING }, 'i' }, |
| 4332 | { { STATE_IBREAKA0 }, 'o' } |
| 4333 | }; |
| 4334 | |
| 4335 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { |
| 4336 | { { OPERAND_art }, 'm' } |
| 4337 | }; |
| 4338 | |
| 4339 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { |
| 4340 | { { STATE_PSEXCM }, 'i' }, |
| 4341 | { { STATE_PSRING }, 'i' }, |
| 4342 | { { STATE_IBREAKA0 }, 'm' } |
| 4343 | }; |
| 4344 | |
| 4345 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { |
| 4346 | { { OPERAND_art }, 'o' } |
| 4347 | }; |
| 4348 | |
| 4349 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { |
| 4350 | { { STATE_PSEXCM }, 'i' }, |
| 4351 | { { STATE_PSRING }, 'i' }, |
| 4352 | { { STATE_IBREAKA1 }, 'i' } |
| 4353 | }; |
| 4354 | |
| 4355 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { |
| 4356 | { { OPERAND_art }, 'i' } |
| 4357 | }; |
| 4358 | |
| 4359 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { |
| 4360 | { { STATE_PSEXCM }, 'i' }, |
| 4361 | { { STATE_PSRING }, 'i' }, |
| 4362 | { { STATE_IBREAKA1 }, 'o' } |
| 4363 | }; |
| 4364 | |
| 4365 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { |
| 4366 | { { OPERAND_art }, 'm' } |
| 4367 | }; |
| 4368 | |
| 4369 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { |
| 4370 | { { STATE_PSEXCM }, 'i' }, |
| 4371 | { { STATE_PSRING }, 'i' }, |
| 4372 | { { STATE_IBREAKA1 }, 'm' } |
| 4373 | }; |
| 4374 | |
| 4375 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { |
| 4376 | { { OPERAND_art }, 'o' } |
| 4377 | }; |
| 4378 | |
| 4379 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { |
| 4380 | { { STATE_PSEXCM }, 'i' }, |
| 4381 | { { STATE_PSRING }, 'i' }, |
| 4382 | { { STATE_IBREAKENABLE }, 'i' } |
| 4383 | }; |
| 4384 | |
| 4385 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { |
| 4386 | { { OPERAND_art }, 'i' } |
| 4387 | }; |
| 4388 | |
| 4389 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { |
| 4390 | { { STATE_PSEXCM }, 'i' }, |
| 4391 | { { STATE_PSRING }, 'i' }, |
| 4392 | { { STATE_IBREAKENABLE }, 'o' } |
| 4393 | }; |
| 4394 | |
| 4395 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { |
| 4396 | { { OPERAND_art }, 'm' } |
| 4397 | }; |
| 4398 | |
| 4399 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { |
| 4400 | { { STATE_PSEXCM }, 'i' }, |
| 4401 | { { STATE_PSRING }, 'i' }, |
| 4402 | { { STATE_IBREAKENABLE }, 'm' } |
| 4403 | }; |
| 4404 | |
| 4405 | static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { |
| 4406 | { { OPERAND_art }, 'o' } |
| 4407 | }; |
| 4408 | |
| 4409 | static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { |
| 4410 | { { STATE_PSEXCM }, 'i' }, |
| 4411 | { { STATE_PSRING }, 'i' }, |
| 4412 | { { STATE_DEBUGCAUSE }, 'i' }, |
| 4413 | { { STATE_DBNUM }, 'i' } |
| 4414 | }; |
| 4415 | |
| 4416 | static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { |
| 4417 | { { OPERAND_art }, 'i' } |
| 4418 | }; |
| 4419 | |
| 4420 | static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { |
| 4421 | { { STATE_PSEXCM }, 'i' }, |
| 4422 | { { STATE_PSRING }, 'i' }, |
| 4423 | { { STATE_DEBUGCAUSE }, 'o' }, |
| 4424 | { { STATE_DBNUM }, 'o' } |
| 4425 | }; |
| 4426 | |
| 4427 | static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { |
| 4428 | { { OPERAND_art }, 'm' } |
| 4429 | }; |
| 4430 | |
| 4431 | static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { |
| 4432 | { { STATE_PSEXCM }, 'i' }, |
| 4433 | { { STATE_PSRING }, 'i' }, |
| 4434 | { { STATE_DEBUGCAUSE }, 'm' }, |
| 4435 | { { STATE_DBNUM }, 'm' } |
| 4436 | }; |
| 4437 | |
| 4438 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { |
| 4439 | { { OPERAND_art }, 'o' } |
| 4440 | }; |
| 4441 | |
| 4442 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { |
| 4443 | { { STATE_PSEXCM }, 'i' }, |
| 4444 | { { STATE_PSRING }, 'i' }, |
| 4445 | { { STATE_ICOUNT }, 'i' } |
| 4446 | }; |
| 4447 | |
| 4448 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { |
| 4449 | { { OPERAND_art }, 'i' } |
| 4450 | }; |
| 4451 | |
| 4452 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { |
| 4453 | { { STATE_PSEXCM }, 'i' }, |
| 4454 | { { STATE_PSRING }, 'i' }, |
| 4455 | { { STATE_XTSYNC }, 'o' }, |
| 4456 | { { STATE_ICOUNT }, 'o' } |
| 4457 | }; |
| 4458 | |
| 4459 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { |
| 4460 | { { OPERAND_art }, 'm' } |
| 4461 | }; |
| 4462 | |
| 4463 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { |
| 4464 | { { STATE_PSEXCM }, 'i' }, |
| 4465 | { { STATE_PSRING }, 'i' }, |
| 4466 | { { STATE_XTSYNC }, 'o' }, |
| 4467 | { { STATE_ICOUNT }, 'm' } |
| 4468 | }; |
| 4469 | |
| 4470 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { |
| 4471 | { { OPERAND_art }, 'o' } |
| 4472 | }; |
| 4473 | |
| 4474 | static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { |
| 4475 | { { STATE_PSEXCM }, 'i' }, |
| 4476 | { { STATE_PSRING }, 'i' }, |
| 4477 | { { STATE_ICOUNTLEVEL }, 'i' } |
| 4478 | }; |
| 4479 | |
| 4480 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { |
| 4481 | { { OPERAND_art }, 'i' } |
| 4482 | }; |
| 4483 | |
| 4484 | static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { |
| 4485 | { { STATE_PSEXCM }, 'i' }, |
| 4486 | { { STATE_PSRING }, 'i' }, |
| 4487 | { { STATE_ICOUNTLEVEL }, 'o' } |
| 4488 | }; |
| 4489 | |
| 4490 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { |
| 4491 | { { OPERAND_art }, 'm' } |
| 4492 | }; |
| 4493 | |
| 4494 | static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { |
| 4495 | { { STATE_PSEXCM }, 'i' }, |
| 4496 | { { STATE_PSRING }, 'i' }, |
| 4497 | { { STATE_ICOUNTLEVEL }, 'm' } |
| 4498 | }; |
| 4499 | |
| 4500 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { |
| 4501 | { { OPERAND_art }, 'o' } |
| 4502 | }; |
| 4503 | |
| 4504 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { |
| 4505 | { { STATE_PSEXCM }, 'i' }, |
| 4506 | { { STATE_PSRING }, 'i' }, |
| 4507 | { { STATE_DDR }, 'i' } |
| 4508 | }; |
| 4509 | |
| 4510 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { |
| 4511 | { { OPERAND_art }, 'i' } |
| 4512 | }; |
| 4513 | |
| 4514 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { |
| 4515 | { { STATE_PSEXCM }, 'i' }, |
| 4516 | { { STATE_PSRING }, 'i' }, |
| 4517 | { { STATE_XTSYNC }, 'o' }, |
| 4518 | { { STATE_DDR }, 'o' } |
| 4519 | }; |
| 4520 | |
| 4521 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { |
| 4522 | { { OPERAND_art }, 'm' } |
| 4523 | }; |
| 4524 | |
| 4525 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { |
| 4526 | { { STATE_PSEXCM }, 'i' }, |
| 4527 | { { STATE_PSRING }, 'i' }, |
| 4528 | { { STATE_XTSYNC }, 'o' }, |
| 4529 | { { STATE_DDR }, 'm' } |
| 4530 | }; |
| 4531 | |
| 4532 | static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { |
| 4533 | { { OPERAND_imms }, 'i' } |
| 4534 | }; |
| 4535 | |
| 4536 | static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { |
| 4537 | { { STATE_InOCDMode }, 'm' }, |
| 4538 | { { STATE_EPC6 }, 'i' }, |
| 4539 | { { STATE_PSWOE }, 'o' }, |
| 4540 | { { STATE_PSCALLINC }, 'o' }, |
| 4541 | { { STATE_PSOWB }, 'o' }, |
| 4542 | { { STATE_PSRING }, 'o' }, |
| 4543 | { { STATE_PSUM }, 'o' }, |
| 4544 | { { STATE_PSEXCM }, 'o' }, |
| 4545 | { { STATE_PSINTLEVEL }, 'o' }, |
| 4546 | { { STATE_EPS6 }, 'i' } |
| 4547 | }; |
| 4548 | |
| 4549 | static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { |
| 4550 | { { STATE_InOCDMode }, 'm' } |
| 4551 | }; |
| 4552 | |
| 4553 | static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { |
| 4554 | { { OPERAND_art }, 'i' } |
| 4555 | }; |
| 4556 | |
| 4557 | static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { |
| 4558 | { { STATE_PSEXCM }, 'i' }, |
| 4559 | { { STATE_PSRING }, 'i' }, |
| 4560 | { { STATE_XTSYNC }, 'o' } |
| 4561 | }; |
| 4562 | |
| 4563 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { |
| 4564 | { { OPERAND_art }, 'o' } |
| 4565 | }; |
| 4566 | |
| 4567 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { |
| 4568 | { { STATE_PSEXCM }, 'i' }, |
| 4569 | { { STATE_PSRING }, 'i' }, |
| 4570 | { { STATE_CCOUNT }, 'i' } |
| 4571 | }; |
| 4572 | |
| 4573 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { |
| 4574 | { { OPERAND_art }, 'i' } |
| 4575 | }; |
| 4576 | |
| 4577 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { |
| 4578 | { { STATE_PSEXCM }, 'i' }, |
| 4579 | { { STATE_PSRING }, 'i' }, |
| 4580 | { { STATE_XTSYNC }, 'o' }, |
| 4581 | { { STATE_CCOUNT }, 'o' } |
| 4582 | }; |
| 4583 | |
| 4584 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { |
| 4585 | { { OPERAND_art }, 'm' } |
| 4586 | }; |
| 4587 | |
| 4588 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { |
| 4589 | { { STATE_PSEXCM }, 'i' }, |
| 4590 | { { STATE_PSRING }, 'i' }, |
| 4591 | { { STATE_XTSYNC }, 'o' }, |
| 4592 | { { STATE_CCOUNT }, 'm' } |
| 4593 | }; |
| 4594 | |
| 4595 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { |
| 4596 | { { OPERAND_art }, 'o' } |
| 4597 | }; |
| 4598 | |
| 4599 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { |
| 4600 | { { STATE_PSEXCM }, 'i' }, |
| 4601 | { { STATE_PSRING }, 'i' }, |
| 4602 | { { STATE_CCOMPARE0 }, 'i' } |
| 4603 | }; |
| 4604 | |
| 4605 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { |
| 4606 | { { OPERAND_art }, 'i' } |
| 4607 | }; |
| 4608 | |
| 4609 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { |
| 4610 | { { STATE_PSEXCM }, 'i' }, |
| 4611 | { { STATE_PSRING }, 'i' }, |
| 4612 | { { STATE_CCOMPARE0 }, 'o' }, |
| 4613 | { { STATE_INTERRUPT }, 'm' } |
| 4614 | }; |
| 4615 | |
| 4616 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { |
| 4617 | { { OPERAND_art }, 'm' } |
| 4618 | }; |
| 4619 | |
| 4620 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { |
| 4621 | { { STATE_PSEXCM }, 'i' }, |
| 4622 | { { STATE_PSRING }, 'i' }, |
| 4623 | { { STATE_CCOMPARE0 }, 'm' }, |
| 4624 | { { STATE_INTERRUPT }, 'm' } |
| 4625 | }; |
| 4626 | |
| 4627 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { |
| 4628 | { { OPERAND_art }, 'o' } |
| 4629 | }; |
| 4630 | |
| 4631 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { |
| 4632 | { { STATE_PSEXCM }, 'i' }, |
| 4633 | { { STATE_PSRING }, 'i' }, |
| 4634 | { { STATE_CCOMPARE1 }, 'i' } |
| 4635 | }; |
| 4636 | |
| 4637 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { |
| 4638 | { { OPERAND_art }, 'i' } |
| 4639 | }; |
| 4640 | |
| 4641 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { |
| 4642 | { { STATE_PSEXCM }, 'i' }, |
| 4643 | { { STATE_PSRING }, 'i' }, |
| 4644 | { { STATE_CCOMPARE1 }, 'o' }, |
| 4645 | { { STATE_INTERRUPT }, 'm' } |
| 4646 | }; |
| 4647 | |
| 4648 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { |
| 4649 | { { OPERAND_art }, 'm' } |
| 4650 | }; |
| 4651 | |
| 4652 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { |
| 4653 | { { STATE_PSEXCM }, 'i' }, |
| 4654 | { { STATE_PSRING }, 'i' }, |
| 4655 | { { STATE_CCOMPARE1 }, 'm' }, |
| 4656 | { { STATE_INTERRUPT }, 'm' } |
| 4657 | }; |
| 4658 | |
| 4659 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { |
| 4660 | { { OPERAND_art }, 'o' } |
| 4661 | }; |
| 4662 | |
| 4663 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { |
| 4664 | { { STATE_PSEXCM }, 'i' }, |
| 4665 | { { STATE_PSRING }, 'i' }, |
| 4666 | { { STATE_CCOMPARE2 }, 'i' } |
| 4667 | }; |
| 4668 | |
| 4669 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { |
| 4670 | { { OPERAND_art }, 'i' } |
| 4671 | }; |
| 4672 | |
| 4673 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { |
| 4674 | { { STATE_PSEXCM }, 'i' }, |
| 4675 | { { STATE_PSRING }, 'i' }, |
| 4676 | { { STATE_CCOMPARE2 }, 'o' }, |
| 4677 | { { STATE_INTERRUPT }, 'm' } |
| 4678 | }; |
| 4679 | |
| 4680 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { |
| 4681 | { { OPERAND_art }, 'm' } |
| 4682 | }; |
| 4683 | |
| 4684 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { |
| 4685 | { { STATE_PSEXCM }, 'i' }, |
| 4686 | { { STATE_PSRING }, 'i' }, |
| 4687 | { { STATE_CCOMPARE2 }, 'm' }, |
| 4688 | { { STATE_INTERRUPT }, 'm' } |
| 4689 | }; |
| 4690 | |
| 4691 | static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { |
| 4692 | { { OPERAND_ars }, 'i' }, |
| 4693 | { { OPERAND_uimm8x4 }, 'i' } |
| 4694 | }; |
| 4695 | |
| 4696 | static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { |
| 4697 | { { OPERAND_ars }, 'i' }, |
| 4698 | { { OPERAND_uimm4x16 }, 'i' } |
| 4699 | }; |
| 4700 | |
| 4701 | static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { |
| 4702 | { { STATE_PSEXCM }, 'i' }, |
| 4703 | { { STATE_PSRING }, 'i' } |
| 4704 | }; |
| 4705 | |
| 4706 | static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { |
| 4707 | { { OPERAND_ars }, 'i' }, |
| 4708 | { { OPERAND_uimm8x4 }, 'i' } |
| 4709 | }; |
| 4710 | |
| 4711 | static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { |
| 4712 | { { STATE_PSEXCM }, 'i' }, |
| 4713 | { { STATE_PSRING }, 'i' } |
| 4714 | }; |
| 4715 | |
| 4716 | static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { |
| 4717 | { { OPERAND_art }, 'o' }, |
| 4718 | { { OPERAND_ars }, 'i' } |
| 4719 | }; |
| 4720 | |
| 4721 | static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { |
| 4722 | { { STATE_PSEXCM }, 'i' }, |
| 4723 | { { STATE_PSRING }, 'i' } |
| 4724 | }; |
| 4725 | |
| 4726 | static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { |
| 4727 | { { OPERAND_art }, 'i' }, |
| 4728 | { { OPERAND_ars }, 'i' } |
| 4729 | }; |
| 4730 | |
| 4731 | static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { |
| 4732 | { { STATE_PSEXCM }, 'i' }, |
| 4733 | { { STATE_PSRING }, 'i' } |
| 4734 | }; |
| 4735 | |
| 4736 | static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { |
| 4737 | { { OPERAND_ars }, 'i' }, |
| 4738 | { { OPERAND_uimm8x4 }, 'i' } |
| 4739 | }; |
| 4740 | |
| 4741 | static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { |
| 4742 | { { OPERAND_ars }, 'i' }, |
| 4743 | { { OPERAND_uimm4x16 }, 'i' } |
| 4744 | }; |
| 4745 | |
| 4746 | static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { |
| 4747 | { { STATE_PSEXCM }, 'i' }, |
| 4748 | { { STATE_PSRING }, 'i' } |
| 4749 | }; |
| 4750 | |
| 4751 | static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { |
| 4752 | { { OPERAND_ars }, 'i' }, |
| 4753 | { { OPERAND_uimm8x4 }, 'i' } |
| 4754 | }; |
| 4755 | |
| 4756 | static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { |
| 4757 | { { STATE_PSEXCM }, 'i' }, |
| 4758 | { { STATE_PSRING }, 'i' } |
| 4759 | }; |
| 4760 | |
| 4761 | static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { |
| 4762 | { { OPERAND_ars }, 'i' }, |
| 4763 | { { OPERAND_uimm8x4 }, 'i' } |
| 4764 | }; |
| 4765 | |
| 4766 | static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { |
| 4767 | { { OPERAND_ars }, 'i' }, |
| 4768 | { { OPERAND_uimm4x16 }, 'i' } |
| 4769 | }; |
| 4770 | |
| 4771 | static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { |
| 4772 | { { STATE_PSEXCM }, 'i' }, |
| 4773 | { { STATE_PSRING }, 'i' } |
| 4774 | }; |
| 4775 | |
| 4776 | static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { |
| 4777 | { { OPERAND_art }, 'i' }, |
| 4778 | { { OPERAND_ars }, 'i' } |
| 4779 | }; |
| 4780 | |
| 4781 | static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { |
| 4782 | { { STATE_PSEXCM }, 'i' }, |
| 4783 | { { STATE_PSRING }, 'i' } |
| 4784 | }; |
| 4785 | |
| 4786 | static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { |
| 4787 | { { OPERAND_art }, 'o' }, |
| 4788 | { { OPERAND_ars }, 'i' } |
| 4789 | }; |
| 4790 | |
| 4791 | static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { |
| 4792 | { { STATE_PSEXCM }, 'i' }, |
| 4793 | { { STATE_PSRING }, 'i' } |
| 4794 | }; |
| 4795 | |
| 4796 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { |
| 4797 | { { OPERAND_art }, 'i' } |
| 4798 | }; |
| 4799 | |
| 4800 | static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { |
| 4801 | { { STATE_PSEXCM }, 'i' }, |
| 4802 | { { STATE_PSRING }, 'i' }, |
| 4803 | { { STATE_PTBASE }, 'o' }, |
| 4804 | { { STATE_XTSYNC }, 'o' } |
| 4805 | }; |
| 4806 | |
| 4807 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { |
| 4808 | { { OPERAND_art }, 'o' } |
| 4809 | }; |
| 4810 | |
| 4811 | static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { |
| 4812 | { { STATE_PSEXCM }, 'i' }, |
| 4813 | { { STATE_PSRING }, 'i' }, |
| 4814 | { { STATE_PTBASE }, 'i' }, |
| 4815 | { { STATE_EXCVADDR }, 'i' } |
| 4816 | }; |
| 4817 | |
| 4818 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { |
| 4819 | { { OPERAND_art }, 'm' } |
| 4820 | }; |
| 4821 | |
| 4822 | static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { |
| 4823 | { { STATE_PSEXCM }, 'i' }, |
| 4824 | { { STATE_PSRING }, 'i' }, |
| 4825 | { { STATE_PTBASE }, 'm' }, |
| 4826 | { { STATE_EXCVADDR }, 'i' }, |
| 4827 | { { STATE_XTSYNC }, 'o' } |
| 4828 | }; |
| 4829 | |
| 4830 | static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { |
| 4831 | { { OPERAND_art }, 'o' } |
| 4832 | }; |
| 4833 | |
| 4834 | static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { |
| 4835 | { { STATE_PSEXCM }, 'i' }, |
| 4836 | { { STATE_PSRING }, 'i' }, |
| 4837 | { { STATE_ASID3 }, 'i' }, |
| 4838 | { { STATE_ASID2 }, 'i' }, |
| 4839 | { { STATE_ASID1 }, 'i' } |
| 4840 | }; |
| 4841 | |
| 4842 | static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { |
| 4843 | { { OPERAND_art }, 'i' } |
| 4844 | }; |
| 4845 | |
| 4846 | static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { |
| 4847 | { { STATE_XTSYNC }, 'o' }, |
| 4848 | { { STATE_PSEXCM }, 'i' }, |
| 4849 | { { STATE_PSRING }, 'i' }, |
| 4850 | { { STATE_ASID3 }, 'o' }, |
| 4851 | { { STATE_ASID2 }, 'o' }, |
| 4852 | { { STATE_ASID1 }, 'o' } |
| 4853 | }; |
| 4854 | |
| 4855 | static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { |
| 4856 | { { OPERAND_art }, 'm' } |
| 4857 | }; |
| 4858 | |
| 4859 | static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { |
| 4860 | { { STATE_XTSYNC }, 'o' }, |
| 4861 | { { STATE_PSEXCM }, 'i' }, |
| 4862 | { { STATE_PSRING }, 'i' }, |
| 4863 | { { STATE_ASID3 }, 'm' }, |
| 4864 | { { STATE_ASID2 }, 'm' }, |
| 4865 | { { STATE_ASID1 }, 'm' } |
| 4866 | }; |
| 4867 | |
| 4868 | static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { |
| 4869 | { { OPERAND_art }, 'o' } |
| 4870 | }; |
| 4871 | |
| 4872 | static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { |
| 4873 | { { STATE_PSEXCM }, 'i' }, |
| 4874 | { { STATE_PSRING }, 'i' }, |
| 4875 | { { STATE_INSTPGSZID4 }, 'i' } |
| 4876 | }; |
| 4877 | |
| 4878 | static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { |
| 4879 | { { OPERAND_art }, 'i' } |
| 4880 | }; |
| 4881 | |
| 4882 | static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { |
| 4883 | { { STATE_XTSYNC }, 'o' }, |
| 4884 | { { STATE_PSEXCM }, 'i' }, |
| 4885 | { { STATE_PSRING }, 'i' }, |
| 4886 | { { STATE_INSTPGSZID4 }, 'o' } |
| 4887 | }; |
| 4888 | |
| 4889 | static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { |
| 4890 | { { OPERAND_art }, 'm' } |
| 4891 | }; |
| 4892 | |
| 4893 | static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { |
| 4894 | { { STATE_XTSYNC }, 'o' }, |
| 4895 | { { STATE_PSEXCM }, 'i' }, |
| 4896 | { { STATE_PSRING }, 'i' }, |
| 4897 | { { STATE_INSTPGSZID4 }, 'm' } |
| 4898 | }; |
| 4899 | |
| 4900 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { |
| 4901 | { { OPERAND_art }, 'o' } |
| 4902 | }; |
| 4903 | |
| 4904 | static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { |
| 4905 | { { STATE_PSEXCM }, 'i' }, |
| 4906 | { { STATE_PSRING }, 'i' }, |
| 4907 | { { STATE_DATAPGSZID4 }, 'i' } |
| 4908 | }; |
| 4909 | |
| 4910 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { |
| 4911 | { { OPERAND_art }, 'i' } |
| 4912 | }; |
| 4913 | |
| 4914 | static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { |
| 4915 | { { STATE_XTSYNC }, 'o' }, |
| 4916 | { { STATE_PSEXCM }, 'i' }, |
| 4917 | { { STATE_PSRING }, 'i' }, |
| 4918 | { { STATE_DATAPGSZID4 }, 'o' } |
| 4919 | }; |
| 4920 | |
| 4921 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { |
| 4922 | { { OPERAND_art }, 'm' } |
| 4923 | }; |
| 4924 | |
| 4925 | static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { |
| 4926 | { { STATE_XTSYNC }, 'o' }, |
| 4927 | { { STATE_PSEXCM }, 'i' }, |
| 4928 | { { STATE_PSRING }, 'i' }, |
| 4929 | { { STATE_DATAPGSZID4 }, 'm' } |
| 4930 | }; |
| 4931 | |
| 4932 | static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { |
| 4933 | { { OPERAND_ars }, 'i' } |
| 4934 | }; |
| 4935 | |
| 4936 | static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { |
| 4937 | { { STATE_PSEXCM }, 'i' }, |
| 4938 | { { STATE_PSRING }, 'i' }, |
| 4939 | { { STATE_XTSYNC }, 'o' } |
| 4940 | }; |
| 4941 | |
| 4942 | static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { |
| 4943 | { { OPERAND_art }, 'o' }, |
| 4944 | { { OPERAND_ars }, 'i' } |
| 4945 | }; |
| 4946 | |
| 4947 | static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { |
| 4948 | { { STATE_PSEXCM }, 'i' }, |
| 4949 | { { STATE_PSRING }, 'i' } |
| 4950 | }; |
| 4951 | |
| 4952 | static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { |
| 4953 | { { OPERAND_art }, 'i' }, |
| 4954 | { { OPERAND_ars }, 'i' } |
| 4955 | }; |
| 4956 | |
| 4957 | static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { |
| 4958 | { { STATE_PSEXCM }, 'i' }, |
| 4959 | { { STATE_PSRING }, 'i' }, |
| 4960 | { { STATE_XTSYNC }, 'o' } |
| 4961 | }; |
| 4962 | |
| 4963 | static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { |
| 4964 | { { OPERAND_ars }, 'i' } |
| 4965 | }; |
| 4966 | |
| 4967 | static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { |
| 4968 | { { STATE_PSEXCM }, 'i' }, |
| 4969 | { { STATE_PSRING }, 'i' } |
| 4970 | }; |
| 4971 | |
| 4972 | static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { |
| 4973 | { { OPERAND_art }, 'o' }, |
| 4974 | { { OPERAND_ars }, 'i' } |
| 4975 | }; |
| 4976 | |
| 4977 | static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { |
| 4978 | { { STATE_PSEXCM }, 'i' }, |
| 4979 | { { STATE_PSRING }, 'i' } |
| 4980 | }; |
| 4981 | |
| 4982 | static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { |
| 4983 | { { OPERAND_art }, 'i' }, |
| 4984 | { { OPERAND_ars }, 'i' } |
| 4985 | }; |
| 4986 | |
| 4987 | static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { |
| 4988 | { { STATE_PSEXCM }, 'i' }, |
| 4989 | { { STATE_PSRING }, 'i' } |
| 4990 | }; |
| 4991 | |
| 4992 | static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { |
| 4993 | { { STATE_PTBASE }, 'i' }, |
| 4994 | { { STATE_EXCVADDR }, 'i' } |
| 4995 | }; |
| 4996 | |
| 4997 | static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { |
| 4998 | { { STATE_EXCVADDR }, 'i' } |
| 4999 | }; |
| 5000 | |
| 5001 | static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { |
| 5002 | { { STATE_EXCVADDR }, 'i' } |
| 5003 | }; |
| 5004 | |
| 5005 | static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { |
| 5006 | { { OPERAND_art }, 'o' } |
| 5007 | }; |
| 5008 | |
| 5009 | static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { |
| 5010 | { { STATE_PSEXCM }, 'i' }, |
| 5011 | { { STATE_PSRING }, 'i' }, |
| 5012 | { { STATE_CPENABLE }, 'i' } |
| 5013 | }; |
| 5014 | |
| 5015 | static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { |
| 5016 | { { OPERAND_art }, 'i' } |
| 5017 | }; |
| 5018 | |
| 5019 | static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { |
| 5020 | { { STATE_PSEXCM }, 'i' }, |
| 5021 | { { STATE_PSRING }, 'i' }, |
| 5022 | { { STATE_CPENABLE }, 'o' } |
| 5023 | }; |
| 5024 | |
| 5025 | static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { |
| 5026 | { { OPERAND_art }, 'm' } |
| 5027 | }; |
| 5028 | |
| 5029 | static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { |
| 5030 | { { STATE_PSEXCM }, 'i' }, |
| 5031 | { { STATE_PSRING }, 'i' }, |
| 5032 | { { STATE_CPENABLE }, 'm' } |
| 5033 | }; |
| 5034 | |
| 5035 | static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { |
| 5036 | { { OPERAND_arr }, 'o' }, |
| 5037 | { { OPERAND_ars }, 'i' }, |
| 5038 | { { OPERAND_tp7 }, 'i' } |
| 5039 | }; |
| 5040 | |
| 5041 | static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { |
| 5042 | { { OPERAND_arr }, 'o' }, |
| 5043 | { { OPERAND_ars }, 'i' }, |
| 5044 | { { OPERAND_art }, 'i' } |
| 5045 | }; |
| 5046 | |
| 5047 | static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { |
| 5048 | { { OPERAND_art }, 'o' }, |
| 5049 | { { OPERAND_ars }, 'i' } |
| 5050 | }; |
| 5051 | |
| 5052 | static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { |
| 5053 | { { OPERAND_arr }, 'o' }, |
| 5054 | { { OPERAND_ars }, 'i' }, |
| 5055 | { { OPERAND_tp7 }, 'i' } |
| 5056 | }; |
| 5057 | |
| 5058 | static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { |
| 5059 | { { OPERAND_art }, 'o' }, |
| 5060 | { { OPERAND_ars }, 'i' }, |
| 5061 | { { OPERAND_uimm8x4 }, 'i' } |
| 5062 | }; |
| 5063 | |
| 5064 | static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { |
| 5065 | { { OPERAND_art }, 'i' }, |
| 5066 | { { OPERAND_ars }, 'i' }, |
| 5067 | { { OPERAND_uimm8x4 }, 'i' } |
| 5068 | }; |
| 5069 | |
| 5070 | static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { |
| 5071 | { { OPERAND_art }, 'm' }, |
| 5072 | { { OPERAND_ars }, 'i' }, |
| 5073 | { { OPERAND_uimm8x4 }, 'i' } |
| 5074 | }; |
| 5075 | |
| 5076 | static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { |
| 5077 | { { STATE_SCOMPARE1 }, 'i' }, |
| 5078 | { { STATE_SCOMPARE1 }, 'i' } |
| 5079 | }; |
| 5080 | |
| 5081 | static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { |
| 5082 | { { OPERAND_art }, 'o' } |
| 5083 | }; |
| 5084 | |
| 5085 | static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { |
| 5086 | { { STATE_SCOMPARE1 }, 'i' } |
| 5087 | }; |
| 5088 | |
| 5089 | static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { |
| 5090 | { { OPERAND_art }, 'i' } |
| 5091 | }; |
| 5092 | |
| 5093 | static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { |
| 5094 | { { STATE_SCOMPARE1 }, 'o' } |
| 5095 | }; |
| 5096 | |
| 5097 | static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { |
| 5098 | { { OPERAND_art }, 'm' } |
| 5099 | }; |
| 5100 | |
| 5101 | static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { |
| 5102 | { { STATE_SCOMPARE1 }, 'm' } |
| 5103 | }; |
| 5104 | |
| 5105 | static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { |
| 5106 | { { OPERAND_arr }, 'o' }, |
| 5107 | { { OPERAND_ars }, 'i' }, |
| 5108 | { { OPERAND_art }, 'i' } |
| 5109 | }; |
| 5110 | |
| 5111 | static xtensa_arg_internal Iclass_xt_mul32_args[] = { |
| 5112 | { { OPERAND_arr }, 'o' }, |
| 5113 | { { OPERAND_ars }, 'i' }, |
| 5114 | { { OPERAND_art }, 'i' } |
| 5115 | }; |
| 5116 | |
| 5117 | static xtensa_iclass_internal iclasses[] = { |
| 5118 | { 0, 0 /* xt_iclass_excw */, |
| 5119 | 0, 0, 0, 0 }, |
| 5120 | { 0, 0 /* xt_iclass_rfe */, |
| 5121 | 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, |
| 5122 | { 0, 0 /* xt_iclass_rfde */, |
| 5123 | 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, |
| 5124 | { 0, 0 /* xt_iclass_syscall */, |
| 5125 | 0, 0, 0, 0 }, |
| 5126 | { 0, 0 /* xt_iclass_simcall */, |
| 5127 | 0, 0, 0, 0 }, |
| 5128 | { 2, Iclass_xt_iclass_call12_args, |
| 5129 | 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, |
| 5130 | { 2, Iclass_xt_iclass_call8_args, |
| 5131 | 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, |
| 5132 | { 2, Iclass_xt_iclass_call4_args, |
| 5133 | 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, |
| 5134 | { 2, Iclass_xt_iclass_callx12_args, |
| 5135 | 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, |
| 5136 | { 2, Iclass_xt_iclass_callx8_args, |
| 5137 | 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, |
| 5138 | { 2, Iclass_xt_iclass_callx4_args, |
| 5139 | 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, |
| 5140 | { 3, Iclass_xt_iclass_entry_args, |
| 5141 | 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, |
| 5142 | { 2, Iclass_xt_iclass_movsp_args, |
| 5143 | 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, |
| 5144 | { 1, Iclass_xt_iclass_rotw_args, |
| 5145 | 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, |
| 5146 | { 1, Iclass_xt_iclass_retw_args, |
| 5147 | 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, |
| 5148 | { 0, 0 /* xt_iclass_rfwou */, |
| 5149 | 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, |
| 5150 | { 3, Iclass_xt_iclass_l32e_args, |
| 5151 | 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, |
| 5152 | { 3, Iclass_xt_iclass_s32e_args, |
| 5153 | 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, |
| 5154 | { 1, Iclass_xt_iclass_rsr_windowbase_args, |
| 5155 | 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, |
| 5156 | { 1, Iclass_xt_iclass_wsr_windowbase_args, |
| 5157 | 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, |
| 5158 | { 1, Iclass_xt_iclass_xsr_windowbase_args, |
| 5159 | 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, |
| 5160 | { 1, Iclass_xt_iclass_rsr_windowstart_args, |
| 5161 | 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, |
| 5162 | { 1, Iclass_xt_iclass_wsr_windowstart_args, |
| 5163 | 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, |
| 5164 | { 1, Iclass_xt_iclass_xsr_windowstart_args, |
| 5165 | 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, |
| 5166 | { 3, Iclass_xt_iclass_add_n_args, |
| 5167 | 0, 0, 0, 0 }, |
| 5168 | { 3, Iclass_xt_iclass_addi_n_args, |
| 5169 | 0, 0, 0, 0 }, |
| 5170 | { 2, Iclass_xt_iclass_bz6_args, |
| 5171 | 0, 0, 0, 0 }, |
| 5172 | { 0, 0 /* xt_iclass_ill_n */, |
| 5173 | 0, 0, 0, 0 }, |
| 5174 | { 3, Iclass_xt_iclass_loadi4_args, |
| 5175 | 0, 0, 0, 0 }, |
| 5176 | { 2, Iclass_xt_iclass_mov_n_args, |
| 5177 | 0, 0, 0, 0 }, |
| 5178 | { 2, Iclass_xt_iclass_movi_n_args, |
| 5179 | 0, 0, 0, 0 }, |
| 5180 | { 0, 0 /* xt_iclass_nopn */, |
| 5181 | 0, 0, 0, 0 }, |
| 5182 | { 1, Iclass_xt_iclass_retn_args, |
| 5183 | 0, 0, 0, 0 }, |
| 5184 | { 3, Iclass_xt_iclass_storei4_args, |
| 5185 | 0, 0, 0, 0 }, |
| 5186 | { 1, Iclass_rur_threadptr_args, |
| 5187 | 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, |
| 5188 | { 1, Iclass_wur_threadptr_args, |
| 5189 | 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, |
| 5190 | { 3, Iclass_xt_iclass_addi_args, |
| 5191 | 0, 0, 0, 0 }, |
| 5192 | { 3, Iclass_xt_iclass_addmi_args, |
| 5193 | 0, 0, 0, 0 }, |
| 5194 | { 3, Iclass_xt_iclass_addsub_args, |
| 5195 | 0, 0, 0, 0 }, |
| 5196 | { 3, Iclass_xt_iclass_bit_args, |
| 5197 | 0, 0, 0, 0 }, |
| 5198 | { 3, Iclass_xt_iclass_bsi8_args, |
| 5199 | 0, 0, 0, 0 }, |
| 5200 | { 3, Iclass_xt_iclass_bsi8b_args, |
| 5201 | 0, 0, 0, 0 }, |
| 5202 | { 3, Iclass_xt_iclass_bsi8u_args, |
| 5203 | 0, 0, 0, 0 }, |
| 5204 | { 3, Iclass_xt_iclass_bst8_args, |
| 5205 | 0, 0, 0, 0 }, |
| 5206 | { 2, Iclass_xt_iclass_bsz12_args, |
| 5207 | 0, 0, 0, 0 }, |
| 5208 | { 2, Iclass_xt_iclass_call0_args, |
| 5209 | 0, 0, 0, 0 }, |
| 5210 | { 2, Iclass_xt_iclass_callx0_args, |
| 5211 | 0, 0, 0, 0 }, |
| 5212 | { 4, Iclass_xt_iclass_exti_args, |
| 5213 | 0, 0, 0, 0 }, |
| 5214 | { 0, 0 /* xt_iclass_ill */, |
| 5215 | 0, 0, 0, 0 }, |
| 5216 | { 1, Iclass_xt_iclass_jump_args, |
| 5217 | 0, 0, 0, 0 }, |
| 5218 | { 1, Iclass_xt_iclass_jumpx_args, |
| 5219 | 0, 0, 0, 0 }, |
| 5220 | { 3, Iclass_xt_iclass_l16ui_args, |
| 5221 | 0, 0, 0, 0 }, |
| 5222 | { 3, Iclass_xt_iclass_l16si_args, |
| 5223 | 0, 0, 0, 0 }, |
| 5224 | { 3, Iclass_xt_iclass_l32i_args, |
| 5225 | 0, 0, 0, 0 }, |
| 5226 | { 2, Iclass_xt_iclass_l32r_args, |
| 5227 | 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, |
| 5228 | { 3, Iclass_xt_iclass_l8i_args, |
| 5229 | 0, 0, 0, 0 }, |
| 5230 | { 2, Iclass_xt_iclass_loop_args, |
| 5231 | 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, |
| 5232 | { 2, Iclass_xt_iclass_loopz_args, |
| 5233 | 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, |
| 5234 | { 2, Iclass_xt_iclass_movi_args, |
| 5235 | 0, 0, 0, 0 }, |
| 5236 | { 3, Iclass_xt_iclass_movz_args, |
| 5237 | 0, 0, 0, 0 }, |
| 5238 | { 2, Iclass_xt_iclass_neg_args, |
| 5239 | 0, 0, 0, 0 }, |
| 5240 | { 0, 0 /* xt_iclass_nop */, |
| 5241 | 0, 0, 0, 0 }, |
| 5242 | { 1, Iclass_xt_iclass_return_args, |
| 5243 | 0, 0, 0, 0 }, |
| 5244 | { 3, Iclass_xt_iclass_s16i_args, |
| 5245 | 0, 0, 0, 0 }, |
| 5246 | { 3, Iclass_xt_iclass_s32i_args, |
| 5247 | 0, 0, 0, 0 }, |
| 5248 | { 3, Iclass_xt_iclass_s8i_args, |
| 5249 | 0, 0, 0, 0 }, |
| 5250 | { 1, Iclass_xt_iclass_sar_args, |
| 5251 | 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, |
| 5252 | { 1, Iclass_xt_iclass_sari_args, |
| 5253 | 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, |
| 5254 | { 2, Iclass_xt_iclass_shifts_args, |
| 5255 | 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, |
| 5256 | { 3, Iclass_xt_iclass_shiftst_args, |
| 5257 | 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, |
| 5258 | { 2, Iclass_xt_iclass_shiftt_args, |
| 5259 | 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, |
| 5260 | { 3, Iclass_xt_iclass_slli_args, |
| 5261 | 0, 0, 0, 0 }, |
| 5262 | { 3, Iclass_xt_iclass_srai_args, |
| 5263 | 0, 0, 0, 0 }, |
| 5264 | { 3, Iclass_xt_iclass_srli_args, |
| 5265 | 0, 0, 0, 0 }, |
| 5266 | { 0, 0 /* xt_iclass_memw */, |
| 5267 | 0, 0, 0, 0 }, |
| 5268 | { 0, 0 /* xt_iclass_extw */, |
| 5269 | 0, 0, 0, 0 }, |
| 5270 | { 0, 0 /* xt_iclass_isync */, |
| 5271 | 0, 0, 0, 0 }, |
| 5272 | { 0, 0 /* xt_iclass_sync */, |
| 5273 | 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, |
| 5274 | { 2, Iclass_xt_iclass_rsil_args, |
| 5275 | 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, |
| 5276 | { 1, Iclass_xt_iclass_rsr_lend_args, |
| 5277 | 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, |
| 5278 | { 1, Iclass_xt_iclass_wsr_lend_args, |
| 5279 | 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, |
| 5280 | { 1, Iclass_xt_iclass_xsr_lend_args, |
| 5281 | 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, |
| 5282 | { 1, Iclass_xt_iclass_rsr_lcount_args, |
| 5283 | 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, |
| 5284 | { 1, Iclass_xt_iclass_wsr_lcount_args, |
| 5285 | 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, |
| 5286 | { 1, Iclass_xt_iclass_xsr_lcount_args, |
| 5287 | 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, |
| 5288 | { 1, Iclass_xt_iclass_rsr_lbeg_args, |
| 5289 | 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, |
| 5290 | { 1, Iclass_xt_iclass_wsr_lbeg_args, |
| 5291 | 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, |
| 5292 | { 1, Iclass_xt_iclass_xsr_lbeg_args, |
| 5293 | 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, |
| 5294 | { 1, Iclass_xt_iclass_rsr_sar_args, |
| 5295 | 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, |
| 5296 | { 1, Iclass_xt_iclass_wsr_sar_args, |
| 5297 | 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, |
| 5298 | { 1, Iclass_xt_iclass_xsr_sar_args, |
| 5299 | 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, |
| 5300 | { 1, Iclass_xt_iclass_rsr_litbase_args, |
| 5301 | 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, |
| 5302 | { 1, Iclass_xt_iclass_wsr_litbase_args, |
| 5303 | 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, |
| 5304 | { 1, Iclass_xt_iclass_xsr_litbase_args, |
| 5305 | 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, |
| 5306 | { 1, Iclass_xt_iclass_rsr_176_args, |
| 5307 | 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, |
| 5308 | { 1, Iclass_xt_iclass_wsr_176_args, |
| 5309 | 2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 }, |
| 5310 | { 1, Iclass_xt_iclass_rsr_208_args, |
| 5311 | 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, |
| 5312 | { 1, Iclass_xt_iclass_rsr_ps_args, |
| 5313 | 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, |
| 5314 | { 1, Iclass_xt_iclass_wsr_ps_args, |
| 5315 | 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, |
| 5316 | { 1, Iclass_xt_iclass_xsr_ps_args, |
| 5317 | 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, |
| 5318 | { 1, Iclass_xt_iclass_rsr_epc1_args, |
| 5319 | 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, |
| 5320 | { 1, Iclass_xt_iclass_wsr_epc1_args, |
| 5321 | 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, |
| 5322 | { 1, Iclass_xt_iclass_xsr_epc1_args, |
| 5323 | 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, |
| 5324 | { 1, Iclass_xt_iclass_rsr_excsave1_args, |
| 5325 | 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, |
| 5326 | { 1, Iclass_xt_iclass_wsr_excsave1_args, |
| 5327 | 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, |
| 5328 | { 1, Iclass_xt_iclass_xsr_excsave1_args, |
| 5329 | 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, |
| 5330 | { 1, Iclass_xt_iclass_rsr_epc2_args, |
| 5331 | 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, |
| 5332 | { 1, Iclass_xt_iclass_wsr_epc2_args, |
| 5333 | 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, |
| 5334 | { 1, Iclass_xt_iclass_xsr_epc2_args, |
| 5335 | 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, |
| 5336 | { 1, Iclass_xt_iclass_rsr_excsave2_args, |
| 5337 | 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, |
| 5338 | { 1, Iclass_xt_iclass_wsr_excsave2_args, |
| 5339 | 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, |
| 5340 | { 1, Iclass_xt_iclass_xsr_excsave2_args, |
| 5341 | 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, |
| 5342 | { 1, Iclass_xt_iclass_rsr_epc3_args, |
| 5343 | 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, |
| 5344 | { 1, Iclass_xt_iclass_wsr_epc3_args, |
| 5345 | 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, |
| 5346 | { 1, Iclass_xt_iclass_xsr_epc3_args, |
| 5347 | 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, |
| 5348 | { 1, Iclass_xt_iclass_rsr_excsave3_args, |
| 5349 | 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, |
| 5350 | { 1, Iclass_xt_iclass_wsr_excsave3_args, |
| 5351 | 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, |
| 5352 | { 1, Iclass_xt_iclass_xsr_excsave3_args, |
| 5353 | 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, |
| 5354 | { 1, Iclass_xt_iclass_rsr_epc4_args, |
| 5355 | 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, |
| 5356 | { 1, Iclass_xt_iclass_wsr_epc4_args, |
| 5357 | 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, |
| 5358 | { 1, Iclass_xt_iclass_xsr_epc4_args, |
| 5359 | 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, |
| 5360 | { 1, Iclass_xt_iclass_rsr_excsave4_args, |
| 5361 | 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, |
| 5362 | { 1, Iclass_xt_iclass_wsr_excsave4_args, |
| 5363 | 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, |
| 5364 | { 1, Iclass_xt_iclass_xsr_excsave4_args, |
| 5365 | 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, |
| 5366 | { 1, Iclass_xt_iclass_rsr_epc5_args, |
| 5367 | 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, |
| 5368 | { 1, Iclass_xt_iclass_wsr_epc5_args, |
| 5369 | 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, |
| 5370 | { 1, Iclass_xt_iclass_xsr_epc5_args, |
| 5371 | 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, |
| 5372 | { 1, Iclass_xt_iclass_rsr_excsave5_args, |
| 5373 | 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, |
| 5374 | { 1, Iclass_xt_iclass_wsr_excsave5_args, |
| 5375 | 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, |
| 5376 | { 1, Iclass_xt_iclass_xsr_excsave5_args, |
| 5377 | 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, |
| 5378 | { 1, Iclass_xt_iclass_rsr_epc6_args, |
| 5379 | 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, |
| 5380 | { 1, Iclass_xt_iclass_wsr_epc6_args, |
| 5381 | 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, |
| 5382 | { 1, Iclass_xt_iclass_xsr_epc6_args, |
| 5383 | 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, |
| 5384 | { 1, Iclass_xt_iclass_rsr_excsave6_args, |
| 5385 | 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, |
| 5386 | { 1, Iclass_xt_iclass_wsr_excsave6_args, |
| 5387 | 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, |
| 5388 | { 1, Iclass_xt_iclass_xsr_excsave6_args, |
| 5389 | 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, |
| 5390 | { 1, Iclass_xt_iclass_rsr_epc7_args, |
| 5391 | 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, |
| 5392 | { 1, Iclass_xt_iclass_wsr_epc7_args, |
| 5393 | 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, |
| 5394 | { 1, Iclass_xt_iclass_xsr_epc7_args, |
| 5395 | 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, |
| 5396 | { 1, Iclass_xt_iclass_rsr_excsave7_args, |
| 5397 | 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, |
| 5398 | { 1, Iclass_xt_iclass_wsr_excsave7_args, |
| 5399 | 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, |
| 5400 | { 1, Iclass_xt_iclass_xsr_excsave7_args, |
| 5401 | 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, |
| 5402 | { 1, Iclass_xt_iclass_rsr_eps2_args, |
| 5403 | 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, |
| 5404 | { 1, Iclass_xt_iclass_wsr_eps2_args, |
| 5405 | 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, |
| 5406 | { 1, Iclass_xt_iclass_xsr_eps2_args, |
| 5407 | 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, |
| 5408 | { 1, Iclass_xt_iclass_rsr_eps3_args, |
| 5409 | 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, |
| 5410 | { 1, Iclass_xt_iclass_wsr_eps3_args, |
| 5411 | 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, |
| 5412 | { 1, Iclass_xt_iclass_xsr_eps3_args, |
| 5413 | 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, |
| 5414 | { 1, Iclass_xt_iclass_rsr_eps4_args, |
| 5415 | 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, |
| 5416 | { 1, Iclass_xt_iclass_wsr_eps4_args, |
| 5417 | 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, |
| 5418 | { 1, Iclass_xt_iclass_xsr_eps4_args, |
| 5419 | 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, |
| 5420 | { 1, Iclass_xt_iclass_rsr_eps5_args, |
| 5421 | 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, |
| 5422 | { 1, Iclass_xt_iclass_wsr_eps5_args, |
| 5423 | 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, |
| 5424 | { 1, Iclass_xt_iclass_xsr_eps5_args, |
| 5425 | 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, |
| 5426 | { 1, Iclass_xt_iclass_rsr_eps6_args, |
| 5427 | 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, |
| 5428 | { 1, Iclass_xt_iclass_wsr_eps6_args, |
| 5429 | 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, |
| 5430 | { 1, Iclass_xt_iclass_xsr_eps6_args, |
| 5431 | 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, |
| 5432 | { 1, Iclass_xt_iclass_rsr_eps7_args, |
| 5433 | 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, |
| 5434 | { 1, Iclass_xt_iclass_wsr_eps7_args, |
| 5435 | 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, |
| 5436 | { 1, Iclass_xt_iclass_xsr_eps7_args, |
| 5437 | 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, |
| 5438 | { 1, Iclass_xt_iclass_rsr_excvaddr_args, |
| 5439 | 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, |
| 5440 | { 1, Iclass_xt_iclass_wsr_excvaddr_args, |
| 5441 | 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, |
| 5442 | { 1, Iclass_xt_iclass_xsr_excvaddr_args, |
| 5443 | 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, |
| 5444 | { 1, Iclass_xt_iclass_rsr_depc_args, |
| 5445 | 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, |
| 5446 | { 1, Iclass_xt_iclass_wsr_depc_args, |
| 5447 | 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, |
| 5448 | { 1, Iclass_xt_iclass_xsr_depc_args, |
| 5449 | 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, |
| 5450 | { 1, Iclass_xt_iclass_rsr_exccause_args, |
| 5451 | 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, |
| 5452 | { 1, Iclass_xt_iclass_wsr_exccause_args, |
| 5453 | 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, |
| 5454 | { 1, Iclass_xt_iclass_xsr_exccause_args, |
| 5455 | 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, |
| 5456 | { 1, Iclass_xt_iclass_rsr_misc0_args, |
| 5457 | 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, |
| 5458 | { 1, Iclass_xt_iclass_wsr_misc0_args, |
| 5459 | 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, |
| 5460 | { 1, Iclass_xt_iclass_xsr_misc0_args, |
| 5461 | 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, |
| 5462 | { 1, Iclass_xt_iclass_rsr_misc1_args, |
| 5463 | 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, |
| 5464 | { 1, Iclass_xt_iclass_wsr_misc1_args, |
| 5465 | 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, |
| 5466 | { 1, Iclass_xt_iclass_xsr_misc1_args, |
| 5467 | 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, |
| 5468 | { 1, Iclass_xt_iclass_rsr_prid_args, |
| 5469 | 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, |
| 5470 | { 1, Iclass_xt_iclass_rsr_vecbase_args, |
| 5471 | 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, |
| 5472 | { 1, Iclass_xt_iclass_wsr_vecbase_args, |
| 5473 | 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, |
| 5474 | { 1, Iclass_xt_iclass_xsr_vecbase_args, |
| 5475 | 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, |
| 5476 | { 3, Iclass_xt_iclass_mul16_args, |
| 5477 | 0, 0, 0, 0 }, |
| 5478 | { 1, Iclass_xt_iclass_rfi_args, |
| 5479 | 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, |
| 5480 | { 1, Iclass_xt_iclass_wait_args, |
| 5481 | 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, |
| 5482 | { 1, Iclass_xt_iclass_rsr_interrupt_args, |
| 5483 | 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, |
| 5484 | { 1, Iclass_xt_iclass_wsr_intset_args, |
| 5485 | 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, |
| 5486 | { 1, Iclass_xt_iclass_wsr_intclear_args, |
| 5487 | 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, |
| 5488 | { 1, Iclass_xt_iclass_rsr_intenable_args, |
| 5489 | 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, |
| 5490 | { 1, Iclass_xt_iclass_wsr_intenable_args, |
| 5491 | 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, |
| 5492 | { 1, Iclass_xt_iclass_xsr_intenable_args, |
| 5493 | 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, |
| 5494 | { 2, Iclass_xt_iclass_break_args, |
| 5495 | 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, |
| 5496 | { 1, Iclass_xt_iclass_break_n_args, |
| 5497 | 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, |
| 5498 | { 1, Iclass_xt_iclass_rsr_dbreaka0_args, |
| 5499 | 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, |
| 5500 | { 1, Iclass_xt_iclass_wsr_dbreaka0_args, |
| 5501 | 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, |
| 5502 | { 1, Iclass_xt_iclass_xsr_dbreaka0_args, |
| 5503 | 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, |
| 5504 | { 1, Iclass_xt_iclass_rsr_dbreakc0_args, |
| 5505 | 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, |
| 5506 | { 1, Iclass_xt_iclass_wsr_dbreakc0_args, |
| 5507 | 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, |
| 5508 | { 1, Iclass_xt_iclass_xsr_dbreakc0_args, |
| 5509 | 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, |
| 5510 | { 1, Iclass_xt_iclass_rsr_dbreaka1_args, |
| 5511 | 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, |
| 5512 | { 1, Iclass_xt_iclass_wsr_dbreaka1_args, |
| 5513 | 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, |
| 5514 | { 1, Iclass_xt_iclass_xsr_dbreaka1_args, |
| 5515 | 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, |
| 5516 | { 1, Iclass_xt_iclass_rsr_dbreakc1_args, |
| 5517 | 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, |
| 5518 | { 1, Iclass_xt_iclass_wsr_dbreakc1_args, |
| 5519 | 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, |
| 5520 | { 1, Iclass_xt_iclass_xsr_dbreakc1_args, |
| 5521 | 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, |
| 5522 | { 1, Iclass_xt_iclass_rsr_ibreaka0_args, |
| 5523 | 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, |
| 5524 | { 1, Iclass_xt_iclass_wsr_ibreaka0_args, |
| 5525 | 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, |
| 5526 | { 1, Iclass_xt_iclass_xsr_ibreaka0_args, |
| 5527 | 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, |
| 5528 | { 1, Iclass_xt_iclass_rsr_ibreaka1_args, |
| 5529 | 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, |
| 5530 | { 1, Iclass_xt_iclass_wsr_ibreaka1_args, |
| 5531 | 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, |
| 5532 | { 1, Iclass_xt_iclass_xsr_ibreaka1_args, |
| 5533 | 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, |
| 5534 | { 1, Iclass_xt_iclass_rsr_ibreakenable_args, |
| 5535 | 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, |
| 5536 | { 1, Iclass_xt_iclass_wsr_ibreakenable_args, |
| 5537 | 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, |
| 5538 | { 1, Iclass_xt_iclass_xsr_ibreakenable_args, |
| 5539 | 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, |
| 5540 | { 1, Iclass_xt_iclass_rsr_debugcause_args, |
| 5541 | 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, |
| 5542 | { 1, Iclass_xt_iclass_wsr_debugcause_args, |
| 5543 | 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, |
| 5544 | { 1, Iclass_xt_iclass_xsr_debugcause_args, |
| 5545 | 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, |
| 5546 | { 1, Iclass_xt_iclass_rsr_icount_args, |
| 5547 | 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, |
| 5548 | { 1, Iclass_xt_iclass_wsr_icount_args, |
| 5549 | 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, |
| 5550 | { 1, Iclass_xt_iclass_xsr_icount_args, |
| 5551 | 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, |
| 5552 | { 1, Iclass_xt_iclass_rsr_icountlevel_args, |
| 5553 | 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, |
| 5554 | { 1, Iclass_xt_iclass_wsr_icountlevel_args, |
| 5555 | 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, |
| 5556 | { 1, Iclass_xt_iclass_xsr_icountlevel_args, |
| 5557 | 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, |
| 5558 | { 1, Iclass_xt_iclass_rsr_ddr_args, |
| 5559 | 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, |
| 5560 | { 1, Iclass_xt_iclass_wsr_ddr_args, |
| 5561 | 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, |
| 5562 | { 1, Iclass_xt_iclass_xsr_ddr_args, |
| 5563 | 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, |
| 5564 | { 1, Iclass_xt_iclass_rfdo_args, |
| 5565 | 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, |
| 5566 | { 0, 0 /* xt_iclass_rfdd */, |
| 5567 | 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, |
| 5568 | { 1, Iclass_xt_iclass_wsr_mmid_args, |
| 5569 | 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, |
| 5570 | { 1, Iclass_xt_iclass_rsr_ccount_args, |
| 5571 | 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, |
| 5572 | { 1, Iclass_xt_iclass_wsr_ccount_args, |
| 5573 | 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, |
| 5574 | { 1, Iclass_xt_iclass_xsr_ccount_args, |
| 5575 | 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, |
| 5576 | { 1, Iclass_xt_iclass_rsr_ccompare0_args, |
| 5577 | 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, |
| 5578 | { 1, Iclass_xt_iclass_wsr_ccompare0_args, |
| 5579 | 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, |
| 5580 | { 1, Iclass_xt_iclass_xsr_ccompare0_args, |
| 5581 | 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, |
| 5582 | { 1, Iclass_xt_iclass_rsr_ccompare1_args, |
| 5583 | 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, |
| 5584 | { 1, Iclass_xt_iclass_wsr_ccompare1_args, |
| 5585 | 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, |
| 5586 | { 1, Iclass_xt_iclass_xsr_ccompare1_args, |
| 5587 | 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, |
| 5588 | { 1, Iclass_xt_iclass_rsr_ccompare2_args, |
| 5589 | 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, |
| 5590 | { 1, Iclass_xt_iclass_wsr_ccompare2_args, |
| 5591 | 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, |
| 5592 | { 1, Iclass_xt_iclass_xsr_ccompare2_args, |
| 5593 | 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, |
| 5594 | { 2, Iclass_xt_iclass_icache_args, |
| 5595 | 0, 0, 0, 0 }, |
| 5596 | { 2, Iclass_xt_iclass_icache_lock_args, |
| 5597 | 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, |
| 5598 | { 2, Iclass_xt_iclass_icache_inv_args, |
| 5599 | 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, |
| 5600 | { 2, Iclass_xt_iclass_licx_args, |
| 5601 | 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, |
| 5602 | { 2, Iclass_xt_iclass_sicx_args, |
| 5603 | 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, |
| 5604 | { 2, Iclass_xt_iclass_dcache_args, |
| 5605 | 0, 0, 0, 0 }, |
| 5606 | { 2, Iclass_xt_iclass_dcache_ind_args, |
| 5607 | 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, |
| 5608 | { 2, Iclass_xt_iclass_dcache_inv_args, |
| 5609 | 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, |
| 5610 | { 2, Iclass_xt_iclass_dpf_args, |
| 5611 | 0, 0, 0, 0 }, |
| 5612 | { 2, Iclass_xt_iclass_dcache_lock_args, |
| 5613 | 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, |
| 5614 | { 2, Iclass_xt_iclass_sdct_args, |
| 5615 | 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, |
| 5616 | { 2, Iclass_xt_iclass_ldct_args, |
| 5617 | 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, |
| 5618 | { 1, Iclass_xt_iclass_wsr_ptevaddr_args, |
| 5619 | 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, |
| 5620 | { 1, Iclass_xt_iclass_rsr_ptevaddr_args, |
| 5621 | 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, |
| 5622 | { 1, Iclass_xt_iclass_xsr_ptevaddr_args, |
| 5623 | 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, |
| 5624 | { 1, Iclass_xt_iclass_rsr_rasid_args, |
| 5625 | 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, |
| 5626 | { 1, Iclass_xt_iclass_wsr_rasid_args, |
| 5627 | 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, |
| 5628 | { 1, Iclass_xt_iclass_xsr_rasid_args, |
| 5629 | 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, |
| 5630 | { 1, Iclass_xt_iclass_rsr_itlbcfg_args, |
| 5631 | 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, |
| 5632 | { 1, Iclass_xt_iclass_wsr_itlbcfg_args, |
| 5633 | 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, |
| 5634 | { 1, Iclass_xt_iclass_xsr_itlbcfg_args, |
| 5635 | 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, |
| 5636 | { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, |
| 5637 | 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, |
| 5638 | { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, |
| 5639 | 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, |
| 5640 | { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, |
| 5641 | 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, |
| 5642 | { 1, Iclass_xt_iclass_idtlb_args, |
| 5643 | 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, |
| 5644 | { 2, Iclass_xt_iclass_rdtlb_args, |
| 5645 | 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, |
| 5646 | { 2, Iclass_xt_iclass_wdtlb_args, |
| 5647 | 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, |
| 5648 | { 1, Iclass_xt_iclass_iitlb_args, |
| 5649 | 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, |
| 5650 | { 2, Iclass_xt_iclass_ritlb_args, |
| 5651 | 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, |
| 5652 | { 2, Iclass_xt_iclass_witlb_args, |
| 5653 | 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, |
| 5654 | { 0, 0 /* xt_iclass_ldpte */, |
| 5655 | 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, |
| 5656 | { 0, 0 /* xt_iclass_hwwitlba */, |
| 5657 | 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, |
| 5658 | { 0, 0 /* xt_iclass_hwwdtlba */, |
| 5659 | 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, |
| 5660 | { 1, Iclass_xt_iclass_rsr_cpenable_args, |
| 5661 | 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, |
| 5662 | { 1, Iclass_xt_iclass_wsr_cpenable_args, |
| 5663 | 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, |
| 5664 | { 1, Iclass_xt_iclass_xsr_cpenable_args, |
| 5665 | 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, |
| 5666 | { 3, Iclass_xt_iclass_clamp_args, |
| 5667 | 0, 0, 0, 0 }, |
| 5668 | { 3, Iclass_xt_iclass_minmax_args, |
| 5669 | 0, 0, 0, 0 }, |
| 5670 | { 2, Iclass_xt_iclass_nsa_args, |
| 5671 | 0, 0, 0, 0 }, |
| 5672 | { 3, Iclass_xt_iclass_sx_args, |
| 5673 | 0, 0, 0, 0 }, |
| 5674 | { 3, Iclass_xt_iclass_l32ai_args, |
| 5675 | 0, 0, 0, 0 }, |
| 5676 | { 3, Iclass_xt_iclass_s32ri_args, |
| 5677 | 0, 0, 0, 0 }, |
| 5678 | { 3, Iclass_xt_iclass_s32c1i_args, |
| 5679 | 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, |
| 5680 | { 1, Iclass_xt_iclass_rsr_scompare1_args, |
| 5681 | 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, |
| 5682 | { 1, Iclass_xt_iclass_wsr_scompare1_args, |
| 5683 | 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, |
| 5684 | { 1, Iclass_xt_iclass_xsr_scompare1_args, |
| 5685 | 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, |
| 5686 | { 3, Iclass_xt_iclass_div_args, |
| 5687 | 0, 0, 0, 0 }, |
| 5688 | { 3, Iclass_xt_mul32_args, |
| 5689 | 0, 0, 0, 0 } |
| 5690 | }; |
| 5691 | |
| 5692 | enum xtensa_iclass_id { |
| 5693 | ICLASS_xt_iclass_excw, |
| 5694 | ICLASS_xt_iclass_rfe, |
| 5695 | ICLASS_xt_iclass_rfde, |
| 5696 | ICLASS_xt_iclass_syscall, |
| 5697 | ICLASS_xt_iclass_simcall, |
| 5698 | ICLASS_xt_iclass_call12, |
| 5699 | ICLASS_xt_iclass_call8, |
| 5700 | ICLASS_xt_iclass_call4, |
| 5701 | ICLASS_xt_iclass_callx12, |
| 5702 | ICLASS_xt_iclass_callx8, |
| 5703 | ICLASS_xt_iclass_callx4, |
| 5704 | ICLASS_xt_iclass_entry, |
| 5705 | ICLASS_xt_iclass_movsp, |
| 5706 | ICLASS_xt_iclass_rotw, |
| 5707 | ICLASS_xt_iclass_retw, |
| 5708 | ICLASS_xt_iclass_rfwou, |
| 5709 | ICLASS_xt_iclass_l32e, |
| 5710 | ICLASS_xt_iclass_s32e, |
| 5711 | ICLASS_xt_iclass_rsr_windowbase, |
| 5712 | ICLASS_xt_iclass_wsr_windowbase, |
| 5713 | ICLASS_xt_iclass_xsr_windowbase, |
| 5714 | ICLASS_xt_iclass_rsr_windowstart, |
| 5715 | ICLASS_xt_iclass_wsr_windowstart, |
| 5716 | ICLASS_xt_iclass_xsr_windowstart, |
| 5717 | ICLASS_xt_iclass_add_n, |
| 5718 | ICLASS_xt_iclass_addi_n, |
| 5719 | ICLASS_xt_iclass_bz6, |
| 5720 | ICLASS_xt_iclass_ill_n, |
| 5721 | ICLASS_xt_iclass_loadi4, |
| 5722 | ICLASS_xt_iclass_mov_n, |
| 5723 | ICLASS_xt_iclass_movi_n, |
| 5724 | ICLASS_xt_iclass_nopn, |
| 5725 | ICLASS_xt_iclass_retn, |
| 5726 | ICLASS_xt_iclass_storei4, |
| 5727 | ICLASS_rur_threadptr, |
| 5728 | ICLASS_wur_threadptr, |
| 5729 | ICLASS_xt_iclass_addi, |
| 5730 | ICLASS_xt_iclass_addmi, |
| 5731 | ICLASS_xt_iclass_addsub, |
| 5732 | ICLASS_xt_iclass_bit, |
| 5733 | ICLASS_xt_iclass_bsi8, |
| 5734 | ICLASS_xt_iclass_bsi8b, |
| 5735 | ICLASS_xt_iclass_bsi8u, |
| 5736 | ICLASS_xt_iclass_bst8, |
| 5737 | ICLASS_xt_iclass_bsz12, |
| 5738 | ICLASS_xt_iclass_call0, |
| 5739 | ICLASS_xt_iclass_callx0, |
| 5740 | ICLASS_xt_iclass_exti, |
| 5741 | ICLASS_xt_iclass_ill, |
| 5742 | ICLASS_xt_iclass_jump, |
| 5743 | ICLASS_xt_iclass_jumpx, |
| 5744 | ICLASS_xt_iclass_l16ui, |
| 5745 | ICLASS_xt_iclass_l16si, |
| 5746 | ICLASS_xt_iclass_l32i, |
| 5747 | ICLASS_xt_iclass_l32r, |
| 5748 | ICLASS_xt_iclass_l8i, |
| 5749 | ICLASS_xt_iclass_loop, |
| 5750 | ICLASS_xt_iclass_loopz, |
| 5751 | ICLASS_xt_iclass_movi, |
| 5752 | ICLASS_xt_iclass_movz, |
| 5753 | ICLASS_xt_iclass_neg, |
| 5754 | ICLASS_xt_iclass_nop, |
| 5755 | ICLASS_xt_iclass_return, |
| 5756 | ICLASS_xt_iclass_s16i, |
| 5757 | ICLASS_xt_iclass_s32i, |
| 5758 | ICLASS_xt_iclass_s8i, |
| 5759 | ICLASS_xt_iclass_sar, |
| 5760 | ICLASS_xt_iclass_sari, |
| 5761 | ICLASS_xt_iclass_shifts, |
| 5762 | ICLASS_xt_iclass_shiftst, |
| 5763 | ICLASS_xt_iclass_shiftt, |
| 5764 | ICLASS_xt_iclass_slli, |
| 5765 | ICLASS_xt_iclass_srai, |
| 5766 | ICLASS_xt_iclass_srli, |
| 5767 | ICLASS_xt_iclass_memw, |
| 5768 | ICLASS_xt_iclass_extw, |
| 5769 | ICLASS_xt_iclass_isync, |
| 5770 | ICLASS_xt_iclass_sync, |
| 5771 | ICLASS_xt_iclass_rsil, |
| 5772 | ICLASS_xt_iclass_rsr_lend, |
| 5773 | ICLASS_xt_iclass_wsr_lend, |
| 5774 | ICLASS_xt_iclass_xsr_lend, |
| 5775 | ICLASS_xt_iclass_rsr_lcount, |
| 5776 | ICLASS_xt_iclass_wsr_lcount, |
| 5777 | ICLASS_xt_iclass_xsr_lcount, |
| 5778 | ICLASS_xt_iclass_rsr_lbeg, |
| 5779 | ICLASS_xt_iclass_wsr_lbeg, |
| 5780 | ICLASS_xt_iclass_xsr_lbeg, |
| 5781 | ICLASS_xt_iclass_rsr_sar, |
| 5782 | ICLASS_xt_iclass_wsr_sar, |
| 5783 | ICLASS_xt_iclass_xsr_sar, |
| 5784 | ICLASS_xt_iclass_rsr_litbase, |
| 5785 | ICLASS_xt_iclass_wsr_litbase, |
| 5786 | ICLASS_xt_iclass_xsr_litbase, |
| 5787 | ICLASS_xt_iclass_rsr_176, |
| 5788 | ICLASS_xt_iclass_wsr_176, |
| 5789 | ICLASS_xt_iclass_rsr_208, |
| 5790 | ICLASS_xt_iclass_rsr_ps, |
| 5791 | ICLASS_xt_iclass_wsr_ps, |
| 5792 | ICLASS_xt_iclass_xsr_ps, |
| 5793 | ICLASS_xt_iclass_rsr_epc1, |
| 5794 | ICLASS_xt_iclass_wsr_epc1, |
| 5795 | ICLASS_xt_iclass_xsr_epc1, |
| 5796 | ICLASS_xt_iclass_rsr_excsave1, |
| 5797 | ICLASS_xt_iclass_wsr_excsave1, |
| 5798 | ICLASS_xt_iclass_xsr_excsave1, |
| 5799 | ICLASS_xt_iclass_rsr_epc2, |
| 5800 | ICLASS_xt_iclass_wsr_epc2, |
| 5801 | ICLASS_xt_iclass_xsr_epc2, |
| 5802 | ICLASS_xt_iclass_rsr_excsave2, |
| 5803 | ICLASS_xt_iclass_wsr_excsave2, |
| 5804 | ICLASS_xt_iclass_xsr_excsave2, |
| 5805 | ICLASS_xt_iclass_rsr_epc3, |
| 5806 | ICLASS_xt_iclass_wsr_epc3, |
| 5807 | ICLASS_xt_iclass_xsr_epc3, |
| 5808 | ICLASS_xt_iclass_rsr_excsave3, |
| 5809 | ICLASS_xt_iclass_wsr_excsave3, |
| 5810 | ICLASS_xt_iclass_xsr_excsave3, |
| 5811 | ICLASS_xt_iclass_rsr_epc4, |
| 5812 | ICLASS_xt_iclass_wsr_epc4, |
| 5813 | ICLASS_xt_iclass_xsr_epc4, |
| 5814 | ICLASS_xt_iclass_rsr_excsave4, |
| 5815 | ICLASS_xt_iclass_wsr_excsave4, |
| 5816 | ICLASS_xt_iclass_xsr_excsave4, |
| 5817 | ICLASS_xt_iclass_rsr_epc5, |
| 5818 | ICLASS_xt_iclass_wsr_epc5, |
| 5819 | ICLASS_xt_iclass_xsr_epc5, |
| 5820 | ICLASS_xt_iclass_rsr_excsave5, |
| 5821 | ICLASS_xt_iclass_wsr_excsave5, |
| 5822 | ICLASS_xt_iclass_xsr_excsave5, |
| 5823 | ICLASS_xt_iclass_rsr_epc6, |
| 5824 | ICLASS_xt_iclass_wsr_epc6, |
| 5825 | ICLASS_xt_iclass_xsr_epc6, |
| 5826 | ICLASS_xt_iclass_rsr_excsave6, |
| 5827 | ICLASS_xt_iclass_wsr_excsave6, |
| 5828 | ICLASS_xt_iclass_xsr_excsave6, |
| 5829 | ICLASS_xt_iclass_rsr_epc7, |
| 5830 | ICLASS_xt_iclass_wsr_epc7, |
| 5831 | ICLASS_xt_iclass_xsr_epc7, |
| 5832 | ICLASS_xt_iclass_rsr_excsave7, |
| 5833 | ICLASS_xt_iclass_wsr_excsave7, |
| 5834 | ICLASS_xt_iclass_xsr_excsave7, |
| 5835 | ICLASS_xt_iclass_rsr_eps2, |
| 5836 | ICLASS_xt_iclass_wsr_eps2, |
| 5837 | ICLASS_xt_iclass_xsr_eps2, |
| 5838 | ICLASS_xt_iclass_rsr_eps3, |
| 5839 | ICLASS_xt_iclass_wsr_eps3, |
| 5840 | ICLASS_xt_iclass_xsr_eps3, |
| 5841 | ICLASS_xt_iclass_rsr_eps4, |
| 5842 | ICLASS_xt_iclass_wsr_eps4, |
| 5843 | ICLASS_xt_iclass_xsr_eps4, |
| 5844 | ICLASS_xt_iclass_rsr_eps5, |
| 5845 | ICLASS_xt_iclass_wsr_eps5, |
| 5846 | ICLASS_xt_iclass_xsr_eps5, |
| 5847 | ICLASS_xt_iclass_rsr_eps6, |
| 5848 | ICLASS_xt_iclass_wsr_eps6, |
| 5849 | ICLASS_xt_iclass_xsr_eps6, |
| 5850 | ICLASS_xt_iclass_rsr_eps7, |
| 5851 | ICLASS_xt_iclass_wsr_eps7, |
| 5852 | ICLASS_xt_iclass_xsr_eps7, |
| 5853 | ICLASS_xt_iclass_rsr_excvaddr, |
| 5854 | ICLASS_xt_iclass_wsr_excvaddr, |
| 5855 | ICLASS_xt_iclass_xsr_excvaddr, |
| 5856 | ICLASS_xt_iclass_rsr_depc, |
| 5857 | ICLASS_xt_iclass_wsr_depc, |
| 5858 | ICLASS_xt_iclass_xsr_depc, |
| 5859 | ICLASS_xt_iclass_rsr_exccause, |
| 5860 | ICLASS_xt_iclass_wsr_exccause, |
| 5861 | ICLASS_xt_iclass_xsr_exccause, |
| 5862 | ICLASS_xt_iclass_rsr_misc0, |
| 5863 | ICLASS_xt_iclass_wsr_misc0, |
| 5864 | ICLASS_xt_iclass_xsr_misc0, |
| 5865 | ICLASS_xt_iclass_rsr_misc1, |
| 5866 | ICLASS_xt_iclass_wsr_misc1, |
| 5867 | ICLASS_xt_iclass_xsr_misc1, |
| 5868 | ICLASS_xt_iclass_rsr_prid, |
| 5869 | ICLASS_xt_iclass_rsr_vecbase, |
| 5870 | ICLASS_xt_iclass_wsr_vecbase, |
| 5871 | ICLASS_xt_iclass_xsr_vecbase, |
| 5872 | ICLASS_xt_iclass_mul16, |
| 5873 | ICLASS_xt_iclass_rfi, |
| 5874 | ICLASS_xt_iclass_wait, |
| 5875 | ICLASS_xt_iclass_rsr_interrupt, |
| 5876 | ICLASS_xt_iclass_wsr_intset, |
| 5877 | ICLASS_xt_iclass_wsr_intclear, |
| 5878 | ICLASS_xt_iclass_rsr_intenable, |
| 5879 | ICLASS_xt_iclass_wsr_intenable, |
| 5880 | ICLASS_xt_iclass_xsr_intenable, |
| 5881 | ICLASS_xt_iclass_break, |
| 5882 | ICLASS_xt_iclass_break_n, |
| 5883 | ICLASS_xt_iclass_rsr_dbreaka0, |
| 5884 | ICLASS_xt_iclass_wsr_dbreaka0, |
| 5885 | ICLASS_xt_iclass_xsr_dbreaka0, |
| 5886 | ICLASS_xt_iclass_rsr_dbreakc0, |
| 5887 | ICLASS_xt_iclass_wsr_dbreakc0, |
| 5888 | ICLASS_xt_iclass_xsr_dbreakc0, |
| 5889 | ICLASS_xt_iclass_rsr_dbreaka1, |
| 5890 | ICLASS_xt_iclass_wsr_dbreaka1, |
| 5891 | ICLASS_xt_iclass_xsr_dbreaka1, |
| 5892 | ICLASS_xt_iclass_rsr_dbreakc1, |
| 5893 | ICLASS_xt_iclass_wsr_dbreakc1, |
| 5894 | ICLASS_xt_iclass_xsr_dbreakc1, |
| 5895 | ICLASS_xt_iclass_rsr_ibreaka0, |
| 5896 | ICLASS_xt_iclass_wsr_ibreaka0, |
| 5897 | ICLASS_xt_iclass_xsr_ibreaka0, |
| 5898 | ICLASS_xt_iclass_rsr_ibreaka1, |
| 5899 | ICLASS_xt_iclass_wsr_ibreaka1, |
| 5900 | ICLASS_xt_iclass_xsr_ibreaka1, |
| 5901 | ICLASS_xt_iclass_rsr_ibreakenable, |
| 5902 | ICLASS_xt_iclass_wsr_ibreakenable, |
| 5903 | ICLASS_xt_iclass_xsr_ibreakenable, |
| 5904 | ICLASS_xt_iclass_rsr_debugcause, |
| 5905 | ICLASS_xt_iclass_wsr_debugcause, |
| 5906 | ICLASS_xt_iclass_xsr_debugcause, |
| 5907 | ICLASS_xt_iclass_rsr_icount, |
| 5908 | ICLASS_xt_iclass_wsr_icount, |
| 5909 | ICLASS_xt_iclass_xsr_icount, |
| 5910 | ICLASS_xt_iclass_rsr_icountlevel, |
| 5911 | ICLASS_xt_iclass_wsr_icountlevel, |
| 5912 | ICLASS_xt_iclass_xsr_icountlevel, |
| 5913 | ICLASS_xt_iclass_rsr_ddr, |
| 5914 | ICLASS_xt_iclass_wsr_ddr, |
| 5915 | ICLASS_xt_iclass_xsr_ddr, |
| 5916 | ICLASS_xt_iclass_rfdo, |
| 5917 | ICLASS_xt_iclass_rfdd, |
| 5918 | ICLASS_xt_iclass_wsr_mmid, |
| 5919 | ICLASS_xt_iclass_rsr_ccount, |
| 5920 | ICLASS_xt_iclass_wsr_ccount, |
| 5921 | ICLASS_xt_iclass_xsr_ccount, |
| 5922 | ICLASS_xt_iclass_rsr_ccompare0, |
| 5923 | ICLASS_xt_iclass_wsr_ccompare0, |
| 5924 | ICLASS_xt_iclass_xsr_ccompare0, |
| 5925 | ICLASS_xt_iclass_rsr_ccompare1, |
| 5926 | ICLASS_xt_iclass_wsr_ccompare1, |
| 5927 | ICLASS_xt_iclass_xsr_ccompare1, |
| 5928 | ICLASS_xt_iclass_rsr_ccompare2, |
| 5929 | ICLASS_xt_iclass_wsr_ccompare2, |
| 5930 | ICLASS_xt_iclass_xsr_ccompare2, |
| 5931 | ICLASS_xt_iclass_icache, |
| 5932 | ICLASS_xt_iclass_icache_lock, |
| 5933 | ICLASS_xt_iclass_icache_inv, |
| 5934 | ICLASS_xt_iclass_licx, |
| 5935 | ICLASS_xt_iclass_sicx, |
| 5936 | ICLASS_xt_iclass_dcache, |
| 5937 | ICLASS_xt_iclass_dcache_ind, |
| 5938 | ICLASS_xt_iclass_dcache_inv, |
| 5939 | ICLASS_xt_iclass_dpf, |
| 5940 | ICLASS_xt_iclass_dcache_lock, |
| 5941 | ICLASS_xt_iclass_sdct, |
| 5942 | ICLASS_xt_iclass_ldct, |
| 5943 | ICLASS_xt_iclass_wsr_ptevaddr, |
| 5944 | ICLASS_xt_iclass_rsr_ptevaddr, |
| 5945 | ICLASS_xt_iclass_xsr_ptevaddr, |
| 5946 | ICLASS_xt_iclass_rsr_rasid, |
| 5947 | ICLASS_xt_iclass_wsr_rasid, |
| 5948 | ICLASS_xt_iclass_xsr_rasid, |
| 5949 | ICLASS_xt_iclass_rsr_itlbcfg, |
| 5950 | ICLASS_xt_iclass_wsr_itlbcfg, |
| 5951 | ICLASS_xt_iclass_xsr_itlbcfg, |
| 5952 | ICLASS_xt_iclass_rsr_dtlbcfg, |
| 5953 | ICLASS_xt_iclass_wsr_dtlbcfg, |
| 5954 | ICLASS_xt_iclass_xsr_dtlbcfg, |
| 5955 | ICLASS_xt_iclass_idtlb, |
| 5956 | ICLASS_xt_iclass_rdtlb, |
| 5957 | ICLASS_xt_iclass_wdtlb, |
| 5958 | ICLASS_xt_iclass_iitlb, |
| 5959 | ICLASS_xt_iclass_ritlb, |
| 5960 | ICLASS_xt_iclass_witlb, |
| 5961 | ICLASS_xt_iclass_ldpte, |
| 5962 | ICLASS_xt_iclass_hwwitlba, |
| 5963 | ICLASS_xt_iclass_hwwdtlba, |
| 5964 | ICLASS_xt_iclass_rsr_cpenable, |
| 5965 | ICLASS_xt_iclass_wsr_cpenable, |
| 5966 | ICLASS_xt_iclass_xsr_cpenable, |
| 5967 | ICLASS_xt_iclass_clamp, |
| 5968 | ICLASS_xt_iclass_minmax, |
| 5969 | ICLASS_xt_iclass_nsa, |
| 5970 | ICLASS_xt_iclass_sx, |
| 5971 | ICLASS_xt_iclass_l32ai, |
| 5972 | ICLASS_xt_iclass_s32ri, |
| 5973 | ICLASS_xt_iclass_s32c1i, |
| 5974 | ICLASS_xt_iclass_rsr_scompare1, |
| 5975 | ICLASS_xt_iclass_wsr_scompare1, |
| 5976 | ICLASS_xt_iclass_xsr_scompare1, |
| 5977 | ICLASS_xt_iclass_div, |
| 5978 | ICLASS_xt_mul32 |
| 5979 | }; |
| 5980 | |
| 5981 | \f |
| 5982 | /* Opcode encodings. */ |
| 5983 | |
| 5984 | static void |
| 5985 | Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5986 | { |
| 5987 | slotbuf[0] = 0x80200; |
| 5988 | } |
| 5989 | |
| 5990 | static void |
| 5991 | Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5992 | { |
| 5993 | slotbuf[0] = 0x300; |
| 5994 | } |
| 5995 | |
| 5996 | static void |
| 5997 | Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 5998 | { |
| 5999 | slotbuf[0] = 0x2300; |
| 6000 | } |
| 6001 | |
| 6002 | static void |
| 6003 | Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6004 | { |
| 6005 | slotbuf[0] = 0x500; |
| 6006 | } |
| 6007 | |
| 6008 | static void |
| 6009 | Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6010 | { |
| 6011 | slotbuf[0] = 0x1500; |
| 6012 | } |
| 6013 | |
| 6014 | static void |
| 6015 | Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6016 | { |
| 6017 | slotbuf[0] = 0x5c0000; |
| 6018 | } |
| 6019 | |
| 6020 | static void |
| 6021 | Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6022 | { |
| 6023 | slotbuf[0] = 0x580000; |
| 6024 | } |
| 6025 | |
| 6026 | static void |
| 6027 | Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6028 | { |
| 6029 | slotbuf[0] = 0x540000; |
| 6030 | } |
| 6031 | |
| 6032 | static void |
| 6033 | Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6034 | { |
| 6035 | slotbuf[0] = 0xf0000; |
| 6036 | } |
| 6037 | |
| 6038 | static void |
| 6039 | Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6040 | { |
| 6041 | slotbuf[0] = 0xb0000; |
| 6042 | } |
| 6043 | |
| 6044 | static void |
| 6045 | Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6046 | { |
| 6047 | slotbuf[0] = 0x70000; |
| 6048 | } |
| 6049 | |
| 6050 | static void |
| 6051 | Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6052 | { |
| 6053 | slotbuf[0] = 0x6c0000; |
| 6054 | } |
| 6055 | |
| 6056 | static void |
| 6057 | Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6058 | { |
| 6059 | slotbuf[0] = 0x100; |
| 6060 | } |
| 6061 | |
| 6062 | static void |
| 6063 | Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6064 | { |
| 6065 | slotbuf[0] = 0x804; |
| 6066 | } |
| 6067 | |
| 6068 | static void |
| 6069 | Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6070 | { |
| 6071 | slotbuf[0] = 0x60000; |
| 6072 | } |
| 6073 | |
| 6074 | static void |
| 6075 | Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6076 | { |
| 6077 | slotbuf[0] = 0xd10f; |
| 6078 | } |
| 6079 | |
| 6080 | static void |
| 6081 | Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6082 | { |
| 6083 | slotbuf[0] = 0x4300; |
| 6084 | } |
| 6085 | |
| 6086 | static void |
| 6087 | Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6088 | { |
| 6089 | slotbuf[0] = 0x5300; |
| 6090 | } |
| 6091 | |
| 6092 | static void |
| 6093 | Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6094 | { |
| 6095 | slotbuf[0] = 0x90; |
| 6096 | } |
| 6097 | |
| 6098 | static void |
| 6099 | Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6100 | { |
| 6101 | slotbuf[0] = 0x94; |
| 6102 | } |
| 6103 | |
| 6104 | static void |
| 6105 | Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6106 | { |
| 6107 | slotbuf[0] = 0x4830; |
| 6108 | } |
| 6109 | |
| 6110 | static void |
| 6111 | Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6112 | { |
| 6113 | slotbuf[0] = 0x4831; |
| 6114 | } |
| 6115 | |
| 6116 | static void |
| 6117 | Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6118 | { |
| 6119 | slotbuf[0] = 0x4816; |
| 6120 | } |
| 6121 | |
| 6122 | static void |
| 6123 | Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6124 | { |
| 6125 | slotbuf[0] = 0x4930; |
| 6126 | } |
| 6127 | |
| 6128 | static void |
| 6129 | Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6130 | { |
| 6131 | slotbuf[0] = 0x4931; |
| 6132 | } |
| 6133 | |
| 6134 | static void |
| 6135 | Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6136 | { |
| 6137 | slotbuf[0] = 0x4916; |
| 6138 | } |
| 6139 | |
| 6140 | static void |
| 6141 | Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 6142 | { |
| 6143 | slotbuf[0] = 0xa000; |
| 6144 | } |
| 6145 | |
| 6146 | static void |
| 6147 | Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 6148 | { |
| 6149 | slotbuf[0] = 0xb000; |
| 6150 | } |
| 6151 | |
| 6152 | static void |
| 6153 | Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6154 | { |
| 6155 | slotbuf[0] = 0xc800; |
| 6156 | } |
| 6157 | |
| 6158 | static void |
| 6159 | Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6160 | { |
| 6161 | slotbuf[0] = 0xcc00; |
| 6162 | } |
| 6163 | |
| 6164 | static void |
| 6165 | Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6166 | { |
| 6167 | slotbuf[0] = 0xd60f; |
| 6168 | } |
| 6169 | |
| 6170 | static void |
| 6171 | Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 6172 | { |
| 6173 | slotbuf[0] = 0x8000; |
| 6174 | } |
| 6175 | |
| 6176 | static void |
| 6177 | Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6178 | { |
| 6179 | slotbuf[0] = 0xd000; |
| 6180 | } |
| 6181 | |
| 6182 | static void |
| 6183 | Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6184 | { |
| 6185 | slotbuf[0] = 0xc000; |
| 6186 | } |
| 6187 | |
| 6188 | static void |
| 6189 | Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6190 | { |
| 6191 | slotbuf[0] = 0xd30f; |
| 6192 | } |
| 6193 | |
| 6194 | static void |
| 6195 | Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 6196 | { |
| 6197 | slotbuf[0] = 0xd00f; |
| 6198 | } |
| 6199 | |
| 6200 | static void |
| 6201 | Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) |
| 6202 | { |
| 6203 | slotbuf[0] = 0x9000; |
| 6204 | } |
| 6205 | |
| 6206 | static void |
| 6207 | Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6208 | { |
| 6209 | slotbuf[0] = 0x7e03e; |
| 6210 | } |
| 6211 | |
| 6212 | static void |
| 6213 | Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6214 | { |
| 6215 | slotbuf[0] = 0xe73f; |
| 6216 | } |
| 6217 | |
| 6218 | static void |
| 6219 | Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6220 | { |
| 6221 | slotbuf[0] = 0x200c00; |
| 6222 | } |
| 6223 | |
| 6224 | static void |
| 6225 | Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6226 | { |
| 6227 | slotbuf[0] = 0x200d00; |
| 6228 | } |
| 6229 | |
| 6230 | static void |
| 6231 | Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6232 | { |
| 6233 | slotbuf[0] = 0x8; |
| 6234 | } |
| 6235 | |
| 6236 | static void |
| 6237 | Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6238 | { |
| 6239 | slotbuf[0] = 0xc; |
| 6240 | } |
| 6241 | |
| 6242 | static void |
| 6243 | Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6244 | { |
| 6245 | slotbuf[0] = 0x9; |
| 6246 | } |
| 6247 | |
| 6248 | static void |
| 6249 | Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6250 | { |
| 6251 | slotbuf[0] = 0xa; |
| 6252 | } |
| 6253 | |
| 6254 | static void |
| 6255 | Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6256 | { |
| 6257 | slotbuf[0] = 0xb; |
| 6258 | } |
| 6259 | |
| 6260 | static void |
| 6261 | Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6262 | { |
| 6263 | slotbuf[0] = 0xd; |
| 6264 | } |
| 6265 | |
| 6266 | static void |
| 6267 | Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6268 | { |
| 6269 | slotbuf[0] = 0xe; |
| 6270 | } |
| 6271 | |
| 6272 | static void |
| 6273 | Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6274 | { |
| 6275 | slotbuf[0] = 0xf; |
| 6276 | } |
| 6277 | |
| 6278 | static void |
| 6279 | Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6280 | { |
| 6281 | slotbuf[0] = 0x1; |
| 6282 | } |
| 6283 | |
| 6284 | static void |
| 6285 | Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6286 | { |
| 6287 | slotbuf[0] = 0x2; |
| 6288 | } |
| 6289 | |
| 6290 | static void |
| 6291 | Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6292 | { |
| 6293 | slotbuf[0] = 0x3; |
| 6294 | } |
| 6295 | |
| 6296 | static void |
| 6297 | Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6298 | { |
| 6299 | slotbuf[0] = 0x680000; |
| 6300 | } |
| 6301 | |
| 6302 | static void |
| 6303 | Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6304 | { |
| 6305 | slotbuf[0] = 0x690000; |
| 6306 | } |
| 6307 | |
| 6308 | static void |
| 6309 | Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6310 | { |
| 6311 | slotbuf[0] = 0x6b0000; |
| 6312 | } |
| 6313 | |
| 6314 | static void |
| 6315 | Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6316 | { |
| 6317 | slotbuf[0] = 0x6a0000; |
| 6318 | } |
| 6319 | |
| 6320 | static void |
| 6321 | Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6322 | { |
| 6323 | slotbuf[0] = 0x700600; |
| 6324 | } |
| 6325 | |
| 6326 | static void |
| 6327 | Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6328 | { |
| 6329 | slotbuf[0] = 0x700e00; |
| 6330 | } |
| 6331 | |
| 6332 | static void |
| 6333 | Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6334 | { |
| 6335 | slotbuf[0] = 0x6f0000; |
| 6336 | } |
| 6337 | |
| 6338 | static void |
| 6339 | Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6340 | { |
| 6341 | slotbuf[0] = 0x6e0000; |
| 6342 | } |
| 6343 | |
| 6344 | static void |
| 6345 | Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6346 | { |
| 6347 | slotbuf[0] = 0x700100; |
| 6348 | } |
| 6349 | |
| 6350 | static void |
| 6351 | Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6352 | { |
| 6353 | slotbuf[0] = 0x700900; |
| 6354 | } |
| 6355 | |
| 6356 | static void |
| 6357 | Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6358 | { |
| 6359 | slotbuf[0] = 0x700a00; |
| 6360 | } |
| 6361 | |
| 6362 | static void |
| 6363 | Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6364 | { |
| 6365 | slotbuf[0] = 0x700200; |
| 6366 | } |
| 6367 | |
| 6368 | static void |
| 6369 | Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6370 | { |
| 6371 | slotbuf[0] = 0x700b00; |
| 6372 | } |
| 6373 | |
| 6374 | static void |
| 6375 | Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6376 | { |
| 6377 | slotbuf[0] = 0x700300; |
| 6378 | } |
| 6379 | |
| 6380 | static void |
| 6381 | Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6382 | { |
| 6383 | slotbuf[0] = 0x700800; |
| 6384 | } |
| 6385 | |
| 6386 | static void |
| 6387 | Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6388 | { |
| 6389 | slotbuf[0] = 0x700000; |
| 6390 | } |
| 6391 | |
| 6392 | static void |
| 6393 | Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6394 | { |
| 6395 | slotbuf[0] = 0x700400; |
| 6396 | } |
| 6397 | |
| 6398 | static void |
| 6399 | Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6400 | { |
| 6401 | slotbuf[0] = 0x700c00; |
| 6402 | } |
| 6403 | |
| 6404 | static void |
| 6405 | Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6406 | { |
| 6407 | slotbuf[0] = 0x700500; |
| 6408 | } |
| 6409 | |
| 6410 | static void |
| 6411 | Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6412 | { |
| 6413 | slotbuf[0] = 0x700d00; |
| 6414 | } |
| 6415 | |
| 6416 | static void |
| 6417 | Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6418 | { |
| 6419 | slotbuf[0] = 0x640000; |
| 6420 | } |
| 6421 | |
| 6422 | static void |
| 6423 | Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6424 | { |
| 6425 | slotbuf[0] = 0x650000; |
| 6426 | } |
| 6427 | |
| 6428 | static void |
| 6429 | Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6430 | { |
| 6431 | slotbuf[0] = 0x670000; |
| 6432 | } |
| 6433 | |
| 6434 | static void |
| 6435 | Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6436 | { |
| 6437 | slotbuf[0] = 0x660000; |
| 6438 | } |
| 6439 | |
| 6440 | static void |
| 6441 | Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6442 | { |
| 6443 | slotbuf[0] = 0x500000; |
| 6444 | } |
| 6445 | |
| 6446 | static void |
| 6447 | Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6448 | { |
| 6449 | slotbuf[0] = 0x30000; |
| 6450 | } |
| 6451 | |
| 6452 | static void |
| 6453 | Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6454 | { |
| 6455 | slotbuf[0] = 0x40; |
| 6456 | } |
| 6457 | |
| 6458 | static void |
| 6459 | Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6460 | { |
| 6461 | slotbuf[0] = 0; |
| 6462 | } |
| 6463 | |
| 6464 | static void |
| 6465 | Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6466 | { |
| 6467 | slotbuf[0] = 0x600000; |
| 6468 | } |
| 6469 | |
| 6470 | static void |
| 6471 | Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6472 | { |
| 6473 | slotbuf[0] = 0xa0000; |
| 6474 | } |
| 6475 | |
| 6476 | static void |
| 6477 | Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6478 | { |
| 6479 | slotbuf[0] = 0x200100; |
| 6480 | } |
| 6481 | |
| 6482 | static void |
| 6483 | Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6484 | { |
| 6485 | slotbuf[0] = 0x200900; |
| 6486 | } |
| 6487 | |
| 6488 | static void |
| 6489 | Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6490 | { |
| 6491 | slotbuf[0] = 0x200200; |
| 6492 | } |
| 6493 | |
| 6494 | static void |
| 6495 | Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6496 | { |
| 6497 | slotbuf[0] = 0x100000; |
| 6498 | } |
| 6499 | |
| 6500 | static void |
| 6501 | Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6502 | { |
| 6503 | slotbuf[0] = 0x200000; |
| 6504 | } |
| 6505 | |
| 6506 | static void |
| 6507 | Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6508 | { |
| 6509 | slotbuf[0] = 0x6d0800; |
| 6510 | } |
| 6511 | |
| 6512 | static void |
| 6513 | Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6514 | { |
| 6515 | slotbuf[0] = 0x6d0900; |
| 6516 | } |
| 6517 | |
| 6518 | static void |
| 6519 | Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6520 | { |
| 6521 | slotbuf[0] = 0x6d0a00; |
| 6522 | } |
| 6523 | |
| 6524 | static void |
| 6525 | Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6526 | { |
| 6527 | slotbuf[0] = 0x200a00; |
| 6528 | } |
| 6529 | |
| 6530 | static void |
| 6531 | Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6532 | { |
| 6533 | slotbuf[0] = 0x38; |
| 6534 | } |
| 6535 | |
| 6536 | static void |
| 6537 | Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6538 | { |
| 6539 | slotbuf[0] = 0x39; |
| 6540 | } |
| 6541 | |
| 6542 | static void |
| 6543 | Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6544 | { |
| 6545 | slotbuf[0] = 0x3a; |
| 6546 | } |
| 6547 | |
| 6548 | static void |
| 6549 | Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6550 | { |
| 6551 | slotbuf[0] = 0x3b; |
| 6552 | } |
| 6553 | |
| 6554 | static void |
| 6555 | Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6556 | { |
| 6557 | slotbuf[0] = 0x6; |
| 6558 | } |
| 6559 | |
| 6560 | static void |
| 6561 | Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6562 | { |
| 6563 | slotbuf[0] = 0x1006; |
| 6564 | } |
| 6565 | |
| 6566 | static void |
| 6567 | Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6568 | { |
| 6569 | slotbuf[0] = 0xf0200; |
| 6570 | } |
| 6571 | |
| 6572 | static void |
| 6573 | Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6574 | { |
| 6575 | slotbuf[0] = 0x20000; |
| 6576 | } |
| 6577 | |
| 6578 | static void |
| 6579 | Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6580 | { |
| 6581 | slotbuf[0] = 0x200500; |
| 6582 | } |
| 6583 | |
| 6584 | static void |
| 6585 | Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6586 | { |
| 6587 | slotbuf[0] = 0x200600; |
| 6588 | } |
| 6589 | |
| 6590 | static void |
| 6591 | Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6592 | { |
| 6593 | slotbuf[0] = 0x200400; |
| 6594 | } |
| 6595 | |
| 6596 | static void |
| 6597 | Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6598 | { |
| 6599 | slotbuf[0] = 0x4; |
| 6600 | } |
| 6601 | |
| 6602 | static void |
| 6603 | Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6604 | { |
| 6605 | slotbuf[0] = 0x104; |
| 6606 | } |
| 6607 | |
| 6608 | static void |
| 6609 | Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6610 | { |
| 6611 | slotbuf[0] = 0x204; |
| 6612 | } |
| 6613 | |
| 6614 | static void |
| 6615 | Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6616 | { |
| 6617 | slotbuf[0] = 0x304; |
| 6618 | } |
| 6619 | |
| 6620 | static void |
| 6621 | Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6622 | { |
| 6623 | slotbuf[0] = 0x404; |
| 6624 | } |
| 6625 | |
| 6626 | static void |
| 6627 | Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6628 | { |
| 6629 | slotbuf[0] = 0x1a; |
| 6630 | } |
| 6631 | |
| 6632 | static void |
| 6633 | Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6634 | { |
| 6635 | slotbuf[0] = 0x18; |
| 6636 | } |
| 6637 | |
| 6638 | static void |
| 6639 | Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6640 | { |
| 6641 | slotbuf[0] = 0x19; |
| 6642 | } |
| 6643 | |
| 6644 | static void |
| 6645 | Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6646 | { |
| 6647 | slotbuf[0] = 0x1b; |
| 6648 | } |
| 6649 | |
| 6650 | static void |
| 6651 | Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6652 | { |
| 6653 | slotbuf[0] = 0x10; |
| 6654 | } |
| 6655 | |
| 6656 | static void |
| 6657 | Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6658 | { |
| 6659 | slotbuf[0] = 0x12; |
| 6660 | } |
| 6661 | |
| 6662 | static void |
| 6663 | Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6664 | { |
| 6665 | slotbuf[0] = 0x14; |
| 6666 | } |
| 6667 | |
| 6668 | static void |
| 6669 | Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6670 | { |
| 6671 | slotbuf[0] = 0xc0200; |
| 6672 | } |
| 6673 | |
| 6674 | static void |
| 6675 | Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6676 | { |
| 6677 | slotbuf[0] = 0xd0200; |
| 6678 | } |
| 6679 | |
| 6680 | static void |
| 6681 | Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6682 | { |
| 6683 | slotbuf[0] = 0x200; |
| 6684 | } |
| 6685 | |
| 6686 | static void |
| 6687 | Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6688 | { |
| 6689 | slotbuf[0] = 0x10200; |
| 6690 | } |
| 6691 | |
| 6692 | static void |
| 6693 | Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6694 | { |
| 6695 | slotbuf[0] = 0x20200; |
| 6696 | } |
| 6697 | |
| 6698 | static void |
| 6699 | Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6700 | { |
| 6701 | slotbuf[0] = 0x30200; |
| 6702 | } |
| 6703 | |
| 6704 | static void |
| 6705 | Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6706 | { |
| 6707 | slotbuf[0] = 0x600; |
| 6708 | } |
| 6709 | |
| 6710 | static void |
| 6711 | Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6712 | { |
| 6713 | slotbuf[0] = 0x130; |
| 6714 | } |
| 6715 | |
| 6716 | static void |
| 6717 | Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6718 | { |
| 6719 | slotbuf[0] = 0x131; |
| 6720 | } |
| 6721 | |
| 6722 | static void |
| 6723 | Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6724 | { |
| 6725 | slotbuf[0] = 0x116; |
| 6726 | } |
| 6727 | |
| 6728 | static void |
| 6729 | Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6730 | { |
| 6731 | slotbuf[0] = 0x230; |
| 6732 | } |
| 6733 | |
| 6734 | static void |
| 6735 | Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6736 | { |
| 6737 | slotbuf[0] = 0x231; |
| 6738 | } |
| 6739 | |
| 6740 | static void |
| 6741 | Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6742 | { |
| 6743 | slotbuf[0] = 0x216; |
| 6744 | } |
| 6745 | |
| 6746 | static void |
| 6747 | Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6748 | { |
| 6749 | slotbuf[0] = 0x30; |
| 6750 | } |
| 6751 | |
| 6752 | static void |
| 6753 | Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6754 | { |
| 6755 | slotbuf[0] = 0x31; |
| 6756 | } |
| 6757 | |
| 6758 | static void |
| 6759 | Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6760 | { |
| 6761 | slotbuf[0] = 0x16; |
| 6762 | } |
| 6763 | |
| 6764 | static void |
| 6765 | Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6766 | { |
| 6767 | slotbuf[0] = 0x330; |
| 6768 | } |
| 6769 | |
| 6770 | static void |
| 6771 | Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6772 | { |
| 6773 | slotbuf[0] = 0x331; |
| 6774 | } |
| 6775 | |
| 6776 | static void |
| 6777 | Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6778 | { |
| 6779 | slotbuf[0] = 0x316; |
| 6780 | } |
| 6781 | |
| 6782 | static void |
| 6783 | Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6784 | { |
| 6785 | slotbuf[0] = 0x530; |
| 6786 | } |
| 6787 | |
| 6788 | static void |
| 6789 | Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6790 | { |
| 6791 | slotbuf[0] = 0x531; |
| 6792 | } |
| 6793 | |
| 6794 | static void |
| 6795 | Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6796 | { |
| 6797 | slotbuf[0] = 0x516; |
| 6798 | } |
| 6799 | |
| 6800 | static void |
| 6801 | Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6802 | { |
| 6803 | slotbuf[0] = 0xb030; |
| 6804 | } |
| 6805 | |
| 6806 | static void |
| 6807 | Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6808 | { |
| 6809 | slotbuf[0] = 0xb031; |
| 6810 | } |
| 6811 | |
| 6812 | static void |
| 6813 | Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6814 | { |
| 6815 | slotbuf[0] = 0xd030; |
| 6816 | } |
| 6817 | |
| 6818 | static void |
| 6819 | Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6820 | { |
| 6821 | slotbuf[0] = 0xe630; |
| 6822 | } |
| 6823 | |
| 6824 | static void |
| 6825 | Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6826 | { |
| 6827 | slotbuf[0] = 0xe631; |
| 6828 | } |
| 6829 | |
| 6830 | static void |
| 6831 | Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6832 | { |
| 6833 | slotbuf[0] = 0xe616; |
| 6834 | } |
| 6835 | |
| 6836 | static void |
| 6837 | Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6838 | { |
| 6839 | slotbuf[0] = 0xb130; |
| 6840 | } |
| 6841 | |
| 6842 | static void |
| 6843 | Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6844 | { |
| 6845 | slotbuf[0] = 0xb131; |
| 6846 | } |
| 6847 | |
| 6848 | static void |
| 6849 | Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6850 | { |
| 6851 | slotbuf[0] = 0xb116; |
| 6852 | } |
| 6853 | |
| 6854 | static void |
| 6855 | Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6856 | { |
| 6857 | slotbuf[0] = 0xd130; |
| 6858 | } |
| 6859 | |
| 6860 | static void |
| 6861 | Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6862 | { |
| 6863 | slotbuf[0] = 0xd131; |
| 6864 | } |
| 6865 | |
| 6866 | static void |
| 6867 | Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6868 | { |
| 6869 | slotbuf[0] = 0xd116; |
| 6870 | } |
| 6871 | |
| 6872 | static void |
| 6873 | Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6874 | { |
| 6875 | slotbuf[0] = 0xb230; |
| 6876 | } |
| 6877 | |
| 6878 | static void |
| 6879 | Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6880 | { |
| 6881 | slotbuf[0] = 0xb231; |
| 6882 | } |
| 6883 | |
| 6884 | static void |
| 6885 | Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6886 | { |
| 6887 | slotbuf[0] = 0xb216; |
| 6888 | } |
| 6889 | |
| 6890 | static void |
| 6891 | Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6892 | { |
| 6893 | slotbuf[0] = 0xd230; |
| 6894 | } |
| 6895 | |
| 6896 | static void |
| 6897 | Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6898 | { |
| 6899 | slotbuf[0] = 0xd231; |
| 6900 | } |
| 6901 | |
| 6902 | static void |
| 6903 | Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6904 | { |
| 6905 | slotbuf[0] = 0xd216; |
| 6906 | } |
| 6907 | |
| 6908 | static void |
| 6909 | Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6910 | { |
| 6911 | slotbuf[0] = 0xb330; |
| 6912 | } |
| 6913 | |
| 6914 | static void |
| 6915 | Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6916 | { |
| 6917 | slotbuf[0] = 0xb331; |
| 6918 | } |
| 6919 | |
| 6920 | static void |
| 6921 | Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6922 | { |
| 6923 | slotbuf[0] = 0xb316; |
| 6924 | } |
| 6925 | |
| 6926 | static void |
| 6927 | Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6928 | { |
| 6929 | slotbuf[0] = 0xd330; |
| 6930 | } |
| 6931 | |
| 6932 | static void |
| 6933 | Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6934 | { |
| 6935 | slotbuf[0] = 0xd331; |
| 6936 | } |
| 6937 | |
| 6938 | static void |
| 6939 | Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6940 | { |
| 6941 | slotbuf[0] = 0xd316; |
| 6942 | } |
| 6943 | |
| 6944 | static void |
| 6945 | Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6946 | { |
| 6947 | slotbuf[0] = 0xb430; |
| 6948 | } |
| 6949 | |
| 6950 | static void |
| 6951 | Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6952 | { |
| 6953 | slotbuf[0] = 0xb431; |
| 6954 | } |
| 6955 | |
| 6956 | static void |
| 6957 | Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6958 | { |
| 6959 | slotbuf[0] = 0xb416; |
| 6960 | } |
| 6961 | |
| 6962 | static void |
| 6963 | Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6964 | { |
| 6965 | slotbuf[0] = 0xd430; |
| 6966 | } |
| 6967 | |
| 6968 | static void |
| 6969 | Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6970 | { |
| 6971 | slotbuf[0] = 0xd431; |
| 6972 | } |
| 6973 | |
| 6974 | static void |
| 6975 | Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6976 | { |
| 6977 | slotbuf[0] = 0xd416; |
| 6978 | } |
| 6979 | |
| 6980 | static void |
| 6981 | Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6982 | { |
| 6983 | slotbuf[0] = 0xb530; |
| 6984 | } |
| 6985 | |
| 6986 | static void |
| 6987 | Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6988 | { |
| 6989 | slotbuf[0] = 0xb531; |
| 6990 | } |
| 6991 | |
| 6992 | static void |
| 6993 | Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 6994 | { |
| 6995 | slotbuf[0] = 0xb516; |
| 6996 | } |
| 6997 | |
| 6998 | static void |
| 6999 | Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7000 | { |
| 7001 | slotbuf[0] = 0xd530; |
| 7002 | } |
| 7003 | |
| 7004 | static void |
| 7005 | Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7006 | { |
| 7007 | slotbuf[0] = 0xd531; |
| 7008 | } |
| 7009 | |
| 7010 | static void |
| 7011 | Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7012 | { |
| 7013 | slotbuf[0] = 0xd516; |
| 7014 | } |
| 7015 | |
| 7016 | static void |
| 7017 | Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7018 | { |
| 7019 | slotbuf[0] = 0xb630; |
| 7020 | } |
| 7021 | |
| 7022 | static void |
| 7023 | Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7024 | { |
| 7025 | slotbuf[0] = 0xb631; |
| 7026 | } |
| 7027 | |
| 7028 | static void |
| 7029 | Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7030 | { |
| 7031 | slotbuf[0] = 0xb616; |
| 7032 | } |
| 7033 | |
| 7034 | static void |
| 7035 | Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7036 | { |
| 7037 | slotbuf[0] = 0xd630; |
| 7038 | } |
| 7039 | |
| 7040 | static void |
| 7041 | Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7042 | { |
| 7043 | slotbuf[0] = 0xd631; |
| 7044 | } |
| 7045 | |
| 7046 | static void |
| 7047 | Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7048 | { |
| 7049 | slotbuf[0] = 0xd616; |
| 7050 | } |
| 7051 | |
| 7052 | static void |
| 7053 | Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7054 | { |
| 7055 | slotbuf[0] = 0xb730; |
| 7056 | } |
| 7057 | |
| 7058 | static void |
| 7059 | Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7060 | { |
| 7061 | slotbuf[0] = 0xb731; |
| 7062 | } |
| 7063 | |
| 7064 | static void |
| 7065 | Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7066 | { |
| 7067 | slotbuf[0] = 0xb716; |
| 7068 | } |
| 7069 | |
| 7070 | static void |
| 7071 | Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7072 | { |
| 7073 | slotbuf[0] = 0xd730; |
| 7074 | } |
| 7075 | |
| 7076 | static void |
| 7077 | Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7078 | { |
| 7079 | slotbuf[0] = 0xd731; |
| 7080 | } |
| 7081 | |
| 7082 | static void |
| 7083 | Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7084 | { |
| 7085 | slotbuf[0] = 0xd716; |
| 7086 | } |
| 7087 | |
| 7088 | static void |
| 7089 | Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7090 | { |
| 7091 | slotbuf[0] = 0xc230; |
| 7092 | } |
| 7093 | |
| 7094 | static void |
| 7095 | Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7096 | { |
| 7097 | slotbuf[0] = 0xc231; |
| 7098 | } |
| 7099 | |
| 7100 | static void |
| 7101 | Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7102 | { |
| 7103 | slotbuf[0] = 0xc216; |
| 7104 | } |
| 7105 | |
| 7106 | static void |
| 7107 | Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7108 | { |
| 7109 | slotbuf[0] = 0xc330; |
| 7110 | } |
| 7111 | |
| 7112 | static void |
| 7113 | Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7114 | { |
| 7115 | slotbuf[0] = 0xc331; |
| 7116 | } |
| 7117 | |
| 7118 | static void |
| 7119 | Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7120 | { |
| 7121 | slotbuf[0] = 0xc316; |
| 7122 | } |
| 7123 | |
| 7124 | static void |
| 7125 | Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7126 | { |
| 7127 | slotbuf[0] = 0xc430; |
| 7128 | } |
| 7129 | |
| 7130 | static void |
| 7131 | Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7132 | { |
| 7133 | slotbuf[0] = 0xc431; |
| 7134 | } |
| 7135 | |
| 7136 | static void |
| 7137 | Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7138 | { |
| 7139 | slotbuf[0] = 0xc416; |
| 7140 | } |
| 7141 | |
| 7142 | static void |
| 7143 | Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7144 | { |
| 7145 | slotbuf[0] = 0xc530; |
| 7146 | } |
| 7147 | |
| 7148 | static void |
| 7149 | Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7150 | { |
| 7151 | slotbuf[0] = 0xc531; |
| 7152 | } |
| 7153 | |
| 7154 | static void |
| 7155 | Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7156 | { |
| 7157 | slotbuf[0] = 0xc516; |
| 7158 | } |
| 7159 | |
| 7160 | static void |
| 7161 | Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7162 | { |
| 7163 | slotbuf[0] = 0xc630; |
| 7164 | } |
| 7165 | |
| 7166 | static void |
| 7167 | Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7168 | { |
| 7169 | slotbuf[0] = 0xc631; |
| 7170 | } |
| 7171 | |
| 7172 | static void |
| 7173 | Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7174 | { |
| 7175 | slotbuf[0] = 0xc616; |
| 7176 | } |
| 7177 | |
| 7178 | static void |
| 7179 | Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7180 | { |
| 7181 | slotbuf[0] = 0xc730; |
| 7182 | } |
| 7183 | |
| 7184 | static void |
| 7185 | Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7186 | { |
| 7187 | slotbuf[0] = 0xc731; |
| 7188 | } |
| 7189 | |
| 7190 | static void |
| 7191 | Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7192 | { |
| 7193 | slotbuf[0] = 0xc716; |
| 7194 | } |
| 7195 | |
| 7196 | static void |
| 7197 | Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7198 | { |
| 7199 | slotbuf[0] = 0xee30; |
| 7200 | } |
| 7201 | |
| 7202 | static void |
| 7203 | Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7204 | { |
| 7205 | slotbuf[0] = 0xee31; |
| 7206 | } |
| 7207 | |
| 7208 | static void |
| 7209 | Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7210 | { |
| 7211 | slotbuf[0] = 0xee16; |
| 7212 | } |
| 7213 | |
| 7214 | static void |
| 7215 | Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7216 | { |
| 7217 | slotbuf[0] = 0xc030; |
| 7218 | } |
| 7219 | |
| 7220 | static void |
| 7221 | Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7222 | { |
| 7223 | slotbuf[0] = 0xc031; |
| 7224 | } |
| 7225 | |
| 7226 | static void |
| 7227 | Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7228 | { |
| 7229 | slotbuf[0] = 0xc016; |
| 7230 | } |
| 7231 | |
| 7232 | static void |
| 7233 | Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7234 | { |
| 7235 | slotbuf[0] = 0xe830; |
| 7236 | } |
| 7237 | |
| 7238 | static void |
| 7239 | Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7240 | { |
| 7241 | slotbuf[0] = 0xe831; |
| 7242 | } |
| 7243 | |
| 7244 | static void |
| 7245 | Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7246 | { |
| 7247 | slotbuf[0] = 0xe816; |
| 7248 | } |
| 7249 | |
| 7250 | static void |
| 7251 | Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7252 | { |
| 7253 | slotbuf[0] = 0xf430; |
| 7254 | } |
| 7255 | |
| 7256 | static void |
| 7257 | Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7258 | { |
| 7259 | slotbuf[0] = 0xf431; |
| 7260 | } |
| 7261 | |
| 7262 | static void |
| 7263 | Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7264 | { |
| 7265 | slotbuf[0] = 0xf416; |
| 7266 | } |
| 7267 | |
| 7268 | static void |
| 7269 | Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7270 | { |
| 7271 | slotbuf[0] = 0xf530; |
| 7272 | } |
| 7273 | |
| 7274 | static void |
| 7275 | Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7276 | { |
| 7277 | slotbuf[0] = 0xf531; |
| 7278 | } |
| 7279 | |
| 7280 | static void |
| 7281 | Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7282 | { |
| 7283 | slotbuf[0] = 0xf516; |
| 7284 | } |
| 7285 | |
| 7286 | static void |
| 7287 | Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7288 | { |
| 7289 | slotbuf[0] = 0xeb30; |
| 7290 | } |
| 7291 | |
| 7292 | static void |
| 7293 | Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7294 | { |
| 7295 | slotbuf[0] = 0xe730; |
| 7296 | } |
| 7297 | |
| 7298 | static void |
| 7299 | Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7300 | { |
| 7301 | slotbuf[0] = 0xe731; |
| 7302 | } |
| 7303 | |
| 7304 | static void |
| 7305 | Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7306 | { |
| 7307 | slotbuf[0] = 0xe716; |
| 7308 | } |
| 7309 | |
| 7310 | static void |
| 7311 | Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7312 | { |
| 7313 | slotbuf[0] = 0x1c; |
| 7314 | } |
| 7315 | |
| 7316 | static void |
| 7317 | Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7318 | { |
| 7319 | slotbuf[0] = 0x1d; |
| 7320 | } |
| 7321 | |
| 7322 | static void |
| 7323 | Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7324 | { |
| 7325 | slotbuf[0] = 0x10300; |
| 7326 | } |
| 7327 | |
| 7328 | static void |
| 7329 | Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7330 | { |
| 7331 | slotbuf[0] = 0x700; |
| 7332 | } |
| 7333 | |
| 7334 | static void |
| 7335 | Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7336 | { |
| 7337 | slotbuf[0] = 0xe230; |
| 7338 | } |
| 7339 | |
| 7340 | static void |
| 7341 | Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7342 | { |
| 7343 | slotbuf[0] = 0xe231; |
| 7344 | } |
| 7345 | |
| 7346 | static void |
| 7347 | Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7348 | { |
| 7349 | slotbuf[0] = 0xe331; |
| 7350 | } |
| 7351 | |
| 7352 | static void |
| 7353 | Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7354 | { |
| 7355 | slotbuf[0] = 0xe430; |
| 7356 | } |
| 7357 | |
| 7358 | static void |
| 7359 | Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7360 | { |
| 7361 | slotbuf[0] = 0xe431; |
| 7362 | } |
| 7363 | |
| 7364 | static void |
| 7365 | Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7366 | { |
| 7367 | slotbuf[0] = 0xe416; |
| 7368 | } |
| 7369 | |
| 7370 | static void |
| 7371 | Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7372 | { |
| 7373 | slotbuf[0] = 0x400; |
| 7374 | } |
| 7375 | |
| 7376 | static void |
| 7377 | Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) |
| 7378 | { |
| 7379 | slotbuf[0] = 0xd20f; |
| 7380 | } |
| 7381 | |
| 7382 | static void |
| 7383 | Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7384 | { |
| 7385 | slotbuf[0] = 0x9030; |
| 7386 | } |
| 7387 | |
| 7388 | static void |
| 7389 | Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7390 | { |
| 7391 | slotbuf[0] = 0x9031; |
| 7392 | } |
| 7393 | |
| 7394 | static void |
| 7395 | Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7396 | { |
| 7397 | slotbuf[0] = 0x9016; |
| 7398 | } |
| 7399 | |
| 7400 | static void |
| 7401 | Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7402 | { |
| 7403 | slotbuf[0] = 0xa030; |
| 7404 | } |
| 7405 | |
| 7406 | static void |
| 7407 | Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7408 | { |
| 7409 | slotbuf[0] = 0xa031; |
| 7410 | } |
| 7411 | |
| 7412 | static void |
| 7413 | Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7414 | { |
| 7415 | slotbuf[0] = 0xa016; |
| 7416 | } |
| 7417 | |
| 7418 | static void |
| 7419 | Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7420 | { |
| 7421 | slotbuf[0] = 0x9130; |
| 7422 | } |
| 7423 | |
| 7424 | static void |
| 7425 | Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7426 | { |
| 7427 | slotbuf[0] = 0x9131; |
| 7428 | } |
| 7429 | |
| 7430 | static void |
| 7431 | Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7432 | { |
| 7433 | slotbuf[0] = 0x9116; |
| 7434 | } |
| 7435 | |
| 7436 | static void |
| 7437 | Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7438 | { |
| 7439 | slotbuf[0] = 0xa130; |
| 7440 | } |
| 7441 | |
| 7442 | static void |
| 7443 | Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7444 | { |
| 7445 | slotbuf[0] = 0xa131; |
| 7446 | } |
| 7447 | |
| 7448 | static void |
| 7449 | Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7450 | { |
| 7451 | slotbuf[0] = 0xa116; |
| 7452 | } |
| 7453 | |
| 7454 | static void |
| 7455 | Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7456 | { |
| 7457 | slotbuf[0] = 0x8030; |
| 7458 | } |
| 7459 | |
| 7460 | static void |
| 7461 | Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7462 | { |
| 7463 | slotbuf[0] = 0x8031; |
| 7464 | } |
| 7465 | |
| 7466 | static void |
| 7467 | Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7468 | { |
| 7469 | slotbuf[0] = 0x8016; |
| 7470 | } |
| 7471 | |
| 7472 | static void |
| 7473 | Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7474 | { |
| 7475 | slotbuf[0] = 0x8130; |
| 7476 | } |
| 7477 | |
| 7478 | static void |
| 7479 | Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7480 | { |
| 7481 | slotbuf[0] = 0x8131; |
| 7482 | } |
| 7483 | |
| 7484 | static void |
| 7485 | Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7486 | { |
| 7487 | slotbuf[0] = 0x8116; |
| 7488 | } |
| 7489 | |
| 7490 | static void |
| 7491 | Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7492 | { |
| 7493 | slotbuf[0] = 0x6030; |
| 7494 | } |
| 7495 | |
| 7496 | static void |
| 7497 | Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7498 | { |
| 7499 | slotbuf[0] = 0x6031; |
| 7500 | } |
| 7501 | |
| 7502 | static void |
| 7503 | Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7504 | { |
| 7505 | slotbuf[0] = 0x6016; |
| 7506 | } |
| 7507 | |
| 7508 | static void |
| 7509 | Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7510 | { |
| 7511 | slotbuf[0] = 0xe930; |
| 7512 | } |
| 7513 | |
| 7514 | static void |
| 7515 | Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7516 | { |
| 7517 | slotbuf[0] = 0xe931; |
| 7518 | } |
| 7519 | |
| 7520 | static void |
| 7521 | Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7522 | { |
| 7523 | slotbuf[0] = 0xe916; |
| 7524 | } |
| 7525 | |
| 7526 | static void |
| 7527 | Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7528 | { |
| 7529 | slotbuf[0] = 0xec30; |
| 7530 | } |
| 7531 | |
| 7532 | static void |
| 7533 | Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7534 | { |
| 7535 | slotbuf[0] = 0xec31; |
| 7536 | } |
| 7537 | |
| 7538 | static void |
| 7539 | Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7540 | { |
| 7541 | slotbuf[0] = 0xec16; |
| 7542 | } |
| 7543 | |
| 7544 | static void |
| 7545 | Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7546 | { |
| 7547 | slotbuf[0] = 0xed30; |
| 7548 | } |
| 7549 | |
| 7550 | static void |
| 7551 | Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7552 | { |
| 7553 | slotbuf[0] = 0xed31; |
| 7554 | } |
| 7555 | |
| 7556 | static void |
| 7557 | Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7558 | { |
| 7559 | slotbuf[0] = 0xed16; |
| 7560 | } |
| 7561 | |
| 7562 | static void |
| 7563 | Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7564 | { |
| 7565 | slotbuf[0] = 0x6830; |
| 7566 | } |
| 7567 | |
| 7568 | static void |
| 7569 | Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7570 | { |
| 7571 | slotbuf[0] = 0x6831; |
| 7572 | } |
| 7573 | |
| 7574 | static void |
| 7575 | Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7576 | { |
| 7577 | slotbuf[0] = 0x6816; |
| 7578 | } |
| 7579 | |
| 7580 | static void |
| 7581 | Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7582 | { |
| 7583 | slotbuf[0] = 0xe1f; |
| 7584 | } |
| 7585 | |
| 7586 | static void |
| 7587 | Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7588 | { |
| 7589 | slotbuf[0] = 0x10e1f; |
| 7590 | } |
| 7591 | |
| 7592 | static void |
| 7593 | Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7594 | { |
| 7595 | slotbuf[0] = 0x5931; |
| 7596 | } |
| 7597 | |
| 7598 | static void |
| 7599 | Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7600 | { |
| 7601 | slotbuf[0] = 0xea30; |
| 7602 | } |
| 7603 | |
| 7604 | static void |
| 7605 | Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7606 | { |
| 7607 | slotbuf[0] = 0xea31; |
| 7608 | } |
| 7609 | |
| 7610 | static void |
| 7611 | Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7612 | { |
| 7613 | slotbuf[0] = 0xea16; |
| 7614 | } |
| 7615 | |
| 7616 | static void |
| 7617 | Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7618 | { |
| 7619 | slotbuf[0] = 0xf030; |
| 7620 | } |
| 7621 | |
| 7622 | static void |
| 7623 | Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7624 | { |
| 7625 | slotbuf[0] = 0xf031; |
| 7626 | } |
| 7627 | |
| 7628 | static void |
| 7629 | Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7630 | { |
| 7631 | slotbuf[0] = 0xf016; |
| 7632 | } |
| 7633 | |
| 7634 | static void |
| 7635 | Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7636 | { |
| 7637 | slotbuf[0] = 0xf130; |
| 7638 | } |
| 7639 | |
| 7640 | static void |
| 7641 | Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7642 | { |
| 7643 | slotbuf[0] = 0xf131; |
| 7644 | } |
| 7645 | |
| 7646 | static void |
| 7647 | Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7648 | { |
| 7649 | slotbuf[0] = 0xf116; |
| 7650 | } |
| 7651 | |
| 7652 | static void |
| 7653 | Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7654 | { |
| 7655 | slotbuf[0] = 0xf230; |
| 7656 | } |
| 7657 | |
| 7658 | static void |
| 7659 | Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7660 | { |
| 7661 | slotbuf[0] = 0xf231; |
| 7662 | } |
| 7663 | |
| 7664 | static void |
| 7665 | Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7666 | { |
| 7667 | slotbuf[0] = 0xf216; |
| 7668 | } |
| 7669 | |
| 7670 | static void |
| 7671 | Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7672 | { |
| 7673 | slotbuf[0] = 0x2c0700; |
| 7674 | } |
| 7675 | |
| 7676 | static void |
| 7677 | Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7678 | { |
| 7679 | slotbuf[0] = 0x2e0700; |
| 7680 | } |
| 7681 | |
| 7682 | static void |
| 7683 | Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7684 | { |
| 7685 | slotbuf[0] = 0x2d0700; |
| 7686 | } |
| 7687 | |
| 7688 | static void |
| 7689 | Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7690 | { |
| 7691 | slotbuf[0] = 0x2d0720; |
| 7692 | } |
| 7693 | |
| 7694 | static void |
| 7695 | Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7696 | { |
| 7697 | slotbuf[0] = 0x2d0730; |
| 7698 | } |
| 7699 | |
| 7700 | static void |
| 7701 | Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7702 | { |
| 7703 | slotbuf[0] = 0x2f0700; |
| 7704 | } |
| 7705 | |
| 7706 | static void |
| 7707 | Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7708 | { |
| 7709 | slotbuf[0] = 0x1f; |
| 7710 | } |
| 7711 | |
| 7712 | static void |
| 7713 | Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7714 | { |
| 7715 | slotbuf[0] = 0x21f; |
| 7716 | } |
| 7717 | |
| 7718 | static void |
| 7719 | Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7720 | { |
| 7721 | slotbuf[0] = 0x11f; |
| 7722 | } |
| 7723 | |
| 7724 | static void |
| 7725 | Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7726 | { |
| 7727 | slotbuf[0] = 0x31f; |
| 7728 | } |
| 7729 | |
| 7730 | static void |
| 7731 | Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7732 | { |
| 7733 | slotbuf[0] = 0x240700; |
| 7734 | } |
| 7735 | |
| 7736 | static void |
| 7737 | Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7738 | { |
| 7739 | slotbuf[0] = 0x250700; |
| 7740 | } |
| 7741 | |
| 7742 | static void |
| 7743 | Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7744 | { |
| 7745 | slotbuf[0] = 0x280740; |
| 7746 | } |
| 7747 | |
| 7748 | static void |
| 7749 | Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7750 | { |
| 7751 | slotbuf[0] = 0x280750; |
| 7752 | } |
| 7753 | |
| 7754 | static void |
| 7755 | Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7756 | { |
| 7757 | slotbuf[0] = 0x260700; |
| 7758 | } |
| 7759 | |
| 7760 | static void |
| 7761 | Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7762 | { |
| 7763 | slotbuf[0] = 0x270700; |
| 7764 | } |
| 7765 | |
| 7766 | static void |
| 7767 | Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7768 | { |
| 7769 | slotbuf[0] = 0x200700; |
| 7770 | } |
| 7771 | |
| 7772 | static void |
| 7773 | Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7774 | { |
| 7775 | slotbuf[0] = 0x210700; |
| 7776 | } |
| 7777 | |
| 7778 | static void |
| 7779 | Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7780 | { |
| 7781 | slotbuf[0] = 0x220700; |
| 7782 | } |
| 7783 | |
| 7784 | static void |
| 7785 | Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7786 | { |
| 7787 | slotbuf[0] = 0x230700; |
| 7788 | } |
| 7789 | |
| 7790 | static void |
| 7791 | Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7792 | { |
| 7793 | slotbuf[0] = 0x280700; |
| 7794 | } |
| 7795 | |
| 7796 | static void |
| 7797 | Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7798 | { |
| 7799 | slotbuf[0] = 0x280720; |
| 7800 | } |
| 7801 | |
| 7802 | static void |
| 7803 | Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7804 | { |
| 7805 | slotbuf[0] = 0x280730; |
| 7806 | } |
| 7807 | |
| 7808 | static void |
| 7809 | Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7810 | { |
| 7811 | slotbuf[0] = 0x91f; |
| 7812 | } |
| 7813 | |
| 7814 | static void |
| 7815 | Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7816 | { |
| 7817 | slotbuf[0] = 0x81f; |
| 7818 | } |
| 7819 | |
| 7820 | static void |
| 7821 | Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7822 | { |
| 7823 | slotbuf[0] = 0x5331; |
| 7824 | } |
| 7825 | |
| 7826 | static void |
| 7827 | Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7828 | { |
| 7829 | slotbuf[0] = 0x5330; |
| 7830 | } |
| 7831 | |
| 7832 | static void |
| 7833 | Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7834 | { |
| 7835 | slotbuf[0] = 0x5316; |
| 7836 | } |
| 7837 | |
| 7838 | static void |
| 7839 | Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7840 | { |
| 7841 | slotbuf[0] = 0x5a30; |
| 7842 | } |
| 7843 | |
| 7844 | static void |
| 7845 | Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7846 | { |
| 7847 | slotbuf[0] = 0x5a31; |
| 7848 | } |
| 7849 | |
| 7850 | static void |
| 7851 | Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7852 | { |
| 7853 | slotbuf[0] = 0x5a16; |
| 7854 | } |
| 7855 | |
| 7856 | static void |
| 7857 | Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7858 | { |
| 7859 | slotbuf[0] = 0x5b30; |
| 7860 | } |
| 7861 | |
| 7862 | static void |
| 7863 | Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7864 | { |
| 7865 | slotbuf[0] = 0x5b31; |
| 7866 | } |
| 7867 | |
| 7868 | static void |
| 7869 | Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7870 | { |
| 7871 | slotbuf[0] = 0x5b16; |
| 7872 | } |
| 7873 | |
| 7874 | static void |
| 7875 | Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7876 | { |
| 7877 | slotbuf[0] = 0x5c30; |
| 7878 | } |
| 7879 | |
| 7880 | static void |
| 7881 | Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7882 | { |
| 7883 | slotbuf[0] = 0x5c31; |
| 7884 | } |
| 7885 | |
| 7886 | static void |
| 7887 | Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7888 | { |
| 7889 | slotbuf[0] = 0x5c16; |
| 7890 | } |
| 7891 | |
| 7892 | static void |
| 7893 | Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7894 | { |
| 7895 | slotbuf[0] = 0xc05; |
| 7896 | } |
| 7897 | |
| 7898 | static void |
| 7899 | Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7900 | { |
| 7901 | slotbuf[0] = 0xd05; |
| 7902 | } |
| 7903 | |
| 7904 | static void |
| 7905 | Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7906 | { |
| 7907 | slotbuf[0] = 0xb05; |
| 7908 | } |
| 7909 | |
| 7910 | static void |
| 7911 | Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7912 | { |
| 7913 | slotbuf[0] = 0xf05; |
| 7914 | } |
| 7915 | |
| 7916 | static void |
| 7917 | Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7918 | { |
| 7919 | slotbuf[0] = 0xe05; |
| 7920 | } |
| 7921 | |
| 7922 | static void |
| 7923 | Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7924 | { |
| 7925 | slotbuf[0] = 0x405; |
| 7926 | } |
| 7927 | |
| 7928 | static void |
| 7929 | Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7930 | { |
| 7931 | slotbuf[0] = 0x505; |
| 7932 | } |
| 7933 | |
| 7934 | static void |
| 7935 | Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7936 | { |
| 7937 | slotbuf[0] = 0x305; |
| 7938 | } |
| 7939 | |
| 7940 | static void |
| 7941 | Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7942 | { |
| 7943 | slotbuf[0] = 0x705; |
| 7944 | } |
| 7945 | |
| 7946 | static void |
| 7947 | Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7948 | { |
| 7949 | slotbuf[0] = 0x605; |
| 7950 | } |
| 7951 | |
| 7952 | static void |
| 7953 | Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7954 | { |
| 7955 | slotbuf[0] = 0xf1f; |
| 7956 | } |
| 7957 | |
| 7958 | static void |
| 7959 | Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7960 | { |
| 7961 | slotbuf[0] = 0x105; |
| 7962 | } |
| 7963 | |
| 7964 | static void |
| 7965 | Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7966 | { |
| 7967 | slotbuf[0] = 0x905; |
| 7968 | } |
| 7969 | |
| 7970 | static void |
| 7971 | Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7972 | { |
| 7973 | slotbuf[0] = 0xe030; |
| 7974 | } |
| 7975 | |
| 7976 | static void |
| 7977 | Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7978 | { |
| 7979 | slotbuf[0] = 0xe031; |
| 7980 | } |
| 7981 | |
| 7982 | static void |
| 7983 | Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7984 | { |
| 7985 | slotbuf[0] = 0xe016; |
| 7986 | } |
| 7987 | |
| 7988 | static void |
| 7989 | Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7990 | { |
| 7991 | slotbuf[0] = 0x33; |
| 7992 | } |
| 7993 | |
| 7994 | static void |
| 7995 | Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 7996 | { |
| 7997 | slotbuf[0] = 0x34; |
| 7998 | } |
| 7999 | |
| 8000 | static void |
| 8001 | Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8002 | { |
| 8003 | slotbuf[0] = 0x35; |
| 8004 | } |
| 8005 | |
| 8006 | static void |
| 8007 | Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8008 | { |
| 8009 | slotbuf[0] = 0x36; |
| 8010 | } |
| 8011 | |
| 8012 | static void |
| 8013 | Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8014 | { |
| 8015 | slotbuf[0] = 0x37; |
| 8016 | } |
| 8017 | |
| 8018 | static void |
| 8019 | Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8020 | { |
| 8021 | slotbuf[0] = 0xe04; |
| 8022 | } |
| 8023 | |
| 8024 | static void |
| 8025 | Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8026 | { |
| 8027 | slotbuf[0] = 0xf04; |
| 8028 | } |
| 8029 | |
| 8030 | static void |
| 8031 | Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8032 | { |
| 8033 | slotbuf[0] = 0x32; |
| 8034 | } |
| 8035 | |
| 8036 | static void |
| 8037 | Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8038 | { |
| 8039 | slotbuf[0] = 0x200b00; |
| 8040 | } |
| 8041 | |
| 8042 | static void |
| 8043 | Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8044 | { |
| 8045 | slotbuf[0] = 0x200f00; |
| 8046 | } |
| 8047 | |
| 8048 | static void |
| 8049 | Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8050 | { |
| 8051 | slotbuf[0] = 0x200e00; |
| 8052 | } |
| 8053 | |
| 8054 | static void |
| 8055 | Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8056 | { |
| 8057 | slotbuf[0] = 0xc30; |
| 8058 | } |
| 8059 | |
| 8060 | static void |
| 8061 | Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8062 | { |
| 8063 | slotbuf[0] = 0xc31; |
| 8064 | } |
| 8065 | |
| 8066 | static void |
| 8067 | Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8068 | { |
| 8069 | slotbuf[0] = 0xc16; |
| 8070 | } |
| 8071 | |
| 8072 | static void |
| 8073 | Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8074 | { |
| 8075 | slotbuf[0] = 0x2c; |
| 8076 | } |
| 8077 | |
| 8078 | static void |
| 8079 | Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8080 | { |
| 8081 | slotbuf[0] = 0x2d; |
| 8082 | } |
| 8083 | |
| 8084 | static void |
| 8085 | Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8086 | { |
| 8087 | slotbuf[0] = 0x2e; |
| 8088 | } |
| 8089 | |
| 8090 | static void |
| 8091 | Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8092 | { |
| 8093 | slotbuf[0] = 0x2f; |
| 8094 | } |
| 8095 | |
| 8096 | static void |
| 8097 | Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) |
| 8098 | { |
| 8099 | slotbuf[0] = 0x28; |
| 8100 | } |
| 8101 | |
| 8102 | xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { |
| 8103 | Opcode_excw_Slot_inst_encode, 0, 0 |
| 8104 | }; |
| 8105 | |
| 8106 | xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { |
| 8107 | Opcode_rfe_Slot_inst_encode, 0, 0 |
| 8108 | }; |
| 8109 | |
| 8110 | xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { |
| 8111 | Opcode_rfde_Slot_inst_encode, 0, 0 |
| 8112 | }; |
| 8113 | |
| 8114 | xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { |
| 8115 | Opcode_syscall_Slot_inst_encode, 0, 0 |
| 8116 | }; |
| 8117 | |
| 8118 | xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { |
| 8119 | Opcode_simcall_Slot_inst_encode, 0, 0 |
| 8120 | }; |
| 8121 | |
| 8122 | xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { |
| 8123 | Opcode_call12_Slot_inst_encode, 0, 0 |
| 8124 | }; |
| 8125 | |
| 8126 | xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { |
| 8127 | Opcode_call8_Slot_inst_encode, 0, 0 |
| 8128 | }; |
| 8129 | |
| 8130 | xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { |
| 8131 | Opcode_call4_Slot_inst_encode, 0, 0 |
| 8132 | }; |
| 8133 | |
| 8134 | xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { |
| 8135 | Opcode_callx12_Slot_inst_encode, 0, 0 |
| 8136 | }; |
| 8137 | |
| 8138 | xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { |
| 8139 | Opcode_callx8_Slot_inst_encode, 0, 0 |
| 8140 | }; |
| 8141 | |
| 8142 | xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { |
| 8143 | Opcode_callx4_Slot_inst_encode, 0, 0 |
| 8144 | }; |
| 8145 | |
| 8146 | xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { |
| 8147 | Opcode_entry_Slot_inst_encode, 0, 0 |
| 8148 | }; |
| 8149 | |
| 8150 | xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { |
| 8151 | Opcode_movsp_Slot_inst_encode, 0, 0 |
| 8152 | }; |
| 8153 | |
| 8154 | xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { |
| 8155 | Opcode_rotw_Slot_inst_encode, 0, 0 |
| 8156 | }; |
| 8157 | |
| 8158 | xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { |
| 8159 | Opcode_retw_Slot_inst_encode, 0, 0 |
| 8160 | }; |
| 8161 | |
| 8162 | xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { |
| 8163 | 0, 0, Opcode_retw_n_Slot_inst16b_encode |
| 8164 | }; |
| 8165 | |
| 8166 | xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { |
| 8167 | Opcode_rfwo_Slot_inst_encode, 0, 0 |
| 8168 | }; |
| 8169 | |
| 8170 | xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { |
| 8171 | Opcode_rfwu_Slot_inst_encode, 0, 0 |
| 8172 | }; |
| 8173 | |
| 8174 | xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { |
| 8175 | Opcode_l32e_Slot_inst_encode, 0, 0 |
| 8176 | }; |
| 8177 | |
| 8178 | xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { |
| 8179 | Opcode_s32e_Slot_inst_encode, 0, 0 |
| 8180 | }; |
| 8181 | |
| 8182 | xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { |
| 8183 | Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 |
| 8184 | }; |
| 8185 | |
| 8186 | xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { |
| 8187 | Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 |
| 8188 | }; |
| 8189 | |
| 8190 | xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { |
| 8191 | Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 |
| 8192 | }; |
| 8193 | |
| 8194 | xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { |
| 8195 | Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 |
| 8196 | }; |
| 8197 | |
| 8198 | xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { |
| 8199 | Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 |
| 8200 | }; |
| 8201 | |
| 8202 | xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { |
| 8203 | Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 |
| 8204 | }; |
| 8205 | |
| 8206 | xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { |
| 8207 | 0, Opcode_add_n_Slot_inst16a_encode, 0 |
| 8208 | }; |
| 8209 | |
| 8210 | xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { |
| 8211 | 0, Opcode_addi_n_Slot_inst16a_encode, 0 |
| 8212 | }; |
| 8213 | |
| 8214 | xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { |
| 8215 | 0, 0, Opcode_beqz_n_Slot_inst16b_encode |
| 8216 | }; |
| 8217 | |
| 8218 | xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { |
| 8219 | 0, 0, Opcode_bnez_n_Slot_inst16b_encode |
| 8220 | }; |
| 8221 | |
| 8222 | xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { |
| 8223 | 0, 0, Opcode_ill_n_Slot_inst16b_encode |
| 8224 | }; |
| 8225 | |
| 8226 | xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { |
| 8227 | 0, Opcode_l32i_n_Slot_inst16a_encode, 0 |
| 8228 | }; |
| 8229 | |
| 8230 | xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { |
| 8231 | 0, 0, Opcode_mov_n_Slot_inst16b_encode |
| 8232 | }; |
| 8233 | |
| 8234 | xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { |
| 8235 | 0, 0, Opcode_movi_n_Slot_inst16b_encode |
| 8236 | }; |
| 8237 | |
| 8238 | xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { |
| 8239 | 0, 0, Opcode_nop_n_Slot_inst16b_encode |
| 8240 | }; |
| 8241 | |
| 8242 | xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { |
| 8243 | 0, 0, Opcode_ret_n_Slot_inst16b_encode |
| 8244 | }; |
| 8245 | |
| 8246 | xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { |
| 8247 | 0, Opcode_s32i_n_Slot_inst16a_encode, 0 |
| 8248 | }; |
| 8249 | |
| 8250 | xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { |
| 8251 | Opcode_rur_threadptr_Slot_inst_encode, 0, 0 |
| 8252 | }; |
| 8253 | |
| 8254 | xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { |
| 8255 | Opcode_wur_threadptr_Slot_inst_encode, 0, 0 |
| 8256 | }; |
| 8257 | |
| 8258 | xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { |
| 8259 | Opcode_addi_Slot_inst_encode, 0, 0 |
| 8260 | }; |
| 8261 | |
| 8262 | xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { |
| 8263 | Opcode_addmi_Slot_inst_encode, 0, 0 |
| 8264 | }; |
| 8265 | |
| 8266 | xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { |
| 8267 | Opcode_add_Slot_inst_encode, 0, 0 |
| 8268 | }; |
| 8269 | |
| 8270 | xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { |
| 8271 | Opcode_sub_Slot_inst_encode, 0, 0 |
| 8272 | }; |
| 8273 | |
| 8274 | xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { |
| 8275 | Opcode_addx2_Slot_inst_encode, 0, 0 |
| 8276 | }; |
| 8277 | |
| 8278 | xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { |
| 8279 | Opcode_addx4_Slot_inst_encode, 0, 0 |
| 8280 | }; |
| 8281 | |
| 8282 | xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { |
| 8283 | Opcode_addx8_Slot_inst_encode, 0, 0 |
| 8284 | }; |
| 8285 | |
| 8286 | xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { |
| 8287 | Opcode_subx2_Slot_inst_encode, 0, 0 |
| 8288 | }; |
| 8289 | |
| 8290 | xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { |
| 8291 | Opcode_subx4_Slot_inst_encode, 0, 0 |
| 8292 | }; |
| 8293 | |
| 8294 | xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { |
| 8295 | Opcode_subx8_Slot_inst_encode, 0, 0 |
| 8296 | }; |
| 8297 | |
| 8298 | xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { |
| 8299 | Opcode_and_Slot_inst_encode, 0, 0 |
| 8300 | }; |
| 8301 | |
| 8302 | xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { |
| 8303 | Opcode_or_Slot_inst_encode, 0, 0 |
| 8304 | }; |
| 8305 | |
| 8306 | xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { |
| 8307 | Opcode_xor_Slot_inst_encode, 0, 0 |
| 8308 | }; |
| 8309 | |
| 8310 | xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { |
| 8311 | Opcode_beqi_Slot_inst_encode, 0, 0 |
| 8312 | }; |
| 8313 | |
| 8314 | xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { |
| 8315 | Opcode_bnei_Slot_inst_encode, 0, 0 |
| 8316 | }; |
| 8317 | |
| 8318 | xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { |
| 8319 | Opcode_bgei_Slot_inst_encode, 0, 0 |
| 8320 | }; |
| 8321 | |
| 8322 | xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { |
| 8323 | Opcode_blti_Slot_inst_encode, 0, 0 |
| 8324 | }; |
| 8325 | |
| 8326 | xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { |
| 8327 | Opcode_bbci_Slot_inst_encode, 0, 0 |
| 8328 | }; |
| 8329 | |
| 8330 | xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { |
| 8331 | Opcode_bbsi_Slot_inst_encode, 0, 0 |
| 8332 | }; |
| 8333 | |
| 8334 | xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { |
| 8335 | Opcode_bgeui_Slot_inst_encode, 0, 0 |
| 8336 | }; |
| 8337 | |
| 8338 | xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { |
| 8339 | Opcode_bltui_Slot_inst_encode, 0, 0 |
| 8340 | }; |
| 8341 | |
| 8342 | xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { |
| 8343 | Opcode_beq_Slot_inst_encode, 0, 0 |
| 8344 | }; |
| 8345 | |
| 8346 | xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { |
| 8347 | Opcode_bne_Slot_inst_encode, 0, 0 |
| 8348 | }; |
| 8349 | |
| 8350 | xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { |
| 8351 | Opcode_bge_Slot_inst_encode, 0, 0 |
| 8352 | }; |
| 8353 | |
| 8354 | xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { |
| 8355 | Opcode_blt_Slot_inst_encode, 0, 0 |
| 8356 | }; |
| 8357 | |
| 8358 | xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { |
| 8359 | Opcode_bgeu_Slot_inst_encode, 0, 0 |
| 8360 | }; |
| 8361 | |
| 8362 | xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { |
| 8363 | Opcode_bltu_Slot_inst_encode, 0, 0 |
| 8364 | }; |
| 8365 | |
| 8366 | xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { |
| 8367 | Opcode_bany_Slot_inst_encode, 0, 0 |
| 8368 | }; |
| 8369 | |
| 8370 | xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { |
| 8371 | Opcode_bnone_Slot_inst_encode, 0, 0 |
| 8372 | }; |
| 8373 | |
| 8374 | xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { |
| 8375 | Opcode_ball_Slot_inst_encode, 0, 0 |
| 8376 | }; |
| 8377 | |
| 8378 | xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { |
| 8379 | Opcode_bnall_Slot_inst_encode, 0, 0 |
| 8380 | }; |
| 8381 | |
| 8382 | xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { |
| 8383 | Opcode_bbc_Slot_inst_encode, 0, 0 |
| 8384 | }; |
| 8385 | |
| 8386 | xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { |
| 8387 | Opcode_bbs_Slot_inst_encode, 0, 0 |
| 8388 | }; |
| 8389 | |
| 8390 | xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { |
| 8391 | Opcode_beqz_Slot_inst_encode, 0, 0 |
| 8392 | }; |
| 8393 | |
| 8394 | xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { |
| 8395 | Opcode_bnez_Slot_inst_encode, 0, 0 |
| 8396 | }; |
| 8397 | |
| 8398 | xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { |
| 8399 | Opcode_bgez_Slot_inst_encode, 0, 0 |
| 8400 | }; |
| 8401 | |
| 8402 | xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { |
| 8403 | Opcode_bltz_Slot_inst_encode, 0, 0 |
| 8404 | }; |
| 8405 | |
| 8406 | xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { |
| 8407 | Opcode_call0_Slot_inst_encode, 0, 0 |
| 8408 | }; |
| 8409 | |
| 8410 | xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { |
| 8411 | Opcode_callx0_Slot_inst_encode, 0, 0 |
| 8412 | }; |
| 8413 | |
| 8414 | xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { |
| 8415 | Opcode_extui_Slot_inst_encode, 0, 0 |
| 8416 | }; |
| 8417 | |
| 8418 | xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { |
| 8419 | Opcode_ill_Slot_inst_encode, 0, 0 |
| 8420 | }; |
| 8421 | |
| 8422 | xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { |
| 8423 | Opcode_j_Slot_inst_encode, 0, 0 |
| 8424 | }; |
| 8425 | |
| 8426 | xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { |
| 8427 | Opcode_jx_Slot_inst_encode, 0, 0 |
| 8428 | }; |
| 8429 | |
| 8430 | xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { |
| 8431 | Opcode_l16ui_Slot_inst_encode, 0, 0 |
| 8432 | }; |
| 8433 | |
| 8434 | xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { |
| 8435 | Opcode_l16si_Slot_inst_encode, 0, 0 |
| 8436 | }; |
| 8437 | |
| 8438 | xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { |
| 8439 | Opcode_l32i_Slot_inst_encode, 0, 0 |
| 8440 | }; |
| 8441 | |
| 8442 | xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { |
| 8443 | Opcode_l32r_Slot_inst_encode, 0, 0 |
| 8444 | }; |
| 8445 | |
| 8446 | xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { |
| 8447 | Opcode_l8ui_Slot_inst_encode, 0, 0 |
| 8448 | }; |
| 8449 | |
| 8450 | xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { |
| 8451 | Opcode_loop_Slot_inst_encode, 0, 0 |
| 8452 | }; |
| 8453 | |
| 8454 | xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { |
| 8455 | Opcode_loopnez_Slot_inst_encode, 0, 0 |
| 8456 | }; |
| 8457 | |
| 8458 | xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { |
| 8459 | Opcode_loopgtz_Slot_inst_encode, 0, 0 |
| 8460 | }; |
| 8461 | |
| 8462 | xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { |
| 8463 | Opcode_movi_Slot_inst_encode, 0, 0 |
| 8464 | }; |
| 8465 | |
| 8466 | xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { |
| 8467 | Opcode_moveqz_Slot_inst_encode, 0, 0 |
| 8468 | }; |
| 8469 | |
| 8470 | xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { |
| 8471 | Opcode_movnez_Slot_inst_encode, 0, 0 |
| 8472 | }; |
| 8473 | |
| 8474 | xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { |
| 8475 | Opcode_movltz_Slot_inst_encode, 0, 0 |
| 8476 | }; |
| 8477 | |
| 8478 | xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { |
| 8479 | Opcode_movgez_Slot_inst_encode, 0, 0 |
| 8480 | }; |
| 8481 | |
| 8482 | xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { |
| 8483 | Opcode_neg_Slot_inst_encode, 0, 0 |
| 8484 | }; |
| 8485 | |
| 8486 | xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { |
| 8487 | Opcode_abs_Slot_inst_encode, 0, 0 |
| 8488 | }; |
| 8489 | |
| 8490 | xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { |
| 8491 | Opcode_nop_Slot_inst_encode, 0, 0 |
| 8492 | }; |
| 8493 | |
| 8494 | xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { |
| 8495 | Opcode_ret_Slot_inst_encode, 0, 0 |
| 8496 | }; |
| 8497 | |
| 8498 | xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { |
| 8499 | Opcode_s16i_Slot_inst_encode, 0, 0 |
| 8500 | }; |
| 8501 | |
| 8502 | xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { |
| 8503 | Opcode_s32i_Slot_inst_encode, 0, 0 |
| 8504 | }; |
| 8505 | |
| 8506 | xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { |
| 8507 | Opcode_s8i_Slot_inst_encode, 0, 0 |
| 8508 | }; |
| 8509 | |
| 8510 | xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { |
| 8511 | Opcode_ssr_Slot_inst_encode, 0, 0 |
| 8512 | }; |
| 8513 | |
| 8514 | xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { |
| 8515 | Opcode_ssl_Slot_inst_encode, 0, 0 |
| 8516 | }; |
| 8517 | |
| 8518 | xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { |
| 8519 | Opcode_ssa8l_Slot_inst_encode, 0, 0 |
| 8520 | }; |
| 8521 | |
| 8522 | xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { |
| 8523 | Opcode_ssa8b_Slot_inst_encode, 0, 0 |
| 8524 | }; |
| 8525 | |
| 8526 | xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { |
| 8527 | Opcode_ssai_Slot_inst_encode, 0, 0 |
| 8528 | }; |
| 8529 | |
| 8530 | xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { |
| 8531 | Opcode_sll_Slot_inst_encode, 0, 0 |
| 8532 | }; |
| 8533 | |
| 8534 | xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { |
| 8535 | Opcode_src_Slot_inst_encode, 0, 0 |
| 8536 | }; |
| 8537 | |
| 8538 | xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { |
| 8539 | Opcode_srl_Slot_inst_encode, 0, 0 |
| 8540 | }; |
| 8541 | |
| 8542 | xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { |
| 8543 | Opcode_sra_Slot_inst_encode, 0, 0 |
| 8544 | }; |
| 8545 | |
| 8546 | xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { |
| 8547 | Opcode_slli_Slot_inst_encode, 0, 0 |
| 8548 | }; |
| 8549 | |
| 8550 | xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { |
| 8551 | Opcode_srai_Slot_inst_encode, 0, 0 |
| 8552 | }; |
| 8553 | |
| 8554 | xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { |
| 8555 | Opcode_srli_Slot_inst_encode, 0, 0 |
| 8556 | }; |
| 8557 | |
| 8558 | xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { |
| 8559 | Opcode_memw_Slot_inst_encode, 0, 0 |
| 8560 | }; |
| 8561 | |
| 8562 | xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { |
| 8563 | Opcode_extw_Slot_inst_encode, 0, 0 |
| 8564 | }; |
| 8565 | |
| 8566 | xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { |
| 8567 | Opcode_isync_Slot_inst_encode, 0, 0 |
| 8568 | }; |
| 8569 | |
| 8570 | xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { |
| 8571 | Opcode_rsync_Slot_inst_encode, 0, 0 |
| 8572 | }; |
| 8573 | |
| 8574 | xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { |
| 8575 | Opcode_esync_Slot_inst_encode, 0, 0 |
| 8576 | }; |
| 8577 | |
| 8578 | xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { |
| 8579 | Opcode_dsync_Slot_inst_encode, 0, 0 |
| 8580 | }; |
| 8581 | |
| 8582 | xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { |
| 8583 | Opcode_rsil_Slot_inst_encode, 0, 0 |
| 8584 | }; |
| 8585 | |
| 8586 | xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { |
| 8587 | Opcode_rsr_lend_Slot_inst_encode, 0, 0 |
| 8588 | }; |
| 8589 | |
| 8590 | xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { |
| 8591 | Opcode_wsr_lend_Slot_inst_encode, 0, 0 |
| 8592 | }; |
| 8593 | |
| 8594 | xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { |
| 8595 | Opcode_xsr_lend_Slot_inst_encode, 0, 0 |
| 8596 | }; |
| 8597 | |
| 8598 | xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { |
| 8599 | Opcode_rsr_lcount_Slot_inst_encode, 0, 0 |
| 8600 | }; |
| 8601 | |
| 8602 | xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { |
| 8603 | Opcode_wsr_lcount_Slot_inst_encode, 0, 0 |
| 8604 | }; |
| 8605 | |
| 8606 | xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { |
| 8607 | Opcode_xsr_lcount_Slot_inst_encode, 0, 0 |
| 8608 | }; |
| 8609 | |
| 8610 | xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { |
| 8611 | Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 |
| 8612 | }; |
| 8613 | |
| 8614 | xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { |
| 8615 | Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 |
| 8616 | }; |
| 8617 | |
| 8618 | xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { |
| 8619 | Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 |
| 8620 | }; |
| 8621 | |
| 8622 | xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { |
| 8623 | Opcode_rsr_sar_Slot_inst_encode, 0, 0 |
| 8624 | }; |
| 8625 | |
| 8626 | xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { |
| 8627 | Opcode_wsr_sar_Slot_inst_encode, 0, 0 |
| 8628 | }; |
| 8629 | |
| 8630 | xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { |
| 8631 | Opcode_xsr_sar_Slot_inst_encode, 0, 0 |
| 8632 | }; |
| 8633 | |
| 8634 | xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { |
| 8635 | Opcode_rsr_litbase_Slot_inst_encode, 0, 0 |
| 8636 | }; |
| 8637 | |
| 8638 | xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { |
| 8639 | Opcode_wsr_litbase_Slot_inst_encode, 0, 0 |
| 8640 | }; |
| 8641 | |
| 8642 | xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { |
| 8643 | Opcode_xsr_litbase_Slot_inst_encode, 0, 0 |
| 8644 | }; |
| 8645 | |
| 8646 | xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { |
| 8647 | Opcode_rsr_176_Slot_inst_encode, 0, 0 |
| 8648 | }; |
| 8649 | |
| 8650 | xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { |
| 8651 | Opcode_wsr_176_Slot_inst_encode, 0, 0 |
| 8652 | }; |
| 8653 | |
| 8654 | xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { |
| 8655 | Opcode_rsr_208_Slot_inst_encode, 0, 0 |
| 8656 | }; |
| 8657 | |
| 8658 | xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { |
| 8659 | Opcode_rsr_ps_Slot_inst_encode, 0, 0 |
| 8660 | }; |
| 8661 | |
| 8662 | xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { |
| 8663 | Opcode_wsr_ps_Slot_inst_encode, 0, 0 |
| 8664 | }; |
| 8665 | |
| 8666 | xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { |
| 8667 | Opcode_xsr_ps_Slot_inst_encode, 0, 0 |
| 8668 | }; |
| 8669 | |
| 8670 | xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { |
| 8671 | Opcode_rsr_epc1_Slot_inst_encode, 0, 0 |
| 8672 | }; |
| 8673 | |
| 8674 | xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { |
| 8675 | Opcode_wsr_epc1_Slot_inst_encode, 0, 0 |
| 8676 | }; |
| 8677 | |
| 8678 | xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { |
| 8679 | Opcode_xsr_epc1_Slot_inst_encode, 0, 0 |
| 8680 | }; |
| 8681 | |
| 8682 | xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { |
| 8683 | Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 |
| 8684 | }; |
| 8685 | |
| 8686 | xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { |
| 8687 | Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 |
| 8688 | }; |
| 8689 | |
| 8690 | xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { |
| 8691 | Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 |
| 8692 | }; |
| 8693 | |
| 8694 | xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { |
| 8695 | Opcode_rsr_epc2_Slot_inst_encode, 0, 0 |
| 8696 | }; |
| 8697 | |
| 8698 | xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { |
| 8699 | Opcode_wsr_epc2_Slot_inst_encode, 0, 0 |
| 8700 | }; |
| 8701 | |
| 8702 | xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { |
| 8703 | Opcode_xsr_epc2_Slot_inst_encode, 0, 0 |
| 8704 | }; |
| 8705 | |
| 8706 | xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { |
| 8707 | Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 |
| 8708 | }; |
| 8709 | |
| 8710 | xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { |
| 8711 | Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 |
| 8712 | }; |
| 8713 | |
| 8714 | xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { |
| 8715 | Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 |
| 8716 | }; |
| 8717 | |
| 8718 | xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { |
| 8719 | Opcode_rsr_epc3_Slot_inst_encode, 0, 0 |
| 8720 | }; |
| 8721 | |
| 8722 | xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { |
| 8723 | Opcode_wsr_epc3_Slot_inst_encode, 0, 0 |
| 8724 | }; |
| 8725 | |
| 8726 | xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { |
| 8727 | Opcode_xsr_epc3_Slot_inst_encode, 0, 0 |
| 8728 | }; |
| 8729 | |
| 8730 | xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { |
| 8731 | Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 |
| 8732 | }; |
| 8733 | |
| 8734 | xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { |
| 8735 | Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 |
| 8736 | }; |
| 8737 | |
| 8738 | xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { |
| 8739 | Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 |
| 8740 | }; |
| 8741 | |
| 8742 | xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { |
| 8743 | Opcode_rsr_epc4_Slot_inst_encode, 0, 0 |
| 8744 | }; |
| 8745 | |
| 8746 | xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { |
| 8747 | Opcode_wsr_epc4_Slot_inst_encode, 0, 0 |
| 8748 | }; |
| 8749 | |
| 8750 | xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { |
| 8751 | Opcode_xsr_epc4_Slot_inst_encode, 0, 0 |
| 8752 | }; |
| 8753 | |
| 8754 | xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { |
| 8755 | Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 |
| 8756 | }; |
| 8757 | |
| 8758 | xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { |
| 8759 | Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 |
| 8760 | }; |
| 8761 | |
| 8762 | xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { |
| 8763 | Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 |
| 8764 | }; |
| 8765 | |
| 8766 | xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { |
| 8767 | Opcode_rsr_epc5_Slot_inst_encode, 0, 0 |
| 8768 | }; |
| 8769 | |
| 8770 | xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { |
| 8771 | Opcode_wsr_epc5_Slot_inst_encode, 0, 0 |
| 8772 | }; |
| 8773 | |
| 8774 | xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { |
| 8775 | Opcode_xsr_epc5_Slot_inst_encode, 0, 0 |
| 8776 | }; |
| 8777 | |
| 8778 | xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { |
| 8779 | Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 |
| 8780 | }; |
| 8781 | |
| 8782 | xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { |
| 8783 | Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 |
| 8784 | }; |
| 8785 | |
| 8786 | xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { |
| 8787 | Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 |
| 8788 | }; |
| 8789 | |
| 8790 | xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { |
| 8791 | Opcode_rsr_epc6_Slot_inst_encode, 0, 0 |
| 8792 | }; |
| 8793 | |
| 8794 | xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { |
| 8795 | Opcode_wsr_epc6_Slot_inst_encode, 0, 0 |
| 8796 | }; |
| 8797 | |
| 8798 | xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { |
| 8799 | Opcode_xsr_epc6_Slot_inst_encode, 0, 0 |
| 8800 | }; |
| 8801 | |
| 8802 | xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { |
| 8803 | Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 |
| 8804 | }; |
| 8805 | |
| 8806 | xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { |
| 8807 | Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 |
| 8808 | }; |
| 8809 | |
| 8810 | xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { |
| 8811 | Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 |
| 8812 | }; |
| 8813 | |
| 8814 | xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { |
| 8815 | Opcode_rsr_epc7_Slot_inst_encode, 0, 0 |
| 8816 | }; |
| 8817 | |
| 8818 | xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { |
| 8819 | Opcode_wsr_epc7_Slot_inst_encode, 0, 0 |
| 8820 | }; |
| 8821 | |
| 8822 | xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { |
| 8823 | Opcode_xsr_epc7_Slot_inst_encode, 0, 0 |
| 8824 | }; |
| 8825 | |
| 8826 | xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { |
| 8827 | Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 |
| 8828 | }; |
| 8829 | |
| 8830 | xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { |
| 8831 | Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 |
| 8832 | }; |
| 8833 | |
| 8834 | xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { |
| 8835 | Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 |
| 8836 | }; |
| 8837 | |
| 8838 | xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { |
| 8839 | Opcode_rsr_eps2_Slot_inst_encode, 0, 0 |
| 8840 | }; |
| 8841 | |
| 8842 | xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { |
| 8843 | Opcode_wsr_eps2_Slot_inst_encode, 0, 0 |
| 8844 | }; |
| 8845 | |
| 8846 | xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { |
| 8847 | Opcode_xsr_eps2_Slot_inst_encode, 0, 0 |
| 8848 | }; |
| 8849 | |
| 8850 | xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { |
| 8851 | Opcode_rsr_eps3_Slot_inst_encode, 0, 0 |
| 8852 | }; |
| 8853 | |
| 8854 | xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { |
| 8855 | Opcode_wsr_eps3_Slot_inst_encode, 0, 0 |
| 8856 | }; |
| 8857 | |
| 8858 | xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { |
| 8859 | Opcode_xsr_eps3_Slot_inst_encode, 0, 0 |
| 8860 | }; |
| 8861 | |
| 8862 | xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { |
| 8863 | Opcode_rsr_eps4_Slot_inst_encode, 0, 0 |
| 8864 | }; |
| 8865 | |
| 8866 | xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { |
| 8867 | Opcode_wsr_eps4_Slot_inst_encode, 0, 0 |
| 8868 | }; |
| 8869 | |
| 8870 | xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { |
| 8871 | Opcode_xsr_eps4_Slot_inst_encode, 0, 0 |
| 8872 | }; |
| 8873 | |
| 8874 | xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { |
| 8875 | Opcode_rsr_eps5_Slot_inst_encode, 0, 0 |
| 8876 | }; |
| 8877 | |
| 8878 | xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { |
| 8879 | Opcode_wsr_eps5_Slot_inst_encode, 0, 0 |
| 8880 | }; |
| 8881 | |
| 8882 | xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { |
| 8883 | Opcode_xsr_eps5_Slot_inst_encode, 0, 0 |
| 8884 | }; |
| 8885 | |
| 8886 | xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { |
| 8887 | Opcode_rsr_eps6_Slot_inst_encode, 0, 0 |
| 8888 | }; |
| 8889 | |
| 8890 | xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { |
| 8891 | Opcode_wsr_eps6_Slot_inst_encode, 0, 0 |
| 8892 | }; |
| 8893 | |
| 8894 | xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { |
| 8895 | Opcode_xsr_eps6_Slot_inst_encode, 0, 0 |
| 8896 | }; |
| 8897 | |
| 8898 | xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { |
| 8899 | Opcode_rsr_eps7_Slot_inst_encode, 0, 0 |
| 8900 | }; |
| 8901 | |
| 8902 | xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { |
| 8903 | Opcode_wsr_eps7_Slot_inst_encode, 0, 0 |
| 8904 | }; |
| 8905 | |
| 8906 | xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { |
| 8907 | Opcode_xsr_eps7_Slot_inst_encode, 0, 0 |
| 8908 | }; |
| 8909 | |
| 8910 | xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { |
| 8911 | Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 |
| 8912 | }; |
| 8913 | |
| 8914 | xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { |
| 8915 | Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 |
| 8916 | }; |
| 8917 | |
| 8918 | xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { |
| 8919 | Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 |
| 8920 | }; |
| 8921 | |
| 8922 | xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { |
| 8923 | Opcode_rsr_depc_Slot_inst_encode, 0, 0 |
| 8924 | }; |
| 8925 | |
| 8926 | xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { |
| 8927 | Opcode_wsr_depc_Slot_inst_encode, 0, 0 |
| 8928 | }; |
| 8929 | |
| 8930 | xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { |
| 8931 | Opcode_xsr_depc_Slot_inst_encode, 0, 0 |
| 8932 | }; |
| 8933 | |
| 8934 | xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { |
| 8935 | Opcode_rsr_exccause_Slot_inst_encode, 0, 0 |
| 8936 | }; |
| 8937 | |
| 8938 | xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { |
| 8939 | Opcode_wsr_exccause_Slot_inst_encode, 0, 0 |
| 8940 | }; |
| 8941 | |
| 8942 | xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { |
| 8943 | Opcode_xsr_exccause_Slot_inst_encode, 0, 0 |
| 8944 | }; |
| 8945 | |
| 8946 | xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { |
| 8947 | Opcode_rsr_misc0_Slot_inst_encode, 0, 0 |
| 8948 | }; |
| 8949 | |
| 8950 | xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { |
| 8951 | Opcode_wsr_misc0_Slot_inst_encode, 0, 0 |
| 8952 | }; |
| 8953 | |
| 8954 | xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { |
| 8955 | Opcode_xsr_misc0_Slot_inst_encode, 0, 0 |
| 8956 | }; |
| 8957 | |
| 8958 | xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { |
| 8959 | Opcode_rsr_misc1_Slot_inst_encode, 0, 0 |
| 8960 | }; |
| 8961 | |
| 8962 | xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { |
| 8963 | Opcode_wsr_misc1_Slot_inst_encode, 0, 0 |
| 8964 | }; |
| 8965 | |
| 8966 | xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { |
| 8967 | Opcode_xsr_misc1_Slot_inst_encode, 0, 0 |
| 8968 | }; |
| 8969 | |
| 8970 | xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { |
| 8971 | Opcode_rsr_prid_Slot_inst_encode, 0, 0 |
| 8972 | }; |
| 8973 | |
| 8974 | xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { |
| 8975 | Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 |
| 8976 | }; |
| 8977 | |
| 8978 | xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { |
| 8979 | Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 |
| 8980 | }; |
| 8981 | |
| 8982 | xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { |
| 8983 | Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 |
| 8984 | }; |
| 8985 | |
| 8986 | xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { |
| 8987 | Opcode_mul16u_Slot_inst_encode, 0, 0 |
| 8988 | }; |
| 8989 | |
| 8990 | xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { |
| 8991 | Opcode_mul16s_Slot_inst_encode, 0, 0 |
| 8992 | }; |
| 8993 | |
| 8994 | xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { |
| 8995 | Opcode_rfi_Slot_inst_encode, 0, 0 |
| 8996 | }; |
| 8997 | |
| 8998 | xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { |
| 8999 | Opcode_waiti_Slot_inst_encode, 0, 0 |
| 9000 | }; |
| 9001 | |
| 9002 | xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { |
| 9003 | Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 |
| 9004 | }; |
| 9005 | |
| 9006 | xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { |
| 9007 | Opcode_wsr_intset_Slot_inst_encode, 0, 0 |
| 9008 | }; |
| 9009 | |
| 9010 | xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { |
| 9011 | Opcode_wsr_intclear_Slot_inst_encode, 0, 0 |
| 9012 | }; |
| 9013 | |
| 9014 | xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { |
| 9015 | Opcode_rsr_intenable_Slot_inst_encode, 0, 0 |
| 9016 | }; |
| 9017 | |
| 9018 | xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { |
| 9019 | Opcode_wsr_intenable_Slot_inst_encode, 0, 0 |
| 9020 | }; |
| 9021 | |
| 9022 | xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { |
| 9023 | Opcode_xsr_intenable_Slot_inst_encode, 0, 0 |
| 9024 | }; |
| 9025 | |
| 9026 | xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { |
| 9027 | Opcode_break_Slot_inst_encode, 0, 0 |
| 9028 | }; |
| 9029 | |
| 9030 | xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { |
| 9031 | 0, 0, Opcode_break_n_Slot_inst16b_encode |
| 9032 | }; |
| 9033 | |
| 9034 | xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { |
| 9035 | Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 |
| 9036 | }; |
| 9037 | |
| 9038 | xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { |
| 9039 | Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 |
| 9040 | }; |
| 9041 | |
| 9042 | xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { |
| 9043 | Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 |
| 9044 | }; |
| 9045 | |
| 9046 | xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { |
| 9047 | Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 |
| 9048 | }; |
| 9049 | |
| 9050 | xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { |
| 9051 | Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 |
| 9052 | }; |
| 9053 | |
| 9054 | xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { |
| 9055 | Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 |
| 9056 | }; |
| 9057 | |
| 9058 | xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { |
| 9059 | Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 |
| 9060 | }; |
| 9061 | |
| 9062 | xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { |
| 9063 | Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 |
| 9064 | }; |
| 9065 | |
| 9066 | xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { |
| 9067 | Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 |
| 9068 | }; |
| 9069 | |
| 9070 | xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { |
| 9071 | Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 |
| 9072 | }; |
| 9073 | |
| 9074 | xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { |
| 9075 | Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 |
| 9076 | }; |
| 9077 | |
| 9078 | xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { |
| 9079 | Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 |
| 9080 | }; |
| 9081 | |
| 9082 | xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { |
| 9083 | Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 |
| 9084 | }; |
| 9085 | |
| 9086 | xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { |
| 9087 | Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 |
| 9088 | }; |
| 9089 | |
| 9090 | xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { |
| 9091 | Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 |
| 9092 | }; |
| 9093 | |
| 9094 | xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { |
| 9095 | Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 |
| 9096 | }; |
| 9097 | |
| 9098 | xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { |
| 9099 | Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 |
| 9100 | }; |
| 9101 | |
| 9102 | xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { |
| 9103 | Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 |
| 9104 | }; |
| 9105 | |
| 9106 | xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { |
| 9107 | Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 |
| 9108 | }; |
| 9109 | |
| 9110 | xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { |
| 9111 | Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 |
| 9112 | }; |
| 9113 | |
| 9114 | xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { |
| 9115 | Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 |
| 9116 | }; |
| 9117 | |
| 9118 | xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { |
| 9119 | Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 |
| 9120 | }; |
| 9121 | |
| 9122 | xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { |
| 9123 | Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 |
| 9124 | }; |
| 9125 | |
| 9126 | xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { |
| 9127 | Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 |
| 9128 | }; |
| 9129 | |
| 9130 | xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { |
| 9131 | Opcode_rsr_icount_Slot_inst_encode, 0, 0 |
| 9132 | }; |
| 9133 | |
| 9134 | xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { |
| 9135 | Opcode_wsr_icount_Slot_inst_encode, 0, 0 |
| 9136 | }; |
| 9137 | |
| 9138 | xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { |
| 9139 | Opcode_xsr_icount_Slot_inst_encode, 0, 0 |
| 9140 | }; |
| 9141 | |
| 9142 | xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { |
| 9143 | Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 |
| 9144 | }; |
| 9145 | |
| 9146 | xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { |
| 9147 | Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 |
| 9148 | }; |
| 9149 | |
| 9150 | xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { |
| 9151 | Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 |
| 9152 | }; |
| 9153 | |
| 9154 | xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { |
| 9155 | Opcode_rsr_ddr_Slot_inst_encode, 0, 0 |
| 9156 | }; |
| 9157 | |
| 9158 | xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { |
| 9159 | Opcode_wsr_ddr_Slot_inst_encode, 0, 0 |
| 9160 | }; |
| 9161 | |
| 9162 | xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { |
| 9163 | Opcode_xsr_ddr_Slot_inst_encode, 0, 0 |
| 9164 | }; |
| 9165 | |
| 9166 | xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { |
| 9167 | Opcode_rfdo_Slot_inst_encode, 0, 0 |
| 9168 | }; |
| 9169 | |
| 9170 | xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { |
| 9171 | Opcode_rfdd_Slot_inst_encode, 0, 0 |
| 9172 | }; |
| 9173 | |
| 9174 | xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { |
| 9175 | Opcode_wsr_mmid_Slot_inst_encode, 0, 0 |
| 9176 | }; |
| 9177 | |
| 9178 | xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { |
| 9179 | Opcode_rsr_ccount_Slot_inst_encode, 0, 0 |
| 9180 | }; |
| 9181 | |
| 9182 | xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { |
| 9183 | Opcode_wsr_ccount_Slot_inst_encode, 0, 0 |
| 9184 | }; |
| 9185 | |
| 9186 | xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { |
| 9187 | Opcode_xsr_ccount_Slot_inst_encode, 0, 0 |
| 9188 | }; |
| 9189 | |
| 9190 | xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { |
| 9191 | Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 |
| 9192 | }; |
| 9193 | |
| 9194 | xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { |
| 9195 | Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 |
| 9196 | }; |
| 9197 | |
| 9198 | xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { |
| 9199 | Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 |
| 9200 | }; |
| 9201 | |
| 9202 | xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { |
| 9203 | Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 |
| 9204 | }; |
| 9205 | |
| 9206 | xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { |
| 9207 | Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 |
| 9208 | }; |
| 9209 | |
| 9210 | xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { |
| 9211 | Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 |
| 9212 | }; |
| 9213 | |
| 9214 | xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { |
| 9215 | Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 |
| 9216 | }; |
| 9217 | |
| 9218 | xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { |
| 9219 | Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 |
| 9220 | }; |
| 9221 | |
| 9222 | xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { |
| 9223 | Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 |
| 9224 | }; |
| 9225 | |
| 9226 | xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { |
| 9227 | Opcode_ipf_Slot_inst_encode, 0, 0 |
| 9228 | }; |
| 9229 | |
| 9230 | xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { |
| 9231 | Opcode_ihi_Slot_inst_encode, 0, 0 |
| 9232 | }; |
| 9233 | |
| 9234 | xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { |
| 9235 | Opcode_ipfl_Slot_inst_encode, 0, 0 |
| 9236 | }; |
| 9237 | |
| 9238 | xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { |
| 9239 | Opcode_ihu_Slot_inst_encode, 0, 0 |
| 9240 | }; |
| 9241 | |
| 9242 | xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { |
| 9243 | Opcode_iiu_Slot_inst_encode, 0, 0 |
| 9244 | }; |
| 9245 | |
| 9246 | xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { |
| 9247 | Opcode_iii_Slot_inst_encode, 0, 0 |
| 9248 | }; |
| 9249 | |
| 9250 | xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { |
| 9251 | Opcode_lict_Slot_inst_encode, 0, 0 |
| 9252 | }; |
| 9253 | |
| 9254 | xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { |
| 9255 | Opcode_licw_Slot_inst_encode, 0, 0 |
| 9256 | }; |
| 9257 | |
| 9258 | xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { |
| 9259 | Opcode_sict_Slot_inst_encode, 0, 0 |
| 9260 | }; |
| 9261 | |
| 9262 | xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { |
| 9263 | Opcode_sicw_Slot_inst_encode, 0, 0 |
| 9264 | }; |
| 9265 | |
| 9266 | xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { |
| 9267 | Opcode_dhwb_Slot_inst_encode, 0, 0 |
| 9268 | }; |
| 9269 | |
| 9270 | xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { |
| 9271 | Opcode_dhwbi_Slot_inst_encode, 0, 0 |
| 9272 | }; |
| 9273 | |
| 9274 | xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { |
| 9275 | Opcode_diwb_Slot_inst_encode, 0, 0 |
| 9276 | }; |
| 9277 | |
| 9278 | xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { |
| 9279 | Opcode_diwbi_Slot_inst_encode, 0, 0 |
| 9280 | }; |
| 9281 | |
| 9282 | xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { |
| 9283 | Opcode_dhi_Slot_inst_encode, 0, 0 |
| 9284 | }; |
| 9285 | |
| 9286 | xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { |
| 9287 | Opcode_dii_Slot_inst_encode, 0, 0 |
| 9288 | }; |
| 9289 | |
| 9290 | xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { |
| 9291 | Opcode_dpfr_Slot_inst_encode, 0, 0 |
| 9292 | }; |
| 9293 | |
| 9294 | xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { |
| 9295 | Opcode_dpfw_Slot_inst_encode, 0, 0 |
| 9296 | }; |
| 9297 | |
| 9298 | xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { |
| 9299 | Opcode_dpfro_Slot_inst_encode, 0, 0 |
| 9300 | }; |
| 9301 | |
| 9302 | xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { |
| 9303 | Opcode_dpfwo_Slot_inst_encode, 0, 0 |
| 9304 | }; |
| 9305 | |
| 9306 | xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { |
| 9307 | Opcode_dpfl_Slot_inst_encode, 0, 0 |
| 9308 | }; |
| 9309 | |
| 9310 | xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { |
| 9311 | Opcode_dhu_Slot_inst_encode, 0, 0 |
| 9312 | }; |
| 9313 | |
| 9314 | xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { |
| 9315 | Opcode_diu_Slot_inst_encode, 0, 0 |
| 9316 | }; |
| 9317 | |
| 9318 | xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { |
| 9319 | Opcode_sdct_Slot_inst_encode, 0, 0 |
| 9320 | }; |
| 9321 | |
| 9322 | xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { |
| 9323 | Opcode_ldct_Slot_inst_encode, 0, 0 |
| 9324 | }; |
| 9325 | |
| 9326 | xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { |
| 9327 | Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 |
| 9328 | }; |
| 9329 | |
| 9330 | xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { |
| 9331 | Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 |
| 9332 | }; |
| 9333 | |
| 9334 | xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { |
| 9335 | Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 |
| 9336 | }; |
| 9337 | |
| 9338 | xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { |
| 9339 | Opcode_rsr_rasid_Slot_inst_encode, 0, 0 |
| 9340 | }; |
| 9341 | |
| 9342 | xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { |
| 9343 | Opcode_wsr_rasid_Slot_inst_encode, 0, 0 |
| 9344 | }; |
| 9345 | |
| 9346 | xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { |
| 9347 | Opcode_xsr_rasid_Slot_inst_encode, 0, 0 |
| 9348 | }; |
| 9349 | |
| 9350 | xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { |
| 9351 | Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 |
| 9352 | }; |
| 9353 | |
| 9354 | xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { |
| 9355 | Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 |
| 9356 | }; |
| 9357 | |
| 9358 | xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { |
| 9359 | Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 |
| 9360 | }; |
| 9361 | |
| 9362 | xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { |
| 9363 | Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 |
| 9364 | }; |
| 9365 | |
| 9366 | xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { |
| 9367 | Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 |
| 9368 | }; |
| 9369 | |
| 9370 | xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { |
| 9371 | Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 |
| 9372 | }; |
| 9373 | |
| 9374 | xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { |
| 9375 | Opcode_idtlb_Slot_inst_encode, 0, 0 |
| 9376 | }; |
| 9377 | |
| 9378 | xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { |
| 9379 | Opcode_pdtlb_Slot_inst_encode, 0, 0 |
| 9380 | }; |
| 9381 | |
| 9382 | xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { |
| 9383 | Opcode_rdtlb0_Slot_inst_encode, 0, 0 |
| 9384 | }; |
| 9385 | |
| 9386 | xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { |
| 9387 | Opcode_rdtlb1_Slot_inst_encode, 0, 0 |
| 9388 | }; |
| 9389 | |
| 9390 | xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { |
| 9391 | Opcode_wdtlb_Slot_inst_encode, 0, 0 |
| 9392 | }; |
| 9393 | |
| 9394 | xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { |
| 9395 | Opcode_iitlb_Slot_inst_encode, 0, 0 |
| 9396 | }; |
| 9397 | |
| 9398 | xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { |
| 9399 | Opcode_pitlb_Slot_inst_encode, 0, 0 |
| 9400 | }; |
| 9401 | |
| 9402 | xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { |
| 9403 | Opcode_ritlb0_Slot_inst_encode, 0, 0 |
| 9404 | }; |
| 9405 | |
| 9406 | xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { |
| 9407 | Opcode_ritlb1_Slot_inst_encode, 0, 0 |
| 9408 | }; |
| 9409 | |
| 9410 | xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { |
| 9411 | Opcode_witlb_Slot_inst_encode, 0, 0 |
| 9412 | }; |
| 9413 | |
| 9414 | xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { |
| 9415 | Opcode_ldpte_Slot_inst_encode, 0, 0 |
| 9416 | }; |
| 9417 | |
| 9418 | xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { |
| 9419 | Opcode_hwwitlba_Slot_inst_encode, 0, 0 |
| 9420 | }; |
| 9421 | |
| 9422 | xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { |
| 9423 | Opcode_hwwdtlba_Slot_inst_encode, 0, 0 |
| 9424 | }; |
| 9425 | |
| 9426 | xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { |
| 9427 | Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 |
| 9428 | }; |
| 9429 | |
| 9430 | xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { |
| 9431 | Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 |
| 9432 | }; |
| 9433 | |
| 9434 | xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { |
| 9435 | Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 |
| 9436 | }; |
| 9437 | |
| 9438 | xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { |
| 9439 | Opcode_clamps_Slot_inst_encode, 0, 0 |
| 9440 | }; |
| 9441 | |
| 9442 | xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { |
| 9443 | Opcode_min_Slot_inst_encode, 0, 0 |
| 9444 | }; |
| 9445 | |
| 9446 | xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { |
| 9447 | Opcode_max_Slot_inst_encode, 0, 0 |
| 9448 | }; |
| 9449 | |
| 9450 | xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { |
| 9451 | Opcode_minu_Slot_inst_encode, 0, 0 |
| 9452 | }; |
| 9453 | |
| 9454 | xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { |
| 9455 | Opcode_maxu_Slot_inst_encode, 0, 0 |
| 9456 | }; |
| 9457 | |
| 9458 | xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { |
| 9459 | Opcode_nsa_Slot_inst_encode, 0, 0 |
| 9460 | }; |
| 9461 | |
| 9462 | xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { |
| 9463 | Opcode_nsau_Slot_inst_encode, 0, 0 |
| 9464 | }; |
| 9465 | |
| 9466 | xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { |
| 9467 | Opcode_sext_Slot_inst_encode, 0, 0 |
| 9468 | }; |
| 9469 | |
| 9470 | xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { |
| 9471 | Opcode_l32ai_Slot_inst_encode, 0, 0 |
| 9472 | }; |
| 9473 | |
| 9474 | xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { |
| 9475 | Opcode_s32ri_Slot_inst_encode, 0, 0 |
| 9476 | }; |
| 9477 | |
| 9478 | xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { |
| 9479 | Opcode_s32c1i_Slot_inst_encode, 0, 0 |
| 9480 | }; |
| 9481 | |
| 9482 | xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { |
| 9483 | Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 |
| 9484 | }; |
| 9485 | |
| 9486 | xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { |
| 9487 | Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 |
| 9488 | }; |
| 9489 | |
| 9490 | xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { |
| 9491 | Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 |
| 9492 | }; |
| 9493 | |
| 9494 | xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { |
| 9495 | Opcode_quou_Slot_inst_encode, 0, 0 |
| 9496 | }; |
| 9497 | |
| 9498 | xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { |
| 9499 | Opcode_quos_Slot_inst_encode, 0, 0 |
| 9500 | }; |
| 9501 | |
| 9502 | xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { |
| 9503 | Opcode_remu_Slot_inst_encode, 0, 0 |
| 9504 | }; |
| 9505 | |
| 9506 | xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { |
| 9507 | Opcode_rems_Slot_inst_encode, 0, 0 |
| 9508 | }; |
| 9509 | |
| 9510 | xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { |
| 9511 | Opcode_mull_Slot_inst_encode, 0, 0 |
| 9512 | }; |
| 9513 | |
| 9514 | \f |
| 9515 | /* Opcode table. */ |
| 9516 | |
| 9517 | static xtensa_opcode_internal opcodes[] = { |
| 9518 | { "excw", ICLASS_xt_iclass_excw, |
| 9519 | 0, |
| 9520 | Opcode_excw_encode_fns, 0, 0 }, |
| 9521 | { "rfe", ICLASS_xt_iclass_rfe, |
| 9522 | XTENSA_OPCODE_IS_JUMP, |
| 9523 | Opcode_rfe_encode_fns, 0, 0 }, |
| 9524 | { "rfde", ICLASS_xt_iclass_rfde, |
| 9525 | XTENSA_OPCODE_IS_JUMP, |
| 9526 | Opcode_rfde_encode_fns, 0, 0 }, |
| 9527 | { "syscall", ICLASS_xt_iclass_syscall, |
| 9528 | 0, |
| 9529 | Opcode_syscall_encode_fns, 0, 0 }, |
| 9530 | { "simcall", ICLASS_xt_iclass_simcall, |
| 9531 | 0, |
| 9532 | Opcode_simcall_encode_fns, 0, 0 }, |
| 9533 | { "call12", ICLASS_xt_iclass_call12, |
| 9534 | XTENSA_OPCODE_IS_CALL, |
| 9535 | Opcode_call12_encode_fns, 0, 0 }, |
| 9536 | { "call8", ICLASS_xt_iclass_call8, |
| 9537 | XTENSA_OPCODE_IS_CALL, |
| 9538 | Opcode_call8_encode_fns, 0, 0 }, |
| 9539 | { "call4", ICLASS_xt_iclass_call4, |
| 9540 | XTENSA_OPCODE_IS_CALL, |
| 9541 | Opcode_call4_encode_fns, 0, 0 }, |
| 9542 | { "callx12", ICLASS_xt_iclass_callx12, |
| 9543 | XTENSA_OPCODE_IS_CALL, |
| 9544 | Opcode_callx12_encode_fns, 0, 0 }, |
| 9545 | { "callx8", ICLASS_xt_iclass_callx8, |
| 9546 | XTENSA_OPCODE_IS_CALL, |
| 9547 | Opcode_callx8_encode_fns, 0, 0 }, |
| 9548 | { "callx4", ICLASS_xt_iclass_callx4, |
| 9549 | XTENSA_OPCODE_IS_CALL, |
| 9550 | Opcode_callx4_encode_fns, 0, 0 }, |
| 9551 | { "entry", ICLASS_xt_iclass_entry, |
| 9552 | 0, |
| 9553 | Opcode_entry_encode_fns, 0, 0 }, |
| 9554 | { "movsp", ICLASS_xt_iclass_movsp, |
| 9555 | 0, |
| 9556 | Opcode_movsp_encode_fns, 0, 0 }, |
| 9557 | { "rotw", ICLASS_xt_iclass_rotw, |
| 9558 | 0, |
| 9559 | Opcode_rotw_encode_fns, 0, 0 }, |
| 9560 | { "retw", ICLASS_xt_iclass_retw, |
| 9561 | XTENSA_OPCODE_IS_JUMP, |
| 9562 | Opcode_retw_encode_fns, 0, 0 }, |
| 9563 | { "retw.n", ICLASS_xt_iclass_retw, |
| 9564 | XTENSA_OPCODE_IS_JUMP, |
| 9565 | Opcode_retw_n_encode_fns, 0, 0 }, |
| 9566 | { "rfwo", ICLASS_xt_iclass_rfwou, |
| 9567 | XTENSA_OPCODE_IS_JUMP, |
| 9568 | Opcode_rfwo_encode_fns, 0, 0 }, |
| 9569 | { "rfwu", ICLASS_xt_iclass_rfwou, |
| 9570 | XTENSA_OPCODE_IS_JUMP, |
| 9571 | Opcode_rfwu_encode_fns, 0, 0 }, |
| 9572 | { "l32e", ICLASS_xt_iclass_l32e, |
| 9573 | 0, |
| 9574 | Opcode_l32e_encode_fns, 0, 0 }, |
| 9575 | { "s32e", ICLASS_xt_iclass_s32e, |
| 9576 | 0, |
| 9577 | Opcode_s32e_encode_fns, 0, 0 }, |
| 9578 | { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, |
| 9579 | 0, |
| 9580 | Opcode_rsr_windowbase_encode_fns, 0, 0 }, |
| 9581 | { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, |
| 9582 | 0, |
| 9583 | Opcode_wsr_windowbase_encode_fns, 0, 0 }, |
| 9584 | { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, |
| 9585 | 0, |
| 9586 | Opcode_xsr_windowbase_encode_fns, 0, 0 }, |
| 9587 | { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, |
| 9588 | 0, |
| 9589 | Opcode_rsr_windowstart_encode_fns, 0, 0 }, |
| 9590 | { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, |
| 9591 | 0, |
| 9592 | Opcode_wsr_windowstart_encode_fns, 0, 0 }, |
| 9593 | { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, |
| 9594 | 0, |
| 9595 | Opcode_xsr_windowstart_encode_fns, 0, 0 }, |
| 9596 | { "add.n", ICLASS_xt_iclass_add_n, |
| 9597 | 0, |
| 9598 | Opcode_add_n_encode_fns, 0, 0 }, |
| 9599 | { "addi.n", ICLASS_xt_iclass_addi_n, |
| 9600 | 0, |
| 9601 | Opcode_addi_n_encode_fns, 0, 0 }, |
| 9602 | { "beqz.n", ICLASS_xt_iclass_bz6, |
| 9603 | XTENSA_OPCODE_IS_BRANCH, |
| 9604 | Opcode_beqz_n_encode_fns, 0, 0 }, |
| 9605 | { "bnez.n", ICLASS_xt_iclass_bz6, |
| 9606 | XTENSA_OPCODE_IS_BRANCH, |
| 9607 | Opcode_bnez_n_encode_fns, 0, 0 }, |
| 9608 | { "ill.n", ICLASS_xt_iclass_ill_n, |
| 9609 | 0, |
| 9610 | Opcode_ill_n_encode_fns, 0, 0 }, |
| 9611 | { "l32i.n", ICLASS_xt_iclass_loadi4, |
| 9612 | 0, |
| 9613 | Opcode_l32i_n_encode_fns, 0, 0 }, |
| 9614 | { "mov.n", ICLASS_xt_iclass_mov_n, |
| 9615 | 0, |
| 9616 | Opcode_mov_n_encode_fns, 0, 0 }, |
| 9617 | { "movi.n", ICLASS_xt_iclass_movi_n, |
| 9618 | 0, |
| 9619 | Opcode_movi_n_encode_fns, 0, 0 }, |
| 9620 | { "nop.n", ICLASS_xt_iclass_nopn, |
| 9621 | 0, |
| 9622 | Opcode_nop_n_encode_fns, 0, 0 }, |
| 9623 | { "ret.n", ICLASS_xt_iclass_retn, |
| 9624 | XTENSA_OPCODE_IS_JUMP, |
| 9625 | Opcode_ret_n_encode_fns, 0, 0 }, |
| 9626 | { "s32i.n", ICLASS_xt_iclass_storei4, |
| 9627 | 0, |
| 9628 | Opcode_s32i_n_encode_fns, 0, 0 }, |
| 9629 | { "rur.threadptr", ICLASS_rur_threadptr, |
| 9630 | 0, |
| 9631 | Opcode_rur_threadptr_encode_fns, 0, 0 }, |
| 9632 | { "wur.threadptr", ICLASS_wur_threadptr, |
| 9633 | 0, |
| 9634 | Opcode_wur_threadptr_encode_fns, 0, 0 }, |
| 9635 | { "addi", ICLASS_xt_iclass_addi, |
| 9636 | 0, |
| 9637 | Opcode_addi_encode_fns, 0, 0 }, |
| 9638 | { "addmi", ICLASS_xt_iclass_addmi, |
| 9639 | 0, |
| 9640 | Opcode_addmi_encode_fns, 0, 0 }, |
| 9641 | { "add", ICLASS_xt_iclass_addsub, |
| 9642 | 0, |
| 9643 | Opcode_add_encode_fns, 0, 0 }, |
| 9644 | { "sub", ICLASS_xt_iclass_addsub, |
| 9645 | 0, |
| 9646 | Opcode_sub_encode_fns, 0, 0 }, |
| 9647 | { "addx2", ICLASS_xt_iclass_addsub, |
| 9648 | 0, |
| 9649 | Opcode_addx2_encode_fns, 0, 0 }, |
| 9650 | { "addx4", ICLASS_xt_iclass_addsub, |
| 9651 | 0, |
| 9652 | Opcode_addx4_encode_fns, 0, 0 }, |
| 9653 | { "addx8", ICLASS_xt_iclass_addsub, |
| 9654 | 0, |
| 9655 | Opcode_addx8_encode_fns, 0, 0 }, |
| 9656 | { "subx2", ICLASS_xt_iclass_addsub, |
| 9657 | 0, |
| 9658 | Opcode_subx2_encode_fns, 0, 0 }, |
| 9659 | { "subx4", ICLASS_xt_iclass_addsub, |
| 9660 | 0, |
| 9661 | Opcode_subx4_encode_fns, 0, 0 }, |
| 9662 | { "subx8", ICLASS_xt_iclass_addsub, |
| 9663 | 0, |
| 9664 | Opcode_subx8_encode_fns, 0, 0 }, |
| 9665 | { "and", ICLASS_xt_iclass_bit, |
| 9666 | 0, |
| 9667 | Opcode_and_encode_fns, 0, 0 }, |
| 9668 | { "or", ICLASS_xt_iclass_bit, |
| 9669 | 0, |
| 9670 | Opcode_or_encode_fns, 0, 0 }, |
| 9671 | { "xor", ICLASS_xt_iclass_bit, |
| 9672 | 0, |
| 9673 | Opcode_xor_encode_fns, 0, 0 }, |
| 9674 | { "beqi", ICLASS_xt_iclass_bsi8, |
| 9675 | XTENSA_OPCODE_IS_BRANCH, |
| 9676 | Opcode_beqi_encode_fns, 0, 0 }, |
| 9677 | { "bnei", ICLASS_xt_iclass_bsi8, |
| 9678 | XTENSA_OPCODE_IS_BRANCH, |
| 9679 | Opcode_bnei_encode_fns, 0, 0 }, |
| 9680 | { "bgei", ICLASS_xt_iclass_bsi8, |
| 9681 | XTENSA_OPCODE_IS_BRANCH, |
| 9682 | Opcode_bgei_encode_fns, 0, 0 }, |
| 9683 | { "blti", ICLASS_xt_iclass_bsi8, |
| 9684 | XTENSA_OPCODE_IS_BRANCH, |
| 9685 | Opcode_blti_encode_fns, 0, 0 }, |
| 9686 | { "bbci", ICLASS_xt_iclass_bsi8b, |
| 9687 | XTENSA_OPCODE_IS_BRANCH, |
| 9688 | Opcode_bbci_encode_fns, 0, 0 }, |
| 9689 | { "bbsi", ICLASS_xt_iclass_bsi8b, |
| 9690 | XTENSA_OPCODE_IS_BRANCH, |
| 9691 | Opcode_bbsi_encode_fns, 0, 0 }, |
| 9692 | { "bgeui", ICLASS_xt_iclass_bsi8u, |
| 9693 | XTENSA_OPCODE_IS_BRANCH, |
| 9694 | Opcode_bgeui_encode_fns, 0, 0 }, |
| 9695 | { "bltui", ICLASS_xt_iclass_bsi8u, |
| 9696 | XTENSA_OPCODE_IS_BRANCH, |
| 9697 | Opcode_bltui_encode_fns, 0, 0 }, |
| 9698 | { "beq", ICLASS_xt_iclass_bst8, |
| 9699 | XTENSA_OPCODE_IS_BRANCH, |
| 9700 | Opcode_beq_encode_fns, 0, 0 }, |
| 9701 | { "bne", ICLASS_xt_iclass_bst8, |
| 9702 | XTENSA_OPCODE_IS_BRANCH, |
| 9703 | Opcode_bne_encode_fns, 0, 0 }, |
| 9704 | { "bge", ICLASS_xt_iclass_bst8, |
| 9705 | XTENSA_OPCODE_IS_BRANCH, |
| 9706 | Opcode_bge_encode_fns, 0, 0 }, |
| 9707 | { "blt", ICLASS_xt_iclass_bst8, |
| 9708 | XTENSA_OPCODE_IS_BRANCH, |
| 9709 | Opcode_blt_encode_fns, 0, 0 }, |
| 9710 | { "bgeu", ICLASS_xt_iclass_bst8, |
| 9711 | XTENSA_OPCODE_IS_BRANCH, |
| 9712 | Opcode_bgeu_encode_fns, 0, 0 }, |
| 9713 | { "bltu", ICLASS_xt_iclass_bst8, |
| 9714 | XTENSA_OPCODE_IS_BRANCH, |
| 9715 | Opcode_bltu_encode_fns, 0, 0 }, |
| 9716 | { "bany", ICLASS_xt_iclass_bst8, |
| 9717 | XTENSA_OPCODE_IS_BRANCH, |
| 9718 | Opcode_bany_encode_fns, 0, 0 }, |
| 9719 | { "bnone", ICLASS_xt_iclass_bst8, |
| 9720 | XTENSA_OPCODE_IS_BRANCH, |
| 9721 | Opcode_bnone_encode_fns, 0, 0 }, |
| 9722 | { "ball", ICLASS_xt_iclass_bst8, |
| 9723 | XTENSA_OPCODE_IS_BRANCH, |
| 9724 | Opcode_ball_encode_fns, 0, 0 }, |
| 9725 | { "bnall", ICLASS_xt_iclass_bst8, |
| 9726 | XTENSA_OPCODE_IS_BRANCH, |
| 9727 | Opcode_bnall_encode_fns, 0, 0 }, |
| 9728 | { "bbc", ICLASS_xt_iclass_bst8, |
| 9729 | XTENSA_OPCODE_IS_BRANCH, |
| 9730 | Opcode_bbc_encode_fns, 0, 0 }, |
| 9731 | { "bbs", ICLASS_xt_iclass_bst8, |
| 9732 | XTENSA_OPCODE_IS_BRANCH, |
| 9733 | Opcode_bbs_encode_fns, 0, 0 }, |
| 9734 | { "beqz", ICLASS_xt_iclass_bsz12, |
| 9735 | XTENSA_OPCODE_IS_BRANCH, |
| 9736 | Opcode_beqz_encode_fns, 0, 0 }, |
| 9737 | { "bnez", ICLASS_xt_iclass_bsz12, |
| 9738 | XTENSA_OPCODE_IS_BRANCH, |
| 9739 | Opcode_bnez_encode_fns, 0, 0 }, |
| 9740 | { "bgez", ICLASS_xt_iclass_bsz12, |
| 9741 | XTENSA_OPCODE_IS_BRANCH, |
| 9742 | Opcode_bgez_encode_fns, 0, 0 }, |
| 9743 | { "bltz", ICLASS_xt_iclass_bsz12, |
| 9744 | XTENSA_OPCODE_IS_BRANCH, |
| 9745 | Opcode_bltz_encode_fns, 0, 0 }, |
| 9746 | { "call0", ICLASS_xt_iclass_call0, |
| 9747 | XTENSA_OPCODE_IS_CALL, |
| 9748 | Opcode_call0_encode_fns, 0, 0 }, |
| 9749 | { "callx0", ICLASS_xt_iclass_callx0, |
| 9750 | XTENSA_OPCODE_IS_CALL, |
| 9751 | Opcode_callx0_encode_fns, 0, 0 }, |
| 9752 | { "extui", ICLASS_xt_iclass_exti, |
| 9753 | 0, |
| 9754 | Opcode_extui_encode_fns, 0, 0 }, |
| 9755 | { "ill", ICLASS_xt_iclass_ill, |
| 9756 | 0, |
| 9757 | Opcode_ill_encode_fns, 0, 0 }, |
| 9758 | { "j", ICLASS_xt_iclass_jump, |
| 9759 | XTENSA_OPCODE_IS_JUMP, |
| 9760 | Opcode_j_encode_fns, 0, 0 }, |
| 9761 | { "jx", ICLASS_xt_iclass_jumpx, |
| 9762 | XTENSA_OPCODE_IS_JUMP, |
| 9763 | Opcode_jx_encode_fns, 0, 0 }, |
| 9764 | { "l16ui", ICLASS_xt_iclass_l16ui, |
| 9765 | 0, |
| 9766 | Opcode_l16ui_encode_fns, 0, 0 }, |
| 9767 | { "l16si", ICLASS_xt_iclass_l16si, |
| 9768 | 0, |
| 9769 | Opcode_l16si_encode_fns, 0, 0 }, |
| 9770 | { "l32i", ICLASS_xt_iclass_l32i, |
| 9771 | 0, |
| 9772 | Opcode_l32i_encode_fns, 0, 0 }, |
| 9773 | { "l32r", ICLASS_xt_iclass_l32r, |
| 9774 | 0, |
| 9775 | Opcode_l32r_encode_fns, 0, 0 }, |
| 9776 | { "l8ui", ICLASS_xt_iclass_l8i, |
| 9777 | 0, |
| 9778 | Opcode_l8ui_encode_fns, 0, 0 }, |
| 9779 | { "loop", ICLASS_xt_iclass_loop, |
| 9780 | XTENSA_OPCODE_IS_LOOP, |
| 9781 | Opcode_loop_encode_fns, 0, 0 }, |
| 9782 | { "loopnez", ICLASS_xt_iclass_loopz, |
| 9783 | XTENSA_OPCODE_IS_LOOP, |
| 9784 | Opcode_loopnez_encode_fns, 0, 0 }, |
| 9785 | { "loopgtz", ICLASS_xt_iclass_loopz, |
| 9786 | XTENSA_OPCODE_IS_LOOP, |
| 9787 | Opcode_loopgtz_encode_fns, 0, 0 }, |
| 9788 | { "movi", ICLASS_xt_iclass_movi, |
| 9789 | 0, |
| 9790 | Opcode_movi_encode_fns, 0, 0 }, |
| 9791 | { "moveqz", ICLASS_xt_iclass_movz, |
| 9792 | 0, |
| 9793 | Opcode_moveqz_encode_fns, 0, 0 }, |
| 9794 | { "movnez", ICLASS_xt_iclass_movz, |
| 9795 | 0, |
| 9796 | Opcode_movnez_encode_fns, 0, 0 }, |
| 9797 | { "movltz", ICLASS_xt_iclass_movz, |
| 9798 | 0, |
| 9799 | Opcode_movltz_encode_fns, 0, 0 }, |
| 9800 | { "movgez", ICLASS_xt_iclass_movz, |
| 9801 | 0, |
| 9802 | Opcode_movgez_encode_fns, 0, 0 }, |
| 9803 | { "neg", ICLASS_xt_iclass_neg, |
| 9804 | 0, |
| 9805 | Opcode_neg_encode_fns, 0, 0 }, |
| 9806 | { "abs", ICLASS_xt_iclass_neg, |
| 9807 | 0, |
| 9808 | Opcode_abs_encode_fns, 0, 0 }, |
| 9809 | { "nop", ICLASS_xt_iclass_nop, |
| 9810 | 0, |
| 9811 | Opcode_nop_encode_fns, 0, 0 }, |
| 9812 | { "ret", ICLASS_xt_iclass_return, |
| 9813 | XTENSA_OPCODE_IS_JUMP, |
| 9814 | Opcode_ret_encode_fns, 0, 0 }, |
| 9815 | { "s16i", ICLASS_xt_iclass_s16i, |
| 9816 | 0, |
| 9817 | Opcode_s16i_encode_fns, 0, 0 }, |
| 9818 | { "s32i", ICLASS_xt_iclass_s32i, |
| 9819 | 0, |
| 9820 | Opcode_s32i_encode_fns, 0, 0 }, |
| 9821 | { "s8i", ICLASS_xt_iclass_s8i, |
| 9822 | 0, |
| 9823 | Opcode_s8i_encode_fns, 0, 0 }, |
| 9824 | { "ssr", ICLASS_xt_iclass_sar, |
| 9825 | 0, |
| 9826 | Opcode_ssr_encode_fns, 0, 0 }, |
| 9827 | { "ssl", ICLASS_xt_iclass_sar, |
| 9828 | 0, |
| 9829 | Opcode_ssl_encode_fns, 0, 0 }, |
| 9830 | { "ssa8l", ICLASS_xt_iclass_sar, |
| 9831 | 0, |
| 9832 | Opcode_ssa8l_encode_fns, 0, 0 }, |
| 9833 | { "ssa8b", ICLASS_xt_iclass_sar, |
| 9834 | 0, |
| 9835 | Opcode_ssa8b_encode_fns, 0, 0 }, |
| 9836 | { "ssai", ICLASS_xt_iclass_sari, |
| 9837 | 0, |
| 9838 | Opcode_ssai_encode_fns, 0, 0 }, |
| 9839 | { "sll", ICLASS_xt_iclass_shifts, |
| 9840 | 0, |
| 9841 | Opcode_sll_encode_fns, 0, 0 }, |
| 9842 | { "src", ICLASS_xt_iclass_shiftst, |
| 9843 | 0, |
| 9844 | Opcode_src_encode_fns, 0, 0 }, |
| 9845 | { "srl", ICLASS_xt_iclass_shiftt, |
| 9846 | 0, |
| 9847 | Opcode_srl_encode_fns, 0, 0 }, |
| 9848 | { "sra", ICLASS_xt_iclass_shiftt, |
| 9849 | 0, |
| 9850 | Opcode_sra_encode_fns, 0, 0 }, |
| 9851 | { "slli", ICLASS_xt_iclass_slli, |
| 9852 | 0, |
| 9853 | Opcode_slli_encode_fns, 0, 0 }, |
| 9854 | { "srai", ICLASS_xt_iclass_srai, |
| 9855 | 0, |
| 9856 | Opcode_srai_encode_fns, 0, 0 }, |
| 9857 | { "srli", ICLASS_xt_iclass_srli, |
| 9858 | 0, |
| 9859 | Opcode_srli_encode_fns, 0, 0 }, |
| 9860 | { "memw", ICLASS_xt_iclass_memw, |
| 9861 | 0, |
| 9862 | Opcode_memw_encode_fns, 0, 0 }, |
| 9863 | { "extw", ICLASS_xt_iclass_extw, |
| 9864 | 0, |
| 9865 | Opcode_extw_encode_fns, 0, 0 }, |
| 9866 | { "isync", ICLASS_xt_iclass_isync, |
| 9867 | 0, |
| 9868 | Opcode_isync_encode_fns, 0, 0 }, |
| 9869 | { "rsync", ICLASS_xt_iclass_sync, |
| 9870 | 0, |
| 9871 | Opcode_rsync_encode_fns, 0, 0 }, |
| 9872 | { "esync", ICLASS_xt_iclass_sync, |
| 9873 | 0, |
| 9874 | Opcode_esync_encode_fns, 0, 0 }, |
| 9875 | { "dsync", ICLASS_xt_iclass_sync, |
| 9876 | 0, |
| 9877 | Opcode_dsync_encode_fns, 0, 0 }, |
| 9878 | { "rsil", ICLASS_xt_iclass_rsil, |
| 9879 | 0, |
| 9880 | Opcode_rsil_encode_fns, 0, 0 }, |
| 9881 | { "rsr.lend", ICLASS_xt_iclass_rsr_lend, |
| 9882 | 0, |
| 9883 | Opcode_rsr_lend_encode_fns, 0, 0 }, |
| 9884 | { "wsr.lend", ICLASS_xt_iclass_wsr_lend, |
| 9885 | 0, |
| 9886 | Opcode_wsr_lend_encode_fns, 0, 0 }, |
| 9887 | { "xsr.lend", ICLASS_xt_iclass_xsr_lend, |
| 9888 | 0, |
| 9889 | Opcode_xsr_lend_encode_fns, 0, 0 }, |
| 9890 | { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, |
| 9891 | 0, |
| 9892 | Opcode_rsr_lcount_encode_fns, 0, 0 }, |
| 9893 | { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, |
| 9894 | 0, |
| 9895 | Opcode_wsr_lcount_encode_fns, 0, 0 }, |
| 9896 | { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, |
| 9897 | 0, |
| 9898 | Opcode_xsr_lcount_encode_fns, 0, 0 }, |
| 9899 | { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, |
| 9900 | 0, |
| 9901 | Opcode_rsr_lbeg_encode_fns, 0, 0 }, |
| 9902 | { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, |
| 9903 | 0, |
| 9904 | Opcode_wsr_lbeg_encode_fns, 0, 0 }, |
| 9905 | { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, |
| 9906 | 0, |
| 9907 | Opcode_xsr_lbeg_encode_fns, 0, 0 }, |
| 9908 | { "rsr.sar", ICLASS_xt_iclass_rsr_sar, |
| 9909 | 0, |
| 9910 | Opcode_rsr_sar_encode_fns, 0, 0 }, |
| 9911 | { "wsr.sar", ICLASS_xt_iclass_wsr_sar, |
| 9912 | 0, |
| 9913 | Opcode_wsr_sar_encode_fns, 0, 0 }, |
| 9914 | { "xsr.sar", ICLASS_xt_iclass_xsr_sar, |
| 9915 | 0, |
| 9916 | Opcode_xsr_sar_encode_fns, 0, 0 }, |
| 9917 | { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, |
| 9918 | 0, |
| 9919 | Opcode_rsr_litbase_encode_fns, 0, 0 }, |
| 9920 | { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, |
| 9921 | 0, |
| 9922 | Opcode_wsr_litbase_encode_fns, 0, 0 }, |
| 9923 | { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, |
| 9924 | 0, |
| 9925 | Opcode_xsr_litbase_encode_fns, 0, 0 }, |
| 9926 | { "rsr.176", ICLASS_xt_iclass_rsr_176, |
| 9927 | 0, |
| 9928 | Opcode_rsr_176_encode_fns, 0, 0 }, |
| 9929 | { "wsr.176", ICLASS_xt_iclass_wsr_176, |
| 9930 | 0, |
| 9931 | Opcode_wsr_176_encode_fns, 0, 0 }, |
| 9932 | { "rsr.208", ICLASS_xt_iclass_rsr_208, |
| 9933 | 0, |
| 9934 | Opcode_rsr_208_encode_fns, 0, 0 }, |
| 9935 | { "rsr.ps", ICLASS_xt_iclass_rsr_ps, |
| 9936 | 0, |
| 9937 | Opcode_rsr_ps_encode_fns, 0, 0 }, |
| 9938 | { "wsr.ps", ICLASS_xt_iclass_wsr_ps, |
| 9939 | 0, |
| 9940 | Opcode_wsr_ps_encode_fns, 0, 0 }, |
| 9941 | { "xsr.ps", ICLASS_xt_iclass_xsr_ps, |
| 9942 | 0, |
| 9943 | Opcode_xsr_ps_encode_fns, 0, 0 }, |
| 9944 | { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, |
| 9945 | 0, |
| 9946 | Opcode_rsr_epc1_encode_fns, 0, 0 }, |
| 9947 | { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, |
| 9948 | 0, |
| 9949 | Opcode_wsr_epc1_encode_fns, 0, 0 }, |
| 9950 | { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, |
| 9951 | 0, |
| 9952 | Opcode_xsr_epc1_encode_fns, 0, 0 }, |
| 9953 | { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, |
| 9954 | 0, |
| 9955 | Opcode_rsr_excsave1_encode_fns, 0, 0 }, |
| 9956 | { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, |
| 9957 | 0, |
| 9958 | Opcode_wsr_excsave1_encode_fns, 0, 0 }, |
| 9959 | { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, |
| 9960 | 0, |
| 9961 | Opcode_xsr_excsave1_encode_fns, 0, 0 }, |
| 9962 | { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, |
| 9963 | 0, |
| 9964 | Opcode_rsr_epc2_encode_fns, 0, 0 }, |
| 9965 | { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, |
| 9966 | 0, |
| 9967 | Opcode_wsr_epc2_encode_fns, 0, 0 }, |
| 9968 | { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, |
| 9969 | 0, |
| 9970 | Opcode_xsr_epc2_encode_fns, 0, 0 }, |
| 9971 | { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, |
| 9972 | 0, |
| 9973 | Opcode_rsr_excsave2_encode_fns, 0, 0 }, |
| 9974 | { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, |
| 9975 | 0, |
| 9976 | Opcode_wsr_excsave2_encode_fns, 0, 0 }, |
| 9977 | { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, |
| 9978 | 0, |
| 9979 | Opcode_xsr_excsave2_encode_fns, 0, 0 }, |
| 9980 | { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, |
| 9981 | 0, |
| 9982 | Opcode_rsr_epc3_encode_fns, 0, 0 }, |
| 9983 | { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, |
| 9984 | 0, |
| 9985 | Opcode_wsr_epc3_encode_fns, 0, 0 }, |
| 9986 | { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, |
| 9987 | 0, |
| 9988 | Opcode_xsr_epc3_encode_fns, 0, 0 }, |
| 9989 | { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, |
| 9990 | 0, |
| 9991 | Opcode_rsr_excsave3_encode_fns, 0, 0 }, |
| 9992 | { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, |
| 9993 | 0, |
| 9994 | Opcode_wsr_excsave3_encode_fns, 0, 0 }, |
| 9995 | { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, |
| 9996 | 0, |
| 9997 | Opcode_xsr_excsave3_encode_fns, 0, 0 }, |
| 9998 | { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, |
| 9999 | 0, |
| 10000 | Opcode_rsr_epc4_encode_fns, 0, 0 }, |
| 10001 | { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, |
| 10002 | 0, |
| 10003 | Opcode_wsr_epc4_encode_fns, 0, 0 }, |
| 10004 | { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, |
| 10005 | 0, |
| 10006 | Opcode_xsr_epc4_encode_fns, 0, 0 }, |
| 10007 | { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, |
| 10008 | 0, |
| 10009 | Opcode_rsr_excsave4_encode_fns, 0, 0 }, |
| 10010 | { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, |
| 10011 | 0, |
| 10012 | Opcode_wsr_excsave4_encode_fns, 0, 0 }, |
| 10013 | { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, |
| 10014 | 0, |
| 10015 | Opcode_xsr_excsave4_encode_fns, 0, 0 }, |
| 10016 | { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, |
| 10017 | 0, |
| 10018 | Opcode_rsr_epc5_encode_fns, 0, 0 }, |
| 10019 | { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, |
| 10020 | 0, |
| 10021 | Opcode_wsr_epc5_encode_fns, 0, 0 }, |
| 10022 | { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, |
| 10023 | 0, |
| 10024 | Opcode_xsr_epc5_encode_fns, 0, 0 }, |
| 10025 | { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, |
| 10026 | 0, |
| 10027 | Opcode_rsr_excsave5_encode_fns, 0, 0 }, |
| 10028 | { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, |
| 10029 | 0, |
| 10030 | Opcode_wsr_excsave5_encode_fns, 0, 0 }, |
| 10031 | { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, |
| 10032 | 0, |
| 10033 | Opcode_xsr_excsave5_encode_fns, 0, 0 }, |
| 10034 | { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, |
| 10035 | 0, |
| 10036 | Opcode_rsr_epc6_encode_fns, 0, 0 }, |
| 10037 | { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, |
| 10038 | 0, |
| 10039 | Opcode_wsr_epc6_encode_fns, 0, 0 }, |
| 10040 | { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, |
| 10041 | 0, |
| 10042 | Opcode_xsr_epc6_encode_fns, 0, 0 }, |
| 10043 | { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, |
| 10044 | 0, |
| 10045 | Opcode_rsr_excsave6_encode_fns, 0, 0 }, |
| 10046 | { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, |
| 10047 | 0, |
| 10048 | Opcode_wsr_excsave6_encode_fns, 0, 0 }, |
| 10049 | { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, |
| 10050 | 0, |
| 10051 | Opcode_xsr_excsave6_encode_fns, 0, 0 }, |
| 10052 | { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, |
| 10053 | 0, |
| 10054 | Opcode_rsr_epc7_encode_fns, 0, 0 }, |
| 10055 | { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, |
| 10056 | 0, |
| 10057 | Opcode_wsr_epc7_encode_fns, 0, 0 }, |
| 10058 | { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, |
| 10059 | 0, |
| 10060 | Opcode_xsr_epc7_encode_fns, 0, 0 }, |
| 10061 | { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, |
| 10062 | 0, |
| 10063 | Opcode_rsr_excsave7_encode_fns, 0, 0 }, |
| 10064 | { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, |
| 10065 | 0, |
| 10066 | Opcode_wsr_excsave7_encode_fns, 0, 0 }, |
| 10067 | { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, |
| 10068 | 0, |
| 10069 | Opcode_xsr_excsave7_encode_fns, 0, 0 }, |
| 10070 | { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, |
| 10071 | 0, |
| 10072 | Opcode_rsr_eps2_encode_fns, 0, 0 }, |
| 10073 | { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, |
| 10074 | 0, |
| 10075 | Opcode_wsr_eps2_encode_fns, 0, 0 }, |
| 10076 | { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, |
| 10077 | 0, |
| 10078 | Opcode_xsr_eps2_encode_fns, 0, 0 }, |
| 10079 | { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, |
| 10080 | 0, |
| 10081 | Opcode_rsr_eps3_encode_fns, 0, 0 }, |
| 10082 | { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, |
| 10083 | 0, |
| 10084 | Opcode_wsr_eps3_encode_fns, 0, 0 }, |
| 10085 | { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, |
| 10086 | 0, |
| 10087 | Opcode_xsr_eps3_encode_fns, 0, 0 }, |
| 10088 | { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, |
| 10089 | 0, |
| 10090 | Opcode_rsr_eps4_encode_fns, 0, 0 }, |
| 10091 | { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, |
| 10092 | 0, |
| 10093 | Opcode_wsr_eps4_encode_fns, 0, 0 }, |
| 10094 | { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, |
| 10095 | 0, |
| 10096 | Opcode_xsr_eps4_encode_fns, 0, 0 }, |
| 10097 | { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, |
| 10098 | 0, |
| 10099 | Opcode_rsr_eps5_encode_fns, 0, 0 }, |
| 10100 | { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, |
| 10101 | 0, |
| 10102 | Opcode_wsr_eps5_encode_fns, 0, 0 }, |
| 10103 | { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, |
| 10104 | 0, |
| 10105 | Opcode_xsr_eps5_encode_fns, 0, 0 }, |
| 10106 | { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, |
| 10107 | 0, |
| 10108 | Opcode_rsr_eps6_encode_fns, 0, 0 }, |
| 10109 | { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, |
| 10110 | 0, |
| 10111 | Opcode_wsr_eps6_encode_fns, 0, 0 }, |
| 10112 | { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, |
| 10113 | 0, |
| 10114 | Opcode_xsr_eps6_encode_fns, 0, 0 }, |
| 10115 | { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, |
| 10116 | 0, |
| 10117 | Opcode_rsr_eps7_encode_fns, 0, 0 }, |
| 10118 | { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, |
| 10119 | 0, |
| 10120 | Opcode_wsr_eps7_encode_fns, 0, 0 }, |
| 10121 | { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, |
| 10122 | 0, |
| 10123 | Opcode_xsr_eps7_encode_fns, 0, 0 }, |
| 10124 | { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, |
| 10125 | 0, |
| 10126 | Opcode_rsr_excvaddr_encode_fns, 0, 0 }, |
| 10127 | { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, |
| 10128 | 0, |
| 10129 | Opcode_wsr_excvaddr_encode_fns, 0, 0 }, |
| 10130 | { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, |
| 10131 | 0, |
| 10132 | Opcode_xsr_excvaddr_encode_fns, 0, 0 }, |
| 10133 | { "rsr.depc", ICLASS_xt_iclass_rsr_depc, |
| 10134 | 0, |
| 10135 | Opcode_rsr_depc_encode_fns, 0, 0 }, |
| 10136 | { "wsr.depc", ICLASS_xt_iclass_wsr_depc, |
| 10137 | 0, |
| 10138 | Opcode_wsr_depc_encode_fns, 0, 0 }, |
| 10139 | { "xsr.depc", ICLASS_xt_iclass_xsr_depc, |
| 10140 | 0, |
| 10141 | Opcode_xsr_depc_encode_fns, 0, 0 }, |
| 10142 | { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, |
| 10143 | 0, |
| 10144 | Opcode_rsr_exccause_encode_fns, 0, 0 }, |
| 10145 | { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, |
| 10146 | 0, |
| 10147 | Opcode_wsr_exccause_encode_fns, 0, 0 }, |
| 10148 | { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, |
| 10149 | 0, |
| 10150 | Opcode_xsr_exccause_encode_fns, 0, 0 }, |
| 10151 | { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, |
| 10152 | 0, |
| 10153 | Opcode_rsr_misc0_encode_fns, 0, 0 }, |
| 10154 | { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, |
| 10155 | 0, |
| 10156 | Opcode_wsr_misc0_encode_fns, 0, 0 }, |
| 10157 | { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, |
| 10158 | 0, |
| 10159 | Opcode_xsr_misc0_encode_fns, 0, 0 }, |
| 10160 | { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, |
| 10161 | 0, |
| 10162 | Opcode_rsr_misc1_encode_fns, 0, 0 }, |
| 10163 | { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, |
| 10164 | 0, |
| 10165 | Opcode_wsr_misc1_encode_fns, 0, 0 }, |
| 10166 | { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, |
| 10167 | 0, |
| 10168 | Opcode_xsr_misc1_encode_fns, 0, 0 }, |
| 10169 | { "rsr.prid", ICLASS_xt_iclass_rsr_prid, |
| 10170 | 0, |
| 10171 | Opcode_rsr_prid_encode_fns, 0, 0 }, |
| 10172 | { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, |
| 10173 | 0, |
| 10174 | Opcode_rsr_vecbase_encode_fns, 0, 0 }, |
| 10175 | { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, |
| 10176 | 0, |
| 10177 | Opcode_wsr_vecbase_encode_fns, 0, 0 }, |
| 10178 | { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, |
| 10179 | 0, |
| 10180 | Opcode_xsr_vecbase_encode_fns, 0, 0 }, |
| 10181 | { "mul16u", ICLASS_xt_iclass_mul16, |
| 10182 | 0, |
| 10183 | Opcode_mul16u_encode_fns, 0, 0 }, |
| 10184 | { "mul16s", ICLASS_xt_iclass_mul16, |
| 10185 | 0, |
| 10186 | Opcode_mul16s_encode_fns, 0, 0 }, |
| 10187 | { "rfi", ICLASS_xt_iclass_rfi, |
| 10188 | XTENSA_OPCODE_IS_JUMP, |
| 10189 | Opcode_rfi_encode_fns, 0, 0 }, |
| 10190 | { "waiti", ICLASS_xt_iclass_wait, |
| 10191 | 0, |
| 10192 | Opcode_waiti_encode_fns, 0, 0 }, |
| 10193 | { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, |
| 10194 | 0, |
| 10195 | Opcode_rsr_interrupt_encode_fns, 0, 0 }, |
| 10196 | { "wsr.intset", ICLASS_xt_iclass_wsr_intset, |
| 10197 | 0, |
| 10198 | Opcode_wsr_intset_encode_fns, 0, 0 }, |
| 10199 | { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, |
| 10200 | 0, |
| 10201 | Opcode_wsr_intclear_encode_fns, 0, 0 }, |
| 10202 | { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, |
| 10203 | 0, |
| 10204 | Opcode_rsr_intenable_encode_fns, 0, 0 }, |
| 10205 | { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, |
| 10206 | 0, |
| 10207 | Opcode_wsr_intenable_encode_fns, 0, 0 }, |
| 10208 | { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, |
| 10209 | 0, |
| 10210 | Opcode_xsr_intenable_encode_fns, 0, 0 }, |
| 10211 | { "break", ICLASS_xt_iclass_break, |
| 10212 | 0, |
| 10213 | Opcode_break_encode_fns, 0, 0 }, |
| 10214 | { "break.n", ICLASS_xt_iclass_break_n, |
| 10215 | 0, |
| 10216 | Opcode_break_n_encode_fns, 0, 0 }, |
| 10217 | { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, |
| 10218 | 0, |
| 10219 | Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, |
| 10220 | { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, |
| 10221 | 0, |
| 10222 | Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, |
| 10223 | { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, |
| 10224 | 0, |
| 10225 | Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, |
| 10226 | { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, |
| 10227 | 0, |
| 10228 | Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, |
| 10229 | { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, |
| 10230 | 0, |
| 10231 | Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, |
| 10232 | { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, |
| 10233 | 0, |
| 10234 | Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, |
| 10235 | { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, |
| 10236 | 0, |
| 10237 | Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, |
| 10238 | { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, |
| 10239 | 0, |
| 10240 | Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, |
| 10241 | { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, |
| 10242 | 0, |
| 10243 | Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, |
| 10244 | { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, |
| 10245 | 0, |
| 10246 | Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, |
| 10247 | { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, |
| 10248 | 0, |
| 10249 | Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, |
| 10250 | { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, |
| 10251 | 0, |
| 10252 | Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, |
| 10253 | { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, |
| 10254 | 0, |
| 10255 | Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, |
| 10256 | { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, |
| 10257 | 0, |
| 10258 | Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, |
| 10259 | { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, |
| 10260 | 0, |
| 10261 | Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, |
| 10262 | { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, |
| 10263 | 0, |
| 10264 | Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, |
| 10265 | { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, |
| 10266 | 0, |
| 10267 | Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, |
| 10268 | { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, |
| 10269 | 0, |
| 10270 | Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, |
| 10271 | { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, |
| 10272 | 0, |
| 10273 | Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, |
| 10274 | { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, |
| 10275 | 0, |
| 10276 | Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, |
| 10277 | { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, |
| 10278 | 0, |
| 10279 | Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, |
| 10280 | { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, |
| 10281 | 0, |
| 10282 | Opcode_rsr_debugcause_encode_fns, 0, 0 }, |
| 10283 | { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, |
| 10284 | 0, |
| 10285 | Opcode_wsr_debugcause_encode_fns, 0, 0 }, |
| 10286 | { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, |
| 10287 | 0, |
| 10288 | Opcode_xsr_debugcause_encode_fns, 0, 0 }, |
| 10289 | { "rsr.icount", ICLASS_xt_iclass_rsr_icount, |
| 10290 | 0, |
| 10291 | Opcode_rsr_icount_encode_fns, 0, 0 }, |
| 10292 | { "wsr.icount", ICLASS_xt_iclass_wsr_icount, |
| 10293 | 0, |
| 10294 | Opcode_wsr_icount_encode_fns, 0, 0 }, |
| 10295 | { "xsr.icount", ICLASS_xt_iclass_xsr_icount, |
| 10296 | 0, |
| 10297 | Opcode_xsr_icount_encode_fns, 0, 0 }, |
| 10298 | { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, |
| 10299 | 0, |
| 10300 | Opcode_rsr_icountlevel_encode_fns, 0, 0 }, |
| 10301 | { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, |
| 10302 | 0, |
| 10303 | Opcode_wsr_icountlevel_encode_fns, 0, 0 }, |
| 10304 | { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, |
| 10305 | 0, |
| 10306 | Opcode_xsr_icountlevel_encode_fns, 0, 0 }, |
| 10307 | { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, |
| 10308 | 0, |
| 10309 | Opcode_rsr_ddr_encode_fns, 0, 0 }, |
| 10310 | { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, |
| 10311 | 0, |
| 10312 | Opcode_wsr_ddr_encode_fns, 0, 0 }, |
| 10313 | { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, |
| 10314 | 0, |
| 10315 | Opcode_xsr_ddr_encode_fns, 0, 0 }, |
| 10316 | { "rfdo", ICLASS_xt_iclass_rfdo, |
| 10317 | XTENSA_OPCODE_IS_JUMP, |
| 10318 | Opcode_rfdo_encode_fns, 0, 0 }, |
| 10319 | { "rfdd", ICLASS_xt_iclass_rfdd, |
| 10320 | XTENSA_OPCODE_IS_JUMP, |
| 10321 | Opcode_rfdd_encode_fns, 0, 0 }, |
| 10322 | { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, |
| 10323 | 0, |
| 10324 | Opcode_wsr_mmid_encode_fns, 0, 0 }, |
| 10325 | { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, |
| 10326 | 0, |
| 10327 | Opcode_rsr_ccount_encode_fns, 0, 0 }, |
| 10328 | { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, |
| 10329 | 0, |
| 10330 | Opcode_wsr_ccount_encode_fns, 0, 0 }, |
| 10331 | { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, |
| 10332 | 0, |
| 10333 | Opcode_xsr_ccount_encode_fns, 0, 0 }, |
| 10334 | { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, |
| 10335 | 0, |
| 10336 | Opcode_rsr_ccompare0_encode_fns, 0, 0 }, |
| 10337 | { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, |
| 10338 | 0, |
| 10339 | Opcode_wsr_ccompare0_encode_fns, 0, 0 }, |
| 10340 | { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, |
| 10341 | 0, |
| 10342 | Opcode_xsr_ccompare0_encode_fns, 0, 0 }, |
| 10343 | { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, |
| 10344 | 0, |
| 10345 | Opcode_rsr_ccompare1_encode_fns, 0, 0 }, |
| 10346 | { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, |
| 10347 | 0, |
| 10348 | Opcode_wsr_ccompare1_encode_fns, 0, 0 }, |
| 10349 | { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, |
| 10350 | 0, |
| 10351 | Opcode_xsr_ccompare1_encode_fns, 0, 0 }, |
| 10352 | { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, |
| 10353 | 0, |
| 10354 | Opcode_rsr_ccompare2_encode_fns, 0, 0 }, |
| 10355 | { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, |
| 10356 | 0, |
| 10357 | Opcode_wsr_ccompare2_encode_fns, 0, 0 }, |
| 10358 | { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, |
| 10359 | 0, |
| 10360 | Opcode_xsr_ccompare2_encode_fns, 0, 0 }, |
| 10361 | { "ipf", ICLASS_xt_iclass_icache, |
| 10362 | 0, |
| 10363 | Opcode_ipf_encode_fns, 0, 0 }, |
| 10364 | { "ihi", ICLASS_xt_iclass_icache, |
| 10365 | 0, |
| 10366 | Opcode_ihi_encode_fns, 0, 0 }, |
| 10367 | { "ipfl", ICLASS_xt_iclass_icache_lock, |
| 10368 | 0, |
| 10369 | Opcode_ipfl_encode_fns, 0, 0 }, |
| 10370 | { "ihu", ICLASS_xt_iclass_icache_lock, |
| 10371 | 0, |
| 10372 | Opcode_ihu_encode_fns, 0, 0 }, |
| 10373 | { "iiu", ICLASS_xt_iclass_icache_lock, |
| 10374 | 0, |
| 10375 | Opcode_iiu_encode_fns, 0, 0 }, |
| 10376 | { "iii", ICLASS_xt_iclass_icache_inv, |
| 10377 | 0, |
| 10378 | Opcode_iii_encode_fns, 0, 0 }, |
| 10379 | { "lict", ICLASS_xt_iclass_licx, |
| 10380 | 0, |
| 10381 | Opcode_lict_encode_fns, 0, 0 }, |
| 10382 | { "licw", ICLASS_xt_iclass_licx, |
| 10383 | 0, |
| 10384 | Opcode_licw_encode_fns, 0, 0 }, |
| 10385 | { "sict", ICLASS_xt_iclass_sicx, |
| 10386 | 0, |
| 10387 | Opcode_sict_encode_fns, 0, 0 }, |
| 10388 | { "sicw", ICLASS_xt_iclass_sicx, |
| 10389 | 0, |
| 10390 | Opcode_sicw_encode_fns, 0, 0 }, |
| 10391 | { "dhwb", ICLASS_xt_iclass_dcache, |
| 10392 | 0, |
| 10393 | Opcode_dhwb_encode_fns, 0, 0 }, |
| 10394 | { "dhwbi", ICLASS_xt_iclass_dcache, |
| 10395 | 0, |
| 10396 | Opcode_dhwbi_encode_fns, 0, 0 }, |
| 10397 | { "diwb", ICLASS_xt_iclass_dcache_ind, |
| 10398 | 0, |
| 10399 | Opcode_diwb_encode_fns, 0, 0 }, |
| 10400 | { "diwbi", ICLASS_xt_iclass_dcache_ind, |
| 10401 | 0, |
| 10402 | Opcode_diwbi_encode_fns, 0, 0 }, |
| 10403 | { "dhi", ICLASS_xt_iclass_dcache_inv, |
| 10404 | 0, |
| 10405 | Opcode_dhi_encode_fns, 0, 0 }, |
| 10406 | { "dii", ICLASS_xt_iclass_dcache_inv, |
| 10407 | 0, |
| 10408 | Opcode_dii_encode_fns, 0, 0 }, |
| 10409 | { "dpfr", ICLASS_xt_iclass_dpf, |
| 10410 | 0, |
| 10411 | Opcode_dpfr_encode_fns, 0, 0 }, |
| 10412 | { "dpfw", ICLASS_xt_iclass_dpf, |
| 10413 | 0, |
| 10414 | Opcode_dpfw_encode_fns, 0, 0 }, |
| 10415 | { "dpfro", ICLASS_xt_iclass_dpf, |
| 10416 | 0, |
| 10417 | Opcode_dpfro_encode_fns, 0, 0 }, |
| 10418 | { "dpfwo", ICLASS_xt_iclass_dpf, |
| 10419 | 0, |
| 10420 | Opcode_dpfwo_encode_fns, 0, 0 }, |
| 10421 | { "dpfl", ICLASS_xt_iclass_dcache_lock, |
| 10422 | 0, |
| 10423 | Opcode_dpfl_encode_fns, 0, 0 }, |
| 10424 | { "dhu", ICLASS_xt_iclass_dcache_lock, |
| 10425 | 0, |
| 10426 | Opcode_dhu_encode_fns, 0, 0 }, |
| 10427 | { "diu", ICLASS_xt_iclass_dcache_lock, |
| 10428 | 0, |
| 10429 | Opcode_diu_encode_fns, 0, 0 }, |
| 10430 | { "sdct", ICLASS_xt_iclass_sdct, |
| 10431 | 0, |
| 10432 | Opcode_sdct_encode_fns, 0, 0 }, |
| 10433 | { "ldct", ICLASS_xt_iclass_ldct, |
| 10434 | 0, |
| 10435 | Opcode_ldct_encode_fns, 0, 0 }, |
| 10436 | { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, |
| 10437 | 0, |
| 10438 | Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, |
| 10439 | { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, |
| 10440 | 0, |
| 10441 | Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, |
| 10442 | { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, |
| 10443 | 0, |
| 10444 | Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, |
| 10445 | { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, |
| 10446 | 0, |
| 10447 | Opcode_rsr_rasid_encode_fns, 0, 0 }, |
| 10448 | { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, |
| 10449 | 0, |
| 10450 | Opcode_wsr_rasid_encode_fns, 0, 0 }, |
| 10451 | { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, |
| 10452 | 0, |
| 10453 | Opcode_xsr_rasid_encode_fns, 0, 0 }, |
| 10454 | { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, |
| 10455 | 0, |
| 10456 | Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, |
| 10457 | { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, |
| 10458 | 0, |
| 10459 | Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, |
| 10460 | { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, |
| 10461 | 0, |
| 10462 | Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, |
| 10463 | { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, |
| 10464 | 0, |
| 10465 | Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, |
| 10466 | { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, |
| 10467 | 0, |
| 10468 | Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, |
| 10469 | { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, |
| 10470 | 0, |
| 10471 | Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, |
| 10472 | { "idtlb", ICLASS_xt_iclass_idtlb, |
| 10473 | 0, |
| 10474 | Opcode_idtlb_encode_fns, 0, 0 }, |
| 10475 | { "pdtlb", ICLASS_xt_iclass_rdtlb, |
| 10476 | 0, |
| 10477 | Opcode_pdtlb_encode_fns, 0, 0 }, |
| 10478 | { "rdtlb0", ICLASS_xt_iclass_rdtlb, |
| 10479 | 0, |
| 10480 | Opcode_rdtlb0_encode_fns, 0, 0 }, |
| 10481 | { "rdtlb1", ICLASS_xt_iclass_rdtlb, |
| 10482 | 0, |
| 10483 | Opcode_rdtlb1_encode_fns, 0, 0 }, |
| 10484 | { "wdtlb", ICLASS_xt_iclass_wdtlb, |
| 10485 | 0, |
| 10486 | Opcode_wdtlb_encode_fns, 0, 0 }, |
| 10487 | { "iitlb", ICLASS_xt_iclass_iitlb, |
| 10488 | 0, |
| 10489 | Opcode_iitlb_encode_fns, 0, 0 }, |
| 10490 | { "pitlb", ICLASS_xt_iclass_ritlb, |
| 10491 | 0, |
| 10492 | Opcode_pitlb_encode_fns, 0, 0 }, |
| 10493 | { "ritlb0", ICLASS_xt_iclass_ritlb, |
| 10494 | 0, |
| 10495 | Opcode_ritlb0_encode_fns, 0, 0 }, |
| 10496 | { "ritlb1", ICLASS_xt_iclass_ritlb, |
| 10497 | 0, |
| 10498 | Opcode_ritlb1_encode_fns, 0, 0 }, |
| 10499 | { "witlb", ICLASS_xt_iclass_witlb, |
| 10500 | 0, |
| 10501 | Opcode_witlb_encode_fns, 0, 0 }, |
| 10502 | { "ldpte", ICLASS_xt_iclass_ldpte, |
| 10503 | 0, |
| 10504 | Opcode_ldpte_encode_fns, 0, 0 }, |
| 10505 | { "hwwitlba", ICLASS_xt_iclass_hwwitlba, |
| 10506 | XTENSA_OPCODE_IS_BRANCH, |
| 10507 | Opcode_hwwitlba_encode_fns, 0, 0 }, |
| 10508 | { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, |
| 10509 | 0, |
| 10510 | Opcode_hwwdtlba_encode_fns, 0, 0 }, |
| 10511 | { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, |
| 10512 | 0, |
| 10513 | Opcode_rsr_cpenable_encode_fns, 0, 0 }, |
| 10514 | { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, |
| 10515 | 0, |
| 10516 | Opcode_wsr_cpenable_encode_fns, 0, 0 }, |
| 10517 | { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, |
| 10518 | 0, |
| 10519 | Opcode_xsr_cpenable_encode_fns, 0, 0 }, |
| 10520 | { "clamps", ICLASS_xt_iclass_clamp, |
| 10521 | 0, |
| 10522 | Opcode_clamps_encode_fns, 0, 0 }, |
| 10523 | { "min", ICLASS_xt_iclass_minmax, |
| 10524 | 0, |
| 10525 | Opcode_min_encode_fns, 0, 0 }, |
| 10526 | { "max", ICLASS_xt_iclass_minmax, |
| 10527 | 0, |
| 10528 | Opcode_max_encode_fns, 0, 0 }, |
| 10529 | { "minu", ICLASS_xt_iclass_minmax, |
| 10530 | 0, |
| 10531 | Opcode_minu_encode_fns, 0, 0 }, |
| 10532 | { "maxu", ICLASS_xt_iclass_minmax, |
| 10533 | 0, |
| 10534 | Opcode_maxu_encode_fns, 0, 0 }, |
| 10535 | { "nsa", ICLASS_xt_iclass_nsa, |
| 10536 | 0, |
| 10537 | Opcode_nsa_encode_fns, 0, 0 }, |
| 10538 | { "nsau", ICLASS_xt_iclass_nsa, |
| 10539 | 0, |
| 10540 | Opcode_nsau_encode_fns, 0, 0 }, |
| 10541 | { "sext", ICLASS_xt_iclass_sx, |
| 10542 | 0, |
| 10543 | Opcode_sext_encode_fns, 0, 0 }, |
| 10544 | { "l32ai", ICLASS_xt_iclass_l32ai, |
| 10545 | 0, |
| 10546 | Opcode_l32ai_encode_fns, 0, 0 }, |
| 10547 | { "s32ri", ICLASS_xt_iclass_s32ri, |
| 10548 | 0, |
| 10549 | Opcode_s32ri_encode_fns, 0, 0 }, |
| 10550 | { "s32c1i", ICLASS_xt_iclass_s32c1i, |
| 10551 | 0, |
| 10552 | Opcode_s32c1i_encode_fns, 0, 0 }, |
| 10553 | { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, |
| 10554 | 0, |
| 10555 | Opcode_rsr_scompare1_encode_fns, 0, 0 }, |
| 10556 | { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, |
| 10557 | 0, |
| 10558 | Opcode_wsr_scompare1_encode_fns, 0, 0 }, |
| 10559 | { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, |
| 10560 | 0, |
| 10561 | Opcode_xsr_scompare1_encode_fns, 0, 0 }, |
| 10562 | { "quou", ICLASS_xt_iclass_div, |
| 10563 | 0, |
| 10564 | Opcode_quou_encode_fns, 0, 0 }, |
| 10565 | { "quos", ICLASS_xt_iclass_div, |
| 10566 | 0, |
| 10567 | Opcode_quos_encode_fns, 0, 0 }, |
| 10568 | { "remu", ICLASS_xt_iclass_div, |
| 10569 | 0, |
| 10570 | Opcode_remu_encode_fns, 0, 0 }, |
| 10571 | { "rems", ICLASS_xt_iclass_div, |
| 10572 | 0, |
| 10573 | Opcode_rems_encode_fns, 0, 0 }, |
| 10574 | { "mull", ICLASS_xt_mul32, |
| 10575 | 0, |
| 10576 | Opcode_mull_encode_fns, 0, 0 } |
| 10577 | }; |
| 10578 | |
| 10579 | enum xtensa_opcode_id { |
| 10580 | OPCODE_EXCW, |
| 10581 | OPCODE_RFE, |
| 10582 | OPCODE_RFDE, |
| 10583 | OPCODE_SYSCALL, |
| 10584 | OPCODE_SIMCALL, |
| 10585 | OPCODE_CALL12, |
| 10586 | OPCODE_CALL8, |
| 10587 | OPCODE_CALL4, |
| 10588 | OPCODE_CALLX12, |
| 10589 | OPCODE_CALLX8, |
| 10590 | OPCODE_CALLX4, |
| 10591 | OPCODE_ENTRY, |
| 10592 | OPCODE_MOVSP, |
| 10593 | OPCODE_ROTW, |
| 10594 | OPCODE_RETW, |
| 10595 | OPCODE_RETW_N, |
| 10596 | OPCODE_RFWO, |
| 10597 | OPCODE_RFWU, |
| 10598 | OPCODE_L32E, |
| 10599 | OPCODE_S32E, |
| 10600 | OPCODE_RSR_WINDOWBASE, |
| 10601 | OPCODE_WSR_WINDOWBASE, |
| 10602 | OPCODE_XSR_WINDOWBASE, |
| 10603 | OPCODE_RSR_WINDOWSTART, |
| 10604 | OPCODE_WSR_WINDOWSTART, |
| 10605 | OPCODE_XSR_WINDOWSTART, |
| 10606 | OPCODE_ADD_N, |
| 10607 | OPCODE_ADDI_N, |
| 10608 | OPCODE_BEQZ_N, |
| 10609 | OPCODE_BNEZ_N, |
| 10610 | OPCODE_ILL_N, |
| 10611 | OPCODE_L32I_N, |
| 10612 | OPCODE_MOV_N, |
| 10613 | OPCODE_MOVI_N, |
| 10614 | OPCODE_NOP_N, |
| 10615 | OPCODE_RET_N, |
| 10616 | OPCODE_S32I_N, |
| 10617 | OPCODE_RUR_THREADPTR, |
| 10618 | OPCODE_WUR_THREADPTR, |
| 10619 | OPCODE_ADDI, |
| 10620 | OPCODE_ADDMI, |
| 10621 | OPCODE_ADD, |
| 10622 | OPCODE_SUB, |
| 10623 | OPCODE_ADDX2, |
| 10624 | OPCODE_ADDX4, |
| 10625 | OPCODE_ADDX8, |
| 10626 | OPCODE_SUBX2, |
| 10627 | OPCODE_SUBX4, |
| 10628 | OPCODE_SUBX8, |
| 10629 | OPCODE_AND, |
| 10630 | OPCODE_OR, |
| 10631 | OPCODE_XOR, |
| 10632 | OPCODE_BEQI, |
| 10633 | OPCODE_BNEI, |
| 10634 | OPCODE_BGEI, |
| 10635 | OPCODE_BLTI, |
| 10636 | OPCODE_BBCI, |
| 10637 | OPCODE_BBSI, |
| 10638 | OPCODE_BGEUI, |
| 10639 | OPCODE_BLTUI, |
| 10640 | OPCODE_BEQ, |
| 10641 | OPCODE_BNE, |
| 10642 | OPCODE_BGE, |
| 10643 | OPCODE_BLT, |
| 10644 | OPCODE_BGEU, |
| 10645 | OPCODE_BLTU, |
| 10646 | OPCODE_BANY, |
| 10647 | OPCODE_BNONE, |
| 10648 | OPCODE_BALL, |
| 10649 | OPCODE_BNALL, |
| 10650 | OPCODE_BBC, |
| 10651 | OPCODE_BBS, |
| 10652 | OPCODE_BEQZ, |
| 10653 | OPCODE_BNEZ, |
| 10654 | OPCODE_BGEZ, |
| 10655 | OPCODE_BLTZ, |
| 10656 | OPCODE_CALL0, |
| 10657 | OPCODE_CALLX0, |
| 10658 | OPCODE_EXTUI, |
| 10659 | OPCODE_ILL, |
| 10660 | OPCODE_J, |
| 10661 | OPCODE_JX, |
| 10662 | OPCODE_L16UI, |
| 10663 | OPCODE_L16SI, |
| 10664 | OPCODE_L32I, |
| 10665 | OPCODE_L32R, |
| 10666 | OPCODE_L8UI, |
| 10667 | OPCODE_LOOP, |
| 10668 | OPCODE_LOOPNEZ, |
| 10669 | OPCODE_LOOPGTZ, |
| 10670 | OPCODE_MOVI, |
| 10671 | OPCODE_MOVEQZ, |
| 10672 | OPCODE_MOVNEZ, |
| 10673 | OPCODE_MOVLTZ, |
| 10674 | OPCODE_MOVGEZ, |
| 10675 | OPCODE_NEG, |
| 10676 | OPCODE_ABS, |
| 10677 | OPCODE_NOP, |
| 10678 | OPCODE_RET, |
| 10679 | OPCODE_S16I, |
| 10680 | OPCODE_S32I, |
| 10681 | OPCODE_S8I, |
| 10682 | OPCODE_SSR, |
| 10683 | OPCODE_SSL, |
| 10684 | OPCODE_SSA8L, |
| 10685 | OPCODE_SSA8B, |
| 10686 | OPCODE_SSAI, |
| 10687 | OPCODE_SLL, |
| 10688 | OPCODE_SRC, |
| 10689 | OPCODE_SRL, |
| 10690 | OPCODE_SRA, |
| 10691 | OPCODE_SLLI, |
| 10692 | OPCODE_SRAI, |
| 10693 | OPCODE_SRLI, |
| 10694 | OPCODE_MEMW, |
| 10695 | OPCODE_EXTW, |
| 10696 | OPCODE_ISYNC, |
| 10697 | OPCODE_RSYNC, |
| 10698 | OPCODE_ESYNC, |
| 10699 | OPCODE_DSYNC, |
| 10700 | OPCODE_RSIL, |
| 10701 | OPCODE_RSR_LEND, |
| 10702 | OPCODE_WSR_LEND, |
| 10703 | OPCODE_XSR_LEND, |
| 10704 | OPCODE_RSR_LCOUNT, |
| 10705 | OPCODE_WSR_LCOUNT, |
| 10706 | OPCODE_XSR_LCOUNT, |
| 10707 | OPCODE_RSR_LBEG, |
| 10708 | OPCODE_WSR_LBEG, |
| 10709 | OPCODE_XSR_LBEG, |
| 10710 | OPCODE_RSR_SAR, |
| 10711 | OPCODE_WSR_SAR, |
| 10712 | OPCODE_XSR_SAR, |
| 10713 | OPCODE_RSR_LITBASE, |
| 10714 | OPCODE_WSR_LITBASE, |
| 10715 | OPCODE_XSR_LITBASE, |
| 10716 | OPCODE_RSR_176, |
| 10717 | OPCODE_WSR_176, |
| 10718 | OPCODE_RSR_208, |
| 10719 | OPCODE_RSR_PS, |
| 10720 | OPCODE_WSR_PS, |
| 10721 | OPCODE_XSR_PS, |
| 10722 | OPCODE_RSR_EPC1, |
| 10723 | OPCODE_WSR_EPC1, |
| 10724 | OPCODE_XSR_EPC1, |
| 10725 | OPCODE_RSR_EXCSAVE1, |
| 10726 | OPCODE_WSR_EXCSAVE1, |
| 10727 | OPCODE_XSR_EXCSAVE1, |
| 10728 | OPCODE_RSR_EPC2, |
| 10729 | OPCODE_WSR_EPC2, |
| 10730 | OPCODE_XSR_EPC2, |
| 10731 | OPCODE_RSR_EXCSAVE2, |
| 10732 | OPCODE_WSR_EXCSAVE2, |
| 10733 | OPCODE_XSR_EXCSAVE2, |
| 10734 | OPCODE_RSR_EPC3, |
| 10735 | OPCODE_WSR_EPC3, |
| 10736 | OPCODE_XSR_EPC3, |
| 10737 | OPCODE_RSR_EXCSAVE3, |
| 10738 | OPCODE_WSR_EXCSAVE3, |
| 10739 | OPCODE_XSR_EXCSAVE3, |
| 10740 | OPCODE_RSR_EPC4, |
| 10741 | OPCODE_WSR_EPC4, |
| 10742 | OPCODE_XSR_EPC4, |
| 10743 | OPCODE_RSR_EXCSAVE4, |
| 10744 | OPCODE_WSR_EXCSAVE4, |
| 10745 | OPCODE_XSR_EXCSAVE4, |
| 10746 | OPCODE_RSR_EPC5, |
| 10747 | OPCODE_WSR_EPC5, |
| 10748 | OPCODE_XSR_EPC5, |
| 10749 | OPCODE_RSR_EXCSAVE5, |
| 10750 | OPCODE_WSR_EXCSAVE5, |
| 10751 | OPCODE_XSR_EXCSAVE5, |
| 10752 | OPCODE_RSR_EPC6, |
| 10753 | OPCODE_WSR_EPC6, |
| 10754 | OPCODE_XSR_EPC6, |
| 10755 | OPCODE_RSR_EXCSAVE6, |
| 10756 | OPCODE_WSR_EXCSAVE6, |
| 10757 | OPCODE_XSR_EXCSAVE6, |
| 10758 | OPCODE_RSR_EPC7, |
| 10759 | OPCODE_WSR_EPC7, |
| 10760 | OPCODE_XSR_EPC7, |
| 10761 | OPCODE_RSR_EXCSAVE7, |
| 10762 | OPCODE_WSR_EXCSAVE7, |
| 10763 | OPCODE_XSR_EXCSAVE7, |
| 10764 | OPCODE_RSR_EPS2, |
| 10765 | OPCODE_WSR_EPS2, |
| 10766 | OPCODE_XSR_EPS2, |
| 10767 | OPCODE_RSR_EPS3, |
| 10768 | OPCODE_WSR_EPS3, |
| 10769 | OPCODE_XSR_EPS3, |
| 10770 | OPCODE_RSR_EPS4, |
| 10771 | OPCODE_WSR_EPS4, |
| 10772 | OPCODE_XSR_EPS4, |
| 10773 | OPCODE_RSR_EPS5, |
| 10774 | OPCODE_WSR_EPS5, |
| 10775 | OPCODE_XSR_EPS5, |
| 10776 | OPCODE_RSR_EPS6, |
| 10777 | OPCODE_WSR_EPS6, |
| 10778 | OPCODE_XSR_EPS6, |
| 10779 | OPCODE_RSR_EPS7, |
| 10780 | OPCODE_WSR_EPS7, |
| 10781 | OPCODE_XSR_EPS7, |
| 10782 | OPCODE_RSR_EXCVADDR, |
| 10783 | OPCODE_WSR_EXCVADDR, |
| 10784 | OPCODE_XSR_EXCVADDR, |
| 10785 | OPCODE_RSR_DEPC, |
| 10786 | OPCODE_WSR_DEPC, |
| 10787 | OPCODE_XSR_DEPC, |
| 10788 | OPCODE_RSR_EXCCAUSE, |
| 10789 | OPCODE_WSR_EXCCAUSE, |
| 10790 | OPCODE_XSR_EXCCAUSE, |
| 10791 | OPCODE_RSR_MISC0, |
| 10792 | OPCODE_WSR_MISC0, |
| 10793 | OPCODE_XSR_MISC0, |
| 10794 | OPCODE_RSR_MISC1, |
| 10795 | OPCODE_WSR_MISC1, |
| 10796 | OPCODE_XSR_MISC1, |
| 10797 | OPCODE_RSR_PRID, |
| 10798 | OPCODE_RSR_VECBASE, |
| 10799 | OPCODE_WSR_VECBASE, |
| 10800 | OPCODE_XSR_VECBASE, |
| 10801 | OPCODE_MUL16U, |
| 10802 | OPCODE_MUL16S, |
| 10803 | OPCODE_RFI, |
| 10804 | OPCODE_WAITI, |
| 10805 | OPCODE_RSR_INTERRUPT, |
| 10806 | OPCODE_WSR_INTSET, |
| 10807 | OPCODE_WSR_INTCLEAR, |
| 10808 | OPCODE_RSR_INTENABLE, |
| 10809 | OPCODE_WSR_INTENABLE, |
| 10810 | OPCODE_XSR_INTENABLE, |
| 10811 | OPCODE_BREAK, |
| 10812 | OPCODE_BREAK_N, |
| 10813 | OPCODE_RSR_DBREAKA0, |
| 10814 | OPCODE_WSR_DBREAKA0, |
| 10815 | OPCODE_XSR_DBREAKA0, |
| 10816 | OPCODE_RSR_DBREAKC0, |
| 10817 | OPCODE_WSR_DBREAKC0, |
| 10818 | OPCODE_XSR_DBREAKC0, |
| 10819 | OPCODE_RSR_DBREAKA1, |
| 10820 | OPCODE_WSR_DBREAKA1, |
| 10821 | OPCODE_XSR_DBREAKA1, |
| 10822 | OPCODE_RSR_DBREAKC1, |
| 10823 | OPCODE_WSR_DBREAKC1, |
| 10824 | OPCODE_XSR_DBREAKC1, |
| 10825 | OPCODE_RSR_IBREAKA0, |
| 10826 | OPCODE_WSR_IBREAKA0, |
| 10827 | OPCODE_XSR_IBREAKA0, |
| 10828 | OPCODE_RSR_IBREAKA1, |
| 10829 | OPCODE_WSR_IBREAKA1, |
| 10830 | OPCODE_XSR_IBREAKA1, |
| 10831 | OPCODE_RSR_IBREAKENABLE, |
| 10832 | OPCODE_WSR_IBREAKENABLE, |
| 10833 | OPCODE_XSR_IBREAKENABLE, |
| 10834 | OPCODE_RSR_DEBUGCAUSE, |
| 10835 | OPCODE_WSR_DEBUGCAUSE, |
| 10836 | OPCODE_XSR_DEBUGCAUSE, |
| 10837 | OPCODE_RSR_ICOUNT, |
| 10838 | OPCODE_WSR_ICOUNT, |
| 10839 | OPCODE_XSR_ICOUNT, |
| 10840 | OPCODE_RSR_ICOUNTLEVEL, |
| 10841 | OPCODE_WSR_ICOUNTLEVEL, |
| 10842 | OPCODE_XSR_ICOUNTLEVEL, |
| 10843 | OPCODE_RSR_DDR, |
| 10844 | OPCODE_WSR_DDR, |
| 10845 | OPCODE_XSR_DDR, |
| 10846 | OPCODE_RFDO, |
| 10847 | OPCODE_RFDD, |
| 10848 | OPCODE_WSR_MMID, |
| 10849 | OPCODE_RSR_CCOUNT, |
| 10850 | OPCODE_WSR_CCOUNT, |
| 10851 | OPCODE_XSR_CCOUNT, |
| 10852 | OPCODE_RSR_CCOMPARE0, |
| 10853 | OPCODE_WSR_CCOMPARE0, |
| 10854 | OPCODE_XSR_CCOMPARE0, |
| 10855 | OPCODE_RSR_CCOMPARE1, |
| 10856 | OPCODE_WSR_CCOMPARE1, |
| 10857 | OPCODE_XSR_CCOMPARE1, |
| 10858 | OPCODE_RSR_CCOMPARE2, |
| 10859 | OPCODE_WSR_CCOMPARE2, |
| 10860 | OPCODE_XSR_CCOMPARE2, |
| 10861 | OPCODE_IPF, |
| 10862 | OPCODE_IHI, |
| 10863 | OPCODE_IPFL, |
| 10864 | OPCODE_IHU, |
| 10865 | OPCODE_IIU, |
| 10866 | OPCODE_III, |
| 10867 | OPCODE_LICT, |
| 10868 | OPCODE_LICW, |
| 10869 | OPCODE_SICT, |
| 10870 | OPCODE_SICW, |
| 10871 | OPCODE_DHWB, |
| 10872 | OPCODE_DHWBI, |
| 10873 | OPCODE_DIWB, |
| 10874 | OPCODE_DIWBI, |
| 10875 | OPCODE_DHI, |
| 10876 | OPCODE_DII, |
| 10877 | OPCODE_DPFR, |
| 10878 | OPCODE_DPFW, |
| 10879 | OPCODE_DPFRO, |
| 10880 | OPCODE_DPFWO, |
| 10881 | OPCODE_DPFL, |
| 10882 | OPCODE_DHU, |
| 10883 | OPCODE_DIU, |
| 10884 | OPCODE_SDCT, |
| 10885 | OPCODE_LDCT, |
| 10886 | OPCODE_WSR_PTEVADDR, |
| 10887 | OPCODE_RSR_PTEVADDR, |
| 10888 | OPCODE_XSR_PTEVADDR, |
| 10889 | OPCODE_RSR_RASID, |
| 10890 | OPCODE_WSR_RASID, |
| 10891 | OPCODE_XSR_RASID, |
| 10892 | OPCODE_RSR_ITLBCFG, |
| 10893 | OPCODE_WSR_ITLBCFG, |
| 10894 | OPCODE_XSR_ITLBCFG, |
| 10895 | OPCODE_RSR_DTLBCFG, |
| 10896 | OPCODE_WSR_DTLBCFG, |
| 10897 | OPCODE_XSR_DTLBCFG, |
| 10898 | OPCODE_IDTLB, |
| 10899 | OPCODE_PDTLB, |
| 10900 | OPCODE_RDTLB0, |
| 10901 | OPCODE_RDTLB1, |
| 10902 | OPCODE_WDTLB, |
| 10903 | OPCODE_IITLB, |
| 10904 | OPCODE_PITLB, |
| 10905 | OPCODE_RITLB0, |
| 10906 | OPCODE_RITLB1, |
| 10907 | OPCODE_WITLB, |
| 10908 | OPCODE_LDPTE, |
| 10909 | OPCODE_HWWITLBA, |
| 10910 | OPCODE_HWWDTLBA, |
| 10911 | OPCODE_RSR_CPENABLE, |
| 10912 | OPCODE_WSR_CPENABLE, |
| 10913 | OPCODE_XSR_CPENABLE, |
| 10914 | OPCODE_CLAMPS, |
| 10915 | OPCODE_MIN, |
| 10916 | OPCODE_MAX, |
| 10917 | OPCODE_MINU, |
| 10918 | OPCODE_MAXU, |
| 10919 | OPCODE_NSA, |
| 10920 | OPCODE_NSAU, |
| 10921 | OPCODE_SEXT, |
| 10922 | OPCODE_L32AI, |
| 10923 | OPCODE_S32RI, |
| 10924 | OPCODE_S32C1I, |
| 10925 | OPCODE_RSR_SCOMPARE1, |
| 10926 | OPCODE_WSR_SCOMPARE1, |
| 10927 | OPCODE_XSR_SCOMPARE1, |
| 10928 | OPCODE_QUOU, |
| 10929 | OPCODE_QUOS, |
| 10930 | OPCODE_REMU, |
| 10931 | OPCODE_REMS, |
| 10932 | OPCODE_MULL |
| 10933 | }; |
| 10934 | |
| 10935 | \f |
| 10936 | /* Slot-specific opcode decode functions. */ |
| 10937 | |
| 10938 | static int |
| 10939 | Slot_inst_decode (const xtensa_insnbuf insn) |
| 10940 | { |
| 10941 | switch (Field_op0_Slot_inst_get (insn)) |
| 10942 | { |
| 10943 | case 0: |
| 10944 | switch (Field_op1_Slot_inst_get (insn)) |
| 10945 | { |
| 10946 | case 0: |
| 10947 | switch (Field_op2_Slot_inst_get (insn)) |
| 10948 | { |
| 10949 | case 0: |
| 10950 | switch (Field_r_Slot_inst_get (insn)) |
| 10951 | { |
| 10952 | case 0: |
| 10953 | switch (Field_m_Slot_inst_get (insn)) |
| 10954 | { |
| 10955 | case 0: |
| 10956 | if (Field_s_Slot_inst_get (insn) == 0 && |
| 10957 | Field_n_Slot_inst_get (insn) == 0) |
| 10958 | return OPCODE_ILL; |
| 10959 | break; |
| 10960 | case 2: |
| 10961 | switch (Field_n_Slot_inst_get (insn)) |
| 10962 | { |
| 10963 | case 0: |
| 10964 | return OPCODE_RET; |
| 10965 | case 1: |
| 10966 | return OPCODE_RETW; |
| 10967 | case 2: |
| 10968 | return OPCODE_JX; |
| 10969 | } |
| 10970 | break; |
| 10971 | case 3: |
| 10972 | switch (Field_n_Slot_inst_get (insn)) |
| 10973 | { |
| 10974 | case 0: |
| 10975 | return OPCODE_CALLX0; |
| 10976 | case 1: |
| 10977 | return OPCODE_CALLX4; |
| 10978 | case 2: |
| 10979 | return OPCODE_CALLX8; |
| 10980 | case 3: |
| 10981 | return OPCODE_CALLX12; |
| 10982 | } |
| 10983 | break; |
| 10984 | } |
| 10985 | break; |
| 10986 | case 1: |
| 10987 | return OPCODE_MOVSP; |
| 10988 | case 2: |
| 10989 | if (Field_s_Slot_inst_get (insn) == 0) |
| 10990 | { |
| 10991 | switch (Field_t_Slot_inst_get (insn)) |
| 10992 | { |
| 10993 | case 0: |
| 10994 | return OPCODE_ISYNC; |
| 10995 | case 1: |
| 10996 | return OPCODE_RSYNC; |
| 10997 | case 2: |
| 10998 | return OPCODE_ESYNC; |
| 10999 | case 3: |
| 11000 | return OPCODE_DSYNC; |
| 11001 | case 8: |
| 11002 | return OPCODE_EXCW; |
| 11003 | case 12: |
| 11004 | return OPCODE_MEMW; |
| 11005 | case 13: |
| 11006 | return OPCODE_EXTW; |
| 11007 | case 15: |
| 11008 | return OPCODE_NOP; |
| 11009 | } |
| 11010 | } |
| 11011 | break; |
| 11012 | case 3: |
| 11013 | switch (Field_t_Slot_inst_get (insn)) |
| 11014 | { |
| 11015 | case 0: |
| 11016 | switch (Field_s_Slot_inst_get (insn)) |
| 11017 | { |
| 11018 | case 0: |
| 11019 | return OPCODE_RFE; |
| 11020 | case 2: |
| 11021 | return OPCODE_RFDE; |
| 11022 | case 4: |
| 11023 | return OPCODE_RFWO; |
| 11024 | case 5: |
| 11025 | return OPCODE_RFWU; |
| 11026 | } |
| 11027 | break; |
| 11028 | case 1: |
| 11029 | return OPCODE_RFI; |
| 11030 | } |
| 11031 | break; |
| 11032 | case 4: |
| 11033 | return OPCODE_BREAK; |
| 11034 | case 5: |
| 11035 | switch (Field_s_Slot_inst_get (insn)) |
| 11036 | { |
| 11037 | case 0: |
| 11038 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11039 | return OPCODE_SYSCALL; |
| 11040 | break; |
| 11041 | case 1: |
| 11042 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11043 | return OPCODE_SIMCALL; |
| 11044 | break; |
| 11045 | } |
| 11046 | break; |
| 11047 | case 6: |
| 11048 | return OPCODE_RSIL; |
| 11049 | case 7: |
| 11050 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11051 | return OPCODE_WAITI; |
| 11052 | break; |
| 11053 | } |
| 11054 | break; |
| 11055 | case 1: |
| 11056 | return OPCODE_AND; |
| 11057 | case 2: |
| 11058 | return OPCODE_OR; |
| 11059 | case 3: |
| 11060 | return OPCODE_XOR; |
| 11061 | case 4: |
| 11062 | switch (Field_r_Slot_inst_get (insn)) |
| 11063 | { |
| 11064 | case 0: |
| 11065 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11066 | return OPCODE_SSR; |
| 11067 | break; |
| 11068 | case 1: |
| 11069 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11070 | return OPCODE_SSL; |
| 11071 | break; |
| 11072 | case 2: |
| 11073 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11074 | return OPCODE_SSA8L; |
| 11075 | break; |
| 11076 | case 3: |
| 11077 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11078 | return OPCODE_SSA8B; |
| 11079 | break; |
| 11080 | case 4: |
| 11081 | if (Field_thi3_Slot_inst_get (insn) == 0) |
| 11082 | return OPCODE_SSAI; |
| 11083 | break; |
| 11084 | case 8: |
| 11085 | if (Field_s_Slot_inst_get (insn) == 0) |
| 11086 | return OPCODE_ROTW; |
| 11087 | break; |
| 11088 | case 14: |
| 11089 | return OPCODE_NSA; |
| 11090 | case 15: |
| 11091 | return OPCODE_NSAU; |
| 11092 | } |
| 11093 | break; |
| 11094 | case 5: |
| 11095 | switch (Field_r_Slot_inst_get (insn)) |
| 11096 | { |
| 11097 | case 1: |
| 11098 | return OPCODE_HWWITLBA; |
| 11099 | case 3: |
| 11100 | return OPCODE_RITLB0; |
| 11101 | case 4: |
| 11102 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11103 | return OPCODE_IITLB; |
| 11104 | break; |
| 11105 | case 5: |
| 11106 | return OPCODE_PITLB; |
| 11107 | case 6: |
| 11108 | return OPCODE_WITLB; |
| 11109 | case 7: |
| 11110 | return OPCODE_RITLB1; |
| 11111 | case 9: |
| 11112 | return OPCODE_HWWDTLBA; |
| 11113 | case 11: |
| 11114 | return OPCODE_RDTLB0; |
| 11115 | case 12: |
| 11116 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11117 | return OPCODE_IDTLB; |
| 11118 | break; |
| 11119 | case 13: |
| 11120 | return OPCODE_PDTLB; |
| 11121 | case 14: |
| 11122 | return OPCODE_WDTLB; |
| 11123 | case 15: |
| 11124 | return OPCODE_RDTLB1; |
| 11125 | } |
| 11126 | break; |
| 11127 | case 6: |
| 11128 | switch (Field_s_Slot_inst_get (insn)) |
| 11129 | { |
| 11130 | case 0: |
| 11131 | return OPCODE_NEG; |
| 11132 | case 1: |
| 11133 | return OPCODE_ABS; |
| 11134 | } |
| 11135 | break; |
| 11136 | case 8: |
| 11137 | return OPCODE_ADD; |
| 11138 | case 9: |
| 11139 | return OPCODE_ADDX2; |
| 11140 | case 10: |
| 11141 | return OPCODE_ADDX4; |
| 11142 | case 11: |
| 11143 | return OPCODE_ADDX8; |
| 11144 | case 12: |
| 11145 | return OPCODE_SUB; |
| 11146 | case 13: |
| 11147 | return OPCODE_SUBX2; |
| 11148 | case 14: |
| 11149 | return OPCODE_SUBX4; |
| 11150 | case 15: |
| 11151 | return OPCODE_SUBX8; |
| 11152 | } |
| 11153 | break; |
| 11154 | case 1: |
| 11155 | switch (Field_op2_Slot_inst_get (insn)) |
| 11156 | { |
| 11157 | case 0: |
| 11158 | case 1: |
| 11159 | return OPCODE_SLLI; |
| 11160 | case 2: |
| 11161 | case 3: |
| 11162 | return OPCODE_SRAI; |
| 11163 | case 4: |
| 11164 | return OPCODE_SRLI; |
| 11165 | case 6: |
| 11166 | switch (Field_sr_Slot_inst_get (insn)) |
| 11167 | { |
| 11168 | case 0: |
| 11169 | return OPCODE_XSR_LBEG; |
| 11170 | case 1: |
| 11171 | return OPCODE_XSR_LEND; |
| 11172 | case 2: |
| 11173 | return OPCODE_XSR_LCOUNT; |
| 11174 | case 3: |
| 11175 | return OPCODE_XSR_SAR; |
| 11176 | case 5: |
| 11177 | return OPCODE_XSR_LITBASE; |
| 11178 | case 12: |
| 11179 | return OPCODE_XSR_SCOMPARE1; |
| 11180 | case 72: |
| 11181 | return OPCODE_XSR_WINDOWBASE; |
| 11182 | case 73: |
| 11183 | return OPCODE_XSR_WINDOWSTART; |
| 11184 | case 83: |
| 11185 | return OPCODE_XSR_PTEVADDR; |
| 11186 | case 90: |
| 11187 | return OPCODE_XSR_RASID; |
| 11188 | case 91: |
| 11189 | return OPCODE_XSR_ITLBCFG; |
| 11190 | case 92: |
| 11191 | return OPCODE_XSR_DTLBCFG; |
| 11192 | case 96: |
| 11193 | return OPCODE_XSR_IBREAKENABLE; |
| 11194 | case 104: |
| 11195 | return OPCODE_XSR_DDR; |
| 11196 | case 128: |
| 11197 | return OPCODE_XSR_IBREAKA0; |
| 11198 | case 129: |
| 11199 | return OPCODE_XSR_IBREAKA1; |
| 11200 | case 144: |
| 11201 | return OPCODE_XSR_DBREAKA0; |
| 11202 | case 145: |
| 11203 | return OPCODE_XSR_DBREAKA1; |
| 11204 | case 160: |
| 11205 | return OPCODE_XSR_DBREAKC0; |
| 11206 | case 161: |
| 11207 | return OPCODE_XSR_DBREAKC1; |
| 11208 | case 177: |
| 11209 | return OPCODE_XSR_EPC1; |
| 11210 | case 178: |
| 11211 | return OPCODE_XSR_EPC2; |
| 11212 | case 179: |
| 11213 | return OPCODE_XSR_EPC3; |
| 11214 | case 180: |
| 11215 | return OPCODE_XSR_EPC4; |
| 11216 | case 181: |
| 11217 | return OPCODE_XSR_EPC5; |
| 11218 | case 182: |
| 11219 | return OPCODE_XSR_EPC6; |
| 11220 | case 183: |
| 11221 | return OPCODE_XSR_EPC7; |
| 11222 | case 192: |
| 11223 | return OPCODE_XSR_DEPC; |
| 11224 | case 194: |
| 11225 | return OPCODE_XSR_EPS2; |
| 11226 | case 195: |
| 11227 | return OPCODE_XSR_EPS3; |
| 11228 | case 196: |
| 11229 | return OPCODE_XSR_EPS4; |
| 11230 | case 197: |
| 11231 | return OPCODE_XSR_EPS5; |
| 11232 | case 198: |
| 11233 | return OPCODE_XSR_EPS6; |
| 11234 | case 199: |
| 11235 | return OPCODE_XSR_EPS7; |
| 11236 | case 209: |
| 11237 | return OPCODE_XSR_EXCSAVE1; |
| 11238 | case 210: |
| 11239 | return OPCODE_XSR_EXCSAVE2; |
| 11240 | case 211: |
| 11241 | return OPCODE_XSR_EXCSAVE3; |
| 11242 | case 212: |
| 11243 | return OPCODE_XSR_EXCSAVE4; |
| 11244 | case 213: |
| 11245 | return OPCODE_XSR_EXCSAVE5; |
| 11246 | case 214: |
| 11247 | return OPCODE_XSR_EXCSAVE6; |
| 11248 | case 215: |
| 11249 | return OPCODE_XSR_EXCSAVE7; |
| 11250 | case 224: |
| 11251 | return OPCODE_XSR_CPENABLE; |
| 11252 | case 228: |
| 11253 | return OPCODE_XSR_INTENABLE; |
| 11254 | case 230: |
| 11255 | return OPCODE_XSR_PS; |
| 11256 | case 231: |
| 11257 | return OPCODE_XSR_VECBASE; |
| 11258 | case 232: |
| 11259 | return OPCODE_XSR_EXCCAUSE; |
| 11260 | case 233: |
| 11261 | return OPCODE_XSR_DEBUGCAUSE; |
| 11262 | case 234: |
| 11263 | return OPCODE_XSR_CCOUNT; |
| 11264 | case 236: |
| 11265 | return OPCODE_XSR_ICOUNT; |
| 11266 | case 237: |
| 11267 | return OPCODE_XSR_ICOUNTLEVEL; |
| 11268 | case 238: |
| 11269 | return OPCODE_XSR_EXCVADDR; |
| 11270 | case 240: |
| 11271 | return OPCODE_XSR_CCOMPARE0; |
| 11272 | case 241: |
| 11273 | return OPCODE_XSR_CCOMPARE1; |
| 11274 | case 242: |
| 11275 | return OPCODE_XSR_CCOMPARE2; |
| 11276 | case 244: |
| 11277 | return OPCODE_XSR_MISC0; |
| 11278 | case 245: |
| 11279 | return OPCODE_XSR_MISC1; |
| 11280 | } |
| 11281 | break; |
| 11282 | case 8: |
| 11283 | return OPCODE_SRC; |
| 11284 | case 9: |
| 11285 | if (Field_s_Slot_inst_get (insn) == 0) |
| 11286 | return OPCODE_SRL; |
| 11287 | break; |
| 11288 | case 10: |
| 11289 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11290 | return OPCODE_SLL; |
| 11291 | break; |
| 11292 | case 11: |
| 11293 | if (Field_s_Slot_inst_get (insn) == 0) |
| 11294 | return OPCODE_SRA; |
| 11295 | break; |
| 11296 | case 12: |
| 11297 | return OPCODE_MUL16U; |
| 11298 | case 13: |
| 11299 | return OPCODE_MUL16S; |
| 11300 | case 15: |
| 11301 | switch (Field_r_Slot_inst_get (insn)) |
| 11302 | { |
| 11303 | case 0: |
| 11304 | return OPCODE_LICT; |
| 11305 | case 1: |
| 11306 | return OPCODE_SICT; |
| 11307 | case 2: |
| 11308 | return OPCODE_LICW; |
| 11309 | case 3: |
| 11310 | return OPCODE_SICW; |
| 11311 | case 8: |
| 11312 | return OPCODE_LDCT; |
| 11313 | case 9: |
| 11314 | return OPCODE_SDCT; |
| 11315 | case 14: |
| 11316 | if (Field_t_Slot_inst_get (insn) == 0) |
| 11317 | return OPCODE_RFDO; |
| 11318 | if (Field_t_Slot_inst_get (insn) == 1) |
| 11319 | return OPCODE_RFDD; |
| 11320 | break; |
| 11321 | case 15: |
| 11322 | return OPCODE_LDPTE; |
| 11323 | } |
| 11324 | break; |
| 11325 | } |
| 11326 | break; |
| 11327 | case 2: |
| 11328 | switch (Field_op2_Slot_inst_get (insn)) |
| 11329 | { |
| 11330 | case 8: |
| 11331 | return OPCODE_MULL; |
| 11332 | case 12: |
| 11333 | return OPCODE_QUOU; |
| 11334 | case 13: |
| 11335 | return OPCODE_QUOS; |
| 11336 | case 14: |
| 11337 | return OPCODE_REMU; |
| 11338 | case 15: |
| 11339 | return OPCODE_REMS; |
| 11340 | } |
| 11341 | break; |
| 11342 | case 3: |
| 11343 | switch (Field_op2_Slot_inst_get (insn)) |
| 11344 | { |
| 11345 | case 0: |
| 11346 | switch (Field_sr_Slot_inst_get (insn)) |
| 11347 | { |
| 11348 | case 0: |
| 11349 | return OPCODE_RSR_LBEG; |
| 11350 | case 1: |
| 11351 | return OPCODE_RSR_LEND; |
| 11352 | case 2: |
| 11353 | return OPCODE_RSR_LCOUNT; |
| 11354 | case 3: |
| 11355 | return OPCODE_RSR_SAR; |
| 11356 | case 5: |
| 11357 | return OPCODE_RSR_LITBASE; |
| 11358 | case 12: |
| 11359 | return OPCODE_RSR_SCOMPARE1; |
| 11360 | case 72: |
| 11361 | return OPCODE_RSR_WINDOWBASE; |
| 11362 | case 73: |
| 11363 | return OPCODE_RSR_WINDOWSTART; |
| 11364 | case 83: |
| 11365 | return OPCODE_RSR_PTEVADDR; |
| 11366 | case 90: |
| 11367 | return OPCODE_RSR_RASID; |
| 11368 | case 91: |
| 11369 | return OPCODE_RSR_ITLBCFG; |
| 11370 | case 92: |
| 11371 | return OPCODE_RSR_DTLBCFG; |
| 11372 | case 96: |
| 11373 | return OPCODE_RSR_IBREAKENABLE; |
| 11374 | case 104: |
| 11375 | return OPCODE_RSR_DDR; |
| 11376 | case 128: |
| 11377 | return OPCODE_RSR_IBREAKA0; |
| 11378 | case 129: |
| 11379 | return OPCODE_RSR_IBREAKA1; |
| 11380 | case 144: |
| 11381 | return OPCODE_RSR_DBREAKA0; |
| 11382 | case 145: |
| 11383 | return OPCODE_RSR_DBREAKA1; |
| 11384 | case 160: |
| 11385 | return OPCODE_RSR_DBREAKC0; |
| 11386 | case 161: |
| 11387 | return OPCODE_RSR_DBREAKC1; |
| 11388 | case 176: |
| 11389 | return OPCODE_RSR_176; |
| 11390 | case 177: |
| 11391 | return OPCODE_RSR_EPC1; |
| 11392 | case 178: |
| 11393 | return OPCODE_RSR_EPC2; |
| 11394 | case 179: |
| 11395 | return OPCODE_RSR_EPC3; |
| 11396 | case 180: |
| 11397 | return OPCODE_RSR_EPC4; |
| 11398 | case 181: |
| 11399 | return OPCODE_RSR_EPC5; |
| 11400 | case 182: |
| 11401 | return OPCODE_RSR_EPC6; |
| 11402 | case 183: |
| 11403 | return OPCODE_RSR_EPC7; |
| 11404 | case 192: |
| 11405 | return OPCODE_RSR_DEPC; |
| 11406 | case 194: |
| 11407 | return OPCODE_RSR_EPS2; |
| 11408 | case 195: |
| 11409 | return OPCODE_RSR_EPS3; |
| 11410 | case 196: |
| 11411 | return OPCODE_RSR_EPS4; |
| 11412 | case 197: |
| 11413 | return OPCODE_RSR_EPS5; |
| 11414 | case 198: |
| 11415 | return OPCODE_RSR_EPS6; |
| 11416 | case 199: |
| 11417 | return OPCODE_RSR_EPS7; |
| 11418 | case 208: |
| 11419 | return OPCODE_RSR_208; |
| 11420 | case 209: |
| 11421 | return OPCODE_RSR_EXCSAVE1; |
| 11422 | case 210: |
| 11423 | return OPCODE_RSR_EXCSAVE2; |
| 11424 | case 211: |
| 11425 | return OPCODE_RSR_EXCSAVE3; |
| 11426 | case 212: |
| 11427 | return OPCODE_RSR_EXCSAVE4; |
| 11428 | case 213: |
| 11429 | return OPCODE_RSR_EXCSAVE5; |
| 11430 | case 214: |
| 11431 | return OPCODE_RSR_EXCSAVE6; |
| 11432 | case 215: |
| 11433 | return OPCODE_RSR_EXCSAVE7; |
| 11434 | case 224: |
| 11435 | return OPCODE_RSR_CPENABLE; |
| 11436 | case 226: |
| 11437 | return OPCODE_RSR_INTERRUPT; |
| 11438 | case 228: |
| 11439 | return OPCODE_RSR_INTENABLE; |
| 11440 | case 230: |
| 11441 | return OPCODE_RSR_PS; |
| 11442 | case 231: |
| 11443 | return OPCODE_RSR_VECBASE; |
| 11444 | case 232: |
| 11445 | return OPCODE_RSR_EXCCAUSE; |
| 11446 | case 233: |
| 11447 | return OPCODE_RSR_DEBUGCAUSE; |
| 11448 | case 234: |
| 11449 | return OPCODE_RSR_CCOUNT; |
| 11450 | case 235: |
| 11451 | return OPCODE_RSR_PRID; |
| 11452 | case 236: |
| 11453 | return OPCODE_RSR_ICOUNT; |
| 11454 | case 237: |
| 11455 | return OPCODE_RSR_ICOUNTLEVEL; |
| 11456 | case 238: |
| 11457 | return OPCODE_RSR_EXCVADDR; |
| 11458 | case 240: |
| 11459 | return OPCODE_RSR_CCOMPARE0; |
| 11460 | case 241: |
| 11461 | return OPCODE_RSR_CCOMPARE1; |
| 11462 | case 242: |
| 11463 | return OPCODE_RSR_CCOMPARE2; |
| 11464 | case 244: |
| 11465 | return OPCODE_RSR_MISC0; |
| 11466 | case 245: |
| 11467 | return OPCODE_RSR_MISC1; |
| 11468 | } |
| 11469 | break; |
| 11470 | case 1: |
| 11471 | switch (Field_sr_Slot_inst_get (insn)) |
| 11472 | { |
| 11473 | case 0: |
| 11474 | return OPCODE_WSR_LBEG; |
| 11475 | case 1: |
| 11476 | return OPCODE_WSR_LEND; |
| 11477 | case 2: |
| 11478 | return OPCODE_WSR_LCOUNT; |
| 11479 | case 3: |
| 11480 | return OPCODE_WSR_SAR; |
| 11481 | case 5: |
| 11482 | return OPCODE_WSR_LITBASE; |
| 11483 | case 12: |
| 11484 | return OPCODE_WSR_SCOMPARE1; |
| 11485 | case 72: |
| 11486 | return OPCODE_WSR_WINDOWBASE; |
| 11487 | case 73: |
| 11488 | return OPCODE_WSR_WINDOWSTART; |
| 11489 | case 83: |
| 11490 | return OPCODE_WSR_PTEVADDR; |
| 11491 | case 89: |
| 11492 | return OPCODE_WSR_MMID; |
| 11493 | case 90: |
| 11494 | return OPCODE_WSR_RASID; |
| 11495 | case 91: |
| 11496 | return OPCODE_WSR_ITLBCFG; |
| 11497 | case 92: |
| 11498 | return OPCODE_WSR_DTLBCFG; |
| 11499 | case 96: |
| 11500 | return OPCODE_WSR_IBREAKENABLE; |
| 11501 | case 104: |
| 11502 | return OPCODE_WSR_DDR; |
| 11503 | case 128: |
| 11504 | return OPCODE_WSR_IBREAKA0; |
| 11505 | case 129: |
| 11506 | return OPCODE_WSR_IBREAKA1; |
| 11507 | case 144: |
| 11508 | return OPCODE_WSR_DBREAKA0; |
| 11509 | case 145: |
| 11510 | return OPCODE_WSR_DBREAKA1; |
| 11511 | case 160: |
| 11512 | return OPCODE_WSR_DBREAKC0; |
| 11513 | case 161: |
| 11514 | return OPCODE_WSR_DBREAKC1; |
| 11515 | case 176: |
| 11516 | return OPCODE_WSR_176; |
| 11517 | case 177: |
| 11518 | return OPCODE_WSR_EPC1; |
| 11519 | case 178: |
| 11520 | return OPCODE_WSR_EPC2; |
| 11521 | case 179: |
| 11522 | return OPCODE_WSR_EPC3; |
| 11523 | case 180: |
| 11524 | return OPCODE_WSR_EPC4; |
| 11525 | case 181: |
| 11526 | return OPCODE_WSR_EPC5; |
| 11527 | case 182: |
| 11528 | return OPCODE_WSR_EPC6; |
| 11529 | case 183: |
| 11530 | return OPCODE_WSR_EPC7; |
| 11531 | case 192: |
| 11532 | return OPCODE_WSR_DEPC; |
| 11533 | case 194: |
| 11534 | return OPCODE_WSR_EPS2; |
| 11535 | case 195: |
| 11536 | return OPCODE_WSR_EPS3; |
| 11537 | case 196: |
| 11538 | return OPCODE_WSR_EPS4; |
| 11539 | case 197: |
| 11540 | return OPCODE_WSR_EPS5; |
| 11541 | case 198: |
| 11542 | return OPCODE_WSR_EPS6; |
| 11543 | case 199: |
| 11544 | return OPCODE_WSR_EPS7; |
| 11545 | case 209: |
| 11546 | return OPCODE_WSR_EXCSAVE1; |
| 11547 | case 210: |
| 11548 | return OPCODE_WSR_EXCSAVE2; |
| 11549 | case 211: |
| 11550 | return OPCODE_WSR_EXCSAVE3; |
| 11551 | case 212: |
| 11552 | return OPCODE_WSR_EXCSAVE4; |
| 11553 | case 213: |
| 11554 | return OPCODE_WSR_EXCSAVE5; |
| 11555 | case 214: |
| 11556 | return OPCODE_WSR_EXCSAVE6; |
| 11557 | case 215: |
| 11558 | return OPCODE_WSR_EXCSAVE7; |
| 11559 | case 224: |
| 11560 | return OPCODE_WSR_CPENABLE; |
| 11561 | case 226: |
| 11562 | return OPCODE_WSR_INTSET; |
| 11563 | case 227: |
| 11564 | return OPCODE_WSR_INTCLEAR; |
| 11565 | case 228: |
| 11566 | return OPCODE_WSR_INTENABLE; |
| 11567 | case 230: |
| 11568 | return OPCODE_WSR_PS; |
| 11569 | case 231: |
| 11570 | return OPCODE_WSR_VECBASE; |
| 11571 | case 232: |
| 11572 | return OPCODE_WSR_EXCCAUSE; |
| 11573 | case 233: |
| 11574 | return OPCODE_WSR_DEBUGCAUSE; |
| 11575 | case 234: |
| 11576 | return OPCODE_WSR_CCOUNT; |
| 11577 | case 236: |
| 11578 | return OPCODE_WSR_ICOUNT; |
| 11579 | case 237: |
| 11580 | return OPCODE_WSR_ICOUNTLEVEL; |
| 11581 | case 238: |
| 11582 | return OPCODE_WSR_EXCVADDR; |
| 11583 | case 240: |
| 11584 | return OPCODE_WSR_CCOMPARE0; |
| 11585 | case 241: |
| 11586 | return OPCODE_WSR_CCOMPARE1; |
| 11587 | case 242: |
| 11588 | return OPCODE_WSR_CCOMPARE2; |
| 11589 | case 244: |
| 11590 | return OPCODE_WSR_MISC0; |
| 11591 | case 245: |
| 11592 | return OPCODE_WSR_MISC1; |
| 11593 | } |
| 11594 | break; |
| 11595 | case 2: |
| 11596 | return OPCODE_SEXT; |
| 11597 | case 3: |
| 11598 | return OPCODE_CLAMPS; |
| 11599 | case 4: |
| 11600 | return OPCODE_MIN; |
| 11601 | case 5: |
| 11602 | return OPCODE_MAX; |
| 11603 | case 6: |
| 11604 | return OPCODE_MINU; |
| 11605 | case 7: |
| 11606 | return OPCODE_MAXU; |
| 11607 | case 8: |
| 11608 | return OPCODE_MOVEQZ; |
| 11609 | case 9: |
| 11610 | return OPCODE_MOVNEZ; |
| 11611 | case 10: |
| 11612 | return OPCODE_MOVLTZ; |
| 11613 | case 11: |
| 11614 | return OPCODE_MOVGEZ; |
| 11615 | case 14: |
| 11616 | if (Field_st_Slot_inst_get (insn) == 231) |
| 11617 | return OPCODE_RUR_THREADPTR; |
| 11618 | break; |
| 11619 | case 15: |
| 11620 | if (Field_sr_Slot_inst_get (insn) == 231) |
| 11621 | return OPCODE_WUR_THREADPTR; |
| 11622 | break; |
| 11623 | } |
| 11624 | break; |
| 11625 | case 4: |
| 11626 | case 5: |
| 11627 | return OPCODE_EXTUI; |
| 11628 | case 9: |
| 11629 | switch (Field_op2_Slot_inst_get (insn)) |
| 11630 | { |
| 11631 | case 0: |
| 11632 | return OPCODE_L32E; |
| 11633 | case 4: |
| 11634 | return OPCODE_S32E; |
| 11635 | } |
| 11636 | break; |
| 11637 | } |
| 11638 | break; |
| 11639 | case 1: |
| 11640 | return OPCODE_L32R; |
| 11641 | case 2: |
| 11642 | switch (Field_r_Slot_inst_get (insn)) |
| 11643 | { |
| 11644 | case 0: |
| 11645 | return OPCODE_L8UI; |
| 11646 | case 1: |
| 11647 | return OPCODE_L16UI; |
| 11648 | case 2: |
| 11649 | return OPCODE_L32I; |
| 11650 | case 4: |
| 11651 | return OPCODE_S8I; |
| 11652 | case 5: |
| 11653 | return OPCODE_S16I; |
| 11654 | case 6: |
| 11655 | return OPCODE_S32I; |
| 11656 | case 7: |
| 11657 | switch (Field_t_Slot_inst_get (insn)) |
| 11658 | { |
| 11659 | case 0: |
| 11660 | return OPCODE_DPFR; |
| 11661 | case 1: |
| 11662 | return OPCODE_DPFW; |
| 11663 | case 2: |
| 11664 | return OPCODE_DPFRO; |
| 11665 | case 3: |
| 11666 | return OPCODE_DPFWO; |
| 11667 | case 4: |
| 11668 | return OPCODE_DHWB; |
| 11669 | case 5: |
| 11670 | return OPCODE_DHWBI; |
| 11671 | case 6: |
| 11672 | return OPCODE_DHI; |
| 11673 | case 7: |
| 11674 | return OPCODE_DII; |
| 11675 | case 8: |
| 11676 | switch (Field_op1_Slot_inst_get (insn)) |
| 11677 | { |
| 11678 | case 0: |
| 11679 | return OPCODE_DPFL; |
| 11680 | case 2: |
| 11681 | return OPCODE_DHU; |
| 11682 | case 3: |
| 11683 | return OPCODE_DIU; |
| 11684 | case 4: |
| 11685 | return OPCODE_DIWB; |
| 11686 | case 5: |
| 11687 | return OPCODE_DIWBI; |
| 11688 | } |
| 11689 | break; |
| 11690 | case 12: |
| 11691 | return OPCODE_IPF; |
| 11692 | case 13: |
| 11693 | switch (Field_op1_Slot_inst_get (insn)) |
| 11694 | { |
| 11695 | case 0: |
| 11696 | return OPCODE_IPFL; |
| 11697 | case 2: |
| 11698 | return OPCODE_IHU; |
| 11699 | case 3: |
| 11700 | return OPCODE_IIU; |
| 11701 | } |
| 11702 | break; |
| 11703 | case 14: |
| 11704 | return OPCODE_IHI; |
| 11705 | case 15: |
| 11706 | return OPCODE_III; |
| 11707 | } |
| 11708 | break; |
| 11709 | case 9: |
| 11710 | return OPCODE_L16SI; |
| 11711 | case 10: |
| 11712 | return OPCODE_MOVI; |
| 11713 | case 11: |
| 11714 | return OPCODE_L32AI; |
| 11715 | case 12: |
| 11716 | return OPCODE_ADDI; |
| 11717 | case 13: |
| 11718 | return OPCODE_ADDMI; |
| 11719 | case 14: |
| 11720 | return OPCODE_S32C1I; |
| 11721 | case 15: |
| 11722 | return OPCODE_S32RI; |
| 11723 | } |
| 11724 | break; |
| 11725 | case 5: |
| 11726 | switch (Field_n_Slot_inst_get (insn)) |
| 11727 | { |
| 11728 | case 0: |
| 11729 | return OPCODE_CALL0; |
| 11730 | case 1: |
| 11731 | return OPCODE_CALL4; |
| 11732 | case 2: |
| 11733 | return OPCODE_CALL8; |
| 11734 | case 3: |
| 11735 | return OPCODE_CALL12; |
| 11736 | } |
| 11737 | break; |
| 11738 | case 6: |
| 11739 | switch (Field_n_Slot_inst_get (insn)) |
| 11740 | { |
| 11741 | case 0: |
| 11742 | return OPCODE_J; |
| 11743 | case 1: |
| 11744 | switch (Field_m_Slot_inst_get (insn)) |
| 11745 | { |
| 11746 | case 0: |
| 11747 | return OPCODE_BEQZ; |
| 11748 | case 1: |
| 11749 | return OPCODE_BNEZ; |
| 11750 | case 2: |
| 11751 | return OPCODE_BLTZ; |
| 11752 | case 3: |
| 11753 | return OPCODE_BGEZ; |
| 11754 | } |
| 11755 | break; |
| 11756 | case 2: |
| 11757 | switch (Field_m_Slot_inst_get (insn)) |
| 11758 | { |
| 11759 | case 0: |
| 11760 | return OPCODE_BEQI; |
| 11761 | case 1: |
| 11762 | return OPCODE_BNEI; |
| 11763 | case 2: |
| 11764 | return OPCODE_BLTI; |
| 11765 | case 3: |
| 11766 | return OPCODE_BGEI; |
| 11767 | } |
| 11768 | break; |
| 11769 | case 3: |
| 11770 | switch (Field_m_Slot_inst_get (insn)) |
| 11771 | { |
| 11772 | case 0: |
| 11773 | return OPCODE_ENTRY; |
| 11774 | case 1: |
| 11775 | switch (Field_r_Slot_inst_get (insn)) |
| 11776 | { |
| 11777 | case 8: |
| 11778 | return OPCODE_LOOP; |
| 11779 | case 9: |
| 11780 | return OPCODE_LOOPNEZ; |
| 11781 | case 10: |
| 11782 | return OPCODE_LOOPGTZ; |
| 11783 | } |
| 11784 | break; |
| 11785 | case 2: |
| 11786 | return OPCODE_BLTUI; |
| 11787 | case 3: |
| 11788 | return OPCODE_BGEUI; |
| 11789 | } |
| 11790 | break; |
| 11791 | } |
| 11792 | break; |
| 11793 | case 7: |
| 11794 | switch (Field_r_Slot_inst_get (insn)) |
| 11795 | { |
| 11796 | case 0: |
| 11797 | return OPCODE_BNONE; |
| 11798 | case 1: |
| 11799 | return OPCODE_BEQ; |
| 11800 | case 2: |
| 11801 | return OPCODE_BLT; |
| 11802 | case 3: |
| 11803 | return OPCODE_BLTU; |
| 11804 | case 4: |
| 11805 | return OPCODE_BALL; |
| 11806 | case 5: |
| 11807 | return OPCODE_BBC; |
| 11808 | case 6: |
| 11809 | case 7: |
| 11810 | return OPCODE_BBCI; |
| 11811 | case 8: |
| 11812 | return OPCODE_BANY; |
| 11813 | case 9: |
| 11814 | return OPCODE_BNE; |
| 11815 | case 10: |
| 11816 | return OPCODE_BGE; |
| 11817 | case 11: |
| 11818 | return OPCODE_BGEU; |
| 11819 | case 12: |
| 11820 | return OPCODE_BNALL; |
| 11821 | case 13: |
| 11822 | return OPCODE_BBS; |
| 11823 | case 14: |
| 11824 | case 15: |
| 11825 | return OPCODE_BBSI; |
| 11826 | } |
| 11827 | break; |
| 11828 | } |
| 11829 | return 0; |
| 11830 | } |
| 11831 | |
| 11832 | static int |
| 11833 | Slot_inst16b_decode (const xtensa_insnbuf insn) |
| 11834 | { |
| 11835 | switch (Field_op0_Slot_inst16b_get (insn)) |
| 11836 | { |
| 11837 | case 12: |
| 11838 | switch (Field_i_Slot_inst16b_get (insn)) |
| 11839 | { |
| 11840 | case 0: |
| 11841 | return OPCODE_MOVI_N; |
| 11842 | case 1: |
| 11843 | switch (Field_z_Slot_inst16b_get (insn)) |
| 11844 | { |
| 11845 | case 0: |
| 11846 | return OPCODE_BEQZ_N; |
| 11847 | case 1: |
| 11848 | return OPCODE_BNEZ_N; |
| 11849 | } |
| 11850 | break; |
| 11851 | } |
| 11852 | break; |
| 11853 | case 13: |
| 11854 | switch (Field_r_Slot_inst16b_get (insn)) |
| 11855 | { |
| 11856 | case 0: |
| 11857 | return OPCODE_MOV_N; |
| 11858 | case 15: |
| 11859 | switch (Field_t_Slot_inst16b_get (insn)) |
| 11860 | { |
| 11861 | case 0: |
| 11862 | return OPCODE_RET_N; |
| 11863 | case 1: |
| 11864 | return OPCODE_RETW_N; |
| 11865 | case 2: |
| 11866 | return OPCODE_BREAK_N; |
| 11867 | case 3: |
| 11868 | if (Field_s_Slot_inst16b_get (insn) == 0) |
| 11869 | return OPCODE_NOP_N; |
| 11870 | break; |
| 11871 | case 6: |
| 11872 | if (Field_s_Slot_inst16b_get (insn) == 0) |
| 11873 | return OPCODE_ILL_N; |
| 11874 | break; |
| 11875 | } |
| 11876 | break; |
| 11877 | } |
| 11878 | break; |
| 11879 | } |
| 11880 | return 0; |
| 11881 | } |
| 11882 | |
| 11883 | static int |
| 11884 | Slot_inst16a_decode (const xtensa_insnbuf insn) |
| 11885 | { |
| 11886 | switch (Field_op0_Slot_inst16a_get (insn)) |
| 11887 | { |
| 11888 | case 8: |
| 11889 | return OPCODE_L32I_N; |
| 11890 | case 9: |
| 11891 | return OPCODE_S32I_N; |
| 11892 | case 10: |
| 11893 | return OPCODE_ADD_N; |
| 11894 | case 11: |
| 11895 | return OPCODE_ADDI_N; |
| 11896 | } |
| 11897 | return 0; |
| 11898 | } |
| 11899 | |
| 11900 | \f |
| 11901 | /* Instruction slots. */ |
| 11902 | |
| 11903 | static void |
| 11904 | Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, |
| 11905 | xtensa_insnbuf slotbuf) |
| 11906 | { |
| 11907 | slotbuf[0] = (insn[0] & 0xffffff); |
| 11908 | } |
| 11909 | |
| 11910 | static void |
| 11911 | Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, |
| 11912 | const xtensa_insnbuf slotbuf) |
| 11913 | { |
| 11914 | insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); |
| 11915 | } |
| 11916 | |
| 11917 | static void |
| 11918 | Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, |
| 11919 | xtensa_insnbuf slotbuf) |
| 11920 | { |
| 11921 | slotbuf[0] = ((insn[0] & 0xffff00) >> 8); |
| 11922 | } |
| 11923 | |
| 11924 | static void |
| 11925 | Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, |
| 11926 | const xtensa_insnbuf slotbuf) |
| 11927 | { |
| 11928 | insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); |
| 11929 | } |
| 11930 | |
| 11931 | static void |
| 11932 | Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, |
| 11933 | xtensa_insnbuf slotbuf) |
| 11934 | { |
| 11935 | slotbuf[0] = ((insn[0] & 0xffff00) >> 8); |
| 11936 | } |
| 11937 | |
| 11938 | static void |
| 11939 | Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, |
| 11940 | const xtensa_insnbuf slotbuf) |
| 11941 | { |
| 11942 | insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); |
| 11943 | } |
| 11944 | |
| 11945 | static xtensa_get_field_fn |
| 11946 | Slot_inst_get_field_fns[] = { |
| 11947 | Field_t_Slot_inst_get, |
| 11948 | Field_bbi4_Slot_inst_get, |
| 11949 | Field_bbi_Slot_inst_get, |
| 11950 | Field_imm12_Slot_inst_get, |
| 11951 | Field_imm8_Slot_inst_get, |
| 11952 | Field_s_Slot_inst_get, |
| 11953 | Field_imm12b_Slot_inst_get, |
| 11954 | Field_imm16_Slot_inst_get, |
| 11955 | Field_m_Slot_inst_get, |
| 11956 | Field_n_Slot_inst_get, |
| 11957 | Field_offset_Slot_inst_get, |
| 11958 | Field_op0_Slot_inst_get, |
| 11959 | Field_op1_Slot_inst_get, |
| 11960 | Field_op2_Slot_inst_get, |
| 11961 | Field_r_Slot_inst_get, |
| 11962 | Field_sa4_Slot_inst_get, |
| 11963 | Field_sae4_Slot_inst_get, |
| 11964 | Field_sae_Slot_inst_get, |
| 11965 | Field_sal_Slot_inst_get, |
| 11966 | Field_sargt_Slot_inst_get, |
| 11967 | Field_sas4_Slot_inst_get, |
| 11968 | Field_sas_Slot_inst_get, |
| 11969 | Field_sr_Slot_inst_get, |
| 11970 | Field_st_Slot_inst_get, |
| 11971 | Field_thi3_Slot_inst_get, |
| 11972 | Field_imm4_Slot_inst_get, |
| 11973 | Field_mn_Slot_inst_get, |
| 11974 | 0, |
| 11975 | 0, |
| 11976 | 0, |
| 11977 | 0, |
| 11978 | 0, |
| 11979 | 0, |
| 11980 | 0, |
| 11981 | 0, |
| 11982 | Field_xt_wbr15_imm_Slot_inst_get, |
| 11983 | Field_xt_wbr18_imm_Slot_inst_get, |
| 11984 | Implicit_Field_ar0_get, |
| 11985 | Implicit_Field_ar4_get, |
| 11986 | Implicit_Field_ar8_get, |
| 11987 | Implicit_Field_ar12_get |
| 11988 | }; |
| 11989 | |
| 11990 | static xtensa_set_field_fn |
| 11991 | Slot_inst_set_field_fns[] = { |
| 11992 | Field_t_Slot_inst_set, |
| 11993 | Field_bbi4_Slot_inst_set, |
| 11994 | Field_bbi_Slot_inst_set, |
| 11995 | Field_imm12_Slot_inst_set, |
| 11996 | Field_imm8_Slot_inst_set, |
| 11997 | Field_s_Slot_inst_set, |
| 11998 | Field_imm12b_Slot_inst_set, |
| 11999 | Field_imm16_Slot_inst_set, |
| 12000 | Field_m_Slot_inst_set, |
| 12001 | Field_n_Slot_inst_set, |
| 12002 | Field_offset_Slot_inst_set, |
| 12003 | Field_op0_Slot_inst_set, |
| 12004 | Field_op1_Slot_inst_set, |
| 12005 | Field_op2_Slot_inst_set, |
| 12006 | Field_r_Slot_inst_set, |
| 12007 | Field_sa4_Slot_inst_set, |
| 12008 | Field_sae4_Slot_inst_set, |
| 12009 | Field_sae_Slot_inst_set, |
| 12010 | Field_sal_Slot_inst_set, |
| 12011 | Field_sargt_Slot_inst_set, |
| 12012 | Field_sas4_Slot_inst_set, |
| 12013 | Field_sas_Slot_inst_set, |
| 12014 | Field_sr_Slot_inst_set, |
| 12015 | Field_st_Slot_inst_set, |
| 12016 | Field_thi3_Slot_inst_set, |
| 12017 | Field_imm4_Slot_inst_set, |
| 12018 | Field_mn_Slot_inst_set, |
| 12019 | 0, |
| 12020 | 0, |
| 12021 | 0, |
| 12022 | 0, |
| 12023 | 0, |
| 12024 | 0, |
| 12025 | 0, |
| 12026 | 0, |
| 12027 | Field_xt_wbr15_imm_Slot_inst_set, |
| 12028 | Field_xt_wbr18_imm_Slot_inst_set, |
| 12029 | Implicit_Field_set, |
| 12030 | Implicit_Field_set, |
| 12031 | Implicit_Field_set, |
| 12032 | Implicit_Field_set |
| 12033 | }; |
| 12034 | |
| 12035 | static xtensa_get_field_fn |
| 12036 | Slot_inst16a_get_field_fns[] = { |
| 12037 | Field_t_Slot_inst16a_get, |
| 12038 | 0, |
| 12039 | 0, |
| 12040 | 0, |
| 12041 | 0, |
| 12042 | Field_s_Slot_inst16a_get, |
| 12043 | 0, |
| 12044 | 0, |
| 12045 | 0, |
| 12046 | 0, |
| 12047 | 0, |
| 12048 | Field_op0_Slot_inst16a_get, |
| 12049 | 0, |
| 12050 | 0, |
| 12051 | Field_r_Slot_inst16a_get, |
| 12052 | 0, |
| 12053 | 0, |
| 12054 | 0, |
| 12055 | 0, |
| 12056 | 0, |
| 12057 | 0, |
| 12058 | 0, |
| 12059 | Field_sr_Slot_inst16a_get, |
| 12060 | Field_st_Slot_inst16a_get, |
| 12061 | 0, |
| 12062 | Field_imm4_Slot_inst16a_get, |
| 12063 | 0, |
| 12064 | Field_i_Slot_inst16a_get, |
| 12065 | Field_imm6lo_Slot_inst16a_get, |
| 12066 | Field_imm6hi_Slot_inst16a_get, |
| 12067 | Field_imm7lo_Slot_inst16a_get, |
| 12068 | Field_imm7hi_Slot_inst16a_get, |
| 12069 | Field_z_Slot_inst16a_get, |
| 12070 | Field_imm6_Slot_inst16a_get, |
| 12071 | Field_imm7_Slot_inst16a_get, |
| 12072 | 0, |
| 12073 | 0, |
| 12074 | Implicit_Field_ar0_get, |
| 12075 | Implicit_Field_ar4_get, |
| 12076 | Implicit_Field_ar8_get, |
| 12077 | Implicit_Field_ar12_get |
| 12078 | }; |
| 12079 | |
| 12080 | static xtensa_set_field_fn |
| 12081 | Slot_inst16a_set_field_fns[] = { |
| 12082 | Field_t_Slot_inst16a_set, |
| 12083 | 0, |
| 12084 | 0, |
| 12085 | 0, |
| 12086 | 0, |
| 12087 | Field_s_Slot_inst16a_set, |
| 12088 | 0, |
| 12089 | 0, |
| 12090 | 0, |
| 12091 | 0, |
| 12092 | 0, |
| 12093 | Field_op0_Slot_inst16a_set, |
| 12094 | 0, |
| 12095 | 0, |
| 12096 | Field_r_Slot_inst16a_set, |
| 12097 | 0, |
| 12098 | 0, |
| 12099 | 0, |
| 12100 | 0, |
| 12101 | 0, |
| 12102 | 0, |
| 12103 | 0, |
| 12104 | Field_sr_Slot_inst16a_set, |
| 12105 | Field_st_Slot_inst16a_set, |
| 12106 | 0, |
| 12107 | Field_imm4_Slot_inst16a_set, |
| 12108 | 0, |
| 12109 | Field_i_Slot_inst16a_set, |
| 12110 | Field_imm6lo_Slot_inst16a_set, |
| 12111 | Field_imm6hi_Slot_inst16a_set, |
| 12112 | Field_imm7lo_Slot_inst16a_set, |
| 12113 | Field_imm7hi_Slot_inst16a_set, |
| 12114 | Field_z_Slot_inst16a_set, |
| 12115 | Field_imm6_Slot_inst16a_set, |
| 12116 | Field_imm7_Slot_inst16a_set, |
| 12117 | 0, |
| 12118 | 0, |
| 12119 | Implicit_Field_set, |
| 12120 | Implicit_Field_set, |
| 12121 | Implicit_Field_set, |
| 12122 | Implicit_Field_set |
| 12123 | }; |
| 12124 | |
| 12125 | static xtensa_get_field_fn |
| 12126 | Slot_inst16b_get_field_fns[] = { |
| 12127 | Field_t_Slot_inst16b_get, |
| 12128 | 0, |
| 12129 | 0, |
| 12130 | 0, |
| 12131 | 0, |
| 12132 | Field_s_Slot_inst16b_get, |
| 12133 | 0, |
| 12134 | 0, |
| 12135 | 0, |
| 12136 | 0, |
| 12137 | 0, |
| 12138 | Field_op0_Slot_inst16b_get, |
| 12139 | 0, |
| 12140 | 0, |
| 12141 | Field_r_Slot_inst16b_get, |
| 12142 | 0, |
| 12143 | 0, |
| 12144 | 0, |
| 12145 | 0, |
| 12146 | 0, |
| 12147 | 0, |
| 12148 | 0, |
| 12149 | Field_sr_Slot_inst16b_get, |
| 12150 | Field_st_Slot_inst16b_get, |
| 12151 | 0, |
| 12152 | Field_imm4_Slot_inst16b_get, |
| 12153 | 0, |
| 12154 | Field_i_Slot_inst16b_get, |
| 12155 | Field_imm6lo_Slot_inst16b_get, |
| 12156 | Field_imm6hi_Slot_inst16b_get, |
| 12157 | Field_imm7lo_Slot_inst16b_get, |
| 12158 | Field_imm7hi_Slot_inst16b_get, |
| 12159 | Field_z_Slot_inst16b_get, |
| 12160 | Field_imm6_Slot_inst16b_get, |
| 12161 | Field_imm7_Slot_inst16b_get, |
| 12162 | 0, |
| 12163 | 0, |
| 12164 | Implicit_Field_ar0_get, |
| 12165 | Implicit_Field_ar4_get, |
| 12166 | Implicit_Field_ar8_get, |
| 12167 | Implicit_Field_ar12_get |
| 12168 | }; |
| 12169 | |
| 12170 | static xtensa_set_field_fn |
| 12171 | Slot_inst16b_set_field_fns[] = { |
| 12172 | Field_t_Slot_inst16b_set, |
| 12173 | 0, |
| 12174 | 0, |
| 12175 | 0, |
| 12176 | 0, |
| 12177 | Field_s_Slot_inst16b_set, |
| 12178 | 0, |
| 12179 | 0, |
| 12180 | 0, |
| 12181 | 0, |
| 12182 | 0, |
| 12183 | Field_op0_Slot_inst16b_set, |
| 12184 | 0, |
| 12185 | 0, |
| 12186 | Field_r_Slot_inst16b_set, |
| 12187 | 0, |
| 12188 | 0, |
| 12189 | 0, |
| 12190 | 0, |
| 12191 | 0, |
| 12192 | 0, |
| 12193 | 0, |
| 12194 | Field_sr_Slot_inst16b_set, |
| 12195 | Field_st_Slot_inst16b_set, |
| 12196 | 0, |
| 12197 | Field_imm4_Slot_inst16b_set, |
| 12198 | 0, |
| 12199 | Field_i_Slot_inst16b_set, |
| 12200 | Field_imm6lo_Slot_inst16b_set, |
| 12201 | Field_imm6hi_Slot_inst16b_set, |
| 12202 | Field_imm7lo_Slot_inst16b_set, |
| 12203 | Field_imm7hi_Slot_inst16b_set, |
| 12204 | Field_z_Slot_inst16b_set, |
| 12205 | Field_imm6_Slot_inst16b_set, |
| 12206 | Field_imm7_Slot_inst16b_set, |
| 12207 | 0, |
| 12208 | 0, |
| 12209 | Implicit_Field_set, |
| 12210 | Implicit_Field_set, |
| 12211 | Implicit_Field_set, |
| 12212 | Implicit_Field_set |
| 12213 | }; |
| 12214 | |
| 12215 | static xtensa_slot_internal slots[] = { |
| 12216 | { "Inst", "x24", 0, |
| 12217 | Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, |
| 12218 | Slot_inst_get_field_fns, Slot_inst_set_field_fns, |
| 12219 | Slot_inst_decode, "nop" }, |
| 12220 | { "Inst16a", "x16a", 0, |
| 12221 | Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, |
| 12222 | Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, |
| 12223 | Slot_inst16a_decode, "" }, |
| 12224 | { "Inst16b", "x16b", 0, |
| 12225 | Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, |
| 12226 | Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, |
| 12227 | Slot_inst16b_decode, "nop.n" } |
| 12228 | }; |
| 12229 | |
| 12230 | \f |
| 12231 | /* Instruction formats. */ |
| 12232 | |
| 12233 | static void |
| 12234 | Format_x24_encode (xtensa_insnbuf insn) |
| 12235 | { |
| 12236 | insn[0] = 0; |
| 12237 | } |
| 12238 | |
| 12239 | static void |
| 12240 | Format_x16a_encode (xtensa_insnbuf insn) |
| 12241 | { |
| 12242 | insn[0] = 0x800000; |
| 12243 | } |
| 12244 | |
| 12245 | static void |
| 12246 | Format_x16b_encode (xtensa_insnbuf insn) |
| 12247 | { |
| 12248 | insn[0] = 0xc00000; |
| 12249 | } |
| 12250 | |
| 12251 | static int Format_x24_slots[] = { 0 }; |
| 12252 | |
| 12253 | static int Format_x16a_slots[] = { 1 }; |
| 12254 | |
| 12255 | static int Format_x16b_slots[] = { 2 }; |
| 12256 | |
| 12257 | static xtensa_format_internal formats[] = { |
| 12258 | { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, |
| 12259 | { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, |
| 12260 | { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } |
| 12261 | }; |
| 12262 | |
| 12263 | |
| 12264 | static int |
| 12265 | format_decoder (const xtensa_insnbuf insn) |
| 12266 | { |
| 12267 | if ((insn[0] & 0x800000) == 0) |
| 12268 | return 0; /* x24 */ |
| 12269 | if ((insn[0] & 0xc00000) == 0x800000) |
| 12270 | return 1; /* x16a */ |
| 12271 | if ((insn[0] & 0xe00000) == 0xc00000) |
| 12272 | return 2; /* x16b */ |
| 12273 | return -1; |
| 12274 | } |
| 12275 | |
| 12276 | static int length_table[16] = { |
| 12277 | 3, |
| 12278 | 3, |
| 12279 | 3, |
| 12280 | 3, |
| 12281 | 3, |
| 12282 | 3, |
| 12283 | 3, |
| 12284 | 3, |
| 12285 | 2, |
| 12286 | 2, |
| 12287 | 2, |
| 12288 | 2, |
| 12289 | 2, |
| 12290 | 2, |
| 12291 | -1, |
| 12292 | -1 |
| 12293 | }; |
| 12294 | |
| 12295 | static int |
| 12296 | length_decoder (const unsigned char *insn) |
| 12297 | { |
| 12298 | int op0 = (insn[0] >> 4) & 0xf; |
| 12299 | return length_table[op0]; |
| 12300 | } |
| 12301 | |
| 12302 | \f |
| 12303 | /* Top-level ISA structure. */ |
| 12304 | |
| 12305 | xtensa_isa_internal xtensa_modules = { |
| 12306 | 1 /* big-endian */, |
| 12307 | 3 /* insn_size */, 0, |
| 12308 | 3, formats, format_decoder, length_decoder, |
| 12309 | 3, slots, |
| 12310 | 41 /* num_fields */, |
| 12311 | 75, operands, |
| 12312 | 286, iclasses, |
| 12313 | 353, opcodes, 0, |
| 12314 | 1, regfiles, |
| 12315 | NUM_STATES, states, 0, |
| 12316 | NUM_SYSREGS, sysregs, 0, |
| 12317 | { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, |
| 12318 | 0, interfaces, 0, |
| 12319 | 0, funcUnits, 0 |
| 12320 | }; |