| 1 | ; Renesas M32R CPU description. -*- Scheme -*- |
| 2 | ; |
| 3 | ; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009 |
| 4 | ; Free Software Foundation, Inc. |
| 5 | ; |
| 6 | ; Contributed by Red Hat Inc; developed under contract from Mitsubishi |
| 7 | ; Electric Corporation. |
| 8 | ; |
| 9 | ; This file is part of the GNU Binutils. |
| 10 | ; |
| 11 | ; This program is free software; you can redistribute it and/or modify |
| 12 | ; it under the terms of the GNU General Public License as published by |
| 13 | ; the Free Software Foundation; either version 3 of the License, or |
| 14 | ; (at your option) any later version. |
| 15 | ; |
| 16 | ; This program is distributed in the hope that it will be useful, |
| 17 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | ; GNU General Public License for more details. |
| 20 | ; |
| 21 | ; You should have received a copy of the GNU General Public License |
| 22 | ; along with this program; if not, write to the Free Software |
| 23 | ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 24 | ; MA 02110-1301, USA. |
| 25 | |
| 26 | (include "simplify.inc") |
| 27 | |
| 28 | ; FIXME: Delete sign extension of accumulator results. |
| 29 | ; Sign extension is done when accumulator is read. |
| 30 | |
| 31 | ; define-arch must appear first |
| 32 | |
| 33 | (define-arch |
| 34 | (name m32r) ; name of cpu family |
| 35 | (comment "Renesas M32R") |
| 36 | (default-alignment aligned) |
| 37 | (insn-lsb0? #f) |
| 38 | (machs m32r m32rx m32r2) |
| 39 | (isas m32r) |
| 40 | ) |
| 41 | |
| 42 | ; Attributes. |
| 43 | |
| 44 | ; An attribute to describe which pipeline an insn runs in. |
| 45 | ; O_OS is a special attribute for sll, sra, sla, slli, srai, slai. |
| 46 | ; These instructions have O attribute for m32rx and OS attribute for m32r2. |
| 47 | |
| 48 | (define-attr |
| 49 | (for insn) |
| 50 | (type enum) |
| 51 | (name PIPE) |
| 52 | (comment "parallel execution pipeline selection") |
| 53 | (values NONE O S OS O_OS) |
| 54 | ) |
| 55 | |
| 56 | ; A derived attribute that says which insns can be executed in parallel |
| 57 | ; with others. This is a required attribute for architectures with |
| 58 | ; parallel execution. |
| 59 | |
| 60 | (define-attr |
| 61 | (for insn) |
| 62 | (type enum) |
| 63 | (name PARALLEL) |
| 64 | (attrs META) ; do not define in any generated file for now |
| 65 | (values NO YES) |
| 66 | (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES))) |
| 67 | ) |
| 68 | |
| 69 | ; Instruction set parameters. |
| 70 | |
| 71 | (define-isa |
| 72 | (name m32r) |
| 73 | |
| 74 | ; This is 32 because 16 bit insns always appear as pairs. |
| 75 | ; ??? See if this can go away. It's only used by the disassembler (right?) |
| 76 | ; to decide how long an unknown insn is. One value isn't sufficient (e.g. if |
| 77 | ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.) |
| 78 | (default-insn-bitsize 32) |
| 79 | |
| 80 | ; Number of bytes of insn we can initially fetch. |
| 81 | ; The M32R is tricky in that insns are either two 16-bit insns |
| 82 | ; (executed sequentially or in parallel) or one 32-bit insn. |
| 83 | ; So on one hand the base insn size is 16 bits, but on another it's 32. |
| 84 | ; 32 is chosen because: |
| 85 | ; - if the chip were ever bi-endian it is believed that the byte order would |
| 86 | ; be based on 32 bit quantities |
| 87 | ; - 32 bit insns are always aligned on 32 bit boundaries |
| 88 | ; - the pc will never stop on a 16 bit (and not 32 bit) boundary |
| 89 | ; [well actually it can, but there are no branches to such places] |
| 90 | (base-insn-bitsize 32) |
| 91 | |
| 92 | ; Used in computing bit numbers. |
| 93 | (default-insn-word-bitsize 32) |
| 94 | |
| 95 | ; The m32r fetches 2 insns at a time. |
| 96 | (liw-insns 2) |
| 97 | |
| 98 | ; While the m32r can execute insns in parallel, the base mach can't |
| 99 | ; (other than nop). The base mach is greatly handicapped by this, but |
| 100 | ; we still need to cleanly handle it. |
| 101 | (parallel-insns 2) |
| 102 | |
| 103 | ; Initial bitnumbers to decode insns by. |
| 104 | (decode-assist (0 1 2 3 8 9 10 11)) |
| 105 | |
| 106 | ; Classification of instructions that fit in the various frames. |
| 107 | ; wip, not currently used |
| 108 | (insn-types (long ; name |
| 109 | 31 ; length |
| 110 | (eq-attr (current-insn) LENGTH 31) ; matching insns |
| 111 | (0 1 2 7 8 9 10) ; decode-assist |
| 112 | ) |
| 113 | (short |
| 114 | 15 |
| 115 | (eq-attr (current-insn) LENGTH 15) ; matching insns |
| 116 | (0 1 2 7 8 9 10) |
| 117 | ) |
| 118 | ) |
| 119 | |
| 120 | ; Instruction framing. |
| 121 | ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed |
| 122 | ; serially (left->right), or two 16 bit insns executed parallelly. |
| 123 | ; wip, not currently used |
| 124 | (frame long32 ; name |
| 125 | ((long)) ; list of insns in frame, plus constraint |
| 126 | "$0" ; assembler |
| 127 | (+ (1 1) (31 $0)) ; value |
| 128 | (sequence () (execute $0)) ; action |
| 129 | ) |
| 130 | (frame serial2x16 |
| 131 | ((short) |
| 132 | (short)) |
| 133 | "$0 -> $1" |
| 134 | (+ (1 0) (15 $0) (1 0) (15 $1)) |
| 135 | (sequence () |
| 136 | (execute $0) |
| 137 | (execute $1)) |
| 138 | ) |
| 139 | (frame parallel2x16 |
| 140 | ((short (eq-attr (current-insn) PIPE "O,BOTH")) |
| 141 | (short (eq-attr (current-insn) PIPE "S,BOTH"))) |
| 142 | "$0 || $1" |
| 143 | (+ (1 0) (15 $0) (1 1) (15 $1)) |
| 144 | (parallel () |
| 145 | (execute $0) |
| 146 | (execute $1)) |
| 147 | ) |
| 148 | ) |
| 149 | \f |
| 150 | ; Cpu family definitions. |
| 151 | |
| 152 | ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than |
| 153 | ; define-cpu. |
| 154 | ; ??? Have define-arch provide defaults for architecture that define-cpu can |
| 155 | ; then override [reduces duplication in define-cpu]. |
| 156 | ; ??? Another way to go is to delete cpu-families entirely and have one mach |
| 157 | ; able to inherit things from another mach (would also need the ability to |
| 158 | ; not only override specific inherited things but also disable some, |
| 159 | ; e.g. if an insn wasn't supported). |
| 160 | |
| 161 | (define-cpu |
| 162 | ; cpu names must be distinct from the architecture name and machine names. |
| 163 | ; The "b" suffix stands for "base" and is the convention. |
| 164 | ; The "f" suffix stands for "family" and is the convention. |
| 165 | (name m32rbf) |
| 166 | (comment "Renesas M32R base family") |
| 167 | (endian either) |
| 168 | (word-bitsize 32) |
| 169 | ; Override isa spec (??? keeps things simpler, though it was more true |
| 170 | ; in the early days and not so much now). |
| 171 | (parallel-insns 1) |
| 172 | ) |
| 173 | |
| 174 | (define-cpu |
| 175 | (name m32rxf) |
| 176 | (comment "Renesas M32Rx family") |
| 177 | (endian either) |
| 178 | (word-bitsize 32) |
| 179 | ; Generated files have an "x" suffix. |
| 180 | (file-transform "x") |
| 181 | ) |
| 182 | |
| 183 | (define-cpu |
| 184 | (name m32r2f) |
| 185 | (comment "Renesas M32R2 family") |
| 186 | (endian either) |
| 187 | (word-bitsize 32) |
| 188 | ; Generated files have an "2" suffix. |
| 189 | (file-transform "2") |
| 190 | ) |
| 191 | |
| 192 | (define-mach |
| 193 | (name m32r) |
| 194 | (comment "Generic M32R cpu") |
| 195 | (cpu m32rbf) |
| 196 | ) |
| 197 | |
| 198 | (define-mach |
| 199 | (name m32rx) |
| 200 | (comment "M32RX cpu") |
| 201 | (cpu m32rxf) |
| 202 | ) |
| 203 | |
| 204 | (define-mach |
| 205 | (name m32r2) |
| 206 | (comment "M32R2 cpu") |
| 207 | (cpu m32r2f) |
| 208 | ) |
| 209 | \f |
| 210 | ; Model descriptions. |
| 211 | |
| 212 | ; The meaning of this value is wip but at the moment it's intended to describe |
| 213 | ; the implementation (i.e. what -mtune=foo does in sparc gcc). |
| 214 | ; |
| 215 | ; Notes while wip: |
| 216 | ; - format of pipeline entry: |
| 217 | ; (pipeline name (stage1-name ...) (stage2-name ...) ...) |
| 218 | ; The contents of a stage description is wip. |
| 219 | ; - each mach must have at least one model |
| 220 | ; - the default model must be the first one |
| 221 | ;- maybe have `retire' support update total cycle count to handle current |
| 222 | ; parallel insn cycle counting problems |
| 223 | |
| 224 | (define-model |
| 225 | (name m32r/d) (comment "m32r/d") (attrs) |
| 226 | (mach m32r) |
| 227 | |
| 228 | ;(prefetch) |
| 229 | ;(retire) |
| 230 | |
| 231 | (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback))) |
| 232 | (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) |
| 233 | |
| 234 | ; `state' is a list of variables for recording model state |
| 235 | (state |
| 236 | ; bit mask of h-gr registers, =1 means value being loaded from memory |
| 237 | (h-gr UINT) |
| 238 | ) |
| 239 | |
| 240 | (unit u-exec "Execution Unit" () |
| 241 | 1 1 ; issue done |
| 242 | () ; state |
| 243 | ((sr INT -1) (dr INT -1)) ; inputs |
| 244 | ((dr INT -1)) ; outputs |
| 245 | () ; profile action (default) |
| 246 | ) |
| 247 | (unit u-cmp "Compare Unit" () |
| 248 | 1 1 ; issue done |
| 249 | () ; state |
| 250 | ((src1 INT -1) (src2 INT -1)) ; inputs |
| 251 | () ; outputs |
| 252 | () ; profile action (default) |
| 253 | ) |
| 254 | (unit u-mac "Multiply/Accumulate Unit" () |
| 255 | 1 1 ; issue done |
| 256 | () ; state |
| 257 | ((src1 INT -1) (src2 INT -1)) ; inputs |
| 258 | () ; outputs |
| 259 | () ; profile action (default) |
| 260 | ) |
| 261 | (unit u-cti "Branch Unit" () |
| 262 | 1 1 ; issue done |
| 263 | () ; state |
| 264 | ((sr INT -1)) ; inputs |
| 265 | ((pc)) ; outputs |
| 266 | () ; profile action (default) |
| 267 | ) |
| 268 | (unit u-load "Memory Load Unit" () |
| 269 | 1 1 ; issue done |
| 270 | () ; state |
| 271 | ((sr INT) |
| 272 | ;(ld-mem AI) |
| 273 | ) ; inputs |
| 274 | ((dr INT)) ; outputs |
| 275 | () ; profile action (default) |
| 276 | ) |
| 277 | (unit u-store "Memory Store Unit" () |
| 278 | 1 1 ; issue done |
| 279 | () ; state |
| 280 | ((src1 INT) (src2 INT)) ; inputs |
| 281 | () ; ((st-mem AI)) ; outputs |
| 282 | () ; profile action (default) |
| 283 | ) |
| 284 | ) |
| 285 | |
| 286 | (define-model |
| 287 | (name test) (comment "test") (attrs) |
| 288 | (mach m32r) |
| 289 | (pipeline all "" () ((fetch) (decode) (execute) (writeback))) |
| 290 | (unit u-exec "Execution Unit" () |
| 291 | 1 1 ; issue done |
| 292 | () () () ()) |
| 293 | ) |
| 294 | |
| 295 | ; Each mach must have at least one model. |
| 296 | |
| 297 | (define-model |
| 298 | (name m32rx) (comment "m32rx") (attrs) |
| 299 | (mach m32rx) |
| 300 | |
| 301 | ; ??? It's 6 stages but I forget the details right now. |
| 302 | (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) |
| 303 | (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) |
| 304 | (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) |
| 305 | |
| 306 | (unit u-exec "Execution Unit" () |
| 307 | 1 1 ; issue done |
| 308 | () ; state |
| 309 | ((sr INT -1) (dr INT -1)) ; inputs |
| 310 | ((dr INT -1)) ; outputs |
| 311 | () ; profile action (default) |
| 312 | ) |
| 313 | (unit u-cmp "Compare Unit" () |
| 314 | 1 1 ; issue done |
| 315 | () ; state |
| 316 | ((src1 INT -1) (src2 INT -1)) ; inputs |
| 317 | () ; outputs |
| 318 | () ; profile action (default) |
| 319 | ) |
| 320 | (unit u-mac "Multiply/Accumulate Unit" () |
| 321 | 1 1 ; issue done |
| 322 | () ; state |
| 323 | ((src1 INT -1) (src2 INT -1)) ; inputs |
| 324 | () ; outputs |
| 325 | () ; profile action (default) |
| 326 | ) |
| 327 | (unit u-cti "Branch Unit" () |
| 328 | 1 1 ; issue done |
| 329 | () ; state |
| 330 | ((sr INT -1)) ; inputs |
| 331 | ((pc)) ; outputs |
| 332 | () ; profile action (default) |
| 333 | ) |
| 334 | (unit u-load "Memory Load Unit" () |
| 335 | 1 1 ; issue done |
| 336 | () ; state |
| 337 | ((sr INT)) ; inputs |
| 338 | ((dr INT)) ; outputs |
| 339 | () ; profile action (default) |
| 340 | ) |
| 341 | (unit u-store "Memory Store Unit" () |
| 342 | 1 1 ; issue done |
| 343 | () ; state |
| 344 | ((src1 INT) (src2 INT)) ; inputs |
| 345 | () ; outputs |
| 346 | () ; profile action (default) |
| 347 | ) |
| 348 | ) |
| 349 | |
| 350 | (define-model |
| 351 | (name m32r2) (comment "m32r2") (attrs) |
| 352 | (mach m32r2) |
| 353 | |
| 354 | ; ??? It's 6 stages but I forget the details right now. |
| 355 | (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) |
| 356 | (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) |
| 357 | (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) |
| 358 | |
| 359 | (unit u-exec "Execution Unit" () |
| 360 | 1 1 ; issue done |
| 361 | () ; state |
| 362 | ((sr INT -1) (dr INT -1)) ; inputs |
| 363 | ((dr INT -1)) ; outputs |
| 364 | () ; profile action (default) |
| 365 | ) |
| 366 | (unit u-cmp "Compare Unit" () |
| 367 | 1 1 ; issue done |
| 368 | () ; state |
| 369 | ((src1 INT -1) (src2 INT -1)) ; inputs |
| 370 | () ; outputs |
| 371 | () ; profile action (default) |
| 372 | ) |
| 373 | (unit u-mac "Multiply/Accumulate Unit" () |
| 374 | 1 1 ; issue done |
| 375 | () ; state |
| 376 | ((src1 INT -1) (src2 INT -1)) ; inputs |
| 377 | () ; outputs |
| 378 | () ; profile action (default) |
| 379 | ) |
| 380 | (unit u-cti "Branch Unit" () |
| 381 | 1 1 ; issue done |
| 382 | () ; state |
| 383 | ((sr INT -1)) ; inputs |
| 384 | ((pc)) ; outputs |
| 385 | () ; profile action (default) |
| 386 | ) |
| 387 | (unit u-load "Memory Load Unit" () |
| 388 | 1 1 ; issue done |
| 389 | () ; state |
| 390 | ((sr INT)) ; inputs |
| 391 | ((dr INT)) ; outputs |
| 392 | () ; profile action (default) |
| 393 | ) |
| 394 | (unit u-store "Memory Store Unit" () |
| 395 | 1 1 ; issue done |
| 396 | () ; state |
| 397 | ((src1 INT) (src2 INT)) ; inputs |
| 398 | () ; outputs |
| 399 | () ; profile action (default) |
| 400 | ) |
| 401 | ) |
| 402 | \f |
| 403 | ; The instruction fetch/execute cycle. |
| 404 | ; This is split into two parts as sometimes more than one instruction is |
| 405 | ; decoded at once. |
| 406 | ; The `const SI' argument to decode/execute is used to distinguish |
| 407 | ; multiple instructions processed at the same time (e.g. m32r). |
| 408 | ; |
| 409 | ; ??? This is wip, and not currently used. |
| 410 | ; ??? Needs to be moved to define-isa. |
| 411 | |
| 412 | ; This is how to fetch and decode an instruction. |
| 413 | |
| 414 | ;(define-extract |
| 415 | ; (sequence VOID |
| 416 | ; (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0)) |
| 417 | ; (sequence VOID |
| 418 | ; (set-quiet USI (scratch UHI insn1) (ifetch UHI pc)) |
| 419 | ; (decode VOID pc (and UHI insn1 (const UHI #x7fff)) |
| 420 | ; (const SI 0))) |
| 421 | ; (sequence VOID |
| 422 | ; (set-quiet USI (scratch USI insn) (ifetch USI pc)) |
| 423 | ; (if VOID (ne USI (and USI insn (const USI #x80000000)) |
| 424 | ; (const USI 0)) |
| 425 | ; (decode VOID pc (srl USI insn (const WI 16)) (const SI 0)) |
| 426 | ; (sequence VOID |
| 427 | ; ; ??? parallel support |
| 428 | ; (decode VOID pc (srl USI insn (const WI 16)) |
| 429 | ; (const SI 0)) |
| 430 | ; (decode VOID (add AI pc (const AI 2)) |
| 431 | ; (and USI insn (const WI #x7fff)) |
| 432 | ; (const SI 1)))))) |
| 433 | ; ) |
| 434 | ;) |
| 435 | |
| 436 | ; This is how to execute a decoded instruction. |
| 437 | |
| 438 | ;(define-execute |
| 439 | ; (sequence VOID () ; () is empty option list |
| 440 | ; ((AI new_pc)) |
| 441 | ; (set AI new_pc (execute: AI (const 0)) #:quiet) |
| 442 | ; (set AI pc new_pc #:direct) |
| 443 | ; ) |
| 444 | ;) |
| 445 | |
| 446 | ; FIXME: It might simplify things to separate the execute process from the |
| 447 | ; one that updates the PC. |
| 448 | \f |
| 449 | ; Instruction fields. |
| 450 | ; |
| 451 | ; Attributes: |
| 452 | ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) |
| 453 | ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) |
| 454 | ; RESERVED: bits are not used to decode insn, must be all 0 |
| 455 | ; RELOC: there is a relocation associated with this field (experiment) |
| 456 | |
| 457 | (define-attr |
| 458 | (for ifield operand) |
| 459 | (type boolean) |
| 460 | (name RELOC) |
| 461 | (comment "there is a reloc associated with this field (experiment)") |
| 462 | ) |
| 463 | |
| 464 | (dnf f-op1 "op1" () 0 4) |
| 465 | (dnf f-op2 "op2" () 8 4) |
| 466 | (dnf f-cond "cond" () 4 4) |
| 467 | (dnf f-r1 "r1" () 4 4) |
| 468 | (dnf f-r2 "r2" () 12 4) |
| 469 | (df f-simm8 "simm8" () 8 8 INT #f #f) |
| 470 | (df f-simm16 "simm16" () 16 16 INT #f #f) |
| 471 | (dnf f-shift-op2 "shift op2" () 8 3) |
| 472 | (dnf f-uimm3 "uimm3" () 5 3) |
| 473 | (dnf f-uimm4 "uimm4" () 12 4) |
| 474 | (dnf f-uimm5 "uimm5" () 11 5) |
| 475 | (dnf f-uimm8 "uimm8" () 8 8) |
| 476 | (dnf f-uimm16 "uimm16" () 16 16) |
| 477 | (dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24) |
| 478 | (dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16) |
| 479 | (df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT |
| 480 | ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2))) |
| 481 | ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4))))) |
| 482 | (df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT |
| 483 | ((value pc) (sra WI (sub WI value pc) (const 2))) |
| 484 | ((value pc) (add WI (sll WI value (const 2)) pc))) |
| 485 | (df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT |
| 486 | ((value pc) (sra WI (sub WI value pc) (const 2))) |
| 487 | ((value pc) (add WI (sll WI value (const 2)) pc))) |
| 488 | |
| 489 | (dnf f-op23 "op2.3" () 9 3) |
| 490 | (dnf f-op3 "op3" () 14 2) |
| 491 | (dnf f-acc "acc" () 8 1) |
| 492 | (dnf f-accs "accs" () 12 2) |
| 493 | (dnf f-accd "accd" () 4 2) |
| 494 | (dnf f-bits67 "bits67" () 6 2) |
| 495 | (dnf f-bit4 "bit4" () 4 1) |
| 496 | (dnf f-bit14 "bit14" () 14 1) |
| 497 | |
| 498 | (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2") |
| 499 | (attrs) |
| 500 | (start 15) (length 1) |
| 501 | (encode (value pc) (sub WI value (const WI 1))) |
| 502 | (decode (value pc) (add WI value (const WI 1))) |
| 503 | ) |
| 504 | \f |
| 505 | ; Enums. |
| 506 | |
| 507 | ; insn-op1: bits 0-3 |
| 508 | ; FIXME: should use die macro or some such |
| 509 | (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 |
| 510 | ("0" "1" "2" "3" "4" "5" "6" "7" |
| 511 | "8" "9" "10" "11" "12" "13" "14" "15") |
| 512 | ) |
| 513 | |
| 514 | ; insn-op2: bits 8-11 |
| 515 | ; FIXME: should use die macro or some such |
| 516 | (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 |
| 517 | ("0" "1" "2" "3" "4" "5" "6" "7" |
| 518 | "8" "9" "10" "11" "12" "13" "14" "15") |
| 519 | ) |
| 520 | \f |
| 521 | ; Hardware pieces. |
| 522 | ; These entries list the elements of the raw hardware. |
| 523 | ; They're also used to provide tables and other elements of the assembly |
| 524 | ; language. |
| 525 | |
| 526 | (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) |
| 527 | |
| 528 | (dnh h-hi16 "high 16 bits" () |
| 529 | (immediate (UINT 16)) |
| 530 | () () () |
| 531 | ) |
| 532 | |
| 533 | ; These two aren't technically needed. |
| 534 | ; They're here for illustration sake mostly. |
| 535 | ; Plus they cause the value to be stored in the extraction buffers to only |
| 536 | ; be 16 bits wide (vs 32 or 64). Whoopie ding. But it's fun. |
| 537 | (dnh h-slo16 "signed low 16 bits" () |
| 538 | (immediate (INT 16)) |
| 539 | () () () |
| 540 | ) |
| 541 | (dnh h-ulo16 "unsigned low 16 bits" () |
| 542 | (immediate (UINT 16)) |
| 543 | () () () |
| 544 | ) |
| 545 | |
| 546 | (define-keyword |
| 547 | (name gr-names) |
| 548 | (print-name h-gr) |
| 549 | (prefix "") |
| 550 | (values (fp 13) (lr 14) (sp 15) |
| 551 | (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) |
| 552 | (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)) |
| 553 | ) |
| 554 | |
| 555 | (define-hardware |
| 556 | (name h-gr) |
| 557 | (comment "general registers") |
| 558 | (attrs PROFILE CACHE-ADDR) |
| 559 | (type register WI (16)) |
| 560 | (indices extern-keyword gr-names) |
| 561 | ) |
| 562 | |
| 563 | (define-keyword |
| 564 | (name cr-names) |
| 565 | (print-name h-cr) |
| 566 | (prefix "") |
| 567 | (values (psw 0) (cbr 1) (spi 2) (spu 3) |
| 568 | (bpc 6) (bbpsw 8) (bbpc 14) (evb 5) |
| 569 | (cr0 0) (cr1 1) (cr2 2) (cr3 3) |
| 570 | (cr4 4) (cr5 5) (cr6 6) (cr7 7) |
| 571 | (cr8 8) (cr9 9) (cr10 10) (cr11 11) |
| 572 | (cr12 12) (cr13 13) (cr14 14) (cr15 15)) |
| 573 | ) |
| 574 | |
| 575 | (define-hardware |
| 576 | (name h-cr) |
| 577 | (comment "control registers") |
| 578 | (type register UWI (16)) |
| 579 | (indices extern-keyword cr-names) |
| 580 | (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index)) |
| 581 | (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval)) |
| 582 | ) |
| 583 | |
| 584 | ; The actual accumulator is only 56 bits. |
| 585 | ; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0). |
| 586 | ; To simplify the accumulator instructions, no attempt is made to keep the |
| 587 | ; top 8 bits properly sign extended (currently there's no point since they |
| 588 | ; all ignore them). When the value is read it is properly sign extended |
| 589 | ; [in the `get' handler]. |
| 590 | (define-hardware |
| 591 | (name h-accum) |
| 592 | (comment "accumulator") |
| 593 | (type register DI) |
| 594 | (get () (c-call DI "@cpu@_h_accum_get_handler")) |
| 595 | (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval)) |
| 596 | ) |
| 597 | |
| 598 | ; FIXME: Revisit after sanitization can be removed. Remove h-accum. |
| 599 | (define-hardware |
| 600 | (name h-accums) |
| 601 | (comment "accumulators") |
| 602 | (attrs (MACH m32rx,m32r2)) |
| 603 | (type register DI (2)) |
| 604 | (indices keyword "" ((a0 0) (a1 1))) |
| 605 | ; get/set so a0 accesses are redirected to h-accum. |
| 606 | ; They're also so reads can properly sign extend the value. |
| 607 | ; FIXME: Needn't be a function call. |
| 608 | (get (index) (c-call DI "@cpu@_h_accums_get_handler" index)) |
| 609 | (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval)) |
| 610 | ) |
| 611 | |
| 612 | ; For condbit operand. FIXME: Need to allow spec of get/set of operands. |
| 613 | ; Having this separate from h-psw keeps the parts that use it simpler |
| 614 | ; [since they greatly outnumber those that use h-psw]. |
| 615 | (dsh h-cond "condition bit" () (register BI)) |
| 616 | |
| 617 | ; The actual values of psw,bpsw,bbpsw are recorded here to allow access |
| 618 | ; to them as a unit. |
| 619 | (define-hardware |
| 620 | (name h-psw) |
| 621 | (comment "psw part of psw") |
| 622 | (type register UQI) |
| 623 | ; get/set to handle cond bit. |
| 624 | ; FIXME: missing: use's and clobber's |
| 625 | ; FIXME: remove c-call? |
| 626 | (get () (c-call UQI "@cpu@_h_psw_get_handler")) |
| 627 | (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval)) |
| 628 | ) |
| 629 | (dsh h-bpsw "backup psw" () (register UQI)) |
| 630 | (dsh h-bbpsw "backup bpsw" () (register UQI)) |
| 631 | |
| 632 | ; FIXME: Later make add get/set specs and support SMP. |
| 633 | (dsh h-lock "lock" () (register BI)) |
| 634 | \f |
| 635 | ; Instruction Operands. |
| 636 | ; These entries provide a layer between the assembler and the raw hardware |
| 637 | ; description, and are used to refer to hardware elements in the semantic |
| 638 | ; code. Usually there's a bit of over-specification, but in more complicated |
| 639 | ; instruction sets there isn't. |
| 640 | |
| 641 | ;; Print some operands take a hash prefix. |
| 642 | ;; ??? Why don't we also handle one when parsing? |
| 643 | |
| 644 | (define-pmacro (duhpo x-name x-comment x-attrs x-type x-index) |
| 645 | (define-operand (name x-name) (comment x-comment) |
| 646 | (.splice attrs (.unsplice x-attrs)) |
| 647 | (type x-type) (index x-index) |
| 648 | (handlers (print "unsigned_with_hash_prefix"))) |
| 649 | ) |
| 650 | |
| 651 | (define-pmacro (dshpo x-name x-comment x-attrs x-type x-index) |
| 652 | (define-operand (name x-name) (comment x-comment) |
| 653 | (.splice attrs (.unsplice x-attrs)) |
| 654 | (type x-type) (index x-index) |
| 655 | (handlers (print "signed_with_hash_prefix"))) |
| 656 | ) |
| 657 | |
| 658 | ; ??? Convention says this should be o-sr, but then the insn definitions |
| 659 | ; should refer to o-sr which is clumsy. The "o-" could be implicit, but |
| 660 | ; then it should be implicit for all the symbols here, but then there would |
| 661 | ; be confusion between (f-)simm8 and (h-)simm8. |
| 662 | ; So for now the rule is exactly as it appears here. |
| 663 | |
| 664 | (dnop sr "source register" () h-gr f-r2) |
| 665 | (dnop dr "destination register" () h-gr f-r1) |
| 666 | ;; The assembler relies upon the fact that dr and src1 are the same field. |
| 667 | ;; FIXME: Revisit. |
| 668 | (dnop src1 "source register 1" () h-gr f-r1) |
| 669 | (dnop src2 "source register 2" () h-gr f-r2) |
| 670 | (dnop scr "source control register" () h-cr f-r2) |
| 671 | (dnop dcr "destination control register" () h-cr f-r1) |
| 672 | |
| 673 | (dshpo simm8 "8 bit signed immediate" () h-sint f-simm8) |
| 674 | (dshpo simm16 "16 bit signed immediate" () h-sint f-simm16) |
| 675 | (duhpo uimm3 "3 bit unsigned number" () h-uint f-uimm3) |
| 676 | (duhpo uimm4 "4 bit trap number" () h-uint f-uimm4) |
| 677 | (duhpo uimm5 "5 bit shift count" () h-uint f-uimm5) |
| 678 | (duhpo uimm8 "8 bit unsigned immediate" () h-uint f-uimm8) |
| 679 | (duhpo uimm16 "16 bit unsigned immediate" () h-uint f-uimm16) |
| 680 | |
| 681 | (duhpo imm1 "1 bit immediate" ((MACH m32rx,m32r2)) h-uint f-imm1) |
| 682 | |
| 683 | (dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd) |
| 684 | (dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs) |
| 685 | (dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc) |
| 686 | |
| 687 | ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases. |
| 688 | ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use special handlers on |
| 689 | ; the operands themselves. |
| 690 | ; Instead we create a fake operand `hash'. The m32r is an illustration port, |
| 691 | ; so we often try out various ways of doing things. |
| 692 | |
| 693 | (define-operand (name hash) (comment "# prefix") (attrs) |
| 694 | (type h-sint) ; doesn't really matter |
| 695 | (index f-nil) |
| 696 | (handlers (parse "hash") (print "hash")) |
| 697 | ) |
| 698 | |
| 699 | ; For high(foo),shigh(foo). |
| 700 | (define-operand |
| 701 | (name hi16) |
| 702 | (comment "high 16 bit immediate, sign optional") |
| 703 | (attrs) |
| 704 | (type h-hi16) |
| 705 | (index f-hi16) |
| 706 | (handlers (parse "hi16")) |
| 707 | ) |
| 708 | |
| 709 | ; For low(foo),sda(foo). |
| 710 | (define-operand |
| 711 | (name slo16) |
| 712 | (comment "16 bit signed immediate, for low()") |
| 713 | (attrs) |
| 714 | (type h-slo16) |
| 715 | (index f-simm16) |
| 716 | (handlers (parse "slo16")) |
| 717 | ) |
| 718 | |
| 719 | ; For low(foo). |
| 720 | (define-operand |
| 721 | (name ulo16) |
| 722 | (comment "16 bit unsigned immediate, for low()") |
| 723 | (attrs) |
| 724 | (type h-ulo16) |
| 725 | (index f-uimm16) |
| 726 | (handlers (parse "ulo16")) |
| 727 | ) |
| 728 | |
| 729 | (dnop uimm24 "24 bit address" () h-addr f-uimm24) |
| 730 | |
| 731 | (define-operand |
| 732 | (name disp8) |
| 733 | (comment "8 bit displacement") |
| 734 | (attrs RELAX) |
| 735 | (type h-iaddr) |
| 736 | (index f-disp8) |
| 737 | ; ??? Early experiments had insert/extract fields here. |
| 738 | ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce |
| 739 | ; fields here to handle more complicated cases. |
| 740 | ) |
| 741 | |
| 742 | (dnop disp16 "16 bit displacement" () h-iaddr f-disp16) |
| 743 | (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24) |
| 744 | |
| 745 | ; These hardware elements are refered to frequently. |
| 746 | |
| 747 | (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) |
| 748 | (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil) |
| 749 | \f |
| 750 | ; Instruction definitions. |
| 751 | ; |
| 752 | ; Notes while wip: |
| 753 | ; - dni is a cover macro to the real "this is an instruction" keyword. |
| 754 | ; The syntax of the real one is yet to be determined. |
| 755 | ; At the lowest level (i.e. the "real" one) it will probably take a variable |
| 756 | ; list of arguments where each argument [perhaps after the standard three of |
| 757 | ; name, comment, attrs] is "(keyword arg-to-keyword)". This syntax is simple |
| 758 | ; and yet completely upward extensible. And given the macro facility, one |
| 759 | ; needn't code at that low a level so even though it'll be more verbose than |
| 760 | ; necessary it won't matter. This same reasoning can be applied to most |
| 761 | ; types of entries in this file. |
| 762 | |
| 763 | ; M32R specific instruction attributes: |
| 764 | |
| 765 | ; FILL-SLOT: Need next insn to begin on 32 bit boundary. |
| 766 | ; (A "slot" as used here is a 32 bit quantity that can either be filled with |
| 767 | ; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right |
| 768 | ; bin" where the left bin is the one with a lower address). |
| 769 | |
| 770 | (define-attr |
| 771 | (for insn) |
| 772 | (type boolean) |
| 773 | (name FILL-SLOT) |
| 774 | (comment "fill right bin with `nop' if insn is in left bin") |
| 775 | ) |
| 776 | |
| 777 | (define-attr |
| 778 | (for insn) |
| 779 | (type boolean) |
| 780 | (name SPECIAL) |
| 781 | (comment "non-public m32rx insn") |
| 782 | ) |
| 783 | |
| 784 | (define-attr |
| 785 | (for insn) |
| 786 | (type boolean) |
| 787 | (name SPECIAL_M32R) |
| 788 | (comment "non-public m32r insn") |
| 789 | ) |
| 790 | |
| 791 | (define-attr |
| 792 | (for insn) |
| 793 | (type boolean) |
| 794 | (name SPECIAL_FLOAT) |
| 795 | (comment "floating point insn") |
| 796 | ) |
| 797 | |
| 798 | ; IDOC attribute for instruction documentation. |
| 799 | |
| 800 | (define-attr |
| 801 | (for insn) |
| 802 | (type enum) |
| 803 | (name IDOC) |
| 804 | (comment "insn kind for documentation") |
| 805 | (attrs META) |
| 806 | (values |
| 807 | (MEM - () "Memory") |
| 808 | (ALU - () "ALU") |
| 809 | (BR - () "Branch") |
| 810 | (ACCUM - () "Accumulator") |
| 811 | (MAC - () "Multiply/Accumulate") |
| 812 | (MISC - () "Miscellaneous") |
| 813 | ) |
| 814 | ) |
| 815 | |
| 816 | (define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm) |
| 817 | (begin |
| 818 | (dni mnemonic |
| 819 | (.str mnemonic " reg/reg") |
| 820 | ((PIPE OS) (IDOC ALU)) |
| 821 | (.str mnemonic " $dr,$sr") |
| 822 | (+ OP1_0 op2-op dr sr) |
| 823 | (set dr (sem-op dr sr)) |
| 824 | () |
| 825 | ) |
| 826 | (dni (.sym mnemonic "3") |
| 827 | (.str mnemonic " reg/" imm) |
| 828 | ((IDOC ALU)) |
| 829 | (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm) |
| 830 | (+ OP1_8 op2-op dr sr imm) |
| 831 | (set dr (sem-op sr imm)) |
| 832 | () |
| 833 | ) |
| 834 | ) |
| 835 | ) |
| 836 | (bin-op add OP2_10 add "$hash" slo16) |
| 837 | ; sub isn't present because sub3 doesn't exist. |
| 838 | (bin-op and OP2_12 and "" uimm16) |
| 839 | (bin-op or OP2_14 or "$hash" ulo16) |
| 840 | (bin-op xor OP2_13 xor "" uimm16) |
| 841 | |
| 842 | (dni addi "addi" |
| 843 | ((PIPE OS) (IDOC ALU)) |
| 844 | ;#.(string-append "addi " "$dr,$simm8") ; #. experiment |
| 845 | "addi $dr,$simm8" |
| 846 | (+ OP1_4 dr simm8) |
| 847 | (set dr (add dr simm8)) |
| 848 | ((m32r/d (unit u-exec)) |
| 849 | (m32rx (unit u-exec)) |
| 850 | (m32r2 (unit u-exec))) |
| 851 | ) |
| 852 | |
| 853 | (dni addv "addv" |
| 854 | ((PIPE OS) (IDOC ALU)) |
| 855 | "addv $dr,$sr" |
| 856 | (+ OP1_0 OP2_8 dr sr) |
| 857 | (parallel () |
| 858 | (set dr (add dr sr)) |
| 859 | (set condbit (add-oflag dr sr (const 0)))) |
| 860 | () |
| 861 | ) |
| 862 | |
| 863 | (dni addv3 "addv3" |
| 864 | ((IDOC ALU)) |
| 865 | "addv3 $dr,$sr,$simm16" |
| 866 | (+ OP1_8 OP2_8 dr sr simm16) |
| 867 | (parallel () |
| 868 | (set dr (add sr simm16)) |
| 869 | (set condbit (add-oflag sr simm16 (const 0)))) |
| 870 | () |
| 871 | ) |
| 872 | |
| 873 | (dni addx "addx" |
| 874 | ((PIPE OS) (IDOC ALU)) |
| 875 | "addx $dr,$sr" |
| 876 | (+ OP1_0 OP2_9 dr sr) |
| 877 | (parallel () |
| 878 | (set dr (addc dr sr condbit)) |
| 879 | (set condbit (add-cflag dr sr condbit))) |
| 880 | () |
| 881 | ) |
| 882 | |
| 883 | (dni bc8 "bc with 8 bit displacement" |
| 884 | (COND-CTI (PIPE O) (IDOC BR)) |
| 885 | "bc.s $disp8" |
| 886 | (+ OP1_7 (f-r1 12) disp8) |
| 887 | (if condbit (set pc disp8)) |
| 888 | ((m32r/d (unit u-cti)) |
| 889 | (m32rx (unit u-cti)) |
| 890 | (m32r2 (unit u-cti))) |
| 891 | ) |
| 892 | |
| 893 | (dnmi bc8r "relaxable bc8" |
| 894 | (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) |
| 895 | "bc $disp8" |
| 896 | (emit bc8 disp8) |
| 897 | ) |
| 898 | |
| 899 | (dni bc24 "bc with 24 bit displacement" |
| 900 | (COND-CTI (IDOC BR)) |
| 901 | "bc.l $disp24" |
| 902 | (+ OP1_15 (f-r1 12) disp24) |
| 903 | (if condbit (set pc disp24)) |
| 904 | ((m32r/d (unit u-cti)) |
| 905 | (m32rx (unit u-cti)) |
| 906 | (m32r2 (unit u-cti))) |
| 907 | ) |
| 908 | |
| 909 | (dnmi bc24r "relaxable bc24" |
| 910 | (COND-CTI RELAXED (IDOC BR)) |
| 911 | "bc $disp24" |
| 912 | (emit bc24 disp24) |
| 913 | ) |
| 914 | |
| 915 | (dni beq "beq" |
| 916 | (COND-CTI (IDOC BR)) |
| 917 | "beq $src1,$src2,$disp16" |
| 918 | (+ OP1_11 OP2_0 src1 src2 disp16) |
| 919 | (if (eq src1 src2) (set pc disp16)) |
| 920 | ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) |
| 921 | (m32rx (unit u-cti) (unit u-cmp (cycles 0))) |
| 922 | (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) |
| 923 | ) |
| 924 | |
| 925 | (define-pmacro (cbranch sym comment op2-op comp-op) |
| 926 | (dni sym comment (COND-CTI (IDOC BR)) |
| 927 | (.str sym " $src2,$disp16") |
| 928 | (+ OP1_11 op2-op (f-r1 0) src2 disp16) |
| 929 | (if (comp-op src2 (const WI 0)) (set pc disp16)) |
| 930 | ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) |
| 931 | (m32rx (unit u-cti) (unit u-cmp (cycles 0))) |
| 932 | (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) |
| 933 | ) |
| 934 | ) |
| 935 | (cbranch beqz "beqz" OP2_8 eq) |
| 936 | (cbranch bgez "bgez" OP2_11 ge) |
| 937 | (cbranch bgtz "bgtz" OP2_13 gt) |
| 938 | (cbranch blez "blez" OP2_12 le) |
| 939 | (cbranch bltz "bltz" OP2_10 lt) |
| 940 | (cbranch bnez "bnez" OP2_9 ne) |
| 941 | |
| 942 | (dni bl8 "bl with 8 bit displacement" |
| 943 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) |
| 944 | "bl.s $disp8" |
| 945 | (+ OP1_7 (f-r1 14) disp8) |
| 946 | (sequence () |
| 947 | (set (reg h-gr 14) |
| 948 | (add (and pc (const -4)) (const 4))) |
| 949 | (set pc disp8)) |
| 950 | ((m32r/d (unit u-cti)) |
| 951 | (m32rx (unit u-cti)) |
| 952 | (m32r2 (unit u-cti))) |
| 953 | ) |
| 954 | |
| 955 | (dnmi bl8r "relaxable bl8" |
| 956 | (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) |
| 957 | "bl $disp8" |
| 958 | (emit bl8 disp8) |
| 959 | ) |
| 960 | |
| 961 | (dni bl24 "bl with 24 bit displacement" |
| 962 | (UNCOND-CTI (IDOC BR)) |
| 963 | "bl.l $disp24" |
| 964 | (+ OP1_15 (f-r1 14) disp24) |
| 965 | (sequence () |
| 966 | (set (reg h-gr 14) (add pc (const 4))) |
| 967 | (set pc disp24)) |
| 968 | ((m32r/d (unit u-cti)) |
| 969 | (m32rx (unit u-cti)) |
| 970 | (m32r2 (unit u-cti))) |
| 971 | ) |
| 972 | |
| 973 | (dnmi bl24r "relaxable bl24" |
| 974 | (UNCOND-CTI RELAXED (IDOC BR)) |
| 975 | "bl $disp24" |
| 976 | (emit bl24 disp24) |
| 977 | ) |
| 978 | |
| 979 | (dni bcl8 "bcl with 8 bit displacement" |
| 980 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) |
| 981 | "bcl.s $disp8" |
| 982 | (+ OP1_7 (f-r1 8) disp8) |
| 983 | (if condbit |
| 984 | (sequence () |
| 985 | (set (reg h-gr 14) |
| 986 | (add (and pc (const -4)) |
| 987 | (const 4))) |
| 988 | (set pc disp8))) |
| 989 | ((m32rx (unit u-cti)) |
| 990 | (m32r2 (unit u-cti))) |
| 991 | ) |
| 992 | |
| 993 | (dnmi bcl8r "relaxable bcl8" |
| 994 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) |
| 995 | "bcl $disp8" |
| 996 | (emit bcl8 disp8) |
| 997 | ) |
| 998 | |
| 999 | (dni bcl24 "bcl with 24 bit displacement" |
| 1000 | (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) |
| 1001 | "bcl.l $disp24" |
| 1002 | (+ OP1_15 (f-r1 8) disp24) |
| 1003 | (if condbit |
| 1004 | (sequence () |
| 1005 | (set (reg h-gr 14) (add pc (const 4))) |
| 1006 | (set pc disp24))) |
| 1007 | ((m32rx (unit u-cti)) |
| 1008 | (m32r2 (unit u-cti))) |
| 1009 | ) |
| 1010 | |
| 1011 | (dnmi bcl24r "relaxable bcl24" |
| 1012 | (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) |
| 1013 | "bcl $disp24" |
| 1014 | (emit bcl24 disp24) |
| 1015 | ) |
| 1016 | |
| 1017 | (dni bnc8 "bnc with 8 bit displacement" |
| 1018 | (COND-CTI (PIPE O) (IDOC BR)) |
| 1019 | "bnc.s $disp8" |
| 1020 | (+ OP1_7 (f-r1 13) disp8) |
| 1021 | (if (not condbit) (set pc disp8)) |
| 1022 | ((m32r/d (unit u-cti)) |
| 1023 | (m32rx (unit u-cti)) |
| 1024 | (m32r2 (unit u-cti))) |
| 1025 | ) |
| 1026 | |
| 1027 | (dnmi bnc8r "relaxable bnc8" |
| 1028 | (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) |
| 1029 | "bnc $disp8" |
| 1030 | (emit bnc8 disp8) |
| 1031 | ) |
| 1032 | |
| 1033 | (dni bnc24 "bnc with 24 bit displacement" |
| 1034 | (COND-CTI (IDOC BR)) |
| 1035 | "bnc.l $disp24" |
| 1036 | (+ OP1_15 (f-r1 13) disp24) |
| 1037 | (if (not condbit) (set pc disp24)) |
| 1038 | ((m32r/d (unit u-cti)) |
| 1039 | (m32rx (unit u-cti)) |
| 1040 | (m32r2 (unit u-cti))) |
| 1041 | ) |
| 1042 | |
| 1043 | (dnmi bnc24r "relaxable bnc24" |
| 1044 | (COND-CTI RELAXED (IDOC BR)) |
| 1045 | "bnc $disp24" |
| 1046 | (emit bnc24 disp24) |
| 1047 | ) |
| 1048 | |
| 1049 | (dni bne "bne" |
| 1050 | (COND-CTI (IDOC BR)) |
| 1051 | "bne $src1,$src2,$disp16" |
| 1052 | (+ OP1_11 OP2_1 src1 src2 disp16) |
| 1053 | (if (ne src1 src2) (set pc disp16)) |
| 1054 | ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) |
| 1055 | (m32rx (unit u-cti) (unit u-cmp (cycles 0))) |
| 1056 | (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) |
| 1057 | ) |
| 1058 | |
| 1059 | (dni bra8 "bra with 8 bit displacement" |
| 1060 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) |
| 1061 | "bra.s $disp8" |
| 1062 | (+ OP1_7 (f-r1 15) disp8) |
| 1063 | (set pc disp8) |
| 1064 | ((m32r/d (unit u-cti)) |
| 1065 | (m32rx (unit u-cti)) |
| 1066 | (m32r2 (unit u-cti))) |
| 1067 | ) |
| 1068 | |
| 1069 | (dnmi bra8r "relaxable bra8" |
| 1070 | (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) |
| 1071 | "bra $disp8" |
| 1072 | (emit bra8 disp8) |
| 1073 | ) |
| 1074 | |
| 1075 | (dni bra24 "bra with 24 displacement" |
| 1076 | (UNCOND-CTI (IDOC BR)) |
| 1077 | "bra.l $disp24" |
| 1078 | (+ OP1_15 (f-r1 15) disp24) |
| 1079 | (set pc disp24) |
| 1080 | ((m32r/d (unit u-cti)) |
| 1081 | (m32rx (unit u-cti)) |
| 1082 | (m32r2 (unit u-cti))) |
| 1083 | ) |
| 1084 | |
| 1085 | (dnmi bra24r "relaxable bra24" |
| 1086 | (UNCOND-CTI RELAXED (IDOC BR)) |
| 1087 | "bra $disp24" |
| 1088 | (emit bra24 disp24) |
| 1089 | ) |
| 1090 | |
| 1091 | (dni bncl8 "bncl with 8 bit displacement" |
| 1092 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) |
| 1093 | "bncl.s $disp8" |
| 1094 | (+ OP1_7 (f-r1 9) disp8) |
| 1095 | (if (not condbit) |
| 1096 | (sequence () |
| 1097 | (set (reg h-gr 14) |
| 1098 | (add (and pc (const -4)) |
| 1099 | (const 4))) |
| 1100 | (set pc disp8))) |
| 1101 | ((m32rx (unit u-cti)) |
| 1102 | (m32r2 (unit u-cti))) |
| 1103 | ) |
| 1104 | |
| 1105 | (dnmi bncl8r "relaxable bncl8" |
| 1106 | (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) |
| 1107 | "bncl $disp8" |
| 1108 | (emit bncl8 disp8) |
| 1109 | ) |
| 1110 | |
| 1111 | (dni bncl24 "bncl with 24 bit displacement" |
| 1112 | (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) |
| 1113 | "bncl.l $disp24" |
| 1114 | (+ OP1_15 (f-r1 9) disp24) |
| 1115 | (if (not condbit) |
| 1116 | (sequence () |
| 1117 | (set (reg h-gr 14) (add pc (const 4))) |
| 1118 | (set pc disp24))) |
| 1119 | ((m32rx (unit u-cti)) |
| 1120 | (m32r2 (unit u-cti))) |
| 1121 | ) |
| 1122 | |
| 1123 | (dnmi bncl24r "relaxable bncl24" |
| 1124 | (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) |
| 1125 | "bncl $disp24" |
| 1126 | (emit bncl24 disp24) |
| 1127 | ) |
| 1128 | |
| 1129 | (dni cmp "cmp" |
| 1130 | ((PIPE OS) (IDOC ALU)) |
| 1131 | "cmp $src1,$src2" |
| 1132 | (+ OP1_0 OP2_4 src1 src2) |
| 1133 | (set condbit (lt src1 src2)) |
| 1134 | ((m32r/d (unit u-cmp)) |
| 1135 | (m32rx (unit u-cmp)) |
| 1136 | (m32r2 (unit u-cmp))) |
| 1137 | ) |
| 1138 | |
| 1139 | (dni cmpi "cmpi" |
| 1140 | ((IDOC ALU)) |
| 1141 | "cmpi $src2,$simm16" |
| 1142 | (+ OP1_8 (f-r1 0) OP2_4 src2 simm16) |
| 1143 | (set condbit (lt src2 simm16)) |
| 1144 | ((m32r/d (unit u-cmp)) |
| 1145 | (m32rx (unit u-cmp)) |
| 1146 | (m32r2 (unit u-cmp))) |
| 1147 | ) |
| 1148 | |
| 1149 | (dni cmpu "cmpu" |
| 1150 | ((PIPE OS) (IDOC ALU)) |
| 1151 | "cmpu $src1,$src2" |
| 1152 | (+ OP1_0 OP2_5 src1 src2) |
| 1153 | (set condbit (ltu src1 src2)) |
| 1154 | ((m32r/d (unit u-cmp)) |
| 1155 | (m32rx (unit u-cmp)) |
| 1156 | (m32r2 (unit u-cmp))) |
| 1157 | ) |
| 1158 | |
| 1159 | (dni cmpui "cmpui" |
| 1160 | ((IDOC ALU)) |
| 1161 | "cmpui $src2,$simm16" |
| 1162 | (+ OP1_8 (f-r1 0) OP2_5 src2 simm16) |
| 1163 | (set condbit (ltu src2 simm16)) |
| 1164 | ((m32r/d (unit u-cmp)) |
| 1165 | (m32rx (unit u-cmp)) |
| 1166 | (m32r2 (unit u-cmp))) |
| 1167 | ) |
| 1168 | |
| 1169 | (dni cmpeq "cmpeq" |
| 1170 | ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) |
| 1171 | "cmpeq $src1,$src2" |
| 1172 | (+ OP1_0 OP2_6 src1 src2) |
| 1173 | (set condbit (eq src1 src2)) |
| 1174 | ((m32rx (unit u-cmp)) |
| 1175 | (m32r2 (unit u-cmp))) |
| 1176 | ) |
| 1177 | |
| 1178 | (dni cmpz "cmpz" |
| 1179 | ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) |
| 1180 | "cmpz $src2" |
| 1181 | (+ OP1_0 OP2_7 (f-r1 0) src2) |
| 1182 | (set condbit (eq src2 (const 0))) |
| 1183 | ((m32rx (unit u-cmp)) |
| 1184 | (m32r2 (unit u-cmp))) |
| 1185 | ) |
| 1186 | |
| 1187 | (dni div "div" |
| 1188 | ((IDOC ALU)) |
| 1189 | "div $dr,$sr" |
| 1190 | (+ OP1_9 OP2_0 dr sr (f-simm16 0)) |
| 1191 | (if (ne sr (const 0)) (set dr (div dr sr))) |
| 1192 | ((m32r/d (unit u-exec (cycles 37))) |
| 1193 | (m32rx (unit u-exec (cycles 37))) |
| 1194 | (m32r2 (unit u-exec (cycles 37)))) |
| 1195 | ) |
| 1196 | |
| 1197 | (dni divu "divu" |
| 1198 | ((IDOC ALU)) |
| 1199 | "divu $dr,$sr" |
| 1200 | (+ OP1_9 OP2_1 dr sr (f-simm16 0)) |
| 1201 | (if (ne sr (const 0)) (set dr (udiv dr sr))) |
| 1202 | ((m32r/d (unit u-exec (cycles 37))) |
| 1203 | (m32rx (unit u-exec (cycles 37))) |
| 1204 | (m32r2 (unit u-exec (cycles 37)))) |
| 1205 | ) |
| 1206 | |
| 1207 | (dni rem "rem" |
| 1208 | ((IDOC ALU)) |
| 1209 | "rem $dr,$sr" |
| 1210 | (+ OP1_9 OP2_2 dr sr (f-simm16 0)) |
| 1211 | ; FIXME: Check rounding direction. |
| 1212 | (if (ne sr (const 0)) (set dr (mod dr sr))) |
| 1213 | ((m32r/d (unit u-exec (cycles 37))) |
| 1214 | (m32rx (unit u-exec (cycles 37))) |
| 1215 | (m32r2 (unit u-exec (cycles 37)))) |
| 1216 | ) |
| 1217 | |
| 1218 | (dni remu "remu" |
| 1219 | ((IDOC ALU)) |
| 1220 | "remu $dr,$sr" |
| 1221 | (+ OP1_9 OP2_3 dr sr (f-simm16 0)) |
| 1222 | ; FIXME: Check rounding direction. |
| 1223 | (if (ne sr (const 0)) (set dr (umod dr sr))) |
| 1224 | ((m32r/d (unit u-exec (cycles 37))) |
| 1225 | (m32rx (unit u-exec (cycles 37))) |
| 1226 | (m32r2 (unit u-exec (cycles 37)))) |
| 1227 | ) |
| 1228 | |
| 1229 | (dni remh "remh" |
| 1230 | ((MACH m32r2)) |
| 1231 | "remh $dr,$sr" |
| 1232 | (+ OP1_9 OP2_2 dr sr (f-simm16 #x10)) |
| 1233 | ; FIXME: Check rounding direction. |
| 1234 | (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr))) |
| 1235 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1236 | ) |
| 1237 | |
| 1238 | (dni remuh "remuh" |
| 1239 | ((MACH m32r2)) |
| 1240 | "remuh $dr,$sr" |
| 1241 | (+ OP1_9 OP2_3 dr sr (f-simm16 #x10)) |
| 1242 | ; FIXME: Check rounding direction. |
| 1243 | (if (ne sr (const 0)) (set dr (umod dr sr))) |
| 1244 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1245 | ) |
| 1246 | |
| 1247 | (dni remb "remb" |
| 1248 | ((MACH m32r2)) |
| 1249 | "remb $dr,$sr" |
| 1250 | (+ OP1_9 OP2_2 dr sr (f-simm16 #x18)) |
| 1251 | ; FIXME: Check rounding direction. |
| 1252 | (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr))) |
| 1253 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1254 | ) |
| 1255 | |
| 1256 | (dni remub "remub" |
| 1257 | ((MACH m32r2)) |
| 1258 | "remub $dr,$sr" |
| 1259 | (+ OP1_9 OP2_3 dr sr (f-simm16 #x18)) |
| 1260 | ; FIXME: Check rounding direction. |
| 1261 | (if (ne sr (const 0)) (set dr (umod dr sr))) |
| 1262 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1263 | ) |
| 1264 | |
| 1265 | (dni divuh "divuh" |
| 1266 | ((MACH m32r2)) |
| 1267 | "divuh $dr,$sr" |
| 1268 | (+ OP1_9 OP2_1 dr sr (f-simm16 #x10)) |
| 1269 | (if (ne sr (const 0)) (set dr (udiv dr sr))) |
| 1270 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1271 | ) |
| 1272 | |
| 1273 | (dni divb "divb" |
| 1274 | ((MACH m32r2)) |
| 1275 | "divb $dr,$sr" |
| 1276 | (+ OP1_9 OP2_0 dr sr (f-simm16 #x18)) |
| 1277 | (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr))) |
| 1278 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1279 | ) |
| 1280 | |
| 1281 | (dni divub "divub" |
| 1282 | ((MACH m32r2)) |
| 1283 | "divub $dr,$sr" |
| 1284 | (+ OP1_9 OP2_1 dr sr (f-simm16 #x18)) |
| 1285 | (if (ne sr (const 0)) (set dr (udiv dr sr))) |
| 1286 | ((m32r2 (unit u-exec (cycles 21)))) |
| 1287 | ) |
| 1288 | |
| 1289 | (dni divh "divh" |
| 1290 | ((MACH m32rx,m32r2) (IDOC ALU)) |
| 1291 | "divh $dr,$sr" |
| 1292 | (+ OP1_9 OP2_0 dr sr (f-simm16 #x10)) |
| 1293 | (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr))) |
| 1294 | ((m32rx (unit u-exec (cycles 21))) |
| 1295 | (m32r2 (unit u-exec (cycles 21)))) |
| 1296 | ) |
| 1297 | |
| 1298 | (dni jc "jc" |
| 1299 | (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
| 1300 | "jc $sr" |
| 1301 | (+ OP1_1 (f-r1 12) OP2_12 sr) |
| 1302 | (if condbit (set pc (and sr (const -4)))) |
| 1303 | ((m32rx (unit u-cti)) |
| 1304 | (m32r2 (unit u-cti))) |
| 1305 | ) |
| 1306 | |
| 1307 | (dni jnc "jnc" |
| 1308 | (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
| 1309 | "jnc $sr" |
| 1310 | (+ OP1_1 (f-r1 13) OP2_12 sr) |
| 1311 | (if (not condbit) (set pc (and sr (const -4)))) |
| 1312 | ((m32rx (unit u-cti)) |
| 1313 | (m32r2 (unit u-cti))) |
| 1314 | ) |
| 1315 | |
| 1316 | (dni jl "jl" |
| 1317 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) |
| 1318 | "jl $sr" |
| 1319 | (+ OP1_1 (f-r1 14) OP2_12 sr) |
| 1320 | (parallel () |
| 1321 | (set (reg h-gr 14) |
| 1322 | (add (and pc (const -4)) (const 4))) |
| 1323 | (set pc (and sr (const -4)))) |
| 1324 | ((m32r/d (unit u-cti)) |
| 1325 | (m32rx (unit u-cti)) |
| 1326 | (m32r2 (unit u-cti))) |
| 1327 | ) |
| 1328 | |
| 1329 | (dni jmp "jmp" |
| 1330 | (UNCOND-CTI (PIPE O) (IDOC BR)) |
| 1331 | "jmp $sr" |
| 1332 | (+ OP1_1 (f-r1 15) OP2_12 sr) |
| 1333 | (set pc (and sr (const -4))) |
| 1334 | ; The above works now so this kludge has been commented out. |
| 1335 | ; It's kept around because the f-r1 reference in the semantic part |
| 1336 | ; should work. |
| 1337 | ; FIXME: kludge, instruction decoding not finished. |
| 1338 | ; But this should work, so that's another FIXME. |
| 1339 | ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14)) |
| 1340 | ; FIXME: abuf->insn should be a macro of some sort. |
| 1341 | ;(sequence VOID |
| 1342 | ; (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)") |
| 1343 | ; (const SI 14)) |
| 1344 | ; (set WI (reg WI h-gr 14) |
| 1345 | ; (add WI (and WI pc (const WI -4)) (const WI 4)))) |
| 1346 | ; (set WI pc sr)) |
| 1347 | ((m32r/d (unit u-cti)) |
| 1348 | (m32rx (unit u-cti)) |
| 1349 | (m32r2 (unit u-cti))) |
| 1350 | ) |
| 1351 | |
| 1352 | (define-pmacro (no-ext-expr mode expr) expr) |
| 1353 | (define-pmacro (ext-expr mode expr) (ext mode expr)) |
| 1354 | (define-pmacro (zext-expr mode expr) (zext mode expr)) |
| 1355 | |
| 1356 | (define-pmacro (load-op suffix op2-op mode ext-op) |
| 1357 | (begin |
| 1358 | (dni (.sym ld suffix) (.str "ld" suffix) |
| 1359 | ((PIPE O) (IDOC MEM)) |
| 1360 | (.str "ld" suffix " $dr,@$sr") |
| 1361 | (+ OP1_2 op2-op dr sr) |
| 1362 | (set dr (ext-op WI (mem mode sr))) |
| 1363 | ((m32r/d (unit u-load)) |
| 1364 | (m32rx (unit u-load)) |
| 1365 | (m32r2 (unit u-load))) |
| 1366 | ) |
| 1367 | (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2") |
| 1368 | (NO-DIS (PIPE O) (IDOC MEM)) |
| 1369 | (.str "ld" suffix " $dr,@($sr)") |
| 1370 | (emit (.sym ld suffix) dr sr)) |
| 1371 | (dni (.sym ld suffix -d) (.str "ld" suffix "-d") |
| 1372 | ((IDOC MEM)) |
| 1373 | (.str "ld" suffix " $dr,@($slo16,$sr)") |
| 1374 | (+ OP1_10 op2-op dr sr slo16) |
| 1375 | (set dr (ext-op WI (mem mode (add sr slo16)))) |
| 1376 | ((m32r/d (unit u-load (cycles 2))) |
| 1377 | (m32rx (unit u-load (cycles 2))) |
| 1378 | (m32r2 (unit u-load (cycles 2)))) |
| 1379 | ) |
| 1380 | (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2") |
| 1381 | (NO-DIS (IDOC MEM)) |
| 1382 | (.str "ld" suffix " $dr,@($sr,$slo16)") |
| 1383 | (emit (.sym ld suffix -d) dr sr slo16)) |
| 1384 | ) |
| 1385 | ) |
| 1386 | (load-op "" OP2_12 WI no-ext-expr) |
| 1387 | (load-op b OP2_8 QI ext-expr) |
| 1388 | (load-op h OP2_10 HI ext-expr) |
| 1389 | (load-op ub OP2_9 QI zext-expr) |
| 1390 | (load-op uh OP2_11 HI zext-expr) |
| 1391 | |
| 1392 | (dni ld-plus "ld+" |
| 1393 | ((PIPE O) (IDOC MEM)) |
| 1394 | "ld $dr,@$sr+" |
| 1395 | (+ OP1_2 dr OP2_14 sr) |
| 1396 | (parallel () |
| 1397 | ; wip: memory addresses in profiling support |
| 1398 | ;(set dr (name ld-mem (mem WI sr))) |
| 1399 | (set dr (mem WI sr)) |
| 1400 | (set sr (add sr (const 4)))) |
| 1401 | ; Note: `pred' is the constraint. Also useful here is (ref name) |
| 1402 | ; and returns true if operand <name> was referenced |
| 1403 | ; (where "referenced" means _read_ if input operand and _written_ if |
| 1404 | ; output operand). |
| 1405 | ; args to unit are "unit-name (name1 value1) ..." |
| 1406 | ; - cycles(done),issue,pred are also specified this way |
| 1407 | ; - if unspecified, default is used |
| 1408 | ; - for ins/outs, extra arg is passed that says what was specified |
| 1409 | ; - this is AND'd with `written' for outs |
| 1410 | ((m32r/d (unit u-load (pred (const 1))) |
| 1411 | (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) |
| 1412 | (m32rx (unit u-load) |
| 1413 | (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) |
| 1414 | (m32r2 (unit u-load) |
| 1415 | (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) |
| 1416 | ) |
| 1417 | ) |
| 1418 | |
| 1419 | (dnmi pop "pop" |
| 1420 | ((PIPE O) (IDOC MEM)) |
| 1421 | "pop $dr" |
| 1422 | (emit ld-plus dr (sr 15)) ; "ld %0,@sp+" |
| 1423 | ) |
| 1424 | |
| 1425 | (dni ld24 "ld24" |
| 1426 | ((IDOC MEM)) |
| 1427 | "ld24 $dr,$uimm24" |
| 1428 | (+ OP1_14 dr uimm24) |
| 1429 | (set dr uimm24) |
| 1430 | () |
| 1431 | ) |
| 1432 | |
| 1433 | ; ldi8 appears before ldi16 so we try the shorter version first |
| 1434 | |
| 1435 | (dni ldi8 "ldi8" |
| 1436 | ((PIPE OS) (IDOC ALU)) |
| 1437 | "ldi8 $dr,$simm8" |
| 1438 | (+ OP1_6 dr simm8) |
| 1439 | (set dr simm8) |
| 1440 | () |
| 1441 | ) |
| 1442 | |
| 1443 | (dnmi ldi8a "ldi8 alias" |
| 1444 | ((PIPE OS) (IDOC ALU)) |
| 1445 | "ldi $dr,$simm8" |
| 1446 | (emit ldi8 dr simm8) |
| 1447 | ) |
| 1448 | |
| 1449 | (dni ldi16 "ldi16" |
| 1450 | ((IDOC ALU)) |
| 1451 | "ldi16 $dr,$hash$slo16" |
| 1452 | (+ OP1_9 OP2_15 (f-r2 0) dr slo16) |
| 1453 | (set dr slo16) |
| 1454 | () |
| 1455 | ) |
| 1456 | |
| 1457 | (dnmi ldi16a "ldi16 alias" |
| 1458 | ((IDOC ALU)) |
| 1459 | "ldi $dr,$hash$slo16" |
| 1460 | (emit ldi16 dr slo16) |
| 1461 | ) |
| 1462 | |
| 1463 | (dni lock "lock" |
| 1464 | ((PIPE O) (IDOC MISC)) |
| 1465 | "lock $dr,@$sr" |
| 1466 | (+ OP1_2 OP2_13 dr sr) |
| 1467 | (sequence () |
| 1468 | (set (reg h-lock) (const BI 1)) |
| 1469 | (set dr (mem WI sr))) |
| 1470 | ((m32r/d (unit u-load)) |
| 1471 | (m32rx (unit u-load)) |
| 1472 | (m32r2 (unit u-load))) |
| 1473 | ) |
| 1474 | |
| 1475 | (dni machi "machi" |
| 1476 | ( |
| 1477 | ; (MACH m32r) is a temporary hack. This insn collides with machi-a |
| 1478 | ; in the simulator so disable it for m32rx. |
| 1479 | (MACH m32r) (PIPE S) (IDOC MAC) |
| 1480 | ) |
| 1481 | "machi $src1,$src2" |
| 1482 | (+ OP1_3 OP2_4 src1 src2) |
| 1483 | ; FIXME: TRACE_RESULT will print the wrong thing since we |
| 1484 | ; alter one of the arguments. |
| 1485 | (set accum |
| 1486 | (sra DI |
| 1487 | (sll DI |
| 1488 | (add DI |
| 1489 | accum |
| 1490 | (mul DI |
| 1491 | (ext DI (and WI src1 (const #xffff0000))) |
| 1492 | (ext DI (trunc HI (sra WI src2 (const 16)))))) |
| 1493 | (const 8)) |
| 1494 | (const 8))) |
| 1495 | ((m32r/d (unit u-mac))) |
| 1496 | ) |
| 1497 | |
| 1498 | (dni machi-a "machi-a" |
| 1499 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1500 | "machi $src1,$src2,$acc" |
| 1501 | (+ OP1_3 src1 acc (f-op23 4) src2) |
| 1502 | (set acc |
| 1503 | (sra DI |
| 1504 | (sll DI |
| 1505 | (add DI |
| 1506 | acc |
| 1507 | (mul DI |
| 1508 | (ext DI (and WI src1 (const #xffff0000))) |
| 1509 | (ext DI (trunc HI (sra WI src2 (const 16)))))) |
| 1510 | (const 8)) |
| 1511 | (const 8))) |
| 1512 | ((m32rx (unit u-mac)) |
| 1513 | (m32r2 (unit u-mac))) |
| 1514 | ) |
| 1515 | |
| 1516 | (dni maclo "maclo" |
| 1517 | ((MACH m32r) (PIPE S) (IDOC MAC)) |
| 1518 | "maclo $src1,$src2" |
| 1519 | (+ OP1_3 OP2_5 src1 src2) |
| 1520 | (set accum |
| 1521 | (sra DI |
| 1522 | (sll DI |
| 1523 | (add DI |
| 1524 | accum |
| 1525 | (mul DI |
| 1526 | (ext DI (sll WI src1 (const 16))) |
| 1527 | (ext DI (trunc HI src2)))) |
| 1528 | (const 8)) |
| 1529 | (const 8))) |
| 1530 | ((m32r/d (unit u-mac))) |
| 1531 | ) |
| 1532 | |
| 1533 | (dni maclo-a "maclo-a" |
| 1534 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1535 | "maclo $src1,$src2,$acc" |
| 1536 | (+ OP1_3 src1 acc (f-op23 5) src2) |
| 1537 | (set acc |
| 1538 | (sra DI |
| 1539 | (sll DI |
| 1540 | (add DI |
| 1541 | acc |
| 1542 | (mul DI |
| 1543 | (ext DI (sll WI src1 (const 16))) |
| 1544 | (ext DI (trunc HI src2)))) |
| 1545 | (const 8)) |
| 1546 | (const 8))) |
| 1547 | ((m32rx (unit u-mac)) |
| 1548 | (m32r2 (unit u-mac))) |
| 1549 | ) |
| 1550 | |
| 1551 | (dni macwhi "macwhi" |
| 1552 | ((MACH m32r) (PIPE S) (IDOC MAC)) |
| 1553 | "macwhi $src1,$src2" |
| 1554 | (+ OP1_3 OP2_6 src1 src2) |
| 1555 | (set accum |
| 1556 | (sra DI |
| 1557 | (sll DI |
| 1558 | (add DI |
| 1559 | accum |
| 1560 | (mul DI |
| 1561 | (ext DI src1) |
| 1562 | (ext DI (trunc HI (sra WI src2 (const 16)))))) |
| 1563 | (const 8)) |
| 1564 | (const 8))) |
| 1565 | ((m32r/d (unit u-mac))) |
| 1566 | ) |
| 1567 | |
| 1568 | (dni macwhi-a "macwhi-a" |
| 1569 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) |
| 1570 | "macwhi $src1,$src2,$acc" |
| 1571 | (+ OP1_3 src1 acc (f-op23 6) src2) |
| 1572 | ; Note that this doesn't do the sign extension, which is correct. |
| 1573 | (set acc |
| 1574 | (add acc |
| 1575 | (mul (ext DI src1) |
| 1576 | (ext DI (trunc HI (sra src2 (const 16))))))) |
| 1577 | ((m32rx (unit u-mac)) |
| 1578 | (m32r2 (unit u-mac))) |
| 1579 | ) |
| 1580 | |
| 1581 | (dni macwlo "macwlo" |
| 1582 | ((MACH m32r) (PIPE S) (IDOC MAC)) |
| 1583 | "macwlo $src1,$src2" |
| 1584 | (+ OP1_3 OP2_7 src1 src2) |
| 1585 | (set accum |
| 1586 | (sra DI |
| 1587 | (sll DI |
| 1588 | (add DI |
| 1589 | accum |
| 1590 | (mul DI |
| 1591 | (ext DI src1) |
| 1592 | (ext DI (trunc HI src2)))) |
| 1593 | (const 8)) |
| 1594 | (const 8))) |
| 1595 | ((m32r/d (unit u-mac))) |
| 1596 | ) |
| 1597 | |
| 1598 | (dni macwlo-a "macwlo-a" |
| 1599 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) |
| 1600 | "macwlo $src1,$src2,$acc" |
| 1601 | (+ OP1_3 src1 acc (f-op23 7) src2) |
| 1602 | ; Note that this doesn't do the sign extension, which is correct. |
| 1603 | (set acc |
| 1604 | (add acc |
| 1605 | (mul (ext DI src1) |
| 1606 | (ext DI (trunc HI src2))))) |
| 1607 | ((m32rx (unit u-mac)) |
| 1608 | (m32r2 (unit u-mac))) |
| 1609 | ) |
| 1610 | |
| 1611 | (dni mul "mul" |
| 1612 | ((PIPE S) (IDOC ALU)) |
| 1613 | "mul $dr,$sr" |
| 1614 | (+ OP1_1 OP2_6 dr sr) |
| 1615 | (set dr (mul dr sr)) |
| 1616 | ((m32r/d (unit u-exec (cycles 4))) |
| 1617 | (m32rx (unit u-exec (cycles 4))) |
| 1618 | (m32r2 (unit u-exec (cycles 4)))) |
| 1619 | ) |
| 1620 | |
| 1621 | (dni mulhi "mulhi" |
| 1622 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1623 | "mulhi $src1,$src2" |
| 1624 | (+ OP1_3 OP2_0 src1 src2) |
| 1625 | (set accum |
| 1626 | (sra DI |
| 1627 | (sll DI |
| 1628 | (mul DI |
| 1629 | (ext DI (and WI src1 (const #xffff0000))) |
| 1630 | (ext DI (trunc HI (sra WI src2 (const 16))))) |
| 1631 | (const 16)) |
| 1632 | (const 16))) |
| 1633 | ((m32r/d (unit u-mac))) |
| 1634 | ) |
| 1635 | |
| 1636 | (dni mulhi-a "mulhi-a" |
| 1637 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1638 | "mulhi $src1,$src2,$acc" |
| 1639 | (+ OP1_3 (f-op23 0) src1 acc src2) |
| 1640 | (set acc |
| 1641 | (sra DI |
| 1642 | (sll DI |
| 1643 | (mul DI |
| 1644 | (ext DI (and WI src1 (const #xffff0000))) |
| 1645 | (ext DI (trunc HI (sra WI src2 (const 16))))) |
| 1646 | (const 16)) |
| 1647 | (const 16))) |
| 1648 | ((m32rx (unit u-mac)) |
| 1649 | (m32r2 (unit u-mac))) |
| 1650 | ) |
| 1651 | |
| 1652 | (dni mullo "mullo" |
| 1653 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1654 | "mullo $src1,$src2" |
| 1655 | (+ OP1_3 OP2_1 src1 src2) |
| 1656 | (set accum |
| 1657 | (sra DI |
| 1658 | (sll DI |
| 1659 | (mul DI |
| 1660 | (ext DI (sll WI src1 (const 16))) |
| 1661 | (ext DI (trunc HI src2))) |
| 1662 | (const 16)) |
| 1663 | (const 16))) |
| 1664 | ((m32r/d (unit u-mac))) |
| 1665 | ) |
| 1666 | |
| 1667 | (dni mullo-a "mullo-a" |
| 1668 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1669 | "mullo $src1,$src2,$acc" |
| 1670 | (+ OP1_3 src1 acc (f-op23 1) src2) |
| 1671 | (set acc |
| 1672 | (sra DI |
| 1673 | (sll DI |
| 1674 | (mul DI |
| 1675 | (ext DI (sll WI src1 (const 16))) |
| 1676 | (ext DI (trunc HI src2))) |
| 1677 | (const 16)) |
| 1678 | (const 16))) |
| 1679 | ((m32rx (unit u-mac)) |
| 1680 | (m32r2 (unit u-mac))) |
| 1681 | ) |
| 1682 | |
| 1683 | (dni mulwhi "mulwhi" |
| 1684 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1685 | "mulwhi $src1,$src2" |
| 1686 | (+ OP1_3 OP2_2 src1 src2) |
| 1687 | (set accum |
| 1688 | (sra DI |
| 1689 | (sll DI |
| 1690 | (mul DI |
| 1691 | (ext DI src1) |
| 1692 | (ext DI (trunc HI (sra WI src2 (const 16))))) |
| 1693 | (const 8)) |
| 1694 | (const 8))) |
| 1695 | ((m32r/d (unit u-mac))) |
| 1696 | ) |
| 1697 | |
| 1698 | (dni mulwhi-a "mulwhi-a" |
| 1699 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) |
| 1700 | "mulwhi $src1,$src2,$acc" |
| 1701 | (+ OP1_3 src1 acc (f-op23 2) src2) |
| 1702 | ; Note that this doesn't do the sign extension, which is correct. |
| 1703 | (set acc |
| 1704 | (mul (ext DI src1) |
| 1705 | (ext DI (trunc HI (sra src2 (const 16)))))) |
| 1706 | ((m32rx (unit u-mac)) |
| 1707 | (m32r2 (unit u-mac))) |
| 1708 | ) |
| 1709 | |
| 1710 | (dni mulwlo "mulwlo" |
| 1711 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1712 | "mulwlo $src1,$src2" |
| 1713 | (+ OP1_3 OP2_3 src1 src2) |
| 1714 | (set accum |
| 1715 | (sra DI |
| 1716 | (sll DI |
| 1717 | (mul DI |
| 1718 | (ext DI src1) |
| 1719 | (ext DI (trunc HI src2))) |
| 1720 | (const 8)) |
| 1721 | (const 8))) |
| 1722 | ((m32r/d (unit u-mac))) |
| 1723 | ) |
| 1724 | |
| 1725 | (dni mulwlo-a "mulwlo-a" |
| 1726 | ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) |
| 1727 | "mulwlo $src1,$src2,$acc" |
| 1728 | (+ OP1_3 src1 acc (f-op23 3) src2) |
| 1729 | ; Note that this doesn't do the sign extension, which is correct. |
| 1730 | (set acc |
| 1731 | (mul (ext DI src1) |
| 1732 | (ext DI (trunc HI src2)))) |
| 1733 | ((m32rx (unit u-mac)) |
| 1734 | (m32r2 (unit u-mac))) |
| 1735 | ) |
| 1736 | |
| 1737 | (dni mv "mv" |
| 1738 | ((PIPE OS) (IDOC ALU)) |
| 1739 | "mv $dr,$sr" |
| 1740 | (+ OP1_1 OP2_8 dr sr) |
| 1741 | (set dr sr) |
| 1742 | () |
| 1743 | ) |
| 1744 | |
| 1745 | (dni mvfachi "mvfachi" |
| 1746 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1747 | "mvfachi $dr" |
| 1748 | (+ OP1_5 OP2_15 (f-r2 0) dr) |
| 1749 | (set dr (trunc WI (sra DI accum (const 32)))) |
| 1750 | ((m32r/d (unit u-exec (cycles 2)))) |
| 1751 | ) |
| 1752 | |
| 1753 | (dni mvfachi-a "mvfachi-a" |
| 1754 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1755 | "mvfachi $dr,$accs" |
| 1756 | (+ OP1_5 dr OP2_15 accs (f-op3 0)) |
| 1757 | (set dr (trunc WI (sra DI accs (const 32)))) |
| 1758 | ((m32rx (unit u-exec (cycles 2))) |
| 1759 | (m32r2 (unit u-exec (cycles 2)))) |
| 1760 | ) |
| 1761 | |
| 1762 | (dni mvfaclo "mvfaclo" |
| 1763 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1764 | "mvfaclo $dr" |
| 1765 | (+ OP1_5 OP2_15 (f-r2 1) dr) |
| 1766 | (set dr (trunc WI accum)) |
| 1767 | ((m32r/d (unit u-exec (cycles 2)))) |
| 1768 | ) |
| 1769 | |
| 1770 | (dni mvfaclo-a "mvfaclo-a" |
| 1771 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1772 | "mvfaclo $dr,$accs" |
| 1773 | (+ OP1_5 dr OP2_15 accs (f-op3 1)) |
| 1774 | (set dr (trunc WI accs)) |
| 1775 | ((m32rx (unit u-exec (cycles 2))) |
| 1776 | (m32r2 (unit u-exec (cycles 2)))) |
| 1777 | ) |
| 1778 | |
| 1779 | (dni mvfacmi "mvfacmi" |
| 1780 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1781 | "mvfacmi $dr" |
| 1782 | (+ OP1_5 OP2_15 (f-r2 2) dr) |
| 1783 | (set dr (trunc WI (sra DI accum (const 16)))) |
| 1784 | ((m32r/d (unit u-exec (cycles 2)))) |
| 1785 | ) |
| 1786 | |
| 1787 | (dni mvfacmi-a "mvfacmi-a" |
| 1788 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1789 | "mvfacmi $dr,$accs" |
| 1790 | (+ OP1_5 dr OP2_15 accs (f-op3 2)) |
| 1791 | (set dr (trunc WI (sra DI accs (const 16)))) |
| 1792 | ((m32rx (unit u-exec (cycles 2))) |
| 1793 | (m32r2 (unit u-exec (cycles 2)))) |
| 1794 | ) |
| 1795 | |
| 1796 | (dni mvfc "mvfc" |
| 1797 | ((PIPE O) (IDOC MISC)) |
| 1798 | "mvfc $dr,$scr" |
| 1799 | (+ OP1_1 OP2_9 dr scr) |
| 1800 | (set dr scr) |
| 1801 | () |
| 1802 | ) |
| 1803 | |
| 1804 | (dni mvtachi "mvtachi" |
| 1805 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1806 | "mvtachi $src1" |
| 1807 | (+ OP1_5 OP2_7 (f-r2 0) src1) |
| 1808 | (set accum |
| 1809 | (or DI |
| 1810 | (and DI accum (const DI #xffffffff)) |
| 1811 | (sll DI (ext DI src1) (const 32)))) |
| 1812 | ((m32r/d (unit u-exec (in sr src1)))) |
| 1813 | ) |
| 1814 | |
| 1815 | (dni mvtachi-a "mvtachi-a" |
| 1816 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1817 | "mvtachi $src1,$accs" |
| 1818 | (+ OP1_5 src1 OP2_7 accs (f-op3 0)) |
| 1819 | (set accs |
| 1820 | (or DI |
| 1821 | (and DI accs (const DI #xffffffff)) |
| 1822 | (sll DI (ext DI src1) (const 32)))) |
| 1823 | ((m32rx (unit u-exec (in sr src1))) |
| 1824 | (m32r2 (unit u-exec (in sr src1)))) |
| 1825 | ) |
| 1826 | |
| 1827 | (dni mvtaclo "mvtaclo" |
| 1828 | ((MACH m32r) (PIPE S) (IDOC ACCUM)) |
| 1829 | "mvtaclo $src1" |
| 1830 | (+ OP1_5 OP2_7 (f-r2 1) src1) |
| 1831 | (set accum |
| 1832 | (or DI |
| 1833 | (and DI accum (const DI #xffffffff00000000)) |
| 1834 | (zext DI src1))) |
| 1835 | ((m32r/d (unit u-exec (in sr src1)))) |
| 1836 | ) |
| 1837 | |
| 1838 | (dni mvtaclo-a "mvtaclo-a" |
| 1839 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 1840 | "mvtaclo $src1,$accs" |
| 1841 | (+ OP1_5 src1 OP2_7 accs (f-op3 1)) |
| 1842 | (set accs |
| 1843 | (or DI |
| 1844 | (and DI accs (const DI #xffffffff00000000)) |
| 1845 | (zext DI src1))) |
| 1846 | ((m32rx (unit u-exec (in sr src1))) |
| 1847 | (m32r2 (unit u-exec (in sr src1)))) |
| 1848 | ) |
| 1849 | |
| 1850 | (dni mvtc "mvtc" |
| 1851 | ((PIPE O) (IDOC MISC)) |
| 1852 | "mvtc $sr,$dcr" |
| 1853 | (+ OP1_1 OP2_10 dcr sr) |
| 1854 | (set dcr sr) |
| 1855 | () |
| 1856 | ) |
| 1857 | |
| 1858 | (dni neg "neg" |
| 1859 | ((PIPE OS) (IDOC ALU)) |
| 1860 | "neg $dr,$sr" |
| 1861 | (+ OP1_0 OP2_3 dr sr) |
| 1862 | (set dr (neg sr)) |
| 1863 | () |
| 1864 | ) |
| 1865 | |
| 1866 | (dni nop "nop" |
| 1867 | ((PIPE OS) (IDOC MISC)) |
| 1868 | "nop" |
| 1869 | (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0)) |
| 1870 | (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n") |
| 1871 | ; FIXME: quick hack: parallel nops don't contribute to cycle count. |
| 1872 | ; Other kinds of nops do however (which we currently ignore). |
| 1873 | ((m32r/d (unit u-exec (cycles 0))) |
| 1874 | (m32rx (unit u-exec (cycles 0))) |
| 1875 | (m32r2 (unit u-exec (cycles 0)))) |
| 1876 | ) |
| 1877 | |
| 1878 | (dni not "not" |
| 1879 | ((PIPE OS) (IDOC ALU)) |
| 1880 | "not $dr,$sr" |
| 1881 | (+ OP1_0 OP2_11 dr sr) |
| 1882 | (set dr (inv sr)) |
| 1883 | () |
| 1884 | ) |
| 1885 | |
| 1886 | (dni rac "rac" |
| 1887 | ((MACH m32r) (PIPE S) (IDOC MAC)) |
| 1888 | "rac" |
| 1889 | (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0)) |
| 1890 | (sequence ((DI tmp1)) |
| 1891 | (set tmp1 (sll DI accum (const 1))) |
| 1892 | (set tmp1 (add DI tmp1 (const DI #x8000))) |
| 1893 | (set accum |
| 1894 | (cond DI |
| 1895 | ((gt tmp1 (const DI #x00007fffffff0000)) |
| 1896 | (const DI #x00007fffffff0000)) |
| 1897 | ((lt tmp1 (const DI #xffff800000000000)) |
| 1898 | (const DI #xffff800000000000)) |
| 1899 | (else (and tmp1 (const DI #xffffffffffff0000))))) |
| 1900 | ) |
| 1901 | ((m32r/d (unit u-mac))) |
| 1902 | ) |
| 1903 | |
| 1904 | (dni rac-dsi "rac-dsi" |
| 1905 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1906 | "rac $accd,$accs,$imm1" |
| 1907 | (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1) |
| 1908 | (sequence ((DI tmp1)) |
| 1909 | (set tmp1 (sll accs imm1)) |
| 1910 | (set tmp1 (add tmp1 (const DI #x8000))) |
| 1911 | (set accd |
| 1912 | (cond DI |
| 1913 | ((gt tmp1 (const DI #x00007fffffff0000)) |
| 1914 | (const DI #x00007fffffff0000)) |
| 1915 | ((lt tmp1 (const DI #xffff800000000000)) |
| 1916 | (const DI #xffff800000000000)) |
| 1917 | (else (and tmp1 (const DI #xffffffffffff0000))))) |
| 1918 | ) |
| 1919 | ((m32rx (unit u-mac)) |
| 1920 | (m32r2 (unit u-mac))) |
| 1921 | ) |
| 1922 | |
| 1923 | (dnmi rac-d "rac-d" |
| 1924 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1925 | "rac $accd" |
| 1926 | (emit rac-dsi accd (f-accs 0) (f-imm1 0)) |
| 1927 | ) |
| 1928 | |
| 1929 | (dnmi rac-ds "rac-ds" |
| 1930 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1931 | "rac $accd,$accs" |
| 1932 | (emit rac-dsi accd accs (f-imm1 0)) |
| 1933 | ) |
| 1934 | |
| 1935 | |
| 1936 | (dni rach "rach" |
| 1937 | ((MACH m32r) (PIPE S) (IDOC MAC)) |
| 1938 | "rach" |
| 1939 | (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0)) |
| 1940 | (sequence ((DI tmp1)) |
| 1941 | ; Lop off top 8 bits. |
| 1942 | ; The sign bit we want to use is bit 55 so the 64 bit value |
| 1943 | ; isn't properly signed which we deal with in the if's below. |
| 1944 | (set tmp1 (and accum (const DI #xffffffffffffff))) |
| 1945 | (if (andif (ge tmp1 (const DI #x003fff80000000)) |
| 1946 | (le tmp1 (const DI #x7fffffffffffff))) |
| 1947 | (set tmp1 (const DI #x003fff80000000)) |
| 1948 | ; else part |
| 1949 | (if (andif (ge tmp1 (const DI #x80000000000000)) |
| 1950 | (le tmp1 (const DI #xffc00000000000))) |
| 1951 | (set tmp1 (const DI #xffc00000000000)) |
| 1952 | (set tmp1 (and (add accum (const DI #x40000000)) |
| 1953 | (const DI #xffffffff80000000))))) |
| 1954 | (set tmp1 (sll tmp1 (const 1))) |
| 1955 | ; Sign extend top 8 bits. |
| 1956 | (set accum |
| 1957 | ; FIXME: 7? |
| 1958 | (sra DI (sll DI tmp1 (const 7)) (const 7))) |
| 1959 | ) |
| 1960 | ((m32r/d (unit u-mac))) |
| 1961 | ) |
| 1962 | |
| 1963 | (dni rach-dsi "rach-dsi" |
| 1964 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1965 | "rach $accd,$accs,$imm1" |
| 1966 | (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1) |
| 1967 | (sequence ((DI tmp1)) |
| 1968 | (set tmp1 (sll accs imm1)) |
| 1969 | (set tmp1 (add tmp1 (const DI #x80000000))) |
| 1970 | (set accd |
| 1971 | (cond DI |
| 1972 | ((gt tmp1 (const DI #x00007fff00000000)) |
| 1973 | (const DI #x00007fff00000000)) |
| 1974 | ((lt tmp1 (const DI #xffff800000000000)) |
| 1975 | (const DI #xffff800000000000)) |
| 1976 | (else (and tmp1 (const DI #xffffffff00000000))))) |
| 1977 | ) |
| 1978 | ((m32rx (unit u-mac)) |
| 1979 | (m32r2 (unit u-mac))) |
| 1980 | ) |
| 1981 | |
| 1982 | (dnmi rach-d "rach-d" |
| 1983 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1984 | "rach $accd" |
| 1985 | (emit rach-dsi accd (f-accs 0) (f-imm1 0)) |
| 1986 | ) |
| 1987 | |
| 1988 | (dnmi rach-ds "rach-ds" |
| 1989 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 1990 | "rach $accd,$accs" |
| 1991 | (emit rach-dsi accd accs (f-imm1 0)) |
| 1992 | ) |
| 1993 | |
| 1994 | (dni rte "rte" |
| 1995 | (UNCOND-CTI (PIPE O) (IDOC BR)) |
| 1996 | "rte" |
| 1997 | (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6)) |
| 1998 | (sequence () |
| 1999 | ; pc = bpc & -4 |
| 2000 | (set pc (and (reg h-cr 6) (const -4))) |
| 2001 | ; bpc = bbpc |
| 2002 | (set (reg h-cr 6) (reg h-cr 14)) |
| 2003 | ; psw = bpsw |
| 2004 | (set (reg h-psw) (reg h-bpsw)) |
| 2005 | ; bpsw = bbpsw |
| 2006 | (set (reg h-bpsw) (reg h-bbpsw)) |
| 2007 | ) |
| 2008 | () |
| 2009 | ) |
| 2010 | |
| 2011 | (dni seth "seth" |
| 2012 | ((IDOC ALU)) |
| 2013 | "seth $dr,$hash$hi16" |
| 2014 | (+ OP1_13 OP2_12 dr (f-r2 0) hi16) |
| 2015 | (set dr (sll WI hi16 (const 16))) |
| 2016 | () |
| 2017 | ) |
| 2018 | |
| 2019 | (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op) |
| 2020 | (begin |
| 2021 | (dni sym sym ((PIPE O_OS) (IDOC ALU)) |
| 2022 | (.str sym " $dr,$sr") |
| 2023 | (+ OP1_1 op2-r-op dr sr) |
| 2024 | (set dr (sem-op dr (and sr (const 31)))) |
| 2025 | () |
| 2026 | ) |
| 2027 | (dni (.sym sym "3") sym ((IDOC ALU)) |
| 2028 | (.str sym "3 $dr,$sr,$simm16") |
| 2029 | (+ OP1_9 op2-3-op dr sr simm16) |
| 2030 | (set dr (sem-op sr (and WI simm16 (const 31)))) |
| 2031 | () |
| 2032 | ) |
| 2033 | (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU)) |
| 2034 | (.str sym "i $dr,$uimm5") |
| 2035 | (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5) |
| 2036 | (set dr (sem-op dr uimm5)) |
| 2037 | () |
| 2038 | ) |
| 2039 | ) |
| 2040 | ) |
| 2041 | (shift-op sll OP2_4 OP2_12 2 sll) |
| 2042 | (shift-op sra OP2_2 OP2_10 1 sra) |
| 2043 | (shift-op srl OP2_0 OP2_8 0 srl) |
| 2044 | |
| 2045 | (define-pmacro (store-op suffix op2-op mode) |
| 2046 | (begin |
| 2047 | (dni (.sym st suffix) (.str "st" suffix) |
| 2048 | ((PIPE O) (IDOC MEM)) |
| 2049 | (.str "st" suffix " $src1,@$src2") |
| 2050 | (+ OP1_2 op2-op src1 src2) |
| 2051 | (set mode (mem mode src2) src1) |
| 2052 | ((m32r/d (unit u-store (cycles 1))) |
| 2053 | (m32rx (unit u-store (cycles 1))) |
| 2054 | (m32r2 (unit u-store (cycles 1)))) |
| 2055 | ) |
| 2056 | (dnmi (.sym st suffix "-2") (.str "st" suffix "-2") |
| 2057 | (NO-DIS (PIPE O) (IDOC MEM)) |
| 2058 | (.str "st" suffix " $src1,@($src2)") |
| 2059 | (emit (.sym st suffix) src1 src2)) |
| 2060 | (dni (.sym st suffix -d) (.str "st" suffix "-d") |
| 2061 | ((IDOC MEM)) |
| 2062 | (.str "st" suffix " $src1,@($slo16,$src2)") |
| 2063 | (+ OP1_10 op2-op src1 src2 slo16) |
| 2064 | (set mode (mem mode (add src2 slo16)) src1) |
| 2065 | ((m32r/d (unit u-store (cycles 2))) |
| 2066 | (m32rx (unit u-store (cycles 2))) |
| 2067 | (m32r2 (unit u-store (cycles 2)))) |
| 2068 | ) |
| 2069 | (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2") |
| 2070 | (NO-DIS (IDOC MEM)) |
| 2071 | (.str "st" suffix " $src1,@($src2,$slo16)") |
| 2072 | (emit (.sym st suffix -d) src1 src2 slo16)) |
| 2073 | ) |
| 2074 | ) |
| 2075 | (store-op "" OP2_4 WI) |
| 2076 | (store-op b OP2_0 QI) |
| 2077 | (store-op h OP2_2 HI) |
| 2078 | |
| 2079 | (dni st-plus "st+" |
| 2080 | ((PIPE O) (IDOC MEM)) |
| 2081 | "st $src1,@+$src2" |
| 2082 | (+ OP1_2 OP2_6 src1 src2) |
| 2083 | ; This has to be coded carefully to avoid an "earlyclobber" of src2. |
| 2084 | (sequence ((WI new-src2)) |
| 2085 | (set new-src2 (add WI src2 (const WI 4))) |
| 2086 | (set (mem WI new-src2) src1) |
| 2087 | (set src2 new-src2)) |
| 2088 | ((m32r/d (unit u-store) |
| 2089 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2090 | (m32rx (unit u-store) |
| 2091 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2092 | (m32r2 (unit u-store) |
| 2093 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2094 | ) |
| 2095 | ) |
| 2096 | |
| 2097 | (dni sth-plus "sth+" |
| 2098 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL) |
| 2099 | "sth $src1,@$src2+" |
| 2100 | (+ OP1_2 OP2_3 src1 src2) |
| 2101 | ; This has to be coded carefully to avoid an "earlyclobber" of src2. |
| 2102 | (sequence ((WI new-src2)) |
| 2103 | (set new-src2 src2) |
| 2104 | (set (mem HI new-src2) src1) |
| 2105 | (set src2 (add new-src2 (const 2)))) |
| 2106 | ((m32rx (unit u-store) |
| 2107 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2108 | (m32r2 (unit u-store) |
| 2109 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2110 | ) |
| 2111 | ) |
| 2112 | |
| 2113 | (dni stb-plus "stb+" |
| 2114 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL) |
| 2115 | "stb $src1,@$src2+" |
| 2116 | (+ OP1_2 OP2_1 src1 src2) |
| 2117 | ; This has to be coded carefully to avoid an "earlyclobber" of src2. |
| 2118 | (sequence ((WI new-src2)) |
| 2119 | (set new-src2 src2) |
| 2120 | (set (mem QI new-src2) src1) |
| 2121 | (set src2 (add new-src2 (const 1)))) |
| 2122 | ((m32rx (unit u-store) |
| 2123 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2124 | (m32r2 (unit u-store) |
| 2125 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2126 | ) |
| 2127 | ) |
| 2128 | |
| 2129 | (dni st-minus "st-" |
| 2130 | ((PIPE O) (IDOC MEM)) |
| 2131 | "st $src1,@-$src2" |
| 2132 | (+ OP1_2 OP2_7 src1 src2) |
| 2133 | ; This is the original way. It doesn't work for parallel execution |
| 2134 | ; because of the earlyclobber of src2. |
| 2135 | ;(sequence () |
| 2136 | ; (set src2 (sub src2 (const 4))) |
| 2137 | ; (set (mem WI src2) src1)) |
| 2138 | (sequence ((WI new-src2)) |
| 2139 | (set new-src2 (sub src2 (const 4))) |
| 2140 | (set (mem WI new-src2) src1) |
| 2141 | (set src2 new-src2)) |
| 2142 | ((m32r/d (unit u-store) |
| 2143 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2144 | (m32rx (unit u-store) |
| 2145 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2146 | (m32r2 (unit u-store) |
| 2147 | (unit u-exec (in dr src2) (out dr src2) (cycles 0))) |
| 2148 | ) |
| 2149 | ) |
| 2150 | |
| 2151 | (dnmi push "push" ((PIPE O) (IDOC MEM)) |
| 2152 | "push $src1" |
| 2153 | (emit st-minus src1 (src2 15)) ; "st %0,@-sp" |
| 2154 | ) |
| 2155 | |
| 2156 | (dni sub "sub" |
| 2157 | ((PIPE OS) (IDOC ALU)) |
| 2158 | "sub $dr,$sr" |
| 2159 | (+ OP1_0 OP2_2 dr sr) |
| 2160 | (set dr (sub dr sr)) |
| 2161 | () |
| 2162 | ) |
| 2163 | |
| 2164 | (dni subv "sub:rv" |
| 2165 | ((PIPE OS) (IDOC ALU)) |
| 2166 | "subv $dr,$sr" |
| 2167 | (+ OP1_0 OP2_0 dr sr) |
| 2168 | (parallel () |
| 2169 | (set dr (sub dr sr)) |
| 2170 | (set condbit (sub-oflag dr sr (const 0)))) |
| 2171 | () |
| 2172 | ) |
| 2173 | |
| 2174 | (dni subx "sub:rx" |
| 2175 | ((PIPE OS) (IDOC ALU)) |
| 2176 | "subx $dr,$sr" |
| 2177 | (+ OP1_0 OP2_1 dr sr) |
| 2178 | (parallel () |
| 2179 | (set dr (subc dr sr condbit)) |
| 2180 | (set condbit (sub-cflag dr sr condbit))) |
| 2181 | () |
| 2182 | ) |
| 2183 | |
| 2184 | (dni trap "trap" |
| 2185 | (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC)) |
| 2186 | "trap $uimm4" |
| 2187 | (+ OP1_1 OP2_15 (f-r1 0) uimm4) |
| 2188 | (sequence () |
| 2189 | ; bbpc = bpc |
| 2190 | (set (reg h-cr 14) (reg h-cr 6)) |
| 2191 | ; Set bpc to the return address. Actually it's not quite the |
| 2192 | ; return address as RTE rounds the address down to a word |
| 2193 | ; boundary. |
| 2194 | (set (reg h-cr 6) (add pc (const 4))) |
| 2195 | ; bbpsw = bpsw |
| 2196 | (set (reg h-bbpsw) (reg h-bpsw)) |
| 2197 | ; bpsw = psw |
| 2198 | (set (reg h-bpsw) (reg h-psw)) |
| 2199 | ; sm is unchanged, ie,c are set to zero. |
| 2200 | (set (reg h-psw) (and (reg h-psw) (const #x80))) |
| 2201 | ; m32r_trap handles operating vs user mode |
| 2202 | (set WI pc (c-call WI "m32r_trap" pc uimm4)) |
| 2203 | ) |
| 2204 | () |
| 2205 | ) |
| 2206 | |
| 2207 | (dni unlock "unlock" |
| 2208 | ((PIPE O) (IDOC MISC)) |
| 2209 | "unlock $src1,@$src2" |
| 2210 | (+ OP1_2 OP2_5 src1 src2) |
| 2211 | (sequence () |
| 2212 | (if (reg h-lock) |
| 2213 | (set (mem WI src2) src1)) |
| 2214 | (set (reg h-lock) (const BI 0))) |
| 2215 | ((m32r/d (unit u-load)) |
| 2216 | (m32rx (unit u-load)) |
| 2217 | (m32r2 (unit u-load))) |
| 2218 | ) |
| 2219 | |
| 2220 | ; Saturate into byte. |
| 2221 | (dni satb "satb" |
| 2222 | ((MACH m32rx,m32r2) (IDOC ALU)) |
| 2223 | "satb $dr,$sr" |
| 2224 | (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300)) |
| 2225 | (set dr |
| 2226 | ; FIXME: min/max would simplify this nicely of course. |
| 2227 | (cond WI |
| 2228 | ((ge sr (const 127)) (const 127)) |
| 2229 | ((le sr (const -128)) (const -128)) |
| 2230 | (else sr))) |
| 2231 | () |
| 2232 | ) |
| 2233 | |
| 2234 | ; Saturate into half word. |
| 2235 | (dni sath "sath" |
| 2236 | ((MACH m32rx,m32r2) (IDOC ALU)) |
| 2237 | "sath $dr,$sr" |
| 2238 | (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200)) |
| 2239 | (set dr |
| 2240 | (cond WI |
| 2241 | ((ge sr (const 32767)) (const 32767)) |
| 2242 | ((le sr (const -32768)) (const -32768)) |
| 2243 | (else sr))) |
| 2244 | () |
| 2245 | ) |
| 2246 | |
| 2247 | ; Saturate word. |
| 2248 | (dni sat "sat" |
| 2249 | ((MACH m32rx,m32r2) SPECIAL (IDOC ALU)) |
| 2250 | "sat $dr,$sr" |
| 2251 | (+ OP1_8 dr OP2_6 sr (f-uimm16 0)) |
| 2252 | (set dr |
| 2253 | (if WI condbit |
| 2254 | (if WI (lt sr (const 0)) |
| 2255 | (const #x7fffffff) |
| 2256 | (const #x80000000)) |
| 2257 | sr)) |
| 2258 | () |
| 2259 | ) |
| 2260 | |
| 2261 | ; Parallel compare byte zeros. |
| 2262 | ; Set C bit in condition register if any byte in source register is zero. |
| 2263 | (dni pcmpbz "pcmpbz" |
| 2264 | ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU)) |
| 2265 | "pcmpbz $src2" |
| 2266 | (+ OP1_0 (f-r1 3) OP2_7 src2) |
| 2267 | (set condbit |
| 2268 | (cond BI |
| 2269 | ((eq (and src2 (const #xff)) (const 0)) (const BI 1)) |
| 2270 | ((eq (and src2 (const #xff00)) (const 0)) (const BI 1)) |
| 2271 | ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1)) |
| 2272 | ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1)) |
| 2273 | (else (const BI 0)))) |
| 2274 | ((m32rx (unit u-cmp)) |
| 2275 | (m32r2 (unit u-cmp))) |
| 2276 | ) |
| 2277 | |
| 2278 | ; Add accumulators |
| 2279 | (dni sadd "sadd" |
| 2280 | ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) |
| 2281 | "sadd" |
| 2282 | (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4)) |
| 2283 | (set (reg h-accums 0) |
| 2284 | (add (sra (reg h-accums 1) (const 16)) |
| 2285 | (reg h-accums 0))) |
| 2286 | ((m32rx (unit u-mac)) |
| 2287 | (m32r2 (unit u-mac))) |
| 2288 | ) |
| 2289 | |
| 2290 | ; Multiply and add into accumulator 1 |
| 2291 | (dni macwu1 "macwu1" |
| 2292 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 2293 | "macwu1 $src1,$src2" |
| 2294 | (+ OP1_5 src1 OP2_11 src2) |
| 2295 | (set (reg h-accums 1) |
| 2296 | (sra DI |
| 2297 | (sll DI |
| 2298 | (add DI |
| 2299 | (reg h-accums 1) |
| 2300 | (mul DI |
| 2301 | (ext DI src1) |
| 2302 | (ext DI (and src2 (const #xffff))))) |
| 2303 | (const 8)) |
| 2304 | (const 8))) |
| 2305 | ((m32rx (unit u-mac)) |
| 2306 | (m32r2 (unit u-mac))) |
| 2307 | ) |
| 2308 | |
| 2309 | ; Multiply and subtract from accumulator 0 |
| 2310 | (dni msblo "msblo" |
| 2311 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 2312 | "msblo $src1,$src2" |
| 2313 | (+ OP1_5 src1 OP2_13 src2) |
| 2314 | (set accum |
| 2315 | (sra DI |
| 2316 | (sll DI |
| 2317 | (sub accum |
| 2318 | (sra DI |
| 2319 | (sll DI |
| 2320 | (mul DI |
| 2321 | (ext DI (trunc HI src1)) |
| 2322 | (ext DI (trunc HI src2))) |
| 2323 | (const 32)) |
| 2324 | (const 16))) |
| 2325 | (const 8)) |
| 2326 | (const 8))) |
| 2327 | ((m32rx (unit u-mac)) |
| 2328 | (m32r2 (unit u-mac))) |
| 2329 | ) |
| 2330 | |
| 2331 | ; Multiply into accumulator 1 |
| 2332 | (dni mulwu1 "mulwu1" |
| 2333 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 2334 | "mulwu1 $src1,$src2" |
| 2335 | (+ OP1_5 src1 OP2_10 src2) |
| 2336 | (set (reg h-accums 1) |
| 2337 | (sra DI |
| 2338 | (sll DI |
| 2339 | (mul DI |
| 2340 | (ext DI src1) |
| 2341 | (ext DI (and src2 (const #xffff)))) |
| 2342 | (const 16)) |
| 2343 | (const 16))) |
| 2344 | ((m32rx (unit u-mac)) |
| 2345 | (m32r2 (unit u-mac))) |
| 2346 | ) |
| 2347 | |
| 2348 | ; Multiply and add into accumulator 1 |
| 2349 | (dni maclh1 "maclh1" |
| 2350 | ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) |
| 2351 | "maclh1 $src1,$src2" |
| 2352 | (+ OP1_5 src1 OP2_12 src2) |
| 2353 | (set (reg h-accums 1) |
| 2354 | (sra DI |
| 2355 | (sll DI |
| 2356 | (add DI |
| 2357 | (reg h-accums 1) |
| 2358 | (sll DI |
| 2359 | (ext DI |
| 2360 | (mul SI |
| 2361 | (ext SI (trunc HI src1)) |
| 2362 | (sra SI src2 (const SI 16)))) |
| 2363 | (const 16))) |
| 2364 | (const 8)) |
| 2365 | (const 8))) |
| 2366 | ((m32rx (unit u-mac)) |
| 2367 | (m32r2 (unit u-mac))) |
| 2368 | ) |
| 2369 | |
| 2370 | ; skip instruction if C |
| 2371 | (dni sc "sc" |
| 2372 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
| 2373 | "sc" |
| 2374 | (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1)) |
| 2375 | (skip (zext INT condbit)) |
| 2376 | () |
| 2377 | ) |
| 2378 | |
| 2379 | ; skip instruction if not C |
| 2380 | (dni snc "snc" |
| 2381 | ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) |
| 2382 | "snc" |
| 2383 | (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1)) |
| 2384 | (skip (zext INT (not condbit))) |
| 2385 | () |
| 2386 | ) |
| 2387 | |
| 2388 | ; PSW &= ((~ uimm8) | 0xff00) |
| 2389 | (dni clrpsw "clrpsw" |
| 2390 | ((PIPE O) SPECIAL_M32R) |
| 2391 | "clrpsw $uimm8" |
| 2392 | (+ OP1_7 (f-r1 2) uimm8) |
| 2393 | (set USI (reg h-cr 0) |
| 2394 | (and USI (reg h-cr 0) |
| 2395 | (or USI (zext SI (inv QI uimm8)) (const #xff00)))) |
| 2396 | () |
| 2397 | ) |
| 2398 | |
| 2399 | ; PSW |= (unsigned char) uimm8 |
| 2400 | (dni setpsw "setpsw" |
| 2401 | ((PIPE O) SPECIAL_M32R) |
| 2402 | "setpsw $uimm8" |
| 2403 | (+ OP1_7 (f-r1 1) uimm8) |
| 2404 | (set USI (reg h-cr 0) uimm8) |
| 2405 | () |
| 2406 | ) |
| 2407 | |
| 2408 | ; bset |
| 2409 | (dni bset "bset" |
| 2410 | (SPECIAL_M32R) |
| 2411 | "bset $uimm3,@($slo16,$sr)" |
| 2412 | (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16) |
| 2413 | (set QI (mem QI (add sr slo16)) |
| 2414 | (or QI (mem QI (add sr slo16)) |
| 2415 | (sll QI (const 1) (sub (const 7) uimm3)))) |
| 2416 | () |
| 2417 | ) |
| 2418 | |
| 2419 | ; bclr |
| 2420 | (dni bclr "bclr" |
| 2421 | (SPECIAL_M32R) |
| 2422 | "bclr $uimm3,@($slo16,$sr)" |
| 2423 | (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16) |
| 2424 | (set QI (mem QI (add sr slo16)) |
| 2425 | (and QI (mem QI (add sr slo16)) |
| 2426 | (inv QI (sll QI (const 1) (sub (const 7) uimm3))))) |
| 2427 | () |
| 2428 | ) |
| 2429 | |
| 2430 | ; btst |
| 2431 | (dni btst "btst" |
| 2432 | (SPECIAL_M32R (PIPE O)) |
| 2433 | "btst $uimm3,$sr" |
| 2434 | (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr) |
| 2435 | (set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1))) |
| 2436 | () |
| 2437 | ) |