| 1 | ; OpenRISC family. -*- Scheme -*- |
| 2 | ; Copyright 2000, 2001, 2011 Free Software Foundation, Inc. |
| 3 | ; Contributed by Johan Rydberg, jrydberg@opencores.org |
| 4 | ; |
| 5 | ; This program is free software; you can redistribute it and/or modify |
| 6 | ; it under the terms of the GNU General Public License as published by |
| 7 | ; the Free Software Foundation; either version 2 of the License, or |
| 8 | ; (at your option) any later version. |
| 9 | ; |
| 10 | ; This program is distributed in the hope that it will be useful, |
| 11 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ; GNU General Public License for more details. |
| 14 | ; |
| 15 | ; You should have received a copy of the GNU General Public License |
| 16 | ; along with this program; if not, write to the Free Software |
| 17 | ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| 18 | |
| 19 | (include "simplify.inc") |
| 20 | |
| 21 | ; OpenRISC 1000 is an architecture of a family of open source, |
| 22 | ; synthesizeable RISC microprocessor cores. It is a 32-bit load |
| 23 | ; and store RISC architecture designed with emphasis on speed, |
| 24 | ; compact instruction set and scalability. OpenRISC 1000 targets |
| 25 | ; wide range of embedded environments. |
| 26 | |
| 27 | (define-arch |
| 28 | (name openrisc) |
| 29 | (comment "OpenRISC 1000") |
| 30 | (insn-lsb0? #t) |
| 31 | (machs openrisc or1300) |
| 32 | (isas or32) |
| 33 | ) |
| 34 | |
| 35 | \f |
| 36 | ; Attributes |
| 37 | |
| 38 | ; An attribute to describe if a model has insn and/or data caches. |
| 39 | (define-attr |
| 40 | (for model) |
| 41 | (type enum) |
| 42 | (name HAS-CACHE) |
| 43 | (comment "if this model has caches") |
| 44 | (values DATA-CACHE INSN-CACHE) |
| 45 | ) |
| 46 | |
| 47 | ; An attribute to describe if an insn can be in the delay slot or not. |
| 48 | (define-attr |
| 49 | (for insn) |
| 50 | (type boolean) |
| 51 | (name NOT-IN-DELAY-SLOT) |
| 52 | (comment "insn can't go in delay slot") |
| 53 | ) |
| 54 | |
| 55 | ; IDOC attribute for instruction documentation. |
| 56 | |
| 57 | (define-attr |
| 58 | (for insn) |
| 59 | (type enum) |
| 60 | (name IDOC) |
| 61 | (comment "insn kind for documentation") |
| 62 | (attrs META) |
| 63 | (values |
| 64 | (MEM - () "Memory") |
| 65 | (ALU - () "ALU") |
| 66 | (FPU - () "FPU") |
| 67 | (BR - () "Branch") |
| 68 | (PRIV - () "Priviledged") |
| 69 | (MISC - () "Miscellaneous") |
| 70 | ) |
| 71 | ) |
| 72 | |
| 73 | ; Enum for exception vectors. |
| 74 | (define-enum |
| 75 | (name e-exception) |
| 76 | (comment "exception vectors") |
| 77 | (attrs) |
| 78 | (prefix E_) |
| 79 | (values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -) |
| 80 | ("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -) |
| 81 | ("SYSCALL" -) ("BREAK" -) ("RESERVED" -))) |
| 82 | ) |
| 83 | |
| 84 | \f |
| 85 | ; Instruction set parameters. |
| 86 | |
| 87 | (define-isa |
| 88 | ; Name of the ISA. |
| 89 | (name or32) |
| 90 | |
| 91 | ; Base insturction length. The insns is always 32 bits wide. |
| 92 | (base-insn-bitsize 32) |
| 93 | |
| 94 | ; Address of insn in delay slot |
| 95 | (setup-semantics (set-quiet (reg h-delay-insn) (add pc 4))) |
| 96 | ) |
| 97 | |
| 98 | \f |
| 99 | ; CPU family definitions. |
| 100 | |
| 101 | (define-cpu |
| 102 | ; CPU names must be distinct from the architecture name and machine names. |
| 103 | ; The "b" suffix stands for "base" and is the convention. |
| 104 | ; The "f" suffix stands for "family" and is the convention. |
| 105 | (name openriscbf) |
| 106 | (comment "OpenRISC base family") |
| 107 | (endian big) |
| 108 | (word-bitsize 32) |
| 109 | ) |
| 110 | |
| 111 | ; Generic machine |
| 112 | (define-mach |
| 113 | (name openrisc) |
| 114 | (comment "Generic OpenRISC cpu") |
| 115 | (cpu openriscbf) |
| 116 | (bfd-name "openrisc") |
| 117 | ) |
| 118 | |
| 119 | ; OpenRISC 1300 machine |
| 120 | (define-mach |
| 121 | (name or1300) |
| 122 | (comment "OpenRISC 1300") |
| 123 | (cpu openriscbf) |
| 124 | (bfd-name "openrisc:1300") |
| 125 | ) |
| 126 | |
| 127 | \f |
| 128 | ; Model descriptions |
| 129 | |
| 130 | ; Generic OpenRISC model |
| 131 | (define-model |
| 132 | (name openrisc-1) (comment "OpenRISC generic model") (attrs) |
| 133 | (mach openrisc) |
| 134 | |
| 135 | ; Nothing special about this. |
| 136 | (unit u-exec "Execution Unit" () 1 1 () () () ()) |
| 137 | ) |
| 138 | |
| 139 | ; OpenRISC 1320 |
| 140 | (define-model |
| 141 | (name or1320-1) (comment "OpenRISC 1320 model") |
| 142 | |
| 143 | ; This model has both instruction and data cache |
| 144 | (attrs (HAS-CACHE INSN-CACHE,DATA-CACHE)) |
| 145 | (mach or1300) |
| 146 | |
| 147 | ; Nothing special about this. |
| 148 | (unit u-exec "Execution Unit" () 1 1 () () () ()) |
| 149 | ) |
| 150 | |
| 151 | \f |
| 152 | ; Instruction fields. |
| 153 | |
| 154 | ; Attributes: |
| 155 | ; . PCREL-ADDR pc relative value (for reloc and disassembly purposes) |
| 156 | ; . ABS-ADDR absolute address (for reloc and disassembly purposes?) |
| 157 | ; . RESERVED bits are not used to decode insn, must be all 0 |
| 158 | |
| 159 | ; Instruction classes. |
| 160 | (dnf f-class "insn class" () 31 2) |
| 161 | (dnf f-sub "sub class" () 29 4) |
| 162 | |
| 163 | ; Register fields. |
| 164 | (dnf f-r1 "r1" () 25 5) |
| 165 | (dnf f-r2 "r2" () 20 5) |
| 166 | (dnf f-r3 "r3" () 15 5) |
| 167 | |
| 168 | ; Immediates. |
| 169 | (df f-simm16 "signed imm (16)" () 15 16 INT #f #f) |
| 170 | (dnf f-uimm16 "unsigned imm (16)" () 15 16) |
| 171 | (dnf f-uimm5 "unsigned imm (5)" () 4 5) |
| 172 | (df f-hi16 "high 16" () 15 16 INT #f #f) |
| 173 | (df f-lo16 "low 16" () 15 16 INT #f #f) |
| 174 | |
| 175 | ; Sub fields |
| 176 | (dnf f-op1 "op1" () 31 2) |
| 177 | (dnf f-op2 "op2" () 29 4) |
| 178 | (dnf f-op3 "op3" () 25 2) |
| 179 | (dnf f-op4 "op4" () 23 3) |
| 180 | (dnf f-op5 "op3" () 25 5) |
| 181 | (dnf f-op6 "op4" () 7 3) |
| 182 | (dnf f-op7 "op5" () 3 4) |
| 183 | |
| 184 | (dnf f-i16-1 "uimm16-1" () 10 11) |
| 185 | (dnf f-i16-2 "uimm16-2" () 25 5) |
| 186 | |
| 187 | ; PC relative, 26-bit (2 shifted to right) |
| 188 | (df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT |
| 189 | ((value pc) (sra WI (sub WI value pc) (const 2))) |
| 190 | ((value pc) (add WI (sll WI value (const 2)) pc))) |
| 191 | |
| 192 | ; absolute, 26-bit (2 shifted to right) |
| 193 | (df f-abs26 "abs26" (ABS-ADDR) 25 26 INT |
| 194 | ((value pc) (sra WI pc (const 2))) |
| 195 | ((value pc) (sll WI value (const 2)))) |
| 196 | |
| 197 | (define-multi-ifield |
| 198 | (name f-i16nc) |
| 199 | (comment "16 bit signed") |
| 200 | (attrs SIGN-OPT) |
| 201 | (mode HI) |
| 202 | (subfields f-i16-1 f-i16-2) |
| 203 | (insert (sequence () |
| 204 | (set (ifield f-i16-2) (and (sra (ifield f-i16nc) |
| 205 | (const 11)) |
| 206 | (const #x1f))) |
| 207 | (set (ifield f-i16-1) (and (ifield f-i16nc) |
| 208 | (const #x7ff))))) |
| 209 | (extract (sequence () |
| 210 | (set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit" |
| 211 | (or (sll (ifield f-i16-2) |
| 212 | (const 11)) |
| 213 | (ifield f-i16-1)))))) |
| 214 | ) |
| 215 | |
| 216 | \f |
| 217 | ; Enums. |
| 218 | |
| 219 | ; insn-class: bits 31-30 |
| 220 | (define-normal-insn-enum insn-class "FIXME" () OP1_ f-class |
| 221 | (.map .str (.iota 4)) |
| 222 | ) |
| 223 | |
| 224 | (define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub |
| 225 | (.map .str (.iota 16)) |
| 226 | ) |
| 227 | |
| 228 | (define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3 |
| 229 | (.map .str (.iota 4)) |
| 230 | ) |
| 231 | |
| 232 | (define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4 |
| 233 | (.map .str (.iota 8)) |
| 234 | ) |
| 235 | |
| 236 | (define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5 |
| 237 | (.map .str (.iota 32)) |
| 238 | ) |
| 239 | |
| 240 | (define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6 |
| 241 | (.map .str (.iota 8)) |
| 242 | ) |
| 243 | |
| 244 | (define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7 |
| 245 | (.map .str (.iota 16)) |
| 246 | ) |
| 247 | |
| 248 | |
| 249 | \f |
| 250 | ; Hardware pieces. |
| 251 | ; These entries list the elements of the raw hardware. |
| 252 | ; They're also used to provide tables and other elements of the assembly |
| 253 | ; language. |
| 254 | |
| 255 | (dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) |
| 256 | |
| 257 | (define-hardware |
| 258 | (name h-gr) (comment "general registers") (attrs PROFILE) |
| 259 | (type register WI (32)) |
| 260 | (indices keyword "" |
| 261 | ((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) |
| 262 | (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) |
| 263 | (r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) |
| 264 | (r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26) |
| 265 | (r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11) |
| 266 | (sp 1) (fp 2))) |
| 267 | ) |
| 268 | |
| 269 | (define-hardware |
| 270 | (name h-sr) (comment "special registers") |
| 271 | (type register WI (#x20000)) |
| 272 | (get (index) (c-call SI "@arch@_h_sr_get_handler" index)) |
| 273 | (set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval)) |
| 274 | ) |
| 275 | |
| 276 | (dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ()) |
| 277 | (dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ()) |
| 278 | |
| 279 | (dsh h-cbit "condition bit" () (register BI)) |
| 280 | (dsh h-delay-insn "delay insn addr" () (register SI)) |
| 281 | |
| 282 | \f |
| 283 | ; Instruction operands. |
| 284 | |
| 285 | (dnop sr "special register" (SEM-ONLY) h-sr f-nil) |
| 286 | (dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil) |
| 287 | (dnop simm-16 "16 bit signed immediate" () h-sint f-simm16) |
| 288 | (dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16) |
| 289 | (dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26) |
| 290 | (dnop abs-26 "abs 26 bit" () h-iaddr f-abs26) |
| 291 | (dnop uimm-5 "imm5" () h-uint f-uimm5) |
| 292 | |
| 293 | (dnop rD "destination register" () h-gr f-r1) |
| 294 | (dnop rA "source register A" () h-gr f-r2) |
| 295 | (dnop rB "source register B" () h-gr f-r3) |
| 296 | |
| 297 | (dnop op-f-23 "f-op23" () h-uint f-op4) |
| 298 | (dnop op-f-3 "f-op3" () h-uint f-op5) |
| 299 | |
| 300 | ; For hi(foo). |
| 301 | (define-operand |
| 302 | (name hi16) (comment "high 16 bit immediate, sign optional") |
| 303 | (attrs SIGN-OPT) |
| 304 | (type h-hi16) |
| 305 | (index f-simm16) |
| 306 | (handlers (parse "hi16")) |
| 307 | ) |
| 308 | |
| 309 | ; For lo(foo) |
| 310 | (define-operand |
| 311 | (name lo16) (comment "low 16 bit immediate, sign optional") |
| 312 | (attrs SIGN-OPT) |
| 313 | (type h-lo16) |
| 314 | (index f-lo16) |
| 315 | (handlers (parse "lo16")) |
| 316 | ) |
| 317 | |
| 318 | (define-operand |
| 319 | (name ui16nc) |
| 320 | (comment "16 bit immediate, sign optional") |
| 321 | (attrs) |
| 322 | (type h-lo16) |
| 323 | (index f-i16nc) |
| 324 | (handlers (parse "lo16")) |
| 325 | ) |
| 326 | |
| 327 | \f |
| 328 | ; Instructions. |
| 329 | |
| 330 | ; Branch releated instructions |
| 331 | |
| 332 | (dni l-j "jump (absolute iaddr)" |
| 333 | ; This function may not be in delay slot |
| 334 | (NOT-IN-DELAY-SLOT) |
| 335 | |
| 336 | "l.j ${abs-26}" |
| 337 | (+ OP1_0 OP2_0 abs-26) |
| 338 | |
| 339 | ; We execute the delay slot before doin' the real branch |
| 340 | (delay 1 (set pc abs-26)) |
| 341 | () |
| 342 | ) |
| 343 | |
| 344 | (dni l-jal "jump and link (absolute iaddr)" |
| 345 | ; This function may not be in delay slot |
| 346 | (NOT-IN-DELAY-SLOT) |
| 347 | |
| 348 | "l.jal ${abs-26}" |
| 349 | (+ OP1_0 OP2_1 abs-26) |
| 350 | |
| 351 | ; We execute the delay slot before doin' the real branch |
| 352 | ; Set LR to (delay insn addr + 4) |
| 353 | (sequence () |
| 354 | (set (reg h-gr 11) (add (reg h-delay-insn) 4)) |
| 355 | (delay 1 (set pc abs-26))) |
| 356 | () |
| 357 | ) |
| 358 | |
| 359 | (dni l-jr "jump register (absolute iaddr)" |
| 360 | ; This function may not be in delay slot |
| 361 | (NOT-IN-DELAY-SLOT) |
| 362 | |
| 363 | "l.jr $rA" |
| 364 | (+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16) |
| 365 | |
| 366 | ; We execute the delay slot before doin' the real branch |
| 367 | (delay 1 (set pc rA)) |
| 368 | () |
| 369 | ) |
| 370 | |
| 371 | (dni l-jalr "jump register and link (absolute iaddr)" |
| 372 | ; This function may not be in delay slot |
| 373 | (NOT-IN-DELAY-SLOT) |
| 374 | |
| 375 | "l.jalr $rA" |
| 376 | (+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16) |
| 377 | |
| 378 | ; We save the value of rA in a temporary slot before setting |
| 379 | ; the link register. This because "l.jalr r11" would cause |
| 380 | ; a forever-and-ever loop otherwise. |
| 381 | ; |
| 382 | ; We execute the delay slot before doin' the real branch |
| 383 | (sequence ((WI tmp-slot)) |
| 384 | (set tmp-slot rA) |
| 385 | (set (reg h-gr 11) (add (reg h-delay-insn) 4)) |
| 386 | (delay 1 (set pc tmp-slot))) |
| 387 | () |
| 388 | ) |
| 389 | |
| 390 | (dni l-bal "branch and link (pc relative iaddr)" |
| 391 | ; This function may not be in delay slot |
| 392 | (NOT-IN-DELAY-SLOT) |
| 393 | |
| 394 | "l.bal ${disp-26}" |
| 395 | (+ OP1_0 OP2_2 disp-26) |
| 396 | |
| 397 | ; We execute the delay slot before doin' the real branch |
| 398 | ; Set LR to (delay insn addr + 4) |
| 399 | (sequence () |
| 400 | (set (reg h-gr 11) (add (reg h-delay-insn) 4)) |
| 401 | (delay 1 (set pc disp-26))) |
| 402 | () |
| 403 | ) |
| 404 | |
| 405 | (dni l-bnf "branch if condition bit not set (pc relative iaddr)" |
| 406 | ; This function may not be in delay slot |
| 407 | (NOT-IN-DELAY-SLOT) |
| 408 | |
| 409 | "l.bnf ${disp-26}" |
| 410 | (+ OP1_0 OP2_3 disp-26) |
| 411 | |
| 412 | ; We execute the delay slot before doin' the real branch |
| 413 | (if (eq cbit 0) |
| 414 | (sequence () |
| 415 | (delay 1 (set pc disp-26)))) |
| 416 | () |
| 417 | ) |
| 418 | |
| 419 | (dni l-bf "branch if condition bit is set (pc relative iaddr)" |
| 420 | ; This function may not be in delay slot |
| 421 | (NOT-IN-DELAY-SLOT) |
| 422 | |
| 423 | "l.bf ${disp-26}" |
| 424 | (+ OP1_0 OP2_4 disp-26) |
| 425 | |
| 426 | ; We execute the delay slot before doin' the real branch |
| 427 | (if (eq cbit 1) |
| 428 | (sequence () |
| 429 | (delay 1 (set pc disp-26)))) |
| 430 | () |
| 431 | ) |
| 432 | |
| 433 | (dni l-brk "break (exception)" |
| 434 | ; This function may not be in delay slot |
| 435 | (NOT-IN-DELAY-SLOT) |
| 436 | |
| 437 | "l.brk ${uimm-16}" |
| 438 | (+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16) |
| 439 | |
| 440 | ; FIXME should we do it like this ?? |
| 441 | (c-call VOID "@cpu@_cpu_brk" uimm-16) |
| 442 | () |
| 443 | ) |
| 444 | |
| 445 | (dni l-rfe "return from exception" |
| 446 | ; This function may not be in delay slot |
| 447 | (NOT-IN-DELAY-SLOT) |
| 448 | |
| 449 | "l.rfe $rA" |
| 450 | (+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16) |
| 451 | (sequence () |
| 452 | (delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA)))) |
| 453 | () |
| 454 | ) |
| 455 | |
| 456 | (dni l-sys "syscall (exception)" |
| 457 | ; This function may not be in delay slot |
| 458 | (NOT-IN-DELAY-SLOT) |
| 459 | |
| 460 | "l.sys ${uimm-16}" |
| 461 | (+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16) |
| 462 | (sequence() |
| 463 | (delay 1 (set pc (c-call SI "@cpu@_except" pc |
| 464 | #xc00 uimm-16)))) |
| 465 | () |
| 466 | ) |
| 467 | |
| 468 | \f |
| 469 | ; Misc instructions |
| 470 | |
| 471 | (dni l-nop "nop" |
| 472 | () |
| 473 | "l.nop" |
| 474 | (+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16) |
| 475 | (nop) |
| 476 | () |
| 477 | ) |
| 478 | |
| 479 | (dnmi l-ret "ret" () |
| 480 | "l.ret" |
| 481 | (emit l-jr (rA 11) (uimm-16 0)) |
| 482 | ) |
| 483 | |
| 484 | (dni l-movhi "movhi" |
| 485 | (DELAY-SLOT) |
| 486 | "l.movhi $rD,$hi16" |
| 487 | (+ OP1_0 OP2_6 hi16 rD rA) |
| 488 | (set rD (sll WI hi16 (const 16))) |
| 489 | () |
| 490 | ) |
| 491 | |
| 492 | \f |
| 493 | ; System releated instructions |
| 494 | |
| 495 | (dni l-mfsr "mfsr" |
| 496 | (DELAY-SLOT) |
| 497 | "l.mfsr $rD,$rA" |
| 498 | (+ OP1_0 OP2_7 rD rA uimm-16) |
| 499 | (set rD (c-call SI "@cpu@_cpu_mfsr" rA)) |
| 500 | () |
| 501 | ) |
| 502 | |
| 503 | (dni l-mtsr "mtsr" |
| 504 | (DELAY-SLOT) |
| 505 | "l.mtsr $rA,$rB" |
| 506 | (+ OP1_1 OP2_0 rA rB rD (f-i16-1 0)) |
| 507 | (c-call VOID "@cpu@_cpu_mtsr" rA rB) |
| 508 | () |
| 509 | ) |
| 510 | |
| 511 | |
| 512 | \f |
| 513 | ; Load instructions |
| 514 | |
| 515 | (dni l-lw "load word" |
| 516 | (DELAY-SLOT) |
| 517 | "l.lw $rD,${simm-16}($rA)" |
| 518 | (+ OP1_2 OP2_0 rD rA simm-16) |
| 519 | (set rD (mem SI (add rA simm-16))) |
| 520 | () |
| 521 | ) |
| 522 | |
| 523 | (dni l-lbz "load byte (zero extend)" |
| 524 | (DELAY-SLOT) |
| 525 | "l.lbz $rD,${simm-16}($rA)" |
| 526 | (+ OP1_2 OP2_1 rD rA simm-16) |
| 527 | (set rD (zext SI (mem QI (add rA simm-16)))) |
| 528 | () |
| 529 | ) |
| 530 | |
| 531 | (dni l-lbs "load byte (sign extend)" |
| 532 | (DELAY-SLOT) |
| 533 | "l.lbs $rD,${simm-16}($rA)" |
| 534 | (+ OP1_2 OP2_2 rD rA simm-16) |
| 535 | (set rD (ext SI (mem QI (add rA simm-16)))) |
| 536 | () |
| 537 | ) |
| 538 | |
| 539 | (dni l-lhz "load halfword (zero extend)" |
| 540 | (DELAY-SLOT) |
| 541 | "l.lhz $rD,${simm-16}($rA)" |
| 542 | (+ OP1_2 OP2_3 rD simm-16 rA) |
| 543 | (set rD (zext SI (mem HI (add rA simm-16)))) |
| 544 | () |
| 545 | ) |
| 546 | |
| 547 | (dni l-lhs "load halfword (sign extend)" |
| 548 | (DELAY-SLOT) |
| 549 | "l.lhs $rD,${simm-16}($rA)" |
| 550 | (+ OP1_2 OP2_4 rD rA simm-16) |
| 551 | (set rD (ext SI (mem HI (add rA simm-16)))) |
| 552 | () |
| 553 | ) |
| 554 | |
| 555 | \f |
| 556 | ; Store instructions |
| 557 | ; |
| 558 | ; We have to use a multi field since the integer is splited over 2 fields |
| 559 | |
| 560 | (define-pmacro (store-insn mnemonic op2-op mode-op) |
| 561 | (begin |
| 562 | (dni (.sym l- mnemonic) |
| 563 | (.str "l." mnemonic " imm(reg)/reg") |
| 564 | (DELAY-SLOT) |
| 565 | (.str "l." mnemonic " ${ui16nc}($rA),$rB") |
| 566 | (+ OP1_3 op2-op rB rD ui16nc) |
| 567 | (set (mem mode-op (add rA ui16nc)) rB) |
| 568 | () |
| 569 | ) |
| 570 | ) |
| 571 | ) |
| 572 | |
| 573 | (store-insn sw OP2_5 SI) |
| 574 | (store-insn sb OP2_6 QI) |
| 575 | (store-insn sh OP2_7 HI) |
| 576 | |
| 577 | |
| 578 | \f |
| 579 | ; Shift and rotate instructions |
| 580 | |
| 581 | ; Reserved fields. |
| 582 | (dnf f-f-15-8 "nop" (RESERVED) 15 8) |
| 583 | (dnf f-f-10-3 "nop" (RESERVED) 10 3) |
| 584 | (dnf f-f-4-1 "nop" (RESERVED) 4 1) |
| 585 | (dnf f-f-7-3 "nop" (RESERVED) 7 3) |
| 586 | |
| 587 | (define-pmacro (shift-insn mnemonic op4-op) |
| 588 | (begin |
| 589 | (dni (.sym l- mnemonic) |
| 590 | (.str "l." mnemonic " reg/reg/reg") |
| 591 | () |
| 592 | (.str "l." mnemonic " $rD,$rA,$rB") |
| 593 | (+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8) |
| 594 | (set rD (mnemonic rA rB)) |
| 595 | () |
| 596 | ) |
| 597 | (dni (.sym l- mnemonic "i") |
| 598 | (.str "l." mnemonic " reg/reg/imm") |
| 599 | () |
| 600 | (.str "l." mnemonic "i $rD,$rA,${uimm-5}") |
| 601 | (+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5) |
| 602 | (set rD (mnemonic rA uimm-5)) |
| 603 | () |
| 604 | ) |
| 605 | ) |
| 606 | ) |
| 607 | |
| 608 | (shift-insn sll OP6_0) |
| 609 | (shift-insn srl OP6_1) |
| 610 | (shift-insn sra OP6_2) |
| 611 | (shift-insn ror OP6_4) |
| 612 | |
| 613 | \f |
| 614 | ; Arethmetic insns |
| 615 | |
| 616 | ; Reserved fields. |
| 617 | (dnf f-f-10-7 "nop" (RESERVED) 10 7) |
| 618 | |
| 619 | (define-pmacro (ar-insn-u mnemonic op2-op op5-op) |
| 620 | (begin |
| 621 | (dni (.sym l- mnemonic) |
| 622 | (.str "l." mnemonic " reg/reg/reg") |
| 623 | () |
| 624 | (.str "l." mnemonic " $rD,$rA,$rB") |
| 625 | (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) |
| 626 | (set rD (mnemonic rA rB)) |
| 627 | () |
| 628 | ) |
| 629 | (dni (.sym l- mnemonic "i") |
| 630 | (.str "l." mnemonic " reg/reg/lo16") |
| 631 | () |
| 632 | (.str "l." mnemonic "i $rD,$rA,$lo16") |
| 633 | (+ OP1_2 op2-op rD rA lo16) |
| 634 | (set rD (mnemonic rA (and lo16 #xffff))) |
| 635 | () |
| 636 | ) |
| 637 | ) |
| 638 | ) |
| 639 | |
| 640 | (define-pmacro (ar-insn-s mnemonic op2-op op5-op) |
| 641 | (begin |
| 642 | (dni (.sym l- mnemonic) |
| 643 | (.str "l." mnemonic " reg/reg/reg") |
| 644 | () |
| 645 | (.str "l." mnemonic " $rD,$rA,$rB") |
| 646 | (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) |
| 647 | (set rD (mnemonic rA rB)) |
| 648 | () |
| 649 | ) |
| 650 | (dni (.sym l- mnemonic "i") |
| 651 | (.str "l." mnemonic " reg/reg/lo16") |
| 652 | () |
| 653 | (.str "l." mnemonic "i $rD,$rA,$lo16") |
| 654 | (+ OP1_2 op2-op rD rA lo16) |
| 655 | (set rD (mnemonic rA lo16)) |
| 656 | () |
| 657 | ) |
| 658 | ) |
| 659 | ) |
| 660 | |
| 661 | (ar-insn-s add OP2_5 OP7_0) |
| 662 | ;;(ar-op-s addc OP2_5 OP7_0) |
| 663 | (ar-insn-s sub OP2_7 OP7_2) |
| 664 | (ar-insn-u and OP2_8 OP7_3) |
| 665 | (ar-insn-u or OP2_9 OP7_4) |
| 666 | (ar-insn-u xor OP2_10 OP7_5) |
| 667 | (ar-insn-u mul OP2_11 OP7_6) |
| 668 | ;;(ar-op-u mac OP2_12 OP7_7) |
| 669 | |
| 670 | |
| 671 | (dni l-div "divide (signed)" |
| 672 | (DELAY-SLOT) |
| 673 | "l.div $rD,$rA,$rB" |
| 674 | (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9) |
| 675 | (if VOID (eq rB (const 0)) |
| 676 | (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) |
| 677 | (set rD (div rA rB))) |
| 678 | () |
| 679 | ) |
| 680 | |
| 681 | (dni l-divu "divide (unsigned)" |
| 682 | (DELAY-SLOT) |
| 683 | "l.divu $rD,$rA,$rB" |
| 684 | (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10) |
| 685 | (if VOID (eq rB (const 0)) |
| 686 | (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) |
| 687 | (set rD (udiv rA rB))) |
| 688 | () |
| 689 | ) |
| 690 | |
| 691 | \f |
| 692 | ; Compare instructions |
| 693 | |
| 694 | ; Reserved fields. |
| 695 | (dnf f-f-10-11 "nop" (RESERVED) 10 11) |
| 696 | |
| 697 | ; Register compare (both signed and unsigned) |
| 698 | (define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op) |
| 699 | (begin |
| 700 | (dni (.sym l- "sf" (.sym sem-op "s")) |
| 701 | (.str "l." mnemonic " reg/reg") |
| 702 | (DELAY-SLOT) |
| 703 | (.str "l.sf" (.str sem-op) "s $rA,$rB") |
| 704 | (+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0)) |
| 705 | (set cbit (sem-op rA rB)) |
| 706 | () |
| 707 | ) |
| 708 | (dni (.sym l- "sf" (.sym sem-op "u")) |
| 709 | (.str "l." mnemonic " reg/reg") |
| 710 | (DELAY-SLOT) |
| 711 | (.str "l.sf" (.str sem-op) "u $rA,$rB") |
| 712 | (+ op1-op op2-op op3-op rA rB (f-f-10-11 0)) |
| 713 | (set cbit (sem-op rA rB)) |
| 714 | () |
| 715 | ) |
| 716 | ) |
| 717 | ) |
| 718 | |
| 719 | ; Immediate compare (both signed and unsigned) |
| 720 | (define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op) |
| 721 | (begin |
| 722 | (dni (.sym l- "sf" (.sym sem-op "si")) |
| 723 | (.str "l." mnemonic "si reg/imm") |
| 724 | (DELAY-SLOT) |
| 725 | (.str "l.sf" (.str sem-op) "si $rA,${simm-16}") |
| 726 | (+ op1-op op2-op op3-op-2 rA simm-16) |
| 727 | (set cbit (sem-op rA simm-16)) |
| 728 | () |
| 729 | ) |
| 730 | (dni (.sym l- "sf" (.sym sem-op "ui")) |
| 731 | (.str "l." mnemonic "ui reg/imm") |
| 732 | (DELAY-SLOT) |
| 733 | (.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}") |
| 734 | (+ op1-op op2-op op3-op rA uimm-16) |
| 735 | (set cbit (sem-op rA uimm-16)) |
| 736 | () |
| 737 | ) |
| 738 | ) |
| 739 | ) |
| 740 | |
| 741 | (define-pmacro (sf-insn op5-op sem-op) |
| 742 | (begin |
| 743 | (dni (.sym l- "sf" sem-op) |
| 744 | (.str "l." mnemonic " reg/reg") |
| 745 | (DELAY-SLOT) |
| 746 | (.str "l.sf" (.str sem-op) " $rA,$rB") |
| 747 | (+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0)) |
| 748 | (set cbit (sem-op rA rB)) |
| 749 | () |
| 750 | ) |
| 751 | (dni (.sym l- "sf" (.sym sem-op "i")) |
| 752 | (.str "l." mnemonic "i reg/imm") |
| 753 | (DELAY-SLOT) |
| 754 | (.str "l.sf" (.str sem-op) "i $rA,${simm-16}") |
| 755 | (+ OP1_2 OP2_14 op5-op rA simm-16) |
| 756 | (set cbit (sem-op rA simm-16)) |
| 757 | () |
| 758 | ) |
| 759 | ) |
| 760 | ) |
| 761 | |
| 762 | |
| 763 | (sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt) |
| 764 | (sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge) |
| 765 | (sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt) |
| 766 | (sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le) |
| 767 | |
| 768 | (sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt) |
| 769 | (sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge) |
| 770 | (sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt) |
| 771 | (sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le) |
| 772 | |
| 773 | (sf-insn OP5_0 eq) |
| 774 | (sf-insn OP5_1 ne) |