| 1 | ; OpenRISC Basic Instruction Set 32-bit (ORBIS) -*- Scheme -*- |
| 2 | ; Copyright 2000-2014 Free Software Foundation, Inc. |
| 3 | ; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org |
| 4 | ; Modified by Julius Baxter, juliusbaxter@gmail.com |
| 5 | ; Modified by Peter Gavin, pgavin@gmail.com |
| 6 | ; |
| 7 | ; This program is free software; you can redistribute it and/or modify |
| 8 | ; it under the terms of the GNU General Public License as published by |
| 9 | ; the Free Software Foundation; either version 3 of the License, or |
| 10 | ; (at your option) any later version. |
| 11 | ; |
| 12 | ; This program is distributed in the hope that it will be useful, |
| 13 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ; GNU General Public License for more details. |
| 16 | ; |
| 17 | ; You should have received a copy of the GNU General Public License |
| 18 | ; along with this program; if not, see <http://www.gnu.org/licenses/> |
| 19 | |
| 20 | ; Instruction fields. |
| 21 | |
| 22 | ; Hardware for immediate operands |
| 23 | (dnh h-simm16 "16-bit signed immediate" ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ()) |
| 24 | (dnh h-uimm16 "16-bit unsigned immediate" () (immediate (UINT 16)) () () ()) |
| 25 | (dnh h-uimm6 "6-bit unsigned immediate" () (immediate (UINT 6)) () () ()) |
| 26 | |
| 27 | ; Hardware for the (internal) atomic registers |
| 28 | (dsh h-atomic-reserve "atomic reserve flag" () (register BI)) |
| 29 | (dsh h-atomic-address "atomic reserve address" () (register SI)) |
| 30 | |
| 31 | ; Instruction classes. |
| 32 | (dnf f-opcode "insn opcode" ((MACH ORBIS-MACHS)) 31 6) |
| 33 | |
| 34 | ; Register fields. |
| 35 | (dnf f-r1 "r1" ((MACH ORBIS-MACHS)) 25 5) |
| 36 | (dnf f-r2 "r2" ((MACH ORBIS-MACHS)) 20 5) |
| 37 | (dnf f-r3 "r3" ((MACH ORBIS-MACHS)) 15 5) |
| 38 | |
| 39 | ; Sub fields |
| 40 | (dnf f-op-25-2 "op-25-2" ((MACH ORBIS-MACHS)) 25 2) ;; nop |
| 41 | (dnf f-op-25-5 "op-25-5" ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf* |
| 42 | (dnf f-op-16-1 "op-16-1" ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc |
| 43 | (dnf f-op-7-4 "op-7-4" ((MACH ORBIS-MACHS)) 7 4) |
| 44 | (dnf f-op-3-4 "op-3-4" ((MACH ORBIS-MACHS)) 3 4) |
| 45 | (dnf f-op-9-2 "op-9-2" ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode |
| 46 | (dnf f-op-9-4 "op-9-4" ((MACH ORBIS-MACHS)) 9 4) ;; |
| 47 | (dnf f-op-7-8 "op-7-8" ((MACH ORBIS-MACHS)) 7 8) |
| 48 | (dnf f-op-7-2 "op-7-2" ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti |
| 49 | |
| 50 | ; Reserved fields |
| 51 | (dnf f-resv-25-26 "resv-25-26" ((MACH ORBIS-MACHS) RESERVED) 25 26) |
| 52 | (dnf f-resv-25-10 "resv-25-10" ((MACH ORBIS-MACHS) RESERVED) 25 10) |
| 53 | (dnf f-resv-25-5 "resv-25-5" ((MACH ORBIS-MACHS) RESERVED) 25 5) |
| 54 | (dnf f-resv-23-8 "resv-23-8" ((MACH ORBIS-MACHS) RESERVED) 23 8) |
| 55 | (dnf f-resv-20-21 "resv-20-21" ((MACH ORBIS-MACHS) RESERVED) 20 21) |
| 56 | (dnf f-resv-20-5 "resv-20-5" ((MACH ORBIS-MACHS) RESERVED) 20 5) |
| 57 | (dnf f-resv-20-4 "resv-20-4" ((MACH ORBIS-MACHS) RESERVED) 20 4) |
| 58 | (dnf f-resv-15-8 "resv-15-8" ((MACH ORBIS-MACHS) RESERVED) 15 8) |
| 59 | (dnf f-resv-15-6 "resv-15-6" ((MACH ORBIS-MACHS) RESERVED) 15 6) |
| 60 | (dnf f-resv-10-11 "resv-10-11" ((MACH ORBIS-MACHS) RESERVED) 10 11) |
| 61 | (dnf f-resv-10-7 "resv-10-7" ((MACH ORBIS-MACHS) RESERVED) 10 7) |
| 62 | (dnf f-resv-10-3 "resv-10-3" ((MACH ORBIS-MACHS) RESERVED) 10 3) |
| 63 | (dnf f-resv-10-1 "resv-10-1" ((MACH ORBIS-MACHS) RESERVED) 10 1) |
| 64 | (dnf f-resv-8-1 "resv-8-1" ((MACH ORBIS-MACHS) RESERVED) 8 1) |
| 65 | (dnf f-resv-7-4 "resv-7-4" ((MACH ORBIS-MACHS) RESERVED) 7 4) |
| 66 | (dnf f-resv-5-2 "resv-5-2" ((MACH ORBIS-MACHS) RESERVED) 5 2) |
| 67 | |
| 68 | (dnf f-imm16-25-5 "imm16-25-5" ((MACH ORBIS-MACHS)) 25 5) |
| 69 | (dnf f-imm16-10-11 "imm16-10-11" ((MACH ORBIS-MACHS)) 10 11) |
| 70 | |
| 71 | ; PC relative, 26-bit (2 shifted to right) |
| 72 | (df f-disp26 |
| 73 | "disp26" |
| 74 | ((MACH ORBIS-MACHS) PCREL-ADDR) |
| 75 | 25 |
| 76 | 26 |
| 77 | INT |
| 78 | ((value pc) (sra IAI (sub IAI value pc) (const 2))) |
| 79 | ((value pc) (add IAI (mul IAI value (const 4)) pc)) |
| 80 | ) |
| 81 | |
| 82 | ; PC relative, 21-bit, 13 shifted to right, aligned. |
| 83 | ; Note that the alignment means that we can't simplify relocations in the |
| 84 | ; same way as we do for pc-relative, so we use ABS-ADDR instead of PCREL-ADDR. |
| 85 | (df f-disp21 |
| 86 | "disp21" |
| 87 | ((MACH ORBIS-MACHS) ABS-ADDR) |
| 88 | 20 |
| 89 | 21 |
| 90 | INT |
| 91 | ((value pc) |
| 92 | (sub IAI (sra IAI value (const 13)) (sra IAI pc (const 13)))) |
| 93 | ((value pc) |
| 94 | (mul IAI (add IAI value (sra IAI pc (const 13))) (const 8192))) |
| 95 | ) |
| 96 | |
| 97 | ; Immediates. |
| 98 | (dnf f-uimm16 "uimm16" ((MACH ORBIS-MACHS)) 15 16) |
| 99 | (df f-simm16 "simm16" ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f) |
| 100 | (dnf f-uimm6 "uimm6" ((MACH ORBIS-MACHS)) 5 6) ;; shroti |
| 101 | |
| 102 | (define-multi-ifield |
| 103 | (name f-uimm16-split) |
| 104 | (comment "16-bit split unsigned immediate") |
| 105 | (attrs (MACH ORBIS-MACHS)) |
| 106 | (mode UINT) |
| 107 | (subfields f-imm16-25-5 f-imm16-10-11) |
| 108 | (insert (sequence () |
| 109 | (set (ifield f-imm16-25-5) |
| 110 | (and (srl (ifield f-uimm16-split) |
| 111 | (const 11)) |
| 112 | (const #x1f))) |
| 113 | (set (ifield f-imm16-10-11) |
| 114 | (and (ifield f-uimm16-split) |
| 115 | (const #x7ff))))) |
| 116 | (extract |
| 117 | (set (ifield f-uimm16-split) |
| 118 | (trunc UHI |
| 119 | (or (sll (ifield f-imm16-25-5) |
| 120 | (const 11)) |
| 121 | (ifield f-imm16-10-11))))) |
| 122 | ) |
| 123 | |
| 124 | (define-multi-ifield |
| 125 | (name f-simm16-split) |
| 126 | (comment "16-bit split signed immediate") |
| 127 | (attrs (MACH ORBIS-MACHS) SIGN-OPT) |
| 128 | (mode INT) |
| 129 | (subfields f-imm16-25-5 f-imm16-10-11) |
| 130 | (insert (sequence () |
| 131 | (set (ifield f-imm16-25-5) |
| 132 | (and (sra (ifield f-simm16-split) |
| 133 | (const 11)) |
| 134 | (const #x1f))) |
| 135 | (set (ifield f-imm16-10-11) |
| 136 | (and (ifield f-simm16-split) |
| 137 | (const #x7ff))))) |
| 138 | (extract |
| 139 | (set (ifield f-simm16-split) |
| 140 | (trunc HI |
| 141 | (or (sll (ifield f-imm16-25-5) |
| 142 | (const 11)) |
| 143 | (ifield f-imm16-10-11))))) |
| 144 | ) |
| 145 | |
| 146 | ; Enums. |
| 147 | |
| 148 | ; insn-opcode: bits 31-26 |
| 149 | (define-normal-insn-enum |
| 150 | insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode |
| 151 | (("J" #x00) |
| 152 | ("JAL" #x01) |
| 153 | ("ADRP" #x02) |
| 154 | ("BNF" #x03) |
| 155 | ("BF" #x04) |
| 156 | ("NOP" #x05) |
| 157 | ("MOVHIMACRC" #x06) |
| 158 | ("SYSTRAPSYNCS" #x08) |
| 159 | ("RFE" #x09) |
| 160 | ("VECTOR" #x0a) |
| 161 | ("JR" #x11) |
| 162 | ("JALR" #x12) |
| 163 | ("MACI" #x13) |
| 164 | ("LWA" #x1b) |
| 165 | ("CUST1" #x1c) |
| 166 | ("CUST2" #x1d) |
| 167 | ("CUST3" #x1e) |
| 168 | ("CUST4" #x1f) |
| 169 | ("LD" #x20) |
| 170 | ("LWZ" #x21) |
| 171 | ("LWS" #x22) |
| 172 | ("LBZ" #x23) |
| 173 | ("LBS" #x24) |
| 174 | ("LHZ" #x25) |
| 175 | ("LHS" #x26) |
| 176 | ("ADDI" #x27) |
| 177 | ("ADDIC" #x28) |
| 178 | ("ANDI" #x29) |
| 179 | ("ORI" #x2a) |
| 180 | ("XORI" #x2b) |
| 181 | ("MULI" #x2c) |
| 182 | ("MFSPR" #x2d) |
| 183 | ("SHROTI" #x2e) |
| 184 | ("SFI" #x2f) |
| 185 | ("MTSPR" #x30) |
| 186 | ("MAC" #x31) |
| 187 | ("FLOAT" #x32) |
| 188 | ("SWA" #x33) |
| 189 | ("SD" #x34) |
| 190 | ("SW" #x35) |
| 191 | ("SB" #x36) |
| 192 | ("SH" #x37) |
| 193 | ("ALU" #x38) |
| 194 | ("SF" #x39) |
| 195 | ("CUST5" #x3c) |
| 196 | ("CUST6" #x3d) |
| 197 | ("CUST7" #x3e) |
| 198 | ("CUST8" #x3f) |
| 199 | ) |
| 200 | ) |
| 201 | |
| 202 | (define-normal-insn-enum insn-opcode-systrapsyncs |
| 203 | "systrapsync insn opcode enums" ((MACH ORBIS-MACHS)) |
| 204 | OPC_SYSTRAPSYNCS_ f-op-25-5 |
| 205 | (("SYSCALL" #x00 ) |
| 206 | ("TRAP" #x08 ) |
| 207 | ("MSYNC" #x10 ) |
| 208 | ("PSYNC" #x14 ) |
| 209 | ("CSYNC" #x18 ) |
| 210 | ) |
| 211 | ) |
| 212 | |
| 213 | (define-normal-insn-enum insn-opcode-movehimacrc |
| 214 | "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS)) |
| 215 | OPC_MOVHIMACRC_ f-op-16-1 |
| 216 | (("MOVHI" #x0) |
| 217 | ("MACRC" #x1) |
| 218 | ) |
| 219 | ) |
| 220 | |
| 221 | (define-normal-insn-enum insn-opcode-mac |
| 222 | "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS)) |
| 223 | OPC_MAC_ f-op-3-4 |
| 224 | (("MAC" #x1) |
| 225 | ("MSB" #x2) |
| 226 | ("MACU" #x3) |
| 227 | ("MSBU" #x4) |
| 228 | ) |
| 229 | ) |
| 230 | |
| 231 | (define-normal-insn-enum insn-opcode-shorts |
| 232 | "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS)) |
| 233 | OPC_SHROTS_ f-op-7-2 |
| 234 | (("SLL" #x0 ) |
| 235 | ("SRL" #x1 ) |
| 236 | ("SRA" #x2 ) |
| 237 | ("ROR" #x3 ) |
| 238 | ) |
| 239 | ) |
| 240 | |
| 241 | (define-normal-insn-enum insn-opcode-extbhs |
| 242 | "extend byte/half opcode enums" ((MACH ORBIS-MACHS)) |
| 243 | OPC_EXTBHS_ f-op-9-4 |
| 244 | (("EXTHS" #x0) |
| 245 | ("EXTBS" #x1) |
| 246 | ("EXTHZ" #x2) |
| 247 | ("EXTBZ" #x3) |
| 248 | ) |
| 249 | ) |
| 250 | |
| 251 | (define-normal-insn-enum insn-opcode-extws |
| 252 | "extend word opcode enums" ((MACH ORBIS-MACHS)) |
| 253 | OPC_EXTWS_ f-op-9-4 |
| 254 | (("EXTWS" #x0) |
| 255 | ("EXTWZ" #x1) |
| 256 | ) |
| 257 | ) |
| 258 | |
| 259 | (define-normal-insn-enum insn-opcode-alu-regreg |
| 260 | "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS)) |
| 261 | OPC_ALU_REGREG_ f-op-3-4 |
| 262 | (("ADD" #x0) |
| 263 | ("ADDC" #x1) |
| 264 | ("SUB" #x2) |
| 265 | ("AND" #x3) |
| 266 | ("OR" #x4) |
| 267 | ("XOR" #x5) |
| 268 | ("MUL" #x6) |
| 269 | ("MULD" #x7) |
| 270 | ("SHROT" #x8) |
| 271 | ("DIV" #x9) |
| 272 | ("DIVU" #xA) |
| 273 | ("MULU" #xB) |
| 274 | ("EXTBH" #xC) |
| 275 | ("EXTW" #xD) |
| 276 | ("MULDU" #xD) |
| 277 | ("CMOV" #xE) |
| 278 | ("FFL1" #xF) |
| 279 | ) |
| 280 | ) |
| 281 | |
| 282 | (define-normal-insn-enum insn-opcode-setflag |
| 283 | "setflag insn opcode enums" ((MACH ORBIS-MACHS)) |
| 284 | OPC_SF_ f-op-25-5 |
| 285 | (("EQ" #x00) |
| 286 | ("NE" #x01) |
| 287 | ("GTU" #x02) |
| 288 | ("GEU" #x03) |
| 289 | ("LTU" #x04) |
| 290 | ("LEU" #x05) |
| 291 | ("GTS" #x0A) |
| 292 | ("GES" #x0B) |
| 293 | ("LTS" #x0C) |
| 294 | ("LES" #x0D) |
| 295 | ) |
| 296 | ) |
| 297 | |
| 298 | \f |
| 299 | ; Instruction operands. |
| 300 | |
| 301 | (dnop sys-sr "supervision register" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr f-nil) |
| 302 | (dnop sys-esr0 "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0 f-nil) |
| 303 | (dnop sys-epcr0 "exception PC register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0 f-nil) |
| 304 | |
| 305 | (dnop sys-sr-lee "SR little endian enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee f-nil) |
| 306 | (dnop sys-sr-f "SR flag bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f f-nil) |
| 307 | (dnop sys-sr-cy "SR carry bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy f-nil) |
| 308 | (dnop sys-sr-ov "SR overflow bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov f-nil) |
| 309 | (dnop sys-sr-ove "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove f-nil) |
| 310 | (dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil) |
| 311 | (dnop sys-cpucfgr-nd "CPUCFGR no delay bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd f-nil) |
| 312 | (dnop sys-fpcsr-rm "floating point round mode" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm f-nil) |
| 313 | |
| 314 | (dnop mac-machi "MAC HI result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi f-nil) |
| 315 | (dnop mac-maclo "MAC LO result register" ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo f-nil) |
| 316 | |
| 317 | (dnop atomic-reserve "atomic reserve flag" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve f-nil) |
| 318 | (dnop atomic-address "atomic address" ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address f-nil) |
| 319 | |
| 320 | (dnop uimm6 "uimm6" ((MACH ORBIS-MACHS)) h-uimm6 f-uimm6) |
| 321 | |
| 322 | (dnop rD "destination register" ((MACH ORBIS-MACHS)) h-gpr f-r1) |
| 323 | (dnop rA "source register A" ((MACH ORBIS-MACHS)) h-gpr f-r2) |
| 324 | (dnop rB "source register B" ((MACH ORBIS-MACHS)) h-gpr f-r3) |
| 325 | |
| 326 | (define-operand |
| 327 | (name disp26) |
| 328 | (comment "pc-rel 26 bit") |
| 329 | (attrs (MACH ORBIS-MACHS)) |
| 330 | (type h-iaddr) |
| 331 | (index f-disp26) |
| 332 | (handlers (parse "disp26")) |
| 333 | ) |
| 334 | |
| 335 | (define-operand |
| 336 | (name disp21) |
| 337 | (comment "pc-rel 21 bit") |
| 338 | (attrs (MACH ORBIS-MACHS)) |
| 339 | (type h-iaddr) |
| 340 | (index f-disp21) |
| 341 | (handlers (parse "disp21")) |
| 342 | ) |
| 343 | |
| 344 | (define-operand |
| 345 | (name simm16) |
| 346 | (comment "16-bit signed immediate") |
| 347 | (attrs (MACH ORBIS-MACHS) SIGN-OPT) |
| 348 | (type h-simm16) |
| 349 | (index f-simm16) |
| 350 | (handlers (parse "simm16")) |
| 351 | ) |
| 352 | |
| 353 | (define-operand |
| 354 | (name uimm16) |
| 355 | (comment "16-bit unsigned immediate") |
| 356 | (attrs (MACH ORBIS-MACHS)) |
| 357 | (type h-uimm16) |
| 358 | (index f-uimm16) |
| 359 | (handlers (parse "uimm16")) |
| 360 | ) |
| 361 | |
| 362 | (define-operand |
| 363 | (name simm16-split) |
| 364 | (comment "split 16-bit signed immediate") |
| 365 | (attrs (MACH ORBIS-MACHS) SIGN-OPT) |
| 366 | (type h-simm16) |
| 367 | (index f-simm16-split) |
| 368 | (handlers (parse "simm16_split")) |
| 369 | ) |
| 370 | |
| 371 | (define-operand |
| 372 | (name uimm16-split) |
| 373 | (comment "split 16-bit unsigned immediate") |
| 374 | (attrs (MACH ORBIS-MACHS)) |
| 375 | (type h-uimm16) |
| 376 | (index f-uimm16-split) |
| 377 | (handlers (parse "uimm16_split")) |
| 378 | ) |
| 379 | |
| 380 | ; Instructions. |
| 381 | |
| 382 | ; Branch releated instructions |
| 383 | |
| 384 | (define-pmacro (cti-link-return) |
| 385 | (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8))) |
| 386 | ) |
| 387 | (define-pmacro (cti-transfer-control condition target) |
| 388 | ;; this mess is necessary because we're |
| 389 | ;; skipping the delay slot, but it's |
| 390 | ;; actually the start of the next basic |
| 391 | ;; block |
| 392 | (sequence () |
| 393 | (if condition |
| 394 | (delay 1 (set IAI pc target)) |
| 395 | (if sys-cpucfgr-nd |
| 396 | (delay 1 (set IAI pc (add pc 4)))) |
| 397 | ) |
| 398 | (if sys-cpucfgr-nd |
| 399 | (skip 1) |
| 400 | ) |
| 401 | ) |
| 402 | ) |
| 403 | |
| 404 | (define-pmacro |
| 405 | (define-cti |
| 406 | cti-name |
| 407 | cti-comment |
| 408 | cti-attrs |
| 409 | cti-syntax |
| 410 | cti-format |
| 411 | cti-semantics) |
| 412 | (begin |
| 413 | (dni |
| 414 | cti-name |
| 415 | cti-comment |
| 416 | (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs)) |
| 417 | cti-syntax |
| 418 | cti-format |
| 419 | (cti-semantics) |
| 420 | () |
| 421 | ) |
| 422 | ) |
| 423 | ) |
| 424 | |
| 425 | (define-cti |
| 426 | l-j |
| 427 | "jump (pc-relative iaddr)" |
| 428 | (!COND-CTI UNCOND-CTI) |
| 429 | "l.j ${disp26}" |
| 430 | (+ OPC_J disp26) |
| 431 | (.pmacro () |
| 432 | (cti-transfer-control 1 disp26) |
| 433 | ) |
| 434 | ) |
| 435 | |
| 436 | (dni l-adrp "load pc-relative page address" |
| 437 | ((MACH ORBIS-MACHS)) |
| 438 | "l.adrp $rD,${disp21}" |
| 439 | (+ OPC_ADRP rD disp21) |
| 440 | (set UWI rD disp21) |
| 441 | () |
| 442 | ) |
| 443 | |
| 444 | (define-cti |
| 445 | l-jal |
| 446 | "jump and link (pc-relative iaddr)" |
| 447 | (!COND-CTI UNCOND-CTI) |
| 448 | "l.jal ${disp26}" |
| 449 | (+ OPC_JAL disp26) |
| 450 | (.pmacro () |
| 451 | (sequence () |
| 452 | (cti-link-return) |
| 453 | (cti-transfer-control 1 disp26) |
| 454 | ) |
| 455 | ) |
| 456 | ) |
| 457 | |
| 458 | (define-cti |
| 459 | l-jr |
| 460 | "jump register (absolute iaddr)" |
| 461 | (!COND-CTI UNCOND-CTI) |
| 462 | "l.jr $rB" |
| 463 | (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0)) |
| 464 | (.pmacro () |
| 465 | (cti-transfer-control 1 rB) |
| 466 | ) |
| 467 | ) |
| 468 | |
| 469 | (define-cti |
| 470 | l-jalr |
| 471 | "jump register and link (absolute iaddr)" |
| 472 | (!COND-CTI UNCOND-CTI) |
| 473 | "l.jalr $rB" |
| 474 | (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) ) |
| 475 | (.pmacro () |
| 476 | (sequence () |
| 477 | (cti-link-return) |
| 478 | (cti-transfer-control 1 rB) |
| 479 | ) |
| 480 | ) |
| 481 | ) |
| 482 | |
| 483 | (define-cti |
| 484 | l-bnf |
| 485 | "branch if condition bit not set (pc relative iaddr)" |
| 486 | (COND-CTI !UNCOND-CTI) |
| 487 | "l.bnf ${disp26}" |
| 488 | (+ OPC_BNF disp26) |
| 489 | (.pmacro () |
| 490 | (cti-transfer-control (not sys-sr-f) disp26) |
| 491 | ) |
| 492 | ) |
| 493 | |
| 494 | (define-cti |
| 495 | l-bf |
| 496 | "branch if condition bit set (pc relative iaddr)" |
| 497 | (COND-CTI !UNCOND-CTI) |
| 498 | "l.bf ${disp26}" |
| 499 | (+ OPC_BF disp26) |
| 500 | (.pmacro () |
| 501 | (cti-transfer-control sys-sr-f disp26) |
| 502 | ) |
| 503 | ) |
| 504 | |
| 505 | (dni l-trap "trap (exception)" |
| 506 | ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) |
| 507 | "l.trap ${uimm16}" |
| 508 | (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16) |
| 509 | ; Do exception entry handling in C function, PC set based on SR state |
| 510 | (raise-exception EXCEPT-TRAP) |
| 511 | () |
| 512 | ) |
| 513 | |
| 514 | |
| 515 | (dni l-sys "syscall (exception)" |
| 516 | ; This function may not be in delay slot |
| 517 | ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT) |
| 518 | |
| 519 | "l.sys ${uimm16}" |
| 520 | (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16) |
| 521 | ; Do exception entry handling in C function, PC set based on SR state |
| 522 | (raise-exception EXCEPT-SYSCALL) |
| 523 | () |
| 524 | ) |
| 525 | |
| 526 | (dni l-msync "memory sync" |
| 527 | ((MACH ORBIS-MACHS)) |
| 528 | "l.msync" |
| 529 | (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_MSYNC (f-resv-20-21 0)) |
| 530 | (nop) |
| 531 | () |
| 532 | ) |
| 533 | |
| 534 | (dni l-psync "pipeline sync" |
| 535 | ((MACH ORBIS-MACHS)) |
| 536 | "l.psync" |
| 537 | (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_PSYNC (f-resv-20-21 0)) |
| 538 | (nop) |
| 539 | () |
| 540 | ) |
| 541 | |
| 542 | (dni l-csync "context sync" |
| 543 | ((MACH ORBIS-MACHS)) |
| 544 | "l.csync" |
| 545 | (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_CSYNC (f-resv-20-21 0)) |
| 546 | (nop) |
| 547 | () |
| 548 | ) |
| 549 | |
| 550 | (dni l-rfe "return from exception" |
| 551 | ; This function may not be in delay slot |
| 552 | ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI) |
| 553 | |
| 554 | "l.rfe" |
| 555 | (+ OPC_RFE (f-resv-25-26 0)) |
| 556 | (c-call VOID "@cpu@_rfe") |
| 557 | () |
| 558 | ) |
| 559 | |
| 560 | \f |
| 561 | ; Misc instructions |
| 562 | |
| 563 | ; l.nop with immediate must be first so it handles all l.nops in sim |
| 564 | (dni l-nop-imm "nop uimm16" |
| 565 | ((MACH ORBIS-MACHS)) |
| 566 | "l.nop ${uimm16}" |
| 567 | (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) |
| 568 | (c-call VOID "@cpu@_nop" (zext UWI uimm16)) |
| 569 | () |
| 570 | ) |
| 571 | |
| 572 | (if (application-is? SIMULATOR) |
| 573 | (begin) |
| 574 | (begin |
| 575 | (dni l-nop "nop" |
| 576 | ((MACH ORBIS-MACHS)) |
| 577 | "l.nop" |
| 578 | (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16) |
| 579 | (nop) |
| 580 | () |
| 581 | ) |
| 582 | ) |
| 583 | ) |
| 584 | |
| 585 | (dni l-movhi "movhi reg/uimm16" |
| 586 | ((MACH ORBIS-MACHS)) |
| 587 | "l.movhi $rD,$uimm16" |
| 588 | (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16) |
| 589 | (set UWI rD (sll UWI (zext UWI uimm16) (const 16))) |
| 590 | () |
| 591 | ) |
| 592 | |
| 593 | (dni l-macrc "macrc reg" |
| 594 | ((MACH ORBIS-MACHS)) |
| 595 | "l.macrc $rD" |
| 596 | (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0)) |
| 597 | (sequence () |
| 598 | (set UWI rD mac-maclo) |
| 599 | (set UWI mac-maclo 0) |
| 600 | (set UWI mac-machi 0) |
| 601 | ) |
| 602 | () |
| 603 | ) |
| 604 | |
| 605 | \f |
| 606 | ; System releated instructions |
| 607 | |
| 608 | (dni l-mfspr "mfspr" |
| 609 | ((MACH ORBIS-MACHS)) |
| 610 | "l.mfspr $rD,$rA,${uimm16}" |
| 611 | (+ OPC_MFSPR rD rA uimm16) |
| 612 | (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16)))) |
| 613 | () |
| 614 | ) |
| 615 | |
| 616 | (dni l-mtspr "mtspr" |
| 617 | ((MACH ORBIS-MACHS)) |
| 618 | "l.mtspr $rA,$rB,${uimm16-split}" |
| 619 | (+ OPC_MTSPR rA rB uimm16-split ) |
| 620 | (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB) |
| 621 | () |
| 622 | ) |
| 623 | |
| 624 | \f |
| 625 | ; Load instructions |
| 626 | (define-pmacro (load-store-addr base offset size) |
| 627 | (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size)) |
| 628 | |
| 629 | (dni l-lwz "l.lwz reg/simm16(reg)" |
| 630 | ((MACH ORBIS-MACHS)) |
| 631 | "l.lwz $rD,${simm16}($rA)" |
| 632 | (+ OPC_LWZ rD rA simm16) |
| 633 | (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) |
| 634 | () |
| 635 | ) |
| 636 | |
| 637 | |
| 638 | (dni l-lws "l.lws reg/simm16(reg)" |
| 639 | ((MACH ORBIS-MACHS)) |
| 640 | "l.lws $rD,${simm16}($rA)" |
| 641 | (+ OPC_LWS rD rA simm16) |
| 642 | (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4)))) |
| 643 | () |
| 644 | ) |
| 645 | |
| 646 | (dni l-lwa "l.lwa reg/simm16(reg)" |
| 647 | ((MACH ORBIS-MACHS)) |
| 648 | "l.lwa $rD,${simm16}($rA)" |
| 649 | (+ OPC_LWA rD rA simm16) |
| 650 | (sequence () |
| 651 | (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4)))) |
| 652 | (set atomic-reserve (const 1)) |
| 653 | (set atomic-address (load-store-addr rA simm16 4)) |
| 654 | ) |
| 655 | () |
| 656 | ) |
| 657 | |
| 658 | (dni l-lbz "l.lbz reg/simm16(reg)" |
| 659 | ((MACH ORBIS-MACHS)) |
| 660 | "l.lbz $rD,${simm16}($rA)" |
| 661 | (+ OPC_LBZ rD rA simm16) |
| 662 | (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1)))) |
| 663 | () |
| 664 | ) |
| 665 | |
| 666 | (dni l-lbs "l.lbs reg/simm16(reg)" |
| 667 | ((MACH ORBIS-MACHS)) |
| 668 | "l.lbs $rD,${simm16}($rA)" |
| 669 | (+ OPC_LBS rD rA simm16) |
| 670 | (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1)))) |
| 671 | () |
| 672 | ) |
| 673 | |
| 674 | (dni l-lhz "l.lhz reg/simm16(reg)" |
| 675 | ((MACH ORBIS-MACHS)) |
| 676 | "l.lhz $rD,${simm16}($rA)" |
| 677 | (+ OPC_LHZ rD simm16 rA) |
| 678 | (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2)))) |
| 679 | () |
| 680 | ) |
| 681 | |
| 682 | (dni l-lhs "l.lhs reg/simm16(reg)" |
| 683 | ((MACH ORBIS-MACHS)) |
| 684 | "l.lhs $rD,${simm16}($rA)" |
| 685 | (+ OPC_LHS rD rA simm16) |
| 686 | (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2)))) |
| 687 | () |
| 688 | ) |
| 689 | |
| 690 | \f |
| 691 | ; Store instructions |
| 692 | |
| 693 | (define-pmacro (store-insn mnemonic opc-op mode size) |
| 694 | (begin |
| 695 | (dni (.sym l- mnemonic) |
| 696 | (.str "l." mnemonic " simm16(reg)/reg") |
| 697 | ((MACH ORBIS-MACHS)) |
| 698 | (.str "l." mnemonic " ${simm16-split}($rA),$rB") |
| 699 | (+ opc-op rA rB simm16-split) |
| 700 | (sequence ((SI addr)) |
| 701 | (set addr (load-store-addr rA simm16-split size)) |
| 702 | (set mode (mem mode addr) (trunc mode rB)) |
| 703 | (if (eq (and addr #xffffffc) atomic-address) |
| 704 | (set atomic-reserve (const 0)) |
| 705 | ) |
| 706 | ) |
| 707 | () |
| 708 | ) |
| 709 | ) |
| 710 | ) |
| 711 | |
| 712 | (store-insn sw OPC_SW USI 4) |
| 713 | (store-insn sb OPC_SB UQI 1) |
| 714 | (store-insn sh OPC_SH UHI 2) |
| 715 | |
| 716 | (dni l-swa "l.swa simm16(reg)/reg" |
| 717 | ((MACH ORBIS-MACHS)) |
| 718 | "l.swa ${simm16-split}($rA),$rB" |
| 719 | (+ OPC_SWA rA rB simm16) |
| 720 | (sequence ((SI addr) (BI flag)) |
| 721 | (set addr (load-store-addr rA simm16-split 4)) |
| 722 | (set sys-sr-f (and atomic-reserve (eq addr atomic-address))) |
| 723 | (if sys-sr-f |
| 724 | (set USI (mem USI addr) (trunc USI rB)) |
| 725 | ) |
| 726 | (set atomic-reserve (const 0)) |
| 727 | ) |
| 728 | () |
| 729 | ) |
| 730 | |
| 731 | \f |
| 732 | ; Shift and rotate instructions |
| 733 | |
| 734 | (define-pmacro (shift-insn mnemonic) |
| 735 | (begin |
| 736 | (dni (.sym l- mnemonic) |
| 737 | (.str "l." mnemonic " reg/reg/reg") |
| 738 | ((MACH ORBIS-MACHS)) |
| 739 | (.str "l." mnemonic " $rD,$rA,$rB") |
| 740 | (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0) |
| 741 | OPC_ALU_REGREG_SHROT ) |
| 742 | (set UWI rD (mnemonic rA rB)) |
| 743 | () |
| 744 | ) |
| 745 | (dni (.sym l- mnemonic "i") |
| 746 | (.str "l." mnemonic " reg/reg/uimm6") |
| 747 | ((MACH ORBIS-MACHS)) |
| 748 | (.str "l." mnemonic "i $rD,$rA,${uimm6}") |
| 749 | (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6) |
| 750 | (set rD (mnemonic rA uimm6)) |
| 751 | () |
| 752 | ) |
| 753 | ) |
| 754 | ) |
| 755 | |
| 756 | (shift-insn sll) |
| 757 | (shift-insn srl) |
| 758 | (shift-insn sra) |
| 759 | (shift-insn ror) |
| 760 | |
| 761 | \f |
| 762 | ; Arithmetic insns |
| 763 | |
| 764 | ; ALU op macro |
| 765 | (define-pmacro (alu-insn mnemonic) |
| 766 | (begin |
| 767 | (dni (.sym l- mnemonic) |
| 768 | (.str "l." mnemonic " reg/reg/reg") |
| 769 | ((MACH ORBIS-MACHS)) |
| 770 | (.str "l." mnemonic " $rD,$rA,$rB") |
| 771 | (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) |
| 772 | (set rD (mnemonic rA rB)) |
| 773 | () |
| 774 | ) |
| 775 | ) |
| 776 | ) |
| 777 | |
| 778 | (alu-insn and) |
| 779 | (alu-insn or) |
| 780 | (alu-insn xor) |
| 781 | |
| 782 | (define-pmacro (alu-carry-insn mnemonic) |
| 783 | (begin |
| 784 | (dni (.sym l- mnemonic) |
| 785 | (.str "l." mnemonic " reg/reg/reg") |
| 786 | ((MACH ORBIS-MACHS)) |
| 787 | (.str "l." mnemonic " $rD,$rA,$rB") |
| 788 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic))) |
| 789 | (sequence () |
| 790 | (sequence () |
| 791 | (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0)) |
| 792 | (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0)) |
| 793 | (set rD (mnemonic WI rA rB)) |
| 794 | ) |
| 795 | (if (andif sys-sr-ov sys-sr-ove) |
| 796 | (raise-exception EXCEPT-RANGE)) |
| 797 | ) |
| 798 | () |
| 799 | ) |
| 800 | ) |
| 801 | ) |
| 802 | |
| 803 | (alu-carry-insn add) |
| 804 | (alu-carry-insn sub) |
| 805 | |
| 806 | (dni (l-addc) "l.addc reg/reg/reg" |
| 807 | ((MACH ORBIS-MACHS)) |
| 808 | ("l.addc $rD,$rA,$rB") |
| 809 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC) |
| 810 | (sequence () |
| 811 | (sequence ((BI tmp-sys-sr-cy)) |
| 812 | (set BI tmp-sys-sr-cy sys-sr-cy) |
| 813 | (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy)) |
| 814 | (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy)) |
| 815 | (set rD (addc WI rA rB tmp-sys-sr-cy)) |
| 816 | ) |
| 817 | (if (andif sys-sr-ov sys-sr-ove) |
| 818 | (raise-exception EXCEPT-RANGE)) |
| 819 | ) |
| 820 | () |
| 821 | ) |
| 822 | |
| 823 | (dni (l-mul) "l.mul reg/reg/reg" |
| 824 | ((MACH ORBIS-MACHS)) |
| 825 | ("l.mul $rD,$rA,$rB") |
| 826 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL) |
| 827 | (sequence () |
| 828 | (sequence () |
| 829 | (set BI sys-sr-ov (mul-o2flag WI rA rB)) |
| 830 | (set rD (mul WI rA rB)) |
| 831 | ) |
| 832 | (if (andif sys-sr-ov sys-sr-ove) |
| 833 | (raise-exception EXCEPT-RANGE)) |
| 834 | ) |
| 835 | () |
| 836 | ) |
| 837 | |
| 838 | (dni (l-muld) "l.muld reg/reg" |
| 839 | ((MACH ORBIS-MACHS)) |
| 840 | ("l.muld $rA,$rB") |
| 841 | (+ OPC_ALU (f-resv-25-5 0) rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULD) |
| 842 | (sequence ((DI result)) |
| 843 | (set DI result (mul DI (ext DI rA) (ext DI rB))) |
| 844 | (set SI mac-machi (subword SI result 0)) |
| 845 | (set SI mac-maclo (subword SI result 1)) |
| 846 | ) |
| 847 | () |
| 848 | ) |
| 849 | |
| 850 | (dni (l-mulu) "l.mulu reg/reg/reg" |
| 851 | ((MACH ORBIS-MACHS)) |
| 852 | ("l.mulu $rD,$rA,$rB") |
| 853 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU) |
| 854 | (sequence () |
| 855 | (sequence () |
| 856 | (set BI sys-sr-cy (mul-o1flag UWI rA rB)) |
| 857 | (set rD (mul UWI rA rB)) |
| 858 | ) |
| 859 | (if (andif sys-sr-cy sys-sr-ove) |
| 860 | (raise-exception EXCEPT-RANGE)) |
| 861 | ) |
| 862 | () |
| 863 | ) |
| 864 | |
| 865 | (dni (l-muldu) "l.muld reg/reg" |
| 866 | ((MACH ORBIS-MACHS)) |
| 867 | ("l.muldu $rA,$rB") |
| 868 | (+ OPC_ALU (f-resv-25-5 0) rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULDU) |
| 869 | (sequence ((DI result)) |
| 870 | (set DI result (mul DI (zext DI rA) (zext DI rB))) |
| 871 | (set SI mac-machi (subword SI result 0)) |
| 872 | (set SI mac-maclo (subword SI result 1)) |
| 873 | ) |
| 874 | () |
| 875 | ) |
| 876 | |
| 877 | (dni l-div "divide (signed)" |
| 878 | ((MACH ORBIS-MACHS)) |
| 879 | "l.div $rD,$rA,$rB" |
| 880 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV) |
| 881 | (if (ne rB 0) |
| 882 | (sequence () |
| 883 | (set BI sys-sr-ov 0) |
| 884 | (set WI rD (div WI rA rB)) |
| 885 | ) |
| 886 | (sequence () |
| 887 | (set BI sys-sr-ov 1) |
| 888 | (if sys-sr-ove |
| 889 | (raise-exception EXCEPT-RANGE)) |
| 890 | ) |
| 891 | ) |
| 892 | () |
| 893 | ) |
| 894 | |
| 895 | (dni l-divu "divide (unsigned)" |
| 896 | ((MACH ORBIS-MACHS)) |
| 897 | "l.divu $rD,$rA,$rB" |
| 898 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU) |
| 899 | (if (ne rB 0) |
| 900 | (sequence () |
| 901 | (set BI sys-sr-cy 0) |
| 902 | (set rD (udiv UWI rA rB)) |
| 903 | ) |
| 904 | (sequence () |
| 905 | (set BI sys-sr-cy 1) |
| 906 | (if sys-sr-ove |
| 907 | (raise-exception EXCEPT-RANGE)) |
| 908 | ) |
| 909 | ) |
| 910 | () |
| 911 | ) |
| 912 | |
| 913 | (dni l-ff1 "find first '1'" |
| 914 | ((MACH ORBIS-MACHS)) |
| 915 | "l.ff1 $rD,$rA" |
| 916 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1) |
| 917 | (set rD (c-call UWI "@cpu@_ff1" rA)) |
| 918 | () |
| 919 | ) |
| 920 | |
| 921 | (dni l-fl1 "find last '1'" |
| 922 | ((MACH ORBIS-MACHS)) |
| 923 | "l.fl1 $rD,$rA" |
| 924 | (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1) |
| 925 | (set rD (c-call UWI "@cpu@_fl1" rA)) |
| 926 | () |
| 927 | ) |
| 928 | |
| 929 | |
| 930 | (define-pmacro (alu-insn-simm mnemonic) |
| 931 | (begin |
| 932 | (dni (.sym l- mnemonic "i") |
| 933 | (.str "l." mnemonic " reg/reg/simm16") |
| 934 | ((MACH ORBIS-MACHS)) |
| 935 | (.str "l." mnemonic "i $rD,$rA,$simm16") |
| 936 | (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) |
| 937 | (set rD (mnemonic rA (ext WI simm16))) |
| 938 | () |
| 939 | ) |
| 940 | ) |
| 941 | ) |
| 942 | |
| 943 | (define-pmacro (alu-insn-uimm mnemonic) |
| 944 | (begin |
| 945 | (dni (.sym l- mnemonic "i") |
| 946 | (.str "l." mnemonic " reg/reg/uimm16") |
| 947 | ((MACH ORBIS-MACHS)) |
| 948 | (.str "l." mnemonic "i $rD,$rA,$uimm16") |
| 949 | (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16) |
| 950 | (set rD (mnemonic rA (zext UWI uimm16))) |
| 951 | () |
| 952 | ) |
| 953 | ) |
| 954 | ) |
| 955 | |
| 956 | (alu-insn-uimm and) |
| 957 | (alu-insn-uimm or) |
| 958 | (alu-insn-simm xor) |
| 959 | |
| 960 | (define-pmacro (alu-carry-insn-simm mnemonic) |
| 961 | (begin |
| 962 | (dni (.sym l- mnemonic "i") |
| 963 | (.str "l." mnemonic "i reg/reg/simm16") |
| 964 | ((MACH ORBIS-MACHS)) |
| 965 | (.str "l." mnemonic "i $rD,$rA,$simm16") |
| 966 | (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) |
| 967 | (sequence () |
| 968 | (sequence () |
| 969 | (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0)) |
| 970 | (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0)) |
| 971 | (set rD (mnemonic WI rA (ext WI simm16))) |
| 972 | ) |
| 973 | (if (andif sys-sr-ov sys-sr-ove) |
| 974 | (raise-exception EXCEPT-RANGE)) |
| 975 | ) |
| 976 | () |
| 977 | ) |
| 978 | ) |
| 979 | ) |
| 980 | |
| 981 | (alu-carry-insn-simm add) |
| 982 | |
| 983 | (dni (l-addic) |
| 984 | ("l.addic reg/reg/simm16") |
| 985 | ((MACH ORBIS-MACHS)) |
| 986 | ("l.addic $rD,$rA,$simm16") |
| 987 | (+ OPC_ADDIC rD rA simm16) |
| 988 | (sequence () |
| 989 | (sequence ((BI tmp-sys-sr-cy)) |
| 990 | (set BI tmp-sys-sr-cy sys-sr-cy) |
| 991 | (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy)) |
| 992 | (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy)) |
| 993 | (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy)) |
| 994 | ) |
| 995 | (if (andif sys-sr-ov sys-sr-ove) |
| 996 | (raise-exception EXCEPT-RANGE)) |
| 997 | ) |
| 998 | () |
| 999 | ) |
| 1000 | |
| 1001 | (dni (l-muli) |
| 1002 | "l.muli reg/reg/simm16" |
| 1003 | ((MACH ORBIS-MACHS)) |
| 1004 | ("l.muli $rD,$rA,$simm16") |
| 1005 | (+ OPC_MULI rD rA simm16) |
| 1006 | (sequence () |
| 1007 | (sequence () |
| 1008 | (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16))) |
| 1009 | (set rD (mul WI rA (ext WI simm16))) |
| 1010 | ) |
| 1011 | (if (andif sys-sr-ov sys-sr-ove) |
| 1012 | (raise-exception EXCEPT-RANGE)) |
| 1013 | ) |
| 1014 | () |
| 1015 | ) |
| 1016 | |
| 1017 | (define-pmacro (extbh-insn mnemonic extop extmode truncmode) |
| 1018 | (begin |
| 1019 | (dni (.sym l- mnemonic) |
| 1020 | (.str "l." mnemonic " reg/reg") |
| 1021 | ((MACH ORBIS-MACHS)) |
| 1022 | (.str "l." mnemonic " $rD,$rA") |
| 1023 | (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH) |
| 1024 | (set rD (extop extmode (trunc truncmode rA))) |
| 1025 | () |
| 1026 | ) |
| 1027 | ) |
| 1028 | ) |
| 1029 | |
| 1030 | (extbh-insn exths ext WI HI) |
| 1031 | (extbh-insn extbs ext WI QI) |
| 1032 | (extbh-insn exthz zext UWI UHI) |
| 1033 | (extbh-insn extbz zext UWI UQI) |
| 1034 | |
| 1035 | (define-pmacro (extw-insn mnemonic extop extmode truncmode) |
| 1036 | (begin |
| 1037 | (dni (.sym l- mnemonic) |
| 1038 | (.str "l." mnemonic " reg/reg") |
| 1039 | ((MACH ORBIS-MACHS)) |
| 1040 | (.str "l." mnemonic " $rD,$rA") |
| 1041 | (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW) |
| 1042 | (set rD (extop extmode (trunc truncmode rA))) |
| 1043 | () |
| 1044 | ) |
| 1045 | ) |
| 1046 | ) |
| 1047 | |
| 1048 | (extw-insn extws ext WI SI) |
| 1049 | (extw-insn extwz zext USI USI) |
| 1050 | |
| 1051 | (dni l-cmov |
| 1052 | "l.cmov reg/reg/reg" |
| 1053 | ((MACH ORBIS-MACHS)) |
| 1054 | "l.cmov $rD,$rA,$rB" |
| 1055 | (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV) |
| 1056 | (if sys-sr-f |
| 1057 | (set UWI rD rA) |
| 1058 | (set UWI rD rB) |
| 1059 | ) |
| 1060 | () |
| 1061 | ) |
| 1062 | |
| 1063 | ; Compare instructions |
| 1064 | |
| 1065 | ; Ordering compare |
| 1066 | (define-pmacro (sf-insn op) |
| 1067 | (begin |
| 1068 | (dni (.sym l- "sf" op "s") ; l-sfgts |
| 1069 | (.str "l.sf" op "s reg/reg") ; "l.sfgts reg/reg" |
| 1070 | ((MACH ORBIS-MACHS)) |
| 1071 | (.str "l.sf" op "s $rA,$rB") ; "l.sfgts $rA,$rB" |
| 1072 | (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0)) |
| 1073 | (set sys-sr-f (op WI rA rB)) ; (set sys-sr-f (gt WI rA rB)) |
| 1074 | () |
| 1075 | ) |
| 1076 | (dni (.sym l- "sf" op "si") ; l-sfgtsi |
| 1077 | (.str "l.sf" op "si reg/simm16") ; "l.sfgtsi reg/simm16" |
| 1078 | ((MACH ORBIS-MACHS)) |
| 1079 | (.str "l.sf" op "si $rA,$simm16") ; "l.sfgtsi $rA,$simm16" |
| 1080 | (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16) ; (+ OPC_SFI OPC_SF_GTS rA simm16) |
| 1081 | (set sys-sr-f (op WI rA (ext WI simm16))) ; (set sys-sr-f (gt WI rA (ext WI simm16))) |
| 1082 | () |
| 1083 | ) |
| 1084 | (dni (.sym l- "sf" op "u") ; l-sfgtu |
| 1085 | (.str "l.sf" op "u reg/reg") ; "l.sfgtu reg/reg" |
| 1086 | ((MACH ORBIS-MACHS)) |
| 1087 | (.str "l.sf" op "u $rA,$rB") ; "l.sfgtu $rA,$rB" |
| 1088 | (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0)) |
| 1089 | (set sys-sr-f ((.sym op "u") WI rA rB)) ; (set sys-sr-f (gtu WI rA rB)) |
| 1090 | () |
| 1091 | ) |
| 1092 | ; immediate is sign extended even for unsigned compare |
| 1093 | (dni (.sym l- "sf" op "ui") ; l-sfgtui |
| 1094 | (.str "l.sf" op "ui reg/simm16") ; "l.sfgtui reg/uimm16" |
| 1095 | ((MACH ORBIS-MACHS)) |
| 1096 | (.str "l.sf" op "ui $rA,$simm16") ; "l.sfgtui $rA,$simm16" |
| 1097 | (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16) ; (+ OPC_SFI OPC_SF_GTU rA simm16) |
| 1098 | (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16))) ; (set sys-sr-f (gtu WI rA (ext WI simm16))) |
| 1099 | () |
| 1100 | ) |
| 1101 | ) |
| 1102 | ) |
| 1103 | |
| 1104 | (sf-insn gt) |
| 1105 | (sf-insn ge) |
| 1106 | (sf-insn lt) |
| 1107 | (sf-insn le) |
| 1108 | |
| 1109 | ; Equality compare |
| 1110 | (define-pmacro (sf-insn-eq op) |
| 1111 | (begin |
| 1112 | (dni (.sym l- "sf" op) |
| 1113 | (.str "l." op " reg/reg") |
| 1114 | ((MACH ORBIS-MACHS)) |
| 1115 | (.str "l.sf" op " $rA,$rB") |
| 1116 | (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0)) |
| 1117 | (set sys-sr-f (op WI rA rB)) |
| 1118 | () |
| 1119 | ) |
| 1120 | (dni (.sym l- "sf" op "i") |
| 1121 | (.str "l.sf" op "i reg/simm16") |
| 1122 | ((MACH ORBIS-MACHS)) |
| 1123 | (.str "l.sf" op "i $rA,$simm16") |
| 1124 | (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16) |
| 1125 | (set sys-sr-f (op WI rA (ext WI simm16))) |
| 1126 | () |
| 1127 | ) |
| 1128 | ) |
| 1129 | ) |
| 1130 | |
| 1131 | (sf-insn-eq eq) |
| 1132 | (sf-insn-eq ne) |
| 1133 | |
| 1134 | (dni l-mac |
| 1135 | "l.mac reg/reg" |
| 1136 | ((MACH ORBIS-MACHS)) |
| 1137 | "l.mac $rA,$rB" |
| 1138 | (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC) |
| 1139 | (sequence () |
| 1140 | (sequence ((DI prod) (DI mac) (DI result)) |
| 1141 | (set DI prod (mul DI (ext DI rA) (ext DI rB))) |
| 1142 | (set DI mac (join DI SI mac-machi mac-maclo)) |
| 1143 | (set DI result (add prod mac)) |
| 1144 | (set SI mac-machi (subword SI result 0)) |
| 1145 | (set SI mac-maclo (subword SI result 1)) |
| 1146 | (set BI sys-sr-ov (addc-oflag prod mac 0)) |
| 1147 | ) |
| 1148 | (if (andif sys-sr-ov sys-sr-ove) |
| 1149 | (raise-exception EXCEPT-RANGE)) |
| 1150 | ) |
| 1151 | () |
| 1152 | ) |
| 1153 | |
| 1154 | (dni l-maci |
| 1155 | "l.maci reg/simm16" |
| 1156 | ((MACH ORBIS-MACHS)) |
| 1157 | "l.maci $rA,${simm16}" |
| 1158 | (+ OPC_MACI (f-resv-25-5 0) rA simm16) |
| 1159 | (sequence () |
| 1160 | (sequence ((DI prod) (DI mac) (DI result)) |
| 1161 | (set DI prod (mul DI (ext DI rA) (ext DI simm16))) |
| 1162 | (set DI mac (join DI SI mac-machi mac-maclo)) |
| 1163 | (set DI result (add mac prod)) |
| 1164 | (set SI mac-machi (subword SI result 0)) |
| 1165 | (set SI mac-maclo (subword SI result 1)) |
| 1166 | (set BI sys-sr-ov (addc-oflag prod mac 0)) |
| 1167 | ) |
| 1168 | (if (andif sys-sr-ov sys-sr-ove) |
| 1169 | (raise-exception EXCEPT-RANGE)) |
| 1170 | ) |
| 1171 | () |
| 1172 | ) |
| 1173 | |
| 1174 | (dni l-macu |
| 1175 | "l.macu reg/reg" |
| 1176 | ((MACH ORBIS-MACHS)) |
| 1177 | "l.macu $rA,$rB" |
| 1178 | (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MACU) |
| 1179 | (sequence () |
| 1180 | (sequence ((DI prod) (DI mac) (DI result)) |
| 1181 | (set DI prod (mul DI (zext DI rA) (zext DI rB))) |
| 1182 | (set DI mac (join DI SI mac-machi mac-maclo)) |
| 1183 | (set DI result (add prod mac)) |
| 1184 | (set SI mac-machi (subword SI result 0)) |
| 1185 | (set SI mac-maclo (subword SI result 1)) |
| 1186 | (set BI sys-sr-cy (addc-cflag prod mac 0)) |
| 1187 | ) |
| 1188 | (if (andif sys-sr-cy sys-sr-ove) |
| 1189 | (raise-exception EXCEPT-RANGE)) |
| 1190 | ) |
| 1191 | () |
| 1192 | ) |
| 1193 | |
| 1194 | (dni l-msb |
| 1195 | "l.msb reg/reg" |
| 1196 | ((MACH ORBIS-MACHS)) |
| 1197 | "l.msb $rA,$rB" |
| 1198 | (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB) |
| 1199 | (sequence () |
| 1200 | (sequence ((DI prod) (DI mac) (DI result)) |
| 1201 | (set DI prod (mul DI (ext DI rA) (ext DI rB))) |
| 1202 | (set DI mac (join DI SI mac-machi mac-maclo)) |
| 1203 | (set DI result (sub mac prod)) |
| 1204 | (set SI mac-machi (subword SI result 0)) |
| 1205 | (set SI mac-maclo (subword SI result 1)) |
| 1206 | (set BI sys-sr-ov (subc-oflag mac result 0)) |
| 1207 | ) |
| 1208 | (if (andif sys-sr-ov sys-sr-ove) |
| 1209 | (raise-exception EXCEPT-RANGE)) |
| 1210 | ) |
| 1211 | () |
| 1212 | ) |
| 1213 | |
| 1214 | (dni l-msbu |
| 1215 | "l.msbu reg/reg" |
| 1216 | ((MACH ORBIS-MACHS)) |
| 1217 | "l.msbu $rA,$rB" |
| 1218 | (+ OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSBU) |
| 1219 | (sequence () |
| 1220 | (sequence ((DI prod) (DI mac) (DI result)) |
| 1221 | (set DI prod (mul DI (zext DI rA) (zext DI rB))) |
| 1222 | (set DI mac (join DI SI mac-machi mac-maclo)) |
| 1223 | (set DI result (sub mac prod)) |
| 1224 | (set SI mac-machi (subword SI result 0)) |
| 1225 | (set SI mac-maclo (subword SI result 1)) |
| 1226 | (set BI sys-sr-cy (subc-cflag mac result 0)) |
| 1227 | ) |
| 1228 | (if (andif sys-sr-cy sys-sr-ove) |
| 1229 | (raise-exception EXCEPT-RANGE)) |
| 1230 | ) |
| 1231 | () |
| 1232 | ) |
| 1233 | |
| 1234 | (define-pmacro (cust-insn cust-num) |
| 1235 | (begin |
| 1236 | (dni (.sym l- "cust" cust-num) |
| 1237 | (.str "l.cust" cust-num) |
| 1238 | ((MACH ORBIS-MACHS)) |
| 1239 | (.str "l.cust" cust-num) |
| 1240 | (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0)) |
| 1241 | (nop) |
| 1242 | () |
| 1243 | ) |
| 1244 | ) |
| 1245 | ) |
| 1246 | |
| 1247 | (cust-insn "1") |
| 1248 | (cust-insn "2") |
| 1249 | (cust-insn "3") |
| 1250 | (cust-insn "4") |
| 1251 | (cust-insn "5") |
| 1252 | (cust-insn "6") |
| 1253 | (cust-insn "7") |
| 1254 | (cust-insn "8") |