Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / drivers / clk / clk-divider.c
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1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adjustable divider clock implementation
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/log2.h>
20
21/*
22 * DOC: basic adjustable divider clock that cannot gate
23 *
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
28 * parent - fixed parent. No clk_set_parent support
29 */
30
31#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
32
33#define div_mask(width) ((1 << (width)) - 1)
34
35static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
36 u8 width)
37{
38 unsigned int maxdiv = 0, mask = div_mask(width);
39 const struct clk_div_table *clkt;
40
41 for (clkt = table; clkt->div; clkt++)
42 if (clkt->div > maxdiv && clkt->val <= mask)
43 maxdiv = clkt->div;
44 return maxdiv;
45}
46
47static unsigned int _get_table_mindiv(const struct clk_div_table *table)
48{
49 unsigned int mindiv = UINT_MAX;
50 const struct clk_div_table *clkt;
51
52 for (clkt = table; clkt->div; clkt++)
53 if (clkt->div < mindiv)
54 mindiv = clkt->div;
55 return mindiv;
56}
57
58static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
59 unsigned long flags)
60{
61 if (flags & CLK_DIVIDER_ONE_BASED)
62 return div_mask(width);
63 if (flags & CLK_DIVIDER_POWER_OF_TWO)
64 return 1 << div_mask(width);
65 if (table)
66 return _get_table_maxdiv(table, width);
67 return div_mask(width) + 1;
68}
69
70static unsigned int _get_table_div(const struct clk_div_table *table,
71 unsigned int val)
72{
73 const struct clk_div_table *clkt;
74
75 for (clkt = table; clkt->div; clkt++)
76 if (clkt->val == val)
77 return clkt->div;
78 return 0;
79}
80
81static unsigned int _get_div(const struct clk_div_table *table,
82 unsigned int val, unsigned long flags, u8 width)
83{
84 if (flags & CLK_DIVIDER_ONE_BASED)
85 return val;
86 if (flags & CLK_DIVIDER_POWER_OF_TWO)
87 return 1 << val;
88 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
89 return val ? val : div_mask(width) + 1;
90 if (table)
91 return _get_table_div(table, val);
92 return val + 1;
93}
94
95static unsigned int _get_table_val(const struct clk_div_table *table,
96 unsigned int div)
97{
98 const struct clk_div_table *clkt;
99
100 for (clkt = table; clkt->div; clkt++)
101 if (clkt->div == div)
102 return clkt->val;
103 return 0;
104}
105
106static unsigned int _get_val(const struct clk_div_table *table,
107 unsigned int div, unsigned long flags, u8 width)
108{
109 if (flags & CLK_DIVIDER_ONE_BASED)
110 return div;
111 if (flags & CLK_DIVIDER_POWER_OF_TWO)
112 return __ffs(div);
113 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
114 return (div == div_mask(width) + 1) ? 0 : div;
115 if (table)
116 return _get_table_val(table, div);
117 return div - 1;
118}
119
120unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
121 unsigned int val,
122 const struct clk_div_table *table,
123 unsigned long flags)
124{
125 struct clk_divider *divider = to_clk_divider(hw);
126 unsigned int div;
127
128 div = _get_div(table, val, flags, divider->width);
129 if (!div) {
130 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
131 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
132 clk_hw_get_name(hw));
133 return parent_rate;
134 }
135
136 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
137}
138EXPORT_SYMBOL_GPL(divider_recalc_rate);
139
140static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
141 unsigned long parent_rate)
142{
143 struct clk_divider *divider = to_clk_divider(hw);
144 unsigned int val;
145
146 val = clk_readl(divider->reg) >> divider->shift;
147 val &= div_mask(divider->width);
148
149 return divider_recalc_rate(hw, parent_rate, val, divider->table,
150 divider->flags);
151}
152
153static bool _is_valid_table_div(const struct clk_div_table *table,
154 unsigned int div)
155{
156 const struct clk_div_table *clkt;
157
158 for (clkt = table; clkt->div; clkt++)
159 if (clkt->div == div)
160 return true;
161 return false;
162}
163
164static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
165 unsigned long flags)
166{
167 if (flags & CLK_DIVIDER_POWER_OF_TWO)
168 return is_power_of_2(div);
169 if (table)
170 return _is_valid_table_div(table, div);
171 return true;
172}
173
174static int _round_up_table(const struct clk_div_table *table, int div)
175{
176 const struct clk_div_table *clkt;
177 int up = INT_MAX;
178
179 for (clkt = table; clkt->div; clkt++) {
180 if (clkt->div == div)
181 return clkt->div;
182 else if (clkt->div < div)
183 continue;
184
185 if ((clkt->div - div) < (up - div))
186 up = clkt->div;
187 }
188
189 return up;
190}
191
192static int _round_down_table(const struct clk_div_table *table, int div)
193{
194 const struct clk_div_table *clkt;
195 int down = _get_table_mindiv(table);
196
197 for (clkt = table; clkt->div; clkt++) {
198 if (clkt->div == div)
199 return clkt->div;
200 else if (clkt->div > div)
201 continue;
202
203 if ((div - clkt->div) < (div - down))
204 down = clkt->div;
205 }
206
207 return down;
208}
209
210static int _div_round_up(const struct clk_div_table *table,
211 unsigned long parent_rate, unsigned long rate,
212 unsigned long flags)
213{
214 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
215
216 if (flags & CLK_DIVIDER_POWER_OF_TWO)
217 div = __roundup_pow_of_two(div);
218 if (table)
219 div = _round_up_table(table, div);
220
221 return div;
222}
223
224static int _div_round_closest(const struct clk_div_table *table,
225 unsigned long parent_rate, unsigned long rate,
226 unsigned long flags)
227{
228 int up, down;
229 unsigned long up_rate, down_rate;
230
231 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
232 down = parent_rate / rate;
233
234 if (flags & CLK_DIVIDER_POWER_OF_TWO) {
235 up = __roundup_pow_of_two(up);
236 down = __rounddown_pow_of_two(down);
237 } else if (table) {
238 up = _round_up_table(table, up);
239 down = _round_down_table(table, down);
240 }
241
242 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
243 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
244
245 return (rate - up_rate) <= (down_rate - rate) ? up : down;
246}
247
248static int _div_round(const struct clk_div_table *table,
249 unsigned long parent_rate, unsigned long rate,
250 unsigned long flags)
251{
252 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
253 return _div_round_closest(table, parent_rate, rate, flags);
254
255 return _div_round_up(table, parent_rate, rate, flags);
256}
257
258static bool _is_best_div(unsigned long rate, unsigned long now,
259 unsigned long best, unsigned long flags)
260{
261 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
262 return abs(rate - now) < abs(rate - best);
263
264 return now <= rate && now > best;
265}
266
267static int _next_div(const struct clk_div_table *table, int div,
268 unsigned long flags)
269{
270 div++;
271
272 if (flags & CLK_DIVIDER_POWER_OF_TWO)
273 return __roundup_pow_of_two(div);
274 if (table)
275 return _round_up_table(table, div);
276
277 return div;
278}
279
280static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
281 unsigned long *best_parent_rate,
282 const struct clk_div_table *table, u8 width,
283 unsigned long flags)
284{
285 int i, bestdiv = 0;
286 unsigned long parent_rate, best = 0, now, maxdiv;
287 unsigned long parent_rate_saved = *best_parent_rate;
288
289 if (!rate)
290 rate = 1;
291
292 maxdiv = _get_maxdiv(table, width, flags);
293
294 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
295 parent_rate = *best_parent_rate;
296 bestdiv = _div_round(table, parent_rate, rate, flags);
297 bestdiv = bestdiv == 0 ? 1 : bestdiv;
298 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
299 return bestdiv;
300 }
301
302 /*
303 * The maximum divider we can use without overflowing
304 * unsigned long in rate * i below
305 */
306 maxdiv = min(ULONG_MAX / rate, maxdiv);
307
308 for (i = 1; i <= maxdiv; i = _next_div(table, i, flags)) {
309 if (!_is_valid_div(table, i, flags))
310 continue;
311 if (rate * i == parent_rate_saved) {
312 /*
313 * It's the most ideal case if the requested rate can be
314 * divided from parent clock without needing to change
315 * parent rate, so return the divider immediately.
316 */
317 *best_parent_rate = parent_rate_saved;
318 return i;
319 }
320 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
321 rate * i);
322 now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
323 if (_is_best_div(rate, now, best, flags)) {
324 bestdiv = i;
325 best = now;
326 *best_parent_rate = parent_rate;
327 }
328 }
329
330 if (!bestdiv) {
331 bestdiv = _get_maxdiv(table, width, flags);
332 *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
333 }
334
335 return bestdiv;
336}
337
338long divider_round_rate(struct clk_hw *hw, unsigned long rate,
339 unsigned long *prate, const struct clk_div_table *table,
340 u8 width, unsigned long flags)
341{
342 int div;
343
344 div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
345
346 return DIV_ROUND_UP_ULL((u64)*prate, div);
347}
348EXPORT_SYMBOL_GPL(divider_round_rate);
349
350static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
351 unsigned long *prate)
352{
353 struct clk_divider *divider = to_clk_divider(hw);
354 int bestdiv;
355
356 /* if read only, just return current value */
357 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
358 bestdiv = readl(divider->reg) >> divider->shift;
359 bestdiv &= div_mask(divider->width);
360 bestdiv = _get_div(divider->table, bestdiv, divider->flags,
361 divider->width);
362 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
363 }
364
365 return divider_round_rate(hw, rate, prate, divider->table,
366 divider->width, divider->flags);
367}
368
369int divider_get_val(unsigned long rate, unsigned long parent_rate,
370 const struct clk_div_table *table, u8 width,
371 unsigned long flags)
372{
373 unsigned int div, value;
374
375 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
376
377 if (!_is_valid_div(table, div, flags))
378 return -EINVAL;
379
380 value = _get_val(table, div, flags, width);
381
382 return min_t(unsigned int, value, div_mask(width));
383}
384EXPORT_SYMBOL_GPL(divider_get_val);
385
386static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
387 unsigned long parent_rate)
388{
389 struct clk_divider *divider = to_clk_divider(hw);
390 unsigned int value;
391 unsigned long flags = 0;
392 u32 val;
393
394 value = divider_get_val(rate, parent_rate, divider->table,
395 divider->width, divider->flags);
396
397 if (divider->lock)
398 spin_lock_irqsave(divider->lock, flags);
399 else
400 __acquire(divider->lock);
401
402 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
403 val = div_mask(divider->width) << (divider->shift + 16);
404 } else {
405 val = clk_readl(divider->reg);
406 val &= ~(div_mask(divider->width) << divider->shift);
407 }
408 val |= value << divider->shift;
409 clk_writel(val, divider->reg);
410
411 if (divider->lock)
412 spin_unlock_irqrestore(divider->lock, flags);
413 else
414 __release(divider->lock);
415
416 return 0;
417}
418
419const struct clk_ops clk_divider_ops = {
420 .recalc_rate = clk_divider_recalc_rate,
421 .round_rate = clk_divider_round_rate,
422 .set_rate = clk_divider_set_rate,
423};
424EXPORT_SYMBOL_GPL(clk_divider_ops);
425
426static struct clk *_register_divider(struct device *dev, const char *name,
427 const char *parent_name, unsigned long flags,
428 void __iomem *reg, u8 shift, u8 width,
429 u8 clk_divider_flags, const struct clk_div_table *table,
430 spinlock_t *lock)
431{
432 struct clk_divider *div;
433 struct clk *clk;
434 struct clk_init_data init;
435
436 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
437 if (width + shift > 16) {
438 pr_warn("divider value exceeds LOWORD field\n");
439 return ERR_PTR(-EINVAL);
440 }
441 }
442
443 /* allocate the divider */
444 div = kzalloc(sizeof(*div), GFP_KERNEL);
445 if (!div)
446 return ERR_PTR(-ENOMEM);
447
448 init.name = name;
449 init.ops = &clk_divider_ops;
450 init.flags = flags | CLK_IS_BASIC;
451 init.parent_names = (parent_name ? &parent_name: NULL);
452 init.num_parents = (parent_name ? 1 : 0);
453
454 /* struct clk_divider assignments */
455 div->reg = reg;
456 div->shift = shift;
457 div->width = width;
458 div->flags = clk_divider_flags;
459 div->lock = lock;
460 div->hw.init = &init;
461 div->table = table;
462
463 /* register the clock */
464 clk = clk_register(dev, &div->hw);
465
466 if (IS_ERR(clk))
467 kfree(div);
468
469 return clk;
470}
471
472/**
473 * clk_register_divider - register a divider clock with the clock framework
474 * @dev: device registering this clock
475 * @name: name of this clock
476 * @parent_name: name of clock's parent
477 * @flags: framework-specific flags
478 * @reg: register address to adjust divider
479 * @shift: number of bits to shift the bitfield
480 * @width: width of the bitfield
481 * @clk_divider_flags: divider-specific flags for this clock
482 * @lock: shared register lock for this clock
483 */
484struct clk *clk_register_divider(struct device *dev, const char *name,
485 const char *parent_name, unsigned long flags,
486 void __iomem *reg, u8 shift, u8 width,
487 u8 clk_divider_flags, spinlock_t *lock)
488{
489 return _register_divider(dev, name, parent_name, flags, reg, shift,
490 width, clk_divider_flags, NULL, lock);
491}
492EXPORT_SYMBOL_GPL(clk_register_divider);
493
494/**
495 * clk_register_divider_table - register a table based divider clock with
496 * the clock framework
497 * @dev: device registering this clock
498 * @name: name of this clock
499 * @parent_name: name of clock's parent
500 * @flags: framework-specific flags
501 * @reg: register address to adjust divider
502 * @shift: number of bits to shift the bitfield
503 * @width: width of the bitfield
504 * @clk_divider_flags: divider-specific flags for this clock
505 * @table: array of divider/value pairs ending with a div set to 0
506 * @lock: shared register lock for this clock
507 */
508struct clk *clk_register_divider_table(struct device *dev, const char *name,
509 const char *parent_name, unsigned long flags,
510 void __iomem *reg, u8 shift, u8 width,
511 u8 clk_divider_flags, const struct clk_div_table *table,
512 spinlock_t *lock)
513{
514 return _register_divider(dev, name, parent_name, flags, reg, shift,
515 width, clk_divider_flags, table, lock);
516}
517EXPORT_SYMBOL_GPL(clk_register_divider_table);
518
519void clk_unregister_divider(struct clk *clk)
520{
521 struct clk_divider *div;
522 struct clk_hw *hw;
523
524 hw = __clk_get_hw(clk);
525 if (!hw)
526 return;
527
528 div = to_clk_divider(hw);
529
530 clk_unregister(clk);
531 kfree(div);
532}
533EXPORT_SYMBOL_GPL(clk_unregister_divider);
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