| 1 | /* |
| 2 | * Intel MID GPIO driver |
| 3 | * |
| 4 | * Copyright (c) 2008-2014 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | /* Supports: |
| 17 | * Moorestown platform Langwell chip. |
| 18 | * Medfield platform Penwell chip. |
| 19 | * Clovertrail platform Cloverview chip. |
| 20 | * Merrifield platform Tangier chip. |
| 21 | */ |
| 22 | |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/pci.h> |
| 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/delay.h> |
| 28 | #include <linux/stddef.h> |
| 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/io.h> |
| 32 | #include <linux/gpio/driver.h> |
| 33 | #include <linux/slab.h> |
| 34 | #include <linux/pm_runtime.h> |
| 35 | |
| 36 | #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0) |
| 37 | #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1) |
| 38 | |
| 39 | /* |
| 40 | * Langwell chip has 64 pins and thus there are 2 32bit registers to control |
| 41 | * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit |
| 42 | * registers to control them, so we only define the order here instead of a |
| 43 | * structure, to get a bit offset for a pin (use GPDR as an example): |
| 44 | * |
| 45 | * nreg = ngpio / 32; |
| 46 | * reg = offset / 32; |
| 47 | * bit = offset % 32; |
| 48 | * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4; |
| 49 | * |
| 50 | * so the bit of reg_addr is to control pin offset's GPDR feature |
| 51 | */ |
| 52 | |
| 53 | enum GPIO_REG { |
| 54 | GPLR = 0, /* pin level read-only */ |
| 55 | GPDR, /* pin direction */ |
| 56 | GPSR, /* pin set */ |
| 57 | GPCR, /* pin clear */ |
| 58 | GRER, /* rising edge detect */ |
| 59 | GFER, /* falling edge detect */ |
| 60 | GEDR, /* edge detect result */ |
| 61 | GAFR, /* alt function */ |
| 62 | }; |
| 63 | |
| 64 | /* intel_mid gpio driver data */ |
| 65 | struct intel_mid_gpio_ddata { |
| 66 | u16 ngpio; /* number of gpio pins */ |
| 67 | u32 gplr_offset; /* offset of first GPLR register from base */ |
| 68 | u32 flis_base; /* base address of FLIS registers */ |
| 69 | u32 flis_len; /* length of FLIS registers */ |
| 70 | u32 (*get_flis_offset)(int gpio); |
| 71 | u32 chip_irq_type; /* chip interrupt type */ |
| 72 | }; |
| 73 | |
| 74 | struct intel_mid_gpio { |
| 75 | struct gpio_chip chip; |
| 76 | void __iomem *reg_base; |
| 77 | spinlock_t lock; |
| 78 | struct pci_dev *pdev; |
| 79 | }; |
| 80 | |
| 81 | static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc) |
| 82 | { |
| 83 | return container_of(gc, struct intel_mid_gpio, chip); |
| 84 | } |
| 85 | |
| 86 | static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, |
| 87 | enum GPIO_REG reg_type) |
| 88 | { |
| 89 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
| 90 | unsigned nreg = chip->ngpio / 32; |
| 91 | u8 reg = offset / 32; |
| 92 | |
| 93 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
| 94 | } |
| 95 | |
| 96 | static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, |
| 97 | enum GPIO_REG reg_type) |
| 98 | { |
| 99 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
| 100 | unsigned nreg = chip->ngpio / 32; |
| 101 | u8 reg = offset / 16; |
| 102 | |
| 103 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
| 104 | } |
| 105 | |
| 106 | static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 107 | { |
| 108 | void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR); |
| 109 | u32 value = readl(gafr); |
| 110 | int shift = (offset % 16) << 1, af = (value >> shift) & 3; |
| 111 | |
| 112 | if (af) { |
| 113 | value &= ~(3 << shift); |
| 114 | writel(value, gafr); |
| 115 | } |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 120 | { |
| 121 | void __iomem *gplr = gpio_reg(chip, offset, GPLR); |
| 122 | |
| 123 | return readl(gplr) & BIT(offset % 32); |
| 124 | } |
| 125 | |
| 126 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 127 | { |
| 128 | void __iomem *gpsr, *gpcr; |
| 129 | |
| 130 | if (value) { |
| 131 | gpsr = gpio_reg(chip, offset, GPSR); |
| 132 | writel(BIT(offset % 32), gpsr); |
| 133 | } else { |
| 134 | gpcr = gpio_reg(chip, offset, GPCR); |
| 135 | writel(BIT(offset % 32), gpcr); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 140 | { |
| 141 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
| 142 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
| 143 | u32 value; |
| 144 | unsigned long flags; |
| 145 | |
| 146 | if (priv->pdev) |
| 147 | pm_runtime_get(&priv->pdev->dev); |
| 148 | |
| 149 | spin_lock_irqsave(&priv->lock, flags); |
| 150 | value = readl(gpdr); |
| 151 | value &= ~BIT(offset % 32); |
| 152 | writel(value, gpdr); |
| 153 | spin_unlock_irqrestore(&priv->lock, flags); |
| 154 | |
| 155 | if (priv->pdev) |
| 156 | pm_runtime_put(&priv->pdev->dev); |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | static int intel_gpio_direction_output(struct gpio_chip *chip, |
| 162 | unsigned offset, int value) |
| 163 | { |
| 164 | struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); |
| 165 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
| 166 | unsigned long flags; |
| 167 | |
| 168 | intel_gpio_set(chip, offset, value); |
| 169 | |
| 170 | if (priv->pdev) |
| 171 | pm_runtime_get(&priv->pdev->dev); |
| 172 | |
| 173 | spin_lock_irqsave(&priv->lock, flags); |
| 174 | value = readl(gpdr); |
| 175 | value |= BIT(offset % 32); |
| 176 | writel(value, gpdr); |
| 177 | spin_unlock_irqrestore(&priv->lock, flags); |
| 178 | |
| 179 | if (priv->pdev) |
| 180 | pm_runtime_put(&priv->pdev->dev); |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | static int intel_mid_irq_type(struct irq_data *d, unsigned type) |
| 186 | { |
| 187 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 188 | struct intel_mid_gpio *priv = to_intel_gpio_priv(gc); |
| 189 | u32 gpio = irqd_to_hwirq(d); |
| 190 | unsigned long flags; |
| 191 | u32 value; |
| 192 | void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); |
| 193 | void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); |
| 194 | |
| 195 | if (gpio >= priv->chip.ngpio) |
| 196 | return -EINVAL; |
| 197 | |
| 198 | if (priv->pdev) |
| 199 | pm_runtime_get(&priv->pdev->dev); |
| 200 | |
| 201 | spin_lock_irqsave(&priv->lock, flags); |
| 202 | if (type & IRQ_TYPE_EDGE_RISING) |
| 203 | value = readl(grer) | BIT(gpio % 32); |
| 204 | else |
| 205 | value = readl(grer) & (~BIT(gpio % 32)); |
| 206 | writel(value, grer); |
| 207 | |
| 208 | if (type & IRQ_TYPE_EDGE_FALLING) |
| 209 | value = readl(gfer) | BIT(gpio % 32); |
| 210 | else |
| 211 | value = readl(gfer) & (~BIT(gpio % 32)); |
| 212 | writel(value, gfer); |
| 213 | spin_unlock_irqrestore(&priv->lock, flags); |
| 214 | |
| 215 | if (priv->pdev) |
| 216 | pm_runtime_put(&priv->pdev->dev); |
| 217 | |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | static void intel_mid_irq_unmask(struct irq_data *d) |
| 222 | { |
| 223 | } |
| 224 | |
| 225 | static void intel_mid_irq_mask(struct irq_data *d) |
| 226 | { |
| 227 | } |
| 228 | |
| 229 | static struct irq_chip intel_mid_irqchip = { |
| 230 | .name = "INTEL_MID-GPIO", |
| 231 | .irq_mask = intel_mid_irq_mask, |
| 232 | .irq_unmask = intel_mid_irq_unmask, |
| 233 | .irq_set_type = intel_mid_irq_type, |
| 234 | }; |
| 235 | |
| 236 | static const struct intel_mid_gpio_ddata gpio_lincroft = { |
| 237 | .ngpio = 64, |
| 238 | }; |
| 239 | |
| 240 | static const struct intel_mid_gpio_ddata gpio_penwell_aon = { |
| 241 | .ngpio = 96, |
| 242 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
| 243 | }; |
| 244 | |
| 245 | static const struct intel_mid_gpio_ddata gpio_penwell_core = { |
| 246 | .ngpio = 96, |
| 247 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
| 248 | }; |
| 249 | |
| 250 | static const struct intel_mid_gpio_ddata gpio_cloverview_aon = { |
| 251 | .ngpio = 96, |
| 252 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL, |
| 253 | }; |
| 254 | |
| 255 | static const struct intel_mid_gpio_ddata gpio_cloverview_core = { |
| 256 | .ngpio = 96, |
| 257 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
| 258 | }; |
| 259 | |
| 260 | static const struct intel_mid_gpio_ddata gpio_tangier = { |
| 261 | .ngpio = 192, |
| 262 | .gplr_offset = 4, |
| 263 | .flis_base = 0xff0c0000, |
| 264 | .flis_len = 0x8000, |
| 265 | .get_flis_offset = NULL, |
| 266 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
| 267 | }; |
| 268 | |
| 269 | static const struct pci_device_id intel_gpio_ids[] = { |
| 270 | { |
| 271 | /* Lincroft */ |
| 272 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), |
| 273 | .driver_data = (kernel_ulong_t)&gpio_lincroft, |
| 274 | }, |
| 275 | { |
| 276 | /* Penwell AON */ |
| 277 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), |
| 278 | .driver_data = (kernel_ulong_t)&gpio_penwell_aon, |
| 279 | }, |
| 280 | { |
| 281 | /* Penwell Core */ |
| 282 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), |
| 283 | .driver_data = (kernel_ulong_t)&gpio_penwell_core, |
| 284 | }, |
| 285 | { |
| 286 | /* Cloverview Aon */ |
| 287 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), |
| 288 | .driver_data = (kernel_ulong_t)&gpio_cloverview_aon, |
| 289 | }, |
| 290 | { |
| 291 | /* Cloverview Core */ |
| 292 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), |
| 293 | .driver_data = (kernel_ulong_t)&gpio_cloverview_core, |
| 294 | }, |
| 295 | { |
| 296 | /* Tangier */ |
| 297 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199), |
| 298 | .driver_data = (kernel_ulong_t)&gpio_tangier, |
| 299 | }, |
| 300 | { 0 } |
| 301 | }; |
| 302 | MODULE_DEVICE_TABLE(pci, intel_gpio_ids); |
| 303 | |
| 304 | static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc) |
| 305 | { |
| 306 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
| 307 | struct intel_mid_gpio *priv = to_intel_gpio_priv(gc); |
| 308 | struct irq_data *data = irq_desc_get_irq_data(desc); |
| 309 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
| 310 | u32 base, gpio, mask; |
| 311 | unsigned long pending; |
| 312 | void __iomem *gedr; |
| 313 | |
| 314 | /* check GPIO controller to check which pin triggered the interrupt */ |
| 315 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
| 316 | gedr = gpio_reg(&priv->chip, base, GEDR); |
| 317 | while ((pending = readl(gedr))) { |
| 318 | gpio = __ffs(pending); |
| 319 | mask = BIT(gpio); |
| 320 | /* Clear before handling so we can't lose an edge */ |
| 321 | writel(mask, gedr); |
| 322 | generic_handle_irq(irq_find_mapping(gc->irqdomain, |
| 323 | base + gpio)); |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | chip->irq_eoi(data); |
| 328 | } |
| 329 | |
| 330 | static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) |
| 331 | { |
| 332 | void __iomem *reg; |
| 333 | unsigned base; |
| 334 | |
| 335 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
| 336 | /* Clear the rising-edge detect register */ |
| 337 | reg = gpio_reg(&priv->chip, base, GRER); |
| 338 | writel(0, reg); |
| 339 | /* Clear the falling-edge detect register */ |
| 340 | reg = gpio_reg(&priv->chip, base, GFER); |
| 341 | writel(0, reg); |
| 342 | /* Clear the edge detect status register */ |
| 343 | reg = gpio_reg(&priv->chip, base, GEDR); |
| 344 | writel(~0, reg); |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | static int intel_gpio_runtime_idle(struct device *dev) |
| 349 | { |
| 350 | int err = pm_schedule_suspend(dev, 500); |
| 351 | return err ?: -EBUSY; |
| 352 | } |
| 353 | |
| 354 | static const struct dev_pm_ops intel_gpio_pm_ops = { |
| 355 | SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle) |
| 356 | }; |
| 357 | |
| 358 | static int intel_gpio_probe(struct pci_dev *pdev, |
| 359 | const struct pci_device_id *id) |
| 360 | { |
| 361 | void __iomem *base; |
| 362 | struct intel_mid_gpio *priv; |
| 363 | u32 gpio_base; |
| 364 | u32 irq_base; |
| 365 | int retval; |
| 366 | struct intel_mid_gpio_ddata *ddata = |
| 367 | (struct intel_mid_gpio_ddata *)id->driver_data; |
| 368 | |
| 369 | retval = pcim_enable_device(pdev); |
| 370 | if (retval) |
| 371 | return retval; |
| 372 | |
| 373 | retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev)); |
| 374 | if (retval) { |
| 375 | dev_err(&pdev->dev, "I/O memory mapping error\n"); |
| 376 | return retval; |
| 377 | } |
| 378 | |
| 379 | base = pcim_iomap_table(pdev)[1]; |
| 380 | |
| 381 | irq_base = readl(base); |
| 382 | gpio_base = readl(sizeof(u32) + base); |
| 383 | |
| 384 | /* release the IO mapping, since we already get the info from bar1 */ |
| 385 | pcim_iounmap_regions(pdev, 1 << 1); |
| 386 | |
| 387 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 388 | if (!priv) { |
| 389 | dev_err(&pdev->dev, "can't allocate chip data\n"); |
| 390 | return -ENOMEM; |
| 391 | } |
| 392 | |
| 393 | priv->reg_base = pcim_iomap_table(pdev)[0]; |
| 394 | priv->chip.label = dev_name(&pdev->dev); |
| 395 | priv->chip.dev = &pdev->dev; |
| 396 | priv->chip.request = intel_gpio_request; |
| 397 | priv->chip.direction_input = intel_gpio_direction_input; |
| 398 | priv->chip.direction_output = intel_gpio_direction_output; |
| 399 | priv->chip.get = intel_gpio_get; |
| 400 | priv->chip.set = intel_gpio_set; |
| 401 | priv->chip.base = gpio_base; |
| 402 | priv->chip.ngpio = ddata->ngpio; |
| 403 | priv->chip.can_sleep = false; |
| 404 | priv->pdev = pdev; |
| 405 | |
| 406 | spin_lock_init(&priv->lock); |
| 407 | |
| 408 | pci_set_drvdata(pdev, priv); |
| 409 | retval = gpiochip_add(&priv->chip); |
| 410 | if (retval) { |
| 411 | dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
| 412 | return retval; |
| 413 | } |
| 414 | |
| 415 | retval = gpiochip_irqchip_add(&priv->chip, |
| 416 | &intel_mid_irqchip, |
| 417 | irq_base, |
| 418 | handle_simple_irq, |
| 419 | IRQ_TYPE_NONE); |
| 420 | if (retval) { |
| 421 | dev_err(&pdev->dev, |
| 422 | "could not connect irqchip to gpiochip\n"); |
| 423 | return retval; |
| 424 | } |
| 425 | |
| 426 | intel_mid_irq_init_hw(priv); |
| 427 | |
| 428 | gpiochip_set_chained_irqchip(&priv->chip, |
| 429 | &intel_mid_irqchip, |
| 430 | pdev->irq, |
| 431 | intel_mid_irq_handler); |
| 432 | |
| 433 | pm_runtime_put_noidle(&pdev->dev); |
| 434 | pm_runtime_allow(&pdev->dev); |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | static struct pci_driver intel_gpio_driver = { |
| 440 | .name = "intel_mid_gpio", |
| 441 | .id_table = intel_gpio_ids, |
| 442 | .probe = intel_gpio_probe, |
| 443 | .driver = { |
| 444 | .pm = &intel_gpio_pm_ops, |
| 445 | }, |
| 446 | }; |
| 447 | |
| 448 | static int __init intel_gpio_init(void) |
| 449 | { |
| 450 | return pci_register_driver(&intel_gpio_driver); |
| 451 | } |
| 452 | |
| 453 | device_initcall(intel_gpio_init); |