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gpio/omap: cleanup omap_gpio_mod_init function
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
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1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24
25#include <mach/hardware.h>
26#include <asm/irq.h>
27#include <mach/irqs.h>
28#include <asm/gpio.h>
29#include <asm/mach/irq.h>
30
31static LIST_HEAD(omap_gpio_list);
32
33struct gpio_regs {
34 u32 irqenable1;
35 u32 irqenable2;
36 u32 wake_en;
37 u32 ctrl;
38 u32 oe;
39 u32 leveldetect0;
40 u32 leveldetect1;
41 u32 risingdetect;
42 u32 fallingdetect;
43 u32 dataout;
44};
45
46struct gpio_bank {
47 struct list_head node;
48 unsigned long pbase;
49 void __iomem *base;
50 u16 irq;
51 u16 virtual_irq_start;
52 int method;
53 u32 suspend_wakeup;
54 u32 saved_wakeup;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 saved_fallingdetect;
60 u32 saved_risingdetect;
61 u32 level_mask;
62 u32 toggle_mask;
63 spinlock_t lock;
64 struct gpio_chip chip;
65 struct clk *dbck;
66 u32 mod_usage;
67 u32 dbck_enable_mask;
68 struct device *dev;
69 bool dbck_flag;
70 bool loses_context;
71 int stride;
72 u32 width;
73 int context_loss_count;
74 u16 id;
75
76 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
77 int (*get_context_loss_count)(struct device *dev);
78
79 struct omap_gpio_reg_offs *regs;
80};
81
82#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
83#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
84#define GPIO_MOD_CTRL_BIT BIT(0)
85
86static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
87{
88 void __iomem *reg = bank->base;
89 u32 l;
90
91 reg += bank->regs->direction;
92 l = __raw_readl(reg);
93 if (is_input)
94 l |= 1 << gpio;
95 else
96 l &= ~(1 << gpio);
97 __raw_writel(l, reg);
98}
99
100
101/* set data out value using dedicate set/clear register */
102static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
103{
104 void __iomem *reg = bank->base;
105 u32 l = GPIO_BIT(bank, gpio);
106
107 if (enable)
108 reg += bank->regs->set_dataout;
109 else
110 reg += bank->regs->clr_dataout;
111
112 __raw_writel(l, reg);
113}
114
115/* set data out value using mask register */
116static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
117{
118 void __iomem *reg = bank->base + bank->regs->dataout;
119 u32 gpio_bit = GPIO_BIT(bank, gpio);
120 u32 l;
121
122 l = __raw_readl(reg);
123 if (enable)
124 l |= gpio_bit;
125 else
126 l &= ~gpio_bit;
127 __raw_writel(l, reg);
128}
129
130static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
131{
132 void __iomem *reg = bank->base + bank->regs->datain;
133
134 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
135}
136
137static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
138{
139 void __iomem *reg = bank->base + bank->regs->dataout;
140
141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
142}
143
144static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
145{
146 int l = __raw_readl(base + reg);
147
148 if (set)
149 l |= mask;
150 else
151 l &= ~mask;
152
153 __raw_writel(l, base + reg);
154}
155
156/**
157 * _set_gpio_debounce - low level gpio debounce time
158 * @bank: the gpio bank we're acting upon
159 * @gpio: the gpio number on this @gpio
160 * @debounce: debounce time to use
161 *
162 * OMAP's debounce time is in 31us steps so we need
163 * to convert and round up to the closest unit.
164 */
165static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
166 unsigned debounce)
167{
168 void __iomem *reg;
169 u32 val;
170 u32 l;
171
172 if (!bank->dbck_flag)
173 return;
174
175 if (debounce < 32)
176 debounce = 0x01;
177 else if (debounce > 7936)
178 debounce = 0xff;
179 else
180 debounce = (debounce / 0x1f) - 1;
181
182 l = GPIO_BIT(bank, gpio);
183
184 reg = bank->base + bank->regs->debounce;
185 __raw_writel(debounce, reg);
186
187 reg = bank->base + bank->regs->debounce_en;
188 val = __raw_readl(reg);
189
190 if (debounce) {
191 val |= l;
192 clk_enable(bank->dbck);
193 } else {
194 val &= ~l;
195 clk_disable(bank->dbck);
196 }
197 bank->dbck_enable_mask = val;
198
199 __raw_writel(val, reg);
200}
201
202static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
203 int trigger)
204{
205 void __iomem *base = bank->base;
206 u32 gpio_bit = 1 << gpio;
207
208 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
209 trigger & IRQ_TYPE_LEVEL_LOW);
210 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
211 trigger & IRQ_TYPE_LEVEL_HIGH);
212 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
213 trigger & IRQ_TYPE_EDGE_RISING);
214 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
215 trigger & IRQ_TYPE_EDGE_FALLING);
216
217 if (likely(!(bank->non_wakeup_gpios & gpio_bit)))
218 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
219
220 /* This part needs to be executed always for OMAP{34xx, 44xx} */
221 if (!bank->regs->irqctrl) {
222 /* On omap24xx proceed only when valid GPIO bit is set */
223 if (bank->non_wakeup_gpios) {
224 if (!(bank->non_wakeup_gpios & gpio_bit))
225 goto exit;
226 }
227
228 /*
229 * Log the edge gpio and manually trigger the IRQ
230 * after resume if the input level changes
231 * to avoid irq lost during PER RET/OFF mode
232 * Applies for omap2 non-wakeup gpio and all omap3 gpios
233 */
234 if (trigger & IRQ_TYPE_EDGE_BOTH)
235 bank->enabled_non_wakeup_gpios |= gpio_bit;
236 else
237 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
238 }
239
240exit:
241 bank->level_mask =
242 __raw_readl(bank->base + bank->regs->leveldetect0) |
243 __raw_readl(bank->base + bank->regs->leveldetect1);
244}
245
246#ifdef CONFIG_ARCH_OMAP1
247/*
248 * This only applies to chips that can't do both rising and falling edge
249 * detection at once. For all other chips, this function is a noop.
250 */
251static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
252{
253 void __iomem *reg = bank->base;
254 u32 l = 0;
255
256 if (!bank->regs->irqctrl)
257 return;
258
259 reg += bank->regs->irqctrl;
260
261 l = __raw_readl(reg);
262 if ((l >> gpio) & 1)
263 l &= ~(1 << gpio);
264 else
265 l |= 1 << gpio;
266
267 __raw_writel(l, reg);
268}
269#else
270static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
271#endif
272
273static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
274{
275 void __iomem *reg = bank->base;
276 void __iomem *base = bank->base;
277 u32 l = 0;
278
279 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
280 set_gpio_trigger(bank, gpio, trigger);
281 } else if (bank->regs->irqctrl) {
282 reg += bank->regs->irqctrl;
283
284 l = __raw_readl(reg);
285 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
286 bank->toggle_mask |= 1 << gpio;
287 if (trigger & IRQ_TYPE_EDGE_RISING)
288 l |= 1 << gpio;
289 else if (trigger & IRQ_TYPE_EDGE_FALLING)
290 l &= ~(1 << gpio);
291 else
292 return -EINVAL;
293
294 __raw_writel(l, reg);
295 } else if (bank->regs->edgectrl1) {
296 if (gpio & 0x08)
297 reg += bank->regs->edgectrl2;
298 else
299 reg += bank->regs->edgectrl1;
300
301 gpio &= 0x07;
302 l = __raw_readl(reg);
303 l &= ~(3 << (gpio << 1));
304 if (trigger & IRQ_TYPE_EDGE_RISING)
305 l |= 2 << (gpio << 1);
306 if (trigger & IRQ_TYPE_EDGE_FALLING)
307 l |= 1 << (gpio << 1);
308
309 /* Enable wake-up during idle for dynamic tick */
310 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
311 __raw_writel(l, reg);
312 }
313 return 0;
314}
315
316static int gpio_irq_type(struct irq_data *d, unsigned type)
317{
318 struct gpio_bank *bank;
319 unsigned gpio;
320 int retval;
321 unsigned long flags;
322
323 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
324 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
325 else
326 gpio = d->irq - IH_GPIO_BASE;
327
328 if (type & ~IRQ_TYPE_SENSE_MASK)
329 return -EINVAL;
330
331 bank = irq_data_get_irq_chip_data(d);
332
333 if (!bank->regs->leveldetect0 &&
334 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
335 return -EINVAL;
336
337 spin_lock_irqsave(&bank->lock, flags);
338 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
339 spin_unlock_irqrestore(&bank->lock, flags);
340
341 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
342 __irq_set_handler_locked(d->irq, handle_level_irq);
343 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
344 __irq_set_handler_locked(d->irq, handle_edge_irq);
345
346 return retval;
347}
348
349static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
350{
351 void __iomem *reg = bank->base;
352
353 reg += bank->regs->irqstatus;
354 __raw_writel(gpio_mask, reg);
355
356 /* Workaround for clearing DSP GPIO interrupts to allow retention */
357 if (bank->regs->irqstatus2) {
358 reg = bank->base + bank->regs->irqstatus2;
359 __raw_writel(gpio_mask, reg);
360 }
361
362 /* Flush posted write for the irq status to avoid spurious interrupts */
363 __raw_readl(reg);
364}
365
366static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
367{
368 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
369}
370
371static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
372{
373 void __iomem *reg = bank->base;
374 u32 l;
375 u32 mask = (1 << bank->width) - 1;
376
377 reg += bank->regs->irqenable;
378 l = __raw_readl(reg);
379 if (bank->regs->irqenable_inv)
380 l = ~l;
381 l &= mask;
382 return l;
383}
384
385static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
386{
387 void __iomem *reg = bank->base;
388 u32 l;
389
390 if (bank->regs->set_irqenable) {
391 reg += bank->regs->set_irqenable;
392 l = gpio_mask;
393 } else {
394 reg += bank->regs->irqenable;
395 l = __raw_readl(reg);
396 if (bank->regs->irqenable_inv)
397 l &= ~gpio_mask;
398 else
399 l |= gpio_mask;
400 }
401
402 __raw_writel(l, reg);
403}
404
405static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
406{
407 void __iomem *reg = bank->base;
408 u32 l;
409
410 if (bank->regs->clr_irqenable) {
411 reg += bank->regs->clr_irqenable;
412 l = gpio_mask;
413 } else {
414 reg += bank->regs->irqenable;
415 l = __raw_readl(reg);
416 if (bank->regs->irqenable_inv)
417 l |= gpio_mask;
418 else
419 l &= ~gpio_mask;
420 }
421
422 __raw_writel(l, reg);
423}
424
425static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
426{
427 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
428}
429
430/*
431 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
432 * 1510 does not seem to have a wake-up register. If JTAG is connected
433 * to the target, system will wake up always on GPIO events. While
434 * system is running all registered GPIO interrupts need to have wake-up
435 * enabled. When system is suspended, only selected GPIO interrupts need
436 * to have wake-up enabled.
437 */
438static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
439{
440 u32 gpio_bit = GPIO_BIT(bank, gpio);
441 unsigned long flags;
442
443 if (bank->non_wakeup_gpios & gpio_bit) {
444 dev_err(bank->dev,
445 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
446 return -EINVAL;
447 }
448
449 spin_lock_irqsave(&bank->lock, flags);
450 if (enable)
451 bank->suspend_wakeup |= gpio_bit;
452 else
453 bank->suspend_wakeup &= ~gpio_bit;
454
455 spin_unlock_irqrestore(&bank->lock, flags);
456
457 return 0;
458}
459
460static void _reset_gpio(struct gpio_bank *bank, int gpio)
461{
462 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
463 _set_gpio_irqenable(bank, gpio, 0);
464 _clear_gpio_irqstatus(bank, gpio);
465 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
466}
467
468/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
469static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
470{
471 unsigned int gpio = d->irq - IH_GPIO_BASE;
472 struct gpio_bank *bank;
473 int retval;
474
475 bank = irq_data_get_irq_chip_data(d);
476 retval = _set_gpio_wakeup(bank, gpio, enable);
477
478 return retval;
479}
480
481static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
482{
483 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
484 unsigned long flags;
485
486 spin_lock_irqsave(&bank->lock, flags);
487
488 /* Set trigger to none. You need to enable the desired trigger with
489 * request_irq() or set_irq_type().
490 */
491 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
492
493#ifdef CONFIG_ARCH_OMAP15XX
494 if (bank->method == METHOD_GPIO_1510) {
495 void __iomem *reg;
496
497 /* Claim the pin for MPU */
498 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
499 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
500 }
501#endif
502 if (bank->regs->ctrl && !bank->mod_usage) {
503 void __iomem *reg = bank->base + bank->regs->ctrl;
504 u32 ctrl;
505
506 ctrl = __raw_readl(reg);
507 /* Module is enabled, clocks are not gated */
508 ctrl &= ~GPIO_MOD_CTRL_BIT;
509 __raw_writel(ctrl, reg);
510 }
511
512 bank->mod_usage |= 1 << offset;
513
514 spin_unlock_irqrestore(&bank->lock, flags);
515
516 return 0;
517}
518
519static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
520{
521 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
522 void __iomem *base = bank->base;
523 unsigned long flags;
524
525 spin_lock_irqsave(&bank->lock, flags);
526
527 if (bank->regs->wkup_en)
528 /* Disable wake-up during idle for dynamic tick */
529 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
530
531 bank->mod_usage &= ~(1 << offset);
532
533 if (bank->regs->ctrl && !bank->mod_usage) {
534 void __iomem *reg = bank->base + bank->regs->ctrl;
535 u32 ctrl;
536
537 ctrl = __raw_readl(reg);
538 /* Module is disabled, clocks are gated */
539 ctrl |= GPIO_MOD_CTRL_BIT;
540 __raw_writel(ctrl, reg);
541 }
542
543 _reset_gpio(bank, bank->chip.base + offset);
544 spin_unlock_irqrestore(&bank->lock, flags);
545}
546
547/*
548 * We need to unmask the GPIO bank interrupt as soon as possible to
549 * avoid missing GPIO interrupts for other lines in the bank.
550 * Then we need to mask-read-clear-unmask the triggered GPIO lines
551 * in the bank to avoid missing nested interrupts for a GPIO line.
552 * If we wait to unmask individual GPIO lines in the bank after the
553 * line's interrupt handler has been run, we may miss some nested
554 * interrupts.
555 */
556static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
557{
558 void __iomem *isr_reg = NULL;
559 u32 isr;
560 unsigned int gpio_irq, gpio_index;
561 struct gpio_bank *bank;
562 u32 retrigger = 0;
563 int unmasked = 0;
564 struct irq_chip *chip = irq_desc_get_chip(desc);
565
566 chained_irq_enter(chip, desc);
567
568 bank = irq_get_handler_data(irq);
569 isr_reg = bank->base + bank->regs->irqstatus;
570
571 if (WARN_ON(!isr_reg))
572 goto exit;
573
574 while(1) {
575 u32 isr_saved, level_mask = 0;
576 u32 enabled;
577
578 enabled = _get_gpio_irqbank_mask(bank);
579 isr_saved = isr = __raw_readl(isr_reg) & enabled;
580
581 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
582 isr &= 0x0000ffff;
583
584 if (bank->level_mask)
585 level_mask = bank->level_mask & enabled;
586
587 /* clear edge sensitive interrupts before handler(s) are
588 called so that we don't miss any interrupt occurred while
589 executing them */
590 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
591 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
592 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
593
594 /* if there is only edge sensitive GPIO pin interrupts
595 configured, we could unmask GPIO bank interrupt immediately */
596 if (!level_mask && !unmasked) {
597 unmasked = 1;
598 chained_irq_exit(chip, desc);
599 }
600
601 isr |= retrigger;
602 retrigger = 0;
603 if (!isr)
604 break;
605
606 gpio_irq = bank->virtual_irq_start;
607 for (; isr != 0; isr >>= 1, gpio_irq++) {
608 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
609
610 if (!(isr & 1))
611 continue;
612
613 /*
614 * Some chips can't respond to both rising and falling
615 * at the same time. If this irq was requested with
616 * both flags, we need to flip the ICR data for the IRQ
617 * to respond to the IRQ for the opposite direction.
618 * This will be indicated in the bank toggle_mask.
619 */
620 if (bank->toggle_mask & (1 << gpio_index))
621 _toggle_gpio_edge_triggering(bank, gpio_index);
622
623 generic_handle_irq(gpio_irq);
624 }
625 }
626 /* if bank has any level sensitive GPIO pin interrupt
627 configured, we must unmask the bank interrupt only after
628 handler(s) are executed in order to avoid spurious bank
629 interrupt */
630exit:
631 if (!unmasked)
632 chained_irq_exit(chip, desc);
633}
634
635static void gpio_irq_shutdown(struct irq_data *d)
636{
637 unsigned int gpio = d->irq - IH_GPIO_BASE;
638 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
639 unsigned long flags;
640
641 spin_lock_irqsave(&bank->lock, flags);
642 _reset_gpio(bank, gpio);
643 spin_unlock_irqrestore(&bank->lock, flags);
644}
645
646static void gpio_ack_irq(struct irq_data *d)
647{
648 unsigned int gpio = d->irq - IH_GPIO_BASE;
649 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
650
651 _clear_gpio_irqstatus(bank, gpio);
652}
653
654static void gpio_mask_irq(struct irq_data *d)
655{
656 unsigned int gpio = d->irq - IH_GPIO_BASE;
657 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
658 unsigned long flags;
659
660 spin_lock_irqsave(&bank->lock, flags);
661 _set_gpio_irqenable(bank, gpio, 0);
662 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
663 spin_unlock_irqrestore(&bank->lock, flags);
664}
665
666static void gpio_unmask_irq(struct irq_data *d)
667{
668 unsigned int gpio = d->irq - IH_GPIO_BASE;
669 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
670 unsigned int irq_mask = GPIO_BIT(bank, gpio);
671 u32 trigger = irqd_get_trigger_type(d);
672 unsigned long flags;
673
674 spin_lock_irqsave(&bank->lock, flags);
675 if (trigger)
676 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
677
678 /* For level-triggered GPIOs, the clearing must be done after
679 * the HW source is cleared, thus after the handler has run */
680 if (bank->level_mask & irq_mask) {
681 _set_gpio_irqenable(bank, gpio, 0);
682 _clear_gpio_irqstatus(bank, gpio);
683 }
684
685 _set_gpio_irqenable(bank, gpio, 1);
686 spin_unlock_irqrestore(&bank->lock, flags);
687}
688
689static struct irq_chip gpio_irq_chip = {
690 .name = "GPIO",
691 .irq_shutdown = gpio_irq_shutdown,
692 .irq_ack = gpio_ack_irq,
693 .irq_mask = gpio_mask_irq,
694 .irq_unmask = gpio_unmask_irq,
695 .irq_set_type = gpio_irq_type,
696 .irq_set_wake = gpio_wake_enable,
697};
698
699/*---------------------------------------------------------------------*/
700
701#ifdef CONFIG_ARCH_OMAP1
702
703#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
704
705#ifdef CONFIG_ARCH_OMAP16XX
706
707#include <linux/platform_device.h>
708
709static int omap_mpuio_suspend_noirq(struct device *dev)
710{
711 struct platform_device *pdev = to_platform_device(dev);
712 struct gpio_bank *bank = platform_get_drvdata(pdev);
713 void __iomem *mask_reg = bank->base +
714 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
715 unsigned long flags;
716
717 spin_lock_irqsave(&bank->lock, flags);
718 bank->saved_wakeup = __raw_readl(mask_reg);
719 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
720 spin_unlock_irqrestore(&bank->lock, flags);
721
722 return 0;
723}
724
725static int omap_mpuio_resume_noirq(struct device *dev)
726{
727 struct platform_device *pdev = to_platform_device(dev);
728 struct gpio_bank *bank = platform_get_drvdata(pdev);
729 void __iomem *mask_reg = bank->base +
730 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
731 unsigned long flags;
732
733 spin_lock_irqsave(&bank->lock, flags);
734 __raw_writel(bank->saved_wakeup, mask_reg);
735 spin_unlock_irqrestore(&bank->lock, flags);
736
737 return 0;
738}
739
740static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
741 .suspend_noirq = omap_mpuio_suspend_noirq,
742 .resume_noirq = omap_mpuio_resume_noirq,
743};
744
745/* use platform_driver for this. */
746static struct platform_driver omap_mpuio_driver = {
747 .driver = {
748 .name = "mpuio",
749 .pm = &omap_mpuio_dev_pm_ops,
750 },
751};
752
753static struct platform_device omap_mpuio_device = {
754 .name = "mpuio",
755 .id = -1,
756 .dev = {
757 .driver = &omap_mpuio_driver.driver,
758 }
759 /* could list the /proc/iomem resources */
760};
761
762static inline void mpuio_init(struct gpio_bank *bank)
763{
764 platform_set_drvdata(&omap_mpuio_device, bank);
765
766 if (platform_driver_register(&omap_mpuio_driver) == 0)
767 (void) platform_device_register(&omap_mpuio_device);
768}
769
770#else
771static inline void mpuio_init(struct gpio_bank *bank) {}
772#endif /* 16xx */
773
774#else
775
776#define bank_is_mpuio(bank) 0
777static inline void mpuio_init(struct gpio_bank *bank) {}
778
779#endif
780
781/*---------------------------------------------------------------------*/
782
783/* REVISIT these are stupid implementations! replace by ones that
784 * don't switch on METHOD_* and which mostly avoid spinlocks
785 */
786
787static int gpio_input(struct gpio_chip *chip, unsigned offset)
788{
789 struct gpio_bank *bank;
790 unsigned long flags;
791
792 bank = container_of(chip, struct gpio_bank, chip);
793 spin_lock_irqsave(&bank->lock, flags);
794 _set_gpio_direction(bank, offset, 1);
795 spin_unlock_irqrestore(&bank->lock, flags);
796 return 0;
797}
798
799static int gpio_is_input(struct gpio_bank *bank, int mask)
800{
801 void __iomem *reg = bank->base + bank->regs->direction;
802
803 return __raw_readl(reg) & mask;
804}
805
806static int gpio_get(struct gpio_chip *chip, unsigned offset)
807{
808 struct gpio_bank *bank;
809 void __iomem *reg;
810 int gpio;
811 u32 mask;
812
813 gpio = chip->base + offset;
814 bank = container_of(chip, struct gpio_bank, chip);
815 reg = bank->base;
816 mask = GPIO_BIT(bank, gpio);
817
818 if (gpio_is_input(bank, mask))
819 return _get_gpio_datain(bank, gpio);
820 else
821 return _get_gpio_dataout(bank, gpio);
822}
823
824static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
825{
826 struct gpio_bank *bank;
827 unsigned long flags;
828
829 bank = container_of(chip, struct gpio_bank, chip);
830 spin_lock_irqsave(&bank->lock, flags);
831 bank->set_dataout(bank, offset, value);
832 _set_gpio_direction(bank, offset, 0);
833 spin_unlock_irqrestore(&bank->lock, flags);
834 return 0;
835}
836
837static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
838 unsigned debounce)
839{
840 struct gpio_bank *bank;
841 unsigned long flags;
842
843 bank = container_of(chip, struct gpio_bank, chip);
844
845 if (!bank->dbck) {
846 bank->dbck = clk_get(bank->dev, "dbclk");
847 if (IS_ERR(bank->dbck))
848 dev_err(bank->dev, "Could not get gpio dbck\n");
849 }
850
851 spin_lock_irqsave(&bank->lock, flags);
852 _set_gpio_debounce(bank, offset, debounce);
853 spin_unlock_irqrestore(&bank->lock, flags);
854
855 return 0;
856}
857
858static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
859{
860 struct gpio_bank *bank;
861 unsigned long flags;
862
863 bank = container_of(chip, struct gpio_bank, chip);
864 spin_lock_irqsave(&bank->lock, flags);
865 bank->set_dataout(bank, offset, value);
866 spin_unlock_irqrestore(&bank->lock, flags);
867}
868
869static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
870{
871 struct gpio_bank *bank;
872
873 bank = container_of(chip, struct gpio_bank, chip);
874 return bank->virtual_irq_start + offset;
875}
876
877/*---------------------------------------------------------------------*/
878
879static void __init omap_gpio_show_rev(struct gpio_bank *bank)
880{
881 static bool called;
882 u32 rev;
883
884 if (called || bank->regs->revision == USHRT_MAX)
885 return;
886
887 rev = __raw_readw(bank->base + bank->regs->revision);
888 pr_info("OMAP GPIO hardware version %d.%d\n",
889 (rev >> 4) & 0x0f, rev & 0x0f);
890
891 called = true;
892}
893
894/* This lock class tells lockdep that GPIO irqs are in a different
895 * category than their parents, so it won't report false recursion.
896 */
897static struct lock_class_key gpio_lock_class;
898
899static void omap_gpio_mod_init(struct gpio_bank *bank)
900{
901 void __iomem *base = bank->base;
902 u32 l = 0xffffffff;
903
904 if (bank->width == 16)
905 l = 0xffff;
906
907 if (bank_is_mpuio(bank)) {
908 __raw_writel(l, bank->base + bank->regs->irqenable);
909 return;
910 }
911
912 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
913 _gpio_rmw(base, bank->regs->irqstatus, l,
914 bank->regs->irqenable_inv == false);
915 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
916 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
917 if (bank->regs->debounce_en)
918 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
919
920 /* Initialize interface clk ungated, module enabled */
921 if (bank->regs->ctrl)
922 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
923}
924
925static __init void
926omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
927 unsigned int num)
928{
929 struct irq_chip_generic *gc;
930 struct irq_chip_type *ct;
931
932 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
933 handle_simple_irq);
934 if (!gc) {
935 dev_err(bank->dev, "Memory alloc failed for gc\n");
936 return;
937 }
938
939 ct = gc->chip_types;
940
941 /* NOTE: No ack required, reading IRQ status clears it. */
942 ct->chip.irq_mask = irq_gc_mask_set_bit;
943 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
944 ct->chip.irq_set_type = gpio_irq_type;
945
946 if (bank->regs->wkup_en)
947 ct->chip.irq_set_wake = gpio_wake_enable,
948
949 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
950 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
951 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
952}
953
954static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
955{
956 int j;
957 static int gpio;
958
959 bank->mod_usage = 0;
960 /*
961 * REVISIT eventually switch from OMAP-specific gpio structs
962 * over to the generic ones
963 */
964 bank->chip.request = omap_gpio_request;
965 bank->chip.free = omap_gpio_free;
966 bank->chip.direction_input = gpio_input;
967 bank->chip.get = gpio_get;
968 bank->chip.direction_output = gpio_output;
969 bank->chip.set_debounce = gpio_debounce;
970 bank->chip.set = gpio_set;
971 bank->chip.to_irq = gpio_2irq;
972 if (bank_is_mpuio(bank)) {
973 bank->chip.label = "mpuio";
974#ifdef CONFIG_ARCH_OMAP16XX
975 if (bank->regs->wkup_en)
976 bank->chip.dev = &omap_mpuio_device.dev;
977#endif
978 bank->chip.base = OMAP_MPUIO(0);
979 } else {
980 bank->chip.label = "gpio";
981 bank->chip.base = gpio;
982 gpio += bank->width;
983 }
984 bank->chip.ngpio = bank->width;
985
986 gpiochip_add(&bank->chip);
987
988 for (j = bank->virtual_irq_start;
989 j < bank->virtual_irq_start + bank->width; j++) {
990 irq_set_lockdep_class(j, &gpio_lock_class);
991 irq_set_chip_data(j, bank);
992 if (bank_is_mpuio(bank)) {
993 omap_mpuio_alloc_gc(bank, j, bank->width);
994 } else {
995 irq_set_chip(j, &gpio_irq_chip);
996 irq_set_handler(j, handle_simple_irq);
997 set_irq_flags(j, IRQF_VALID);
998 }
999 }
1000 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1001 irq_set_handler_data(bank->irq, bank);
1002}
1003
1004static int __devinit omap_gpio_probe(struct platform_device *pdev)
1005{
1006 struct omap_gpio_platform_data *pdata;
1007 struct resource *res;
1008 struct gpio_bank *bank;
1009 int ret = 0;
1010
1011 if (!pdev->dev.platform_data) {
1012 ret = -EINVAL;
1013 goto err_exit;
1014 }
1015
1016 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
1017 if (!bank) {
1018 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1019 ret = -ENOMEM;
1020 goto err_exit;
1021 }
1022
1023 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1024 if (unlikely(!res)) {
1025 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
1026 pdev->id);
1027 ret = -ENODEV;
1028 goto err_free;
1029 }
1030
1031 bank->irq = res->start;
1032 bank->id = pdev->id;
1033
1034 pdata = pdev->dev.platform_data;
1035 bank->virtual_irq_start = pdata->virtual_irq_start;
1036 bank->method = pdata->bank_type;
1037 bank->dev = &pdev->dev;
1038 bank->dbck_flag = pdata->dbck_flag;
1039 bank->stride = pdata->bank_stride;
1040 bank->width = pdata->bank_width;
1041 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1042 bank->loses_context = pdata->loses_context;
1043 bank->get_context_loss_count = pdata->get_context_loss_count;
1044 bank->regs = pdata->regs;
1045
1046 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1047 bank->set_dataout = _set_gpio_dataout_reg;
1048 else
1049 bank->set_dataout = _set_gpio_dataout_mask;
1050
1051 spin_lock_init(&bank->lock);
1052
1053 /* Static mapping, never released */
1054 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1055 if (unlikely(!res)) {
1056 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1057 pdev->id);
1058 ret = -ENODEV;
1059 goto err_free;
1060 }
1061
1062 bank->base = ioremap(res->start, resource_size(res));
1063 if (!bank->base) {
1064 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1065 pdev->id);
1066 ret = -ENOMEM;
1067 goto err_free;
1068 }
1069
1070 pm_runtime_enable(bank->dev);
1071 pm_runtime_get_sync(bank->dev);
1072
1073 if (bank_is_mpuio(bank))
1074 mpuio_init(bank);
1075
1076 omap_gpio_mod_init(bank);
1077 omap_gpio_chip_init(bank);
1078 omap_gpio_show_rev(bank);
1079
1080 list_add_tail(&bank->node, &omap_gpio_list);
1081
1082 return ret;
1083
1084err_free:
1085 kfree(bank);
1086err_exit:
1087 return ret;
1088}
1089
1090static int omap_gpio_suspend(void)
1091{
1092 struct gpio_bank *bank;
1093
1094 list_for_each_entry(bank, &omap_gpio_list, node) {
1095 void __iomem *base = bank->base;
1096 void __iomem *wake_status;
1097 unsigned long flags;
1098
1099 if (!bank->regs->wkup_en)
1100 return 0;
1101
1102 wake_status = bank->base + bank->regs->wkup_en;
1103
1104 spin_lock_irqsave(&bank->lock, flags);
1105 bank->saved_wakeup = __raw_readl(wake_status);
1106 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1107 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1108 spin_unlock_irqrestore(&bank->lock, flags);
1109 }
1110
1111 return 0;
1112}
1113
1114static void omap_gpio_resume(void)
1115{
1116 struct gpio_bank *bank;
1117
1118 list_for_each_entry(bank, &omap_gpio_list, node) {
1119 void __iomem *base = bank->base;
1120 unsigned long flags;
1121
1122 if (!bank->regs->wkup_en)
1123 return;
1124
1125 spin_lock_irqsave(&bank->lock, flags);
1126 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1127 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1128 spin_unlock_irqrestore(&bank->lock, flags);
1129 }
1130}
1131
1132static struct syscore_ops omap_gpio_syscore_ops = {
1133 .suspend = omap_gpio_suspend,
1134 .resume = omap_gpio_resume,
1135};
1136
1137#ifdef CONFIG_ARCH_OMAP2PLUS
1138
1139static void omap_gpio_save_context(struct gpio_bank *bank);
1140static void omap_gpio_restore_context(struct gpio_bank *bank);
1141
1142void omap2_gpio_prepare_for_idle(int off_mode)
1143{
1144 struct gpio_bank *bank;
1145
1146 list_for_each_entry(bank, &omap_gpio_list, node) {
1147 u32 l1 = 0, l2 = 0;
1148 int j;
1149
1150 if (!bank->loses_context)
1151 continue;
1152
1153 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1154 clk_disable(bank->dbck);
1155
1156 if (!off_mode)
1157 continue;
1158
1159 /* If going to OFF, remove triggering for all
1160 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1161 * generated. See OMAP2420 Errata item 1.101. */
1162 if (!(bank->enabled_non_wakeup_gpios))
1163 goto save_gpio_context;
1164
1165 bank->saved_datain = __raw_readl(bank->base +
1166 bank->regs->datain);
1167 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1168 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1169
1170 bank->saved_fallingdetect = l1;
1171 bank->saved_risingdetect = l2;
1172 l1 &= ~bank->enabled_non_wakeup_gpios;
1173 l2 &= ~bank->enabled_non_wakeup_gpios;
1174
1175 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1176 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1177
1178save_gpio_context:
1179 if (bank->get_context_loss_count)
1180 bank->context_loss_count =
1181 bank->get_context_loss_count(bank->dev);
1182
1183 omap_gpio_save_context(bank);
1184 }
1185}
1186
1187void omap2_gpio_resume_after_idle(void)
1188{
1189 struct gpio_bank *bank;
1190
1191 list_for_each_entry(bank, &omap_gpio_list, node) {
1192 int context_lost_cnt_after;
1193 u32 l = 0, gen, gen0, gen1;
1194 int j;
1195
1196 if (!bank->loses_context)
1197 continue;
1198
1199 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1200 clk_enable(bank->dbck);
1201
1202 if (bank->get_context_loss_count) {
1203 context_lost_cnt_after =
1204 bank->get_context_loss_count(bank->dev);
1205 if (context_lost_cnt_after != bank->context_loss_count
1206 || !context_lost_cnt_after)
1207 omap_gpio_restore_context(bank);
1208 }
1209
1210 if (!(bank->enabled_non_wakeup_gpios))
1211 continue;
1212
1213 __raw_writel(bank->saved_fallingdetect,
1214 bank->base + bank->regs->fallingdetect);
1215 __raw_writel(bank->saved_risingdetect,
1216 bank->base + bank->regs->risingdetect);
1217 l = __raw_readl(bank->base + bank->regs->datain);
1218
1219 /* Check if any of the non-wakeup interrupt GPIOs have changed
1220 * state. If so, generate an IRQ by software. This is
1221 * horribly racy, but it's the best we can do to work around
1222 * this silicon bug. */
1223 l ^= bank->saved_datain;
1224 l &= bank->enabled_non_wakeup_gpios;
1225
1226 /*
1227 * No need to generate IRQs for the rising edge for gpio IRQs
1228 * configured with falling edge only; and vice versa.
1229 */
1230 gen0 = l & bank->saved_fallingdetect;
1231 gen0 &= bank->saved_datain;
1232
1233 gen1 = l & bank->saved_risingdetect;
1234 gen1 &= ~(bank->saved_datain);
1235
1236 /* FIXME: Consider GPIO IRQs with level detections properly! */
1237 gen = l & (~(bank->saved_fallingdetect) &
1238 ~(bank->saved_risingdetect));
1239 /* Consider all GPIO IRQs needed to be updated */
1240 gen |= gen0 | gen1;
1241
1242 if (gen) {
1243 u32 old0, old1;
1244
1245 old0 = __raw_readl(bank->base +
1246 bank->regs->leveldetect0);
1247 old1 = __raw_readl(bank->base +
1248 bank->regs->leveldetect1);
1249
1250 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1251 old0 |= gen;
1252 old1 |= gen;
1253 }
1254
1255 if (cpu_is_omap44xx()) {
1256 old0 |= l;
1257 old1 |= l;
1258 }
1259 __raw_writel(old0, bank->base +
1260 bank->regs->leveldetect0);
1261 __raw_writel(old1, bank->base +
1262 bank->regs->leveldetect1);
1263 }
1264 }
1265}
1266
1267static void omap_gpio_save_context(struct gpio_bank *bank)
1268{
1269 bank->context.irqenable1 =
1270 __raw_readl(bank->base + bank->regs->irqenable);
1271 bank->context.irqenable2 =
1272 __raw_readl(bank->base + bank->regs->irqenable2);
1273 bank->context.wake_en =
1274 __raw_readl(bank->base + bank->regs->wkup_en);
1275 bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl);
1276 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
1277 bank->context.leveldetect0 =
1278 __raw_readl(bank->base + bank->regs->leveldetect0);
1279 bank->context.leveldetect1 =
1280 __raw_readl(bank->base + bank->regs->leveldetect1);
1281 bank->context.risingdetect =
1282 __raw_readl(bank->base + bank->regs->risingdetect);
1283 bank->context.fallingdetect =
1284 __raw_readl(bank->base + bank->regs->fallingdetect);
1285 bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout);
1286}
1287
1288static void omap_gpio_restore_context(struct gpio_bank *bank)
1289{
1290 __raw_writel(bank->context.irqenable1,
1291 bank->base + bank->regs->irqenable);
1292 __raw_writel(bank->context.irqenable2,
1293 bank->base + bank->regs->irqenable2);
1294 __raw_writel(bank->context.wake_en,
1295 bank->base + bank->regs->wkup_en);
1296 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1297 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1298 __raw_writel(bank->context.leveldetect0,
1299 bank->base + bank->regs->leveldetect0);
1300 __raw_writel(bank->context.leveldetect1,
1301 bank->base + bank->regs->leveldetect1);
1302 __raw_writel(bank->context.risingdetect,
1303 bank->base + bank->regs->risingdetect);
1304 __raw_writel(bank->context.fallingdetect,
1305 bank->base + bank->regs->fallingdetect);
1306 __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
1307}
1308#endif
1309
1310static struct platform_driver omap_gpio_driver = {
1311 .probe = omap_gpio_probe,
1312 .driver = {
1313 .name = "omap_gpio",
1314 },
1315};
1316
1317/*
1318 * gpio driver register needs to be done before
1319 * machine_init functions access gpio APIs.
1320 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1321 */
1322static int __init omap_gpio_drv_reg(void)
1323{
1324 return platform_driver_register(&omap_gpio_driver);
1325}
1326postcore_initcall(omap_gpio_drv_reg);
1327
1328static int __init omap_gpio_sysinit(void)
1329{
1330
1331#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1332 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1333 register_syscore_ops(&omap_gpio_syscore_ops);
1334#endif
1335
1336 return 0;
1337}
1338
1339arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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