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gpio: omap: fix omap2_set_gpio_debounce
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
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1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/gpio.h>
28#include <linux/bitops.h>
29#include <linux/platform_data/gpio-omap.h>
30
31#define OFF_MODE 1
32#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34static LIST_HEAD(omap_gpio_list);
35
36struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49};
50
51struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 u16 irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 struct gpio_chip chip;
63 struct clk *dbck;
64 u32 mod_usage;
65 u32 irq_usage;
66 u32 dbck_enable_mask;
67 bool dbck_enabled;
68 struct device *dev;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
81
82 struct omap_gpio_reg_offs *regs;
83};
84
85#define GPIO_MOD_CTRL_BIT BIT(0)
86
87#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88#define LINE_USED(line, offset) (line & (BIT(offset)))
89
90static void omap_gpio_unmask_irq(struct irq_data *d);
91
92static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93{
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return container_of(chip, struct gpio_bank, chip);
96}
97
98static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
100{
101 void __iomem *reg = bank->base;
102 u32 l;
103
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
106 if (is_input)
107 l |= BIT(gpio);
108 else
109 l &= ~(BIT(gpio));
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
112}
113
114
115/* set data out value using dedicate set/clear register */
116static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118{
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131}
132
133/* set data out value using mask register */
134static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136{
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
139 u32 l;
140
141 l = readl_relaxed(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
148}
149
150static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151{
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
155}
156
157static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158{
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
162}
163
164static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165{
166 int l = readl_relaxed(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 writel_relaxed(l, base + reg);
174}
175
176static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177{
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_prepare_enable(bank->dbck);
180 bank->dbck_enabled = true;
181
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
184 }
185}
186
187static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188{
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
196
197 clk_disable_unprepare(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200}
201
202/**
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
211 */
212static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
213 unsigned debounce)
214{
215 void __iomem *reg;
216 u32 val;
217 u32 l;
218 bool enable = !!debounce;
219
220 if (!bank->dbck_flag)
221 return;
222
223 if (enable) {
224 debounce = DIV_ROUND_UP(debounce, 31) - 1;
225 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
226 }
227
228 l = BIT(offset);
229
230 clk_prepare_enable(bank->dbck);
231 reg = bank->base + bank->regs->debounce;
232 writel_relaxed(debounce, reg);
233
234 reg = bank->base + bank->regs->debounce_en;
235 val = readl_relaxed(reg);
236
237 if (enable)
238 val |= l;
239 else
240 val &= ~l;
241 bank->dbck_enable_mask = val;
242
243 writel_relaxed(val, reg);
244 clk_disable_unprepare(bank->dbck);
245 /*
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
252 */
253 omap_gpio_dbck_enable(bank);
254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
257 }
258}
259
260/**
261 * omap_clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @offset: the gpio number on this @bank
264 *
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
269 */
270static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
271{
272 u32 gpio_bit = BIT(offset);
273
274 if (!bank->dbck_flag)
275 return;
276
277 if (!(bank->dbck_enable_mask & gpio_bit))
278 return;
279
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 writel_relaxed(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
284
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 writel_relaxed(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable_unprepare(bank->dbck);
290 bank->dbck_enabled = false;
291 }
292}
293
294static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
295 unsigned trigger)
296{
297 void __iomem *base = bank->base;
298 u32 gpio_bit = BIT(gpio);
299
300 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
308
309 bank->context.leveldetect0 =
310 readl_relaxed(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 readl_relaxed(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 readl_relaxed(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 readl_relaxed(bank->base + bank->regs->fallingdetect);
317
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 bank->context.wake_en =
321 readl_relaxed(bank->base + bank->regs->wkup_en);
322 }
323
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
329 goto exit;
330 }
331
332 /*
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 */
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
339 bank->enabled_non_wakeup_gpios |= gpio_bit;
340 else
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
342 }
343
344exit:
345 bank->level_mask =
346 readl_relaxed(bank->base + bank->regs->leveldetect0) |
347 readl_relaxed(bank->base + bank->regs->leveldetect1);
348}
349
350#ifdef CONFIG_ARCH_OMAP1
351/*
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
354 */
355static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
356{
357 void __iomem *reg = bank->base;
358 u32 l = 0;
359
360 if (!bank->regs->irqctrl)
361 return;
362
363 reg += bank->regs->irqctrl;
364
365 l = readl_relaxed(reg);
366 if ((l >> gpio) & 1)
367 l &= ~(BIT(gpio));
368 else
369 l |= BIT(gpio);
370
371 writel_relaxed(l, reg);
372}
373#else
374static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
375#endif
376
377static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
378 unsigned trigger)
379{
380 void __iomem *reg = bank->base;
381 void __iomem *base = bank->base;
382 u32 l = 0;
383
384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 omap_set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
388
389 l = readl_relaxed(reg);
390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 bank->toggle_mask |= BIT(gpio);
392 if (trigger & IRQ_TYPE_EDGE_RISING)
393 l |= BIT(gpio);
394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
395 l &= ~(BIT(gpio));
396 else
397 return -EINVAL;
398
399 writel_relaxed(l, reg);
400 } else if (bank->regs->edgectrl1) {
401 if (gpio & 0x08)
402 reg += bank->regs->edgectrl2;
403 else
404 reg += bank->regs->edgectrl1;
405
406 gpio &= 0x07;
407 l = readl_relaxed(reg);
408 l &= ~(3 << (gpio << 1));
409 if (trigger & IRQ_TYPE_EDGE_RISING)
410 l |= 2 << (gpio << 1);
411 if (trigger & IRQ_TYPE_EDGE_FALLING)
412 l |= BIT(gpio << 1);
413
414 /* Enable wake-up during idle for dynamic tick */
415 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
416 bank->context.wake_en =
417 readl_relaxed(bank->base + bank->regs->wkup_en);
418 writel_relaxed(l, reg);
419 }
420 return 0;
421}
422
423static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
424{
425 if (bank->regs->pinctrl) {
426 void __iomem *reg = bank->base + bank->regs->pinctrl;
427
428 /* Claim the pin for MPU */
429 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
430 }
431
432 if (bank->regs->ctrl && !BANK_USED(bank)) {
433 void __iomem *reg = bank->base + bank->regs->ctrl;
434 u32 ctrl;
435
436 ctrl = readl_relaxed(reg);
437 /* Module is enabled, clocks are not gated */
438 ctrl &= ~GPIO_MOD_CTRL_BIT;
439 writel_relaxed(ctrl, reg);
440 bank->context.ctrl = ctrl;
441 }
442}
443
444static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
445{
446 void __iomem *base = bank->base;
447
448 if (bank->regs->wkup_en &&
449 !LINE_USED(bank->mod_usage, offset) &&
450 !LINE_USED(bank->irq_usage, offset)) {
451 /* Disable wake-up during idle for dynamic tick */
452 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
453 bank->context.wake_en =
454 readl_relaxed(bank->base + bank->regs->wkup_en);
455 }
456
457 if (bank->regs->ctrl && !BANK_USED(bank)) {
458 void __iomem *reg = bank->base + bank->regs->ctrl;
459 u32 ctrl;
460
461 ctrl = readl_relaxed(reg);
462 /* Module is disabled, clocks are gated */
463 ctrl |= GPIO_MOD_CTRL_BIT;
464 writel_relaxed(ctrl, reg);
465 bank->context.ctrl = ctrl;
466 }
467}
468
469static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
470{
471 void __iomem *reg = bank->base + bank->regs->direction;
472
473 return readl_relaxed(reg) & BIT(offset);
474}
475
476static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
477{
478 if (!LINE_USED(bank->mod_usage, offset)) {
479 omap_enable_gpio_module(bank, offset);
480 omap_set_gpio_direction(bank, offset, 1);
481 }
482 bank->irq_usage |= BIT(offset);
483}
484
485static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
486{
487 struct gpio_bank *bank = omap_irq_data_get_bank(d);
488 int retval;
489 unsigned long flags;
490 unsigned offset = d->hwirq;
491
492 if (type & ~IRQ_TYPE_SENSE_MASK)
493 return -EINVAL;
494
495 if (!bank->regs->leveldetect0 &&
496 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
497 return -EINVAL;
498
499 if (!BANK_USED(bank))
500 pm_runtime_get_sync(bank->dev);
501
502 raw_spin_lock_irqsave(&bank->lock, flags);
503 retval = omap_set_gpio_triggering(bank, offset, type);
504 if (retval) {
505 raw_spin_unlock_irqrestore(&bank->lock, flags);
506 goto error;
507 }
508 omap_gpio_init_irq(bank, offset);
509 if (!omap_gpio_is_input(bank, offset)) {
510 raw_spin_unlock_irqrestore(&bank->lock, flags);
511 retval = -EINVAL;
512 goto error;
513 }
514 raw_spin_unlock_irqrestore(&bank->lock, flags);
515
516 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
517 irq_set_handler_locked(d, handle_level_irq);
518 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
519 irq_set_handler_locked(d, handle_edge_irq);
520
521 return 0;
522
523error:
524 if (!BANK_USED(bank))
525 pm_runtime_put(bank->dev);
526 return retval;
527}
528
529static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
530{
531 void __iomem *reg = bank->base;
532
533 reg += bank->regs->irqstatus;
534 writel_relaxed(gpio_mask, reg);
535
536 /* Workaround for clearing DSP GPIO interrupts to allow retention */
537 if (bank->regs->irqstatus2) {
538 reg = bank->base + bank->regs->irqstatus2;
539 writel_relaxed(gpio_mask, reg);
540 }
541
542 /* Flush posted write for the irq status to avoid spurious interrupts */
543 readl_relaxed(reg);
544}
545
546static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
547 unsigned offset)
548{
549 omap_clear_gpio_irqbank(bank, BIT(offset));
550}
551
552static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
553{
554 void __iomem *reg = bank->base;
555 u32 l;
556 u32 mask = (BIT(bank->width)) - 1;
557
558 reg += bank->regs->irqenable;
559 l = readl_relaxed(reg);
560 if (bank->regs->irqenable_inv)
561 l = ~l;
562 l &= mask;
563 return l;
564}
565
566static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
567{
568 void __iomem *reg = bank->base;
569 u32 l;
570
571 if (bank->regs->set_irqenable) {
572 reg += bank->regs->set_irqenable;
573 l = gpio_mask;
574 bank->context.irqenable1 |= gpio_mask;
575 } else {
576 reg += bank->regs->irqenable;
577 l = readl_relaxed(reg);
578 if (bank->regs->irqenable_inv)
579 l &= ~gpio_mask;
580 else
581 l |= gpio_mask;
582 bank->context.irqenable1 = l;
583 }
584
585 writel_relaxed(l, reg);
586}
587
588static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
589{
590 void __iomem *reg = bank->base;
591 u32 l;
592
593 if (bank->regs->clr_irqenable) {
594 reg += bank->regs->clr_irqenable;
595 l = gpio_mask;
596 bank->context.irqenable1 &= ~gpio_mask;
597 } else {
598 reg += bank->regs->irqenable;
599 l = readl_relaxed(reg);
600 if (bank->regs->irqenable_inv)
601 l |= gpio_mask;
602 else
603 l &= ~gpio_mask;
604 bank->context.irqenable1 = l;
605 }
606
607 writel_relaxed(l, reg);
608}
609
610static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
611 unsigned offset, int enable)
612{
613 if (enable)
614 omap_enable_gpio_irqbank(bank, BIT(offset));
615 else
616 omap_disable_gpio_irqbank(bank, BIT(offset));
617}
618
619/*
620 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
621 * 1510 does not seem to have a wake-up register. If JTAG is connected
622 * to the target, system will wake up always on GPIO events. While
623 * system is running all registered GPIO interrupts need to have wake-up
624 * enabled. When system is suspended, only selected GPIO interrupts need
625 * to have wake-up enabled.
626 */
627static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
628 int enable)
629{
630 u32 gpio_bit = BIT(offset);
631 unsigned long flags;
632
633 if (bank->non_wakeup_gpios & gpio_bit) {
634 dev_err(bank->dev,
635 "Unable to modify wakeup on non-wakeup GPIO%d\n",
636 offset);
637 return -EINVAL;
638 }
639
640 raw_spin_lock_irqsave(&bank->lock, flags);
641 if (enable)
642 bank->context.wake_en |= gpio_bit;
643 else
644 bank->context.wake_en &= ~gpio_bit;
645
646 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
647 raw_spin_unlock_irqrestore(&bank->lock, flags);
648
649 return 0;
650}
651
652/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
653static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
654{
655 struct gpio_bank *bank = omap_irq_data_get_bank(d);
656 unsigned offset = d->hwirq;
657
658 return omap_set_gpio_wakeup(bank, offset, enable);
659}
660
661static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
662{
663 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
664 unsigned long flags;
665
666 /*
667 * If this is the first gpio_request for the bank,
668 * enable the bank module.
669 */
670 if (!BANK_USED(bank))
671 pm_runtime_get_sync(bank->dev);
672
673 raw_spin_lock_irqsave(&bank->lock, flags);
674 omap_enable_gpio_module(bank, offset);
675 bank->mod_usage |= BIT(offset);
676 raw_spin_unlock_irqrestore(&bank->lock, flags);
677
678 return 0;
679}
680
681static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
682{
683 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
684 unsigned long flags;
685
686 raw_spin_lock_irqsave(&bank->lock, flags);
687 bank->mod_usage &= ~(BIT(offset));
688 if (!LINE_USED(bank->irq_usage, offset)) {
689 omap_set_gpio_direction(bank, offset, 1);
690 omap_clear_gpio_debounce(bank, offset);
691 }
692 omap_disable_gpio_module(bank, offset);
693 raw_spin_unlock_irqrestore(&bank->lock, flags);
694
695 /*
696 * If this is the last gpio to be freed in the bank,
697 * disable the bank module.
698 */
699 if (!BANK_USED(bank))
700 pm_runtime_put(bank->dev);
701}
702
703/*
704 * We need to unmask the GPIO bank interrupt as soon as possible to
705 * avoid missing GPIO interrupts for other lines in the bank.
706 * Then we need to mask-read-clear-unmask the triggered GPIO lines
707 * in the bank to avoid missing nested interrupts for a GPIO line.
708 * If we wait to unmask individual GPIO lines in the bank after the
709 * line's interrupt handler has been run, we may miss some nested
710 * interrupts.
711 */
712static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
713{
714 void __iomem *isr_reg = NULL;
715 u32 isr;
716 unsigned int bit;
717 struct gpio_bank *bank;
718 int unmasked = 0;
719 struct irq_chip *irqchip = irq_desc_get_chip(desc);
720 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
721
722 chained_irq_enter(irqchip, desc);
723
724 bank = container_of(chip, struct gpio_bank, chip);
725 isr_reg = bank->base + bank->regs->irqstatus;
726 pm_runtime_get_sync(bank->dev);
727
728 if (WARN_ON(!isr_reg))
729 goto exit;
730
731 while (1) {
732 u32 isr_saved, level_mask = 0;
733 u32 enabled;
734
735 enabled = omap_get_gpio_irqbank_mask(bank);
736 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
737
738 if (bank->level_mask)
739 level_mask = bank->level_mask & enabled;
740
741 /* clear edge sensitive interrupts before handler(s) are
742 called so that we don't miss any interrupt occurred while
743 executing them */
744 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
745 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
746 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
747
748 /* if there is only edge sensitive GPIO pin interrupts
749 configured, we could unmask GPIO bank interrupt immediately */
750 if (!level_mask && !unmasked) {
751 unmasked = 1;
752 chained_irq_exit(irqchip, desc);
753 }
754
755 if (!isr)
756 break;
757
758 while (isr) {
759 bit = __ffs(isr);
760 isr &= ~(BIT(bit));
761
762 /*
763 * Some chips can't respond to both rising and falling
764 * at the same time. If this irq was requested with
765 * both flags, we need to flip the ICR data for the IRQ
766 * to respond to the IRQ for the opposite direction.
767 * This will be indicated in the bank toggle_mask.
768 */
769 if (bank->toggle_mask & (BIT(bit)))
770 omap_toggle_gpio_edge_triggering(bank, bit);
771
772 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
773 bit));
774 }
775 }
776 /* if bank has any level sensitive GPIO pin interrupt
777 configured, we must unmask the bank interrupt only after
778 handler(s) are executed in order to avoid spurious bank
779 interrupt */
780exit:
781 if (!unmasked)
782 chained_irq_exit(irqchip, desc);
783 pm_runtime_put(bank->dev);
784}
785
786static unsigned int omap_gpio_irq_startup(struct irq_data *d)
787{
788 struct gpio_bank *bank = omap_irq_data_get_bank(d);
789 unsigned long flags;
790 unsigned offset = d->hwirq;
791
792 if (!BANK_USED(bank))
793 pm_runtime_get_sync(bank->dev);
794
795 raw_spin_lock_irqsave(&bank->lock, flags);
796
797 if (!LINE_USED(bank->mod_usage, offset))
798 omap_set_gpio_direction(bank, offset, 1);
799 else if (!omap_gpio_is_input(bank, offset))
800 goto err;
801 omap_enable_gpio_module(bank, offset);
802 bank->irq_usage |= BIT(offset);
803
804 raw_spin_unlock_irqrestore(&bank->lock, flags);
805 omap_gpio_unmask_irq(d);
806
807 return 0;
808err:
809 raw_spin_unlock_irqrestore(&bank->lock, flags);
810 if (!BANK_USED(bank))
811 pm_runtime_put(bank->dev);
812 return -EINVAL;
813}
814
815static void omap_gpio_irq_shutdown(struct irq_data *d)
816{
817 struct gpio_bank *bank = omap_irq_data_get_bank(d);
818 unsigned long flags;
819 unsigned offset = d->hwirq;
820
821 raw_spin_lock_irqsave(&bank->lock, flags);
822 bank->irq_usage &= ~(BIT(offset));
823 omap_set_gpio_irqenable(bank, offset, 0);
824 omap_clear_gpio_irqstatus(bank, offset);
825 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
826 if (!LINE_USED(bank->mod_usage, offset))
827 omap_clear_gpio_debounce(bank, offset);
828 omap_disable_gpio_module(bank, offset);
829 raw_spin_unlock_irqrestore(&bank->lock, flags);
830
831 /*
832 * If this is the last IRQ to be freed in the bank,
833 * disable the bank module.
834 */
835 if (!BANK_USED(bank))
836 pm_runtime_put(bank->dev);
837}
838
839static void omap_gpio_ack_irq(struct irq_data *d)
840{
841 struct gpio_bank *bank = omap_irq_data_get_bank(d);
842 unsigned offset = d->hwirq;
843
844 omap_clear_gpio_irqstatus(bank, offset);
845}
846
847static void omap_gpio_mask_irq(struct irq_data *d)
848{
849 struct gpio_bank *bank = omap_irq_data_get_bank(d);
850 unsigned offset = d->hwirq;
851 unsigned long flags;
852
853 raw_spin_lock_irqsave(&bank->lock, flags);
854 omap_set_gpio_irqenable(bank, offset, 0);
855 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
856 raw_spin_unlock_irqrestore(&bank->lock, flags);
857}
858
859static void omap_gpio_unmask_irq(struct irq_data *d)
860{
861 struct gpio_bank *bank = omap_irq_data_get_bank(d);
862 unsigned offset = d->hwirq;
863 u32 trigger = irqd_get_trigger_type(d);
864 unsigned long flags;
865
866 raw_spin_lock_irqsave(&bank->lock, flags);
867 if (trigger)
868 omap_set_gpio_triggering(bank, offset, trigger);
869
870 /* For level-triggered GPIOs, the clearing must be done after
871 * the HW source is cleared, thus after the handler has run */
872 if (bank->level_mask & BIT(offset)) {
873 omap_set_gpio_irqenable(bank, offset, 0);
874 omap_clear_gpio_irqstatus(bank, offset);
875 }
876
877 omap_set_gpio_irqenable(bank, offset, 1);
878 raw_spin_unlock_irqrestore(&bank->lock, flags);
879}
880
881/*---------------------------------------------------------------------*/
882
883static int omap_mpuio_suspend_noirq(struct device *dev)
884{
885 struct platform_device *pdev = to_platform_device(dev);
886 struct gpio_bank *bank = platform_get_drvdata(pdev);
887 void __iomem *mask_reg = bank->base +
888 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
889 unsigned long flags;
890
891 raw_spin_lock_irqsave(&bank->lock, flags);
892 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
893 raw_spin_unlock_irqrestore(&bank->lock, flags);
894
895 return 0;
896}
897
898static int omap_mpuio_resume_noirq(struct device *dev)
899{
900 struct platform_device *pdev = to_platform_device(dev);
901 struct gpio_bank *bank = platform_get_drvdata(pdev);
902 void __iomem *mask_reg = bank->base +
903 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
904 unsigned long flags;
905
906 raw_spin_lock_irqsave(&bank->lock, flags);
907 writel_relaxed(bank->context.wake_en, mask_reg);
908 raw_spin_unlock_irqrestore(&bank->lock, flags);
909
910 return 0;
911}
912
913static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
914 .suspend_noirq = omap_mpuio_suspend_noirq,
915 .resume_noirq = omap_mpuio_resume_noirq,
916};
917
918/* use platform_driver for this. */
919static struct platform_driver omap_mpuio_driver = {
920 .driver = {
921 .name = "mpuio",
922 .pm = &omap_mpuio_dev_pm_ops,
923 },
924};
925
926static struct platform_device omap_mpuio_device = {
927 .name = "mpuio",
928 .id = -1,
929 .dev = {
930 .driver = &omap_mpuio_driver.driver,
931 }
932 /* could list the /proc/iomem resources */
933};
934
935static inline void omap_mpuio_init(struct gpio_bank *bank)
936{
937 platform_set_drvdata(&omap_mpuio_device, bank);
938
939 if (platform_driver_register(&omap_mpuio_driver) == 0)
940 (void) platform_device_register(&omap_mpuio_device);
941}
942
943/*---------------------------------------------------------------------*/
944
945static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
946{
947 struct gpio_bank *bank;
948 unsigned long flags;
949 void __iomem *reg;
950 int dir;
951
952 bank = container_of(chip, struct gpio_bank, chip);
953 reg = bank->base + bank->regs->direction;
954 raw_spin_lock_irqsave(&bank->lock, flags);
955 dir = !!(readl_relaxed(reg) & BIT(offset));
956 raw_spin_unlock_irqrestore(&bank->lock, flags);
957 return dir;
958}
959
960static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
961{
962 struct gpio_bank *bank;
963 unsigned long flags;
964
965 bank = container_of(chip, struct gpio_bank, chip);
966 raw_spin_lock_irqsave(&bank->lock, flags);
967 omap_set_gpio_direction(bank, offset, 1);
968 raw_spin_unlock_irqrestore(&bank->lock, flags);
969 return 0;
970}
971
972static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
973{
974 struct gpio_bank *bank;
975
976 bank = container_of(chip, struct gpio_bank, chip);
977
978 if (omap_gpio_is_input(bank, offset))
979 return omap_get_gpio_datain(bank, offset);
980 else
981 return omap_get_gpio_dataout(bank, offset);
982}
983
984static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
985{
986 struct gpio_bank *bank;
987 unsigned long flags;
988
989 bank = container_of(chip, struct gpio_bank, chip);
990 raw_spin_lock_irqsave(&bank->lock, flags);
991 bank->set_dataout(bank, offset, value);
992 omap_set_gpio_direction(bank, offset, 0);
993 raw_spin_unlock_irqrestore(&bank->lock, flags);
994 return 0;
995}
996
997static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
998 unsigned debounce)
999{
1000 struct gpio_bank *bank;
1001 unsigned long flags;
1002
1003 bank = container_of(chip, struct gpio_bank, chip);
1004
1005 raw_spin_lock_irqsave(&bank->lock, flags);
1006 omap2_set_gpio_debounce(bank, offset, debounce);
1007 raw_spin_unlock_irqrestore(&bank->lock, flags);
1008
1009 return 0;
1010}
1011
1012static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1013{
1014 struct gpio_bank *bank;
1015 unsigned long flags;
1016
1017 bank = container_of(chip, struct gpio_bank, chip);
1018 raw_spin_lock_irqsave(&bank->lock, flags);
1019 bank->set_dataout(bank, offset, value);
1020 raw_spin_unlock_irqrestore(&bank->lock, flags);
1021}
1022
1023/*---------------------------------------------------------------------*/
1024
1025static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1026{
1027 static bool called;
1028 u32 rev;
1029
1030 if (called || bank->regs->revision == USHRT_MAX)
1031 return;
1032
1033 rev = readw_relaxed(bank->base + bank->regs->revision);
1034 pr_info("OMAP GPIO hardware version %d.%d\n",
1035 (rev >> 4) & 0x0f, rev & 0x0f);
1036
1037 called = true;
1038}
1039
1040static void omap_gpio_mod_init(struct gpio_bank *bank)
1041{
1042 void __iomem *base = bank->base;
1043 u32 l = 0xffffffff;
1044
1045 if (bank->width == 16)
1046 l = 0xffff;
1047
1048 if (bank->is_mpuio) {
1049 writel_relaxed(l, bank->base + bank->regs->irqenable);
1050 return;
1051 }
1052
1053 omap_gpio_rmw(base, bank->regs->irqenable, l,
1054 bank->regs->irqenable_inv);
1055 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1056 !bank->regs->irqenable_inv);
1057 if (bank->regs->debounce_en)
1058 writel_relaxed(0, base + bank->regs->debounce_en);
1059
1060 /* Save OE default value (0xffffffff) in the context */
1061 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1062 /* Initialize interface clk ungated, module enabled */
1063 if (bank->regs->ctrl)
1064 writel_relaxed(0, base + bank->regs->ctrl);
1065
1066 bank->dbck = clk_get(bank->dev, "dbclk");
1067 if (IS_ERR(bank->dbck))
1068 dev_err(bank->dev, "Could not get gpio dbck\n");
1069}
1070
1071static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1072{
1073 static int gpio;
1074 int irq_base = 0;
1075 int ret;
1076
1077 /*
1078 * REVISIT eventually switch from OMAP-specific gpio structs
1079 * over to the generic ones
1080 */
1081 bank->chip.request = omap_gpio_request;
1082 bank->chip.free = omap_gpio_free;
1083 bank->chip.get_direction = omap_gpio_get_direction;
1084 bank->chip.direction_input = omap_gpio_input;
1085 bank->chip.get = omap_gpio_get;
1086 bank->chip.direction_output = omap_gpio_output;
1087 bank->chip.set_debounce = omap_gpio_debounce;
1088 bank->chip.set = omap_gpio_set;
1089 if (bank->is_mpuio) {
1090 bank->chip.label = "mpuio";
1091 if (bank->regs->wkup_en)
1092 bank->chip.dev = &omap_mpuio_device.dev;
1093 bank->chip.base = OMAP_MPUIO(0);
1094 } else {
1095 bank->chip.label = "gpio";
1096 bank->chip.base = gpio;
1097 gpio += bank->width;
1098 }
1099 bank->chip.ngpio = bank->width;
1100
1101 ret = gpiochip_add(&bank->chip);
1102 if (ret) {
1103 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1104 return ret;
1105 }
1106
1107#ifdef CONFIG_ARCH_OMAP1
1108 /*
1109 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1110 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1111 */
1112 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1113 if (irq_base < 0) {
1114 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1115 return -ENODEV;
1116 }
1117#endif
1118
1119 /* MPUIO is a bit different, reading IRQ status clears it */
1120 if (bank->is_mpuio) {
1121 irqc->irq_ack = dummy_irq_chip.irq_ack;
1122 irqc->irq_mask = irq_gc_mask_set_bit;
1123 irqc->irq_unmask = irq_gc_mask_clr_bit;
1124 if (!bank->regs->wkup_en)
1125 irqc->irq_set_wake = NULL;
1126 }
1127
1128 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1129 irq_base, omap_gpio_irq_handler,
1130 IRQ_TYPE_NONE);
1131
1132 if (ret) {
1133 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1134 gpiochip_remove(&bank->chip);
1135 return -ENODEV;
1136 }
1137
1138 gpiochip_set_chained_irqchip(&bank->chip, irqc,
1139 bank->irq, omap_gpio_irq_handler);
1140
1141 return 0;
1142}
1143
1144static const struct of_device_id omap_gpio_match[];
1145
1146static int omap_gpio_probe(struct platform_device *pdev)
1147{
1148 struct device *dev = &pdev->dev;
1149 struct device_node *node = dev->of_node;
1150 const struct of_device_id *match;
1151 const struct omap_gpio_platform_data *pdata;
1152 struct resource *res;
1153 struct gpio_bank *bank;
1154 struct irq_chip *irqc;
1155 int ret;
1156
1157 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1158
1159 pdata = match ? match->data : dev_get_platdata(dev);
1160 if (!pdata)
1161 return -EINVAL;
1162
1163 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1164 if (!bank) {
1165 dev_err(dev, "Memory alloc failed\n");
1166 return -ENOMEM;
1167 }
1168
1169 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1170 if (!irqc)
1171 return -ENOMEM;
1172
1173 irqc->irq_startup = omap_gpio_irq_startup,
1174 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1175 irqc->irq_ack = omap_gpio_ack_irq,
1176 irqc->irq_mask = omap_gpio_mask_irq,
1177 irqc->irq_unmask = omap_gpio_unmask_irq,
1178 irqc->irq_set_type = omap_gpio_irq_type,
1179 irqc->irq_set_wake = omap_gpio_wake_enable,
1180 irqc->name = dev_name(&pdev->dev);
1181
1182 bank->irq = platform_get_irq(pdev, 0);
1183 if (bank->irq <= 0) {
1184 if (!bank->irq)
1185 bank->irq = -ENXIO;
1186 if (bank->irq != -EPROBE_DEFER)
1187 dev_err(dev,
1188 "can't get irq resource ret=%d\n", bank->irq);
1189 return bank->irq;
1190 }
1191
1192 bank->dev = dev;
1193 bank->chip.dev = dev;
1194 bank->chip.owner = THIS_MODULE;
1195 bank->dbck_flag = pdata->dbck_flag;
1196 bank->stride = pdata->bank_stride;
1197 bank->width = pdata->bank_width;
1198 bank->is_mpuio = pdata->is_mpuio;
1199 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1200 bank->regs = pdata->regs;
1201#ifdef CONFIG_OF_GPIO
1202 bank->chip.of_node = of_node_get(node);
1203#endif
1204 if (node) {
1205 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1206 bank->loses_context = true;
1207 } else {
1208 bank->loses_context = pdata->loses_context;
1209
1210 if (bank->loses_context)
1211 bank->get_context_loss_count =
1212 pdata->get_context_loss_count;
1213 }
1214
1215 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1216 bank->set_dataout = omap_set_gpio_dataout_reg;
1217 else
1218 bank->set_dataout = omap_set_gpio_dataout_mask;
1219
1220 raw_spin_lock_init(&bank->lock);
1221
1222 /* Static mapping, never released */
1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1224 bank->base = devm_ioremap_resource(dev, res);
1225 if (IS_ERR(bank->base)) {
1226 return PTR_ERR(bank->base);
1227 }
1228
1229 platform_set_drvdata(pdev, bank);
1230
1231 pm_runtime_enable(bank->dev);
1232 pm_runtime_irq_safe(bank->dev);
1233 pm_runtime_get_sync(bank->dev);
1234
1235 if (bank->is_mpuio)
1236 omap_mpuio_init(bank);
1237
1238 omap_gpio_mod_init(bank);
1239
1240 ret = omap_gpio_chip_init(bank, irqc);
1241 if (ret)
1242 return ret;
1243
1244 omap_gpio_show_rev(bank);
1245
1246 pm_runtime_put(bank->dev);
1247
1248 list_add_tail(&bank->node, &omap_gpio_list);
1249
1250 return 0;
1251}
1252
1253static int omap_gpio_remove(struct platform_device *pdev)
1254{
1255 struct gpio_bank *bank = platform_get_drvdata(pdev);
1256
1257 list_del(&bank->node);
1258 gpiochip_remove(&bank->chip);
1259 pm_runtime_disable(bank->dev);
1260
1261 return 0;
1262}
1263
1264#ifdef CONFIG_ARCH_OMAP2PLUS
1265
1266#if defined(CONFIG_PM)
1267static void omap_gpio_restore_context(struct gpio_bank *bank);
1268
1269static int omap_gpio_runtime_suspend(struct device *dev)
1270{
1271 struct platform_device *pdev = to_platform_device(dev);
1272 struct gpio_bank *bank = platform_get_drvdata(pdev);
1273 u32 l1 = 0, l2 = 0;
1274 unsigned long flags;
1275 u32 wake_low, wake_hi;
1276
1277 raw_spin_lock_irqsave(&bank->lock, flags);
1278
1279 /*
1280 * Only edges can generate a wakeup event to the PRCM.
1281 *
1282 * Therefore, ensure any wake-up capable GPIOs have
1283 * edge-detection enabled before going idle to ensure a wakeup
1284 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1285 * NDA TRM 25.5.3.1)
1286 *
1287 * The normal values will be restored upon ->runtime_resume()
1288 * by writing back the values saved in bank->context.
1289 */
1290 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1291 if (wake_low)
1292 writel_relaxed(wake_low | bank->context.fallingdetect,
1293 bank->base + bank->regs->fallingdetect);
1294 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1295 if (wake_hi)
1296 writel_relaxed(wake_hi | bank->context.risingdetect,
1297 bank->base + bank->regs->risingdetect);
1298
1299 if (!bank->enabled_non_wakeup_gpios)
1300 goto update_gpio_context_count;
1301
1302 if (bank->power_mode != OFF_MODE) {
1303 bank->power_mode = 0;
1304 goto update_gpio_context_count;
1305 }
1306 /*
1307 * If going to OFF, remove triggering for all
1308 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1309 * generated. See OMAP2420 Errata item 1.101.
1310 */
1311 bank->saved_datain = readl_relaxed(bank->base +
1312 bank->regs->datain);
1313 l1 = bank->context.fallingdetect;
1314 l2 = bank->context.risingdetect;
1315
1316 l1 &= ~bank->enabled_non_wakeup_gpios;
1317 l2 &= ~bank->enabled_non_wakeup_gpios;
1318
1319 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1320 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1321
1322 bank->workaround_enabled = true;
1323
1324update_gpio_context_count:
1325 if (bank->get_context_loss_count)
1326 bank->context_loss_count =
1327 bank->get_context_loss_count(bank->dev);
1328
1329 omap_gpio_dbck_disable(bank);
1330 raw_spin_unlock_irqrestore(&bank->lock, flags);
1331
1332 return 0;
1333}
1334
1335static void omap_gpio_init_context(struct gpio_bank *p);
1336
1337static int omap_gpio_runtime_resume(struct device *dev)
1338{
1339 struct platform_device *pdev = to_platform_device(dev);
1340 struct gpio_bank *bank = platform_get_drvdata(pdev);
1341 u32 l = 0, gen, gen0, gen1;
1342 unsigned long flags;
1343 int c;
1344
1345 raw_spin_lock_irqsave(&bank->lock, flags);
1346
1347 /*
1348 * On the first resume during the probe, the context has not
1349 * been initialised and so initialise it now. Also initialise
1350 * the context loss count.
1351 */
1352 if (bank->loses_context && !bank->context_valid) {
1353 omap_gpio_init_context(bank);
1354
1355 if (bank->get_context_loss_count)
1356 bank->context_loss_count =
1357 bank->get_context_loss_count(bank->dev);
1358 }
1359
1360 omap_gpio_dbck_enable(bank);
1361
1362 /*
1363 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1364 * GPIOs were set to edge trigger also in order to be able to
1365 * generate a PRCM wakeup. Here we restore the
1366 * pre-runtime_suspend() values for edge triggering.
1367 */
1368 writel_relaxed(bank->context.fallingdetect,
1369 bank->base + bank->regs->fallingdetect);
1370 writel_relaxed(bank->context.risingdetect,
1371 bank->base + bank->regs->risingdetect);
1372
1373 if (bank->loses_context) {
1374 if (!bank->get_context_loss_count) {
1375 omap_gpio_restore_context(bank);
1376 } else {
1377 c = bank->get_context_loss_count(bank->dev);
1378 if (c != bank->context_loss_count) {
1379 omap_gpio_restore_context(bank);
1380 } else {
1381 raw_spin_unlock_irqrestore(&bank->lock, flags);
1382 return 0;
1383 }
1384 }
1385 }
1386
1387 if (!bank->workaround_enabled) {
1388 raw_spin_unlock_irqrestore(&bank->lock, flags);
1389 return 0;
1390 }
1391
1392 l = readl_relaxed(bank->base + bank->regs->datain);
1393
1394 /*
1395 * Check if any of the non-wakeup interrupt GPIOs have changed
1396 * state. If so, generate an IRQ by software. This is
1397 * horribly racy, but it's the best we can do to work around
1398 * this silicon bug.
1399 */
1400 l ^= bank->saved_datain;
1401 l &= bank->enabled_non_wakeup_gpios;
1402
1403 /*
1404 * No need to generate IRQs for the rising edge for gpio IRQs
1405 * configured with falling edge only; and vice versa.
1406 */
1407 gen0 = l & bank->context.fallingdetect;
1408 gen0 &= bank->saved_datain;
1409
1410 gen1 = l & bank->context.risingdetect;
1411 gen1 &= ~(bank->saved_datain);
1412
1413 /* FIXME: Consider GPIO IRQs with level detections properly! */
1414 gen = l & (~(bank->context.fallingdetect) &
1415 ~(bank->context.risingdetect));
1416 /* Consider all GPIO IRQs needed to be updated */
1417 gen |= gen0 | gen1;
1418
1419 if (gen) {
1420 u32 old0, old1;
1421
1422 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1423 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1424
1425 if (!bank->regs->irqstatus_raw0) {
1426 writel_relaxed(old0 | gen, bank->base +
1427 bank->regs->leveldetect0);
1428 writel_relaxed(old1 | gen, bank->base +
1429 bank->regs->leveldetect1);
1430 }
1431
1432 if (bank->regs->irqstatus_raw0) {
1433 writel_relaxed(old0 | l, bank->base +
1434 bank->regs->leveldetect0);
1435 writel_relaxed(old1 | l, bank->base +
1436 bank->regs->leveldetect1);
1437 }
1438 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1439 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1440 }
1441
1442 bank->workaround_enabled = false;
1443 raw_spin_unlock_irqrestore(&bank->lock, flags);
1444
1445 return 0;
1446}
1447#endif /* CONFIG_PM */
1448
1449#if IS_BUILTIN(CONFIG_GPIO_OMAP)
1450void omap2_gpio_prepare_for_idle(int pwr_mode)
1451{
1452 struct gpio_bank *bank;
1453
1454 list_for_each_entry(bank, &omap_gpio_list, node) {
1455 if (!BANK_USED(bank) || !bank->loses_context)
1456 continue;
1457
1458 bank->power_mode = pwr_mode;
1459
1460 pm_runtime_put_sync_suspend(bank->dev);
1461 }
1462}
1463
1464void omap2_gpio_resume_after_idle(void)
1465{
1466 struct gpio_bank *bank;
1467
1468 list_for_each_entry(bank, &omap_gpio_list, node) {
1469 if (!BANK_USED(bank) || !bank->loses_context)
1470 continue;
1471
1472 pm_runtime_get_sync(bank->dev);
1473 }
1474}
1475#endif
1476
1477#if defined(CONFIG_PM)
1478static void omap_gpio_init_context(struct gpio_bank *p)
1479{
1480 struct omap_gpio_reg_offs *regs = p->regs;
1481 void __iomem *base = p->base;
1482
1483 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1484 p->context.oe = readl_relaxed(base + regs->direction);
1485 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1486 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1487 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1488 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1489 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1490 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1491 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1492
1493 if (regs->set_dataout && p->regs->clr_dataout)
1494 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1495 else
1496 p->context.dataout = readl_relaxed(base + regs->dataout);
1497
1498 p->context_valid = true;
1499}
1500
1501static void omap_gpio_restore_context(struct gpio_bank *bank)
1502{
1503 writel_relaxed(bank->context.wake_en,
1504 bank->base + bank->regs->wkup_en);
1505 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1506 writel_relaxed(bank->context.leveldetect0,
1507 bank->base + bank->regs->leveldetect0);
1508 writel_relaxed(bank->context.leveldetect1,
1509 bank->base + bank->regs->leveldetect1);
1510 writel_relaxed(bank->context.risingdetect,
1511 bank->base + bank->regs->risingdetect);
1512 writel_relaxed(bank->context.fallingdetect,
1513 bank->base + bank->regs->fallingdetect);
1514 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1515 writel_relaxed(bank->context.dataout,
1516 bank->base + bank->regs->set_dataout);
1517 else
1518 writel_relaxed(bank->context.dataout,
1519 bank->base + bank->regs->dataout);
1520 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1521
1522 if (bank->dbck_enable_mask) {
1523 writel_relaxed(bank->context.debounce, bank->base +
1524 bank->regs->debounce);
1525 writel_relaxed(bank->context.debounce_en,
1526 bank->base + bank->regs->debounce_en);
1527 }
1528
1529 writel_relaxed(bank->context.irqenable1,
1530 bank->base + bank->regs->irqenable);
1531 writel_relaxed(bank->context.irqenable2,
1532 bank->base + bank->regs->irqenable2);
1533}
1534#endif /* CONFIG_PM */
1535#else
1536#define omap_gpio_runtime_suspend NULL
1537#define omap_gpio_runtime_resume NULL
1538static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1539#endif
1540
1541static const struct dev_pm_ops gpio_pm_ops = {
1542 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1543 NULL)
1544};
1545
1546#if defined(CONFIG_OF)
1547static struct omap_gpio_reg_offs omap2_gpio_regs = {
1548 .revision = OMAP24XX_GPIO_REVISION,
1549 .direction = OMAP24XX_GPIO_OE,
1550 .datain = OMAP24XX_GPIO_DATAIN,
1551 .dataout = OMAP24XX_GPIO_DATAOUT,
1552 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1553 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1554 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1555 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1556 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1557 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1558 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1559 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1560 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1561 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1562 .ctrl = OMAP24XX_GPIO_CTRL,
1563 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1564 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1565 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1566 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1567 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1568};
1569
1570static struct omap_gpio_reg_offs omap4_gpio_regs = {
1571 .revision = OMAP4_GPIO_REVISION,
1572 .direction = OMAP4_GPIO_OE,
1573 .datain = OMAP4_GPIO_DATAIN,
1574 .dataout = OMAP4_GPIO_DATAOUT,
1575 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1576 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1577 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1578 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1579 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1580 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1581 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1582 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1583 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1584 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1585 .ctrl = OMAP4_GPIO_CTRL,
1586 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1587 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1588 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1589 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1590 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1591};
1592
1593static const struct omap_gpio_platform_data omap2_pdata = {
1594 .regs = &omap2_gpio_regs,
1595 .bank_width = 32,
1596 .dbck_flag = false,
1597};
1598
1599static const struct omap_gpio_platform_data omap3_pdata = {
1600 .regs = &omap2_gpio_regs,
1601 .bank_width = 32,
1602 .dbck_flag = true,
1603};
1604
1605static const struct omap_gpio_platform_data omap4_pdata = {
1606 .regs = &omap4_gpio_regs,
1607 .bank_width = 32,
1608 .dbck_flag = true,
1609};
1610
1611static const struct of_device_id omap_gpio_match[] = {
1612 {
1613 .compatible = "ti,omap4-gpio",
1614 .data = &omap4_pdata,
1615 },
1616 {
1617 .compatible = "ti,omap3-gpio",
1618 .data = &omap3_pdata,
1619 },
1620 {
1621 .compatible = "ti,omap2-gpio",
1622 .data = &omap2_pdata,
1623 },
1624 { },
1625};
1626MODULE_DEVICE_TABLE(of, omap_gpio_match);
1627#endif
1628
1629static struct platform_driver omap_gpio_driver = {
1630 .probe = omap_gpio_probe,
1631 .remove = omap_gpio_remove,
1632 .driver = {
1633 .name = "omap_gpio",
1634 .pm = &gpio_pm_ops,
1635 .of_match_table = of_match_ptr(omap_gpio_match),
1636 },
1637};
1638
1639/*
1640 * gpio driver register needs to be done before
1641 * machine_init functions access gpio APIs.
1642 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1643 */
1644static int __init omap_gpio_drv_reg(void)
1645{
1646 return platform_driver_register(&omap_gpio_driver);
1647}
1648postcore_initcall(omap_gpio_drv_reg);
1649
1650static void __exit omap_gpio_exit(void)
1651{
1652 platform_driver_unregister(&omap_gpio_driver);
1653}
1654module_exit(omap_gpio_exit);
1655
1656MODULE_DESCRIPTION("omap gpio driver");
1657MODULE_ALIAS("platform:gpio-omap");
1658MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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