| 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Alex Deucher |
| 23 | */ |
| 24 | #include <linux/firmware.h> |
| 25 | #include <drm/drmP.h> |
| 26 | #include "amdgpu.h" |
| 27 | #include "amdgpu_ucode.h" |
| 28 | #include "amdgpu_trace.h" |
| 29 | #include "cikd.h" |
| 30 | #include "cik.h" |
| 31 | |
| 32 | #include "bif/bif_4_1_d.h" |
| 33 | #include "bif/bif_4_1_sh_mask.h" |
| 34 | |
| 35 | #include "gca/gfx_7_2_d.h" |
| 36 | #include "gca/gfx_7_2_enum.h" |
| 37 | #include "gca/gfx_7_2_sh_mask.h" |
| 38 | |
| 39 | #include "gmc/gmc_7_1_d.h" |
| 40 | #include "gmc/gmc_7_1_sh_mask.h" |
| 41 | |
| 42 | #include "oss/oss_2_0_d.h" |
| 43 | #include "oss/oss_2_0_sh_mask.h" |
| 44 | |
| 45 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = |
| 46 | { |
| 47 | SDMA0_REGISTER_OFFSET, |
| 48 | SDMA1_REGISTER_OFFSET |
| 49 | }; |
| 50 | |
| 51 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); |
| 52 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); |
| 53 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); |
| 54 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); |
| 55 | static int cik_sdma_soft_reset(void *handle); |
| 56 | |
| 57 | MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); |
| 58 | MODULE_FIRMWARE("radeon/bonaire_sdma1.bin"); |
| 59 | MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); |
| 60 | MODULE_FIRMWARE("radeon/hawaii_sdma1.bin"); |
| 61 | MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); |
| 62 | MODULE_FIRMWARE("radeon/kaveri_sdma1.bin"); |
| 63 | MODULE_FIRMWARE("radeon/kabini_sdma.bin"); |
| 64 | MODULE_FIRMWARE("radeon/kabini_sdma1.bin"); |
| 65 | MODULE_FIRMWARE("radeon/mullins_sdma.bin"); |
| 66 | MODULE_FIRMWARE("radeon/mullins_sdma1.bin"); |
| 67 | |
| 68 | u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); |
| 69 | |
| 70 | |
| 71 | static void cik_sdma_free_microcode(struct amdgpu_device *adev) |
| 72 | { |
| 73 | int i; |
| 74 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 75 | release_firmware(adev->sdma.instance[i].fw); |
| 76 | adev->sdma.instance[i].fw = NULL; |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * sDMA - System DMA |
| 82 | * Starting with CIK, the GPU has new asynchronous |
| 83 | * DMA engines. These engines are used for compute |
| 84 | * and gfx. There are two DMA engines (SDMA0, SDMA1) |
| 85 | * and each one supports 1 ring buffer used for gfx |
| 86 | * and 2 queues used for compute. |
| 87 | * |
| 88 | * The programming model is very similar to the CP |
| 89 | * (ring buffer, IBs, etc.), but sDMA has it's own |
| 90 | * packet format that is different from the PM4 format |
| 91 | * used by the CP. sDMA supports copying data, writing |
| 92 | * embedded data, solid fills, and a number of other |
| 93 | * things. It also has support for tiling/detiling of |
| 94 | * buffers. |
| 95 | */ |
| 96 | |
| 97 | /** |
| 98 | * cik_sdma_init_microcode - load ucode images from disk |
| 99 | * |
| 100 | * @adev: amdgpu_device pointer |
| 101 | * |
| 102 | * Use the firmware interface to load the ucode images into |
| 103 | * the driver (not loaded into hw). |
| 104 | * Returns 0 on success, error on failure. |
| 105 | */ |
| 106 | static int cik_sdma_init_microcode(struct amdgpu_device *adev) |
| 107 | { |
| 108 | const char *chip_name; |
| 109 | char fw_name[30]; |
| 110 | int err = 0, i; |
| 111 | |
| 112 | DRM_DEBUG("\n"); |
| 113 | |
| 114 | switch (adev->asic_type) { |
| 115 | case CHIP_BONAIRE: |
| 116 | chip_name = "bonaire"; |
| 117 | break; |
| 118 | case CHIP_HAWAII: |
| 119 | chip_name = "hawaii"; |
| 120 | break; |
| 121 | case CHIP_KAVERI: |
| 122 | chip_name = "kaveri"; |
| 123 | break; |
| 124 | case CHIP_KABINI: |
| 125 | chip_name = "kabini"; |
| 126 | break; |
| 127 | case CHIP_MULLINS: |
| 128 | chip_name = "mullins"; |
| 129 | break; |
| 130 | default: BUG(); |
| 131 | } |
| 132 | |
| 133 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 134 | if (i == 0) |
| 135 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); |
| 136 | else |
| 137 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); |
| 138 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
| 139 | if (err) |
| 140 | goto out; |
| 141 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
| 142 | } |
| 143 | out: |
| 144 | if (err) { |
| 145 | printk(KERN_ERR |
| 146 | "cik_sdma: Failed to load firmware \"%s\"\n", |
| 147 | fw_name); |
| 148 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 149 | release_firmware(adev->sdma.instance[i].fw); |
| 150 | adev->sdma.instance[i].fw = NULL; |
| 151 | } |
| 152 | } |
| 153 | return err; |
| 154 | } |
| 155 | |
| 156 | /** |
| 157 | * cik_sdma_ring_get_rptr - get the current read pointer |
| 158 | * |
| 159 | * @ring: amdgpu ring pointer |
| 160 | * |
| 161 | * Get the current rptr from the hardware (CIK+). |
| 162 | */ |
| 163 | static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) |
| 164 | { |
| 165 | u32 rptr; |
| 166 | |
| 167 | rptr = ring->adev->wb.wb[ring->rptr_offs]; |
| 168 | |
| 169 | return (rptr & 0x3fffc) >> 2; |
| 170 | } |
| 171 | |
| 172 | /** |
| 173 | * cik_sdma_ring_get_wptr - get the current write pointer |
| 174 | * |
| 175 | * @ring: amdgpu ring pointer |
| 176 | * |
| 177 | * Get the current wptr from the hardware (CIK+). |
| 178 | */ |
| 179 | static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) |
| 180 | { |
| 181 | struct amdgpu_device *adev = ring->adev; |
| 182 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
| 183 | |
| 184 | return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; |
| 185 | } |
| 186 | |
| 187 | /** |
| 188 | * cik_sdma_ring_set_wptr - commit the write pointer |
| 189 | * |
| 190 | * @ring: amdgpu ring pointer |
| 191 | * |
| 192 | * Write the wptr back to the hardware (CIK+). |
| 193 | */ |
| 194 | static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) |
| 195 | { |
| 196 | struct amdgpu_device *adev = ring->adev; |
| 197 | u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; |
| 198 | |
| 199 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); |
| 200 | } |
| 201 | |
| 202 | static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
| 203 | { |
| 204 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
| 205 | int i; |
| 206 | |
| 207 | for (i = 0; i < count; i++) |
| 208 | if (sdma && sdma->burst_nop && (i == 0)) |
| 209 | amdgpu_ring_write(ring, ring->nop | |
| 210 | SDMA_NOP_COUNT(count - 1)); |
| 211 | else |
| 212 | amdgpu_ring_write(ring, ring->nop); |
| 213 | } |
| 214 | |
| 215 | /** |
| 216 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine |
| 217 | * |
| 218 | * @ring: amdgpu ring pointer |
| 219 | * @ib: IB object to schedule |
| 220 | * |
| 221 | * Schedule an IB in the DMA ring (CIK). |
| 222 | */ |
| 223 | static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, |
| 224 | struct amdgpu_ib *ib, |
| 225 | unsigned vm_id, bool ctx_switch) |
| 226 | { |
| 227 | u32 extra_bits = vm_id & 0xf; |
| 228 | |
| 229 | /* IB packet must end on a 8 DW boundary */ |
| 230 | cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8); |
| 231 | |
| 232 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); |
| 233 | amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ |
| 234 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); |
| 235 | amdgpu_ring_write(ring, ib->length_dw); |
| 236 | |
| 237 | } |
| 238 | |
| 239 | /** |
| 240 | * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
| 241 | * |
| 242 | * @ring: amdgpu ring pointer |
| 243 | * |
| 244 | * Emit an hdp flush packet on the requested DMA ring. |
| 245 | */ |
| 246 | static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
| 247 | { |
| 248 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | |
| 249 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ |
| 250 | u32 ref_and_mask; |
| 251 | |
| 252 | if (ring == &ring->adev->sdma.instance[0].ring) |
| 253 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; |
| 254 | else |
| 255 | ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; |
| 256 | |
| 257 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); |
| 258 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); |
| 259 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); |
| 260 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ |
| 261 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ |
| 262 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ |
| 263 | } |
| 264 | |
| 265 | static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) |
| 266 | { |
| 267 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 268 | amdgpu_ring_write(ring, mmHDP_DEBUG0); |
| 269 | amdgpu_ring_write(ring, 1); |
| 270 | } |
| 271 | |
| 272 | /** |
| 273 | * cik_sdma_ring_emit_fence - emit a fence on the DMA ring |
| 274 | * |
| 275 | * @ring: amdgpu ring pointer |
| 276 | * @fence: amdgpu fence object |
| 277 | * |
| 278 | * Add a DMA fence packet to the ring to write |
| 279 | * the fence seq number and DMA trap packet to generate |
| 280 | * an interrupt if needed (CIK). |
| 281 | */ |
| 282 | static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
| 283 | unsigned flags) |
| 284 | { |
| 285 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
| 286 | /* write the fence */ |
| 287 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); |
| 288 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
| 289 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
| 290 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
| 291 | |
| 292 | /* optionally write high bits as well */ |
| 293 | if (write64bit) { |
| 294 | addr += 4; |
| 295 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); |
| 296 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
| 297 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
| 298 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
| 299 | } |
| 300 | |
| 301 | /* generate an interrupt */ |
| 302 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); |
| 303 | } |
| 304 | |
| 305 | /** |
| 306 | * cik_sdma_gfx_stop - stop the gfx async dma engines |
| 307 | * |
| 308 | * @adev: amdgpu_device pointer |
| 309 | * |
| 310 | * Stop the gfx async dma ring buffers (CIK). |
| 311 | */ |
| 312 | static void cik_sdma_gfx_stop(struct amdgpu_device *adev) |
| 313 | { |
| 314 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
| 315 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; |
| 316 | u32 rb_cntl; |
| 317 | int i; |
| 318 | |
| 319 | if ((adev->mman.buffer_funcs_ring == sdma0) || |
| 320 | (adev->mman.buffer_funcs_ring == sdma1)) |
| 321 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); |
| 322 | |
| 323 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 324 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
| 325 | rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; |
| 326 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); |
| 327 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); |
| 328 | } |
| 329 | sdma0->ready = false; |
| 330 | sdma1->ready = false; |
| 331 | } |
| 332 | |
| 333 | /** |
| 334 | * cik_sdma_rlc_stop - stop the compute async dma engines |
| 335 | * |
| 336 | * @adev: amdgpu_device pointer |
| 337 | * |
| 338 | * Stop the compute async dma queues (CIK). |
| 339 | */ |
| 340 | static void cik_sdma_rlc_stop(struct amdgpu_device *adev) |
| 341 | { |
| 342 | /* XXX todo */ |
| 343 | } |
| 344 | |
| 345 | /** |
| 346 | * cik_sdma_enable - stop the async dma engines |
| 347 | * |
| 348 | * @adev: amdgpu_device pointer |
| 349 | * @enable: enable/disable the DMA MEs. |
| 350 | * |
| 351 | * Halt or unhalt the async dma engines (CIK). |
| 352 | */ |
| 353 | static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) |
| 354 | { |
| 355 | u32 me_cntl; |
| 356 | int i; |
| 357 | |
| 358 | if (!enable) { |
| 359 | cik_sdma_gfx_stop(adev); |
| 360 | cik_sdma_rlc_stop(adev); |
| 361 | } |
| 362 | |
| 363 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 364 | me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
| 365 | if (enable) |
| 366 | me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; |
| 367 | else |
| 368 | me_cntl |= SDMA0_F32_CNTL__HALT_MASK; |
| 369 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | /** |
| 374 | * cik_sdma_gfx_resume - setup and start the async dma engines |
| 375 | * |
| 376 | * @adev: amdgpu_device pointer |
| 377 | * |
| 378 | * Set up the gfx DMA ring buffers and enable them (CIK). |
| 379 | * Returns 0 for success, error for failure. |
| 380 | */ |
| 381 | static int cik_sdma_gfx_resume(struct amdgpu_device *adev) |
| 382 | { |
| 383 | struct amdgpu_ring *ring; |
| 384 | u32 rb_cntl, ib_cntl; |
| 385 | u32 rb_bufsz; |
| 386 | u32 wb_offset; |
| 387 | int i, j, r; |
| 388 | |
| 389 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 390 | ring = &adev->sdma.instance[i].ring; |
| 391 | wb_offset = (ring->rptr_offs * 4); |
| 392 | |
| 393 | mutex_lock(&adev->srbm_mutex); |
| 394 | for (j = 0; j < 16; j++) { |
| 395 | cik_srbm_select(adev, 0, 0, 0, j); |
| 396 | /* SDMA GFX */ |
| 397 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); |
| 398 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); |
| 399 | /* XXX SDMA RLC - todo */ |
| 400 | } |
| 401 | cik_srbm_select(adev, 0, 0, 0, 0); |
| 402 | mutex_unlock(&adev->srbm_mutex); |
| 403 | |
| 404 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
| 405 | adev->gfx.config.gb_addr_config & 0x70); |
| 406 | |
| 407 | WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); |
| 408 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); |
| 409 | |
| 410 | /* Set ring buffer size in dwords */ |
| 411 | rb_bufsz = order_base_2(ring->ring_size / 4); |
| 412 | rb_cntl = rb_bufsz << 1; |
| 413 | #ifdef __BIG_ENDIAN |
| 414 | rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | |
| 415 | SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; |
| 416 | #endif |
| 417 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); |
| 418 | |
| 419 | /* Initialize the ring buffer's read and write pointers */ |
| 420 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); |
| 421 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); |
| 422 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
| 423 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); |
| 424 | |
| 425 | /* set the wb address whether it's enabled or not */ |
| 426 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], |
| 427 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); |
| 428 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], |
| 429 | ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); |
| 430 | |
| 431 | rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; |
| 432 | |
| 433 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); |
| 434 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); |
| 435 | |
| 436 | ring->wptr = 0; |
| 437 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); |
| 438 | |
| 439 | /* enable DMA RB */ |
| 440 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], |
| 441 | rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); |
| 442 | |
| 443 | ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; |
| 444 | #ifdef __BIG_ENDIAN |
| 445 | ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; |
| 446 | #endif |
| 447 | /* enable DMA IBs */ |
| 448 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); |
| 449 | |
| 450 | ring->ready = true; |
| 451 | } |
| 452 | |
| 453 | cik_sdma_enable(adev, true); |
| 454 | |
| 455 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 456 | ring = &adev->sdma.instance[i].ring; |
| 457 | r = amdgpu_ring_test_ring(ring); |
| 458 | if (r) { |
| 459 | ring->ready = false; |
| 460 | return r; |
| 461 | } |
| 462 | |
| 463 | if (adev->mman.buffer_funcs_ring == ring) |
| 464 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); |
| 465 | } |
| 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | /** |
| 471 | * cik_sdma_rlc_resume - setup and start the async dma engines |
| 472 | * |
| 473 | * @adev: amdgpu_device pointer |
| 474 | * |
| 475 | * Set up the compute DMA queues and enable them (CIK). |
| 476 | * Returns 0 for success, error for failure. |
| 477 | */ |
| 478 | static int cik_sdma_rlc_resume(struct amdgpu_device *adev) |
| 479 | { |
| 480 | /* XXX todo */ |
| 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | /** |
| 485 | * cik_sdma_load_microcode - load the sDMA ME ucode |
| 486 | * |
| 487 | * @adev: amdgpu_device pointer |
| 488 | * |
| 489 | * Loads the sDMA0/1 ucode. |
| 490 | * Returns 0 for success, -EINVAL if the ucode is not available. |
| 491 | */ |
| 492 | static int cik_sdma_load_microcode(struct amdgpu_device *adev) |
| 493 | { |
| 494 | const struct sdma_firmware_header_v1_0 *hdr; |
| 495 | const __le32 *fw_data; |
| 496 | u32 fw_size; |
| 497 | int i, j; |
| 498 | |
| 499 | /* halt the MEs */ |
| 500 | cik_sdma_enable(adev, false); |
| 501 | |
| 502 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 503 | if (!adev->sdma.instance[i].fw) |
| 504 | return -EINVAL; |
| 505 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
| 506 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
| 507 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
| 508 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); |
| 509 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); |
| 510 | if (adev->sdma.instance[i].feature_version >= 20) |
| 511 | adev->sdma.instance[i].burst_nop = true; |
| 512 | fw_data = (const __le32 *) |
| 513 | (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
| 514 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); |
| 515 | for (j = 0; j < fw_size; j++) |
| 516 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); |
| 517 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
| 518 | } |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
| 523 | /** |
| 524 | * cik_sdma_start - setup and start the async dma engines |
| 525 | * |
| 526 | * @adev: amdgpu_device pointer |
| 527 | * |
| 528 | * Set up the DMA engines and enable them (CIK). |
| 529 | * Returns 0 for success, error for failure. |
| 530 | */ |
| 531 | static int cik_sdma_start(struct amdgpu_device *adev) |
| 532 | { |
| 533 | int r; |
| 534 | |
| 535 | r = cik_sdma_load_microcode(adev); |
| 536 | if (r) |
| 537 | return r; |
| 538 | |
| 539 | /* halt the engine before programing */ |
| 540 | cik_sdma_enable(adev, false); |
| 541 | |
| 542 | /* start the gfx rings and rlc compute queues */ |
| 543 | r = cik_sdma_gfx_resume(adev); |
| 544 | if (r) |
| 545 | return r; |
| 546 | r = cik_sdma_rlc_resume(adev); |
| 547 | if (r) |
| 548 | return r; |
| 549 | |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | /** |
| 554 | * cik_sdma_ring_test_ring - simple async dma engine test |
| 555 | * |
| 556 | * @ring: amdgpu_ring structure holding ring information |
| 557 | * |
| 558 | * Test the DMA engine by writing using it to write an |
| 559 | * value to memory. (CIK). |
| 560 | * Returns 0 for success, error for failure. |
| 561 | */ |
| 562 | static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) |
| 563 | { |
| 564 | struct amdgpu_device *adev = ring->adev; |
| 565 | unsigned i; |
| 566 | unsigned index; |
| 567 | int r; |
| 568 | u32 tmp; |
| 569 | u64 gpu_addr; |
| 570 | |
| 571 | r = amdgpu_wb_get(adev, &index); |
| 572 | if (r) { |
| 573 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); |
| 574 | return r; |
| 575 | } |
| 576 | |
| 577 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
| 578 | tmp = 0xCAFEDEAD; |
| 579 | adev->wb.wb[index] = cpu_to_le32(tmp); |
| 580 | |
| 581 | r = amdgpu_ring_alloc(ring, 5); |
| 582 | if (r) { |
| 583 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); |
| 584 | amdgpu_wb_free(adev, index); |
| 585 | return r; |
| 586 | } |
| 587 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); |
| 588 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); |
| 589 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); |
| 590 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ |
| 591 | amdgpu_ring_write(ring, 0xDEADBEEF); |
| 592 | amdgpu_ring_commit(ring); |
| 593 | |
| 594 | for (i = 0; i < adev->usec_timeout; i++) { |
| 595 | tmp = le32_to_cpu(adev->wb.wb[index]); |
| 596 | if (tmp == 0xDEADBEEF) |
| 597 | break; |
| 598 | DRM_UDELAY(1); |
| 599 | } |
| 600 | |
| 601 | if (i < adev->usec_timeout) { |
| 602 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
| 603 | } else { |
| 604 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", |
| 605 | ring->idx, tmp); |
| 606 | r = -EINVAL; |
| 607 | } |
| 608 | amdgpu_wb_free(adev, index); |
| 609 | |
| 610 | return r; |
| 611 | } |
| 612 | |
| 613 | /** |
| 614 | * cik_sdma_ring_test_ib - test an IB on the DMA engine |
| 615 | * |
| 616 | * @ring: amdgpu_ring structure holding ring information |
| 617 | * |
| 618 | * Test a simple IB in the DMA ring (CIK). |
| 619 | * Returns 0 on success, error on failure. |
| 620 | */ |
| 621 | static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
| 622 | { |
| 623 | struct amdgpu_device *adev = ring->adev; |
| 624 | struct amdgpu_ib ib; |
| 625 | struct fence *f = NULL; |
| 626 | unsigned index; |
| 627 | u32 tmp = 0; |
| 628 | u64 gpu_addr; |
| 629 | long r; |
| 630 | |
| 631 | r = amdgpu_wb_get(adev, &index); |
| 632 | if (r) { |
| 633 | dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); |
| 634 | return r; |
| 635 | } |
| 636 | |
| 637 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
| 638 | tmp = 0xCAFEDEAD; |
| 639 | adev->wb.wb[index] = cpu_to_le32(tmp); |
| 640 | memset(&ib, 0, sizeof(ib)); |
| 641 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
| 642 | if (r) { |
| 643 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); |
| 644 | goto err0; |
| 645 | } |
| 646 | |
| 647 | ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, |
| 648 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
| 649 | ib.ptr[1] = lower_32_bits(gpu_addr); |
| 650 | ib.ptr[2] = upper_32_bits(gpu_addr); |
| 651 | ib.ptr[3] = 1; |
| 652 | ib.ptr[4] = 0xDEADBEEF; |
| 653 | ib.length_dw = 5; |
| 654 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
| 655 | if (r) |
| 656 | goto err1; |
| 657 | |
| 658 | r = fence_wait_timeout(f, false, timeout); |
| 659 | if (r == 0) { |
| 660 | DRM_ERROR("amdgpu: IB test timed out\n"); |
| 661 | r = -ETIMEDOUT; |
| 662 | goto err1; |
| 663 | } else if (r < 0) { |
| 664 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); |
| 665 | goto err1; |
| 666 | } |
| 667 | tmp = le32_to_cpu(adev->wb.wb[index]); |
| 668 | if (tmp == 0xDEADBEEF) { |
| 669 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); |
| 670 | r = 0; |
| 671 | } else { |
| 672 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); |
| 673 | r = -EINVAL; |
| 674 | } |
| 675 | |
| 676 | err1: |
| 677 | amdgpu_ib_free(adev, &ib, NULL); |
| 678 | fence_put(f); |
| 679 | err0: |
| 680 | amdgpu_wb_free(adev, index); |
| 681 | return r; |
| 682 | } |
| 683 | |
| 684 | /** |
| 685 | * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART |
| 686 | * |
| 687 | * @ib: indirect buffer to fill with commands |
| 688 | * @pe: addr of the page entry |
| 689 | * @src: src addr to copy from |
| 690 | * @count: number of page entries to update |
| 691 | * |
| 692 | * Update PTEs by copying them from the GART using sDMA (CIK). |
| 693 | */ |
| 694 | static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, |
| 695 | uint64_t pe, uint64_t src, |
| 696 | unsigned count) |
| 697 | { |
| 698 | unsigned bytes = count * 8; |
| 699 | |
| 700 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, |
| 701 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
| 702 | ib->ptr[ib->length_dw++] = bytes; |
| 703 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
| 704 | ib->ptr[ib->length_dw++] = lower_32_bits(src); |
| 705 | ib->ptr[ib->length_dw++] = upper_32_bits(src); |
| 706 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
| 707 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
| 708 | } |
| 709 | |
| 710 | /** |
| 711 | * cik_sdma_vm_write_pages - update PTEs by writing them manually |
| 712 | * |
| 713 | * @ib: indirect buffer to fill with commands |
| 714 | * @pe: addr of the page entry |
| 715 | * @value: dst addr to write into pe |
| 716 | * @count: number of page entries to update |
| 717 | * @incr: increase next addr by incr bytes |
| 718 | * |
| 719 | * Update PTEs by writing them manually using sDMA (CIK). |
| 720 | */ |
| 721 | static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
| 722 | uint64_t value, unsigned count, |
| 723 | uint32_t incr) |
| 724 | { |
| 725 | unsigned ndw = count * 2; |
| 726 | |
| 727 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, |
| 728 | SDMA_WRITE_SUB_OPCODE_LINEAR, 0); |
| 729 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
| 730 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
| 731 | ib->ptr[ib->length_dw++] = ndw; |
| 732 | for (; ndw > 0; ndw -= 2) { |
| 733 | ib->ptr[ib->length_dw++] = lower_32_bits(value); |
| 734 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
| 735 | value += incr; |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | /** |
| 740 | * cik_sdma_vm_set_pages - update the page tables using sDMA |
| 741 | * |
| 742 | * @ib: indirect buffer to fill with commands |
| 743 | * @pe: addr of the page entry |
| 744 | * @addr: dst addr to write into pe |
| 745 | * @count: number of page entries to update |
| 746 | * @incr: increase next addr by incr bytes |
| 747 | * @flags: access flags |
| 748 | * |
| 749 | * Update the page tables using sDMA (CIK). |
| 750 | */ |
| 751 | static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, |
| 752 | uint64_t addr, unsigned count, |
| 753 | uint32_t incr, uint32_t flags) |
| 754 | { |
| 755 | /* for physically contiguous pages (vram) */ |
| 756 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); |
| 757 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ |
| 758 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); |
| 759 | ib->ptr[ib->length_dw++] = flags; /* mask */ |
| 760 | ib->ptr[ib->length_dw++] = 0; |
| 761 | ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ |
| 762 | ib->ptr[ib->length_dw++] = upper_32_bits(addr); |
| 763 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
| 764 | ib->ptr[ib->length_dw++] = 0; |
| 765 | ib->ptr[ib->length_dw++] = count; /* number of entries */ |
| 766 | } |
| 767 | |
| 768 | /** |
| 769 | * cik_sdma_vm_pad_ib - pad the IB to the required number of dw |
| 770 | * |
| 771 | * @ib: indirect buffer to fill with padding |
| 772 | * |
| 773 | */ |
| 774 | static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
| 775 | { |
| 776 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
| 777 | u32 pad_count; |
| 778 | int i; |
| 779 | |
| 780 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; |
| 781 | for (i = 0; i < pad_count; i++) |
| 782 | if (sdma && sdma->burst_nop && (i == 0)) |
| 783 | ib->ptr[ib->length_dw++] = |
| 784 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | |
| 785 | SDMA_NOP_COUNT(pad_count - 1); |
| 786 | else |
| 787 | ib->ptr[ib->length_dw++] = |
| 788 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); |
| 789 | } |
| 790 | |
| 791 | /** |
| 792 | * cik_sdma_ring_emit_pipeline_sync - sync the pipeline |
| 793 | * |
| 794 | * @ring: amdgpu_ring pointer |
| 795 | * |
| 796 | * Make sure all previous operations are completed (CIK). |
| 797 | */ |
| 798 | static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
| 799 | { |
| 800 | uint32_t seq = ring->fence_drv.sync_seq; |
| 801 | uint64_t addr = ring->fence_drv.gpu_addr; |
| 802 | |
| 803 | /* wait for idle */ |
| 804 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, |
| 805 | SDMA_POLL_REG_MEM_EXTRA_OP(0) | |
| 806 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ |
| 807 | SDMA_POLL_REG_MEM_EXTRA_M)); |
| 808 | amdgpu_ring_write(ring, addr & 0xfffffffc); |
| 809 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); |
| 810 | amdgpu_ring_write(ring, seq); /* reference */ |
| 811 | amdgpu_ring_write(ring, 0xfffffff); /* mask */ |
| 812 | amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ |
| 813 | } |
| 814 | |
| 815 | /** |
| 816 | * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA |
| 817 | * |
| 818 | * @ring: amdgpu_ring pointer |
| 819 | * @vm: amdgpu_vm pointer |
| 820 | * |
| 821 | * Update the page table base and flush the VM TLB |
| 822 | * using sDMA (CIK). |
| 823 | */ |
| 824 | static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, |
| 825 | unsigned vm_id, uint64_t pd_addr) |
| 826 | { |
| 827 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | |
| 828 | SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ |
| 829 | |
| 830 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 831 | if (vm_id < 8) { |
| 832 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); |
| 833 | } else { |
| 834 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); |
| 835 | } |
| 836 | amdgpu_ring_write(ring, pd_addr >> 12); |
| 837 | |
| 838 | /* flush TLB */ |
| 839 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 840 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); |
| 841 | amdgpu_ring_write(ring, 1 << vm_id); |
| 842 | |
| 843 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); |
| 844 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); |
| 845 | amdgpu_ring_write(ring, 0); |
| 846 | amdgpu_ring_write(ring, 0); /* reference */ |
| 847 | amdgpu_ring_write(ring, 0); /* mask */ |
| 848 | amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ |
| 849 | } |
| 850 | |
| 851 | static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, |
| 852 | bool enable) |
| 853 | { |
| 854 | u32 orig, data; |
| 855 | |
| 856 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { |
| 857 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); |
| 858 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); |
| 859 | } else { |
| 860 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); |
| 861 | data |= 0xff000000; |
| 862 | if (data != orig) |
| 863 | WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); |
| 864 | |
| 865 | orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); |
| 866 | data |= 0xff000000; |
| 867 | if (data != orig) |
| 868 | WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | static void cik_enable_sdma_mgls(struct amdgpu_device *adev, |
| 873 | bool enable) |
| 874 | { |
| 875 | u32 orig, data; |
| 876 | |
| 877 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { |
| 878 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); |
| 879 | data |= 0x100; |
| 880 | if (orig != data) |
| 881 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); |
| 882 | |
| 883 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); |
| 884 | data |= 0x100; |
| 885 | if (orig != data) |
| 886 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); |
| 887 | } else { |
| 888 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); |
| 889 | data &= ~0x100; |
| 890 | if (orig != data) |
| 891 | WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); |
| 892 | |
| 893 | orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); |
| 894 | data &= ~0x100; |
| 895 | if (orig != data) |
| 896 | WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); |
| 897 | } |
| 898 | } |
| 899 | |
| 900 | static int cik_sdma_early_init(void *handle) |
| 901 | { |
| 902 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 903 | |
| 904 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; |
| 905 | |
| 906 | cik_sdma_set_ring_funcs(adev); |
| 907 | cik_sdma_set_irq_funcs(adev); |
| 908 | cik_sdma_set_buffer_funcs(adev); |
| 909 | cik_sdma_set_vm_pte_funcs(adev); |
| 910 | |
| 911 | return 0; |
| 912 | } |
| 913 | |
| 914 | static int cik_sdma_sw_init(void *handle) |
| 915 | { |
| 916 | struct amdgpu_ring *ring; |
| 917 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 918 | int r, i; |
| 919 | |
| 920 | r = cik_sdma_init_microcode(adev); |
| 921 | if (r) { |
| 922 | DRM_ERROR("Failed to load sdma firmware!\n"); |
| 923 | return r; |
| 924 | } |
| 925 | |
| 926 | /* SDMA trap event */ |
| 927 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); |
| 928 | if (r) |
| 929 | return r; |
| 930 | |
| 931 | /* SDMA Privileged inst */ |
| 932 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); |
| 933 | if (r) |
| 934 | return r; |
| 935 | |
| 936 | /* SDMA Privileged inst */ |
| 937 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); |
| 938 | if (r) |
| 939 | return r; |
| 940 | |
| 941 | for (i = 0; i < adev->sdma.num_instances; i++) { |
| 942 | ring = &adev->sdma.instance[i].ring; |
| 943 | ring->ring_obj = NULL; |
| 944 | sprintf(ring->name, "sdma%d", i); |
| 945 | r = amdgpu_ring_init(adev, ring, 1024, |
| 946 | SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, |
| 947 | &adev->sdma.trap_irq, |
| 948 | (i == 0) ? |
| 949 | AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, |
| 950 | AMDGPU_RING_TYPE_SDMA); |
| 951 | if (r) |
| 952 | return r; |
| 953 | } |
| 954 | |
| 955 | return r; |
| 956 | } |
| 957 | |
| 958 | static int cik_sdma_sw_fini(void *handle) |
| 959 | { |
| 960 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 961 | int i; |
| 962 | |
| 963 | for (i = 0; i < adev->sdma.num_instances; i++) |
| 964 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); |
| 965 | |
| 966 | cik_sdma_free_microcode(adev); |
| 967 | return 0; |
| 968 | } |
| 969 | |
| 970 | static int cik_sdma_hw_init(void *handle) |
| 971 | { |
| 972 | int r; |
| 973 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 974 | |
| 975 | r = cik_sdma_start(adev); |
| 976 | if (r) |
| 977 | return r; |
| 978 | |
| 979 | return r; |
| 980 | } |
| 981 | |
| 982 | static int cik_sdma_hw_fini(void *handle) |
| 983 | { |
| 984 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 985 | |
| 986 | cik_sdma_enable(adev, false); |
| 987 | |
| 988 | return 0; |
| 989 | } |
| 990 | |
| 991 | static int cik_sdma_suspend(void *handle) |
| 992 | { |
| 993 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 994 | |
| 995 | return cik_sdma_hw_fini(adev); |
| 996 | } |
| 997 | |
| 998 | static int cik_sdma_resume(void *handle) |
| 999 | { |
| 1000 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1001 | |
| 1002 | cik_sdma_soft_reset(handle); |
| 1003 | |
| 1004 | return cik_sdma_hw_init(adev); |
| 1005 | } |
| 1006 | |
| 1007 | static bool cik_sdma_is_idle(void *handle) |
| 1008 | { |
| 1009 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1010 | u32 tmp = RREG32(mmSRBM_STATUS2); |
| 1011 | |
| 1012 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | |
| 1013 | SRBM_STATUS2__SDMA1_BUSY_MASK)) |
| 1014 | return false; |
| 1015 | |
| 1016 | return true; |
| 1017 | } |
| 1018 | |
| 1019 | static int cik_sdma_wait_for_idle(void *handle) |
| 1020 | { |
| 1021 | unsigned i; |
| 1022 | u32 tmp; |
| 1023 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1024 | |
| 1025 | for (i = 0; i < adev->usec_timeout; i++) { |
| 1026 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | |
| 1027 | SRBM_STATUS2__SDMA1_BUSY_MASK); |
| 1028 | |
| 1029 | if (!tmp) |
| 1030 | return 0; |
| 1031 | udelay(1); |
| 1032 | } |
| 1033 | return -ETIMEDOUT; |
| 1034 | } |
| 1035 | |
| 1036 | static int cik_sdma_soft_reset(void *handle) |
| 1037 | { |
| 1038 | u32 srbm_soft_reset = 0; |
| 1039 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1040 | u32 tmp = RREG32(mmSRBM_STATUS2); |
| 1041 | |
| 1042 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { |
| 1043 | /* sdma0 */ |
| 1044 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); |
| 1045 | tmp |= SDMA0_F32_CNTL__HALT_MASK; |
| 1046 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); |
| 1047 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; |
| 1048 | } |
| 1049 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { |
| 1050 | /* sdma1 */ |
| 1051 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); |
| 1052 | tmp |= SDMA0_F32_CNTL__HALT_MASK; |
| 1053 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); |
| 1054 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; |
| 1055 | } |
| 1056 | |
| 1057 | if (srbm_soft_reset) { |
| 1058 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 1059 | tmp |= srbm_soft_reset; |
| 1060 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); |
| 1061 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 1062 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 1063 | |
| 1064 | udelay(50); |
| 1065 | |
| 1066 | tmp &= ~srbm_soft_reset; |
| 1067 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 1068 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 1069 | |
| 1070 | /* Wait a little for things to settle down */ |
| 1071 | udelay(50); |
| 1072 | } |
| 1073 | |
| 1074 | return 0; |
| 1075 | } |
| 1076 | |
| 1077 | static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, |
| 1078 | struct amdgpu_irq_src *src, |
| 1079 | unsigned type, |
| 1080 | enum amdgpu_interrupt_state state) |
| 1081 | { |
| 1082 | u32 sdma_cntl; |
| 1083 | |
| 1084 | switch (type) { |
| 1085 | case AMDGPU_SDMA_IRQ_TRAP0: |
| 1086 | switch (state) { |
| 1087 | case AMDGPU_IRQ_STATE_DISABLE: |
| 1088 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); |
| 1089 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; |
| 1090 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); |
| 1091 | break; |
| 1092 | case AMDGPU_IRQ_STATE_ENABLE: |
| 1093 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); |
| 1094 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; |
| 1095 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); |
| 1096 | break; |
| 1097 | default: |
| 1098 | break; |
| 1099 | } |
| 1100 | break; |
| 1101 | case AMDGPU_SDMA_IRQ_TRAP1: |
| 1102 | switch (state) { |
| 1103 | case AMDGPU_IRQ_STATE_DISABLE: |
| 1104 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); |
| 1105 | sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; |
| 1106 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); |
| 1107 | break; |
| 1108 | case AMDGPU_IRQ_STATE_ENABLE: |
| 1109 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); |
| 1110 | sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; |
| 1111 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); |
| 1112 | break; |
| 1113 | default: |
| 1114 | break; |
| 1115 | } |
| 1116 | break; |
| 1117 | default: |
| 1118 | break; |
| 1119 | } |
| 1120 | return 0; |
| 1121 | } |
| 1122 | |
| 1123 | static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, |
| 1124 | struct amdgpu_irq_src *source, |
| 1125 | struct amdgpu_iv_entry *entry) |
| 1126 | { |
| 1127 | u8 instance_id, queue_id; |
| 1128 | |
| 1129 | instance_id = (entry->ring_id & 0x3) >> 0; |
| 1130 | queue_id = (entry->ring_id & 0xc) >> 2; |
| 1131 | DRM_DEBUG("IH: SDMA trap\n"); |
| 1132 | switch (instance_id) { |
| 1133 | case 0: |
| 1134 | switch (queue_id) { |
| 1135 | case 0: |
| 1136 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
| 1137 | break; |
| 1138 | case 1: |
| 1139 | /* XXX compute */ |
| 1140 | break; |
| 1141 | case 2: |
| 1142 | /* XXX compute */ |
| 1143 | break; |
| 1144 | } |
| 1145 | break; |
| 1146 | case 1: |
| 1147 | switch (queue_id) { |
| 1148 | case 0: |
| 1149 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
| 1150 | break; |
| 1151 | case 1: |
| 1152 | /* XXX compute */ |
| 1153 | break; |
| 1154 | case 2: |
| 1155 | /* XXX compute */ |
| 1156 | break; |
| 1157 | } |
| 1158 | break; |
| 1159 | } |
| 1160 | |
| 1161 | return 0; |
| 1162 | } |
| 1163 | |
| 1164 | static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, |
| 1165 | struct amdgpu_irq_src *source, |
| 1166 | struct amdgpu_iv_entry *entry) |
| 1167 | { |
| 1168 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); |
| 1169 | schedule_work(&adev->reset_work); |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
| 1173 | static int cik_sdma_set_clockgating_state(void *handle, |
| 1174 | enum amd_clockgating_state state) |
| 1175 | { |
| 1176 | bool gate = false; |
| 1177 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1178 | |
| 1179 | if (state == AMD_CG_STATE_GATE) |
| 1180 | gate = true; |
| 1181 | |
| 1182 | cik_enable_sdma_mgcg(adev, gate); |
| 1183 | cik_enable_sdma_mgls(adev, gate); |
| 1184 | |
| 1185 | return 0; |
| 1186 | } |
| 1187 | |
| 1188 | static int cik_sdma_set_powergating_state(void *handle, |
| 1189 | enum amd_powergating_state state) |
| 1190 | { |
| 1191 | return 0; |
| 1192 | } |
| 1193 | |
| 1194 | const struct amd_ip_funcs cik_sdma_ip_funcs = { |
| 1195 | .name = "cik_sdma", |
| 1196 | .early_init = cik_sdma_early_init, |
| 1197 | .late_init = NULL, |
| 1198 | .sw_init = cik_sdma_sw_init, |
| 1199 | .sw_fini = cik_sdma_sw_fini, |
| 1200 | .hw_init = cik_sdma_hw_init, |
| 1201 | .hw_fini = cik_sdma_hw_fini, |
| 1202 | .suspend = cik_sdma_suspend, |
| 1203 | .resume = cik_sdma_resume, |
| 1204 | .is_idle = cik_sdma_is_idle, |
| 1205 | .wait_for_idle = cik_sdma_wait_for_idle, |
| 1206 | .soft_reset = cik_sdma_soft_reset, |
| 1207 | .set_clockgating_state = cik_sdma_set_clockgating_state, |
| 1208 | .set_powergating_state = cik_sdma_set_powergating_state, |
| 1209 | }; |
| 1210 | |
| 1211 | static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { |
| 1212 | .get_rptr = cik_sdma_ring_get_rptr, |
| 1213 | .get_wptr = cik_sdma_ring_get_wptr, |
| 1214 | .set_wptr = cik_sdma_ring_set_wptr, |
| 1215 | .parse_cs = NULL, |
| 1216 | .emit_ib = cik_sdma_ring_emit_ib, |
| 1217 | .emit_fence = cik_sdma_ring_emit_fence, |
| 1218 | .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, |
| 1219 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
| 1220 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
| 1221 | .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, |
| 1222 | .test_ring = cik_sdma_ring_test_ring, |
| 1223 | .test_ib = cik_sdma_ring_test_ib, |
| 1224 | .insert_nop = cik_sdma_ring_insert_nop, |
| 1225 | .pad_ib = cik_sdma_ring_pad_ib, |
| 1226 | }; |
| 1227 | |
| 1228 | static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) |
| 1229 | { |
| 1230 | int i; |
| 1231 | |
| 1232 | for (i = 0; i < adev->sdma.num_instances; i++) |
| 1233 | adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; |
| 1234 | } |
| 1235 | |
| 1236 | static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { |
| 1237 | .set = cik_sdma_set_trap_irq_state, |
| 1238 | .process = cik_sdma_process_trap_irq, |
| 1239 | }; |
| 1240 | |
| 1241 | static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { |
| 1242 | .process = cik_sdma_process_illegal_inst_irq, |
| 1243 | }; |
| 1244 | |
| 1245 | static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) |
| 1246 | { |
| 1247 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
| 1248 | adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; |
| 1249 | adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; |
| 1250 | } |
| 1251 | |
| 1252 | /** |
| 1253 | * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine |
| 1254 | * |
| 1255 | * @ring: amdgpu_ring structure holding ring information |
| 1256 | * @src_offset: src GPU address |
| 1257 | * @dst_offset: dst GPU address |
| 1258 | * @byte_count: number of bytes to xfer |
| 1259 | * |
| 1260 | * Copy GPU buffers using the DMA engine (CIK). |
| 1261 | * Used by the amdgpu ttm implementation to move pages if |
| 1262 | * registered as the asic copy callback. |
| 1263 | */ |
| 1264 | static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, |
| 1265 | uint64_t src_offset, |
| 1266 | uint64_t dst_offset, |
| 1267 | uint32_t byte_count) |
| 1268 | { |
| 1269 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); |
| 1270 | ib->ptr[ib->length_dw++] = byte_count; |
| 1271 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
| 1272 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); |
| 1273 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); |
| 1274 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); |
| 1275 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); |
| 1276 | } |
| 1277 | |
| 1278 | /** |
| 1279 | * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine |
| 1280 | * |
| 1281 | * @ring: amdgpu_ring structure holding ring information |
| 1282 | * @src_data: value to write to buffer |
| 1283 | * @dst_offset: dst GPU address |
| 1284 | * @byte_count: number of bytes to xfer |
| 1285 | * |
| 1286 | * Fill GPU buffers using the DMA engine (CIK). |
| 1287 | */ |
| 1288 | static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, |
| 1289 | uint32_t src_data, |
| 1290 | uint64_t dst_offset, |
| 1291 | uint32_t byte_count) |
| 1292 | { |
| 1293 | ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); |
| 1294 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); |
| 1295 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); |
| 1296 | ib->ptr[ib->length_dw++] = src_data; |
| 1297 | ib->ptr[ib->length_dw++] = byte_count; |
| 1298 | } |
| 1299 | |
| 1300 | static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { |
| 1301 | .copy_max_bytes = 0x1fffff, |
| 1302 | .copy_num_dw = 7, |
| 1303 | .emit_copy_buffer = cik_sdma_emit_copy_buffer, |
| 1304 | |
| 1305 | .fill_max_bytes = 0x1fffff, |
| 1306 | .fill_num_dw = 5, |
| 1307 | .emit_fill_buffer = cik_sdma_emit_fill_buffer, |
| 1308 | }; |
| 1309 | |
| 1310 | static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) |
| 1311 | { |
| 1312 | if (adev->mman.buffer_funcs == NULL) { |
| 1313 | adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; |
| 1314 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
| 1315 | } |
| 1316 | } |
| 1317 | |
| 1318 | static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { |
| 1319 | .copy_pte = cik_sdma_vm_copy_pte, |
| 1320 | .write_pte = cik_sdma_vm_write_pte, |
| 1321 | .set_pte_pde = cik_sdma_vm_set_pte_pde, |
| 1322 | }; |
| 1323 | |
| 1324 | static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) |
| 1325 | { |
| 1326 | unsigned i; |
| 1327 | |
| 1328 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
| 1329 | adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; |
| 1330 | for (i = 0; i < adev->sdma.num_instances; i++) |
| 1331 | adev->vm_manager.vm_pte_rings[i] = |
| 1332 | &adev->sdma.instance[i].ring; |
| 1333 | |
| 1334 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; |
| 1335 | } |
| 1336 | } |