| 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/firmware.h> |
| 24 | #include "drmP.h" |
| 25 | #include "amdgpu.h" |
| 26 | #include "cikd.h" |
| 27 | #include "cik.h" |
| 28 | #include "gmc_v7_0.h" |
| 29 | #include "amdgpu_ucode.h" |
| 30 | |
| 31 | #include "bif/bif_4_1_d.h" |
| 32 | #include "bif/bif_4_1_sh_mask.h" |
| 33 | |
| 34 | #include "gmc/gmc_7_1_d.h" |
| 35 | #include "gmc/gmc_7_1_sh_mask.h" |
| 36 | |
| 37 | #include "oss/oss_2_0_d.h" |
| 38 | #include "oss/oss_2_0_sh_mask.h" |
| 39 | |
| 40 | static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev); |
| 41 | static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); |
| 42 | |
| 43 | MODULE_FIRMWARE("radeon/bonaire_mc.bin"); |
| 44 | MODULE_FIRMWARE("radeon/hawaii_mc.bin"); |
| 45 | |
| 46 | /** |
| 47 | * gmc8_mc_wait_for_idle - wait for MC idle callback. |
| 48 | * |
| 49 | * @adev: amdgpu_device pointer |
| 50 | * |
| 51 | * Wait for the MC (memory controller) to be idle. |
| 52 | * (evergreen+). |
| 53 | * Returns 0 if the MC is idle, -1 if not. |
| 54 | */ |
| 55 | int gmc_v7_0_mc_wait_for_idle(struct amdgpu_device *adev) |
| 56 | { |
| 57 | unsigned i; |
| 58 | u32 tmp; |
| 59 | |
| 60 | for (i = 0; i < adev->usec_timeout; i++) { |
| 61 | /* read MC_STATUS */ |
| 62 | tmp = RREG32(mmSRBM_STATUS) & 0x1F00; |
| 63 | if (!tmp) |
| 64 | return 0; |
| 65 | udelay(1); |
| 66 | } |
| 67 | return -1; |
| 68 | } |
| 69 | |
| 70 | void gmc_v7_0_mc_stop(struct amdgpu_device *adev, |
| 71 | struct amdgpu_mode_mc_save *save) |
| 72 | { |
| 73 | u32 blackout; |
| 74 | |
| 75 | if (adev->mode_info.num_crtc) |
| 76 | amdgpu_display_stop_mc_access(adev, save); |
| 77 | |
| 78 | amdgpu_asic_wait_for_mc_idle(adev); |
| 79 | |
| 80 | blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
| 81 | if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { |
| 82 | /* Block CPU access */ |
| 83 | WREG32(mmBIF_FB_EN, 0); |
| 84 | /* blackout the MC */ |
| 85 | blackout = REG_SET_FIELD(blackout, |
| 86 | MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); |
| 87 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); |
| 88 | } |
| 89 | /* wait for the MC to settle */ |
| 90 | udelay(100); |
| 91 | } |
| 92 | |
| 93 | void gmc_v7_0_mc_resume(struct amdgpu_device *adev, |
| 94 | struct amdgpu_mode_mc_save *save) |
| 95 | { |
| 96 | u32 tmp; |
| 97 | |
| 98 | /* unblackout the MC */ |
| 99 | tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
| 100 | tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); |
| 101 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); |
| 102 | /* allow CPU access */ |
| 103 | tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); |
| 104 | tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); |
| 105 | WREG32(mmBIF_FB_EN, tmp); |
| 106 | |
| 107 | if (adev->mode_info.num_crtc) |
| 108 | amdgpu_display_resume_mc_access(adev, save); |
| 109 | } |
| 110 | |
| 111 | /** |
| 112 | * gmc_v7_0_init_microcode - load ucode images from disk |
| 113 | * |
| 114 | * @adev: amdgpu_device pointer |
| 115 | * |
| 116 | * Use the firmware interface to load the ucode images into |
| 117 | * the driver (not loaded into hw). |
| 118 | * Returns 0 on success, error on failure. |
| 119 | */ |
| 120 | static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) |
| 121 | { |
| 122 | const char *chip_name; |
| 123 | char fw_name[30]; |
| 124 | int err; |
| 125 | |
| 126 | DRM_DEBUG("\n"); |
| 127 | |
| 128 | switch (adev->asic_type) { |
| 129 | case CHIP_BONAIRE: |
| 130 | chip_name = "bonaire"; |
| 131 | break; |
| 132 | case CHIP_HAWAII: |
| 133 | chip_name = "hawaii"; |
| 134 | break; |
| 135 | case CHIP_KAVERI: |
| 136 | case CHIP_KABINI: |
| 137 | return 0; |
| 138 | default: BUG(); |
| 139 | } |
| 140 | |
| 141 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); |
| 142 | err = request_firmware(&adev->mc.fw, fw_name, adev->dev); |
| 143 | if (err) |
| 144 | goto out; |
| 145 | err = amdgpu_ucode_validate(adev->mc.fw); |
| 146 | |
| 147 | out: |
| 148 | if (err) { |
| 149 | printk(KERN_ERR |
| 150 | "cik_mc: Failed to load firmware \"%s\"\n", |
| 151 | fw_name); |
| 152 | release_firmware(adev->mc.fw); |
| 153 | adev->mc.fw = NULL; |
| 154 | } |
| 155 | return err; |
| 156 | } |
| 157 | |
| 158 | /** |
| 159 | * gmc_v7_0_mc_load_microcode - load MC ucode into the hw |
| 160 | * |
| 161 | * @adev: amdgpu_device pointer |
| 162 | * |
| 163 | * Load the GDDR MC ucode into the hw (CIK). |
| 164 | * Returns 0 on success, error on failure. |
| 165 | */ |
| 166 | static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) |
| 167 | { |
| 168 | const struct mc_firmware_header_v1_0 *hdr; |
| 169 | const __le32 *fw_data = NULL; |
| 170 | const __le32 *io_mc_regs = NULL; |
| 171 | u32 running, blackout = 0; |
| 172 | int i, ucode_size, regs_size; |
| 173 | |
| 174 | if (!adev->mc.fw) |
| 175 | return -EINVAL; |
| 176 | |
| 177 | hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; |
| 178 | amdgpu_ucode_print_mc_hdr(&hdr->header); |
| 179 | |
| 180 | adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); |
| 181 | regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); |
| 182 | io_mc_regs = (const __le32 *) |
| 183 | (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); |
| 184 | ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
| 185 | fw_data = (const __le32 *) |
| 186 | (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
| 187 | |
| 188 | running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); |
| 189 | |
| 190 | if (running == 0) { |
| 191 | if (running) { |
| 192 | blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); |
| 193 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); |
| 194 | } |
| 195 | |
| 196 | /* reset the engine and set to writable */ |
| 197 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); |
| 198 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); |
| 199 | |
| 200 | /* load mc io regs */ |
| 201 | for (i = 0; i < regs_size; i++) { |
| 202 | WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); |
| 203 | WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); |
| 204 | } |
| 205 | /* load the MC ucode */ |
| 206 | for (i = 0; i < ucode_size; i++) |
| 207 | WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); |
| 208 | |
| 209 | /* put the engine back into the active state */ |
| 210 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); |
| 211 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); |
| 212 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); |
| 213 | |
| 214 | /* wait for training to complete */ |
| 215 | for (i = 0; i < adev->usec_timeout; i++) { |
| 216 | if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), |
| 217 | MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) |
| 218 | break; |
| 219 | udelay(1); |
| 220 | } |
| 221 | for (i = 0; i < adev->usec_timeout; i++) { |
| 222 | if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), |
| 223 | MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) |
| 224 | break; |
| 225 | udelay(1); |
| 226 | } |
| 227 | |
| 228 | if (running) |
| 229 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); |
| 230 | } |
| 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
| 235 | static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, |
| 236 | struct amdgpu_mc *mc) |
| 237 | { |
| 238 | if (mc->mc_vram_size > 0xFFC0000000ULL) { |
| 239 | /* leave room for at least 1024M GTT */ |
| 240 | dev_warn(adev->dev, "limiting VRAM\n"); |
| 241 | mc->real_vram_size = 0xFFC0000000ULL; |
| 242 | mc->mc_vram_size = 0xFFC0000000ULL; |
| 243 | } |
| 244 | amdgpu_vram_location(adev, &adev->mc, 0); |
| 245 | adev->mc.gtt_base_align = 0; |
| 246 | amdgpu_gtt_location(adev, mc); |
| 247 | } |
| 248 | |
| 249 | /** |
| 250 | * gmc_v7_0_mc_program - program the GPU memory controller |
| 251 | * |
| 252 | * @adev: amdgpu_device pointer |
| 253 | * |
| 254 | * Set the location of vram, gart, and AGP in the GPU's |
| 255 | * physical address space (CIK). |
| 256 | */ |
| 257 | static void gmc_v7_0_mc_program(struct amdgpu_device *adev) |
| 258 | { |
| 259 | struct amdgpu_mode_mc_save save; |
| 260 | u32 tmp; |
| 261 | int i, j; |
| 262 | |
| 263 | /* Initialize HDP */ |
| 264 | for (i = 0, j = 0; i < 32; i++, j += 0x6) { |
| 265 | WREG32((0xb05 + j), 0x00000000); |
| 266 | WREG32((0xb06 + j), 0x00000000); |
| 267 | WREG32((0xb07 + j), 0x00000000); |
| 268 | WREG32((0xb08 + j), 0x00000000); |
| 269 | WREG32((0xb09 + j), 0x00000000); |
| 270 | } |
| 271 | WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); |
| 272 | |
| 273 | if (adev->mode_info.num_crtc) |
| 274 | amdgpu_display_set_vga_render_state(adev, false); |
| 275 | |
| 276 | gmc_v7_0_mc_stop(adev, &save); |
| 277 | if (amdgpu_asic_wait_for_mc_idle(adev)) { |
| 278 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); |
| 279 | } |
| 280 | /* Update configuration */ |
| 281 | WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| 282 | adev->mc.vram_start >> 12); |
| 283 | WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| 284 | adev->mc.vram_end >> 12); |
| 285 | WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, |
| 286 | adev->vram_scratch.gpu_addr >> 12); |
| 287 | tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; |
| 288 | tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); |
| 289 | WREG32(mmMC_VM_FB_LOCATION, tmp); |
| 290 | /* XXX double check these! */ |
| 291 | WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); |
| 292 | WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); |
| 293 | WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
| 294 | WREG32(mmMC_VM_AGP_BASE, 0); |
| 295 | WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); |
| 296 | WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); |
| 297 | if (amdgpu_asic_wait_for_mc_idle(adev)) { |
| 298 | dev_warn(adev->dev, "Wait for MC idle timedout !\n"); |
| 299 | } |
| 300 | gmc_v7_0_mc_resume(adev, &save); |
| 301 | |
| 302 | WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); |
| 303 | |
| 304 | tmp = RREG32(mmHDP_MISC_CNTL); |
| 305 | tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); |
| 306 | WREG32(mmHDP_MISC_CNTL, tmp); |
| 307 | |
| 308 | tmp = RREG32(mmHDP_HOST_PATH_CNTL); |
| 309 | WREG32(mmHDP_HOST_PATH_CNTL, tmp); |
| 310 | } |
| 311 | |
| 312 | /** |
| 313 | * gmc_v7_0_mc_init - initialize the memory controller driver params |
| 314 | * |
| 315 | * @adev: amdgpu_device pointer |
| 316 | * |
| 317 | * Look up the amount of vram, vram width, and decide how to place |
| 318 | * vram and gart within the GPU's physical address space (CIK). |
| 319 | * Returns 0 for success. |
| 320 | */ |
| 321 | static int gmc_v7_0_mc_init(struct amdgpu_device *adev) |
| 322 | { |
| 323 | u32 tmp; |
| 324 | int chansize, numchan; |
| 325 | |
| 326 | /* Get VRAM informations */ |
| 327 | tmp = RREG32(mmMC_ARB_RAMCFG); |
| 328 | if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { |
| 329 | chansize = 64; |
| 330 | } else { |
| 331 | chansize = 32; |
| 332 | } |
| 333 | tmp = RREG32(mmMC_SHARED_CHMAP); |
| 334 | switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { |
| 335 | case 0: |
| 336 | default: |
| 337 | numchan = 1; |
| 338 | break; |
| 339 | case 1: |
| 340 | numchan = 2; |
| 341 | break; |
| 342 | case 2: |
| 343 | numchan = 4; |
| 344 | break; |
| 345 | case 3: |
| 346 | numchan = 8; |
| 347 | break; |
| 348 | case 4: |
| 349 | numchan = 3; |
| 350 | break; |
| 351 | case 5: |
| 352 | numchan = 6; |
| 353 | break; |
| 354 | case 6: |
| 355 | numchan = 10; |
| 356 | break; |
| 357 | case 7: |
| 358 | numchan = 12; |
| 359 | break; |
| 360 | case 8: |
| 361 | numchan = 16; |
| 362 | break; |
| 363 | } |
| 364 | adev->mc.vram_width = numchan * chansize; |
| 365 | /* Could aper size report 0 ? */ |
| 366 | adev->mc.aper_base = pci_resource_start(adev->pdev, 0); |
| 367 | adev->mc.aper_size = pci_resource_len(adev->pdev, 0); |
| 368 | /* size in MB on si */ |
| 369 | adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
| 370 | adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; |
| 371 | adev->mc.visible_vram_size = adev->mc.aper_size; |
| 372 | |
| 373 | /* In case the PCI BAR is larger than the actual amount of vram */ |
| 374 | if (adev->mc.visible_vram_size > adev->mc.real_vram_size) |
| 375 | adev->mc.visible_vram_size = adev->mc.real_vram_size; |
| 376 | |
| 377 | /* unless the user had overridden it, set the gart |
| 378 | * size equal to the 1024 or vram, whichever is larger. |
| 379 | */ |
| 380 | if (amdgpu_gart_size == -1) |
| 381 | adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); |
| 382 | else |
| 383 | adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; |
| 384 | |
| 385 | gmc_v7_0_vram_gtt_location(adev, &adev->mc); |
| 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | /* |
| 391 | * GART |
| 392 | * VMID 0 is the physical GPU addresses as used by the kernel. |
| 393 | * VMIDs 1-15 are used for userspace clients and are handled |
| 394 | * by the amdgpu vm/hsa code. |
| 395 | */ |
| 396 | |
| 397 | /** |
| 398 | * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback |
| 399 | * |
| 400 | * @adev: amdgpu_device pointer |
| 401 | * @vmid: vm instance to flush |
| 402 | * |
| 403 | * Flush the TLB for the requested page table (CIK). |
| 404 | */ |
| 405 | static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, |
| 406 | uint32_t vmid) |
| 407 | { |
| 408 | /* flush hdp cache */ |
| 409 | WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); |
| 410 | |
| 411 | /* bits 0-15 are the VM contexts0-15 */ |
| 412 | WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); |
| 413 | } |
| 414 | |
| 415 | /** |
| 416 | * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO |
| 417 | * |
| 418 | * @adev: amdgpu_device pointer |
| 419 | * @cpu_pt_addr: cpu address of the page table |
| 420 | * @gpu_page_idx: entry in the page table to update |
| 421 | * @addr: dst addr to write into pte/pde |
| 422 | * @flags: access flags |
| 423 | * |
| 424 | * Update the page tables using the CPU. |
| 425 | */ |
| 426 | static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, |
| 427 | void *cpu_pt_addr, |
| 428 | uint32_t gpu_page_idx, |
| 429 | uint64_t addr, |
| 430 | uint32_t flags) |
| 431 | { |
| 432 | void __iomem *ptr = (void *)cpu_pt_addr; |
| 433 | uint64_t value; |
| 434 | |
| 435 | value = addr & 0xFFFFFFFFFFFFF000ULL; |
| 436 | value |= flags; |
| 437 | writeq(value, ptr + (gpu_page_idx * 8)); |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | /** |
| 443 | * gmc_v8_0_set_fault_enable_default - update VM fault handling |
| 444 | * |
| 445 | * @adev: amdgpu_device pointer |
| 446 | * @value: true redirects VM faults to the default page |
| 447 | */ |
| 448 | static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, |
| 449 | bool value) |
| 450 | { |
| 451 | u32 tmp; |
| 452 | |
| 453 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
| 454 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 455 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 456 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 457 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 458 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 459 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 460 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 461 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 462 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 463 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 464 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 465 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 466 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
| 467 | } |
| 468 | |
| 469 | /** |
| 470 | * gmc_v7_0_gart_enable - gart enable |
| 471 | * |
| 472 | * @adev: amdgpu_device pointer |
| 473 | * |
| 474 | * This sets up the TLBs, programs the page tables for VMID0, |
| 475 | * sets up the hw for VMIDs 1-15 which are allocated on |
| 476 | * demand, and sets up the global locations for the LDS, GDS, |
| 477 | * and GPUVM for FSA64 clients (CIK). |
| 478 | * Returns 0 for success, errors for failure. |
| 479 | */ |
| 480 | static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) |
| 481 | { |
| 482 | int r, i; |
| 483 | u32 tmp; |
| 484 | |
| 485 | if (adev->gart.robj == NULL) { |
| 486 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); |
| 487 | return -EINVAL; |
| 488 | } |
| 489 | r = amdgpu_gart_table_vram_pin(adev); |
| 490 | if (r) |
| 491 | return r; |
| 492 | /* Setup TLB control */ |
| 493 | tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); |
| 494 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); |
| 495 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); |
| 496 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); |
| 497 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); |
| 498 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); |
| 499 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); |
| 500 | /* Setup L2 cache */ |
| 501 | tmp = RREG32(mmVM_L2_CNTL); |
| 502 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); |
| 503 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); |
| 504 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); |
| 505 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); |
| 506 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); |
| 507 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); |
| 508 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); |
| 509 | WREG32(mmVM_L2_CNTL, tmp); |
| 510 | tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); |
| 511 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); |
| 512 | WREG32(mmVM_L2_CNTL2, tmp); |
| 513 | tmp = RREG32(mmVM_L2_CNTL3); |
| 514 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); |
| 515 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); |
| 516 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); |
| 517 | WREG32(mmVM_L2_CNTL3, tmp); |
| 518 | /* setup context0 */ |
| 519 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); |
| 520 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); |
| 521 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); |
| 522 | WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| 523 | (u32)(adev->dummy_page.addr >> 12)); |
| 524 | WREG32(mmVM_CONTEXT0_CNTL2, 0); |
| 525 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
| 526 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); |
| 527 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); |
| 528 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 529 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
| 530 | |
| 531 | WREG32(0x575, 0); |
| 532 | WREG32(0x576, 0); |
| 533 | WREG32(0x577, 0); |
| 534 | |
| 535 | /* empty context1-15 */ |
| 536 | /* FIXME start with 4G, once using 2 level pt switch to full |
| 537 | * vm size space |
| 538 | */ |
| 539 | /* set vm size, must be a multiple of 4 */ |
| 540 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); |
| 541 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); |
| 542 | for (i = 1; i < 16; i++) { |
| 543 | if (i < 8) |
| 544 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, |
| 545 | adev->gart.table_addr >> 12); |
| 546 | else |
| 547 | WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, |
| 548 | adev->gart.table_addr >> 12); |
| 549 | } |
| 550 | |
| 551 | /* enable context1-15 */ |
| 552 | WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, |
| 553 | (u32)(adev->dummy_page.addr >> 12)); |
| 554 | WREG32(mmVM_CONTEXT1_CNTL2, 4); |
| 555 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
| 556 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); |
| 557 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); |
| 558 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, |
| 559 | amdgpu_vm_block_size - 9); |
| 560 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
| 561 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
| 562 | gmc_v7_0_set_fault_enable_default(adev, false); |
| 563 | else |
| 564 | gmc_v7_0_set_fault_enable_default(adev, true); |
| 565 | |
| 566 | if (adev->asic_type == CHIP_KAVERI) { |
| 567 | tmp = RREG32(mmCHUB_CONTROL); |
| 568 | tmp &= ~BYPASS_VM; |
| 569 | WREG32(mmCHUB_CONTROL, tmp); |
| 570 | } |
| 571 | |
| 572 | gmc_v7_0_gart_flush_gpu_tlb(adev, 0); |
| 573 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 574 | (unsigned)(adev->mc.gtt_size >> 20), |
| 575 | (unsigned long long)adev->gart.table_addr); |
| 576 | adev->gart.ready = true; |
| 577 | return 0; |
| 578 | } |
| 579 | |
| 580 | static int gmc_v7_0_gart_init(struct amdgpu_device *adev) |
| 581 | { |
| 582 | int r; |
| 583 | |
| 584 | if (adev->gart.robj) { |
| 585 | WARN(1, "R600 PCIE GART already initialized\n"); |
| 586 | return 0; |
| 587 | } |
| 588 | /* Initialize common gart structure */ |
| 589 | r = amdgpu_gart_init(adev); |
| 590 | if (r) |
| 591 | return r; |
| 592 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; |
| 593 | return amdgpu_gart_table_vram_alloc(adev); |
| 594 | } |
| 595 | |
| 596 | /** |
| 597 | * gmc_v7_0_gart_disable - gart disable |
| 598 | * |
| 599 | * @adev: amdgpu_device pointer |
| 600 | * |
| 601 | * This disables all VM page table (CIK). |
| 602 | */ |
| 603 | static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) |
| 604 | { |
| 605 | u32 tmp; |
| 606 | |
| 607 | /* Disable all tables */ |
| 608 | WREG32(mmVM_CONTEXT0_CNTL, 0); |
| 609 | WREG32(mmVM_CONTEXT1_CNTL, 0); |
| 610 | /* Setup TLB control */ |
| 611 | tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); |
| 612 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); |
| 613 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); |
| 614 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); |
| 615 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); |
| 616 | /* Setup L2 cache */ |
| 617 | tmp = RREG32(mmVM_L2_CNTL); |
| 618 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); |
| 619 | WREG32(mmVM_L2_CNTL, tmp); |
| 620 | WREG32(mmVM_L2_CNTL2, 0); |
| 621 | amdgpu_gart_table_vram_unpin(adev); |
| 622 | } |
| 623 | |
| 624 | /** |
| 625 | * gmc_v7_0_gart_fini - vm fini callback |
| 626 | * |
| 627 | * @adev: amdgpu_device pointer |
| 628 | * |
| 629 | * Tears down the driver GART/VM setup (CIK). |
| 630 | */ |
| 631 | static void gmc_v7_0_gart_fini(struct amdgpu_device *adev) |
| 632 | { |
| 633 | amdgpu_gart_table_vram_free(adev); |
| 634 | amdgpu_gart_fini(adev); |
| 635 | } |
| 636 | |
| 637 | /* |
| 638 | * vm |
| 639 | * VMID 0 is the physical GPU addresses as used by the kernel. |
| 640 | * VMIDs 1-15 are used for userspace clients and are handled |
| 641 | * by the amdgpu vm/hsa code. |
| 642 | */ |
| 643 | /** |
| 644 | * gmc_v7_0_vm_init - cik vm init callback |
| 645 | * |
| 646 | * @adev: amdgpu_device pointer |
| 647 | * |
| 648 | * Inits cik specific vm parameters (number of VMs, base of vram for |
| 649 | * VMIDs 1-15) (CIK). |
| 650 | * Returns 0 for success. |
| 651 | */ |
| 652 | static int gmc_v7_0_vm_init(struct amdgpu_device *adev) |
| 653 | { |
| 654 | /* |
| 655 | * number of VMs |
| 656 | * VMID 0 is reserved for System |
| 657 | * amdgpu graphics/compute will use VMIDs 1-7 |
| 658 | * amdkfd will use VMIDs 8-15 |
| 659 | */ |
| 660 | adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; |
| 661 | |
| 662 | /* base offset of vram pages */ |
| 663 | if (adev->flags & AMD_IS_APU) { |
| 664 | u64 tmp = RREG32(mmMC_VM_FB_OFFSET); |
| 665 | tmp <<= 22; |
| 666 | adev->vm_manager.vram_base_offset = tmp; |
| 667 | } else |
| 668 | adev->vm_manager.vram_base_offset = 0; |
| 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | /** |
| 674 | * gmc_v7_0_vm_fini - cik vm fini callback |
| 675 | * |
| 676 | * @adev: amdgpu_device pointer |
| 677 | * |
| 678 | * Tear down any asic specific VM setup (CIK). |
| 679 | */ |
| 680 | static void gmc_v7_0_vm_fini(struct amdgpu_device *adev) |
| 681 | { |
| 682 | } |
| 683 | |
| 684 | /** |
| 685 | * gmc_v7_0_vm_decode_fault - print human readable fault info |
| 686 | * |
| 687 | * @adev: amdgpu_device pointer |
| 688 | * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value |
| 689 | * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value |
| 690 | * |
| 691 | * Print human readable fault information (CIK). |
| 692 | */ |
| 693 | static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, |
| 694 | u32 status, u32 addr, u32 mc_client) |
| 695 | { |
| 696 | u32 mc_id; |
| 697 | u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); |
| 698 | u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
| 699 | PROTECTIONS); |
| 700 | char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, |
| 701 | (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; |
| 702 | |
| 703 | mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
| 704 | MEMORY_CLIENT_ID); |
| 705 | |
| 706 | printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", |
| 707 | protections, vmid, addr, |
| 708 | REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, |
| 709 | MEMORY_CLIENT_RW) ? |
| 710 | "write" : "read", block, mc_client, mc_id); |
| 711 | } |
| 712 | |
| 713 | |
| 714 | static const u32 mc_cg_registers[] = { |
| 715 | mmMC_HUB_MISC_HUB_CG, |
| 716 | mmMC_HUB_MISC_SIP_CG, |
| 717 | mmMC_HUB_MISC_VM_CG, |
| 718 | mmMC_XPB_CLK_GAT, |
| 719 | mmATC_MISC_CG, |
| 720 | mmMC_CITF_MISC_WR_CG, |
| 721 | mmMC_CITF_MISC_RD_CG, |
| 722 | mmMC_CITF_MISC_VM_CG, |
| 723 | mmVM_L2_CG, |
| 724 | }; |
| 725 | |
| 726 | static const u32 mc_cg_ls_en[] = { |
| 727 | MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, |
| 728 | MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, |
| 729 | MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, |
| 730 | MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, |
| 731 | ATC_MISC_CG__MEM_LS_ENABLE_MASK, |
| 732 | MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, |
| 733 | MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, |
| 734 | MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, |
| 735 | VM_L2_CG__MEM_LS_ENABLE_MASK, |
| 736 | }; |
| 737 | |
| 738 | static const u32 mc_cg_en[] = { |
| 739 | MC_HUB_MISC_HUB_CG__ENABLE_MASK, |
| 740 | MC_HUB_MISC_SIP_CG__ENABLE_MASK, |
| 741 | MC_HUB_MISC_VM_CG__ENABLE_MASK, |
| 742 | MC_XPB_CLK_GAT__ENABLE_MASK, |
| 743 | ATC_MISC_CG__ENABLE_MASK, |
| 744 | MC_CITF_MISC_WR_CG__ENABLE_MASK, |
| 745 | MC_CITF_MISC_RD_CG__ENABLE_MASK, |
| 746 | MC_CITF_MISC_VM_CG__ENABLE_MASK, |
| 747 | VM_L2_CG__ENABLE_MASK, |
| 748 | }; |
| 749 | |
| 750 | static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, |
| 751 | bool enable) |
| 752 | { |
| 753 | int i; |
| 754 | u32 orig, data; |
| 755 | |
| 756 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { |
| 757 | orig = data = RREG32(mc_cg_registers[i]); |
| 758 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) |
| 759 | data |= mc_cg_ls_en[i]; |
| 760 | else |
| 761 | data &= ~mc_cg_ls_en[i]; |
| 762 | if (data != orig) |
| 763 | WREG32(mc_cg_registers[i], data); |
| 764 | } |
| 765 | } |
| 766 | |
| 767 | static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, |
| 768 | bool enable) |
| 769 | { |
| 770 | int i; |
| 771 | u32 orig, data; |
| 772 | |
| 773 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { |
| 774 | orig = data = RREG32(mc_cg_registers[i]); |
| 775 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) |
| 776 | data |= mc_cg_en[i]; |
| 777 | else |
| 778 | data &= ~mc_cg_en[i]; |
| 779 | if (data != orig) |
| 780 | WREG32(mc_cg_registers[i], data); |
| 781 | } |
| 782 | } |
| 783 | |
| 784 | static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, |
| 785 | bool enable) |
| 786 | { |
| 787 | u32 orig, data; |
| 788 | |
| 789 | orig = data = RREG32_PCIE(ixPCIE_CNTL2); |
| 790 | |
| 791 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { |
| 792 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); |
| 793 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); |
| 794 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); |
| 795 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); |
| 796 | } else { |
| 797 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); |
| 798 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); |
| 799 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); |
| 800 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); |
| 801 | } |
| 802 | |
| 803 | if (orig != data) |
| 804 | WREG32_PCIE(ixPCIE_CNTL2, data); |
| 805 | } |
| 806 | |
| 807 | static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, |
| 808 | bool enable) |
| 809 | { |
| 810 | u32 orig, data; |
| 811 | |
| 812 | orig = data = RREG32(mmHDP_HOST_PATH_CNTL); |
| 813 | |
| 814 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) |
| 815 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); |
| 816 | else |
| 817 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); |
| 818 | |
| 819 | if (orig != data) |
| 820 | WREG32(mmHDP_HOST_PATH_CNTL, data); |
| 821 | } |
| 822 | |
| 823 | static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, |
| 824 | bool enable) |
| 825 | { |
| 826 | u32 orig, data; |
| 827 | |
| 828 | orig = data = RREG32(mmHDP_MEM_POWER_LS); |
| 829 | |
| 830 | if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) |
| 831 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); |
| 832 | else |
| 833 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); |
| 834 | |
| 835 | if (orig != data) |
| 836 | WREG32(mmHDP_MEM_POWER_LS, data); |
| 837 | } |
| 838 | |
| 839 | static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) |
| 840 | { |
| 841 | switch (mc_seq_vram_type) { |
| 842 | case MC_SEQ_MISC0__MT__GDDR1: |
| 843 | return AMDGPU_VRAM_TYPE_GDDR1; |
| 844 | case MC_SEQ_MISC0__MT__DDR2: |
| 845 | return AMDGPU_VRAM_TYPE_DDR2; |
| 846 | case MC_SEQ_MISC0__MT__GDDR3: |
| 847 | return AMDGPU_VRAM_TYPE_GDDR3; |
| 848 | case MC_SEQ_MISC0__MT__GDDR4: |
| 849 | return AMDGPU_VRAM_TYPE_GDDR4; |
| 850 | case MC_SEQ_MISC0__MT__GDDR5: |
| 851 | return AMDGPU_VRAM_TYPE_GDDR5; |
| 852 | case MC_SEQ_MISC0__MT__HBM: |
| 853 | return AMDGPU_VRAM_TYPE_HBM; |
| 854 | case MC_SEQ_MISC0__MT__DDR3: |
| 855 | return AMDGPU_VRAM_TYPE_DDR3; |
| 856 | default: |
| 857 | return AMDGPU_VRAM_TYPE_UNKNOWN; |
| 858 | } |
| 859 | } |
| 860 | |
| 861 | static int gmc_v7_0_early_init(void *handle) |
| 862 | { |
| 863 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 864 | |
| 865 | gmc_v7_0_set_gart_funcs(adev); |
| 866 | gmc_v7_0_set_irq_funcs(adev); |
| 867 | |
| 868 | if (adev->flags & AMD_IS_APU) { |
| 869 | adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; |
| 870 | } else { |
| 871 | u32 tmp = RREG32(mmMC_SEQ_MISC0); |
| 872 | tmp &= MC_SEQ_MISC0__MT__MASK; |
| 873 | adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); |
| 874 | } |
| 875 | |
| 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | static int gmc_v7_0_late_init(void *handle) |
| 880 | { |
| 881 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 882 | |
| 883 | return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); |
| 884 | } |
| 885 | |
| 886 | static int gmc_v7_0_sw_init(void *handle) |
| 887 | { |
| 888 | int r; |
| 889 | int dma_bits; |
| 890 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 891 | |
| 892 | r = amdgpu_gem_init(adev); |
| 893 | if (r) |
| 894 | return r; |
| 895 | |
| 896 | r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); |
| 897 | if (r) |
| 898 | return r; |
| 899 | |
| 900 | r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); |
| 901 | if (r) |
| 902 | return r; |
| 903 | |
| 904 | /* Adjust VM size here. |
| 905 | * Currently set to 4GB ((1 << 20) 4k pages). |
| 906 | * Max GPUVM size for cayman and SI is 40 bits. |
| 907 | */ |
| 908 | adev->vm_manager.max_pfn = amdgpu_vm_size << 18; |
| 909 | |
| 910 | /* Set the internal MC address mask |
| 911 | * This is the max address of the GPU's |
| 912 | * internal address space. |
| 913 | */ |
| 914 | adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
| 915 | |
| 916 | /* set DMA mask + need_dma32 flags. |
| 917 | * PCIE - can handle 40-bits. |
| 918 | * IGP - can handle 40-bits |
| 919 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
| 920 | */ |
| 921 | adev->need_dma32 = false; |
| 922 | dma_bits = adev->need_dma32 ? 32 : 40; |
| 923 | r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); |
| 924 | if (r) { |
| 925 | adev->need_dma32 = true; |
| 926 | dma_bits = 32; |
| 927 | printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); |
| 928 | } |
| 929 | r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); |
| 930 | if (r) { |
| 931 | pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); |
| 932 | printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); |
| 933 | } |
| 934 | |
| 935 | r = gmc_v7_0_init_microcode(adev); |
| 936 | if (r) { |
| 937 | DRM_ERROR("Failed to load mc firmware!\n"); |
| 938 | return r; |
| 939 | } |
| 940 | |
| 941 | r = gmc_v7_0_mc_init(adev); |
| 942 | if (r) |
| 943 | return r; |
| 944 | |
| 945 | /* Memory manager */ |
| 946 | r = amdgpu_bo_init(adev); |
| 947 | if (r) |
| 948 | return r; |
| 949 | |
| 950 | r = gmc_v7_0_gart_init(adev); |
| 951 | if (r) |
| 952 | return r; |
| 953 | |
| 954 | if (!adev->vm_manager.enabled) { |
| 955 | r = gmc_v7_0_vm_init(adev); |
| 956 | if (r) { |
| 957 | dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); |
| 958 | return r; |
| 959 | } |
| 960 | adev->vm_manager.enabled = true; |
| 961 | } |
| 962 | |
| 963 | return r; |
| 964 | } |
| 965 | |
| 966 | static int gmc_v7_0_sw_fini(void *handle) |
| 967 | { |
| 968 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 969 | |
| 970 | if (adev->vm_manager.enabled) { |
| 971 | amdgpu_vm_manager_fini(adev); |
| 972 | gmc_v7_0_vm_fini(adev); |
| 973 | adev->vm_manager.enabled = false; |
| 974 | } |
| 975 | gmc_v7_0_gart_fini(adev); |
| 976 | amdgpu_gem_fini(adev); |
| 977 | amdgpu_bo_fini(adev); |
| 978 | |
| 979 | return 0; |
| 980 | } |
| 981 | |
| 982 | static int gmc_v7_0_hw_init(void *handle) |
| 983 | { |
| 984 | int r; |
| 985 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 986 | |
| 987 | gmc_v7_0_mc_program(adev); |
| 988 | |
| 989 | if (!(adev->flags & AMD_IS_APU)) { |
| 990 | r = gmc_v7_0_mc_load_microcode(adev); |
| 991 | if (r) { |
| 992 | DRM_ERROR("Failed to load MC firmware!\n"); |
| 993 | return r; |
| 994 | } |
| 995 | } |
| 996 | |
| 997 | r = gmc_v7_0_gart_enable(adev); |
| 998 | if (r) |
| 999 | return r; |
| 1000 | |
| 1001 | return r; |
| 1002 | } |
| 1003 | |
| 1004 | static int gmc_v7_0_hw_fini(void *handle) |
| 1005 | { |
| 1006 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1007 | |
| 1008 | amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); |
| 1009 | gmc_v7_0_gart_disable(adev); |
| 1010 | |
| 1011 | return 0; |
| 1012 | } |
| 1013 | |
| 1014 | static int gmc_v7_0_suspend(void *handle) |
| 1015 | { |
| 1016 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1017 | |
| 1018 | if (adev->vm_manager.enabled) { |
| 1019 | gmc_v7_0_vm_fini(adev); |
| 1020 | adev->vm_manager.enabled = false; |
| 1021 | } |
| 1022 | gmc_v7_0_hw_fini(adev); |
| 1023 | |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
| 1027 | static int gmc_v7_0_resume(void *handle) |
| 1028 | { |
| 1029 | int r; |
| 1030 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1031 | |
| 1032 | r = gmc_v7_0_hw_init(adev); |
| 1033 | if (r) |
| 1034 | return r; |
| 1035 | |
| 1036 | if (!adev->vm_manager.enabled) { |
| 1037 | r = gmc_v7_0_vm_init(adev); |
| 1038 | if (r) { |
| 1039 | dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); |
| 1040 | return r; |
| 1041 | } |
| 1042 | adev->vm_manager.enabled = true; |
| 1043 | } |
| 1044 | |
| 1045 | return r; |
| 1046 | } |
| 1047 | |
| 1048 | static bool gmc_v7_0_is_idle(void *handle) |
| 1049 | { |
| 1050 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1051 | u32 tmp = RREG32(mmSRBM_STATUS); |
| 1052 | |
| 1053 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | |
| 1054 | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) |
| 1055 | return false; |
| 1056 | |
| 1057 | return true; |
| 1058 | } |
| 1059 | |
| 1060 | static int gmc_v7_0_wait_for_idle(void *handle) |
| 1061 | { |
| 1062 | unsigned i; |
| 1063 | u32 tmp; |
| 1064 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1065 | |
| 1066 | for (i = 0; i < adev->usec_timeout; i++) { |
| 1067 | /* read MC_STATUS */ |
| 1068 | tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | |
| 1069 | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | |
| 1070 | SRBM_STATUS__MCC_BUSY_MASK | |
| 1071 | SRBM_STATUS__MCD_BUSY_MASK | |
| 1072 | SRBM_STATUS__VMC_BUSY_MASK); |
| 1073 | if (!tmp) |
| 1074 | return 0; |
| 1075 | udelay(1); |
| 1076 | } |
| 1077 | return -ETIMEDOUT; |
| 1078 | |
| 1079 | } |
| 1080 | |
| 1081 | static void gmc_v7_0_print_status(void *handle) |
| 1082 | { |
| 1083 | int i, j; |
| 1084 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1085 | |
| 1086 | dev_info(adev->dev, "GMC 8.x registers\n"); |
| 1087 | dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", |
| 1088 | RREG32(mmSRBM_STATUS)); |
| 1089 | dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", |
| 1090 | RREG32(mmSRBM_STATUS2)); |
| 1091 | |
| 1092 | dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
| 1093 | RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); |
| 1094 | dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
| 1095 | RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); |
| 1096 | dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", |
| 1097 | RREG32(mmMC_VM_MX_L1_TLB_CNTL)); |
| 1098 | dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", |
| 1099 | RREG32(mmVM_L2_CNTL)); |
| 1100 | dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", |
| 1101 | RREG32(mmVM_L2_CNTL2)); |
| 1102 | dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", |
| 1103 | RREG32(mmVM_L2_CNTL3)); |
| 1104 | dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", |
| 1105 | RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); |
| 1106 | dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", |
| 1107 | RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); |
| 1108 | dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", |
| 1109 | RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); |
| 1110 | dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", |
| 1111 | RREG32(mmVM_CONTEXT0_CNTL2)); |
| 1112 | dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", |
| 1113 | RREG32(mmVM_CONTEXT0_CNTL)); |
| 1114 | dev_info(adev->dev, " 0x15D4=0x%08X\n", |
| 1115 | RREG32(0x575)); |
| 1116 | dev_info(adev->dev, " 0x15D8=0x%08X\n", |
| 1117 | RREG32(0x576)); |
| 1118 | dev_info(adev->dev, " 0x15DC=0x%08X\n", |
| 1119 | RREG32(0x577)); |
| 1120 | dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", |
| 1121 | RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); |
| 1122 | dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", |
| 1123 | RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); |
| 1124 | dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", |
| 1125 | RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); |
| 1126 | dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", |
| 1127 | RREG32(mmVM_CONTEXT1_CNTL2)); |
| 1128 | dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", |
| 1129 | RREG32(mmVM_CONTEXT1_CNTL)); |
| 1130 | for (i = 0; i < 16; i++) { |
| 1131 | if (i < 8) |
| 1132 | dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", |
| 1133 | i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); |
| 1134 | else |
| 1135 | dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", |
| 1136 | i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); |
| 1137 | } |
| 1138 | dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", |
| 1139 | RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); |
| 1140 | dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", |
| 1141 | RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); |
| 1142 | dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", |
| 1143 | RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); |
| 1144 | dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", |
| 1145 | RREG32(mmMC_VM_FB_LOCATION)); |
| 1146 | dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", |
| 1147 | RREG32(mmMC_VM_AGP_BASE)); |
| 1148 | dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", |
| 1149 | RREG32(mmMC_VM_AGP_TOP)); |
| 1150 | dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", |
| 1151 | RREG32(mmMC_VM_AGP_BOT)); |
| 1152 | |
| 1153 | if (adev->asic_type == CHIP_KAVERI) { |
| 1154 | dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n", |
| 1155 | RREG32(mmCHUB_CONTROL)); |
| 1156 | } |
| 1157 | |
| 1158 | dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", |
| 1159 | RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); |
| 1160 | dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", |
| 1161 | RREG32(mmHDP_NONSURFACE_BASE)); |
| 1162 | dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", |
| 1163 | RREG32(mmHDP_NONSURFACE_INFO)); |
| 1164 | dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", |
| 1165 | RREG32(mmHDP_NONSURFACE_SIZE)); |
| 1166 | dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", |
| 1167 | RREG32(mmHDP_MISC_CNTL)); |
| 1168 | dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", |
| 1169 | RREG32(mmHDP_HOST_PATH_CNTL)); |
| 1170 | |
| 1171 | for (i = 0, j = 0; i < 32; i++, j += 0x6) { |
| 1172 | dev_info(adev->dev, " %d:\n", i); |
| 1173 | dev_info(adev->dev, " 0x%04X=0x%08X\n", |
| 1174 | 0xb05 + j, RREG32(0xb05 + j)); |
| 1175 | dev_info(adev->dev, " 0x%04X=0x%08X\n", |
| 1176 | 0xb06 + j, RREG32(0xb06 + j)); |
| 1177 | dev_info(adev->dev, " 0x%04X=0x%08X\n", |
| 1178 | 0xb07 + j, RREG32(0xb07 + j)); |
| 1179 | dev_info(adev->dev, " 0x%04X=0x%08X\n", |
| 1180 | 0xb08 + j, RREG32(0xb08 + j)); |
| 1181 | dev_info(adev->dev, " 0x%04X=0x%08X\n", |
| 1182 | 0xb09 + j, RREG32(0xb09 + j)); |
| 1183 | } |
| 1184 | |
| 1185 | dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", |
| 1186 | RREG32(mmBIF_FB_EN)); |
| 1187 | } |
| 1188 | |
| 1189 | static int gmc_v7_0_soft_reset(void *handle) |
| 1190 | { |
| 1191 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1192 | struct amdgpu_mode_mc_save save; |
| 1193 | u32 srbm_soft_reset = 0; |
| 1194 | u32 tmp = RREG32(mmSRBM_STATUS); |
| 1195 | |
| 1196 | if (tmp & SRBM_STATUS__VMC_BUSY_MASK) |
| 1197 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
| 1198 | SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); |
| 1199 | |
| 1200 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | |
| 1201 | SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { |
| 1202 | if (!(adev->flags & AMD_IS_APU)) |
| 1203 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
| 1204 | SRBM_SOFT_RESET, SOFT_RESET_MC, 1); |
| 1205 | } |
| 1206 | |
| 1207 | if (srbm_soft_reset) { |
| 1208 | gmc_v7_0_print_status((void *)adev); |
| 1209 | |
| 1210 | gmc_v7_0_mc_stop(adev, &save); |
| 1211 | if (gmc_v7_0_wait_for_idle(adev)) { |
| 1212 | dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); |
| 1213 | } |
| 1214 | |
| 1215 | |
| 1216 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 1217 | tmp |= srbm_soft_reset; |
| 1218 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); |
| 1219 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 1220 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 1221 | |
| 1222 | udelay(50); |
| 1223 | |
| 1224 | tmp &= ~srbm_soft_reset; |
| 1225 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 1226 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 1227 | |
| 1228 | /* Wait a little for things to settle down */ |
| 1229 | udelay(50); |
| 1230 | |
| 1231 | gmc_v7_0_mc_resume(adev, &save); |
| 1232 | udelay(50); |
| 1233 | |
| 1234 | gmc_v7_0_print_status((void *)adev); |
| 1235 | } |
| 1236 | |
| 1237 | return 0; |
| 1238 | } |
| 1239 | |
| 1240 | static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
| 1241 | struct amdgpu_irq_src *src, |
| 1242 | unsigned type, |
| 1243 | enum amdgpu_interrupt_state state) |
| 1244 | { |
| 1245 | u32 tmp; |
| 1246 | u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
| 1247 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
| 1248 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
| 1249 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
| 1250 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
| 1251 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); |
| 1252 | |
| 1253 | switch (state) { |
| 1254 | case AMDGPU_IRQ_STATE_DISABLE: |
| 1255 | /* system context */ |
| 1256 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
| 1257 | tmp &= ~bits; |
| 1258 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
| 1259 | /* VMs */ |
| 1260 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
| 1261 | tmp &= ~bits; |
| 1262 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
| 1263 | break; |
| 1264 | case AMDGPU_IRQ_STATE_ENABLE: |
| 1265 | /* system context */ |
| 1266 | tmp = RREG32(mmVM_CONTEXT0_CNTL); |
| 1267 | tmp |= bits; |
| 1268 | WREG32(mmVM_CONTEXT0_CNTL, tmp); |
| 1269 | /* VMs */ |
| 1270 | tmp = RREG32(mmVM_CONTEXT1_CNTL); |
| 1271 | tmp |= bits; |
| 1272 | WREG32(mmVM_CONTEXT1_CNTL, tmp); |
| 1273 | break; |
| 1274 | default: |
| 1275 | break; |
| 1276 | } |
| 1277 | |
| 1278 | return 0; |
| 1279 | } |
| 1280 | |
| 1281 | static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, |
| 1282 | struct amdgpu_irq_src *source, |
| 1283 | struct amdgpu_iv_entry *entry) |
| 1284 | { |
| 1285 | u32 addr, status, mc_client; |
| 1286 | |
| 1287 | addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); |
| 1288 | status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); |
| 1289 | mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); |
| 1290 | /* reset addr and status */ |
| 1291 | WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); |
| 1292 | |
| 1293 | if (!addr && !status) |
| 1294 | return 0; |
| 1295 | |
| 1296 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) |
| 1297 | gmc_v7_0_set_fault_enable_default(adev, false); |
| 1298 | |
| 1299 | dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", |
| 1300 | entry->src_id, entry->src_data); |
| 1301 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", |
| 1302 | addr); |
| 1303 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", |
| 1304 | status); |
| 1305 | gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); |
| 1306 | |
| 1307 | return 0; |
| 1308 | } |
| 1309 | |
| 1310 | static int gmc_v7_0_set_clockgating_state(void *handle, |
| 1311 | enum amd_clockgating_state state) |
| 1312 | { |
| 1313 | bool gate = false; |
| 1314 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1315 | |
| 1316 | if (state == AMD_CG_STATE_GATE) |
| 1317 | gate = true; |
| 1318 | |
| 1319 | if (!(adev->flags & AMD_IS_APU)) { |
| 1320 | gmc_v7_0_enable_mc_mgcg(adev, gate); |
| 1321 | gmc_v7_0_enable_mc_ls(adev, gate); |
| 1322 | } |
| 1323 | gmc_v7_0_enable_bif_mgls(adev, gate); |
| 1324 | gmc_v7_0_enable_hdp_mgcg(adev, gate); |
| 1325 | gmc_v7_0_enable_hdp_ls(adev, gate); |
| 1326 | |
| 1327 | return 0; |
| 1328 | } |
| 1329 | |
| 1330 | static int gmc_v7_0_set_powergating_state(void *handle, |
| 1331 | enum amd_powergating_state state) |
| 1332 | { |
| 1333 | return 0; |
| 1334 | } |
| 1335 | |
| 1336 | const struct amd_ip_funcs gmc_v7_0_ip_funcs = { |
| 1337 | .early_init = gmc_v7_0_early_init, |
| 1338 | .late_init = gmc_v7_0_late_init, |
| 1339 | .sw_init = gmc_v7_0_sw_init, |
| 1340 | .sw_fini = gmc_v7_0_sw_fini, |
| 1341 | .hw_init = gmc_v7_0_hw_init, |
| 1342 | .hw_fini = gmc_v7_0_hw_fini, |
| 1343 | .suspend = gmc_v7_0_suspend, |
| 1344 | .resume = gmc_v7_0_resume, |
| 1345 | .is_idle = gmc_v7_0_is_idle, |
| 1346 | .wait_for_idle = gmc_v7_0_wait_for_idle, |
| 1347 | .soft_reset = gmc_v7_0_soft_reset, |
| 1348 | .print_status = gmc_v7_0_print_status, |
| 1349 | .set_clockgating_state = gmc_v7_0_set_clockgating_state, |
| 1350 | .set_powergating_state = gmc_v7_0_set_powergating_state, |
| 1351 | }; |
| 1352 | |
| 1353 | static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = { |
| 1354 | .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb, |
| 1355 | .set_pte_pde = gmc_v7_0_gart_set_pte_pde, |
| 1356 | }; |
| 1357 | |
| 1358 | static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { |
| 1359 | .set = gmc_v7_0_vm_fault_interrupt_state, |
| 1360 | .process = gmc_v7_0_process_interrupt, |
| 1361 | }; |
| 1362 | |
| 1363 | static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev) |
| 1364 | { |
| 1365 | if (adev->gart.gart_funcs == NULL) |
| 1366 | adev->gart.gart_funcs = &gmc_v7_0_gart_funcs; |
| 1367 | } |
| 1368 | |
| 1369 | static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) |
| 1370 | { |
| 1371 | adev->mc.vm_fault.num_types = 1; |
| 1372 | adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; |
| 1373 | } |