| 1 | /************************************************************************** |
| 2 | * |
| 3 | * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | **************************************************************************/ |
| 27 | /* |
| 28 | * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> |
| 29 | */ |
| 30 | |
| 31 | #include <linux/export.h> |
| 32 | #include <drm/drmP.h> |
| 33 | |
| 34 | #if defined(CONFIG_X86) |
| 35 | static void |
| 36 | drm_clflush_page(struct page *page) |
| 37 | { |
| 38 | uint8_t *page_virtual; |
| 39 | unsigned int i; |
| 40 | const int size = boot_cpu_data.x86_clflush_size; |
| 41 | |
| 42 | if (unlikely(page == NULL)) |
| 43 | return; |
| 44 | |
| 45 | page_virtual = kmap_atomic(page); |
| 46 | for (i = 0; i < PAGE_SIZE; i += size) |
| 47 | clflush(page_virtual + i); |
| 48 | kunmap_atomic(page_virtual); |
| 49 | } |
| 50 | |
| 51 | static void drm_cache_flush_clflush(struct page *pages[], |
| 52 | unsigned long num_pages) |
| 53 | { |
| 54 | unsigned long i; |
| 55 | |
| 56 | mb(); |
| 57 | for (i = 0; i < num_pages; i++) |
| 58 | drm_clflush_page(*pages++); |
| 59 | mb(); |
| 60 | } |
| 61 | |
| 62 | static void |
| 63 | drm_clflush_ipi_handler(void *null) |
| 64 | { |
| 65 | wbinvd(); |
| 66 | } |
| 67 | #endif |
| 68 | |
| 69 | void |
| 70 | drm_clflush_pages(struct page *pages[], unsigned long num_pages) |
| 71 | { |
| 72 | |
| 73 | #if defined(CONFIG_X86) |
| 74 | if (cpu_has_clflush) { |
| 75 | drm_cache_flush_clflush(pages, num_pages); |
| 76 | return; |
| 77 | } |
| 78 | |
| 79 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) |
| 80 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
| 81 | |
| 82 | #elif defined(__powerpc__) |
| 83 | unsigned long i; |
| 84 | for (i = 0; i < num_pages; i++) { |
| 85 | struct page *page = pages[i]; |
| 86 | void *page_virtual; |
| 87 | |
| 88 | if (unlikely(page == NULL)) |
| 89 | continue; |
| 90 | |
| 91 | page_virtual = kmap_atomic(page); |
| 92 | flush_dcache_range((unsigned long)page_virtual, |
| 93 | (unsigned long)page_virtual + PAGE_SIZE); |
| 94 | kunmap_atomic(page_virtual); |
| 95 | } |
| 96 | #else |
| 97 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
| 98 | WARN_ON_ONCE(1); |
| 99 | #endif |
| 100 | } |
| 101 | EXPORT_SYMBOL(drm_clflush_pages); |
| 102 | |
| 103 | void |
| 104 | drm_clflush_sg(struct sg_table *st) |
| 105 | { |
| 106 | #if defined(CONFIG_X86) |
| 107 | if (cpu_has_clflush) { |
| 108 | struct sg_page_iter sg_iter; |
| 109 | |
| 110 | mb(); |
| 111 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
| 112 | drm_clflush_page(sg_page_iter_page(&sg_iter)); |
| 113 | mb(); |
| 114 | |
| 115 | return; |
| 116 | } |
| 117 | |
| 118 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) |
| 119 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
| 120 | #else |
| 121 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
| 122 | WARN_ON_ONCE(1); |
| 123 | #endif |
| 124 | } |
| 125 | EXPORT_SYMBOL(drm_clflush_sg); |
| 126 | |
| 127 | void |
| 128 | drm_clflush_virt_range(char *addr, unsigned long length) |
| 129 | { |
| 130 | #if defined(CONFIG_X86) |
| 131 | if (cpu_has_clflush) { |
| 132 | char *end = addr + length; |
| 133 | mb(); |
| 134 | for (; addr < end; addr += boot_cpu_data.x86_clflush_size) |
| 135 | clflush(addr); |
| 136 | clflush(end - 1); |
| 137 | mb(); |
| 138 | return; |
| 139 | } |
| 140 | |
| 141 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) |
| 142 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
| 143 | #else |
| 144 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
| 145 | WARN_ON_ONCE(1); |
| 146 | #endif |
| 147 | } |
| 148 | EXPORT_SYMBOL(drm_clflush_virt_range); |