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drm/modes: drop __drm_framebuffer_unregister.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/circ_buf.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/slab.h>
34#include <linux/export.h>
35#include <linux/list_sort.h>
36#include <asm/msr-index.h>
37#include <drm/drmP.h>
38#include "intel_drv.h"
39#include "intel_ringbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47};
48
49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
75static int i915_capabilities(struct seq_file *m, void *data)
76{
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
88
89 return 0;
90}
91
92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93{
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98}
99
100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101{
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108}
109
110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113}
114
115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
122 size += vma->node.size;
123 }
124
125 return size;
126}
127
128static void
129describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130{
131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
132 struct intel_engine_cs *engine;
133 struct i915_vma *vma;
134 int pin_count = 0;
135 enum intel_engine_id id;
136
137 lockdep_assert_held(&obj->base.dev->struct_mutex);
138
139 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
140 &obj->base,
141 obj->active ? "*" : " ",
142 get_pin_flag(obj),
143 get_tiling_flag(obj),
144 get_global_flag(obj),
145 obj->base.size / 1024,
146 obj->base.read_domains,
147 obj->base.write_domain);
148 for_each_engine_id(engine, dev_priv, id)
149 seq_printf(m, "%x ",
150 i915_gem_request_get_seqno(obj->last_read_req[id]));
151 seq_printf(m, "] %x %x%s%s%s",
152 i915_gem_request_get_seqno(obj->last_write_req),
153 i915_gem_request_get_seqno(obj->last_fenced_req),
154 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
155 obj->dirty ? " dirty" : "",
156 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
160 if (vma->pin_count > 0)
161 pin_count++;
162 }
163 seq_printf(m, " (pinned x %d)", pin_count);
164 if (obj->pin_display)
165 seq_printf(m, " (display)");
166 if (obj->fence_reg != I915_FENCE_REG_NONE)
167 seq_printf(m, " (fence: %d)", obj->fence_reg);
168 list_for_each_entry(vma, &obj->vma_list, obj_link) {
169 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
170 vma->is_ggtt ? "g" : "pp",
171 vma->node.start, vma->node.size);
172 if (vma->is_ggtt)
173 seq_printf(m, ", type: %u", vma->ggtt_view.type);
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_engine(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192}
193
194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195{
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
201static int i915_gem_object_list_info(struct seq_file *m, void *data)
202{
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = to_i915(dev);
208 struct i915_ggtt *ggtt = &dev_priv->ggtt;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &ggtt->base.active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &ggtt->base.inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, vm_link) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246}
247
248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261}
262
263static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264{
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311}
312
313#define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322} while (0)
323
324struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330};
331
332static int per_file_stats(int id, void *ptr, void *data)
333{
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, obj_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (vma->is_ggtt) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382}
383
384#define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395} while (0)
396
397static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399{
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *engine;
403 int j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_engine(engine, dev_priv) {
408 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &engine->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417}
418
419#define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428} while (0)
429
430static int i915_gem_object_info(struct seq_file *m, void* data)
431{
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = to_i915(dev);
435 struct i915_ggtt *ggtt = &dev_priv->ggtt;
436 u32 count, mappable_count, purgeable_count;
437 u64 size, mappable_size, purgeable_size;
438 struct drm_i915_gem_object *obj;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&ggtt->base.active_list, vm_link);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&ggtt->base.inactive_list, vm_link);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
498
499 seq_putc(m, '\n');
500 print_batch_pool_stats(m, dev_priv);
501 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
502 struct file_stats stats;
503 struct task_struct *task;
504
505 memset(&stats, 0, sizeof(stats));
506 stats.file_priv = file->driver_priv;
507 spin_lock(&file->table_lock);
508 idr_for_each(&file->object_idr, per_file_stats, &stats);
509 spin_unlock(&file->table_lock);
510 /*
511 * Although we have a valid reference on file->pid, that does
512 * not guarantee that the task_struct who called get_pid() is
513 * still alive (e.g. get_pid(current) => fork() => exit()).
514 * Therefore, we need to protect this ->comm access using RCU.
515 */
516 rcu_read_lock();
517 task = pid_task(file->pid, PIDTYPE_PID);
518 print_file_stats(m, task ? task->comm : "<unknown>", stats);
519 rcu_read_unlock();
520 }
521
522 mutex_unlock(&dev->struct_mutex);
523
524 return 0;
525}
526
527static int i915_gem_gtt_info(struct seq_file *m, void *data)
528{
529 struct drm_info_node *node = m->private;
530 struct drm_device *dev = node->minor->dev;
531 uintptr_t list = (uintptr_t) node->info_ent->data;
532 struct drm_i915_private *dev_priv = dev->dev_private;
533 struct drm_i915_gem_object *obj;
534 u64 total_obj_size, total_gtt_size;
535 int count, ret;
536
537 ret = mutex_lock_interruptible(&dev->struct_mutex);
538 if (ret)
539 return ret;
540
541 total_obj_size = total_gtt_size = count = 0;
542 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
543 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
544 continue;
545
546 seq_puts(m, " ");
547 describe_obj(m, obj);
548 seq_putc(m, '\n');
549 total_obj_size += obj->base.size;
550 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
551 count++;
552 }
553
554 mutex_unlock(&dev->struct_mutex);
555
556 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
557 count, total_obj_size, total_gtt_size);
558
559 return 0;
560}
561
562static int i915_gem_pageflip_info(struct seq_file *m, void *data)
563{
564 struct drm_info_node *node = m->private;
565 struct drm_device *dev = node->minor->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_crtc *crtc;
568 int ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
574 for_each_intel_crtc(dev, crtc) {
575 const char pipe = pipe_name(crtc->pipe);
576 const char plane = plane_name(crtc->plane);
577 struct intel_unpin_work *work;
578
579 spin_lock_irq(&dev->event_lock);
580 work = crtc->unpin_work;
581 if (work == NULL) {
582 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
583 pipe, plane);
584 } else {
585 u32 addr;
586
587 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
588 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
589 pipe, plane);
590 } else {
591 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
592 pipe, plane);
593 }
594 if (work->flip_queued_req) {
595 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
596
597 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
598 engine->name,
599 i915_gem_request_get_seqno(work->flip_queued_req),
600 dev_priv->next_seqno,
601 engine->get_seqno(engine),
602 i915_gem_request_completed(work->flip_queued_req, true));
603 } else
604 seq_printf(m, "Flip not associated with any ring\n");
605 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work->flip_queued_vblank,
607 work->flip_ready_vblank,
608 drm_crtc_vblank_count(&crtc->base));
609 if (work->enable_stall_check)
610 seq_puts(m, "Stall check enabled, ");
611 else
612 seq_puts(m, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
614
615 if (INTEL_INFO(dev)->gen >= 4)
616 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
617 else
618 addr = I915_READ(DSPADDR(crtc->plane));
619 seq_printf(m, "Current scanout address 0x%08x\n", addr);
620
621 if (work->pending_flip_obj) {
622 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
623 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
624 }
625 }
626 spin_unlock_irq(&dev->event_lock);
627 }
628
629 mutex_unlock(&dev->struct_mutex);
630
631 return 0;
632}
633
634static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
635{
636 struct drm_info_node *node = m->private;
637 struct drm_device *dev = node->minor->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj;
640 struct intel_engine_cs *engine;
641 int total = 0;
642 int ret, j;
643
644 ret = mutex_lock_interruptible(&dev->struct_mutex);
645 if (ret)
646 return ret;
647
648 for_each_engine(engine, dev_priv) {
649 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
650 int count;
651
652 count = 0;
653 list_for_each_entry(obj,
654 &engine->batch_pool.cache_list[j],
655 batch_pool_link)
656 count++;
657 seq_printf(m, "%s cache[%d]: %d objects\n",
658 engine->name, j, count);
659
660 list_for_each_entry(obj,
661 &engine->batch_pool.cache_list[j],
662 batch_pool_link) {
663 seq_puts(m, " ");
664 describe_obj(m, obj);
665 seq_putc(m, '\n');
666 }
667
668 total += count;
669 }
670 }
671
672 seq_printf(m, "total: %d\n", total);
673
674 mutex_unlock(&dev->struct_mutex);
675
676 return 0;
677}
678
679static int i915_gem_request_info(struct seq_file *m, void *data)
680{
681 struct drm_info_node *node = m->private;
682 struct drm_device *dev = node->minor->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_engine_cs *engine;
685 struct drm_i915_gem_request *req;
686 int ret, any;
687
688 ret = mutex_lock_interruptible(&dev->struct_mutex);
689 if (ret)
690 return ret;
691
692 any = 0;
693 for_each_engine(engine, dev_priv) {
694 int count;
695
696 count = 0;
697 list_for_each_entry(req, &engine->request_list, list)
698 count++;
699 if (count == 0)
700 continue;
701
702 seq_printf(m, "%s requests: %d\n", engine->name, count);
703 list_for_each_entry(req, &engine->request_list, list) {
704 struct task_struct *task;
705
706 rcu_read_lock();
707 task = NULL;
708 if (req->pid)
709 task = pid_task(req->pid, PIDTYPE_PID);
710 seq_printf(m, " %x @ %d: %s [%d]\n",
711 req->seqno,
712 (int) (jiffies - req->emitted_jiffies),
713 task ? task->comm : "<unknown>",
714 task ? task->pid : -1);
715 rcu_read_unlock();
716 }
717
718 any++;
719 }
720 mutex_unlock(&dev->struct_mutex);
721
722 if (any == 0)
723 seq_puts(m, "No requests\n");
724
725 return 0;
726}
727
728static void i915_ring_seqno_info(struct seq_file *m,
729 struct intel_engine_cs *engine)
730{
731 seq_printf(m, "Current sequence (%s): %x\n",
732 engine->name, engine->get_seqno(engine));
733 seq_printf(m, "Current user interrupts (%s): %x\n",
734 engine->name, READ_ONCE(engine->user_interrupts));
735}
736
737static int i915_gem_seqno_info(struct seq_file *m, void *data)
738{
739 struct drm_info_node *node = m->private;
740 struct drm_device *dev = node->minor->dev;
741 struct drm_i915_private *dev_priv = dev->dev_private;
742 struct intel_engine_cs *engine;
743 int ret;
744
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
746 if (ret)
747 return ret;
748 intel_runtime_pm_get(dev_priv);
749
750 for_each_engine(engine, dev_priv)
751 i915_ring_seqno_info(m, engine);
752
753 intel_runtime_pm_put(dev_priv);
754 mutex_unlock(&dev->struct_mutex);
755
756 return 0;
757}
758
759
760static int i915_interrupt_info(struct seq_file *m, void *data)
761{
762 struct drm_info_node *node = m->private;
763 struct drm_device *dev = node->minor->dev;
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct intel_engine_cs *engine;
766 int ret, i, pipe;
767
768 ret = mutex_lock_interruptible(&dev->struct_mutex);
769 if (ret)
770 return ret;
771 intel_runtime_pm_get(dev_priv);
772
773 if (IS_CHERRYVIEW(dev)) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 seq_printf(m, "Display IER:\t%08x\n",
778 I915_READ(VLV_IER));
779 seq_printf(m, "Display IIR:\t%08x\n",
780 I915_READ(VLV_IIR));
781 seq_printf(m, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW));
783 seq_printf(m, "Display IMR:\t%08x\n",
784 I915_READ(VLV_IMR));
785 for_each_pipe(dev_priv, pipe)
786 seq_printf(m, "Pipe %c stat:\t%08x\n",
787 pipe_name(pipe),
788 I915_READ(PIPESTAT(pipe)));
789
790 seq_printf(m, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN));
792 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT));
794 seq_printf(m, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT));
796
797 for (i = 0; i < 4; i++) {
798 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IMR(i)));
800 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IIR(i)));
802 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IER(i)));
804 }
805
806 seq_printf(m, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR));
808 seq_printf(m, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR));
810 seq_printf(m, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER));
812 } else if (INTEL_INFO(dev)->gen >= 8) {
813 seq_printf(m, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ));
815
816 for (i = 0; i < 4; i++) {
817 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IMR(i)));
819 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IIR(i)));
821 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IER(i)));
823 }
824
825 for_each_pipe(dev_priv, pipe) {
826 enum intel_display_power_domain power_domain;
827
828 power_domain = POWER_DOMAIN_PIPE(pipe);
829 if (!intel_display_power_get_if_enabled(dev_priv,
830 power_domain)) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
844
845 intel_display_power_put(dev_priv, power_domain);
846 }
847
848 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR));
850 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR));
852 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER));
854
855 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR));
857 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR));
859 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER));
861
862 seq_printf(m, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR));
864 seq_printf(m, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR));
866 seq_printf(m, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER));
868 } else if (IS_VALLEYVIEW(dev)) {
869 seq_printf(m, "Display IER:\t%08x\n",
870 I915_READ(VLV_IER));
871 seq_printf(m, "Display IIR:\t%08x\n",
872 I915_READ(VLV_IIR));
873 seq_printf(m, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW));
875 seq_printf(m, "Display IMR:\t%08x\n",
876 I915_READ(VLV_IMR));
877 for_each_pipe(dev_priv, pipe)
878 seq_printf(m, "Pipe %c stat:\t%08x\n",
879 pipe_name(pipe),
880 I915_READ(PIPESTAT(pipe)));
881
882 seq_printf(m, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER));
884
885 seq_printf(m, "Render IER:\t%08x\n",
886 I915_READ(GTIER));
887 seq_printf(m, "Render IIR:\t%08x\n",
888 I915_READ(GTIIR));
889 seq_printf(m, "Render IMR:\t%08x\n",
890 I915_READ(GTIMR));
891
892 seq_printf(m, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER));
894 seq_printf(m, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR));
896 seq_printf(m, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR));
898
899 seq_printf(m, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN));
901 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT));
903 seq_printf(m, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT));
905
906 } else if (!HAS_PCH_SPLIT(dev)) {
907 seq_printf(m, "Interrupt enable: %08x\n",
908 I915_READ(IER));
909 seq_printf(m, "Interrupt identity: %08x\n",
910 I915_READ(IIR));
911 seq_printf(m, "Interrupt mask: %08x\n",
912 I915_READ(IMR));
913 for_each_pipe(dev_priv, pipe)
914 seq_printf(m, "Pipe %c stat: %08x\n",
915 pipe_name(pipe),
916 I915_READ(PIPESTAT(pipe)));
917 } else {
918 seq_printf(m, "North Display Interrupt enable: %08x\n",
919 I915_READ(DEIER));
920 seq_printf(m, "North Display Interrupt identity: %08x\n",
921 I915_READ(DEIIR));
922 seq_printf(m, "North Display Interrupt mask: %08x\n",
923 I915_READ(DEIMR));
924 seq_printf(m, "South Display Interrupt enable: %08x\n",
925 I915_READ(SDEIER));
926 seq_printf(m, "South Display Interrupt identity: %08x\n",
927 I915_READ(SDEIIR));
928 seq_printf(m, "South Display Interrupt mask: %08x\n",
929 I915_READ(SDEIMR));
930 seq_printf(m, "Graphics Interrupt enable: %08x\n",
931 I915_READ(GTIER));
932 seq_printf(m, "Graphics Interrupt identity: %08x\n",
933 I915_READ(GTIIR));
934 seq_printf(m, "Graphics Interrupt mask: %08x\n",
935 I915_READ(GTIMR));
936 }
937 for_each_engine(engine, dev_priv) {
938 if (INTEL_INFO(dev)->gen >= 6) {
939 seq_printf(m,
940 "Graphics Interrupt mask (%s): %08x\n",
941 engine->name, I915_READ_IMR(engine));
942 }
943 i915_ring_seqno_info(m, engine);
944 }
945 intel_runtime_pm_put(dev_priv);
946 mutex_unlock(&dev->struct_mutex);
947
948 return 0;
949}
950
951static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
952{
953 struct drm_info_node *node = m->private;
954 struct drm_device *dev = node->minor->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 int i, ret;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
961
962 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
963 for (i = 0; i < dev_priv->num_fence_regs; i++) {
964 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
965
966 seq_printf(m, "Fence %d, pin count = %d, object = ",
967 i, dev_priv->fence_regs[i].pin_count);
968 if (obj == NULL)
969 seq_puts(m, "unused");
970 else
971 describe_obj(m, obj);
972 seq_putc(m, '\n');
973 }
974
975 mutex_unlock(&dev->struct_mutex);
976 return 0;
977}
978
979static int i915_hws_info(struct seq_file *m, void *data)
980{
981 struct drm_info_node *node = m->private;
982 struct drm_device *dev = node->minor->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct intel_engine_cs *engine;
985 const u32 *hws;
986 int i;
987
988 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
989 hws = engine->status_page.page_addr;
990 if (hws == NULL)
991 return 0;
992
993 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
994 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
995 i * 4,
996 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
997 }
998 return 0;
999}
1000
1001static ssize_t
1002i915_error_state_write(struct file *filp,
1003 const char __user *ubuf,
1004 size_t cnt,
1005 loff_t *ppos)
1006{
1007 struct i915_error_state_file_priv *error_priv = filp->private_data;
1008 struct drm_device *dev = error_priv->dev;
1009 int ret;
1010
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1012
1013 ret = mutex_lock_interruptible(&dev->struct_mutex);
1014 if (ret)
1015 return ret;
1016
1017 i915_destroy_error_state(dev);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return cnt;
1021}
1022
1023static int i915_error_state_open(struct inode *inode, struct file *file)
1024{
1025 struct drm_device *dev = inode->i_private;
1026 struct i915_error_state_file_priv *error_priv;
1027
1028 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029 if (!error_priv)
1030 return -ENOMEM;
1031
1032 error_priv->dev = dev;
1033
1034 i915_error_state_get(dev, error_priv);
1035
1036 file->private_data = error_priv;
1037
1038 return 0;
1039}
1040
1041static int i915_error_state_release(struct inode *inode, struct file *file)
1042{
1043 struct i915_error_state_file_priv *error_priv = file->private_data;
1044
1045 i915_error_state_put(error_priv);
1046 kfree(error_priv);
1047
1048 return 0;
1049}
1050
1051static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052 size_t count, loff_t *pos)
1053{
1054 struct i915_error_state_file_priv *error_priv = file->private_data;
1055 struct drm_i915_error_state_buf error_str;
1056 loff_t tmp_pos = 0;
1057 ssize_t ret_count = 0;
1058 int ret;
1059
1060 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061 if (ret)
1062 return ret;
1063
1064 ret = i915_error_state_to_str(&error_str, error_priv);
1065 if (ret)
1066 goto out;
1067
1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069 error_str.buf,
1070 error_str.bytes);
1071
1072 if (ret_count < 0)
1073 ret = ret_count;
1074 else
1075 *pos = error_str.start + ret_count;
1076out:
1077 i915_error_state_buf_release(&error_str);
1078 return ret ?: ret_count;
1079}
1080
1081static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
1084 .read = i915_error_state_read,
1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1088};
1089
1090static int
1091i915_next_seqno_get(void *data, u64 *val)
1092{
1093 struct drm_device *dev = data;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
1100
1101 *val = dev_priv->next_seqno;
1102 mutex_unlock(&dev->struct_mutex);
1103
1104 return 0;
1105}
1106
1107static int
1108i915_next_seqno_set(void *data, u64 val)
1109{
1110 struct drm_device *dev = data;
1111 int ret;
1112
1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 if (ret)
1115 return ret;
1116
1117 ret = i915_gem_set_seqno(dev, val);
1118 mutex_unlock(&dev->struct_mutex);
1119
1120 return ret;
1121}
1122
1123DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
1125 "0x%llx\n");
1126
1127static int i915_frequency_info(struct seq_file *m, void *unused)
1128{
1129 struct drm_info_node *node = m->private;
1130 struct drm_device *dev = node->minor->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132 int ret = 0;
1133
1134 intel_runtime_pm_get(dev_priv);
1135
1136 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
1138 if (IS_GEN5(dev)) {
1139 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145 MEMSTAT_VID_SHIFT);
1146 seq_printf(m, "Current P-state: %d\n",
1147 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149 u32 freq_sts;
1150
1151 mutex_lock(&dev_priv->rps.hw_lock);
1152 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156 seq_printf(m, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159 seq_printf(m, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162 seq_printf(m, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165 seq_printf(m, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168 seq_printf(m, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171 seq_printf(m,
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174 mutex_unlock(&dev_priv->rps.hw_lock);
1175 } else if (INTEL_INFO(dev)->gen >= 6) {
1176 u32 rp_state_limits;
1177 u32 gt_perf_status;
1178 u32 rp_state_cap;
1179 u32 rpmodectl, rpinclimit, rpdeclimit;
1180 u32 rpstat, cagf, reqf;
1181 u32 rpupei, rpcurup, rpprevup;
1182 u32 rpdownei, rpcurdown, rpprevdown;
1183 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1184 int max_freq;
1185
1186 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187 if (IS_BROXTON(dev)) {
1188 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190 } else {
1191 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193 }
1194
1195 /* RPSTAT1 is in the GT power well */
1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197 if (ret)
1198 goto out;
1199
1200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1201
1202 reqf = I915_READ(GEN6_RPNSWREQ);
1203 if (IS_GEN9(dev))
1204 reqf >>= 23;
1205 else {
1206 reqf &= ~GEN6_TURBO_DISABLE;
1207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208 reqf >>= 24;
1209 else
1210 reqf >>= 25;
1211 }
1212 reqf = intel_gpu_freq(dev_priv, reqf);
1213
1214 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
1218 rpstat = I915_READ(GEN6_RPSTAT1);
1219 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1225 if (IS_GEN9(dev))
1226 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229 else
1230 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231 cagf = intel_gpu_freq(dev_priv, cagf);
1232
1233 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234 mutex_unlock(&dev->struct_mutex);
1235
1236 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237 pm_ier = I915_READ(GEN6_PMIER);
1238 pm_imr = I915_READ(GEN6_PMIMR);
1239 pm_isr = I915_READ(GEN6_PMISR);
1240 pm_iir = I915_READ(GEN6_PMIIR);
1241 pm_mask = I915_READ(GEN6_PMINTRMSK);
1242 } else {
1243 pm_ier = I915_READ(GEN8_GT_IER(2));
1244 pm_imr = I915_READ(GEN8_GT_IMR(2));
1245 pm_isr = I915_READ(GEN8_GT_ISR(2));
1246 pm_iir = I915_READ(GEN8_GT_IIR(2));
1247 pm_mask = I915_READ(GEN6_PMINTRMSK);
1248 }
1249 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252 seq_printf(m, "Render p-state ratio: %d\n",
1253 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m, "Render p-state VID: %d\n",
1255 gt_perf_status & 0xff);
1256 seq_printf(m, "Render p-state limit: %d\n",
1257 rp_state_limits & 0xff);
1258 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265 GEN6_CURICONT_MASK);
1266 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267 GEN6_CURBSYTAVG_MASK);
1268 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269 GEN6_CURBSYTAVG_MASK);
1270 seq_printf(m, "Up threshold: %d%%\n",
1271 dev_priv->rps.up_threshold);
1272
1273 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274 GEN6_CURIAVG_MASK);
1275 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276 GEN6_CURBSYTAVG_MASK);
1277 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278 GEN6_CURBSYTAVG_MASK);
1279 seq_printf(m, "Down threshold: %d%%\n",
1280 dev_priv->rps.down_threshold);
1281
1282 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283 rp_state_cap >> 16) & 0xff;
1284 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285 GEN9_FREQ_SCALER : 1);
1286 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv, max_freq));
1288
1289 max_freq = (rp_state_cap & 0xff00) >> 8;
1290 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291 GEN9_FREQ_SCALER : 1);
1292 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv, max_freq));
1294
1295 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296 rp_state_cap >> 0) & 0xff;
1297 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298 GEN9_FREQ_SCALER : 1);
1299 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv, max_freq));
1301 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304 seq_printf(m, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307 seq_printf(m, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309 seq_printf(m, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311 seq_printf(m, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313 seq_printf(m,
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1316 } else {
1317 seq_puts(m, "no P-state info available\n");
1318 }
1319
1320 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
1324out:
1325 intel_runtime_pm_put(dev_priv);
1326 return ret;
1327}
1328
1329static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330{
1331 struct drm_info_node *node = m->private;
1332 struct drm_device *dev = node->minor->dev;
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct intel_engine_cs *engine;
1335 u64 acthd[I915_NUM_ENGINES];
1336 u32 seqno[I915_NUM_ENGINES];
1337 u32 instdone[I915_NUM_INSTDONE_REG];
1338 enum intel_engine_id id;
1339 int j;
1340
1341 if (!i915.enable_hangcheck) {
1342 seq_printf(m, "Hangcheck disabled\n");
1343 return 0;
1344 }
1345
1346 intel_runtime_pm_get(dev_priv);
1347
1348 for_each_engine_id(engine, dev_priv, id) {
1349 acthd[id] = intel_ring_get_active_head(engine);
1350 seqno[id] = engine->get_seqno(engine);
1351 }
1352
1353 i915_get_extra_instdone(dev, instdone);
1354
1355 intel_runtime_pm_put(dev_priv);
1356
1357 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1358 seq_printf(m, "Hangcheck active, fires in %dms\n",
1359 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1360 jiffies));
1361 } else
1362 seq_printf(m, "Hangcheck inactive\n");
1363
1364 for_each_engine_id(engine, dev_priv, id) {
1365 seq_printf(m, "%s:\n", engine->name);
1366 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1367 engine->hangcheck.seqno,
1368 seqno[id],
1369 engine->last_submitted_seqno);
1370 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1371 engine->hangcheck.user_interrupts,
1372 READ_ONCE(engine->user_interrupts));
1373 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1374 (long long)engine->hangcheck.acthd,
1375 (long long)acthd[id]);
1376 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1377 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1378
1379 if (engine->id == RCS) {
1380 seq_puts(m, "\tinstdone read =");
1381
1382 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1383 seq_printf(m, " 0x%08x", instdone[j]);
1384
1385 seq_puts(m, "\n\tinstdone accu =");
1386
1387 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1388 seq_printf(m, " 0x%08x",
1389 engine->hangcheck.instdone[j]);
1390
1391 seq_puts(m, "\n");
1392 }
1393 }
1394
1395 return 0;
1396}
1397
1398static int ironlake_drpc_info(struct seq_file *m)
1399{
1400 struct drm_info_node *node = m->private;
1401 struct drm_device *dev = node->minor->dev;
1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 rgvmodectl, rstdbyctl;
1404 u16 crstandvid;
1405 int ret;
1406
1407 ret = mutex_lock_interruptible(&dev->struct_mutex);
1408 if (ret)
1409 return ret;
1410 intel_runtime_pm_get(dev_priv);
1411
1412 rgvmodectl = I915_READ(MEMMODECTL);
1413 rstdbyctl = I915_READ(RSTDBYCTL);
1414 crstandvid = I915_READ16(CRSTANDVID);
1415
1416 intel_runtime_pm_put(dev_priv);
1417 mutex_unlock(&dev->struct_mutex);
1418
1419 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1420 seq_printf(m, "Boost freq: %d\n",
1421 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1422 MEMMODE_BOOST_FREQ_SHIFT);
1423 seq_printf(m, "HW control enabled: %s\n",
1424 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1425 seq_printf(m, "SW control enabled: %s\n",
1426 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1427 seq_printf(m, "Gated voltage change: %s\n",
1428 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1429 seq_printf(m, "Starting frequency: P%d\n",
1430 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1431 seq_printf(m, "Max P-state: P%d\n",
1432 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1433 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1434 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1435 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1436 seq_printf(m, "Render standby enabled: %s\n",
1437 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1438 seq_puts(m, "Current RS state: ");
1439 switch (rstdbyctl & RSX_STATUS_MASK) {
1440 case RSX_STATUS_ON:
1441 seq_puts(m, "on\n");
1442 break;
1443 case RSX_STATUS_RC1:
1444 seq_puts(m, "RC1\n");
1445 break;
1446 case RSX_STATUS_RC1E:
1447 seq_puts(m, "RC1E\n");
1448 break;
1449 case RSX_STATUS_RS1:
1450 seq_puts(m, "RS1\n");
1451 break;
1452 case RSX_STATUS_RS2:
1453 seq_puts(m, "RS2 (RC6)\n");
1454 break;
1455 case RSX_STATUS_RS3:
1456 seq_puts(m, "RC3 (RC6+)\n");
1457 break;
1458 default:
1459 seq_puts(m, "unknown\n");
1460 break;
1461 }
1462
1463 return 0;
1464}
1465
1466static int i915_forcewake_domains(struct seq_file *m, void *data)
1467{
1468 struct drm_info_node *node = m->private;
1469 struct drm_device *dev = node->minor->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct intel_uncore_forcewake_domain *fw_domain;
1472 int i;
1473
1474 spin_lock_irq(&dev_priv->uncore.lock);
1475 for_each_fw_domain(fw_domain, dev_priv, i) {
1476 seq_printf(m, "%s.wake_count = %u\n",
1477 intel_uncore_forcewake_domain_to_str(i),
1478 fw_domain->wake_count);
1479 }
1480 spin_unlock_irq(&dev_priv->uncore.lock);
1481
1482 return 0;
1483}
1484
1485static int vlv_drpc_info(struct seq_file *m)
1486{
1487 struct drm_info_node *node = m->private;
1488 struct drm_device *dev = node->minor->dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 u32 rpmodectl1, rcctl1, pw_status;
1491
1492 intel_runtime_pm_get(dev_priv);
1493
1494 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1495 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1496 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1497
1498 intel_runtime_pm_put(dev_priv);
1499
1500 seq_printf(m, "Video Turbo Mode: %s\n",
1501 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1502 seq_printf(m, "Turbo enabled: %s\n",
1503 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1504 seq_printf(m, "HW control enabled: %s\n",
1505 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1506 seq_printf(m, "SW control enabled: %s\n",
1507 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1508 GEN6_RP_MEDIA_SW_MODE));
1509 seq_printf(m, "RC6 Enabled: %s\n",
1510 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1511 GEN6_RC_CTL_EI_MODE(1))));
1512 seq_printf(m, "Render Power Well: %s\n",
1513 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1514 seq_printf(m, "Media Power Well: %s\n",
1515 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1516
1517 seq_printf(m, "Render RC6 residency since boot: %u\n",
1518 I915_READ(VLV_GT_RENDER_RC6));
1519 seq_printf(m, "Media RC6 residency since boot: %u\n",
1520 I915_READ(VLV_GT_MEDIA_RC6));
1521
1522 return i915_forcewake_domains(m, NULL);
1523}
1524
1525static int gen6_drpc_info(struct seq_file *m)
1526{
1527 struct drm_info_node *node = m->private;
1528 struct drm_device *dev = node->minor->dev;
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1531 unsigned forcewake_count;
1532 int count = 0, ret;
1533
1534 ret = mutex_lock_interruptible(&dev->struct_mutex);
1535 if (ret)
1536 return ret;
1537 intel_runtime_pm_get(dev_priv);
1538
1539 spin_lock_irq(&dev_priv->uncore.lock);
1540 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1541 spin_unlock_irq(&dev_priv->uncore.lock);
1542
1543 if (forcewake_count) {
1544 seq_puts(m, "RC information inaccurate because somebody "
1545 "holds a forcewake reference \n");
1546 } else {
1547 /* NB: we cannot use forcewake, else we read the wrong values */
1548 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1549 udelay(10);
1550 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1551 }
1552
1553 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1554 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1555
1556 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1557 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1558 mutex_unlock(&dev->struct_mutex);
1559 mutex_lock(&dev_priv->rps.hw_lock);
1560 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1561 mutex_unlock(&dev_priv->rps.hw_lock);
1562
1563 intel_runtime_pm_put(dev_priv);
1564
1565 seq_printf(m, "Video Turbo Mode: %s\n",
1566 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1567 seq_printf(m, "HW control enabled: %s\n",
1568 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1569 seq_printf(m, "SW control enabled: %s\n",
1570 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1571 GEN6_RP_MEDIA_SW_MODE));
1572 seq_printf(m, "RC1e Enabled: %s\n",
1573 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1574 seq_printf(m, "RC6 Enabled: %s\n",
1575 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1576 seq_printf(m, "Deep RC6 Enabled: %s\n",
1577 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1578 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1579 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1580 seq_puts(m, "Current RC state: ");
1581 switch (gt_core_status & GEN6_RCn_MASK) {
1582 case GEN6_RC0:
1583 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1584 seq_puts(m, "Core Power Down\n");
1585 else
1586 seq_puts(m, "on\n");
1587 break;
1588 case GEN6_RC3:
1589 seq_puts(m, "RC3\n");
1590 break;
1591 case GEN6_RC6:
1592 seq_puts(m, "RC6\n");
1593 break;
1594 case GEN6_RC7:
1595 seq_puts(m, "RC7\n");
1596 break;
1597 default:
1598 seq_puts(m, "Unknown\n");
1599 break;
1600 }
1601
1602 seq_printf(m, "Core Power Down: %s\n",
1603 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1604
1605 /* Not exactly sure what this is */
1606 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1607 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1608 seq_printf(m, "RC6 residency since boot: %u\n",
1609 I915_READ(GEN6_GT_GFX_RC6));
1610 seq_printf(m, "RC6+ residency since boot: %u\n",
1611 I915_READ(GEN6_GT_GFX_RC6p));
1612 seq_printf(m, "RC6++ residency since boot: %u\n",
1613 I915_READ(GEN6_GT_GFX_RC6pp));
1614
1615 seq_printf(m, "RC6 voltage: %dmV\n",
1616 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1617 seq_printf(m, "RC6+ voltage: %dmV\n",
1618 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1619 seq_printf(m, "RC6++ voltage: %dmV\n",
1620 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1621 return 0;
1622}
1623
1624static int i915_drpc_info(struct seq_file *m, void *unused)
1625{
1626 struct drm_info_node *node = m->private;
1627 struct drm_device *dev = node->minor->dev;
1628
1629 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1630 return vlv_drpc_info(m);
1631 else if (INTEL_INFO(dev)->gen >= 6)
1632 return gen6_drpc_info(m);
1633 else
1634 return ironlake_drpc_info(m);
1635}
1636
1637static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1638{
1639 struct drm_info_node *node = m->private;
1640 struct drm_device *dev = node->minor->dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642
1643 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1644 dev_priv->fb_tracking.busy_bits);
1645
1646 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1647 dev_priv->fb_tracking.flip_bits);
1648
1649 return 0;
1650}
1651
1652static int i915_fbc_status(struct seq_file *m, void *unused)
1653{
1654 struct drm_info_node *node = m->private;
1655 struct drm_device *dev = node->minor->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658 if (!HAS_FBC(dev)) {
1659 seq_puts(m, "FBC unsupported on this chipset\n");
1660 return 0;
1661 }
1662
1663 intel_runtime_pm_get(dev_priv);
1664 mutex_lock(&dev_priv->fbc.lock);
1665
1666 if (intel_fbc_is_active(dev_priv))
1667 seq_puts(m, "FBC enabled\n");
1668 else
1669 seq_printf(m, "FBC disabled: %s\n",
1670 dev_priv->fbc.no_fbc_reason);
1671
1672 if (INTEL_INFO(dev_priv)->gen >= 7)
1673 seq_printf(m, "Compressing: %s\n",
1674 yesno(I915_READ(FBC_STATUS2) &
1675 FBC_COMPRESSION_MASK));
1676
1677 mutex_unlock(&dev_priv->fbc.lock);
1678 intel_runtime_pm_put(dev_priv);
1679
1680 return 0;
1681}
1682
1683static int i915_fbc_fc_get(void *data, u64 *val)
1684{
1685 struct drm_device *dev = data;
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687
1688 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1689 return -ENODEV;
1690
1691 *val = dev_priv->fbc.false_color;
1692
1693 return 0;
1694}
1695
1696static int i915_fbc_fc_set(void *data, u64 val)
1697{
1698 struct drm_device *dev = data;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 u32 reg;
1701
1702 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1703 return -ENODEV;
1704
1705 mutex_lock(&dev_priv->fbc.lock);
1706
1707 reg = I915_READ(ILK_DPFC_CONTROL);
1708 dev_priv->fbc.false_color = val;
1709
1710 I915_WRITE(ILK_DPFC_CONTROL, val ?
1711 (reg | FBC_CTL_FALSE_COLOR) :
1712 (reg & ~FBC_CTL_FALSE_COLOR));
1713
1714 mutex_unlock(&dev_priv->fbc.lock);
1715 return 0;
1716}
1717
1718DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1719 i915_fbc_fc_get, i915_fbc_fc_set,
1720 "%llu\n");
1721
1722static int i915_ips_status(struct seq_file *m, void *unused)
1723{
1724 struct drm_info_node *node = m->private;
1725 struct drm_device *dev = node->minor->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727
1728 if (!HAS_IPS(dev)) {
1729 seq_puts(m, "not supported\n");
1730 return 0;
1731 }
1732
1733 intel_runtime_pm_get(dev_priv);
1734
1735 seq_printf(m, "Enabled by kernel parameter: %s\n",
1736 yesno(i915.enable_ips));
1737
1738 if (INTEL_INFO(dev)->gen >= 8) {
1739 seq_puts(m, "Currently: unknown\n");
1740 } else {
1741 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1742 seq_puts(m, "Currently: enabled\n");
1743 else
1744 seq_puts(m, "Currently: disabled\n");
1745 }
1746
1747 intel_runtime_pm_put(dev_priv);
1748
1749 return 0;
1750}
1751
1752static int i915_sr_status(struct seq_file *m, void *unused)
1753{
1754 struct drm_info_node *node = m->private;
1755 struct drm_device *dev = node->minor->dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 bool sr_enabled = false;
1758
1759 intel_runtime_pm_get(dev_priv);
1760
1761 if (HAS_PCH_SPLIT(dev))
1762 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1763 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1764 IS_I945G(dev) || IS_I945GM(dev))
1765 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1766 else if (IS_I915GM(dev))
1767 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1768 else if (IS_PINEVIEW(dev))
1769 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1770 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1771 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1772
1773 intel_runtime_pm_put(dev_priv);
1774
1775 seq_printf(m, "self-refresh: %s\n",
1776 sr_enabled ? "enabled" : "disabled");
1777
1778 return 0;
1779}
1780
1781static int i915_emon_status(struct seq_file *m, void *unused)
1782{
1783 struct drm_info_node *node = m->private;
1784 struct drm_device *dev = node->minor->dev;
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1786 unsigned long temp, chipset, gfx;
1787 int ret;
1788
1789 if (!IS_GEN5(dev))
1790 return -ENODEV;
1791
1792 ret = mutex_lock_interruptible(&dev->struct_mutex);
1793 if (ret)
1794 return ret;
1795
1796 temp = i915_mch_val(dev_priv);
1797 chipset = i915_chipset_val(dev_priv);
1798 gfx = i915_gfx_val(dev_priv);
1799 mutex_unlock(&dev->struct_mutex);
1800
1801 seq_printf(m, "GMCH temp: %ld\n", temp);
1802 seq_printf(m, "Chipset power: %ld\n", chipset);
1803 seq_printf(m, "GFX power: %ld\n", gfx);
1804 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1805
1806 return 0;
1807}
1808
1809static int i915_ring_freq_table(struct seq_file *m, void *unused)
1810{
1811 struct drm_info_node *node = m->private;
1812 struct drm_device *dev = node->minor->dev;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 int ret = 0;
1815 int gpu_freq, ia_freq;
1816 unsigned int max_gpu_freq, min_gpu_freq;
1817
1818 if (!HAS_CORE_RING_FREQ(dev)) {
1819 seq_puts(m, "unsupported on this chipset\n");
1820 return 0;
1821 }
1822
1823 intel_runtime_pm_get(dev_priv);
1824
1825 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1826
1827 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1828 if (ret)
1829 goto out;
1830
1831 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1832 /* Convert GT frequency to 50 HZ units */
1833 min_gpu_freq =
1834 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1835 max_gpu_freq =
1836 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1837 } else {
1838 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1839 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1840 }
1841
1842 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1843
1844 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1845 ia_freq = gpu_freq;
1846 sandybridge_pcode_read(dev_priv,
1847 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1848 &ia_freq);
1849 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1850 intel_gpu_freq(dev_priv, (gpu_freq *
1851 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1852 GEN9_FREQ_SCALER : 1))),
1853 ((ia_freq >> 0) & 0xff) * 100,
1854 ((ia_freq >> 8) & 0xff) * 100);
1855 }
1856
1857 mutex_unlock(&dev_priv->rps.hw_lock);
1858
1859out:
1860 intel_runtime_pm_put(dev_priv);
1861 return ret;
1862}
1863
1864static int i915_opregion(struct seq_file *m, void *unused)
1865{
1866 struct drm_info_node *node = m->private;
1867 struct drm_device *dev = node->minor->dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_opregion *opregion = &dev_priv->opregion;
1870 int ret;
1871
1872 ret = mutex_lock_interruptible(&dev->struct_mutex);
1873 if (ret)
1874 goto out;
1875
1876 if (opregion->header)
1877 seq_write(m, opregion->header, OPREGION_SIZE);
1878
1879 mutex_unlock(&dev->struct_mutex);
1880
1881out:
1882 return 0;
1883}
1884
1885static int i915_vbt(struct seq_file *m, void *unused)
1886{
1887 struct drm_info_node *node = m->private;
1888 struct drm_device *dev = node->minor->dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_opregion *opregion = &dev_priv->opregion;
1891
1892 if (opregion->vbt)
1893 seq_write(m, opregion->vbt, opregion->vbt_size);
1894
1895 return 0;
1896}
1897
1898static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1899{
1900 struct drm_info_node *node = m->private;
1901 struct drm_device *dev = node->minor->dev;
1902 struct intel_framebuffer *fbdev_fb = NULL;
1903 struct drm_framebuffer *drm_fb;
1904 int ret;
1905
1906 ret = mutex_lock_interruptible(&dev->struct_mutex);
1907 if (ret)
1908 return ret;
1909
1910#ifdef CONFIG_DRM_FBDEV_EMULATION
1911 if (to_i915(dev)->fbdev) {
1912 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1913
1914 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1915 fbdev_fb->base.width,
1916 fbdev_fb->base.height,
1917 fbdev_fb->base.depth,
1918 fbdev_fb->base.bits_per_pixel,
1919 fbdev_fb->base.modifier[0],
1920 atomic_read(&fbdev_fb->base.refcount.refcount));
1921 describe_obj(m, fbdev_fb->obj);
1922 seq_putc(m, '\n');
1923 }
1924#endif
1925
1926 mutex_lock(&dev->mode_config.fb_lock);
1927 drm_for_each_fb(drm_fb, dev) {
1928 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1929 if (fb == fbdev_fb)
1930 continue;
1931
1932 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1933 fb->base.width,
1934 fb->base.height,
1935 fb->base.depth,
1936 fb->base.bits_per_pixel,
1937 fb->base.modifier[0],
1938 atomic_read(&fb->base.refcount.refcount));
1939 describe_obj(m, fb->obj);
1940 seq_putc(m, '\n');
1941 }
1942 mutex_unlock(&dev->mode_config.fb_lock);
1943 mutex_unlock(&dev->struct_mutex);
1944
1945 return 0;
1946}
1947
1948static void describe_ctx_ringbuf(struct seq_file *m,
1949 struct intel_ringbuffer *ringbuf)
1950{
1951 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1952 ringbuf->space, ringbuf->head, ringbuf->tail,
1953 ringbuf->last_retired_head);
1954}
1955
1956static int i915_context_status(struct seq_file *m, void *unused)
1957{
1958 struct drm_info_node *node = m->private;
1959 struct drm_device *dev = node->minor->dev;
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961 struct intel_engine_cs *engine;
1962 struct intel_context *ctx;
1963 enum intel_engine_id id;
1964 int ret;
1965
1966 ret = mutex_lock_interruptible(&dev->struct_mutex);
1967 if (ret)
1968 return ret;
1969
1970 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1971 if (!i915.enable_execlists &&
1972 ctx->legacy_hw_ctx.rcs_state == NULL)
1973 continue;
1974
1975 seq_puts(m, "HW context ");
1976 describe_ctx(m, ctx);
1977 if (ctx == dev_priv->kernel_context)
1978 seq_printf(m, "(kernel context) ");
1979
1980 if (i915.enable_execlists) {
1981 seq_putc(m, '\n');
1982 for_each_engine_id(engine, dev_priv, id) {
1983 struct drm_i915_gem_object *ctx_obj =
1984 ctx->engine[id].state;
1985 struct intel_ringbuffer *ringbuf =
1986 ctx->engine[id].ringbuf;
1987
1988 seq_printf(m, "%s: ", engine->name);
1989 if (ctx_obj)
1990 describe_obj(m, ctx_obj);
1991 if (ringbuf)
1992 describe_ctx_ringbuf(m, ringbuf);
1993 seq_putc(m, '\n');
1994 }
1995 } else {
1996 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1997 }
1998
1999 seq_putc(m, '\n');
2000 }
2001
2002 mutex_unlock(&dev->struct_mutex);
2003
2004 return 0;
2005}
2006
2007static void i915_dump_lrc_obj(struct seq_file *m,
2008 struct intel_context *ctx,
2009 struct intel_engine_cs *engine)
2010{
2011 struct page *page;
2012 uint32_t *reg_state;
2013 int j;
2014 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2015 unsigned long ggtt_offset = 0;
2016
2017 if (ctx_obj == NULL) {
2018 seq_printf(m, "Context on %s with no gem object\n",
2019 engine->name);
2020 return;
2021 }
2022
2023 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2024 intel_execlists_ctx_id(ctx, engine));
2025
2026 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2027 seq_puts(m, "\tNot bound in GGTT\n");
2028 else
2029 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2030
2031 if (i915_gem_object_get_pages(ctx_obj)) {
2032 seq_puts(m, "\tFailed to get pages for context object\n");
2033 return;
2034 }
2035
2036 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2037 if (!WARN_ON(page == NULL)) {
2038 reg_state = kmap_atomic(page);
2039
2040 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2041 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2042 ggtt_offset + 4096 + (j * 4),
2043 reg_state[j], reg_state[j + 1],
2044 reg_state[j + 2], reg_state[j + 3]);
2045 }
2046 kunmap_atomic(reg_state);
2047 }
2048
2049 seq_putc(m, '\n');
2050}
2051
2052static int i915_dump_lrc(struct seq_file *m, void *unused)
2053{
2054 struct drm_info_node *node = (struct drm_info_node *) m->private;
2055 struct drm_device *dev = node->minor->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct intel_engine_cs *engine;
2058 struct intel_context *ctx;
2059 int ret;
2060
2061 if (!i915.enable_execlists) {
2062 seq_printf(m, "Logical Ring Contexts are disabled\n");
2063 return 0;
2064 }
2065
2066 ret = mutex_lock_interruptible(&dev->struct_mutex);
2067 if (ret)
2068 return ret;
2069
2070 list_for_each_entry(ctx, &dev_priv->context_list, link)
2071 if (ctx != dev_priv->kernel_context)
2072 for_each_engine(engine, dev_priv)
2073 i915_dump_lrc_obj(m, ctx, engine);
2074
2075 mutex_unlock(&dev->struct_mutex);
2076
2077 return 0;
2078}
2079
2080static int i915_execlists(struct seq_file *m, void *data)
2081{
2082 struct drm_info_node *node = (struct drm_info_node *)m->private;
2083 struct drm_device *dev = node->minor->dev;
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct intel_engine_cs *engine;
2086 u32 status_pointer;
2087 u8 read_pointer;
2088 u8 write_pointer;
2089 u32 status;
2090 u32 ctx_id;
2091 struct list_head *cursor;
2092 int i, ret;
2093
2094 if (!i915.enable_execlists) {
2095 seq_puts(m, "Logical Ring Contexts are disabled\n");
2096 return 0;
2097 }
2098
2099 ret = mutex_lock_interruptible(&dev->struct_mutex);
2100 if (ret)
2101 return ret;
2102
2103 intel_runtime_pm_get(dev_priv);
2104
2105 for_each_engine(engine, dev_priv) {
2106 struct drm_i915_gem_request *head_req = NULL;
2107 int count = 0;
2108
2109 seq_printf(m, "%s\n", engine->name);
2110
2111 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2112 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2113 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2114 status, ctx_id);
2115
2116 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2117 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2118
2119 read_pointer = engine->next_context_status_buffer;
2120 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2121 if (read_pointer > write_pointer)
2122 write_pointer += GEN8_CSB_ENTRIES;
2123 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2124 read_pointer, write_pointer);
2125
2126 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2127 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2128 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2129
2130 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2131 i, status, ctx_id);
2132 }
2133
2134 spin_lock_bh(&engine->execlist_lock);
2135 list_for_each(cursor, &engine->execlist_queue)
2136 count++;
2137 head_req = list_first_entry_or_null(&engine->execlist_queue,
2138 struct drm_i915_gem_request,
2139 execlist_link);
2140 spin_unlock_bh(&engine->execlist_lock);
2141
2142 seq_printf(m, "\t%d requests in queue\n", count);
2143 if (head_req) {
2144 seq_printf(m, "\tHead request id: %u\n",
2145 intel_execlists_ctx_id(head_req->ctx, engine));
2146 seq_printf(m, "\tHead request tail: %u\n",
2147 head_req->tail);
2148 }
2149
2150 seq_putc(m, '\n');
2151 }
2152
2153 intel_runtime_pm_put(dev_priv);
2154 mutex_unlock(&dev->struct_mutex);
2155
2156 return 0;
2157}
2158
2159static const char *swizzle_string(unsigned swizzle)
2160{
2161 switch (swizzle) {
2162 case I915_BIT_6_SWIZZLE_NONE:
2163 return "none";
2164 case I915_BIT_6_SWIZZLE_9:
2165 return "bit9";
2166 case I915_BIT_6_SWIZZLE_9_10:
2167 return "bit9/bit10";
2168 case I915_BIT_6_SWIZZLE_9_11:
2169 return "bit9/bit11";
2170 case I915_BIT_6_SWIZZLE_9_10_11:
2171 return "bit9/bit10/bit11";
2172 case I915_BIT_6_SWIZZLE_9_17:
2173 return "bit9/bit17";
2174 case I915_BIT_6_SWIZZLE_9_10_17:
2175 return "bit9/bit10/bit17";
2176 case I915_BIT_6_SWIZZLE_UNKNOWN:
2177 return "unknown";
2178 }
2179
2180 return "bug";
2181}
2182
2183static int i915_swizzle_info(struct seq_file *m, void *data)
2184{
2185 struct drm_info_node *node = m->private;
2186 struct drm_device *dev = node->minor->dev;
2187 struct drm_i915_private *dev_priv = dev->dev_private;
2188 int ret;
2189
2190 ret = mutex_lock_interruptible(&dev->struct_mutex);
2191 if (ret)
2192 return ret;
2193 intel_runtime_pm_get(dev_priv);
2194
2195 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2196 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2197 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2198 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2199
2200 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2201 seq_printf(m, "DDC = 0x%08x\n",
2202 I915_READ(DCC));
2203 seq_printf(m, "DDC2 = 0x%08x\n",
2204 I915_READ(DCC2));
2205 seq_printf(m, "C0DRB3 = 0x%04x\n",
2206 I915_READ16(C0DRB3));
2207 seq_printf(m, "C1DRB3 = 0x%04x\n",
2208 I915_READ16(C1DRB3));
2209 } else if (INTEL_INFO(dev)->gen >= 6) {
2210 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2211 I915_READ(MAD_DIMM_C0));
2212 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2213 I915_READ(MAD_DIMM_C1));
2214 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2215 I915_READ(MAD_DIMM_C2));
2216 seq_printf(m, "TILECTL = 0x%08x\n",
2217 I915_READ(TILECTL));
2218 if (INTEL_INFO(dev)->gen >= 8)
2219 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2220 I915_READ(GAMTARBMODE));
2221 else
2222 seq_printf(m, "ARB_MODE = 0x%08x\n",
2223 I915_READ(ARB_MODE));
2224 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2225 I915_READ(DISP_ARB_CTL));
2226 }
2227
2228 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2229 seq_puts(m, "L-shaped memory detected\n");
2230
2231 intel_runtime_pm_put(dev_priv);
2232 mutex_unlock(&dev->struct_mutex);
2233
2234 return 0;
2235}
2236
2237static int per_file_ctx(int id, void *ptr, void *data)
2238{
2239 struct intel_context *ctx = ptr;
2240 struct seq_file *m = data;
2241 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2242
2243 if (!ppgtt) {
2244 seq_printf(m, " no ppgtt for context %d\n",
2245 ctx->user_handle);
2246 return 0;
2247 }
2248
2249 if (i915_gem_context_is_default(ctx))
2250 seq_puts(m, " default context:\n");
2251 else
2252 seq_printf(m, " context %d:\n", ctx->user_handle);
2253 ppgtt->debug_dump(ppgtt, m);
2254
2255 return 0;
2256}
2257
2258static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2259{
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261 struct intel_engine_cs *engine;
2262 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2263 int i;
2264
2265 if (!ppgtt)
2266 return;
2267
2268 for_each_engine(engine, dev_priv) {
2269 seq_printf(m, "%s\n", engine->name);
2270 for (i = 0; i < 4; i++) {
2271 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2272 pdp <<= 32;
2273 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2274 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2275 }
2276 }
2277}
2278
2279static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2280{
2281 struct drm_i915_private *dev_priv = dev->dev_private;
2282 struct intel_engine_cs *engine;
2283
2284 if (INTEL_INFO(dev)->gen == 6)
2285 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2286
2287 for_each_engine(engine, dev_priv) {
2288 seq_printf(m, "%s\n", engine->name);
2289 if (INTEL_INFO(dev)->gen == 7)
2290 seq_printf(m, "GFX_MODE: 0x%08x\n",
2291 I915_READ(RING_MODE_GEN7(engine)));
2292 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2293 I915_READ(RING_PP_DIR_BASE(engine)));
2294 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2295 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2296 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2297 I915_READ(RING_PP_DIR_DCLV(engine)));
2298 }
2299 if (dev_priv->mm.aliasing_ppgtt) {
2300 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2301
2302 seq_puts(m, "aliasing PPGTT:\n");
2303 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2304
2305 ppgtt->debug_dump(ppgtt, m);
2306 }
2307
2308 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2309}
2310
2311static int i915_ppgtt_info(struct seq_file *m, void *data)
2312{
2313 struct drm_info_node *node = m->private;
2314 struct drm_device *dev = node->minor->dev;
2315 struct drm_i915_private *dev_priv = dev->dev_private;
2316 struct drm_file *file;
2317
2318 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2319 if (ret)
2320 return ret;
2321 intel_runtime_pm_get(dev_priv);
2322
2323 if (INTEL_INFO(dev)->gen >= 8)
2324 gen8_ppgtt_info(m, dev);
2325 else if (INTEL_INFO(dev)->gen >= 6)
2326 gen6_ppgtt_info(m, dev);
2327
2328 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2329 struct drm_i915_file_private *file_priv = file->driver_priv;
2330 struct task_struct *task;
2331
2332 task = get_pid_task(file->pid, PIDTYPE_PID);
2333 if (!task) {
2334 ret = -ESRCH;
2335 goto out_put;
2336 }
2337 seq_printf(m, "\nproc: %s\n", task->comm);
2338 put_task_struct(task);
2339 idr_for_each(&file_priv->context_idr, per_file_ctx,
2340 (void *)(unsigned long)m);
2341 }
2342
2343out_put:
2344 intel_runtime_pm_put(dev_priv);
2345 mutex_unlock(&dev->struct_mutex);
2346
2347 return ret;
2348}
2349
2350static int count_irq_waiters(struct drm_i915_private *i915)
2351{
2352 struct intel_engine_cs *engine;
2353 int count = 0;
2354
2355 for_each_engine(engine, i915)
2356 count += engine->irq_refcount;
2357
2358 return count;
2359}
2360
2361static int i915_rps_boost_info(struct seq_file *m, void *data)
2362{
2363 struct drm_info_node *node = m->private;
2364 struct drm_device *dev = node->minor->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct drm_file *file;
2367
2368 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2369 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2370 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2371 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2372 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2373 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2374 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2375 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2376 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2377 spin_lock(&dev_priv->rps.client_lock);
2378 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2379 struct drm_i915_file_private *file_priv = file->driver_priv;
2380 struct task_struct *task;
2381
2382 rcu_read_lock();
2383 task = pid_task(file->pid, PIDTYPE_PID);
2384 seq_printf(m, "%s [%d]: %d boosts%s\n",
2385 task ? task->comm : "<unknown>",
2386 task ? task->pid : -1,
2387 file_priv->rps.boosts,
2388 list_empty(&file_priv->rps.link) ? "" : ", active");
2389 rcu_read_unlock();
2390 }
2391 seq_printf(m, "Semaphore boosts: %d%s\n",
2392 dev_priv->rps.semaphores.boosts,
2393 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2394 seq_printf(m, "MMIO flip boosts: %d%s\n",
2395 dev_priv->rps.mmioflips.boosts,
2396 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2397 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2398 spin_unlock(&dev_priv->rps.client_lock);
2399
2400 return 0;
2401}
2402
2403static int i915_llc(struct seq_file *m, void *data)
2404{
2405 struct drm_info_node *node = m->private;
2406 struct drm_device *dev = node->minor->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408
2409 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2410 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2411 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2412
2413 return 0;
2414}
2415
2416static int i915_guc_load_status_info(struct seq_file *m, void *data)
2417{
2418 struct drm_info_node *node = m->private;
2419 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2420 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2421 u32 tmp, i;
2422
2423 if (!HAS_GUC_UCODE(dev_priv))
2424 return 0;
2425
2426 seq_printf(m, "GuC firmware status:\n");
2427 seq_printf(m, "\tpath: %s\n",
2428 guc_fw->guc_fw_path);
2429 seq_printf(m, "\tfetch: %s\n",
2430 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2431 seq_printf(m, "\tload: %s\n",
2432 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2433 seq_printf(m, "\tversion wanted: %d.%d\n",
2434 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2435 seq_printf(m, "\tversion found: %d.%d\n",
2436 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2437 seq_printf(m, "\theader: offset is %d; size = %d\n",
2438 guc_fw->header_offset, guc_fw->header_size);
2439 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2440 guc_fw->ucode_offset, guc_fw->ucode_size);
2441 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2442 guc_fw->rsa_offset, guc_fw->rsa_size);
2443
2444 tmp = I915_READ(GUC_STATUS);
2445
2446 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2447 seq_printf(m, "\tBootrom status = 0x%x\n",
2448 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2449 seq_printf(m, "\tuKernel status = 0x%x\n",
2450 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2451 seq_printf(m, "\tMIA Core status = 0x%x\n",
2452 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2453 seq_puts(m, "\nScratch registers:\n");
2454 for (i = 0; i < 16; i++)
2455 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2456
2457 return 0;
2458}
2459
2460static void i915_guc_client_info(struct seq_file *m,
2461 struct drm_i915_private *dev_priv,
2462 struct i915_guc_client *client)
2463{
2464 struct intel_engine_cs *engine;
2465 uint64_t tot = 0;
2466
2467 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2468 client->priority, client->ctx_index, client->proc_desc_offset);
2469 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2470 client->doorbell_id, client->doorbell_offset, client->cookie);
2471 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2472 client->wq_size, client->wq_offset, client->wq_tail);
2473
2474 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2475 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2476 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2477
2478 for_each_engine(engine, dev_priv) {
2479 seq_printf(m, "\tSubmissions: %llu %s\n",
2480 client->submissions[engine->guc_id],
2481 engine->name);
2482 tot += client->submissions[engine->guc_id];
2483 }
2484 seq_printf(m, "\tTotal: %llu\n", tot);
2485}
2486
2487static int i915_guc_info(struct seq_file *m, void *data)
2488{
2489 struct drm_info_node *node = m->private;
2490 struct drm_device *dev = node->minor->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct intel_guc guc;
2493 struct i915_guc_client client = {};
2494 struct intel_engine_cs *engine;
2495 u64 total = 0;
2496
2497 if (!HAS_GUC_SCHED(dev_priv))
2498 return 0;
2499
2500 if (mutex_lock_interruptible(&dev->struct_mutex))
2501 return 0;
2502
2503 /* Take a local copy of the GuC data, so we can dump it at leisure */
2504 guc = dev_priv->guc;
2505 if (guc.execbuf_client)
2506 client = *guc.execbuf_client;
2507
2508 mutex_unlock(&dev->struct_mutex);
2509
2510 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2511 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2512 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2513 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2514 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2515
2516 seq_printf(m, "\nGuC submissions:\n");
2517 for_each_engine(engine, dev_priv) {
2518 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2519 engine->name, guc.submissions[engine->guc_id],
2520 guc.last_seqno[engine->guc_id]);
2521 total += guc.submissions[engine->guc_id];
2522 }
2523 seq_printf(m, "\t%s: %llu\n", "Total", total);
2524
2525 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2526 i915_guc_client_info(m, dev_priv, &client);
2527
2528 /* Add more as required ... */
2529
2530 return 0;
2531}
2532
2533static int i915_guc_log_dump(struct seq_file *m, void *data)
2534{
2535 struct drm_info_node *node = m->private;
2536 struct drm_device *dev = node->minor->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2539 u32 *log;
2540 int i = 0, pg;
2541
2542 if (!log_obj)
2543 return 0;
2544
2545 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2546 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2547
2548 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2549 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2550 *(log + i), *(log + i + 1),
2551 *(log + i + 2), *(log + i + 3));
2552
2553 kunmap_atomic(log);
2554 }
2555
2556 seq_putc(m, '\n');
2557
2558 return 0;
2559}
2560
2561static int i915_edp_psr_status(struct seq_file *m, void *data)
2562{
2563 struct drm_info_node *node = m->private;
2564 struct drm_device *dev = node->minor->dev;
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 u32 psrperf = 0;
2567 u32 stat[3];
2568 enum pipe pipe;
2569 bool enabled = false;
2570
2571 if (!HAS_PSR(dev)) {
2572 seq_puts(m, "PSR not supported\n");
2573 return 0;
2574 }
2575
2576 intel_runtime_pm_get(dev_priv);
2577
2578 mutex_lock(&dev_priv->psr.lock);
2579 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2580 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2581 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2582 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2583 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2584 dev_priv->psr.busy_frontbuffer_bits);
2585 seq_printf(m, "Re-enable work scheduled: %s\n",
2586 yesno(work_busy(&dev_priv->psr.work.work)));
2587
2588 if (HAS_DDI(dev))
2589 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2590 else {
2591 for_each_pipe(dev_priv, pipe) {
2592 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2593 VLV_EDP_PSR_CURR_STATE_MASK;
2594 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2595 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2596 enabled = true;
2597 }
2598 }
2599
2600 seq_printf(m, "Main link in standby mode: %s\n",
2601 yesno(dev_priv->psr.link_standby));
2602
2603 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2604
2605 if (!HAS_DDI(dev))
2606 for_each_pipe(dev_priv, pipe) {
2607 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2608 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2609 seq_printf(m, " pipe %c", pipe_name(pipe));
2610 }
2611 seq_puts(m, "\n");
2612
2613 /*
2614 * VLV/CHV PSR has no kind of performance counter
2615 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2616 */
2617 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2618 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2619 EDP_PSR_PERF_CNT_MASK;
2620
2621 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2622 }
2623 mutex_unlock(&dev_priv->psr.lock);
2624
2625 intel_runtime_pm_put(dev_priv);
2626 return 0;
2627}
2628
2629static int i915_sink_crc(struct seq_file *m, void *data)
2630{
2631 struct drm_info_node *node = m->private;
2632 struct drm_device *dev = node->minor->dev;
2633 struct intel_encoder *encoder;
2634 struct intel_connector *connector;
2635 struct intel_dp *intel_dp = NULL;
2636 int ret;
2637 u8 crc[6];
2638
2639 drm_modeset_lock_all(dev);
2640 for_each_intel_connector(dev, connector) {
2641
2642 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2643 continue;
2644
2645 if (!connector->base.encoder)
2646 continue;
2647
2648 encoder = to_intel_encoder(connector->base.encoder);
2649 if (encoder->type != INTEL_OUTPUT_EDP)
2650 continue;
2651
2652 intel_dp = enc_to_intel_dp(&encoder->base);
2653
2654 ret = intel_dp_sink_crc(intel_dp, crc);
2655 if (ret)
2656 goto out;
2657
2658 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2659 crc[0], crc[1], crc[2],
2660 crc[3], crc[4], crc[5]);
2661 goto out;
2662 }
2663 ret = -ENODEV;
2664out:
2665 drm_modeset_unlock_all(dev);
2666 return ret;
2667}
2668
2669static int i915_energy_uJ(struct seq_file *m, void *data)
2670{
2671 struct drm_info_node *node = m->private;
2672 struct drm_device *dev = node->minor->dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 u64 power;
2675 u32 units;
2676
2677 if (INTEL_INFO(dev)->gen < 6)
2678 return -ENODEV;
2679
2680 intel_runtime_pm_get(dev_priv);
2681
2682 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2683 power = (power & 0x1f00) >> 8;
2684 units = 1000000 / (1 << power); /* convert to uJ */
2685 power = I915_READ(MCH_SECP_NRG_STTS);
2686 power *= units;
2687
2688 intel_runtime_pm_put(dev_priv);
2689
2690 seq_printf(m, "%llu", (long long unsigned)power);
2691
2692 return 0;
2693}
2694
2695static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2696{
2697 struct drm_info_node *node = m->private;
2698 struct drm_device *dev = node->minor->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700
2701 if (!HAS_RUNTIME_PM(dev_priv))
2702 seq_puts(m, "Runtime power management not supported\n");
2703
2704 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2705 seq_printf(m, "IRQs disabled: %s\n",
2706 yesno(!intel_irqs_enabled(dev_priv)));
2707#ifdef CONFIG_PM
2708 seq_printf(m, "Usage count: %d\n",
2709 atomic_read(&dev->dev->power.usage_count));
2710#else
2711 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2712#endif
2713 seq_printf(m, "PCI device power state: %s [%d]\n",
2714 pci_power_name(dev_priv->dev->pdev->current_state),
2715 dev_priv->dev->pdev->current_state);
2716
2717 return 0;
2718}
2719
2720static int i915_power_domain_info(struct seq_file *m, void *unused)
2721{
2722 struct drm_info_node *node = m->private;
2723 struct drm_device *dev = node->minor->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2726 int i;
2727
2728 mutex_lock(&power_domains->lock);
2729
2730 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2731 for (i = 0; i < power_domains->power_well_count; i++) {
2732 struct i915_power_well *power_well;
2733 enum intel_display_power_domain power_domain;
2734
2735 power_well = &power_domains->power_wells[i];
2736 seq_printf(m, "%-25s %d\n", power_well->name,
2737 power_well->count);
2738
2739 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2740 power_domain++) {
2741 if (!(BIT(power_domain) & power_well->domains))
2742 continue;
2743
2744 seq_printf(m, " %-23s %d\n",
2745 intel_display_power_domain_str(power_domain),
2746 power_domains->domain_use_count[power_domain]);
2747 }
2748 }
2749
2750 mutex_unlock(&power_domains->lock);
2751
2752 return 0;
2753}
2754
2755static int i915_dmc_info(struct seq_file *m, void *unused)
2756{
2757 struct drm_info_node *node = m->private;
2758 struct drm_device *dev = node->minor->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_csr *csr;
2761
2762 if (!HAS_CSR(dev)) {
2763 seq_puts(m, "not supported\n");
2764 return 0;
2765 }
2766
2767 csr = &dev_priv->csr;
2768
2769 intel_runtime_pm_get(dev_priv);
2770
2771 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2772 seq_printf(m, "path: %s\n", csr->fw_path);
2773
2774 if (!csr->dmc_payload)
2775 goto out;
2776
2777 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2778 CSR_VERSION_MINOR(csr->version));
2779
2780 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2781 seq_printf(m, "DC3 -> DC5 count: %d\n",
2782 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2783 seq_printf(m, "DC5 -> DC6 count: %d\n",
2784 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2785 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2786 seq_printf(m, "DC3 -> DC5 count: %d\n",
2787 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2788 }
2789
2790out:
2791 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2792 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2793 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2794
2795 intel_runtime_pm_put(dev_priv);
2796
2797 return 0;
2798}
2799
2800static void intel_seq_print_mode(struct seq_file *m, int tabs,
2801 struct drm_display_mode *mode)
2802{
2803 int i;
2804
2805 for (i = 0; i < tabs; i++)
2806 seq_putc(m, '\t');
2807
2808 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2809 mode->base.id, mode->name,
2810 mode->vrefresh, mode->clock,
2811 mode->hdisplay, mode->hsync_start,
2812 mode->hsync_end, mode->htotal,
2813 mode->vdisplay, mode->vsync_start,
2814 mode->vsync_end, mode->vtotal,
2815 mode->type, mode->flags);
2816}
2817
2818static void intel_encoder_info(struct seq_file *m,
2819 struct intel_crtc *intel_crtc,
2820 struct intel_encoder *intel_encoder)
2821{
2822 struct drm_info_node *node = m->private;
2823 struct drm_device *dev = node->minor->dev;
2824 struct drm_crtc *crtc = &intel_crtc->base;
2825 struct intel_connector *intel_connector;
2826 struct drm_encoder *encoder;
2827
2828 encoder = &intel_encoder->base;
2829 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2830 encoder->base.id, encoder->name);
2831 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2832 struct drm_connector *connector = &intel_connector->base;
2833 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2834 connector->base.id,
2835 connector->name,
2836 drm_get_connector_status_name(connector->status));
2837 if (connector->status == connector_status_connected) {
2838 struct drm_display_mode *mode = &crtc->mode;
2839 seq_printf(m, ", mode:\n");
2840 intel_seq_print_mode(m, 2, mode);
2841 } else {
2842 seq_putc(m, '\n');
2843 }
2844 }
2845}
2846
2847static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2848{
2849 struct drm_info_node *node = m->private;
2850 struct drm_device *dev = node->minor->dev;
2851 struct drm_crtc *crtc = &intel_crtc->base;
2852 struct intel_encoder *intel_encoder;
2853 struct drm_plane_state *plane_state = crtc->primary->state;
2854 struct drm_framebuffer *fb = plane_state->fb;
2855
2856 if (fb)
2857 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2858 fb->base.id, plane_state->src_x >> 16,
2859 plane_state->src_y >> 16, fb->width, fb->height);
2860 else
2861 seq_puts(m, "\tprimary plane disabled\n");
2862 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2863 intel_encoder_info(m, intel_crtc, intel_encoder);
2864}
2865
2866static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2867{
2868 struct drm_display_mode *mode = panel->fixed_mode;
2869
2870 seq_printf(m, "\tfixed mode:\n");
2871 intel_seq_print_mode(m, 2, mode);
2872}
2873
2874static void intel_dp_info(struct seq_file *m,
2875 struct intel_connector *intel_connector)
2876{
2877 struct intel_encoder *intel_encoder = intel_connector->encoder;
2878 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2879
2880 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2881 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2882 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2883 intel_panel_info(m, &intel_connector->panel);
2884}
2885
2886static void intel_dp_mst_info(struct seq_file *m,
2887 struct intel_connector *intel_connector)
2888{
2889 struct intel_encoder *intel_encoder = intel_connector->encoder;
2890 struct intel_dp_mst_encoder *intel_mst =
2891 enc_to_mst(&intel_encoder->base);
2892 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2893 struct intel_dp *intel_dp = &intel_dig_port->dp;
2894 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2895 intel_connector->port);
2896
2897 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2898}
2899
2900static void intel_hdmi_info(struct seq_file *m,
2901 struct intel_connector *intel_connector)
2902{
2903 struct intel_encoder *intel_encoder = intel_connector->encoder;
2904 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2905
2906 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2907}
2908
2909static void intel_lvds_info(struct seq_file *m,
2910 struct intel_connector *intel_connector)
2911{
2912 intel_panel_info(m, &intel_connector->panel);
2913}
2914
2915static void intel_connector_info(struct seq_file *m,
2916 struct drm_connector *connector)
2917{
2918 struct intel_connector *intel_connector = to_intel_connector(connector);
2919 struct intel_encoder *intel_encoder = intel_connector->encoder;
2920 struct drm_display_mode *mode;
2921
2922 seq_printf(m, "connector %d: type %s, status: %s\n",
2923 connector->base.id, connector->name,
2924 drm_get_connector_status_name(connector->status));
2925 if (connector->status == connector_status_connected) {
2926 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2927 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2928 connector->display_info.width_mm,
2929 connector->display_info.height_mm);
2930 seq_printf(m, "\tsubpixel order: %s\n",
2931 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2932 seq_printf(m, "\tCEA rev: %d\n",
2933 connector->display_info.cea_rev);
2934 }
2935 if (intel_encoder) {
2936 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2937 intel_encoder->type == INTEL_OUTPUT_EDP)
2938 intel_dp_info(m, intel_connector);
2939 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2940 intel_hdmi_info(m, intel_connector);
2941 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2942 intel_lvds_info(m, intel_connector);
2943 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2944 intel_dp_mst_info(m, intel_connector);
2945 }
2946
2947 seq_printf(m, "\tmodes:\n");
2948 list_for_each_entry(mode, &connector->modes, head)
2949 intel_seq_print_mode(m, 2, mode);
2950}
2951
2952static bool cursor_active(struct drm_device *dev, int pipe)
2953{
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 u32 state;
2956
2957 if (IS_845G(dev) || IS_I865G(dev))
2958 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2959 else
2960 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2961
2962 return state;
2963}
2964
2965static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2966{
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 u32 pos;
2969
2970 pos = I915_READ(CURPOS(pipe));
2971
2972 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2973 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2974 *x = -*x;
2975
2976 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2977 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2978 *y = -*y;
2979
2980 return cursor_active(dev, pipe);
2981}
2982
2983static const char *plane_type(enum drm_plane_type type)
2984{
2985 switch (type) {
2986 case DRM_PLANE_TYPE_OVERLAY:
2987 return "OVL";
2988 case DRM_PLANE_TYPE_PRIMARY:
2989 return "PRI";
2990 case DRM_PLANE_TYPE_CURSOR:
2991 return "CUR";
2992 /*
2993 * Deliberately omitting default: to generate compiler warnings
2994 * when a new drm_plane_type gets added.
2995 */
2996 }
2997
2998 return "unknown";
2999}
3000
3001static const char *plane_rotation(unsigned int rotation)
3002{
3003 static char buf[48];
3004 /*
3005 * According to doc only one DRM_ROTATE_ is allowed but this
3006 * will print them all to visualize if the values are misused
3007 */
3008 snprintf(buf, sizeof(buf),
3009 "%s%s%s%s%s%s(0x%08x)",
3010 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3011 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3012 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3013 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3014 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3015 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3016 rotation);
3017
3018 return buf;
3019}
3020
3021static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3022{
3023 struct drm_info_node *node = m->private;
3024 struct drm_device *dev = node->minor->dev;
3025 struct intel_plane *intel_plane;
3026
3027 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3028 struct drm_plane_state *state;
3029 struct drm_plane *plane = &intel_plane->base;
3030
3031 if (!plane->state) {
3032 seq_puts(m, "plane->state is NULL!\n");
3033 continue;
3034 }
3035
3036 state = plane->state;
3037
3038 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3039 plane->base.id,
3040 plane_type(intel_plane->base.type),
3041 state->crtc_x, state->crtc_y,
3042 state->crtc_w, state->crtc_h,
3043 (state->src_x >> 16),
3044 ((state->src_x & 0xffff) * 15625) >> 10,
3045 (state->src_y >> 16),
3046 ((state->src_y & 0xffff) * 15625) >> 10,
3047 (state->src_w >> 16),
3048 ((state->src_w & 0xffff) * 15625) >> 10,
3049 (state->src_h >> 16),
3050 ((state->src_h & 0xffff) * 15625) >> 10,
3051 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3052 plane_rotation(state->rotation));
3053 }
3054}
3055
3056static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3057{
3058 struct intel_crtc_state *pipe_config;
3059 int num_scalers = intel_crtc->num_scalers;
3060 int i;
3061
3062 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3063
3064 /* Not all platformas have a scaler */
3065 if (num_scalers) {
3066 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3067 num_scalers,
3068 pipe_config->scaler_state.scaler_users,
3069 pipe_config->scaler_state.scaler_id);
3070
3071 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3072 struct intel_scaler *sc =
3073 &pipe_config->scaler_state.scalers[i];
3074
3075 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3076 i, yesno(sc->in_use), sc->mode);
3077 }
3078 seq_puts(m, "\n");
3079 } else {
3080 seq_puts(m, "\tNo scalers available on this platform\n");
3081 }
3082}
3083
3084static int i915_display_info(struct seq_file *m, void *unused)
3085{
3086 struct drm_info_node *node = m->private;
3087 struct drm_device *dev = node->minor->dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 struct intel_crtc *crtc;
3090 struct drm_connector *connector;
3091
3092 intel_runtime_pm_get(dev_priv);
3093 drm_modeset_lock_all(dev);
3094 seq_printf(m, "CRTC info\n");
3095 seq_printf(m, "---------\n");
3096 for_each_intel_crtc(dev, crtc) {
3097 bool active;
3098 struct intel_crtc_state *pipe_config;
3099 int x, y;
3100
3101 pipe_config = to_intel_crtc_state(crtc->base.state);
3102
3103 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3104 crtc->base.base.id, pipe_name(crtc->pipe),
3105 yesno(pipe_config->base.active),
3106 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3107 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3108
3109 if (pipe_config->base.active) {
3110 intel_crtc_info(m, crtc);
3111
3112 active = cursor_position(dev, crtc->pipe, &x, &y);
3113 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3114 yesno(crtc->cursor_base),
3115 x, y, crtc->base.cursor->state->crtc_w,
3116 crtc->base.cursor->state->crtc_h,
3117 crtc->cursor_addr, yesno(active));
3118 intel_scaler_info(m, crtc);
3119 intel_plane_info(m, crtc);
3120 }
3121
3122 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3123 yesno(!crtc->cpu_fifo_underrun_disabled),
3124 yesno(!crtc->pch_fifo_underrun_disabled));
3125 }
3126
3127 seq_printf(m, "\n");
3128 seq_printf(m, "Connector info\n");
3129 seq_printf(m, "--------------\n");
3130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3131 intel_connector_info(m, connector);
3132 }
3133 drm_modeset_unlock_all(dev);
3134 intel_runtime_pm_put(dev_priv);
3135
3136 return 0;
3137}
3138
3139static int i915_semaphore_status(struct seq_file *m, void *unused)
3140{
3141 struct drm_info_node *node = (struct drm_info_node *) m->private;
3142 struct drm_device *dev = node->minor->dev;
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144 struct intel_engine_cs *engine;
3145 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3146 enum intel_engine_id id;
3147 int j, ret;
3148
3149 if (!i915_semaphore_is_enabled(dev)) {
3150 seq_puts(m, "Semaphores are disabled\n");
3151 return 0;
3152 }
3153
3154 ret = mutex_lock_interruptible(&dev->struct_mutex);
3155 if (ret)
3156 return ret;
3157 intel_runtime_pm_get(dev_priv);
3158
3159 if (IS_BROADWELL(dev)) {
3160 struct page *page;
3161 uint64_t *seqno;
3162
3163 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3164
3165 seqno = (uint64_t *)kmap_atomic(page);
3166 for_each_engine_id(engine, dev_priv, id) {
3167 uint64_t offset;
3168
3169 seq_printf(m, "%s\n", engine->name);
3170
3171 seq_puts(m, " Last signal:");
3172 for (j = 0; j < num_rings; j++) {
3173 offset = id * I915_NUM_ENGINES + j;
3174 seq_printf(m, "0x%08llx (0x%02llx) ",
3175 seqno[offset], offset * 8);
3176 }
3177 seq_putc(m, '\n');
3178
3179 seq_puts(m, " Last wait: ");
3180 for (j = 0; j < num_rings; j++) {
3181 offset = id + (j * I915_NUM_ENGINES);
3182 seq_printf(m, "0x%08llx (0x%02llx) ",
3183 seqno[offset], offset * 8);
3184 }
3185 seq_putc(m, '\n');
3186
3187 }
3188 kunmap_atomic(seqno);
3189 } else {
3190 seq_puts(m, " Last signal:");
3191 for_each_engine(engine, dev_priv)
3192 for (j = 0; j < num_rings; j++)
3193 seq_printf(m, "0x%08x\n",
3194 I915_READ(engine->semaphore.mbox.signal[j]));
3195 seq_putc(m, '\n');
3196 }
3197
3198 seq_puts(m, "\nSync seqno:\n");
3199 for_each_engine(engine, dev_priv) {
3200 for (j = 0; j < num_rings; j++)
3201 seq_printf(m, " 0x%08x ",
3202 engine->semaphore.sync_seqno[j]);
3203 seq_putc(m, '\n');
3204 }
3205 seq_putc(m, '\n');
3206
3207 intel_runtime_pm_put(dev_priv);
3208 mutex_unlock(&dev->struct_mutex);
3209 return 0;
3210}
3211
3212static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3213{
3214 struct drm_info_node *node = (struct drm_info_node *) m->private;
3215 struct drm_device *dev = node->minor->dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 int i;
3218
3219 drm_modeset_lock_all(dev);
3220 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3221 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3222
3223 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3224 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3225 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3226 seq_printf(m, " tracked hardware state:\n");
3227 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3228 seq_printf(m, " dpll_md: 0x%08x\n",
3229 pll->config.hw_state.dpll_md);
3230 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3231 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3232 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3233 }
3234 drm_modeset_unlock_all(dev);
3235
3236 return 0;
3237}
3238
3239static int i915_wa_registers(struct seq_file *m, void *unused)
3240{
3241 int i;
3242 int ret;
3243 struct intel_engine_cs *engine;
3244 struct drm_info_node *node = (struct drm_info_node *) m->private;
3245 struct drm_device *dev = node->minor->dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3248 enum intel_engine_id id;
3249
3250 ret = mutex_lock_interruptible(&dev->struct_mutex);
3251 if (ret)
3252 return ret;
3253
3254 intel_runtime_pm_get(dev_priv);
3255
3256 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3257 for_each_engine_id(engine, dev_priv, id)
3258 seq_printf(m, "HW whitelist count for %s: %d\n",
3259 engine->name, workarounds->hw_whitelist_count[id]);
3260 for (i = 0; i < workarounds->count; ++i) {
3261 i915_reg_t addr;
3262 u32 mask, value, read;
3263 bool ok;
3264
3265 addr = workarounds->reg[i].addr;
3266 mask = workarounds->reg[i].mask;
3267 value = workarounds->reg[i].value;
3268 read = I915_READ(addr);
3269 ok = (value & mask) == (read & mask);
3270 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3271 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3272 }
3273
3274 intel_runtime_pm_put(dev_priv);
3275 mutex_unlock(&dev->struct_mutex);
3276
3277 return 0;
3278}
3279
3280static int i915_ddb_info(struct seq_file *m, void *unused)
3281{
3282 struct drm_info_node *node = m->private;
3283 struct drm_device *dev = node->minor->dev;
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3285 struct skl_ddb_allocation *ddb;
3286 struct skl_ddb_entry *entry;
3287 enum pipe pipe;
3288 int plane;
3289
3290 if (INTEL_INFO(dev)->gen < 9)
3291 return 0;
3292
3293 drm_modeset_lock_all(dev);
3294
3295 ddb = &dev_priv->wm.skl_hw.ddb;
3296
3297 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3298
3299 for_each_pipe(dev_priv, pipe) {
3300 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3301
3302 for_each_plane(dev_priv, pipe, plane) {
3303 entry = &ddb->plane[pipe][plane];
3304 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3305 entry->start, entry->end,
3306 skl_ddb_entry_size(entry));
3307 }
3308
3309 entry = &ddb->plane[pipe][PLANE_CURSOR];
3310 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3311 entry->end, skl_ddb_entry_size(entry));
3312 }
3313
3314 drm_modeset_unlock_all(dev);
3315
3316 return 0;
3317}
3318
3319static void drrs_status_per_crtc(struct seq_file *m,
3320 struct drm_device *dev, struct intel_crtc *intel_crtc)
3321{
3322 struct intel_encoder *intel_encoder;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct i915_drrs *drrs = &dev_priv->drrs;
3325 int vrefresh = 0;
3326
3327 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3328 /* Encoder connected on this CRTC */
3329 switch (intel_encoder->type) {
3330 case INTEL_OUTPUT_EDP:
3331 seq_puts(m, "eDP:\n");
3332 break;
3333 case INTEL_OUTPUT_DSI:
3334 seq_puts(m, "DSI:\n");
3335 break;
3336 case INTEL_OUTPUT_HDMI:
3337 seq_puts(m, "HDMI:\n");
3338 break;
3339 case INTEL_OUTPUT_DISPLAYPORT:
3340 seq_puts(m, "DP:\n");
3341 break;
3342 default:
3343 seq_printf(m, "Other encoder (id=%d).\n",
3344 intel_encoder->type);
3345 return;
3346 }
3347 }
3348
3349 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3350 seq_puts(m, "\tVBT: DRRS_type: Static");
3351 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3352 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3353 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3354 seq_puts(m, "\tVBT: DRRS_type: None");
3355 else
3356 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3357
3358 seq_puts(m, "\n\n");
3359
3360 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3361 struct intel_panel *panel;
3362
3363 mutex_lock(&drrs->mutex);
3364 /* DRRS Supported */
3365 seq_puts(m, "\tDRRS Supported: Yes\n");
3366
3367 /* disable_drrs() will make drrs->dp NULL */
3368 if (!drrs->dp) {
3369 seq_puts(m, "Idleness DRRS: Disabled");
3370 mutex_unlock(&drrs->mutex);
3371 return;
3372 }
3373
3374 panel = &drrs->dp->attached_connector->panel;
3375 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3376 drrs->busy_frontbuffer_bits);
3377
3378 seq_puts(m, "\n\t\t");
3379 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3380 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3381 vrefresh = panel->fixed_mode->vrefresh;
3382 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3383 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3384 vrefresh = panel->downclock_mode->vrefresh;
3385 } else {
3386 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3387 drrs->refresh_rate_type);
3388 mutex_unlock(&drrs->mutex);
3389 return;
3390 }
3391 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3392
3393 seq_puts(m, "\n\t\t");
3394 mutex_unlock(&drrs->mutex);
3395 } else {
3396 /* DRRS not supported. Print the VBT parameter*/
3397 seq_puts(m, "\tDRRS Supported : No");
3398 }
3399 seq_puts(m, "\n");
3400}
3401
3402static int i915_drrs_status(struct seq_file *m, void *unused)
3403{
3404 struct drm_info_node *node = m->private;
3405 struct drm_device *dev = node->minor->dev;
3406 struct intel_crtc *intel_crtc;
3407 int active_crtc_cnt = 0;
3408
3409 for_each_intel_crtc(dev, intel_crtc) {
3410 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3411
3412 if (intel_crtc->base.state->active) {
3413 active_crtc_cnt++;
3414 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3415
3416 drrs_status_per_crtc(m, dev, intel_crtc);
3417 }
3418
3419 drm_modeset_unlock(&intel_crtc->base.mutex);
3420 }
3421
3422 if (!active_crtc_cnt)
3423 seq_puts(m, "No active crtc found\n");
3424
3425 return 0;
3426}
3427
3428struct pipe_crc_info {
3429 const char *name;
3430 struct drm_device *dev;
3431 enum pipe pipe;
3432};
3433
3434static int i915_dp_mst_info(struct seq_file *m, void *unused)
3435{
3436 struct drm_info_node *node = (struct drm_info_node *) m->private;
3437 struct drm_device *dev = node->minor->dev;
3438 struct drm_encoder *encoder;
3439 struct intel_encoder *intel_encoder;
3440 struct intel_digital_port *intel_dig_port;
3441 drm_modeset_lock_all(dev);
3442 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3443 intel_encoder = to_intel_encoder(encoder);
3444 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3445 continue;
3446 intel_dig_port = enc_to_dig_port(encoder);
3447 if (!intel_dig_port->dp.can_mst)
3448 continue;
3449 seq_printf(m, "MST Source Port %c\n",
3450 port_name(intel_dig_port->port));
3451 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3452 }
3453 drm_modeset_unlock_all(dev);
3454 return 0;
3455}
3456
3457static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3458{
3459 struct pipe_crc_info *info = inode->i_private;
3460 struct drm_i915_private *dev_priv = info->dev->dev_private;
3461 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3462
3463 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3464 return -ENODEV;
3465
3466 spin_lock_irq(&pipe_crc->lock);
3467
3468 if (pipe_crc->opened) {
3469 spin_unlock_irq(&pipe_crc->lock);
3470 return -EBUSY; /* already open */
3471 }
3472
3473 pipe_crc->opened = true;
3474 filep->private_data = inode->i_private;
3475
3476 spin_unlock_irq(&pipe_crc->lock);
3477
3478 return 0;
3479}
3480
3481static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3482{
3483 struct pipe_crc_info *info = inode->i_private;
3484 struct drm_i915_private *dev_priv = info->dev->dev_private;
3485 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3486
3487 spin_lock_irq(&pipe_crc->lock);
3488 pipe_crc->opened = false;
3489 spin_unlock_irq(&pipe_crc->lock);
3490
3491 return 0;
3492}
3493
3494/* (6 fields, 8 chars each, space separated (5) + '\n') */
3495#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3496/* account for \'0' */
3497#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3498
3499static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3500{
3501 assert_spin_locked(&pipe_crc->lock);
3502 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3503 INTEL_PIPE_CRC_ENTRIES_NR);
3504}
3505
3506static ssize_t
3507i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3508 loff_t *pos)
3509{
3510 struct pipe_crc_info *info = filep->private_data;
3511 struct drm_device *dev = info->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3514 char buf[PIPE_CRC_BUFFER_LEN];
3515 int n_entries;
3516 ssize_t bytes_read;
3517
3518 /*
3519 * Don't allow user space to provide buffers not big enough to hold
3520 * a line of data.
3521 */
3522 if (count < PIPE_CRC_LINE_LEN)
3523 return -EINVAL;
3524
3525 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3526 return 0;
3527
3528 /* nothing to read */
3529 spin_lock_irq(&pipe_crc->lock);
3530 while (pipe_crc_data_count(pipe_crc) == 0) {
3531 int ret;
3532
3533 if (filep->f_flags & O_NONBLOCK) {
3534 spin_unlock_irq(&pipe_crc->lock);
3535 return -EAGAIN;
3536 }
3537
3538 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3539 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3540 if (ret) {
3541 spin_unlock_irq(&pipe_crc->lock);
3542 return ret;
3543 }
3544 }
3545
3546 /* We now have one or more entries to read */
3547 n_entries = count / PIPE_CRC_LINE_LEN;
3548
3549 bytes_read = 0;
3550 while (n_entries > 0) {
3551 struct intel_pipe_crc_entry *entry =
3552 &pipe_crc->entries[pipe_crc->tail];
3553 int ret;
3554
3555 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3556 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3557 break;
3558
3559 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3560 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3561
3562 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3563 "%8u %8x %8x %8x %8x %8x\n",
3564 entry->frame, entry->crc[0],
3565 entry->crc[1], entry->crc[2],
3566 entry->crc[3], entry->crc[4]);
3567
3568 spin_unlock_irq(&pipe_crc->lock);
3569
3570 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3571 if (ret == PIPE_CRC_LINE_LEN)
3572 return -EFAULT;
3573
3574 user_buf += PIPE_CRC_LINE_LEN;
3575 n_entries--;
3576
3577 spin_lock_irq(&pipe_crc->lock);
3578 }
3579
3580 spin_unlock_irq(&pipe_crc->lock);
3581
3582 return bytes_read;
3583}
3584
3585static const struct file_operations i915_pipe_crc_fops = {
3586 .owner = THIS_MODULE,
3587 .open = i915_pipe_crc_open,
3588 .read = i915_pipe_crc_read,
3589 .release = i915_pipe_crc_release,
3590};
3591
3592static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3593 {
3594 .name = "i915_pipe_A_crc",
3595 .pipe = PIPE_A,
3596 },
3597 {
3598 .name = "i915_pipe_B_crc",
3599 .pipe = PIPE_B,
3600 },
3601 {
3602 .name = "i915_pipe_C_crc",
3603 .pipe = PIPE_C,
3604 },
3605};
3606
3607static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3608 enum pipe pipe)
3609{
3610 struct drm_device *dev = minor->dev;
3611 struct dentry *ent;
3612 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3613
3614 info->dev = dev;
3615 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3616 &i915_pipe_crc_fops);
3617 if (!ent)
3618 return -ENOMEM;
3619
3620 return drm_add_fake_info_node(minor, ent, info);
3621}
3622
3623static const char * const pipe_crc_sources[] = {
3624 "none",
3625 "plane1",
3626 "plane2",
3627 "pf",
3628 "pipe",
3629 "TV",
3630 "DP-B",
3631 "DP-C",
3632 "DP-D",
3633 "auto",
3634};
3635
3636static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3637{
3638 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3639 return pipe_crc_sources[source];
3640}
3641
3642static int display_crc_ctl_show(struct seq_file *m, void *data)
3643{
3644 struct drm_device *dev = m->private;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 int i;
3647
3648 for (i = 0; i < I915_MAX_PIPES; i++)
3649 seq_printf(m, "%c %s\n", pipe_name(i),
3650 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3651
3652 return 0;
3653}
3654
3655static int display_crc_ctl_open(struct inode *inode, struct file *file)
3656{
3657 struct drm_device *dev = inode->i_private;
3658
3659 return single_open(file, display_crc_ctl_show, dev);
3660}
3661
3662static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3663 uint32_t *val)
3664{
3665 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3666 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3667
3668 switch (*source) {
3669 case INTEL_PIPE_CRC_SOURCE_PIPE:
3670 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3671 break;
3672 case INTEL_PIPE_CRC_SOURCE_NONE:
3673 *val = 0;
3674 break;
3675 default:
3676 return -EINVAL;
3677 }
3678
3679 return 0;
3680}
3681
3682static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3683 enum intel_pipe_crc_source *source)
3684{
3685 struct intel_encoder *encoder;
3686 struct intel_crtc *crtc;
3687 struct intel_digital_port *dig_port;
3688 int ret = 0;
3689
3690 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3691
3692 drm_modeset_lock_all(dev);
3693 for_each_intel_encoder(dev, encoder) {
3694 if (!encoder->base.crtc)
3695 continue;
3696
3697 crtc = to_intel_crtc(encoder->base.crtc);
3698
3699 if (crtc->pipe != pipe)
3700 continue;
3701
3702 switch (encoder->type) {
3703 case INTEL_OUTPUT_TVOUT:
3704 *source = INTEL_PIPE_CRC_SOURCE_TV;
3705 break;
3706 case INTEL_OUTPUT_DISPLAYPORT:
3707 case INTEL_OUTPUT_EDP:
3708 dig_port = enc_to_dig_port(&encoder->base);
3709 switch (dig_port->port) {
3710 case PORT_B:
3711 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3712 break;
3713 case PORT_C:
3714 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3715 break;
3716 case PORT_D:
3717 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3718 break;
3719 default:
3720 WARN(1, "nonexisting DP port %c\n",
3721 port_name(dig_port->port));
3722 break;
3723 }
3724 break;
3725 default:
3726 break;
3727 }
3728 }
3729 drm_modeset_unlock_all(dev);
3730
3731 return ret;
3732}
3733
3734static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3735 enum pipe pipe,
3736 enum intel_pipe_crc_source *source,
3737 uint32_t *val)
3738{
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 bool need_stable_symbols = false;
3741
3742 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3743 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3744 if (ret)
3745 return ret;
3746 }
3747
3748 switch (*source) {
3749 case INTEL_PIPE_CRC_SOURCE_PIPE:
3750 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3751 break;
3752 case INTEL_PIPE_CRC_SOURCE_DP_B:
3753 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3754 need_stable_symbols = true;
3755 break;
3756 case INTEL_PIPE_CRC_SOURCE_DP_C:
3757 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3758 need_stable_symbols = true;
3759 break;
3760 case INTEL_PIPE_CRC_SOURCE_DP_D:
3761 if (!IS_CHERRYVIEW(dev))
3762 return -EINVAL;
3763 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3764 need_stable_symbols = true;
3765 break;
3766 case INTEL_PIPE_CRC_SOURCE_NONE:
3767 *val = 0;
3768 break;
3769 default:
3770 return -EINVAL;
3771 }
3772
3773 /*
3774 * When the pipe CRC tap point is after the transcoders we need
3775 * to tweak symbol-level features to produce a deterministic series of
3776 * symbols for a given frame. We need to reset those features only once
3777 * a frame (instead of every nth symbol):
3778 * - DC-balance: used to ensure a better clock recovery from the data
3779 * link (SDVO)
3780 * - DisplayPort scrambling: used for EMI reduction
3781 */
3782 if (need_stable_symbols) {
3783 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3784
3785 tmp |= DC_BALANCE_RESET_VLV;
3786 switch (pipe) {
3787 case PIPE_A:
3788 tmp |= PIPE_A_SCRAMBLE_RESET;
3789 break;
3790 case PIPE_B:
3791 tmp |= PIPE_B_SCRAMBLE_RESET;
3792 break;
3793 case PIPE_C:
3794 tmp |= PIPE_C_SCRAMBLE_RESET;
3795 break;
3796 default:
3797 return -EINVAL;
3798 }
3799 I915_WRITE(PORT_DFT2_G4X, tmp);
3800 }
3801
3802 return 0;
3803}
3804
3805static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3806 enum pipe pipe,
3807 enum intel_pipe_crc_source *source,
3808 uint32_t *val)
3809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 bool need_stable_symbols = false;
3812
3813 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3814 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3815 if (ret)
3816 return ret;
3817 }
3818
3819 switch (*source) {
3820 case INTEL_PIPE_CRC_SOURCE_PIPE:
3821 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3822 break;
3823 case INTEL_PIPE_CRC_SOURCE_TV:
3824 if (!SUPPORTS_TV(dev))
3825 return -EINVAL;
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3827 break;
3828 case INTEL_PIPE_CRC_SOURCE_DP_B:
3829 if (!IS_G4X(dev))
3830 return -EINVAL;
3831 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3832 need_stable_symbols = true;
3833 break;
3834 case INTEL_PIPE_CRC_SOURCE_DP_C:
3835 if (!IS_G4X(dev))
3836 return -EINVAL;
3837 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3838 need_stable_symbols = true;
3839 break;
3840 case INTEL_PIPE_CRC_SOURCE_DP_D:
3841 if (!IS_G4X(dev))
3842 return -EINVAL;
3843 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3844 need_stable_symbols = true;
3845 break;
3846 case INTEL_PIPE_CRC_SOURCE_NONE:
3847 *val = 0;
3848 break;
3849 default:
3850 return -EINVAL;
3851 }
3852
3853 /*
3854 * When the pipe CRC tap point is after the transcoders we need
3855 * to tweak symbol-level features to produce a deterministic series of
3856 * symbols for a given frame. We need to reset those features only once
3857 * a frame (instead of every nth symbol):
3858 * - DC-balance: used to ensure a better clock recovery from the data
3859 * link (SDVO)
3860 * - DisplayPort scrambling: used for EMI reduction
3861 */
3862 if (need_stable_symbols) {
3863 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3864
3865 WARN_ON(!IS_G4X(dev));
3866
3867 I915_WRITE(PORT_DFT_I9XX,
3868 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3869
3870 if (pipe == PIPE_A)
3871 tmp |= PIPE_A_SCRAMBLE_RESET;
3872 else
3873 tmp |= PIPE_B_SCRAMBLE_RESET;
3874
3875 I915_WRITE(PORT_DFT2_G4X, tmp);
3876 }
3877
3878 return 0;
3879}
3880
3881static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3882 enum pipe pipe)
3883{
3884 struct drm_i915_private *dev_priv = dev->dev_private;
3885 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3886
3887 switch (pipe) {
3888 case PIPE_A:
3889 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3890 break;
3891 case PIPE_B:
3892 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3893 break;
3894 case PIPE_C:
3895 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3896 break;
3897 default:
3898 return;
3899 }
3900 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3901 tmp &= ~DC_BALANCE_RESET_VLV;
3902 I915_WRITE(PORT_DFT2_G4X, tmp);
3903
3904}
3905
3906static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3907 enum pipe pipe)
3908{
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3911
3912 if (pipe == PIPE_A)
3913 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3914 else
3915 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3916 I915_WRITE(PORT_DFT2_G4X, tmp);
3917
3918 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3919 I915_WRITE(PORT_DFT_I9XX,
3920 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3921 }
3922}
3923
3924static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3925 uint32_t *val)
3926{
3927 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3928 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3929
3930 switch (*source) {
3931 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3932 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3933 break;
3934 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3935 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3936 break;
3937 case INTEL_PIPE_CRC_SOURCE_PIPE:
3938 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3939 break;
3940 case INTEL_PIPE_CRC_SOURCE_NONE:
3941 *val = 0;
3942 break;
3943 default:
3944 return -EINVAL;
3945 }
3946
3947 return 0;
3948}
3949
3950static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3951{
3952 struct drm_i915_private *dev_priv = dev->dev_private;
3953 struct intel_crtc *crtc =
3954 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3955 struct intel_crtc_state *pipe_config;
3956 struct drm_atomic_state *state;
3957 int ret = 0;
3958
3959 drm_modeset_lock_all(dev);
3960 state = drm_atomic_state_alloc(dev);
3961 if (!state) {
3962 ret = -ENOMEM;
3963 goto out;
3964 }
3965
3966 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3967 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3968 if (IS_ERR(pipe_config)) {
3969 ret = PTR_ERR(pipe_config);
3970 goto out;
3971 }
3972
3973 pipe_config->pch_pfit.force_thru = enable;
3974 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3975 pipe_config->pch_pfit.enabled != enable)
3976 pipe_config->base.connectors_changed = true;
3977
3978 ret = drm_atomic_commit(state);
3979out:
3980 drm_modeset_unlock_all(dev);
3981 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3982 if (ret)
3983 drm_atomic_state_free(state);
3984}
3985
3986static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3987 enum pipe pipe,
3988 enum intel_pipe_crc_source *source,
3989 uint32_t *val)
3990{
3991 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3992 *source = INTEL_PIPE_CRC_SOURCE_PF;
3993
3994 switch (*source) {
3995 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3996 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3997 break;
3998 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3999 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4000 break;
4001 case INTEL_PIPE_CRC_SOURCE_PF:
4002 if (IS_HASWELL(dev) && pipe == PIPE_A)
4003 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4004
4005 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4006 break;
4007 case INTEL_PIPE_CRC_SOURCE_NONE:
4008 *val = 0;
4009 break;
4010 default:
4011 return -EINVAL;
4012 }
4013
4014 return 0;
4015}
4016
4017static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4018 enum intel_pipe_crc_source source)
4019{
4020 struct drm_i915_private *dev_priv = dev->dev_private;
4021 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4022 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4023 pipe));
4024 enum intel_display_power_domain power_domain;
4025 u32 val = 0; /* shut up gcc */
4026 int ret;
4027
4028 if (pipe_crc->source == source)
4029 return 0;
4030
4031 /* forbid changing the source without going back to 'none' */
4032 if (pipe_crc->source && source)
4033 return -EINVAL;
4034
4035 power_domain = POWER_DOMAIN_PIPE(pipe);
4036 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4037 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4038 return -EIO;
4039 }
4040
4041 if (IS_GEN2(dev))
4042 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4043 else if (INTEL_INFO(dev)->gen < 5)
4044 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4045 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4046 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4047 else if (IS_GEN5(dev) || IS_GEN6(dev))
4048 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4049 else
4050 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4051
4052 if (ret != 0)
4053 goto out;
4054
4055 /* none -> real source transition */
4056 if (source) {
4057 struct intel_pipe_crc_entry *entries;
4058
4059 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4060 pipe_name(pipe), pipe_crc_source_name(source));
4061
4062 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4063 sizeof(pipe_crc->entries[0]),
4064 GFP_KERNEL);
4065 if (!entries) {
4066 ret = -ENOMEM;
4067 goto out;
4068 }
4069
4070 /*
4071 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4072 * enabled and disabled dynamically based on package C states,
4073 * user space can't make reliable use of the CRCs, so let's just
4074 * completely disable it.
4075 */
4076 hsw_disable_ips(crtc);
4077
4078 spin_lock_irq(&pipe_crc->lock);
4079 kfree(pipe_crc->entries);
4080 pipe_crc->entries = entries;
4081 pipe_crc->head = 0;
4082 pipe_crc->tail = 0;
4083 spin_unlock_irq(&pipe_crc->lock);
4084 }
4085
4086 pipe_crc->source = source;
4087
4088 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4089 POSTING_READ(PIPE_CRC_CTL(pipe));
4090
4091 /* real source -> none transition */
4092 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4093 struct intel_pipe_crc_entry *entries;
4094 struct intel_crtc *crtc =
4095 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4096
4097 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4098 pipe_name(pipe));
4099
4100 drm_modeset_lock(&crtc->base.mutex, NULL);
4101 if (crtc->base.state->active)
4102 intel_wait_for_vblank(dev, pipe);
4103 drm_modeset_unlock(&crtc->base.mutex);
4104
4105 spin_lock_irq(&pipe_crc->lock);
4106 entries = pipe_crc->entries;
4107 pipe_crc->entries = NULL;
4108 pipe_crc->head = 0;
4109 pipe_crc->tail = 0;
4110 spin_unlock_irq(&pipe_crc->lock);
4111
4112 kfree(entries);
4113
4114 if (IS_G4X(dev))
4115 g4x_undo_pipe_scramble_reset(dev, pipe);
4116 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4117 vlv_undo_pipe_scramble_reset(dev, pipe);
4118 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4119 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4120
4121 hsw_enable_ips(crtc);
4122 }
4123
4124 ret = 0;
4125
4126out:
4127 intel_display_power_put(dev_priv, power_domain);
4128
4129 return ret;
4130}
4131
4132/*
4133 * Parse pipe CRC command strings:
4134 * command: wsp* object wsp+ name wsp+ source wsp*
4135 * object: 'pipe'
4136 * name: (A | B | C)
4137 * source: (none | plane1 | plane2 | pf)
4138 * wsp: (#0x20 | #0x9 | #0xA)+
4139 *
4140 * eg.:
4141 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4142 * "pipe A none" -> Stop CRC
4143 */
4144static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4145{
4146 int n_words = 0;
4147
4148 while (*buf) {
4149 char *end;
4150
4151 /* skip leading white space */
4152 buf = skip_spaces(buf);
4153 if (!*buf)
4154 break; /* end of buffer */
4155
4156 /* find end of word */
4157 for (end = buf; *end && !isspace(*end); end++)
4158 ;
4159
4160 if (n_words == max_words) {
4161 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4162 max_words);
4163 return -EINVAL; /* ran out of words[] before bytes */
4164 }
4165
4166 if (*end)
4167 *end++ = '\0';
4168 words[n_words++] = buf;
4169 buf = end;
4170 }
4171
4172 return n_words;
4173}
4174
4175enum intel_pipe_crc_object {
4176 PIPE_CRC_OBJECT_PIPE,
4177};
4178
4179static const char * const pipe_crc_objects[] = {
4180 "pipe",
4181};
4182
4183static int
4184display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4185{
4186 int i;
4187
4188 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4189 if (!strcmp(buf, pipe_crc_objects[i])) {
4190 *o = i;
4191 return 0;
4192 }
4193
4194 return -EINVAL;
4195}
4196
4197static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4198{
4199 const char name = buf[0];
4200
4201 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4202 return -EINVAL;
4203
4204 *pipe = name - 'A';
4205
4206 return 0;
4207}
4208
4209static int
4210display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4211{
4212 int i;
4213
4214 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4215 if (!strcmp(buf, pipe_crc_sources[i])) {
4216 *s = i;
4217 return 0;
4218 }
4219
4220 return -EINVAL;
4221}
4222
4223static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4224{
4225#define N_WORDS 3
4226 int n_words;
4227 char *words[N_WORDS];
4228 enum pipe pipe;
4229 enum intel_pipe_crc_object object;
4230 enum intel_pipe_crc_source source;
4231
4232 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4233 if (n_words != N_WORDS) {
4234 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4235 N_WORDS);
4236 return -EINVAL;
4237 }
4238
4239 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4240 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4241 return -EINVAL;
4242 }
4243
4244 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4245 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4246 return -EINVAL;
4247 }
4248
4249 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4250 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4251 return -EINVAL;
4252 }
4253
4254 return pipe_crc_set_source(dev, pipe, source);
4255}
4256
4257static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4258 size_t len, loff_t *offp)
4259{
4260 struct seq_file *m = file->private_data;
4261 struct drm_device *dev = m->private;
4262 char *tmpbuf;
4263 int ret;
4264
4265 if (len == 0)
4266 return 0;
4267
4268 if (len > PAGE_SIZE - 1) {
4269 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4270 PAGE_SIZE);
4271 return -E2BIG;
4272 }
4273
4274 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4275 if (!tmpbuf)
4276 return -ENOMEM;
4277
4278 if (copy_from_user(tmpbuf, ubuf, len)) {
4279 ret = -EFAULT;
4280 goto out;
4281 }
4282 tmpbuf[len] = '\0';
4283
4284 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4285
4286out:
4287 kfree(tmpbuf);
4288 if (ret < 0)
4289 return ret;
4290
4291 *offp += len;
4292 return len;
4293}
4294
4295static const struct file_operations i915_display_crc_ctl_fops = {
4296 .owner = THIS_MODULE,
4297 .open = display_crc_ctl_open,
4298 .read = seq_read,
4299 .llseek = seq_lseek,
4300 .release = single_release,
4301 .write = display_crc_ctl_write
4302};
4303
4304static ssize_t i915_displayport_test_active_write(struct file *file,
4305 const char __user *ubuf,
4306 size_t len, loff_t *offp)
4307{
4308 char *input_buffer;
4309 int status = 0;
4310 struct drm_device *dev;
4311 struct drm_connector *connector;
4312 struct list_head *connector_list;
4313 struct intel_dp *intel_dp;
4314 int val = 0;
4315
4316 dev = ((struct seq_file *)file->private_data)->private;
4317
4318 connector_list = &dev->mode_config.connector_list;
4319
4320 if (len == 0)
4321 return 0;
4322
4323 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4324 if (!input_buffer)
4325 return -ENOMEM;
4326
4327 if (copy_from_user(input_buffer, ubuf, len)) {
4328 status = -EFAULT;
4329 goto out;
4330 }
4331
4332 input_buffer[len] = '\0';
4333 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4334
4335 list_for_each_entry(connector, connector_list, head) {
4336
4337 if (connector->connector_type !=
4338 DRM_MODE_CONNECTOR_DisplayPort)
4339 continue;
4340
4341 if (connector->status == connector_status_connected &&
4342 connector->encoder != NULL) {
4343 intel_dp = enc_to_intel_dp(connector->encoder);
4344 status = kstrtoint(input_buffer, 10, &val);
4345 if (status < 0)
4346 goto out;
4347 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4348 /* To prevent erroneous activation of the compliance
4349 * testing code, only accept an actual value of 1 here
4350 */
4351 if (val == 1)
4352 intel_dp->compliance_test_active = 1;
4353 else
4354 intel_dp->compliance_test_active = 0;
4355 }
4356 }
4357out:
4358 kfree(input_buffer);
4359 if (status < 0)
4360 return status;
4361
4362 *offp += len;
4363 return len;
4364}
4365
4366static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4367{
4368 struct drm_device *dev = m->private;
4369 struct drm_connector *connector;
4370 struct list_head *connector_list = &dev->mode_config.connector_list;
4371 struct intel_dp *intel_dp;
4372
4373 list_for_each_entry(connector, connector_list, head) {
4374
4375 if (connector->connector_type !=
4376 DRM_MODE_CONNECTOR_DisplayPort)
4377 continue;
4378
4379 if (connector->status == connector_status_connected &&
4380 connector->encoder != NULL) {
4381 intel_dp = enc_to_intel_dp(connector->encoder);
4382 if (intel_dp->compliance_test_active)
4383 seq_puts(m, "1");
4384 else
4385 seq_puts(m, "0");
4386 } else
4387 seq_puts(m, "0");
4388 }
4389
4390 return 0;
4391}
4392
4393static int i915_displayport_test_active_open(struct inode *inode,
4394 struct file *file)
4395{
4396 struct drm_device *dev = inode->i_private;
4397
4398 return single_open(file, i915_displayport_test_active_show, dev);
4399}
4400
4401static const struct file_operations i915_displayport_test_active_fops = {
4402 .owner = THIS_MODULE,
4403 .open = i915_displayport_test_active_open,
4404 .read = seq_read,
4405 .llseek = seq_lseek,
4406 .release = single_release,
4407 .write = i915_displayport_test_active_write
4408};
4409
4410static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4411{
4412 struct drm_device *dev = m->private;
4413 struct drm_connector *connector;
4414 struct list_head *connector_list = &dev->mode_config.connector_list;
4415 struct intel_dp *intel_dp;
4416
4417 list_for_each_entry(connector, connector_list, head) {
4418
4419 if (connector->connector_type !=
4420 DRM_MODE_CONNECTOR_DisplayPort)
4421 continue;
4422
4423 if (connector->status == connector_status_connected &&
4424 connector->encoder != NULL) {
4425 intel_dp = enc_to_intel_dp(connector->encoder);
4426 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4427 } else
4428 seq_puts(m, "0");
4429 }
4430
4431 return 0;
4432}
4433static int i915_displayport_test_data_open(struct inode *inode,
4434 struct file *file)
4435{
4436 struct drm_device *dev = inode->i_private;
4437
4438 return single_open(file, i915_displayport_test_data_show, dev);
4439}
4440
4441static const struct file_operations i915_displayport_test_data_fops = {
4442 .owner = THIS_MODULE,
4443 .open = i915_displayport_test_data_open,
4444 .read = seq_read,
4445 .llseek = seq_lseek,
4446 .release = single_release
4447};
4448
4449static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4450{
4451 struct drm_device *dev = m->private;
4452 struct drm_connector *connector;
4453 struct list_head *connector_list = &dev->mode_config.connector_list;
4454 struct intel_dp *intel_dp;
4455
4456 list_for_each_entry(connector, connector_list, head) {
4457
4458 if (connector->connector_type !=
4459 DRM_MODE_CONNECTOR_DisplayPort)
4460 continue;
4461
4462 if (connector->status == connector_status_connected &&
4463 connector->encoder != NULL) {
4464 intel_dp = enc_to_intel_dp(connector->encoder);
4465 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4466 } else
4467 seq_puts(m, "0");
4468 }
4469
4470 return 0;
4471}
4472
4473static int i915_displayport_test_type_open(struct inode *inode,
4474 struct file *file)
4475{
4476 struct drm_device *dev = inode->i_private;
4477
4478 return single_open(file, i915_displayport_test_type_show, dev);
4479}
4480
4481static const struct file_operations i915_displayport_test_type_fops = {
4482 .owner = THIS_MODULE,
4483 .open = i915_displayport_test_type_open,
4484 .read = seq_read,
4485 .llseek = seq_lseek,
4486 .release = single_release
4487};
4488
4489static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4490{
4491 struct drm_device *dev = m->private;
4492 int level;
4493 int num_levels;
4494
4495 if (IS_CHERRYVIEW(dev))
4496 num_levels = 3;
4497 else if (IS_VALLEYVIEW(dev))
4498 num_levels = 1;
4499 else
4500 num_levels = ilk_wm_max_level(dev) + 1;
4501
4502 drm_modeset_lock_all(dev);
4503
4504 for (level = 0; level < num_levels; level++) {
4505 unsigned int latency = wm[level];
4506
4507 /*
4508 * - WM1+ latency values in 0.5us units
4509 * - latencies are in us on gen9/vlv/chv
4510 */
4511 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4512 IS_CHERRYVIEW(dev))
4513 latency *= 10;
4514 else if (level > 0)
4515 latency *= 5;
4516
4517 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4518 level, wm[level], latency / 10, latency % 10);
4519 }
4520
4521 drm_modeset_unlock_all(dev);
4522}
4523
4524static int pri_wm_latency_show(struct seq_file *m, void *data)
4525{
4526 struct drm_device *dev = m->private;
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 const uint16_t *latencies;
4529
4530 if (INTEL_INFO(dev)->gen >= 9)
4531 latencies = dev_priv->wm.skl_latency;
4532 else
4533 latencies = to_i915(dev)->wm.pri_latency;
4534
4535 wm_latency_show(m, latencies);
4536
4537 return 0;
4538}
4539
4540static int spr_wm_latency_show(struct seq_file *m, void *data)
4541{
4542 struct drm_device *dev = m->private;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 const uint16_t *latencies;
4545
4546 if (INTEL_INFO(dev)->gen >= 9)
4547 latencies = dev_priv->wm.skl_latency;
4548 else
4549 latencies = to_i915(dev)->wm.spr_latency;
4550
4551 wm_latency_show(m, latencies);
4552
4553 return 0;
4554}
4555
4556static int cur_wm_latency_show(struct seq_file *m, void *data)
4557{
4558 struct drm_device *dev = m->private;
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 const uint16_t *latencies;
4561
4562 if (INTEL_INFO(dev)->gen >= 9)
4563 latencies = dev_priv->wm.skl_latency;
4564 else
4565 latencies = to_i915(dev)->wm.cur_latency;
4566
4567 wm_latency_show(m, latencies);
4568
4569 return 0;
4570}
4571
4572static int pri_wm_latency_open(struct inode *inode, struct file *file)
4573{
4574 struct drm_device *dev = inode->i_private;
4575
4576 if (INTEL_INFO(dev)->gen < 5)
4577 return -ENODEV;
4578
4579 return single_open(file, pri_wm_latency_show, dev);
4580}
4581
4582static int spr_wm_latency_open(struct inode *inode, struct file *file)
4583{
4584 struct drm_device *dev = inode->i_private;
4585
4586 if (HAS_GMCH_DISPLAY(dev))
4587 return -ENODEV;
4588
4589 return single_open(file, spr_wm_latency_show, dev);
4590}
4591
4592static int cur_wm_latency_open(struct inode *inode, struct file *file)
4593{
4594 struct drm_device *dev = inode->i_private;
4595
4596 if (HAS_GMCH_DISPLAY(dev))
4597 return -ENODEV;
4598
4599 return single_open(file, cur_wm_latency_show, dev);
4600}
4601
4602static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4603 size_t len, loff_t *offp, uint16_t wm[8])
4604{
4605 struct seq_file *m = file->private_data;
4606 struct drm_device *dev = m->private;
4607 uint16_t new[8] = { 0 };
4608 int num_levels;
4609 int level;
4610 int ret;
4611 char tmp[32];
4612
4613 if (IS_CHERRYVIEW(dev))
4614 num_levels = 3;
4615 else if (IS_VALLEYVIEW(dev))
4616 num_levels = 1;
4617 else
4618 num_levels = ilk_wm_max_level(dev) + 1;
4619
4620 if (len >= sizeof(tmp))
4621 return -EINVAL;
4622
4623 if (copy_from_user(tmp, ubuf, len))
4624 return -EFAULT;
4625
4626 tmp[len] = '\0';
4627
4628 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4629 &new[0], &new[1], &new[2], &new[3],
4630 &new[4], &new[5], &new[6], &new[7]);
4631 if (ret != num_levels)
4632 return -EINVAL;
4633
4634 drm_modeset_lock_all(dev);
4635
4636 for (level = 0; level < num_levels; level++)
4637 wm[level] = new[level];
4638
4639 drm_modeset_unlock_all(dev);
4640
4641 return len;
4642}
4643
4644
4645static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4646 size_t len, loff_t *offp)
4647{
4648 struct seq_file *m = file->private_data;
4649 struct drm_device *dev = m->private;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651 uint16_t *latencies;
4652
4653 if (INTEL_INFO(dev)->gen >= 9)
4654 latencies = dev_priv->wm.skl_latency;
4655 else
4656 latencies = to_i915(dev)->wm.pri_latency;
4657
4658 return wm_latency_write(file, ubuf, len, offp, latencies);
4659}
4660
4661static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4662 size_t len, loff_t *offp)
4663{
4664 struct seq_file *m = file->private_data;
4665 struct drm_device *dev = m->private;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 uint16_t *latencies;
4668
4669 if (INTEL_INFO(dev)->gen >= 9)
4670 latencies = dev_priv->wm.skl_latency;
4671 else
4672 latencies = to_i915(dev)->wm.spr_latency;
4673
4674 return wm_latency_write(file, ubuf, len, offp, latencies);
4675}
4676
4677static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4678 size_t len, loff_t *offp)
4679{
4680 struct seq_file *m = file->private_data;
4681 struct drm_device *dev = m->private;
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683 uint16_t *latencies;
4684
4685 if (INTEL_INFO(dev)->gen >= 9)
4686 latencies = dev_priv->wm.skl_latency;
4687 else
4688 latencies = to_i915(dev)->wm.cur_latency;
4689
4690 return wm_latency_write(file, ubuf, len, offp, latencies);
4691}
4692
4693static const struct file_operations i915_pri_wm_latency_fops = {
4694 .owner = THIS_MODULE,
4695 .open = pri_wm_latency_open,
4696 .read = seq_read,
4697 .llseek = seq_lseek,
4698 .release = single_release,
4699 .write = pri_wm_latency_write
4700};
4701
4702static const struct file_operations i915_spr_wm_latency_fops = {
4703 .owner = THIS_MODULE,
4704 .open = spr_wm_latency_open,
4705 .read = seq_read,
4706 .llseek = seq_lseek,
4707 .release = single_release,
4708 .write = spr_wm_latency_write
4709};
4710
4711static const struct file_operations i915_cur_wm_latency_fops = {
4712 .owner = THIS_MODULE,
4713 .open = cur_wm_latency_open,
4714 .read = seq_read,
4715 .llseek = seq_lseek,
4716 .release = single_release,
4717 .write = cur_wm_latency_write
4718};
4719
4720static int
4721i915_wedged_get(void *data, u64 *val)
4722{
4723 struct drm_device *dev = data;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725
4726 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4727
4728 return 0;
4729}
4730
4731static int
4732i915_wedged_set(void *data, u64 val)
4733{
4734 struct drm_device *dev = data;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736
4737 /*
4738 * There is no safeguard against this debugfs entry colliding
4739 * with the hangcheck calling same i915_handle_error() in
4740 * parallel, causing an explosion. For now we assume that the
4741 * test harness is responsible enough not to inject gpu hangs
4742 * while it is writing to 'i915_wedged'
4743 */
4744
4745 if (i915_reset_in_progress(&dev_priv->gpu_error))
4746 return -EAGAIN;
4747
4748 intel_runtime_pm_get(dev_priv);
4749
4750 i915_handle_error(dev, val,
4751 "Manually setting wedged to %llu", val);
4752
4753 intel_runtime_pm_put(dev_priv);
4754
4755 return 0;
4756}
4757
4758DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4759 i915_wedged_get, i915_wedged_set,
4760 "%llu\n");
4761
4762static int
4763i915_ring_stop_get(void *data, u64 *val)
4764{
4765 struct drm_device *dev = data;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767
4768 *val = dev_priv->gpu_error.stop_rings;
4769
4770 return 0;
4771}
4772
4773static int
4774i915_ring_stop_set(void *data, u64 val)
4775{
4776 struct drm_device *dev = data;
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4778 int ret;
4779
4780 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4781
4782 ret = mutex_lock_interruptible(&dev->struct_mutex);
4783 if (ret)
4784 return ret;
4785
4786 dev_priv->gpu_error.stop_rings = val;
4787 mutex_unlock(&dev->struct_mutex);
4788
4789 return 0;
4790}
4791
4792DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4793 i915_ring_stop_get, i915_ring_stop_set,
4794 "0x%08llx\n");
4795
4796static int
4797i915_ring_missed_irq_get(void *data, u64 *val)
4798{
4799 struct drm_device *dev = data;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801
4802 *val = dev_priv->gpu_error.missed_irq_rings;
4803 return 0;
4804}
4805
4806static int
4807i915_ring_missed_irq_set(void *data, u64 val)
4808{
4809 struct drm_device *dev = data;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 int ret;
4812
4813 /* Lock against concurrent debugfs callers */
4814 ret = mutex_lock_interruptible(&dev->struct_mutex);
4815 if (ret)
4816 return ret;
4817 dev_priv->gpu_error.missed_irq_rings = val;
4818 mutex_unlock(&dev->struct_mutex);
4819
4820 return 0;
4821}
4822
4823DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4824 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4825 "0x%08llx\n");
4826
4827static int
4828i915_ring_test_irq_get(void *data, u64 *val)
4829{
4830 struct drm_device *dev = data;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832
4833 *val = dev_priv->gpu_error.test_irq_rings;
4834
4835 return 0;
4836}
4837
4838static int
4839i915_ring_test_irq_set(void *data, u64 val)
4840{
4841 struct drm_device *dev = data;
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 int ret;
4844
4845 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4846
4847 /* Lock against concurrent debugfs callers */
4848 ret = mutex_lock_interruptible(&dev->struct_mutex);
4849 if (ret)
4850 return ret;
4851
4852 dev_priv->gpu_error.test_irq_rings = val;
4853 mutex_unlock(&dev->struct_mutex);
4854
4855 return 0;
4856}
4857
4858DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4859 i915_ring_test_irq_get, i915_ring_test_irq_set,
4860 "0x%08llx\n");
4861
4862#define DROP_UNBOUND 0x1
4863#define DROP_BOUND 0x2
4864#define DROP_RETIRE 0x4
4865#define DROP_ACTIVE 0x8
4866#define DROP_ALL (DROP_UNBOUND | \
4867 DROP_BOUND | \
4868 DROP_RETIRE | \
4869 DROP_ACTIVE)
4870static int
4871i915_drop_caches_get(void *data, u64 *val)
4872{
4873 *val = DROP_ALL;
4874
4875 return 0;
4876}
4877
4878static int
4879i915_drop_caches_set(void *data, u64 val)
4880{
4881 struct drm_device *dev = data;
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883 int ret;
4884
4885 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4886
4887 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4888 * on ioctls on -EAGAIN. */
4889 ret = mutex_lock_interruptible(&dev->struct_mutex);
4890 if (ret)
4891 return ret;
4892
4893 if (val & DROP_ACTIVE) {
4894 ret = i915_gpu_idle(dev);
4895 if (ret)
4896 goto unlock;
4897 }
4898
4899 if (val & (DROP_RETIRE | DROP_ACTIVE))
4900 i915_gem_retire_requests(dev);
4901
4902 if (val & DROP_BOUND)
4903 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4904
4905 if (val & DROP_UNBOUND)
4906 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4907
4908unlock:
4909 mutex_unlock(&dev->struct_mutex);
4910
4911 return ret;
4912}
4913
4914DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4915 i915_drop_caches_get, i915_drop_caches_set,
4916 "0x%08llx\n");
4917
4918static int
4919i915_max_freq_get(void *data, u64 *val)
4920{
4921 struct drm_device *dev = data;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 int ret;
4924
4925 if (INTEL_INFO(dev)->gen < 6)
4926 return -ENODEV;
4927
4928 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4929
4930 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4931 if (ret)
4932 return ret;
4933
4934 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4935 mutex_unlock(&dev_priv->rps.hw_lock);
4936
4937 return 0;
4938}
4939
4940static int
4941i915_max_freq_set(void *data, u64 val)
4942{
4943 struct drm_device *dev = data;
4944 struct drm_i915_private *dev_priv = dev->dev_private;
4945 u32 hw_max, hw_min;
4946 int ret;
4947
4948 if (INTEL_INFO(dev)->gen < 6)
4949 return -ENODEV;
4950
4951 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4952
4953 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4954
4955 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4956 if (ret)
4957 return ret;
4958
4959 /*
4960 * Turbo will still be enabled, but won't go above the set value.
4961 */
4962 val = intel_freq_opcode(dev_priv, val);
4963
4964 hw_max = dev_priv->rps.max_freq;
4965 hw_min = dev_priv->rps.min_freq;
4966
4967 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4968 mutex_unlock(&dev_priv->rps.hw_lock);
4969 return -EINVAL;
4970 }
4971
4972 dev_priv->rps.max_freq_softlimit = val;
4973
4974 intel_set_rps(dev, val);
4975
4976 mutex_unlock(&dev_priv->rps.hw_lock);
4977
4978 return 0;
4979}
4980
4981DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4982 i915_max_freq_get, i915_max_freq_set,
4983 "%llu\n");
4984
4985static int
4986i915_min_freq_get(void *data, u64 *val)
4987{
4988 struct drm_device *dev = data;
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 int ret;
4991
4992 if (INTEL_INFO(dev)->gen < 6)
4993 return -ENODEV;
4994
4995 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4996
4997 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4998 if (ret)
4999 return ret;
5000
5001 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5002 mutex_unlock(&dev_priv->rps.hw_lock);
5003
5004 return 0;
5005}
5006
5007static int
5008i915_min_freq_set(void *data, u64 val)
5009{
5010 struct drm_device *dev = data;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 u32 hw_max, hw_min;
5013 int ret;
5014
5015 if (INTEL_INFO(dev)->gen < 6)
5016 return -ENODEV;
5017
5018 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5019
5020 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5021
5022 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5023 if (ret)
5024 return ret;
5025
5026 /*
5027 * Turbo will still be enabled, but won't go below the set value.
5028 */
5029 val = intel_freq_opcode(dev_priv, val);
5030
5031 hw_max = dev_priv->rps.max_freq;
5032 hw_min = dev_priv->rps.min_freq;
5033
5034 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5035 mutex_unlock(&dev_priv->rps.hw_lock);
5036 return -EINVAL;
5037 }
5038
5039 dev_priv->rps.min_freq_softlimit = val;
5040
5041 intel_set_rps(dev, val);
5042
5043 mutex_unlock(&dev_priv->rps.hw_lock);
5044
5045 return 0;
5046}
5047
5048DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5049 i915_min_freq_get, i915_min_freq_set,
5050 "%llu\n");
5051
5052static int
5053i915_cache_sharing_get(void *data, u64 *val)
5054{
5055 struct drm_device *dev = data;
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 u32 snpcr;
5058 int ret;
5059
5060 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5061 return -ENODEV;
5062
5063 ret = mutex_lock_interruptible(&dev->struct_mutex);
5064 if (ret)
5065 return ret;
5066 intel_runtime_pm_get(dev_priv);
5067
5068 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5069
5070 intel_runtime_pm_put(dev_priv);
5071 mutex_unlock(&dev_priv->dev->struct_mutex);
5072
5073 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5074
5075 return 0;
5076}
5077
5078static int
5079i915_cache_sharing_set(void *data, u64 val)
5080{
5081 struct drm_device *dev = data;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
5083 u32 snpcr;
5084
5085 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5086 return -ENODEV;
5087
5088 if (val > 3)
5089 return -EINVAL;
5090
5091 intel_runtime_pm_get(dev_priv);
5092 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5093
5094 /* Update the cache sharing policy here as well */
5095 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5096 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5097 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5098 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5099
5100 intel_runtime_pm_put(dev_priv);
5101 return 0;
5102}
5103
5104DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5105 i915_cache_sharing_get, i915_cache_sharing_set,
5106 "%llu\n");
5107
5108struct sseu_dev_status {
5109 unsigned int slice_total;
5110 unsigned int subslice_total;
5111 unsigned int subslice_per_slice;
5112 unsigned int eu_total;
5113 unsigned int eu_per_subslice;
5114};
5115
5116static void cherryview_sseu_device_status(struct drm_device *dev,
5117 struct sseu_dev_status *stat)
5118{
5119 struct drm_i915_private *dev_priv = dev->dev_private;
5120 int ss_max = 2;
5121 int ss;
5122 u32 sig1[ss_max], sig2[ss_max];
5123
5124 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5125 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5126 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5127 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5128
5129 for (ss = 0; ss < ss_max; ss++) {
5130 unsigned int eu_cnt;
5131
5132 if (sig1[ss] & CHV_SS_PG_ENABLE)
5133 /* skip disabled subslice */
5134 continue;
5135
5136 stat->slice_total = 1;
5137 stat->subslice_per_slice++;
5138 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5139 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5140 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5141 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5142 stat->eu_total += eu_cnt;
5143 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5144 }
5145 stat->subslice_total = stat->subslice_per_slice;
5146}
5147
5148static void gen9_sseu_device_status(struct drm_device *dev,
5149 struct sseu_dev_status *stat)
5150{
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 int s_max = 3, ss_max = 4;
5153 int s, ss;
5154 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5155
5156 /* BXT has a single slice and at most 3 subslices. */
5157 if (IS_BROXTON(dev)) {
5158 s_max = 1;
5159 ss_max = 3;
5160 }
5161
5162 for (s = 0; s < s_max; s++) {
5163 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5164 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5165 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5166 }
5167
5168 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5169 GEN9_PGCTL_SSA_EU19_ACK |
5170 GEN9_PGCTL_SSA_EU210_ACK |
5171 GEN9_PGCTL_SSA_EU311_ACK;
5172 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5173 GEN9_PGCTL_SSB_EU19_ACK |
5174 GEN9_PGCTL_SSB_EU210_ACK |
5175 GEN9_PGCTL_SSB_EU311_ACK;
5176
5177 for (s = 0; s < s_max; s++) {
5178 unsigned int ss_cnt = 0;
5179
5180 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5181 /* skip disabled slice */
5182 continue;
5183
5184 stat->slice_total++;
5185
5186 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5187 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5188
5189 for (ss = 0; ss < ss_max; ss++) {
5190 unsigned int eu_cnt;
5191
5192 if (IS_BROXTON(dev) &&
5193 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5194 /* skip disabled subslice */
5195 continue;
5196
5197 if (IS_BROXTON(dev))
5198 ss_cnt++;
5199
5200 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5201 eu_mask[ss%2]);
5202 stat->eu_total += eu_cnt;
5203 stat->eu_per_subslice = max(stat->eu_per_subslice,
5204 eu_cnt);
5205 }
5206
5207 stat->subslice_total += ss_cnt;
5208 stat->subslice_per_slice = max(stat->subslice_per_slice,
5209 ss_cnt);
5210 }
5211}
5212
5213static void broadwell_sseu_device_status(struct drm_device *dev,
5214 struct sseu_dev_status *stat)
5215{
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 int s;
5218 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5219
5220 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5221
5222 if (stat->slice_total) {
5223 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5224 stat->subslice_total = stat->slice_total *
5225 stat->subslice_per_slice;
5226 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5227 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5228
5229 /* subtract fused off EU(s) from enabled slice(s) */
5230 for (s = 0; s < stat->slice_total; s++) {
5231 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5232
5233 stat->eu_total -= hweight8(subslice_7eu);
5234 }
5235 }
5236}
5237
5238static int i915_sseu_status(struct seq_file *m, void *unused)
5239{
5240 struct drm_info_node *node = (struct drm_info_node *) m->private;
5241 struct drm_device *dev = node->minor->dev;
5242 struct sseu_dev_status stat;
5243
5244 if (INTEL_INFO(dev)->gen < 8)
5245 return -ENODEV;
5246
5247 seq_puts(m, "SSEU Device Info\n");
5248 seq_printf(m, " Available Slice Total: %u\n",
5249 INTEL_INFO(dev)->slice_total);
5250 seq_printf(m, " Available Subslice Total: %u\n",
5251 INTEL_INFO(dev)->subslice_total);
5252 seq_printf(m, " Available Subslice Per Slice: %u\n",
5253 INTEL_INFO(dev)->subslice_per_slice);
5254 seq_printf(m, " Available EU Total: %u\n",
5255 INTEL_INFO(dev)->eu_total);
5256 seq_printf(m, " Available EU Per Subslice: %u\n",
5257 INTEL_INFO(dev)->eu_per_subslice);
5258 seq_printf(m, " Has Slice Power Gating: %s\n",
5259 yesno(INTEL_INFO(dev)->has_slice_pg));
5260 seq_printf(m, " Has Subslice Power Gating: %s\n",
5261 yesno(INTEL_INFO(dev)->has_subslice_pg));
5262 seq_printf(m, " Has EU Power Gating: %s\n",
5263 yesno(INTEL_INFO(dev)->has_eu_pg));
5264
5265 seq_puts(m, "SSEU Device Status\n");
5266 memset(&stat, 0, sizeof(stat));
5267 if (IS_CHERRYVIEW(dev)) {
5268 cherryview_sseu_device_status(dev, &stat);
5269 } else if (IS_BROADWELL(dev)) {
5270 broadwell_sseu_device_status(dev, &stat);
5271 } else if (INTEL_INFO(dev)->gen >= 9) {
5272 gen9_sseu_device_status(dev, &stat);
5273 }
5274 seq_printf(m, " Enabled Slice Total: %u\n",
5275 stat.slice_total);
5276 seq_printf(m, " Enabled Subslice Total: %u\n",
5277 stat.subslice_total);
5278 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5279 stat.subslice_per_slice);
5280 seq_printf(m, " Enabled EU Total: %u\n",
5281 stat.eu_total);
5282 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5283 stat.eu_per_subslice);
5284
5285 return 0;
5286}
5287
5288static int i915_forcewake_open(struct inode *inode, struct file *file)
5289{
5290 struct drm_device *dev = inode->i_private;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292
5293 if (INTEL_INFO(dev)->gen < 6)
5294 return 0;
5295
5296 intel_runtime_pm_get(dev_priv);
5297 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5298
5299 return 0;
5300}
5301
5302static int i915_forcewake_release(struct inode *inode, struct file *file)
5303{
5304 struct drm_device *dev = inode->i_private;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306
5307 if (INTEL_INFO(dev)->gen < 6)
5308 return 0;
5309
5310 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5311 intel_runtime_pm_put(dev_priv);
5312
5313 return 0;
5314}
5315
5316static const struct file_operations i915_forcewake_fops = {
5317 .owner = THIS_MODULE,
5318 .open = i915_forcewake_open,
5319 .release = i915_forcewake_release,
5320};
5321
5322static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5323{
5324 struct drm_device *dev = minor->dev;
5325 struct dentry *ent;
5326
5327 ent = debugfs_create_file("i915_forcewake_user",
5328 S_IRUSR,
5329 root, dev,
5330 &i915_forcewake_fops);
5331 if (!ent)
5332 return -ENOMEM;
5333
5334 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5335}
5336
5337static int i915_debugfs_create(struct dentry *root,
5338 struct drm_minor *minor,
5339 const char *name,
5340 const struct file_operations *fops)
5341{
5342 struct drm_device *dev = minor->dev;
5343 struct dentry *ent;
5344
5345 ent = debugfs_create_file(name,
5346 S_IRUGO | S_IWUSR,
5347 root, dev,
5348 fops);
5349 if (!ent)
5350 return -ENOMEM;
5351
5352 return drm_add_fake_info_node(minor, ent, fops);
5353}
5354
5355static const struct drm_info_list i915_debugfs_list[] = {
5356 {"i915_capabilities", i915_capabilities, 0},
5357 {"i915_gem_objects", i915_gem_object_info, 0},
5358 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5359 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5360 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5361 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5362 {"i915_gem_stolen", i915_gem_stolen_list_info },
5363 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5364 {"i915_gem_request", i915_gem_request_info, 0},
5365 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5366 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5367 {"i915_gem_interrupt", i915_interrupt_info, 0},
5368 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5369 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5370 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5371 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5372 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5373 {"i915_guc_info", i915_guc_info, 0},
5374 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5375 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5376 {"i915_frequency_info", i915_frequency_info, 0},
5377 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5378 {"i915_drpc_info", i915_drpc_info, 0},
5379 {"i915_emon_status", i915_emon_status, 0},
5380 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5381 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5382 {"i915_fbc_status", i915_fbc_status, 0},
5383 {"i915_ips_status", i915_ips_status, 0},
5384 {"i915_sr_status", i915_sr_status, 0},
5385 {"i915_opregion", i915_opregion, 0},
5386 {"i915_vbt", i915_vbt, 0},
5387 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5388 {"i915_context_status", i915_context_status, 0},
5389 {"i915_dump_lrc", i915_dump_lrc, 0},
5390 {"i915_execlists", i915_execlists, 0},
5391 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5392 {"i915_swizzle_info", i915_swizzle_info, 0},
5393 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5394 {"i915_llc", i915_llc, 0},
5395 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5396 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5397 {"i915_energy_uJ", i915_energy_uJ, 0},
5398 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5399 {"i915_power_domain_info", i915_power_domain_info, 0},
5400 {"i915_dmc_info", i915_dmc_info, 0},
5401 {"i915_display_info", i915_display_info, 0},
5402 {"i915_semaphore_status", i915_semaphore_status, 0},
5403 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5404 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5405 {"i915_wa_registers", i915_wa_registers, 0},
5406 {"i915_ddb_info", i915_ddb_info, 0},
5407 {"i915_sseu_status", i915_sseu_status, 0},
5408 {"i915_drrs_status", i915_drrs_status, 0},
5409 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5410};
5411#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5412
5413static const struct i915_debugfs_files {
5414 const char *name;
5415 const struct file_operations *fops;
5416} i915_debugfs_files[] = {
5417 {"i915_wedged", &i915_wedged_fops},
5418 {"i915_max_freq", &i915_max_freq_fops},
5419 {"i915_min_freq", &i915_min_freq_fops},
5420 {"i915_cache_sharing", &i915_cache_sharing_fops},
5421 {"i915_ring_stop", &i915_ring_stop_fops},
5422 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5423 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5424 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5425 {"i915_error_state", &i915_error_state_fops},
5426 {"i915_next_seqno", &i915_next_seqno_fops},
5427 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5428 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5429 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5430 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5431 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5432 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5433 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5434 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5435};
5436
5437void intel_display_crc_init(struct drm_device *dev)
5438{
5439 struct drm_i915_private *dev_priv = dev->dev_private;
5440 enum pipe pipe;
5441
5442 for_each_pipe(dev_priv, pipe) {
5443 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5444
5445 pipe_crc->opened = false;
5446 spin_lock_init(&pipe_crc->lock);
5447 init_waitqueue_head(&pipe_crc->wq);
5448 }
5449}
5450
5451int i915_debugfs_init(struct drm_minor *minor)
5452{
5453 int ret, i;
5454
5455 ret = i915_forcewake_create(minor->debugfs_root, minor);
5456 if (ret)
5457 return ret;
5458
5459 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5460 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5461 if (ret)
5462 return ret;
5463 }
5464
5465 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5466 ret = i915_debugfs_create(minor->debugfs_root, minor,
5467 i915_debugfs_files[i].name,
5468 i915_debugfs_files[i].fops);
5469 if (ret)
5470 return ret;
5471 }
5472
5473 return drm_debugfs_create_files(i915_debugfs_list,
5474 I915_DEBUGFS_ENTRIES,
5475 minor->debugfs_root, minor);
5476}
5477
5478void i915_debugfs_cleanup(struct drm_minor *minor)
5479{
5480 int i;
5481
5482 drm_debugfs_remove_files(i915_debugfs_list,
5483 I915_DEBUGFS_ENTRIES, minor);
5484
5485 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5486 1, minor);
5487
5488 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5489 struct drm_info_list *info_list =
5490 (struct drm_info_list *)&i915_pipe_crc_data[i];
5491
5492 drm_debugfs_remove_files(info_list, 1, minor);
5493 }
5494
5495 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5496 struct drm_info_list *info_list =
5497 (struct drm_info_list *) i915_debugfs_files[i].fops;
5498
5499 drm_debugfs_remove_files(info_list, 1, minor);
5500 }
5501}
5502
5503struct dpcd_block {
5504 /* DPCD dump start address. */
5505 unsigned int offset;
5506 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5507 unsigned int end;
5508 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5509 size_t size;
5510 /* Only valid for eDP. */
5511 bool edp;
5512};
5513
5514static const struct dpcd_block i915_dpcd_debug[] = {
5515 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5516 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5517 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5518 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5519 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5520 { .offset = DP_SET_POWER },
5521 { .offset = DP_EDP_DPCD_REV },
5522 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5523 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5524 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5525};
5526
5527static int i915_dpcd_show(struct seq_file *m, void *data)
5528{
5529 struct drm_connector *connector = m->private;
5530 struct intel_dp *intel_dp =
5531 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5532 uint8_t buf[16];
5533 ssize_t err;
5534 int i;
5535
5536 if (connector->status != connector_status_connected)
5537 return -ENODEV;
5538
5539 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5540 const struct dpcd_block *b = &i915_dpcd_debug[i];
5541 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5542
5543 if (b->edp &&
5544 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5545 continue;
5546
5547 /* low tech for now */
5548 if (WARN_ON(size > sizeof(buf)))
5549 continue;
5550
5551 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5552 if (err <= 0) {
5553 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5554 size, b->offset, err);
5555 continue;
5556 }
5557
5558 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5559 }
5560
5561 return 0;
5562}
5563
5564static int i915_dpcd_open(struct inode *inode, struct file *file)
5565{
5566 return single_open(file, i915_dpcd_show, inode->i_private);
5567}
5568
5569static const struct file_operations i915_dpcd_fops = {
5570 .owner = THIS_MODULE,
5571 .open = i915_dpcd_open,
5572 .read = seq_read,
5573 .llseek = seq_lseek,
5574 .release = single_release,
5575};
5576
5577/**
5578 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5579 * @connector: pointer to a registered drm_connector
5580 *
5581 * Cleanup will be done by drm_connector_unregister() through a call to
5582 * drm_debugfs_connector_remove().
5583 *
5584 * Returns 0 on success, negative error codes on error.
5585 */
5586int i915_debugfs_connector_add(struct drm_connector *connector)
5587{
5588 struct dentry *root = connector->debugfs_entry;
5589
5590 /* The connector must have been registered beforehands. */
5591 if (!root)
5592 return -ENODEV;
5593
5594 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5595 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5596 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5597 &i915_dpcd_fops);
5598
5599 return 0;
5600}
Linux kernel - Deliverables
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