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drm/i915/guc: Disable automatic GuC firmware loading
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/circ_buf.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/slab.h>
34#include <linux/export.h>
35#include <linux/list_sort.h>
36#include <asm/msr-index.h>
37#include <drm/drmP.h>
38#include "intel_drv.h"
39#include "intel_ringbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47};
48
49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
75static int i915_capabilities(struct seq_file *m, void *data)
76{
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
88
89 return 0;
90}
91
92static char get_active_flag(struct drm_i915_gem_object *obj)
93{
94 return obj->active ? '*' : ' ';
95}
96
97static char get_pin_flag(struct drm_i915_gem_object *obj)
98{
99 return obj->pin_display ? 'p' : ' ';
100}
101
102static char get_tiling_flag(struct drm_i915_gem_object *obj)
103{
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
109 }
110}
111
112static char get_global_flag(struct drm_i915_gem_object *obj)
113{
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115}
116
117static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->mapping ? 'M' : ' ';
120}
121
122static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123{
124 u64 size = 0;
125 struct i915_vma *vma;
126
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
130 }
131
132 return size;
133}
134
135static void
136describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137{
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
141 int pin_count = 0;
142 enum intel_engine_id id;
143
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
147 &obj->base,
148 get_active_flag(obj),
149 get_pin_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
157 seq_printf(m, "%x ",
158 i915_gem_request_get_seqno(obj->last_read_req[id]));
159 seq_printf(m, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj->last_write_req),
161 i915_gem_request_get_seqno(obj->last_fenced_req),
162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (vma->pin_count > 0)
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
177 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
178 vma->is_ggtt ? "g" : "pp",
179 vma->node.start, vma->node.size);
180 if (vma->is_ggtt)
181 seq_printf(m, ", type: %u", vma->ggtt_view.type);
182 seq_puts(m, ")");
183 }
184 if (obj->stolen)
185 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
186 if (obj->pin_display || obj->fault_mappable) {
187 char s[3], *t = s;
188 if (obj->pin_display)
189 *t++ = 'p';
190 if (obj->fault_mappable)
191 *t++ = 'f';
192 *t = '\0';
193 seq_printf(m, " (%s mappable)", s);
194 }
195 if (obj->last_write_req != NULL)
196 seq_printf(m, " (%s)",
197 i915_gem_request_get_engine(obj->last_write_req)->name);
198 if (obj->frontbuffer_bits)
199 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
200}
201
202static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
203{
204 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
205 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
206 seq_putc(m, ' ');
207}
208
209static int i915_gem_object_list_info(struct seq_file *m, void *data)
210{
211 struct drm_info_node *node = m->private;
212 uintptr_t list = (uintptr_t) node->info_ent->data;
213 struct list_head *head;
214 struct drm_device *dev = node->minor->dev;
215 struct drm_i915_private *dev_priv = to_i915(dev);
216 struct i915_ggtt *ggtt = &dev_priv->ggtt;
217 struct i915_vma *vma;
218 u64 total_obj_size, total_gtt_size;
219 int count, ret;
220
221 ret = mutex_lock_interruptible(&dev->struct_mutex);
222 if (ret)
223 return ret;
224
225 /* FIXME: the user of this interface might want more than just GGTT */
226 switch (list) {
227 case ACTIVE_LIST:
228 seq_puts(m, "Active:\n");
229 head = &ggtt->base.active_list;
230 break;
231 case INACTIVE_LIST:
232 seq_puts(m, "Inactive:\n");
233 head = &ggtt->base.inactive_list;
234 break;
235 default:
236 mutex_unlock(&dev->struct_mutex);
237 return -EINVAL;
238 }
239
240 total_obj_size = total_gtt_size = count = 0;
241 list_for_each_entry(vma, head, vm_link) {
242 seq_printf(m, " ");
243 describe_obj(m, vma->obj);
244 seq_printf(m, "\n");
245 total_obj_size += vma->obj->base.size;
246 total_gtt_size += vma->node.size;
247 count++;
248 }
249 mutex_unlock(&dev->struct_mutex);
250
251 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
252 count, total_obj_size, total_gtt_size);
253 return 0;
254}
255
256static int obj_rank_by_stolen(void *priv,
257 struct list_head *A, struct list_head *B)
258{
259 struct drm_i915_gem_object *a =
260 container_of(A, struct drm_i915_gem_object, obj_exec_link);
261 struct drm_i915_gem_object *b =
262 container_of(B, struct drm_i915_gem_object, obj_exec_link);
263
264 if (a->stolen->start < b->stolen->start)
265 return -1;
266 if (a->stolen->start > b->stolen->start)
267 return 1;
268 return 0;
269}
270
271static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
272{
273 struct drm_info_node *node = m->private;
274 struct drm_device *dev = node->minor->dev;
275 struct drm_i915_private *dev_priv = dev->dev_private;
276 struct drm_i915_gem_object *obj;
277 u64 total_obj_size, total_gtt_size;
278 LIST_HEAD(stolen);
279 int count, ret;
280
281 ret = mutex_lock_interruptible(&dev->struct_mutex);
282 if (ret)
283 return ret;
284
285 total_obj_size = total_gtt_size = count = 0;
286 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
287 if (obj->stolen == NULL)
288 continue;
289
290 list_add(&obj->obj_exec_link, &stolen);
291
292 total_obj_size += obj->base.size;
293 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
294 count++;
295 }
296 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
297 if (obj->stolen == NULL)
298 continue;
299
300 list_add(&obj->obj_exec_link, &stolen);
301
302 total_obj_size += obj->base.size;
303 count++;
304 }
305 list_sort(NULL, &stolen, obj_rank_by_stolen);
306 seq_puts(m, "Stolen:\n");
307 while (!list_empty(&stolen)) {
308 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
309 seq_puts(m, " ");
310 describe_obj(m, obj);
311 seq_putc(m, '\n');
312 list_del_init(&obj->obj_exec_link);
313 }
314 mutex_unlock(&dev->struct_mutex);
315
316 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
317 count, total_obj_size, total_gtt_size);
318 return 0;
319}
320
321#define count_objects(list, member) do { \
322 list_for_each_entry(obj, list, member) { \
323 size += i915_gem_obj_total_ggtt_size(obj); \
324 ++count; \
325 if (obj->map_and_fenceable) { \
326 mappable_size += i915_gem_obj_ggtt_size(obj); \
327 ++mappable_count; \
328 } \
329 } \
330} while (0)
331
332struct file_stats {
333 struct drm_i915_file_private *file_priv;
334 unsigned long count;
335 u64 total, unbound;
336 u64 global, shared;
337 u64 active, inactive;
338};
339
340static int per_file_stats(int id, void *ptr, void *data)
341{
342 struct drm_i915_gem_object *obj = ptr;
343 struct file_stats *stats = data;
344 struct i915_vma *vma;
345
346 stats->count++;
347 stats->total += obj->base.size;
348
349 if (obj->base.name || obj->base.dma_buf)
350 stats->shared += obj->base.size;
351
352 if (USES_FULL_PPGTT(obj->base.dev)) {
353 list_for_each_entry(vma, &obj->vma_list, obj_link) {
354 struct i915_hw_ppgtt *ppgtt;
355
356 if (!drm_mm_node_allocated(&vma->node))
357 continue;
358
359 if (vma->is_ggtt) {
360 stats->global += obj->base.size;
361 continue;
362 }
363
364 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
365 if (ppgtt->file_priv != stats->file_priv)
366 continue;
367
368 if (obj->active) /* XXX per-vma statistic */
369 stats->active += obj->base.size;
370 else
371 stats->inactive += obj->base.size;
372
373 return 0;
374 }
375 } else {
376 if (i915_gem_obj_ggtt_bound(obj)) {
377 stats->global += obj->base.size;
378 if (obj->active)
379 stats->active += obj->base.size;
380 else
381 stats->inactive += obj->base.size;
382 return 0;
383 }
384 }
385
386 if (!list_empty(&obj->global_list))
387 stats->unbound += obj->base.size;
388
389 return 0;
390}
391
392#define print_file_stats(m, name, stats) do { \
393 if (stats.count) \
394 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
395 name, \
396 stats.count, \
397 stats.total, \
398 stats.active, \
399 stats.inactive, \
400 stats.global, \
401 stats.shared, \
402 stats.unbound); \
403} while (0)
404
405static void print_batch_pool_stats(struct seq_file *m,
406 struct drm_i915_private *dev_priv)
407{
408 struct drm_i915_gem_object *obj;
409 struct file_stats stats;
410 struct intel_engine_cs *engine;
411 int j;
412
413 memset(&stats, 0, sizeof(stats));
414
415 for_each_engine(engine, dev_priv) {
416 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
417 list_for_each_entry(obj,
418 &engine->batch_pool.cache_list[j],
419 batch_pool_link)
420 per_file_stats(0, obj, &stats);
421 }
422 }
423
424 print_file_stats(m, "[k]batch pool", stats);
425}
426
427#define count_vmas(list, member) do { \
428 list_for_each_entry(vma, list, member) { \
429 size += i915_gem_obj_total_ggtt_size(vma->obj); \
430 ++count; \
431 if (vma->obj->map_and_fenceable) { \
432 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
433 ++mappable_count; \
434 } \
435 } \
436} while (0)
437
438static int i915_gem_object_info(struct seq_file *m, void* data)
439{
440 struct drm_info_node *node = m->private;
441 struct drm_device *dev = node->minor->dev;
442 struct drm_i915_private *dev_priv = to_i915(dev);
443 struct i915_ggtt *ggtt = &dev_priv->ggtt;
444 u32 count, mappable_count, purgeable_count;
445 u64 size, mappable_size, purgeable_size;
446 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
447 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
448 struct drm_i915_gem_object *obj;
449 struct drm_file *file;
450 struct i915_vma *vma;
451 int ret;
452
453 ret = mutex_lock_interruptible(&dev->struct_mutex);
454 if (ret)
455 return ret;
456
457 seq_printf(m, "%u objects, %zu bytes\n",
458 dev_priv->mm.object_count,
459 dev_priv->mm.object_memory);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_objects(&dev_priv->mm.bound_list, global_list);
463 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = mappable_size = mappable_count = 0;
467 count_vmas(&ggtt->base.active_list, vm_link);
468 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
469 count, mappable_count, size, mappable_size);
470
471 size = count = mappable_size = mappable_count = 0;
472 count_vmas(&ggtt->base.inactive_list, vm_link);
473 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
474 count, mappable_count, size, mappable_size);
475
476 size = count = purgeable_size = purgeable_count = 0;
477 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
478 size += obj->base.size, ++count;
479 if (obj->madv == I915_MADV_DONTNEED)
480 purgeable_size += obj->base.size, ++purgeable_count;
481 if (obj->mapping) {
482 pin_mapped_count++;
483 pin_mapped_size += obj->base.size;
484 if (obj->pages_pin_count == 0) {
485 pin_mapped_purgeable_count++;
486 pin_mapped_purgeable_size += obj->base.size;
487 }
488 }
489 }
490 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
491
492 size = count = mappable_size = mappable_count = 0;
493 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
494 if (obj->fault_mappable) {
495 size += i915_gem_obj_ggtt_size(obj);
496 ++count;
497 }
498 if (obj->pin_display) {
499 mappable_size += i915_gem_obj_ggtt_size(obj);
500 ++mappable_count;
501 }
502 if (obj->madv == I915_MADV_DONTNEED) {
503 purgeable_size += obj->base.size;
504 ++purgeable_count;
505 }
506 if (obj->mapping) {
507 pin_mapped_count++;
508 pin_mapped_size += obj->base.size;
509 if (obj->pages_pin_count == 0) {
510 pin_mapped_purgeable_count++;
511 pin_mapped_purgeable_size += obj->base.size;
512 }
513 }
514 }
515 seq_printf(m, "%u purgeable objects, %llu bytes\n",
516 purgeable_count, purgeable_size);
517 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
518 mappable_count, mappable_size);
519 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
520 count, size);
521 seq_printf(m,
522 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
523 pin_mapped_count, pin_mapped_purgeable_count,
524 pin_mapped_size, pin_mapped_purgeable_size);
525
526 seq_printf(m, "%llu [%llu] gtt total\n",
527 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
528
529 seq_putc(m, '\n');
530 print_batch_pool_stats(m, dev_priv);
531
532 mutex_unlock(&dev->struct_mutex);
533
534 mutex_lock(&dev->filelist_mutex);
535 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
536 struct file_stats stats;
537 struct task_struct *task;
538
539 memset(&stats, 0, sizeof(stats));
540 stats.file_priv = file->driver_priv;
541 spin_lock(&file->table_lock);
542 idr_for_each(&file->object_idr, per_file_stats, &stats);
543 spin_unlock(&file->table_lock);
544 /*
545 * Although we have a valid reference on file->pid, that does
546 * not guarantee that the task_struct who called get_pid() is
547 * still alive (e.g. get_pid(current) => fork() => exit()).
548 * Therefore, we need to protect this ->comm access using RCU.
549 */
550 rcu_read_lock();
551 task = pid_task(file->pid, PIDTYPE_PID);
552 print_file_stats(m, task ? task->comm : "<unknown>", stats);
553 rcu_read_unlock();
554 }
555 mutex_unlock(&dev->filelist_mutex);
556
557 return 0;
558}
559
560static int i915_gem_gtt_info(struct seq_file *m, void *data)
561{
562 struct drm_info_node *node = m->private;
563 struct drm_device *dev = node->minor->dev;
564 uintptr_t list = (uintptr_t) node->info_ent->data;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 struct drm_i915_gem_object *obj;
567 u64 total_obj_size, total_gtt_size;
568 int count, ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
573
574 total_obj_size = total_gtt_size = count = 0;
575 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
576 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
577 continue;
578
579 seq_puts(m, " ");
580 describe_obj(m, obj);
581 seq_putc(m, '\n');
582 total_obj_size += obj->base.size;
583 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
584 count++;
585 }
586
587 mutex_unlock(&dev->struct_mutex);
588
589 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
590 count, total_obj_size, total_gtt_size);
591
592 return 0;
593}
594
595static void i915_dump_pageflip(struct seq_file *m,
596 struct drm_i915_private *dev_priv,
597 struct intel_crtc *crtc,
598 struct intel_flip_work *work)
599{
600 const char pipe = pipe_name(crtc->pipe);
601 u32 pending;
602 int i;
603
604 pending = atomic_read(&work->pending);
605 if (pending) {
606 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
607 pipe, plane_name(crtc->plane));
608 } else {
609 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
610 pipe, plane_name(crtc->plane));
611 }
612
613 for (i = 0; i < work->num_planes; i++) {
614 struct intel_plane_state *old_plane_state = work->old_plane_state[i];
615 struct drm_plane *plane = old_plane_state->base.plane;
616 struct drm_i915_gem_request *req = old_plane_state->wait_req;
617 struct intel_engine_cs *engine;
618
619 seq_printf(m, "[PLANE:%i] part of flip.\n", plane->base.id);
620
621 if (!req) {
622 seq_printf(m, "Plane not associated with any engine\n");
623 continue;
624 }
625
626 engine = i915_gem_request_get_engine(req);
627
628 seq_printf(m, "Plane blocked on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
629 engine->name,
630 i915_gem_request_get_seqno(req),
631 dev_priv->next_seqno,
632 engine->get_seqno(engine),
633 i915_gem_request_completed(req, true));
634 }
635
636 seq_printf(m, "Flip queued on frame %d, now %d\n",
637 pending ? work->flip_queued_vblank : -1,
638 intel_crtc_get_vblank_counter(crtc));
639}
640
641static int i915_gem_pageflip_info(struct seq_file *m, void *data)
642{
643 struct drm_info_node *node = m->private;
644 struct drm_device *dev = node->minor->dev;
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 struct intel_crtc *crtc;
647 int ret;
648
649 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 if (ret)
651 return ret;
652
653 for_each_intel_crtc(dev, crtc) {
654 const char pipe = pipe_name(crtc->pipe);
655 const char plane = plane_name(crtc->plane);
656 struct intel_flip_work *work;
657
658 spin_lock_irq(&dev->event_lock);
659 if (list_empty(&crtc->flip_work)) {
660 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
661 pipe, plane);
662 } else {
663 list_for_each_entry(work, &crtc->flip_work, head) {
664 i915_dump_pageflip(m, dev_priv, crtc, work);
665 seq_puts(m, "\n");
666 }
667 }
668 spin_unlock_irq(&dev->event_lock);
669 }
670
671 mutex_unlock(&dev->struct_mutex);
672
673 return 0;
674}
675
676static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
677{
678 struct drm_info_node *node = m->private;
679 struct drm_device *dev = node->minor->dev;
680 struct drm_i915_private *dev_priv = dev->dev_private;
681 struct drm_i915_gem_object *obj;
682 struct intel_engine_cs *engine;
683 int total = 0;
684 int ret, j;
685
686 ret = mutex_lock_interruptible(&dev->struct_mutex);
687 if (ret)
688 return ret;
689
690 for_each_engine(engine, dev_priv) {
691 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
692 int count;
693
694 count = 0;
695 list_for_each_entry(obj,
696 &engine->batch_pool.cache_list[j],
697 batch_pool_link)
698 count++;
699 seq_printf(m, "%s cache[%d]: %d objects\n",
700 engine->name, j, count);
701
702 list_for_each_entry(obj,
703 &engine->batch_pool.cache_list[j],
704 batch_pool_link) {
705 seq_puts(m, " ");
706 describe_obj(m, obj);
707 seq_putc(m, '\n');
708 }
709
710 total += count;
711 }
712 }
713
714 seq_printf(m, "total: %d\n", total);
715
716 mutex_unlock(&dev->struct_mutex);
717
718 return 0;
719}
720
721static int i915_gem_request_info(struct seq_file *m, void *data)
722{
723 struct drm_info_node *node = m->private;
724 struct drm_device *dev = node->minor->dev;
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 struct intel_engine_cs *engine;
727 struct drm_i915_gem_request *req;
728 int ret, any;
729
730 ret = mutex_lock_interruptible(&dev->struct_mutex);
731 if (ret)
732 return ret;
733
734 any = 0;
735 for_each_engine(engine, dev_priv) {
736 int count;
737
738 count = 0;
739 list_for_each_entry(req, &engine->request_list, list)
740 count++;
741 if (count == 0)
742 continue;
743
744 seq_printf(m, "%s requests: %d\n", engine->name, count);
745 list_for_each_entry(req, &engine->request_list, list) {
746 struct task_struct *task;
747
748 rcu_read_lock();
749 task = NULL;
750 if (req->pid)
751 task = pid_task(req->pid, PIDTYPE_PID);
752 seq_printf(m, " %x @ %d: %s [%d]\n",
753 req->seqno,
754 (int) (jiffies - req->emitted_jiffies),
755 task ? task->comm : "<unknown>",
756 task ? task->pid : -1);
757 rcu_read_unlock();
758 }
759
760 any++;
761 }
762 mutex_unlock(&dev->struct_mutex);
763
764 if (any == 0)
765 seq_puts(m, "No requests\n");
766
767 return 0;
768}
769
770static void i915_ring_seqno_info(struct seq_file *m,
771 struct intel_engine_cs *engine)
772{
773 seq_printf(m, "Current sequence (%s): %x\n",
774 engine->name, engine->get_seqno(engine));
775 seq_printf(m, "Current user interrupts (%s): %x\n",
776 engine->name, READ_ONCE(engine->user_interrupts));
777}
778
779static int i915_gem_seqno_info(struct seq_file *m, void *data)
780{
781 struct drm_info_node *node = m->private;
782 struct drm_device *dev = node->minor->dev;
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 struct intel_engine_cs *engine;
785 int ret;
786
787 ret = mutex_lock_interruptible(&dev->struct_mutex);
788 if (ret)
789 return ret;
790 intel_runtime_pm_get(dev_priv);
791
792 for_each_engine(engine, dev_priv)
793 i915_ring_seqno_info(m, engine);
794
795 intel_runtime_pm_put(dev_priv);
796 mutex_unlock(&dev->struct_mutex);
797
798 return 0;
799}
800
801
802static int i915_interrupt_info(struct seq_file *m, void *data)
803{
804 struct drm_info_node *node = m->private;
805 struct drm_device *dev = node->minor->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 struct intel_engine_cs *engine;
808 int ret, i, pipe;
809
810 ret = mutex_lock_interruptible(&dev->struct_mutex);
811 if (ret)
812 return ret;
813 intel_runtime_pm_get(dev_priv);
814
815 if (IS_CHERRYVIEW(dev)) {
816 seq_printf(m, "Master Interrupt Control:\t%08x\n",
817 I915_READ(GEN8_MASTER_IRQ));
818
819 seq_printf(m, "Display IER:\t%08x\n",
820 I915_READ(VLV_IER));
821 seq_printf(m, "Display IIR:\t%08x\n",
822 I915_READ(VLV_IIR));
823 seq_printf(m, "Display IIR_RW:\t%08x\n",
824 I915_READ(VLV_IIR_RW));
825 seq_printf(m, "Display IMR:\t%08x\n",
826 I915_READ(VLV_IMR));
827 for_each_pipe(dev_priv, pipe)
828 seq_printf(m, "Pipe %c stat:\t%08x\n",
829 pipe_name(pipe),
830 I915_READ(PIPESTAT(pipe)));
831
832 seq_printf(m, "Port hotplug:\t%08x\n",
833 I915_READ(PORT_HOTPLUG_EN));
834 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
835 I915_READ(VLV_DPFLIPSTAT));
836 seq_printf(m, "DPINVGTT:\t%08x\n",
837 I915_READ(DPINVGTT));
838
839 for (i = 0; i < 4; i++) {
840 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
841 i, I915_READ(GEN8_GT_IMR(i)));
842 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
843 i, I915_READ(GEN8_GT_IIR(i)));
844 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
845 i, I915_READ(GEN8_GT_IER(i)));
846 }
847
848 seq_printf(m, "PCU interrupt mask:\t%08x\n",
849 I915_READ(GEN8_PCU_IMR));
850 seq_printf(m, "PCU interrupt identity:\t%08x\n",
851 I915_READ(GEN8_PCU_IIR));
852 seq_printf(m, "PCU interrupt enable:\t%08x\n",
853 I915_READ(GEN8_PCU_IER));
854 } else if (INTEL_INFO(dev)->gen >= 8) {
855 seq_printf(m, "Master Interrupt Control:\t%08x\n",
856 I915_READ(GEN8_MASTER_IRQ));
857
858 for (i = 0; i < 4; i++) {
859 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
860 i, I915_READ(GEN8_GT_IMR(i)));
861 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
862 i, I915_READ(GEN8_GT_IIR(i)));
863 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
864 i, I915_READ(GEN8_GT_IER(i)));
865 }
866
867 for_each_pipe(dev_priv, pipe) {
868 enum intel_display_power_domain power_domain;
869
870 power_domain = POWER_DOMAIN_PIPE(pipe);
871 if (!intel_display_power_get_if_enabled(dev_priv,
872 power_domain)) {
873 seq_printf(m, "Pipe %c power disabled\n",
874 pipe_name(pipe));
875 continue;
876 }
877 seq_printf(m, "Pipe %c IMR:\t%08x\n",
878 pipe_name(pipe),
879 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
880 seq_printf(m, "Pipe %c IIR:\t%08x\n",
881 pipe_name(pipe),
882 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
883 seq_printf(m, "Pipe %c IER:\t%08x\n",
884 pipe_name(pipe),
885 I915_READ(GEN8_DE_PIPE_IER(pipe)));
886
887 intel_display_power_put(dev_priv, power_domain);
888 }
889
890 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
891 I915_READ(GEN8_DE_PORT_IMR));
892 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
893 I915_READ(GEN8_DE_PORT_IIR));
894 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
895 I915_READ(GEN8_DE_PORT_IER));
896
897 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
898 I915_READ(GEN8_DE_MISC_IMR));
899 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
900 I915_READ(GEN8_DE_MISC_IIR));
901 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
902 I915_READ(GEN8_DE_MISC_IER));
903
904 seq_printf(m, "PCU interrupt mask:\t%08x\n",
905 I915_READ(GEN8_PCU_IMR));
906 seq_printf(m, "PCU interrupt identity:\t%08x\n",
907 I915_READ(GEN8_PCU_IIR));
908 seq_printf(m, "PCU interrupt enable:\t%08x\n",
909 I915_READ(GEN8_PCU_IER));
910 } else if (IS_VALLEYVIEW(dev)) {
911 seq_printf(m, "Display IER:\t%08x\n",
912 I915_READ(VLV_IER));
913 seq_printf(m, "Display IIR:\t%08x\n",
914 I915_READ(VLV_IIR));
915 seq_printf(m, "Display IIR_RW:\t%08x\n",
916 I915_READ(VLV_IIR_RW));
917 seq_printf(m, "Display IMR:\t%08x\n",
918 I915_READ(VLV_IMR));
919 for_each_pipe(dev_priv, pipe)
920 seq_printf(m, "Pipe %c stat:\t%08x\n",
921 pipe_name(pipe),
922 I915_READ(PIPESTAT(pipe)));
923
924 seq_printf(m, "Master IER:\t%08x\n",
925 I915_READ(VLV_MASTER_IER));
926
927 seq_printf(m, "Render IER:\t%08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Render IIR:\t%08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Render IMR:\t%08x\n",
932 I915_READ(GTIMR));
933
934 seq_printf(m, "PM IER:\t\t%08x\n",
935 I915_READ(GEN6_PMIER));
936 seq_printf(m, "PM IIR:\t\t%08x\n",
937 I915_READ(GEN6_PMIIR));
938 seq_printf(m, "PM IMR:\t\t%08x\n",
939 I915_READ(GEN6_PMIMR));
940
941 seq_printf(m, "Port hotplug:\t%08x\n",
942 I915_READ(PORT_HOTPLUG_EN));
943 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
944 I915_READ(VLV_DPFLIPSTAT));
945 seq_printf(m, "DPINVGTT:\t%08x\n",
946 I915_READ(DPINVGTT));
947
948 } else if (!HAS_PCH_SPLIT(dev)) {
949 seq_printf(m, "Interrupt enable: %08x\n",
950 I915_READ(IER));
951 seq_printf(m, "Interrupt identity: %08x\n",
952 I915_READ(IIR));
953 seq_printf(m, "Interrupt mask: %08x\n",
954 I915_READ(IMR));
955 for_each_pipe(dev_priv, pipe)
956 seq_printf(m, "Pipe %c stat: %08x\n",
957 pipe_name(pipe),
958 I915_READ(PIPESTAT(pipe)));
959 } else {
960 seq_printf(m, "North Display Interrupt enable: %08x\n",
961 I915_READ(DEIER));
962 seq_printf(m, "North Display Interrupt identity: %08x\n",
963 I915_READ(DEIIR));
964 seq_printf(m, "North Display Interrupt mask: %08x\n",
965 I915_READ(DEIMR));
966 seq_printf(m, "South Display Interrupt enable: %08x\n",
967 I915_READ(SDEIER));
968 seq_printf(m, "South Display Interrupt identity: %08x\n",
969 I915_READ(SDEIIR));
970 seq_printf(m, "South Display Interrupt mask: %08x\n",
971 I915_READ(SDEIMR));
972 seq_printf(m, "Graphics Interrupt enable: %08x\n",
973 I915_READ(GTIER));
974 seq_printf(m, "Graphics Interrupt identity: %08x\n",
975 I915_READ(GTIIR));
976 seq_printf(m, "Graphics Interrupt mask: %08x\n",
977 I915_READ(GTIMR));
978 }
979 for_each_engine(engine, dev_priv) {
980 if (INTEL_INFO(dev)->gen >= 6) {
981 seq_printf(m,
982 "Graphics Interrupt mask (%s): %08x\n",
983 engine->name, I915_READ_IMR(engine));
984 }
985 i915_ring_seqno_info(m, engine);
986 }
987 intel_runtime_pm_put(dev_priv);
988 mutex_unlock(&dev->struct_mutex);
989
990 return 0;
991}
992
993static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
994{
995 struct drm_info_node *node = m->private;
996 struct drm_device *dev = node->minor->dev;
997 struct drm_i915_private *dev_priv = dev->dev_private;
998 int i, ret;
999
1000 ret = mutex_lock_interruptible(&dev->struct_mutex);
1001 if (ret)
1002 return ret;
1003
1004 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1005 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1006 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1007
1008 seq_printf(m, "Fence %d, pin count = %d, object = ",
1009 i, dev_priv->fence_regs[i].pin_count);
1010 if (obj == NULL)
1011 seq_puts(m, "unused");
1012 else
1013 describe_obj(m, obj);
1014 seq_putc(m, '\n');
1015 }
1016
1017 mutex_unlock(&dev->struct_mutex);
1018 return 0;
1019}
1020
1021static int i915_hws_info(struct seq_file *m, void *data)
1022{
1023 struct drm_info_node *node = m->private;
1024 struct drm_device *dev = node->minor->dev;
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1026 struct intel_engine_cs *engine;
1027 const u32 *hws;
1028 int i;
1029
1030 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1031 hws = engine->status_page.page_addr;
1032 if (hws == NULL)
1033 return 0;
1034
1035 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1036 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1037 i * 4,
1038 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1039 }
1040 return 0;
1041}
1042
1043static ssize_t
1044i915_error_state_write(struct file *filp,
1045 const char __user *ubuf,
1046 size_t cnt,
1047 loff_t *ppos)
1048{
1049 struct i915_error_state_file_priv *error_priv = filp->private_data;
1050 struct drm_device *dev = error_priv->dev;
1051 int ret;
1052
1053 DRM_DEBUG_DRIVER("Resetting error state\n");
1054
1055 ret = mutex_lock_interruptible(&dev->struct_mutex);
1056 if (ret)
1057 return ret;
1058
1059 i915_destroy_error_state(dev);
1060 mutex_unlock(&dev->struct_mutex);
1061
1062 return cnt;
1063}
1064
1065static int i915_error_state_open(struct inode *inode, struct file *file)
1066{
1067 struct drm_device *dev = inode->i_private;
1068 struct i915_error_state_file_priv *error_priv;
1069
1070 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1071 if (!error_priv)
1072 return -ENOMEM;
1073
1074 error_priv->dev = dev;
1075
1076 i915_error_state_get(dev, error_priv);
1077
1078 file->private_data = error_priv;
1079
1080 return 0;
1081}
1082
1083static int i915_error_state_release(struct inode *inode, struct file *file)
1084{
1085 struct i915_error_state_file_priv *error_priv = file->private_data;
1086
1087 i915_error_state_put(error_priv);
1088 kfree(error_priv);
1089
1090 return 0;
1091}
1092
1093static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1094 size_t count, loff_t *pos)
1095{
1096 struct i915_error_state_file_priv *error_priv = file->private_data;
1097 struct drm_i915_error_state_buf error_str;
1098 loff_t tmp_pos = 0;
1099 ssize_t ret_count = 0;
1100 int ret;
1101
1102 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1103 if (ret)
1104 return ret;
1105
1106 ret = i915_error_state_to_str(&error_str, error_priv);
1107 if (ret)
1108 goto out;
1109
1110 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1111 error_str.buf,
1112 error_str.bytes);
1113
1114 if (ret_count < 0)
1115 ret = ret_count;
1116 else
1117 *pos = error_str.start + ret_count;
1118out:
1119 i915_error_state_buf_release(&error_str);
1120 return ret ?: ret_count;
1121}
1122
1123static const struct file_operations i915_error_state_fops = {
1124 .owner = THIS_MODULE,
1125 .open = i915_error_state_open,
1126 .read = i915_error_state_read,
1127 .write = i915_error_state_write,
1128 .llseek = default_llseek,
1129 .release = i915_error_state_release,
1130};
1131
1132static int
1133i915_next_seqno_get(void *data, u64 *val)
1134{
1135 struct drm_device *dev = data;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 int ret;
1138
1139 ret = mutex_lock_interruptible(&dev->struct_mutex);
1140 if (ret)
1141 return ret;
1142
1143 *val = dev_priv->next_seqno;
1144 mutex_unlock(&dev->struct_mutex);
1145
1146 return 0;
1147}
1148
1149static int
1150i915_next_seqno_set(void *data, u64 val)
1151{
1152 struct drm_device *dev = data;
1153 int ret;
1154
1155 ret = mutex_lock_interruptible(&dev->struct_mutex);
1156 if (ret)
1157 return ret;
1158
1159 ret = i915_gem_set_seqno(dev, val);
1160 mutex_unlock(&dev->struct_mutex);
1161
1162 return ret;
1163}
1164
1165DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1166 i915_next_seqno_get, i915_next_seqno_set,
1167 "0x%llx\n");
1168
1169static int i915_frequency_info(struct seq_file *m, void *unused)
1170{
1171 struct drm_info_node *node = m->private;
1172 struct drm_device *dev = node->minor->dev;
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 int ret = 0;
1175
1176 intel_runtime_pm_get(dev_priv);
1177
1178 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1179
1180 if (IS_GEN5(dev)) {
1181 u16 rgvswctl = I915_READ16(MEMSWCTL);
1182 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1183
1184 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1185 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1186 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1187 MEMSTAT_VID_SHIFT);
1188 seq_printf(m, "Current P-state: %d\n",
1189 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1190 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1191 u32 freq_sts;
1192
1193 mutex_lock(&dev_priv->rps.hw_lock);
1194 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1195 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1196 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1197
1198 seq_printf(m, "actual GPU freq: %d MHz\n",
1199 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1200
1201 seq_printf(m, "current GPU freq: %d MHz\n",
1202 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1203
1204 seq_printf(m, "max GPU freq: %d MHz\n",
1205 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1206
1207 seq_printf(m, "min GPU freq: %d MHz\n",
1208 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1209
1210 seq_printf(m, "idle GPU freq: %d MHz\n",
1211 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1212
1213 seq_printf(m,
1214 "efficient (RPe) frequency: %d MHz\n",
1215 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1216 mutex_unlock(&dev_priv->rps.hw_lock);
1217 } else if (INTEL_INFO(dev)->gen >= 6) {
1218 u32 rp_state_limits;
1219 u32 gt_perf_status;
1220 u32 rp_state_cap;
1221 u32 rpmodectl, rpinclimit, rpdeclimit;
1222 u32 rpstat, cagf, reqf;
1223 u32 rpupei, rpcurup, rpprevup;
1224 u32 rpdownei, rpcurdown, rpprevdown;
1225 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1226 int max_freq;
1227
1228 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1229 if (IS_BROXTON(dev)) {
1230 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1231 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1232 } else {
1233 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1234 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1235 }
1236
1237 /* RPSTAT1 is in the GT power well */
1238 ret = mutex_lock_interruptible(&dev->struct_mutex);
1239 if (ret)
1240 goto out;
1241
1242 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1243
1244 reqf = I915_READ(GEN6_RPNSWREQ);
1245 if (IS_GEN9(dev))
1246 reqf >>= 23;
1247 else {
1248 reqf &= ~GEN6_TURBO_DISABLE;
1249 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1250 reqf >>= 24;
1251 else
1252 reqf >>= 25;
1253 }
1254 reqf = intel_gpu_freq(dev_priv, reqf);
1255
1256 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1257 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1258 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1259
1260 rpstat = I915_READ(GEN6_RPSTAT1);
1261 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1262 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1263 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1264 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1265 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1266 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1267 if (IS_GEN9(dev))
1268 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1269 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1270 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1271 else
1272 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1273 cagf = intel_gpu_freq(dev_priv, cagf);
1274
1275 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1276 mutex_unlock(&dev->struct_mutex);
1277
1278 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1279 pm_ier = I915_READ(GEN6_PMIER);
1280 pm_imr = I915_READ(GEN6_PMIMR);
1281 pm_isr = I915_READ(GEN6_PMISR);
1282 pm_iir = I915_READ(GEN6_PMIIR);
1283 pm_mask = I915_READ(GEN6_PMINTRMSK);
1284 } else {
1285 pm_ier = I915_READ(GEN8_GT_IER(2));
1286 pm_imr = I915_READ(GEN8_GT_IMR(2));
1287 pm_isr = I915_READ(GEN8_GT_ISR(2));
1288 pm_iir = I915_READ(GEN8_GT_IIR(2));
1289 pm_mask = I915_READ(GEN6_PMINTRMSK);
1290 }
1291 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1292 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1293 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1294 seq_printf(m, "Render p-state ratio: %d\n",
1295 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1296 seq_printf(m, "Render p-state VID: %d\n",
1297 gt_perf_status & 0xff);
1298 seq_printf(m, "Render p-state limit: %d\n",
1299 rp_state_limits & 0xff);
1300 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1301 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1302 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1303 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1304 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1305 seq_printf(m, "CAGF: %dMHz\n", cagf);
1306 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1307 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1308 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1309 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1310 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1311 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1312 seq_printf(m, "Up threshold: %d%%\n",
1313 dev_priv->rps.up_threshold);
1314
1315 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1316 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1317 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1318 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1319 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1320 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1321 seq_printf(m, "Down threshold: %d%%\n",
1322 dev_priv->rps.down_threshold);
1323
1324 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1325 rp_state_cap >> 16) & 0xff;
1326 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1327 GEN9_FREQ_SCALER : 1);
1328 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1329 intel_gpu_freq(dev_priv, max_freq));
1330
1331 max_freq = (rp_state_cap & 0xff00) >> 8;
1332 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1333 GEN9_FREQ_SCALER : 1);
1334 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1335 intel_gpu_freq(dev_priv, max_freq));
1336
1337 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1338 rp_state_cap >> 0) & 0xff;
1339 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1340 GEN9_FREQ_SCALER : 1);
1341 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1342 intel_gpu_freq(dev_priv, max_freq));
1343 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1344 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1345
1346 seq_printf(m, "Current freq: %d MHz\n",
1347 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1348 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1349 seq_printf(m, "Idle freq: %d MHz\n",
1350 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1351 seq_printf(m, "Min freq: %d MHz\n",
1352 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1353 seq_printf(m, "Max freq: %d MHz\n",
1354 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1355 seq_printf(m,
1356 "efficient (RPe) frequency: %d MHz\n",
1357 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1358 } else {
1359 seq_puts(m, "no P-state info available\n");
1360 }
1361
1362 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1363 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1364 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1365
1366out:
1367 intel_runtime_pm_put(dev_priv);
1368 return ret;
1369}
1370
1371static int i915_hangcheck_info(struct seq_file *m, void *unused)
1372{
1373 struct drm_info_node *node = m->private;
1374 struct drm_device *dev = node->minor->dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 struct intel_engine_cs *engine;
1377 u64 acthd[I915_NUM_ENGINES];
1378 u32 seqno[I915_NUM_ENGINES];
1379 u32 instdone[I915_NUM_INSTDONE_REG];
1380 enum intel_engine_id id;
1381 int j;
1382
1383 if (!i915.enable_hangcheck) {
1384 seq_printf(m, "Hangcheck disabled\n");
1385 return 0;
1386 }
1387
1388 intel_runtime_pm_get(dev_priv);
1389
1390 for_each_engine_id(engine, dev_priv, id) {
1391 acthd[id] = intel_ring_get_active_head(engine);
1392 seqno[id] = engine->get_seqno(engine);
1393 }
1394
1395 i915_get_extra_instdone(dev_priv, instdone);
1396
1397 intel_runtime_pm_put(dev_priv);
1398
1399 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1400 seq_printf(m, "Hangcheck active, fires in %dms\n",
1401 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1402 jiffies));
1403 } else
1404 seq_printf(m, "Hangcheck inactive\n");
1405
1406 for_each_engine_id(engine, dev_priv, id) {
1407 seq_printf(m, "%s:\n", engine->name);
1408 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1409 engine->hangcheck.seqno,
1410 seqno[id],
1411 engine->last_submitted_seqno);
1412 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1413 engine->hangcheck.user_interrupts,
1414 READ_ONCE(engine->user_interrupts));
1415 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1416 (long long)engine->hangcheck.acthd,
1417 (long long)acthd[id]);
1418 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1419 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1420
1421 if (engine->id == RCS) {
1422 seq_puts(m, "\tinstdone read =");
1423
1424 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1425 seq_printf(m, " 0x%08x", instdone[j]);
1426
1427 seq_puts(m, "\n\tinstdone accu =");
1428
1429 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1430 seq_printf(m, " 0x%08x",
1431 engine->hangcheck.instdone[j]);
1432
1433 seq_puts(m, "\n");
1434 }
1435 }
1436
1437 return 0;
1438}
1439
1440static int ironlake_drpc_info(struct seq_file *m)
1441{
1442 struct drm_info_node *node = m->private;
1443 struct drm_device *dev = node->minor->dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 u32 rgvmodectl, rstdbyctl;
1446 u16 crstandvid;
1447 int ret;
1448
1449 ret = mutex_lock_interruptible(&dev->struct_mutex);
1450 if (ret)
1451 return ret;
1452 intel_runtime_pm_get(dev_priv);
1453
1454 rgvmodectl = I915_READ(MEMMODECTL);
1455 rstdbyctl = I915_READ(RSTDBYCTL);
1456 crstandvid = I915_READ16(CRSTANDVID);
1457
1458 intel_runtime_pm_put(dev_priv);
1459 mutex_unlock(&dev->struct_mutex);
1460
1461 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1462 seq_printf(m, "Boost freq: %d\n",
1463 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1464 MEMMODE_BOOST_FREQ_SHIFT);
1465 seq_printf(m, "HW control enabled: %s\n",
1466 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1467 seq_printf(m, "SW control enabled: %s\n",
1468 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1469 seq_printf(m, "Gated voltage change: %s\n",
1470 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1471 seq_printf(m, "Starting frequency: P%d\n",
1472 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1473 seq_printf(m, "Max P-state: P%d\n",
1474 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1475 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1476 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1477 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1478 seq_printf(m, "Render standby enabled: %s\n",
1479 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1480 seq_puts(m, "Current RS state: ");
1481 switch (rstdbyctl & RSX_STATUS_MASK) {
1482 case RSX_STATUS_ON:
1483 seq_puts(m, "on\n");
1484 break;
1485 case RSX_STATUS_RC1:
1486 seq_puts(m, "RC1\n");
1487 break;
1488 case RSX_STATUS_RC1E:
1489 seq_puts(m, "RC1E\n");
1490 break;
1491 case RSX_STATUS_RS1:
1492 seq_puts(m, "RS1\n");
1493 break;
1494 case RSX_STATUS_RS2:
1495 seq_puts(m, "RS2 (RC6)\n");
1496 break;
1497 case RSX_STATUS_RS3:
1498 seq_puts(m, "RC3 (RC6+)\n");
1499 break;
1500 default:
1501 seq_puts(m, "unknown\n");
1502 break;
1503 }
1504
1505 return 0;
1506}
1507
1508static int i915_forcewake_domains(struct seq_file *m, void *data)
1509{
1510 struct drm_info_node *node = m->private;
1511 struct drm_device *dev = node->minor->dev;
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1513 struct intel_uncore_forcewake_domain *fw_domain;
1514
1515 spin_lock_irq(&dev_priv->uncore.lock);
1516 for_each_fw_domain(fw_domain, dev_priv) {
1517 seq_printf(m, "%s.wake_count = %u\n",
1518 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1519 fw_domain->wake_count);
1520 }
1521 spin_unlock_irq(&dev_priv->uncore.lock);
1522
1523 return 0;
1524}
1525
1526static int vlv_drpc_info(struct seq_file *m)
1527{
1528 struct drm_info_node *node = m->private;
1529 struct drm_device *dev = node->minor->dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 u32 rpmodectl1, rcctl1, pw_status;
1532
1533 intel_runtime_pm_get(dev_priv);
1534
1535 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1536 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1537 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1538
1539 intel_runtime_pm_put(dev_priv);
1540
1541 seq_printf(m, "Video Turbo Mode: %s\n",
1542 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1543 seq_printf(m, "Turbo enabled: %s\n",
1544 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1545 seq_printf(m, "HW control enabled: %s\n",
1546 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1547 seq_printf(m, "SW control enabled: %s\n",
1548 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1549 GEN6_RP_MEDIA_SW_MODE));
1550 seq_printf(m, "RC6 Enabled: %s\n",
1551 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1552 GEN6_RC_CTL_EI_MODE(1))));
1553 seq_printf(m, "Render Power Well: %s\n",
1554 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1555 seq_printf(m, "Media Power Well: %s\n",
1556 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1557
1558 seq_printf(m, "Render RC6 residency since boot: %u\n",
1559 I915_READ(VLV_GT_RENDER_RC6));
1560 seq_printf(m, "Media RC6 residency since boot: %u\n",
1561 I915_READ(VLV_GT_MEDIA_RC6));
1562
1563 return i915_forcewake_domains(m, NULL);
1564}
1565
1566static int gen6_drpc_info(struct seq_file *m)
1567{
1568 struct drm_info_node *node = m->private;
1569 struct drm_device *dev = node->minor->dev;
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1571 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1572 unsigned forcewake_count;
1573 int count = 0, ret;
1574
1575 ret = mutex_lock_interruptible(&dev->struct_mutex);
1576 if (ret)
1577 return ret;
1578 intel_runtime_pm_get(dev_priv);
1579
1580 spin_lock_irq(&dev_priv->uncore.lock);
1581 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1582 spin_unlock_irq(&dev_priv->uncore.lock);
1583
1584 if (forcewake_count) {
1585 seq_puts(m, "RC information inaccurate because somebody "
1586 "holds a forcewake reference \n");
1587 } else {
1588 /* NB: we cannot use forcewake, else we read the wrong values */
1589 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1590 udelay(10);
1591 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1592 }
1593
1594 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1595 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1596
1597 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1598 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1599 mutex_unlock(&dev->struct_mutex);
1600 mutex_lock(&dev_priv->rps.hw_lock);
1601 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1602 mutex_unlock(&dev_priv->rps.hw_lock);
1603
1604 intel_runtime_pm_put(dev_priv);
1605
1606 seq_printf(m, "Video Turbo Mode: %s\n",
1607 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1608 seq_printf(m, "HW control enabled: %s\n",
1609 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1610 seq_printf(m, "SW control enabled: %s\n",
1611 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1612 GEN6_RP_MEDIA_SW_MODE));
1613 seq_printf(m, "RC1e Enabled: %s\n",
1614 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1615 seq_printf(m, "RC6 Enabled: %s\n",
1616 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1617 seq_printf(m, "Deep RC6 Enabled: %s\n",
1618 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1619 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1620 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1621 seq_puts(m, "Current RC state: ");
1622 switch (gt_core_status & GEN6_RCn_MASK) {
1623 case GEN6_RC0:
1624 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1625 seq_puts(m, "Core Power Down\n");
1626 else
1627 seq_puts(m, "on\n");
1628 break;
1629 case GEN6_RC3:
1630 seq_puts(m, "RC3\n");
1631 break;
1632 case GEN6_RC6:
1633 seq_puts(m, "RC6\n");
1634 break;
1635 case GEN6_RC7:
1636 seq_puts(m, "RC7\n");
1637 break;
1638 default:
1639 seq_puts(m, "Unknown\n");
1640 break;
1641 }
1642
1643 seq_printf(m, "Core Power Down: %s\n",
1644 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1645
1646 /* Not exactly sure what this is */
1647 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1648 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1649 seq_printf(m, "RC6 residency since boot: %u\n",
1650 I915_READ(GEN6_GT_GFX_RC6));
1651 seq_printf(m, "RC6+ residency since boot: %u\n",
1652 I915_READ(GEN6_GT_GFX_RC6p));
1653 seq_printf(m, "RC6++ residency since boot: %u\n",
1654 I915_READ(GEN6_GT_GFX_RC6pp));
1655
1656 seq_printf(m, "RC6 voltage: %dmV\n",
1657 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1658 seq_printf(m, "RC6+ voltage: %dmV\n",
1659 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1660 seq_printf(m, "RC6++ voltage: %dmV\n",
1661 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1662 return 0;
1663}
1664
1665static int i915_drpc_info(struct seq_file *m, void *unused)
1666{
1667 struct drm_info_node *node = m->private;
1668 struct drm_device *dev = node->minor->dev;
1669
1670 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1671 return vlv_drpc_info(m);
1672 else if (INTEL_INFO(dev)->gen >= 6)
1673 return gen6_drpc_info(m);
1674 else
1675 return ironlake_drpc_info(m);
1676}
1677
1678static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1679{
1680 struct drm_info_node *node = m->private;
1681 struct drm_device *dev = node->minor->dev;
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1685 dev_priv->fb_tracking.busy_bits);
1686
1687 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1688 dev_priv->fb_tracking.flip_bits);
1689
1690 return 0;
1691}
1692
1693static int i915_fbc_status(struct seq_file *m, void *unused)
1694{
1695 struct drm_info_node *node = m->private;
1696 struct drm_device *dev = node->minor->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 if (!HAS_FBC(dev)) {
1700 seq_puts(m, "FBC unsupported on this chipset\n");
1701 return 0;
1702 }
1703
1704 intel_runtime_pm_get(dev_priv);
1705 mutex_lock(&dev_priv->fbc.lock);
1706
1707 if (intel_fbc_is_active(dev_priv))
1708 seq_puts(m, "FBC enabled\n");
1709 else
1710 seq_printf(m, "FBC disabled: %s\n",
1711 dev_priv->fbc.no_fbc_reason);
1712
1713 if (INTEL_INFO(dev_priv)->gen >= 7)
1714 seq_printf(m, "Compressing: %s\n",
1715 yesno(I915_READ(FBC_STATUS2) &
1716 FBC_COMPRESSION_MASK));
1717
1718 mutex_unlock(&dev_priv->fbc.lock);
1719 intel_runtime_pm_put(dev_priv);
1720
1721 return 0;
1722}
1723
1724static int i915_fbc_fc_get(void *data, u64 *val)
1725{
1726 struct drm_device *dev = data;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1730 return -ENODEV;
1731
1732 *val = dev_priv->fbc.false_color;
1733
1734 return 0;
1735}
1736
1737static int i915_fbc_fc_set(void *data, u64 val)
1738{
1739 struct drm_device *dev = data;
1740 struct drm_i915_private *dev_priv = dev->dev_private;
1741 u32 reg;
1742
1743 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1744 return -ENODEV;
1745
1746 mutex_lock(&dev_priv->fbc.lock);
1747
1748 reg = I915_READ(ILK_DPFC_CONTROL);
1749 dev_priv->fbc.false_color = val;
1750
1751 I915_WRITE(ILK_DPFC_CONTROL, val ?
1752 (reg | FBC_CTL_FALSE_COLOR) :
1753 (reg & ~FBC_CTL_FALSE_COLOR));
1754
1755 mutex_unlock(&dev_priv->fbc.lock);
1756 return 0;
1757}
1758
1759DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1760 i915_fbc_fc_get, i915_fbc_fc_set,
1761 "%llu\n");
1762
1763static int i915_ips_status(struct seq_file *m, void *unused)
1764{
1765 struct drm_info_node *node = m->private;
1766 struct drm_device *dev = node->minor->dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768
1769 if (!HAS_IPS(dev)) {
1770 seq_puts(m, "not supported\n");
1771 return 0;
1772 }
1773
1774 intel_runtime_pm_get(dev_priv);
1775
1776 seq_printf(m, "Enabled by kernel parameter: %s\n",
1777 yesno(i915.enable_ips));
1778
1779 if (INTEL_INFO(dev)->gen >= 8) {
1780 seq_puts(m, "Currently: unknown\n");
1781 } else {
1782 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1783 seq_puts(m, "Currently: enabled\n");
1784 else
1785 seq_puts(m, "Currently: disabled\n");
1786 }
1787
1788 intel_runtime_pm_put(dev_priv);
1789
1790 return 0;
1791}
1792
1793static int i915_sr_status(struct seq_file *m, void *unused)
1794{
1795 struct drm_info_node *node = m->private;
1796 struct drm_device *dev = node->minor->dev;
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 bool sr_enabled = false;
1799
1800 intel_runtime_pm_get(dev_priv);
1801
1802 if (HAS_PCH_SPLIT(dev))
1803 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1804 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1805 IS_I945G(dev) || IS_I945GM(dev))
1806 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1807 else if (IS_I915GM(dev))
1808 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1809 else if (IS_PINEVIEW(dev))
1810 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1811 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1812 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1813
1814 intel_runtime_pm_put(dev_priv);
1815
1816 seq_printf(m, "self-refresh: %s\n",
1817 sr_enabled ? "enabled" : "disabled");
1818
1819 return 0;
1820}
1821
1822static int i915_emon_status(struct seq_file *m, void *unused)
1823{
1824 struct drm_info_node *node = m->private;
1825 struct drm_device *dev = node->minor->dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 unsigned long temp, chipset, gfx;
1828 int ret;
1829
1830 if (!IS_GEN5(dev))
1831 return -ENODEV;
1832
1833 ret = mutex_lock_interruptible(&dev->struct_mutex);
1834 if (ret)
1835 return ret;
1836
1837 temp = i915_mch_val(dev_priv);
1838 chipset = i915_chipset_val(dev_priv);
1839 gfx = i915_gfx_val(dev_priv);
1840 mutex_unlock(&dev->struct_mutex);
1841
1842 seq_printf(m, "GMCH temp: %ld\n", temp);
1843 seq_printf(m, "Chipset power: %ld\n", chipset);
1844 seq_printf(m, "GFX power: %ld\n", gfx);
1845 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1846
1847 return 0;
1848}
1849
1850static int i915_ring_freq_table(struct seq_file *m, void *unused)
1851{
1852 struct drm_info_node *node = m->private;
1853 struct drm_device *dev = node->minor->dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 int ret = 0;
1856 int gpu_freq, ia_freq;
1857 unsigned int max_gpu_freq, min_gpu_freq;
1858
1859 if (!HAS_CORE_RING_FREQ(dev)) {
1860 seq_puts(m, "unsupported on this chipset\n");
1861 return 0;
1862 }
1863
1864 intel_runtime_pm_get(dev_priv);
1865
1866 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1867
1868 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1869 if (ret)
1870 goto out;
1871
1872 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1873 /* Convert GT frequency to 50 HZ units */
1874 min_gpu_freq =
1875 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1876 max_gpu_freq =
1877 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1878 } else {
1879 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1880 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1881 }
1882
1883 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1884
1885 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1886 ia_freq = gpu_freq;
1887 sandybridge_pcode_read(dev_priv,
1888 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1889 &ia_freq);
1890 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1891 intel_gpu_freq(dev_priv, (gpu_freq *
1892 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1893 GEN9_FREQ_SCALER : 1))),
1894 ((ia_freq >> 0) & 0xff) * 100,
1895 ((ia_freq >> 8) & 0xff) * 100);
1896 }
1897
1898 mutex_unlock(&dev_priv->rps.hw_lock);
1899
1900out:
1901 intel_runtime_pm_put(dev_priv);
1902 return ret;
1903}
1904
1905static int i915_opregion(struct seq_file *m, void *unused)
1906{
1907 struct drm_info_node *node = m->private;
1908 struct drm_device *dev = node->minor->dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_opregion *opregion = &dev_priv->opregion;
1911 int ret;
1912
1913 ret = mutex_lock_interruptible(&dev->struct_mutex);
1914 if (ret)
1915 goto out;
1916
1917 if (opregion->header)
1918 seq_write(m, opregion->header, OPREGION_SIZE);
1919
1920 mutex_unlock(&dev->struct_mutex);
1921
1922out:
1923 return 0;
1924}
1925
1926static int i915_vbt(struct seq_file *m, void *unused)
1927{
1928 struct drm_info_node *node = m->private;
1929 struct drm_device *dev = node->minor->dev;
1930 struct drm_i915_private *dev_priv = dev->dev_private;
1931 struct intel_opregion *opregion = &dev_priv->opregion;
1932
1933 if (opregion->vbt)
1934 seq_write(m, opregion->vbt, opregion->vbt_size);
1935
1936 return 0;
1937}
1938
1939static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1940{
1941 struct drm_info_node *node = m->private;
1942 struct drm_device *dev = node->minor->dev;
1943 struct intel_framebuffer *fbdev_fb = NULL;
1944 struct drm_framebuffer *drm_fb;
1945 int ret;
1946
1947 ret = mutex_lock_interruptible(&dev->struct_mutex);
1948 if (ret)
1949 return ret;
1950
1951#ifdef CONFIG_DRM_FBDEV_EMULATION
1952 if (to_i915(dev)->fbdev) {
1953 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1954
1955 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1956 fbdev_fb->base.width,
1957 fbdev_fb->base.height,
1958 fbdev_fb->base.depth,
1959 fbdev_fb->base.bits_per_pixel,
1960 fbdev_fb->base.modifier[0],
1961 drm_framebuffer_read_refcount(&fbdev_fb->base));
1962 describe_obj(m, fbdev_fb->obj);
1963 seq_putc(m, '\n');
1964 }
1965#endif
1966
1967 mutex_lock(&dev->mode_config.fb_lock);
1968 drm_for_each_fb(drm_fb, dev) {
1969 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1970 if (fb == fbdev_fb)
1971 continue;
1972
1973 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1974 fb->base.width,
1975 fb->base.height,
1976 fb->base.depth,
1977 fb->base.bits_per_pixel,
1978 fb->base.modifier[0],
1979 drm_framebuffer_read_refcount(&fb->base));
1980 describe_obj(m, fb->obj);
1981 seq_putc(m, '\n');
1982 }
1983 mutex_unlock(&dev->mode_config.fb_lock);
1984 mutex_unlock(&dev->struct_mutex);
1985
1986 return 0;
1987}
1988
1989static void describe_ctx_ringbuf(struct seq_file *m,
1990 struct intel_ringbuffer *ringbuf)
1991{
1992 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1993 ringbuf->space, ringbuf->head, ringbuf->tail,
1994 ringbuf->last_retired_head);
1995}
1996
1997static int i915_context_status(struct seq_file *m, void *unused)
1998{
1999 struct drm_info_node *node = m->private;
2000 struct drm_device *dev = node->minor->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_engine_cs *engine;
2003 struct intel_context *ctx;
2004 enum intel_engine_id id;
2005 int ret;
2006
2007 ret = mutex_lock_interruptible(&dev->struct_mutex);
2008 if (ret)
2009 return ret;
2010
2011 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2012 if (!i915.enable_execlists &&
2013 ctx->legacy_hw_ctx.rcs_state == NULL)
2014 continue;
2015
2016 seq_printf(m, "HW context %u ", ctx->hw_id);
2017 describe_ctx(m, ctx);
2018 if (ctx == dev_priv->kernel_context)
2019 seq_printf(m, "(kernel context) ");
2020
2021 if (i915.enable_execlists) {
2022 seq_putc(m, '\n');
2023 for_each_engine_id(engine, dev_priv, id) {
2024 struct drm_i915_gem_object *ctx_obj =
2025 ctx->engine[id].state;
2026 struct intel_ringbuffer *ringbuf =
2027 ctx->engine[id].ringbuf;
2028
2029 seq_printf(m, "%s: ", engine->name);
2030 if (ctx_obj)
2031 describe_obj(m, ctx_obj);
2032 if (ringbuf)
2033 describe_ctx_ringbuf(m, ringbuf);
2034 seq_putc(m, '\n');
2035 }
2036 } else {
2037 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
2038 }
2039
2040 seq_putc(m, '\n');
2041 }
2042
2043 mutex_unlock(&dev->struct_mutex);
2044
2045 return 0;
2046}
2047
2048static void i915_dump_lrc_obj(struct seq_file *m,
2049 struct intel_context *ctx,
2050 struct intel_engine_cs *engine)
2051{
2052 struct page *page;
2053 uint32_t *reg_state;
2054 int j;
2055 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2056 unsigned long ggtt_offset = 0;
2057
2058 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2059
2060 if (ctx_obj == NULL) {
2061 seq_puts(m, "\tNot allocated\n");
2062 return;
2063 }
2064
2065 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2066 seq_puts(m, "\tNot bound in GGTT\n");
2067 else
2068 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2069
2070 if (i915_gem_object_get_pages(ctx_obj)) {
2071 seq_puts(m, "\tFailed to get pages for context object\n");
2072 return;
2073 }
2074
2075 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2076 if (!WARN_ON(page == NULL)) {
2077 reg_state = kmap_atomic(page);
2078
2079 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2080 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2081 ggtt_offset + 4096 + (j * 4),
2082 reg_state[j], reg_state[j + 1],
2083 reg_state[j + 2], reg_state[j + 3]);
2084 }
2085 kunmap_atomic(reg_state);
2086 }
2087
2088 seq_putc(m, '\n');
2089}
2090
2091static int i915_dump_lrc(struct seq_file *m, void *unused)
2092{
2093 struct drm_info_node *node = (struct drm_info_node *) m->private;
2094 struct drm_device *dev = node->minor->dev;
2095 struct drm_i915_private *dev_priv = dev->dev_private;
2096 struct intel_engine_cs *engine;
2097 struct intel_context *ctx;
2098 int ret;
2099
2100 if (!i915.enable_execlists) {
2101 seq_printf(m, "Logical Ring Contexts are disabled\n");
2102 return 0;
2103 }
2104
2105 ret = mutex_lock_interruptible(&dev->struct_mutex);
2106 if (ret)
2107 return ret;
2108
2109 list_for_each_entry(ctx, &dev_priv->context_list, link)
2110 for_each_engine(engine, dev_priv)
2111 i915_dump_lrc_obj(m, ctx, engine);
2112
2113 mutex_unlock(&dev->struct_mutex);
2114
2115 return 0;
2116}
2117
2118static int i915_execlists(struct seq_file *m, void *data)
2119{
2120 struct drm_info_node *node = (struct drm_info_node *)m->private;
2121 struct drm_device *dev = node->minor->dev;
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 struct intel_engine_cs *engine;
2124 u32 status_pointer;
2125 u8 read_pointer;
2126 u8 write_pointer;
2127 u32 status;
2128 u32 ctx_id;
2129 struct list_head *cursor;
2130 int i, ret;
2131
2132 if (!i915.enable_execlists) {
2133 seq_puts(m, "Logical Ring Contexts are disabled\n");
2134 return 0;
2135 }
2136
2137 ret = mutex_lock_interruptible(&dev->struct_mutex);
2138 if (ret)
2139 return ret;
2140
2141 intel_runtime_pm_get(dev_priv);
2142
2143 for_each_engine(engine, dev_priv) {
2144 struct drm_i915_gem_request *head_req = NULL;
2145 int count = 0;
2146
2147 seq_printf(m, "%s\n", engine->name);
2148
2149 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2150 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2151 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2152 status, ctx_id);
2153
2154 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2155 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2156
2157 read_pointer = engine->next_context_status_buffer;
2158 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2159 if (read_pointer > write_pointer)
2160 write_pointer += GEN8_CSB_ENTRIES;
2161 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2162 read_pointer, write_pointer);
2163
2164 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2165 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2166 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2167
2168 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2169 i, status, ctx_id);
2170 }
2171
2172 spin_lock_bh(&engine->execlist_lock);
2173 list_for_each(cursor, &engine->execlist_queue)
2174 count++;
2175 head_req = list_first_entry_or_null(&engine->execlist_queue,
2176 struct drm_i915_gem_request,
2177 execlist_link);
2178 spin_unlock_bh(&engine->execlist_lock);
2179
2180 seq_printf(m, "\t%d requests in queue\n", count);
2181 if (head_req) {
2182 seq_printf(m, "\tHead request context: %u\n",
2183 head_req->ctx->hw_id);
2184 seq_printf(m, "\tHead request tail: %u\n",
2185 head_req->tail);
2186 }
2187
2188 seq_putc(m, '\n');
2189 }
2190
2191 intel_runtime_pm_put(dev_priv);
2192 mutex_unlock(&dev->struct_mutex);
2193
2194 return 0;
2195}
2196
2197static const char *swizzle_string(unsigned swizzle)
2198{
2199 switch (swizzle) {
2200 case I915_BIT_6_SWIZZLE_NONE:
2201 return "none";
2202 case I915_BIT_6_SWIZZLE_9:
2203 return "bit9";
2204 case I915_BIT_6_SWIZZLE_9_10:
2205 return "bit9/bit10";
2206 case I915_BIT_6_SWIZZLE_9_11:
2207 return "bit9/bit11";
2208 case I915_BIT_6_SWIZZLE_9_10_11:
2209 return "bit9/bit10/bit11";
2210 case I915_BIT_6_SWIZZLE_9_17:
2211 return "bit9/bit17";
2212 case I915_BIT_6_SWIZZLE_9_10_17:
2213 return "bit9/bit10/bit17";
2214 case I915_BIT_6_SWIZZLE_UNKNOWN:
2215 return "unknown";
2216 }
2217
2218 return "bug";
2219}
2220
2221static int i915_swizzle_info(struct seq_file *m, void *data)
2222{
2223 struct drm_info_node *node = m->private;
2224 struct drm_device *dev = node->minor->dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 int ret;
2227
2228 ret = mutex_lock_interruptible(&dev->struct_mutex);
2229 if (ret)
2230 return ret;
2231 intel_runtime_pm_get(dev_priv);
2232
2233 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2234 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2235 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2236 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2237
2238 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2239 seq_printf(m, "DDC = 0x%08x\n",
2240 I915_READ(DCC));
2241 seq_printf(m, "DDC2 = 0x%08x\n",
2242 I915_READ(DCC2));
2243 seq_printf(m, "C0DRB3 = 0x%04x\n",
2244 I915_READ16(C0DRB3));
2245 seq_printf(m, "C1DRB3 = 0x%04x\n",
2246 I915_READ16(C1DRB3));
2247 } else if (INTEL_INFO(dev)->gen >= 6) {
2248 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2249 I915_READ(MAD_DIMM_C0));
2250 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2251 I915_READ(MAD_DIMM_C1));
2252 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2253 I915_READ(MAD_DIMM_C2));
2254 seq_printf(m, "TILECTL = 0x%08x\n",
2255 I915_READ(TILECTL));
2256 if (INTEL_INFO(dev)->gen >= 8)
2257 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2258 I915_READ(GAMTARBMODE));
2259 else
2260 seq_printf(m, "ARB_MODE = 0x%08x\n",
2261 I915_READ(ARB_MODE));
2262 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2263 I915_READ(DISP_ARB_CTL));
2264 }
2265
2266 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2267 seq_puts(m, "L-shaped memory detected\n");
2268
2269 intel_runtime_pm_put(dev_priv);
2270 mutex_unlock(&dev->struct_mutex);
2271
2272 return 0;
2273}
2274
2275static int per_file_ctx(int id, void *ptr, void *data)
2276{
2277 struct intel_context *ctx = ptr;
2278 struct seq_file *m = data;
2279 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2280
2281 if (!ppgtt) {
2282 seq_printf(m, " no ppgtt for context %d\n",
2283 ctx->user_handle);
2284 return 0;
2285 }
2286
2287 if (i915_gem_context_is_default(ctx))
2288 seq_puts(m, " default context:\n");
2289 else
2290 seq_printf(m, " context %d:\n", ctx->user_handle);
2291 ppgtt->debug_dump(ppgtt, m);
2292
2293 return 0;
2294}
2295
2296static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2297{
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299 struct intel_engine_cs *engine;
2300 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2301 int i;
2302
2303 if (!ppgtt)
2304 return;
2305
2306 for_each_engine(engine, dev_priv) {
2307 seq_printf(m, "%s\n", engine->name);
2308 for (i = 0; i < 4; i++) {
2309 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2310 pdp <<= 32;
2311 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2312 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2313 }
2314 }
2315}
2316
2317static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2318{
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 struct intel_engine_cs *engine;
2321
2322 if (IS_GEN6(dev_priv))
2323 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2324
2325 for_each_engine(engine, dev_priv) {
2326 seq_printf(m, "%s\n", engine->name);
2327 if (IS_GEN7(dev_priv))
2328 seq_printf(m, "GFX_MODE: 0x%08x\n",
2329 I915_READ(RING_MODE_GEN7(engine)));
2330 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2331 I915_READ(RING_PP_DIR_BASE(engine)));
2332 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2333 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2334 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2335 I915_READ(RING_PP_DIR_DCLV(engine)));
2336 }
2337 if (dev_priv->mm.aliasing_ppgtt) {
2338 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2339
2340 seq_puts(m, "aliasing PPGTT:\n");
2341 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2342
2343 ppgtt->debug_dump(ppgtt, m);
2344 }
2345
2346 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2347}
2348
2349static int i915_ppgtt_info(struct seq_file *m, void *data)
2350{
2351 struct drm_info_node *node = m->private;
2352 struct drm_device *dev = node->minor->dev;
2353 struct drm_i915_private *dev_priv = dev->dev_private;
2354 struct drm_file *file;
2355
2356 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2357 if (ret)
2358 return ret;
2359 intel_runtime_pm_get(dev_priv);
2360
2361 if (INTEL_INFO(dev)->gen >= 8)
2362 gen8_ppgtt_info(m, dev);
2363 else if (INTEL_INFO(dev)->gen >= 6)
2364 gen6_ppgtt_info(m, dev);
2365
2366 mutex_lock(&dev->filelist_mutex);
2367 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2368 struct drm_i915_file_private *file_priv = file->driver_priv;
2369 struct task_struct *task;
2370
2371 task = get_pid_task(file->pid, PIDTYPE_PID);
2372 if (!task) {
2373 ret = -ESRCH;
2374 goto out_put;
2375 }
2376 seq_printf(m, "\nproc: %s\n", task->comm);
2377 put_task_struct(task);
2378 idr_for_each(&file_priv->context_idr, per_file_ctx,
2379 (void *)(unsigned long)m);
2380 }
2381 mutex_unlock(&dev->filelist_mutex);
2382
2383out_put:
2384 intel_runtime_pm_put(dev_priv);
2385 mutex_unlock(&dev->struct_mutex);
2386
2387 return ret;
2388}
2389
2390static int count_irq_waiters(struct drm_i915_private *i915)
2391{
2392 struct intel_engine_cs *engine;
2393 int count = 0;
2394
2395 for_each_engine(engine, i915)
2396 count += engine->irq_refcount;
2397
2398 return count;
2399}
2400
2401static int i915_rps_boost_info(struct seq_file *m, void *data)
2402{
2403 struct drm_info_node *node = m->private;
2404 struct drm_device *dev = node->minor->dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct drm_file *file;
2407
2408 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2409 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2410 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2411 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2412 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2413 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2414 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2415 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2416 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2417
2418 mutex_lock(&dev->filelist_mutex);
2419 spin_lock(&dev_priv->rps.client_lock);
2420 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2421 struct drm_i915_file_private *file_priv = file->driver_priv;
2422 struct task_struct *task;
2423
2424 rcu_read_lock();
2425 task = pid_task(file->pid, PIDTYPE_PID);
2426 seq_printf(m, "%s [%d]: %d boosts%s\n",
2427 task ? task->comm : "<unknown>",
2428 task ? task->pid : -1,
2429 file_priv->rps.boosts,
2430 list_empty(&file_priv->rps.link) ? "" : ", active");
2431 rcu_read_unlock();
2432 }
2433 seq_printf(m, "Semaphore boosts: %d%s\n",
2434 dev_priv->rps.semaphores.boosts,
2435 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2436 seq_printf(m, "MMIO flip boosts: %d%s\n",
2437 dev_priv->rps.mmioflips.boosts,
2438 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2439 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2440 spin_unlock(&dev_priv->rps.client_lock);
2441 mutex_unlock(&dev->filelist_mutex);
2442
2443 return 0;
2444}
2445
2446static int i915_llc(struct seq_file *m, void *data)
2447{
2448 struct drm_info_node *node = m->private;
2449 struct drm_device *dev = node->minor->dev;
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 const bool edram = INTEL_GEN(dev_priv) > 8;
2452
2453 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2454 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2455 intel_uncore_edram_size(dev_priv)/1024/1024);
2456
2457 return 0;
2458}
2459
2460static int i915_guc_load_status_info(struct seq_file *m, void *data)
2461{
2462 struct drm_info_node *node = m->private;
2463 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2464 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2465 u32 tmp, i;
2466
2467 if (!HAS_GUC_UCODE(dev_priv))
2468 return 0;
2469
2470 seq_printf(m, "GuC firmware status:\n");
2471 seq_printf(m, "\tpath: %s\n",
2472 guc_fw->guc_fw_path);
2473 seq_printf(m, "\tfetch: %s\n",
2474 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2475 seq_printf(m, "\tload: %s\n",
2476 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2477 seq_printf(m, "\tversion wanted: %d.%d\n",
2478 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2479 seq_printf(m, "\tversion found: %d.%d\n",
2480 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2481 seq_printf(m, "\theader: offset is %d; size = %d\n",
2482 guc_fw->header_offset, guc_fw->header_size);
2483 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2484 guc_fw->ucode_offset, guc_fw->ucode_size);
2485 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2486 guc_fw->rsa_offset, guc_fw->rsa_size);
2487
2488 tmp = I915_READ(GUC_STATUS);
2489
2490 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2491 seq_printf(m, "\tBootrom status = 0x%x\n",
2492 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2493 seq_printf(m, "\tuKernel status = 0x%x\n",
2494 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2495 seq_printf(m, "\tMIA Core status = 0x%x\n",
2496 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2497 seq_puts(m, "\nScratch registers:\n");
2498 for (i = 0; i < 16; i++)
2499 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2500
2501 return 0;
2502}
2503
2504static void i915_guc_client_info(struct seq_file *m,
2505 struct drm_i915_private *dev_priv,
2506 struct i915_guc_client *client)
2507{
2508 struct intel_engine_cs *engine;
2509 uint64_t tot = 0;
2510
2511 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2512 client->priority, client->ctx_index, client->proc_desc_offset);
2513 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2514 client->doorbell_id, client->doorbell_offset, client->cookie);
2515 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2516 client->wq_size, client->wq_offset, client->wq_tail);
2517
2518 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2519 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2520 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2521 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2522
2523 for_each_engine(engine, dev_priv) {
2524 seq_printf(m, "\tSubmissions: %llu %s\n",
2525 client->submissions[engine->guc_id],
2526 engine->name);
2527 tot += client->submissions[engine->guc_id];
2528 }
2529 seq_printf(m, "\tTotal: %llu\n", tot);
2530}
2531
2532static int i915_guc_info(struct seq_file *m, void *data)
2533{
2534 struct drm_info_node *node = m->private;
2535 struct drm_device *dev = node->minor->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537 struct intel_guc guc;
2538 struct i915_guc_client client = {};
2539 struct intel_engine_cs *engine;
2540 u64 total = 0;
2541
2542 if (!HAS_GUC_SCHED(dev_priv))
2543 return 0;
2544
2545 if (mutex_lock_interruptible(&dev->struct_mutex))
2546 return 0;
2547
2548 /* Take a local copy of the GuC data, so we can dump it at leisure */
2549 guc = dev_priv->guc;
2550 if (guc.execbuf_client)
2551 client = *guc.execbuf_client;
2552
2553 mutex_unlock(&dev->struct_mutex);
2554
2555 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2556 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2557 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2558 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2559 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2560
2561 seq_printf(m, "\nGuC submissions:\n");
2562 for_each_engine(engine, dev_priv) {
2563 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2564 engine->name, guc.submissions[engine->guc_id],
2565 guc.last_seqno[engine->guc_id]);
2566 total += guc.submissions[engine->guc_id];
2567 }
2568 seq_printf(m, "\t%s: %llu\n", "Total", total);
2569
2570 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2571 i915_guc_client_info(m, dev_priv, &client);
2572
2573 /* Add more as required ... */
2574
2575 return 0;
2576}
2577
2578static int i915_guc_log_dump(struct seq_file *m, void *data)
2579{
2580 struct drm_info_node *node = m->private;
2581 struct drm_device *dev = node->minor->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2584 u32 *log;
2585 int i = 0, pg;
2586
2587 if (!log_obj)
2588 return 0;
2589
2590 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2591 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2592
2593 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2594 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2595 *(log + i), *(log + i + 1),
2596 *(log + i + 2), *(log + i + 3));
2597
2598 kunmap_atomic(log);
2599 }
2600
2601 seq_putc(m, '\n');
2602
2603 return 0;
2604}
2605
2606static int i915_edp_psr_status(struct seq_file *m, void *data)
2607{
2608 struct drm_info_node *node = m->private;
2609 struct drm_device *dev = node->minor->dev;
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2611 u32 psrperf = 0;
2612 u32 stat[3];
2613 enum pipe pipe;
2614 bool enabled = false;
2615
2616 if (!HAS_PSR(dev)) {
2617 seq_puts(m, "PSR not supported\n");
2618 return 0;
2619 }
2620
2621 intel_runtime_pm_get(dev_priv);
2622
2623 mutex_lock(&dev_priv->psr.lock);
2624 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2625 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2626 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2627 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2628 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2629 dev_priv->psr.busy_frontbuffer_bits);
2630 seq_printf(m, "Re-enable work scheduled: %s\n",
2631 yesno(work_busy(&dev_priv->psr.work.work)));
2632
2633 if (HAS_DDI(dev))
2634 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2635 else {
2636 for_each_pipe(dev_priv, pipe) {
2637 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2638 VLV_EDP_PSR_CURR_STATE_MASK;
2639 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2640 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2641 enabled = true;
2642 }
2643 }
2644
2645 seq_printf(m, "Main link in standby mode: %s\n",
2646 yesno(dev_priv->psr.link_standby));
2647
2648 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2649
2650 if (!HAS_DDI(dev))
2651 for_each_pipe(dev_priv, pipe) {
2652 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2653 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2654 seq_printf(m, " pipe %c", pipe_name(pipe));
2655 }
2656 seq_puts(m, "\n");
2657
2658 /*
2659 * VLV/CHV PSR has no kind of performance counter
2660 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2661 */
2662 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2663 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2664 EDP_PSR_PERF_CNT_MASK;
2665
2666 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2667 }
2668 mutex_unlock(&dev_priv->psr.lock);
2669
2670 intel_runtime_pm_put(dev_priv);
2671 return 0;
2672}
2673
2674static int i915_sink_crc(struct seq_file *m, void *data)
2675{
2676 struct drm_info_node *node = m->private;
2677 struct drm_device *dev = node->minor->dev;
2678 struct intel_encoder *encoder;
2679 struct intel_connector *connector;
2680 struct intel_dp *intel_dp = NULL;
2681 int ret;
2682 u8 crc[6];
2683
2684 drm_modeset_lock_all(dev);
2685 for_each_intel_connector(dev, connector) {
2686
2687 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2688 continue;
2689
2690 if (!connector->base.encoder)
2691 continue;
2692
2693 encoder = to_intel_encoder(connector->base.encoder);
2694 if (encoder->type != INTEL_OUTPUT_EDP)
2695 continue;
2696
2697 intel_dp = enc_to_intel_dp(&encoder->base);
2698
2699 ret = intel_dp_sink_crc(intel_dp, crc);
2700 if (ret)
2701 goto out;
2702
2703 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2704 crc[0], crc[1], crc[2],
2705 crc[3], crc[4], crc[5]);
2706 goto out;
2707 }
2708 ret = -ENODEV;
2709out:
2710 drm_modeset_unlock_all(dev);
2711 return ret;
2712}
2713
2714static int i915_energy_uJ(struct seq_file *m, void *data)
2715{
2716 struct drm_info_node *node = m->private;
2717 struct drm_device *dev = node->minor->dev;
2718 struct drm_i915_private *dev_priv = dev->dev_private;
2719 u64 power;
2720 u32 units;
2721
2722 if (INTEL_INFO(dev)->gen < 6)
2723 return -ENODEV;
2724
2725 intel_runtime_pm_get(dev_priv);
2726
2727 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2728 power = (power & 0x1f00) >> 8;
2729 units = 1000000 / (1 << power); /* convert to uJ */
2730 power = I915_READ(MCH_SECP_NRG_STTS);
2731 power *= units;
2732
2733 intel_runtime_pm_put(dev_priv);
2734
2735 seq_printf(m, "%llu", (long long unsigned)power);
2736
2737 return 0;
2738}
2739
2740static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2741{
2742 struct drm_info_node *node = m->private;
2743 struct drm_device *dev = node->minor->dev;
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745
2746 if (!HAS_RUNTIME_PM(dev_priv))
2747 seq_puts(m, "Runtime power management not supported\n");
2748
2749 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2750 seq_printf(m, "IRQs disabled: %s\n",
2751 yesno(!intel_irqs_enabled(dev_priv)));
2752#ifdef CONFIG_PM
2753 seq_printf(m, "Usage count: %d\n",
2754 atomic_read(&dev->dev->power.usage_count));
2755#else
2756 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2757#endif
2758 seq_printf(m, "PCI device power state: %s [%d]\n",
2759 pci_power_name(dev_priv->dev->pdev->current_state),
2760 dev_priv->dev->pdev->current_state);
2761
2762 return 0;
2763}
2764
2765static int i915_power_domain_info(struct seq_file *m, void *unused)
2766{
2767 struct drm_info_node *node = m->private;
2768 struct drm_device *dev = node->minor->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2771 int i;
2772
2773 mutex_lock(&power_domains->lock);
2774
2775 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2776 for (i = 0; i < power_domains->power_well_count; i++) {
2777 struct i915_power_well *power_well;
2778 enum intel_display_power_domain power_domain;
2779
2780 power_well = &power_domains->power_wells[i];
2781 seq_printf(m, "%-25s %d\n", power_well->name,
2782 power_well->count);
2783
2784 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2785 power_domain++) {
2786 if (!(BIT(power_domain) & power_well->domains))
2787 continue;
2788
2789 seq_printf(m, " %-23s %d\n",
2790 intel_display_power_domain_str(power_domain),
2791 power_domains->domain_use_count[power_domain]);
2792 }
2793 }
2794
2795 mutex_unlock(&power_domains->lock);
2796
2797 return 0;
2798}
2799
2800static int i915_dmc_info(struct seq_file *m, void *unused)
2801{
2802 struct drm_info_node *node = m->private;
2803 struct drm_device *dev = node->minor->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_csr *csr;
2806
2807 if (!HAS_CSR(dev)) {
2808 seq_puts(m, "not supported\n");
2809 return 0;
2810 }
2811
2812 csr = &dev_priv->csr;
2813
2814 intel_runtime_pm_get(dev_priv);
2815
2816 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2817 seq_printf(m, "path: %s\n", csr->fw_path);
2818
2819 if (!csr->dmc_payload)
2820 goto out;
2821
2822 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2823 CSR_VERSION_MINOR(csr->version));
2824
2825 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2826 seq_printf(m, "DC3 -> DC5 count: %d\n",
2827 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2828 seq_printf(m, "DC5 -> DC6 count: %d\n",
2829 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2830 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2831 seq_printf(m, "DC3 -> DC5 count: %d\n",
2832 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2833 }
2834
2835out:
2836 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2837 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2838 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2839
2840 intel_runtime_pm_put(dev_priv);
2841
2842 return 0;
2843}
2844
2845static void intel_seq_print_mode(struct seq_file *m, int tabs,
2846 struct drm_display_mode *mode)
2847{
2848 int i;
2849
2850 for (i = 0; i < tabs; i++)
2851 seq_putc(m, '\t');
2852
2853 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2854 mode->base.id, mode->name,
2855 mode->vrefresh, mode->clock,
2856 mode->hdisplay, mode->hsync_start,
2857 mode->hsync_end, mode->htotal,
2858 mode->vdisplay, mode->vsync_start,
2859 mode->vsync_end, mode->vtotal,
2860 mode->type, mode->flags);
2861}
2862
2863static void intel_encoder_info(struct seq_file *m,
2864 struct intel_crtc *intel_crtc,
2865 struct intel_encoder *intel_encoder)
2866{
2867 struct drm_info_node *node = m->private;
2868 struct drm_device *dev = node->minor->dev;
2869 struct drm_crtc *crtc = &intel_crtc->base;
2870 struct intel_connector *intel_connector;
2871 struct drm_encoder *encoder;
2872
2873 encoder = &intel_encoder->base;
2874 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2875 encoder->base.id, encoder->name);
2876 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2877 struct drm_connector *connector = &intel_connector->base;
2878 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2879 connector->base.id,
2880 connector->name,
2881 drm_get_connector_status_name(connector->status));
2882 if (connector->status == connector_status_connected) {
2883 struct drm_display_mode *mode = &crtc->mode;
2884 seq_printf(m, ", mode:\n");
2885 intel_seq_print_mode(m, 2, mode);
2886 } else {
2887 seq_putc(m, '\n');
2888 }
2889 }
2890}
2891
2892static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2893{
2894 struct drm_info_node *node = m->private;
2895 struct drm_device *dev = node->minor->dev;
2896 struct drm_crtc *crtc = &intel_crtc->base;
2897 struct intel_encoder *intel_encoder;
2898 struct drm_plane_state *plane_state = crtc->primary->state;
2899 struct drm_framebuffer *fb = plane_state->fb;
2900
2901 if (fb)
2902 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2903 fb->base.id, plane_state->src_x >> 16,
2904 plane_state->src_y >> 16, fb->width, fb->height);
2905 else
2906 seq_puts(m, "\tprimary plane disabled\n");
2907 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2908 intel_encoder_info(m, intel_crtc, intel_encoder);
2909}
2910
2911static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2912{
2913 struct drm_display_mode *mode = panel->fixed_mode;
2914
2915 seq_printf(m, "\tfixed mode:\n");
2916 intel_seq_print_mode(m, 2, mode);
2917}
2918
2919static void intel_dp_info(struct seq_file *m,
2920 struct intel_connector *intel_connector)
2921{
2922 struct intel_encoder *intel_encoder = intel_connector->encoder;
2923 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2924
2925 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2926 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2927 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2928 intel_panel_info(m, &intel_connector->panel);
2929}
2930
2931static void intel_hdmi_info(struct seq_file *m,
2932 struct intel_connector *intel_connector)
2933{
2934 struct intel_encoder *intel_encoder = intel_connector->encoder;
2935 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2936
2937 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2938}
2939
2940static void intel_lvds_info(struct seq_file *m,
2941 struct intel_connector *intel_connector)
2942{
2943 intel_panel_info(m, &intel_connector->panel);
2944}
2945
2946static void intel_connector_info(struct seq_file *m,
2947 struct drm_connector *connector)
2948{
2949 struct intel_connector *intel_connector = to_intel_connector(connector);
2950 struct intel_encoder *intel_encoder = intel_connector->encoder;
2951 struct drm_display_mode *mode;
2952
2953 seq_printf(m, "connector %d: type %s, status: %s\n",
2954 connector->base.id, connector->name,
2955 drm_get_connector_status_name(connector->status));
2956 if (connector->status == connector_status_connected) {
2957 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2958 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2959 connector->display_info.width_mm,
2960 connector->display_info.height_mm);
2961 seq_printf(m, "\tsubpixel order: %s\n",
2962 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2963 seq_printf(m, "\tCEA rev: %d\n",
2964 connector->display_info.cea_rev);
2965 }
2966 if (intel_encoder) {
2967 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2968 intel_encoder->type == INTEL_OUTPUT_EDP)
2969 intel_dp_info(m, intel_connector);
2970 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2971 intel_hdmi_info(m, intel_connector);
2972 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2973 intel_lvds_info(m, intel_connector);
2974 }
2975
2976 seq_printf(m, "\tmodes:\n");
2977 list_for_each_entry(mode, &connector->modes, head)
2978 intel_seq_print_mode(m, 2, mode);
2979}
2980
2981static bool cursor_active(struct drm_device *dev, int pipe)
2982{
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 u32 state;
2985
2986 if (IS_845G(dev) || IS_I865G(dev))
2987 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2988 else
2989 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2990
2991 return state;
2992}
2993
2994static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2995{
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 u32 pos;
2998
2999 pos = I915_READ(CURPOS(pipe));
3000
3001 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3002 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3003 *x = -*x;
3004
3005 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3006 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3007 *y = -*y;
3008
3009 return cursor_active(dev, pipe);
3010}
3011
3012static const char *plane_type(enum drm_plane_type type)
3013{
3014 switch (type) {
3015 case DRM_PLANE_TYPE_OVERLAY:
3016 return "OVL";
3017 case DRM_PLANE_TYPE_PRIMARY:
3018 return "PRI";
3019 case DRM_PLANE_TYPE_CURSOR:
3020 return "CUR";
3021 /*
3022 * Deliberately omitting default: to generate compiler warnings
3023 * when a new drm_plane_type gets added.
3024 */
3025 }
3026
3027 return "unknown";
3028}
3029
3030static const char *plane_rotation(unsigned int rotation)
3031{
3032 static char buf[48];
3033 /*
3034 * According to doc only one DRM_ROTATE_ is allowed but this
3035 * will print them all to visualize if the values are misused
3036 */
3037 snprintf(buf, sizeof(buf),
3038 "%s%s%s%s%s%s(0x%08x)",
3039 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3040 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3041 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3042 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3043 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3044 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3045 rotation);
3046
3047 return buf;
3048}
3049
3050static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3051{
3052 struct drm_info_node *node = m->private;
3053 struct drm_device *dev = node->minor->dev;
3054 struct intel_plane *intel_plane;
3055
3056 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3057 struct drm_plane_state *state;
3058 struct drm_plane *plane = &intel_plane->base;
3059
3060 if (!plane->state) {
3061 seq_puts(m, "plane->state is NULL!\n");
3062 continue;
3063 }
3064
3065 state = plane->state;
3066
3067 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3068 plane->base.id,
3069 plane_type(intel_plane->base.type),
3070 state->crtc_x, state->crtc_y,
3071 state->crtc_w, state->crtc_h,
3072 (state->src_x >> 16),
3073 ((state->src_x & 0xffff) * 15625) >> 10,
3074 (state->src_y >> 16),
3075 ((state->src_y & 0xffff) * 15625) >> 10,
3076 (state->src_w >> 16),
3077 ((state->src_w & 0xffff) * 15625) >> 10,
3078 (state->src_h >> 16),
3079 ((state->src_h & 0xffff) * 15625) >> 10,
3080 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3081 plane_rotation(state->rotation));
3082 }
3083}
3084
3085static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3086{
3087 struct intel_crtc_state *pipe_config;
3088 int num_scalers = intel_crtc->num_scalers;
3089 int i;
3090
3091 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3092
3093 /* Not all platformas have a scaler */
3094 if (num_scalers) {
3095 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3096 num_scalers,
3097 pipe_config->scaler_state.scaler_users,
3098 pipe_config->scaler_state.scaler_id);
3099
3100 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3101 struct intel_scaler *sc =
3102 &pipe_config->scaler_state.scalers[i];
3103
3104 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3105 i, yesno(sc->in_use), sc->mode);
3106 }
3107 seq_puts(m, "\n");
3108 } else {
3109 seq_puts(m, "\tNo scalers available on this platform\n");
3110 }
3111}
3112
3113static int i915_display_info(struct seq_file *m, void *unused)
3114{
3115 struct drm_info_node *node = m->private;
3116 struct drm_device *dev = node->minor->dev;
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118 struct intel_crtc *crtc;
3119 struct drm_connector *connector;
3120
3121 intel_runtime_pm_get(dev_priv);
3122 drm_modeset_lock_all(dev);
3123 seq_printf(m, "CRTC info\n");
3124 seq_printf(m, "---------\n");
3125 for_each_intel_crtc(dev, crtc) {
3126 bool active;
3127 struct intel_crtc_state *pipe_config;
3128 int x, y;
3129
3130 pipe_config = to_intel_crtc_state(crtc->base.state);
3131
3132 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3133 crtc->base.base.id, pipe_name(crtc->pipe),
3134 yesno(pipe_config->base.active),
3135 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3136 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3137
3138 if (pipe_config->base.active) {
3139 intel_crtc_info(m, crtc);
3140
3141 active = cursor_position(dev, crtc->pipe, &x, &y);
3142 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3143 yesno(crtc->cursor_base),
3144 x, y, crtc->base.cursor->state->crtc_w,
3145 crtc->base.cursor->state->crtc_h,
3146 crtc->cursor_addr, yesno(active));
3147 intel_scaler_info(m, crtc);
3148 intel_plane_info(m, crtc);
3149 }
3150
3151 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3152 yesno(!crtc->cpu_fifo_underrun_disabled),
3153 yesno(!crtc->pch_fifo_underrun_disabled));
3154 }
3155
3156 seq_printf(m, "\n");
3157 seq_printf(m, "Connector info\n");
3158 seq_printf(m, "--------------\n");
3159 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3160 intel_connector_info(m, connector);
3161 }
3162 drm_modeset_unlock_all(dev);
3163 intel_runtime_pm_put(dev_priv);
3164
3165 return 0;
3166}
3167
3168static int i915_semaphore_status(struct seq_file *m, void *unused)
3169{
3170 struct drm_info_node *node = (struct drm_info_node *) m->private;
3171 struct drm_device *dev = node->minor->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_engine_cs *engine;
3174 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3175 enum intel_engine_id id;
3176 int j, ret;
3177
3178 if (!i915_semaphore_is_enabled(dev_priv)) {
3179 seq_puts(m, "Semaphores are disabled\n");
3180 return 0;
3181 }
3182
3183 ret = mutex_lock_interruptible(&dev->struct_mutex);
3184 if (ret)
3185 return ret;
3186 intel_runtime_pm_get(dev_priv);
3187
3188 if (IS_BROADWELL(dev)) {
3189 struct page *page;
3190 uint64_t *seqno;
3191
3192 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3193
3194 seqno = (uint64_t *)kmap_atomic(page);
3195 for_each_engine_id(engine, dev_priv, id) {
3196 uint64_t offset;
3197
3198 seq_printf(m, "%s\n", engine->name);
3199
3200 seq_puts(m, " Last signal:");
3201 for (j = 0; j < num_rings; j++) {
3202 offset = id * I915_NUM_ENGINES + j;
3203 seq_printf(m, "0x%08llx (0x%02llx) ",
3204 seqno[offset], offset * 8);
3205 }
3206 seq_putc(m, '\n');
3207
3208 seq_puts(m, " Last wait: ");
3209 for (j = 0; j < num_rings; j++) {
3210 offset = id + (j * I915_NUM_ENGINES);
3211 seq_printf(m, "0x%08llx (0x%02llx) ",
3212 seqno[offset], offset * 8);
3213 }
3214 seq_putc(m, '\n');
3215
3216 }
3217 kunmap_atomic(seqno);
3218 } else {
3219 seq_puts(m, " Last signal:");
3220 for_each_engine(engine, dev_priv)
3221 for (j = 0; j < num_rings; j++)
3222 seq_printf(m, "0x%08x\n",
3223 I915_READ(engine->semaphore.mbox.signal[j]));
3224 seq_putc(m, '\n');
3225 }
3226
3227 seq_puts(m, "\nSync seqno:\n");
3228 for_each_engine(engine, dev_priv) {
3229 for (j = 0; j < num_rings; j++)
3230 seq_printf(m, " 0x%08x ",
3231 engine->semaphore.sync_seqno[j]);
3232 seq_putc(m, '\n');
3233 }
3234 seq_putc(m, '\n');
3235
3236 intel_runtime_pm_put(dev_priv);
3237 mutex_unlock(&dev->struct_mutex);
3238 return 0;
3239}
3240
3241static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3242{
3243 struct drm_info_node *node = (struct drm_info_node *) m->private;
3244 struct drm_device *dev = node->minor->dev;
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246 int i;
3247
3248 drm_modeset_lock_all(dev);
3249 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3250 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3251
3252 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3253 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3254 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3255 seq_printf(m, " tracked hardware state:\n");
3256 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3257 seq_printf(m, " dpll_md: 0x%08x\n",
3258 pll->config.hw_state.dpll_md);
3259 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3260 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3261 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3262 }
3263 drm_modeset_unlock_all(dev);
3264
3265 return 0;
3266}
3267
3268static int i915_wa_registers(struct seq_file *m, void *unused)
3269{
3270 int i;
3271 int ret;
3272 struct intel_engine_cs *engine;
3273 struct drm_info_node *node = (struct drm_info_node *) m->private;
3274 struct drm_device *dev = node->minor->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3277 enum intel_engine_id id;
3278
3279 ret = mutex_lock_interruptible(&dev->struct_mutex);
3280 if (ret)
3281 return ret;
3282
3283 intel_runtime_pm_get(dev_priv);
3284
3285 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3286 for_each_engine_id(engine, dev_priv, id)
3287 seq_printf(m, "HW whitelist count for %s: %d\n",
3288 engine->name, workarounds->hw_whitelist_count[id]);
3289 for (i = 0; i < workarounds->count; ++i) {
3290 i915_reg_t addr;
3291 u32 mask, value, read;
3292 bool ok;
3293
3294 addr = workarounds->reg[i].addr;
3295 mask = workarounds->reg[i].mask;
3296 value = workarounds->reg[i].value;
3297 read = I915_READ(addr);
3298 ok = (value & mask) == (read & mask);
3299 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3300 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3301 }
3302
3303 intel_runtime_pm_put(dev_priv);
3304 mutex_unlock(&dev->struct_mutex);
3305
3306 return 0;
3307}
3308
3309static int i915_ddb_info(struct seq_file *m, void *unused)
3310{
3311 struct drm_info_node *node = m->private;
3312 struct drm_device *dev = node->minor->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct skl_ddb_allocation *ddb;
3315 struct skl_ddb_entry *entry;
3316 enum pipe pipe;
3317 int plane;
3318
3319 if (INTEL_INFO(dev)->gen < 9)
3320 return 0;
3321
3322 drm_modeset_lock_all(dev);
3323
3324 ddb = &dev_priv->wm.skl_hw.ddb;
3325
3326 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3327
3328 for_each_pipe(dev_priv, pipe) {
3329 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3330
3331 for_each_plane(dev_priv, pipe, plane) {
3332 entry = &ddb->plane[pipe][plane];
3333 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3334 entry->start, entry->end,
3335 skl_ddb_entry_size(entry));
3336 }
3337
3338 entry = &ddb->plane[pipe][PLANE_CURSOR];
3339 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3340 entry->end, skl_ddb_entry_size(entry));
3341 }
3342
3343 drm_modeset_unlock_all(dev);
3344
3345 return 0;
3346}
3347
3348static void drrs_status_per_crtc(struct seq_file *m,
3349 struct drm_device *dev, struct intel_crtc *intel_crtc)
3350{
3351 struct intel_encoder *intel_encoder;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct i915_drrs *drrs = &dev_priv->drrs;
3354 int vrefresh = 0;
3355
3356 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3357 /* Encoder connected on this CRTC */
3358 switch (intel_encoder->type) {
3359 case INTEL_OUTPUT_EDP:
3360 seq_puts(m, "eDP:\n");
3361 break;
3362 case INTEL_OUTPUT_DSI:
3363 seq_puts(m, "DSI:\n");
3364 break;
3365 case INTEL_OUTPUT_HDMI:
3366 seq_puts(m, "HDMI:\n");
3367 break;
3368 case INTEL_OUTPUT_DISPLAYPORT:
3369 seq_puts(m, "DP:\n");
3370 break;
3371 default:
3372 seq_printf(m, "Other encoder (id=%d).\n",
3373 intel_encoder->type);
3374 return;
3375 }
3376 }
3377
3378 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3379 seq_puts(m, "\tVBT: DRRS_type: Static");
3380 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3381 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3382 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3383 seq_puts(m, "\tVBT: DRRS_type: None");
3384 else
3385 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3386
3387 seq_puts(m, "\n\n");
3388
3389 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3390 struct intel_panel *panel;
3391
3392 mutex_lock(&drrs->mutex);
3393 /* DRRS Supported */
3394 seq_puts(m, "\tDRRS Supported: Yes\n");
3395
3396 /* disable_drrs() will make drrs->dp NULL */
3397 if (!drrs->dp) {
3398 seq_puts(m, "Idleness DRRS: Disabled");
3399 mutex_unlock(&drrs->mutex);
3400 return;
3401 }
3402
3403 panel = &drrs->dp->attached_connector->panel;
3404 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3405 drrs->busy_frontbuffer_bits);
3406
3407 seq_puts(m, "\n\t\t");
3408 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3409 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3410 vrefresh = panel->fixed_mode->vrefresh;
3411 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3412 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3413 vrefresh = panel->downclock_mode->vrefresh;
3414 } else {
3415 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3416 drrs->refresh_rate_type);
3417 mutex_unlock(&drrs->mutex);
3418 return;
3419 }
3420 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3421
3422 seq_puts(m, "\n\t\t");
3423 mutex_unlock(&drrs->mutex);
3424 } else {
3425 /* DRRS not supported. Print the VBT parameter*/
3426 seq_puts(m, "\tDRRS Supported : No");
3427 }
3428 seq_puts(m, "\n");
3429}
3430
3431static int i915_drrs_status(struct seq_file *m, void *unused)
3432{
3433 struct drm_info_node *node = m->private;
3434 struct drm_device *dev = node->minor->dev;
3435 struct intel_crtc *intel_crtc;
3436 int active_crtc_cnt = 0;
3437
3438 for_each_intel_crtc(dev, intel_crtc) {
3439 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3440
3441 if (intel_crtc->base.state->active) {
3442 active_crtc_cnt++;
3443 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3444
3445 drrs_status_per_crtc(m, dev, intel_crtc);
3446 }
3447
3448 drm_modeset_unlock(&intel_crtc->base.mutex);
3449 }
3450
3451 if (!active_crtc_cnt)
3452 seq_puts(m, "No active crtc found\n");
3453
3454 return 0;
3455}
3456
3457struct pipe_crc_info {
3458 const char *name;
3459 struct drm_device *dev;
3460 enum pipe pipe;
3461};
3462
3463static int i915_dp_mst_info(struct seq_file *m, void *unused)
3464{
3465 struct drm_info_node *node = (struct drm_info_node *) m->private;
3466 struct drm_device *dev = node->minor->dev;
3467 struct drm_encoder *encoder;
3468 struct intel_encoder *intel_encoder;
3469 struct intel_digital_port *intel_dig_port;
3470 drm_modeset_lock_all(dev);
3471 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3472 intel_encoder = to_intel_encoder(encoder);
3473 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3474 continue;
3475 intel_dig_port = enc_to_dig_port(encoder);
3476 if (!intel_dig_port->dp.can_mst)
3477 continue;
3478 seq_printf(m, "MST Source Port %c\n",
3479 port_name(intel_dig_port->port));
3480 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3481 }
3482 drm_modeset_unlock_all(dev);
3483 return 0;
3484}
3485
3486static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3487{
3488 struct pipe_crc_info *info = inode->i_private;
3489 struct drm_i915_private *dev_priv = info->dev->dev_private;
3490 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3491
3492 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3493 return -ENODEV;
3494
3495 spin_lock_irq(&pipe_crc->lock);
3496
3497 if (pipe_crc->opened) {
3498 spin_unlock_irq(&pipe_crc->lock);
3499 return -EBUSY; /* already open */
3500 }
3501
3502 pipe_crc->opened = true;
3503 filep->private_data = inode->i_private;
3504
3505 spin_unlock_irq(&pipe_crc->lock);
3506
3507 return 0;
3508}
3509
3510static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3511{
3512 struct pipe_crc_info *info = inode->i_private;
3513 struct drm_i915_private *dev_priv = info->dev->dev_private;
3514 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3515
3516 spin_lock_irq(&pipe_crc->lock);
3517 pipe_crc->opened = false;
3518 spin_unlock_irq(&pipe_crc->lock);
3519
3520 return 0;
3521}
3522
3523/* (6 fields, 8 chars each, space separated (5) + '\n') */
3524#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3525/* account for \'0' */
3526#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3527
3528static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3529{
3530 assert_spin_locked(&pipe_crc->lock);
3531 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3532 INTEL_PIPE_CRC_ENTRIES_NR);
3533}
3534
3535static ssize_t
3536i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3537 loff_t *pos)
3538{
3539 struct pipe_crc_info *info = filep->private_data;
3540 struct drm_device *dev = info->dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3543 char buf[PIPE_CRC_BUFFER_LEN];
3544 int n_entries;
3545 ssize_t bytes_read;
3546
3547 /*
3548 * Don't allow user space to provide buffers not big enough to hold
3549 * a line of data.
3550 */
3551 if (count < PIPE_CRC_LINE_LEN)
3552 return -EINVAL;
3553
3554 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3555 return 0;
3556
3557 /* nothing to read */
3558 spin_lock_irq(&pipe_crc->lock);
3559 while (pipe_crc_data_count(pipe_crc) == 0) {
3560 int ret;
3561
3562 if (filep->f_flags & O_NONBLOCK) {
3563 spin_unlock_irq(&pipe_crc->lock);
3564 return -EAGAIN;
3565 }
3566
3567 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3568 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3569 if (ret) {
3570 spin_unlock_irq(&pipe_crc->lock);
3571 return ret;
3572 }
3573 }
3574
3575 /* We now have one or more entries to read */
3576 n_entries = count / PIPE_CRC_LINE_LEN;
3577
3578 bytes_read = 0;
3579 while (n_entries > 0) {
3580 struct intel_pipe_crc_entry *entry =
3581 &pipe_crc->entries[pipe_crc->tail];
3582 int ret;
3583
3584 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3585 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3586 break;
3587
3588 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3589 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3590
3591 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3592 "%8u %8x %8x %8x %8x %8x\n",
3593 entry->frame, entry->crc[0],
3594 entry->crc[1], entry->crc[2],
3595 entry->crc[3], entry->crc[4]);
3596
3597 spin_unlock_irq(&pipe_crc->lock);
3598
3599 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3600 if (ret == PIPE_CRC_LINE_LEN)
3601 return -EFAULT;
3602
3603 user_buf += PIPE_CRC_LINE_LEN;
3604 n_entries--;
3605
3606 spin_lock_irq(&pipe_crc->lock);
3607 }
3608
3609 spin_unlock_irq(&pipe_crc->lock);
3610
3611 return bytes_read;
3612}
3613
3614static const struct file_operations i915_pipe_crc_fops = {
3615 .owner = THIS_MODULE,
3616 .open = i915_pipe_crc_open,
3617 .read = i915_pipe_crc_read,
3618 .release = i915_pipe_crc_release,
3619};
3620
3621static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3622 {
3623 .name = "i915_pipe_A_crc",
3624 .pipe = PIPE_A,
3625 },
3626 {
3627 .name = "i915_pipe_B_crc",
3628 .pipe = PIPE_B,
3629 },
3630 {
3631 .name = "i915_pipe_C_crc",
3632 .pipe = PIPE_C,
3633 },
3634};
3635
3636static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3637 enum pipe pipe)
3638{
3639 struct drm_device *dev = minor->dev;
3640 struct dentry *ent;
3641 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3642
3643 info->dev = dev;
3644 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3645 &i915_pipe_crc_fops);
3646 if (!ent)
3647 return -ENOMEM;
3648
3649 return drm_add_fake_info_node(minor, ent, info);
3650}
3651
3652static const char * const pipe_crc_sources[] = {
3653 "none",
3654 "plane1",
3655 "plane2",
3656 "pf",
3657 "pipe",
3658 "TV",
3659 "DP-B",
3660 "DP-C",
3661 "DP-D",
3662 "auto",
3663};
3664
3665static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3666{
3667 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3668 return pipe_crc_sources[source];
3669}
3670
3671static int display_crc_ctl_show(struct seq_file *m, void *data)
3672{
3673 struct drm_device *dev = m->private;
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675 int i;
3676
3677 for (i = 0; i < I915_MAX_PIPES; i++)
3678 seq_printf(m, "%c %s\n", pipe_name(i),
3679 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3680
3681 return 0;
3682}
3683
3684static int display_crc_ctl_open(struct inode *inode, struct file *file)
3685{
3686 struct drm_device *dev = inode->i_private;
3687
3688 return single_open(file, display_crc_ctl_show, dev);
3689}
3690
3691static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3692 uint32_t *val)
3693{
3694 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3695 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3696
3697 switch (*source) {
3698 case INTEL_PIPE_CRC_SOURCE_PIPE:
3699 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3700 break;
3701 case INTEL_PIPE_CRC_SOURCE_NONE:
3702 *val = 0;
3703 break;
3704 default:
3705 return -EINVAL;
3706 }
3707
3708 return 0;
3709}
3710
3711static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3712 enum intel_pipe_crc_source *source)
3713{
3714 struct intel_encoder *encoder;
3715 struct intel_crtc *crtc;
3716 struct intel_digital_port *dig_port;
3717 int ret = 0;
3718
3719 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3720
3721 drm_modeset_lock_all(dev);
3722 for_each_intel_encoder(dev, encoder) {
3723 if (!encoder->base.crtc)
3724 continue;
3725
3726 crtc = to_intel_crtc(encoder->base.crtc);
3727
3728 if (crtc->pipe != pipe)
3729 continue;
3730
3731 switch (encoder->type) {
3732 case INTEL_OUTPUT_TVOUT:
3733 *source = INTEL_PIPE_CRC_SOURCE_TV;
3734 break;
3735 case INTEL_OUTPUT_DISPLAYPORT:
3736 case INTEL_OUTPUT_EDP:
3737 dig_port = enc_to_dig_port(&encoder->base);
3738 switch (dig_port->port) {
3739 case PORT_B:
3740 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3741 break;
3742 case PORT_C:
3743 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3744 break;
3745 case PORT_D:
3746 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3747 break;
3748 default:
3749 WARN(1, "nonexisting DP port %c\n",
3750 port_name(dig_port->port));
3751 break;
3752 }
3753 break;
3754 default:
3755 break;
3756 }
3757 }
3758 drm_modeset_unlock_all(dev);
3759
3760 return ret;
3761}
3762
3763static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3764 enum pipe pipe,
3765 enum intel_pipe_crc_source *source,
3766 uint32_t *val)
3767{
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 bool need_stable_symbols = false;
3770
3771 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3772 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3773 if (ret)
3774 return ret;
3775 }
3776
3777 switch (*source) {
3778 case INTEL_PIPE_CRC_SOURCE_PIPE:
3779 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3780 break;
3781 case INTEL_PIPE_CRC_SOURCE_DP_B:
3782 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3783 need_stable_symbols = true;
3784 break;
3785 case INTEL_PIPE_CRC_SOURCE_DP_C:
3786 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3787 need_stable_symbols = true;
3788 break;
3789 case INTEL_PIPE_CRC_SOURCE_DP_D:
3790 if (!IS_CHERRYVIEW(dev))
3791 return -EINVAL;
3792 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3793 need_stable_symbols = true;
3794 break;
3795 case INTEL_PIPE_CRC_SOURCE_NONE:
3796 *val = 0;
3797 break;
3798 default:
3799 return -EINVAL;
3800 }
3801
3802 /*
3803 * When the pipe CRC tap point is after the transcoders we need
3804 * to tweak symbol-level features to produce a deterministic series of
3805 * symbols for a given frame. We need to reset those features only once
3806 * a frame (instead of every nth symbol):
3807 * - DC-balance: used to ensure a better clock recovery from the data
3808 * link (SDVO)
3809 * - DisplayPort scrambling: used for EMI reduction
3810 */
3811 if (need_stable_symbols) {
3812 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3813
3814 tmp |= DC_BALANCE_RESET_VLV;
3815 switch (pipe) {
3816 case PIPE_A:
3817 tmp |= PIPE_A_SCRAMBLE_RESET;
3818 break;
3819 case PIPE_B:
3820 tmp |= PIPE_B_SCRAMBLE_RESET;
3821 break;
3822 case PIPE_C:
3823 tmp |= PIPE_C_SCRAMBLE_RESET;
3824 break;
3825 default:
3826 return -EINVAL;
3827 }
3828 I915_WRITE(PORT_DFT2_G4X, tmp);
3829 }
3830
3831 return 0;
3832}
3833
3834static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3835 enum pipe pipe,
3836 enum intel_pipe_crc_source *source,
3837 uint32_t *val)
3838{
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 bool need_stable_symbols = false;
3841
3842 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3843 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3844 if (ret)
3845 return ret;
3846 }
3847
3848 switch (*source) {
3849 case INTEL_PIPE_CRC_SOURCE_PIPE:
3850 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3851 break;
3852 case INTEL_PIPE_CRC_SOURCE_TV:
3853 if (!SUPPORTS_TV(dev))
3854 return -EINVAL;
3855 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3856 break;
3857 case INTEL_PIPE_CRC_SOURCE_DP_B:
3858 if (!IS_G4X(dev))
3859 return -EINVAL;
3860 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3861 need_stable_symbols = true;
3862 break;
3863 case INTEL_PIPE_CRC_SOURCE_DP_C:
3864 if (!IS_G4X(dev))
3865 return -EINVAL;
3866 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3867 need_stable_symbols = true;
3868 break;
3869 case INTEL_PIPE_CRC_SOURCE_DP_D:
3870 if (!IS_G4X(dev))
3871 return -EINVAL;
3872 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3873 need_stable_symbols = true;
3874 break;
3875 case INTEL_PIPE_CRC_SOURCE_NONE:
3876 *val = 0;
3877 break;
3878 default:
3879 return -EINVAL;
3880 }
3881
3882 /*
3883 * When the pipe CRC tap point is after the transcoders we need
3884 * to tweak symbol-level features to produce a deterministic series of
3885 * symbols for a given frame. We need to reset those features only once
3886 * a frame (instead of every nth symbol):
3887 * - DC-balance: used to ensure a better clock recovery from the data
3888 * link (SDVO)
3889 * - DisplayPort scrambling: used for EMI reduction
3890 */
3891 if (need_stable_symbols) {
3892 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3893
3894 WARN_ON(!IS_G4X(dev));
3895
3896 I915_WRITE(PORT_DFT_I9XX,
3897 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3898
3899 if (pipe == PIPE_A)
3900 tmp |= PIPE_A_SCRAMBLE_RESET;
3901 else
3902 tmp |= PIPE_B_SCRAMBLE_RESET;
3903
3904 I915_WRITE(PORT_DFT2_G4X, tmp);
3905 }
3906
3907 return 0;
3908}
3909
3910static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3911 enum pipe pipe)
3912{
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3915
3916 switch (pipe) {
3917 case PIPE_A:
3918 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3919 break;
3920 case PIPE_B:
3921 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3922 break;
3923 case PIPE_C:
3924 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3925 break;
3926 default:
3927 return;
3928 }
3929 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3930 tmp &= ~DC_BALANCE_RESET_VLV;
3931 I915_WRITE(PORT_DFT2_G4X, tmp);
3932
3933}
3934
3935static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3936 enum pipe pipe)
3937{
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3940
3941 if (pipe == PIPE_A)
3942 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3943 else
3944 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3945 I915_WRITE(PORT_DFT2_G4X, tmp);
3946
3947 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3948 I915_WRITE(PORT_DFT_I9XX,
3949 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3950 }
3951}
3952
3953static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3954 uint32_t *val)
3955{
3956 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3957 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3958
3959 switch (*source) {
3960 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3961 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3962 break;
3963 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3964 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3965 break;
3966 case INTEL_PIPE_CRC_SOURCE_PIPE:
3967 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3968 break;
3969 case INTEL_PIPE_CRC_SOURCE_NONE:
3970 *val = 0;
3971 break;
3972 default:
3973 return -EINVAL;
3974 }
3975
3976 return 0;
3977}
3978
3979static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3980{
3981 struct drm_i915_private *dev_priv = dev->dev_private;
3982 struct intel_crtc *crtc =
3983 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3984 struct intel_crtc_state *pipe_config;
3985 struct drm_atomic_state *state;
3986 int ret = 0;
3987
3988 drm_modeset_lock_all(dev);
3989 state = drm_atomic_state_alloc(dev);
3990 if (!state) {
3991 ret = -ENOMEM;
3992 goto out;
3993 }
3994
3995 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3996 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3997 if (IS_ERR(pipe_config)) {
3998 ret = PTR_ERR(pipe_config);
3999 goto out;
4000 }
4001
4002 pipe_config->pch_pfit.force_thru = enable;
4003 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4004 pipe_config->pch_pfit.enabled != enable)
4005 pipe_config->base.connectors_changed = true;
4006
4007 ret = drm_atomic_commit(state);
4008out:
4009 drm_modeset_unlock_all(dev);
4010 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4011 if (ret)
4012 drm_atomic_state_free(state);
4013}
4014
4015static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4016 enum pipe pipe,
4017 enum intel_pipe_crc_source *source,
4018 uint32_t *val)
4019{
4020 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4021 *source = INTEL_PIPE_CRC_SOURCE_PF;
4022
4023 switch (*source) {
4024 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4025 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4026 break;
4027 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4028 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4029 break;
4030 case INTEL_PIPE_CRC_SOURCE_PF:
4031 if (IS_HASWELL(dev) && pipe == PIPE_A)
4032 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4033
4034 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4035 break;
4036 case INTEL_PIPE_CRC_SOURCE_NONE:
4037 *val = 0;
4038 break;
4039 default:
4040 return -EINVAL;
4041 }
4042
4043 return 0;
4044}
4045
4046static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4047 enum intel_pipe_crc_source source)
4048{
4049 struct drm_i915_private *dev_priv = dev->dev_private;
4050 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4051 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4052 pipe));
4053 enum intel_display_power_domain power_domain;
4054 u32 val = 0; /* shut up gcc */
4055 int ret;
4056
4057 if (pipe_crc->source == source)
4058 return 0;
4059
4060 /* forbid changing the source without going back to 'none' */
4061 if (pipe_crc->source && source)
4062 return -EINVAL;
4063
4064 power_domain = POWER_DOMAIN_PIPE(pipe);
4065 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4066 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4067 return -EIO;
4068 }
4069
4070 if (IS_GEN2(dev))
4071 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4072 else if (INTEL_INFO(dev)->gen < 5)
4073 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4074 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4075 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4076 else if (IS_GEN5(dev) || IS_GEN6(dev))
4077 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4078 else
4079 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4080
4081 if (ret != 0)
4082 goto out;
4083
4084 /* none -> real source transition */
4085 if (source) {
4086 struct intel_pipe_crc_entry *entries;
4087
4088 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4089 pipe_name(pipe), pipe_crc_source_name(source));
4090
4091 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4092 sizeof(pipe_crc->entries[0]),
4093 GFP_KERNEL);
4094 if (!entries) {
4095 ret = -ENOMEM;
4096 goto out;
4097 }
4098
4099 /*
4100 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4101 * enabled and disabled dynamically based on package C states,
4102 * user space can't make reliable use of the CRCs, so let's just
4103 * completely disable it.
4104 */
4105 hsw_disable_ips(crtc);
4106
4107 spin_lock_irq(&pipe_crc->lock);
4108 kfree(pipe_crc->entries);
4109 pipe_crc->entries = entries;
4110 pipe_crc->head = 0;
4111 pipe_crc->tail = 0;
4112 spin_unlock_irq(&pipe_crc->lock);
4113 }
4114
4115 pipe_crc->source = source;
4116
4117 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4118 POSTING_READ(PIPE_CRC_CTL(pipe));
4119
4120 /* real source -> none transition */
4121 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4122 struct intel_pipe_crc_entry *entries;
4123 struct intel_crtc *crtc =
4124 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4125
4126 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4127 pipe_name(pipe));
4128
4129 drm_modeset_lock(&crtc->base.mutex, NULL);
4130 if (crtc->base.state->active)
4131 intel_wait_for_vblank(dev, pipe);
4132 drm_modeset_unlock(&crtc->base.mutex);
4133
4134 spin_lock_irq(&pipe_crc->lock);
4135 entries = pipe_crc->entries;
4136 pipe_crc->entries = NULL;
4137 pipe_crc->head = 0;
4138 pipe_crc->tail = 0;
4139 spin_unlock_irq(&pipe_crc->lock);
4140
4141 kfree(entries);
4142
4143 if (IS_G4X(dev))
4144 g4x_undo_pipe_scramble_reset(dev, pipe);
4145 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4146 vlv_undo_pipe_scramble_reset(dev, pipe);
4147 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4148 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4149
4150 hsw_enable_ips(crtc);
4151 }
4152
4153 ret = 0;
4154
4155out:
4156 intel_display_power_put(dev_priv, power_domain);
4157
4158 return ret;
4159}
4160
4161/*
4162 * Parse pipe CRC command strings:
4163 * command: wsp* object wsp+ name wsp+ source wsp*
4164 * object: 'pipe'
4165 * name: (A | B | C)
4166 * source: (none | plane1 | plane2 | pf)
4167 * wsp: (#0x20 | #0x9 | #0xA)+
4168 *
4169 * eg.:
4170 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4171 * "pipe A none" -> Stop CRC
4172 */
4173static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4174{
4175 int n_words = 0;
4176
4177 while (*buf) {
4178 char *end;
4179
4180 /* skip leading white space */
4181 buf = skip_spaces(buf);
4182 if (!*buf)
4183 break; /* end of buffer */
4184
4185 /* find end of word */
4186 for (end = buf; *end && !isspace(*end); end++)
4187 ;
4188
4189 if (n_words == max_words) {
4190 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4191 max_words);
4192 return -EINVAL; /* ran out of words[] before bytes */
4193 }
4194
4195 if (*end)
4196 *end++ = '\0';
4197 words[n_words++] = buf;
4198 buf = end;
4199 }
4200
4201 return n_words;
4202}
4203
4204enum intel_pipe_crc_object {
4205 PIPE_CRC_OBJECT_PIPE,
4206};
4207
4208static const char * const pipe_crc_objects[] = {
4209 "pipe",
4210};
4211
4212static int
4213display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4214{
4215 int i;
4216
4217 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4218 if (!strcmp(buf, pipe_crc_objects[i])) {
4219 *o = i;
4220 return 0;
4221 }
4222
4223 return -EINVAL;
4224}
4225
4226static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4227{
4228 const char name = buf[0];
4229
4230 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4231 return -EINVAL;
4232
4233 *pipe = name - 'A';
4234
4235 return 0;
4236}
4237
4238static int
4239display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4240{
4241 int i;
4242
4243 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4244 if (!strcmp(buf, pipe_crc_sources[i])) {
4245 *s = i;
4246 return 0;
4247 }
4248
4249 return -EINVAL;
4250}
4251
4252static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4253{
4254#define N_WORDS 3
4255 int n_words;
4256 char *words[N_WORDS];
4257 enum pipe pipe;
4258 enum intel_pipe_crc_object object;
4259 enum intel_pipe_crc_source source;
4260
4261 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4262 if (n_words != N_WORDS) {
4263 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4264 N_WORDS);
4265 return -EINVAL;
4266 }
4267
4268 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4269 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4270 return -EINVAL;
4271 }
4272
4273 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4274 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4275 return -EINVAL;
4276 }
4277
4278 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4279 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4280 return -EINVAL;
4281 }
4282
4283 return pipe_crc_set_source(dev, pipe, source);
4284}
4285
4286static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4287 size_t len, loff_t *offp)
4288{
4289 struct seq_file *m = file->private_data;
4290 struct drm_device *dev = m->private;
4291 char *tmpbuf;
4292 int ret;
4293
4294 if (len == 0)
4295 return 0;
4296
4297 if (len > PAGE_SIZE - 1) {
4298 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4299 PAGE_SIZE);
4300 return -E2BIG;
4301 }
4302
4303 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4304 if (!tmpbuf)
4305 return -ENOMEM;
4306
4307 if (copy_from_user(tmpbuf, ubuf, len)) {
4308 ret = -EFAULT;
4309 goto out;
4310 }
4311 tmpbuf[len] = '\0';
4312
4313 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4314
4315out:
4316 kfree(tmpbuf);
4317 if (ret < 0)
4318 return ret;
4319
4320 *offp += len;
4321 return len;
4322}
4323
4324static const struct file_operations i915_display_crc_ctl_fops = {
4325 .owner = THIS_MODULE,
4326 .open = display_crc_ctl_open,
4327 .read = seq_read,
4328 .llseek = seq_lseek,
4329 .release = single_release,
4330 .write = display_crc_ctl_write
4331};
4332
4333static ssize_t i915_displayport_test_active_write(struct file *file,
4334 const char __user *ubuf,
4335 size_t len, loff_t *offp)
4336{
4337 char *input_buffer;
4338 int status = 0;
4339 struct drm_device *dev;
4340 struct drm_connector *connector;
4341 struct list_head *connector_list;
4342 struct intel_dp *intel_dp;
4343 int val = 0;
4344
4345 dev = ((struct seq_file *)file->private_data)->private;
4346
4347 connector_list = &dev->mode_config.connector_list;
4348
4349 if (len == 0)
4350 return 0;
4351
4352 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4353 if (!input_buffer)
4354 return -ENOMEM;
4355
4356 if (copy_from_user(input_buffer, ubuf, len)) {
4357 status = -EFAULT;
4358 goto out;
4359 }
4360
4361 input_buffer[len] = '\0';
4362 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4363
4364 list_for_each_entry(connector, connector_list, head) {
4365
4366 if (connector->connector_type !=
4367 DRM_MODE_CONNECTOR_DisplayPort)
4368 continue;
4369
4370 if (connector->status == connector_status_connected &&
4371 connector->encoder != NULL) {
4372 intel_dp = enc_to_intel_dp(connector->encoder);
4373 status = kstrtoint(input_buffer, 10, &val);
4374 if (status < 0)
4375 goto out;
4376 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4377 /* To prevent erroneous activation of the compliance
4378 * testing code, only accept an actual value of 1 here
4379 */
4380 if (val == 1)
4381 intel_dp->compliance_test_active = 1;
4382 else
4383 intel_dp->compliance_test_active = 0;
4384 }
4385 }
4386out:
4387 kfree(input_buffer);
4388 if (status < 0)
4389 return status;
4390
4391 *offp += len;
4392 return len;
4393}
4394
4395static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4396{
4397 struct drm_device *dev = m->private;
4398 struct drm_connector *connector;
4399 struct list_head *connector_list = &dev->mode_config.connector_list;
4400 struct intel_dp *intel_dp;
4401
4402 list_for_each_entry(connector, connector_list, head) {
4403
4404 if (connector->connector_type !=
4405 DRM_MODE_CONNECTOR_DisplayPort)
4406 continue;
4407
4408 if (connector->status == connector_status_connected &&
4409 connector->encoder != NULL) {
4410 intel_dp = enc_to_intel_dp(connector->encoder);
4411 if (intel_dp->compliance_test_active)
4412 seq_puts(m, "1");
4413 else
4414 seq_puts(m, "0");
4415 } else
4416 seq_puts(m, "0");
4417 }
4418
4419 return 0;
4420}
4421
4422static int i915_displayport_test_active_open(struct inode *inode,
4423 struct file *file)
4424{
4425 struct drm_device *dev = inode->i_private;
4426
4427 return single_open(file, i915_displayport_test_active_show, dev);
4428}
4429
4430static const struct file_operations i915_displayport_test_active_fops = {
4431 .owner = THIS_MODULE,
4432 .open = i915_displayport_test_active_open,
4433 .read = seq_read,
4434 .llseek = seq_lseek,
4435 .release = single_release,
4436 .write = i915_displayport_test_active_write
4437};
4438
4439static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4440{
4441 struct drm_device *dev = m->private;
4442 struct drm_connector *connector;
4443 struct list_head *connector_list = &dev->mode_config.connector_list;
4444 struct intel_dp *intel_dp;
4445
4446 list_for_each_entry(connector, connector_list, head) {
4447
4448 if (connector->connector_type !=
4449 DRM_MODE_CONNECTOR_DisplayPort)
4450 continue;
4451
4452 if (connector->status == connector_status_connected &&
4453 connector->encoder != NULL) {
4454 intel_dp = enc_to_intel_dp(connector->encoder);
4455 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4456 } else
4457 seq_puts(m, "0");
4458 }
4459
4460 return 0;
4461}
4462static int i915_displayport_test_data_open(struct inode *inode,
4463 struct file *file)
4464{
4465 struct drm_device *dev = inode->i_private;
4466
4467 return single_open(file, i915_displayport_test_data_show, dev);
4468}
4469
4470static const struct file_operations i915_displayport_test_data_fops = {
4471 .owner = THIS_MODULE,
4472 .open = i915_displayport_test_data_open,
4473 .read = seq_read,
4474 .llseek = seq_lseek,
4475 .release = single_release
4476};
4477
4478static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4479{
4480 struct drm_device *dev = m->private;
4481 struct drm_connector *connector;
4482 struct list_head *connector_list = &dev->mode_config.connector_list;
4483 struct intel_dp *intel_dp;
4484
4485 list_for_each_entry(connector, connector_list, head) {
4486
4487 if (connector->connector_type !=
4488 DRM_MODE_CONNECTOR_DisplayPort)
4489 continue;
4490
4491 if (connector->status == connector_status_connected &&
4492 connector->encoder != NULL) {
4493 intel_dp = enc_to_intel_dp(connector->encoder);
4494 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4495 } else
4496 seq_puts(m, "0");
4497 }
4498
4499 return 0;
4500}
4501
4502static int i915_displayport_test_type_open(struct inode *inode,
4503 struct file *file)
4504{
4505 struct drm_device *dev = inode->i_private;
4506
4507 return single_open(file, i915_displayport_test_type_show, dev);
4508}
4509
4510static const struct file_operations i915_displayport_test_type_fops = {
4511 .owner = THIS_MODULE,
4512 .open = i915_displayport_test_type_open,
4513 .read = seq_read,
4514 .llseek = seq_lseek,
4515 .release = single_release
4516};
4517
4518static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4519{
4520 struct drm_device *dev = m->private;
4521 int level;
4522 int num_levels;
4523
4524 if (IS_CHERRYVIEW(dev))
4525 num_levels = 3;
4526 else if (IS_VALLEYVIEW(dev))
4527 num_levels = 1;
4528 else
4529 num_levels = ilk_wm_max_level(dev) + 1;
4530
4531 drm_modeset_lock_all(dev);
4532
4533 for (level = 0; level < num_levels; level++) {
4534 unsigned int latency = wm[level];
4535
4536 /*
4537 * - WM1+ latency values in 0.5us units
4538 * - latencies are in us on gen9/vlv/chv
4539 */
4540 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4541 IS_CHERRYVIEW(dev))
4542 latency *= 10;
4543 else if (level > 0)
4544 latency *= 5;
4545
4546 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4547 level, wm[level], latency / 10, latency % 10);
4548 }
4549
4550 drm_modeset_unlock_all(dev);
4551}
4552
4553static int pri_wm_latency_show(struct seq_file *m, void *data)
4554{
4555 struct drm_device *dev = m->private;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 const uint16_t *latencies;
4558
4559 if (INTEL_INFO(dev)->gen >= 9)
4560 latencies = dev_priv->wm.skl_latency;
4561 else
4562 latencies = to_i915(dev)->wm.pri_latency;
4563
4564 wm_latency_show(m, latencies);
4565
4566 return 0;
4567}
4568
4569static int spr_wm_latency_show(struct seq_file *m, void *data)
4570{
4571 struct drm_device *dev = m->private;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 const uint16_t *latencies;
4574
4575 if (INTEL_INFO(dev)->gen >= 9)
4576 latencies = dev_priv->wm.skl_latency;
4577 else
4578 latencies = to_i915(dev)->wm.spr_latency;
4579
4580 wm_latency_show(m, latencies);
4581
4582 return 0;
4583}
4584
4585static int cur_wm_latency_show(struct seq_file *m, void *data)
4586{
4587 struct drm_device *dev = m->private;
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4589 const uint16_t *latencies;
4590
4591 if (INTEL_INFO(dev)->gen >= 9)
4592 latencies = dev_priv->wm.skl_latency;
4593 else
4594 latencies = to_i915(dev)->wm.cur_latency;
4595
4596 wm_latency_show(m, latencies);
4597
4598 return 0;
4599}
4600
4601static int pri_wm_latency_open(struct inode *inode, struct file *file)
4602{
4603 struct drm_device *dev = inode->i_private;
4604
4605 if (INTEL_INFO(dev)->gen < 5)
4606 return -ENODEV;
4607
4608 return single_open(file, pri_wm_latency_show, dev);
4609}
4610
4611static int spr_wm_latency_open(struct inode *inode, struct file *file)
4612{
4613 struct drm_device *dev = inode->i_private;
4614
4615 if (HAS_GMCH_DISPLAY(dev))
4616 return -ENODEV;
4617
4618 return single_open(file, spr_wm_latency_show, dev);
4619}
4620
4621static int cur_wm_latency_open(struct inode *inode, struct file *file)
4622{
4623 struct drm_device *dev = inode->i_private;
4624
4625 if (HAS_GMCH_DISPLAY(dev))
4626 return -ENODEV;
4627
4628 return single_open(file, cur_wm_latency_show, dev);
4629}
4630
4631static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4632 size_t len, loff_t *offp, uint16_t wm[8])
4633{
4634 struct seq_file *m = file->private_data;
4635 struct drm_device *dev = m->private;
4636 uint16_t new[8] = { 0 };
4637 int num_levels;
4638 int level;
4639 int ret;
4640 char tmp[32];
4641
4642 if (IS_CHERRYVIEW(dev))
4643 num_levels = 3;
4644 else if (IS_VALLEYVIEW(dev))
4645 num_levels = 1;
4646 else
4647 num_levels = ilk_wm_max_level(dev) + 1;
4648
4649 if (len >= sizeof(tmp))
4650 return -EINVAL;
4651
4652 if (copy_from_user(tmp, ubuf, len))
4653 return -EFAULT;
4654
4655 tmp[len] = '\0';
4656
4657 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4658 &new[0], &new[1], &new[2], &new[3],
4659 &new[4], &new[5], &new[6], &new[7]);
4660 if (ret != num_levels)
4661 return -EINVAL;
4662
4663 drm_modeset_lock_all(dev);
4664
4665 for (level = 0; level < num_levels; level++)
4666 wm[level] = new[level];
4667
4668 drm_modeset_unlock_all(dev);
4669
4670 return len;
4671}
4672
4673
4674static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4675 size_t len, loff_t *offp)
4676{
4677 struct seq_file *m = file->private_data;
4678 struct drm_device *dev = m->private;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 uint16_t *latencies;
4681
4682 if (INTEL_INFO(dev)->gen >= 9)
4683 latencies = dev_priv->wm.skl_latency;
4684 else
4685 latencies = to_i915(dev)->wm.pri_latency;
4686
4687 return wm_latency_write(file, ubuf, len, offp, latencies);
4688}
4689
4690static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4691 size_t len, loff_t *offp)
4692{
4693 struct seq_file *m = file->private_data;
4694 struct drm_device *dev = m->private;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 uint16_t *latencies;
4697
4698 if (INTEL_INFO(dev)->gen >= 9)
4699 latencies = dev_priv->wm.skl_latency;
4700 else
4701 latencies = to_i915(dev)->wm.spr_latency;
4702
4703 return wm_latency_write(file, ubuf, len, offp, latencies);
4704}
4705
4706static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4707 size_t len, loff_t *offp)
4708{
4709 struct seq_file *m = file->private_data;
4710 struct drm_device *dev = m->private;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 uint16_t *latencies;
4713
4714 if (INTEL_INFO(dev)->gen >= 9)
4715 latencies = dev_priv->wm.skl_latency;
4716 else
4717 latencies = to_i915(dev)->wm.cur_latency;
4718
4719 return wm_latency_write(file, ubuf, len, offp, latencies);
4720}
4721
4722static const struct file_operations i915_pri_wm_latency_fops = {
4723 .owner = THIS_MODULE,
4724 .open = pri_wm_latency_open,
4725 .read = seq_read,
4726 .llseek = seq_lseek,
4727 .release = single_release,
4728 .write = pri_wm_latency_write
4729};
4730
4731static const struct file_operations i915_spr_wm_latency_fops = {
4732 .owner = THIS_MODULE,
4733 .open = spr_wm_latency_open,
4734 .read = seq_read,
4735 .llseek = seq_lseek,
4736 .release = single_release,
4737 .write = spr_wm_latency_write
4738};
4739
4740static const struct file_operations i915_cur_wm_latency_fops = {
4741 .owner = THIS_MODULE,
4742 .open = cur_wm_latency_open,
4743 .read = seq_read,
4744 .llseek = seq_lseek,
4745 .release = single_release,
4746 .write = cur_wm_latency_write
4747};
4748
4749static int
4750i915_wedged_get(void *data, u64 *val)
4751{
4752 struct drm_device *dev = data;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754
4755 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4756
4757 return 0;
4758}
4759
4760static int
4761i915_wedged_set(void *data, u64 val)
4762{
4763 struct drm_device *dev = data;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765
4766 /*
4767 * There is no safeguard against this debugfs entry colliding
4768 * with the hangcheck calling same i915_handle_error() in
4769 * parallel, causing an explosion. For now we assume that the
4770 * test harness is responsible enough not to inject gpu hangs
4771 * while it is writing to 'i915_wedged'
4772 */
4773
4774 if (i915_reset_in_progress(&dev_priv->gpu_error))
4775 return -EAGAIN;
4776
4777 intel_runtime_pm_get(dev_priv);
4778
4779 i915_handle_error(dev_priv, val,
4780 "Manually setting wedged to %llu", val);
4781
4782 intel_runtime_pm_put(dev_priv);
4783
4784 return 0;
4785}
4786
4787DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4788 i915_wedged_get, i915_wedged_set,
4789 "%llu\n");
4790
4791static int
4792i915_ring_stop_get(void *data, u64 *val)
4793{
4794 struct drm_device *dev = data;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796
4797 *val = dev_priv->gpu_error.stop_rings;
4798
4799 return 0;
4800}
4801
4802static int
4803i915_ring_stop_set(void *data, u64 val)
4804{
4805 struct drm_device *dev = data;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 int ret;
4808
4809 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4810
4811 ret = mutex_lock_interruptible(&dev->struct_mutex);
4812 if (ret)
4813 return ret;
4814
4815 dev_priv->gpu_error.stop_rings = val;
4816 mutex_unlock(&dev->struct_mutex);
4817
4818 return 0;
4819}
4820
4821DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4822 i915_ring_stop_get, i915_ring_stop_set,
4823 "0x%08llx\n");
4824
4825static int
4826i915_ring_missed_irq_get(void *data, u64 *val)
4827{
4828 struct drm_device *dev = data;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830
4831 *val = dev_priv->gpu_error.missed_irq_rings;
4832 return 0;
4833}
4834
4835static int
4836i915_ring_missed_irq_set(void *data, u64 val)
4837{
4838 struct drm_device *dev = data;
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4840 int ret;
4841
4842 /* Lock against concurrent debugfs callers */
4843 ret = mutex_lock_interruptible(&dev->struct_mutex);
4844 if (ret)
4845 return ret;
4846 dev_priv->gpu_error.missed_irq_rings = val;
4847 mutex_unlock(&dev->struct_mutex);
4848
4849 return 0;
4850}
4851
4852DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4853 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4854 "0x%08llx\n");
4855
4856static int
4857i915_ring_test_irq_get(void *data, u64 *val)
4858{
4859 struct drm_device *dev = data;
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861
4862 *val = dev_priv->gpu_error.test_irq_rings;
4863
4864 return 0;
4865}
4866
4867static int
4868i915_ring_test_irq_set(void *data, u64 val)
4869{
4870 struct drm_device *dev = data;
4871 struct drm_i915_private *dev_priv = dev->dev_private;
4872 int ret;
4873
4874 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4875
4876 /* Lock against concurrent debugfs callers */
4877 ret = mutex_lock_interruptible(&dev->struct_mutex);
4878 if (ret)
4879 return ret;
4880
4881 dev_priv->gpu_error.test_irq_rings = val;
4882 mutex_unlock(&dev->struct_mutex);
4883
4884 return 0;
4885}
4886
4887DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4888 i915_ring_test_irq_get, i915_ring_test_irq_set,
4889 "0x%08llx\n");
4890
4891#define DROP_UNBOUND 0x1
4892#define DROP_BOUND 0x2
4893#define DROP_RETIRE 0x4
4894#define DROP_ACTIVE 0x8
4895#define DROP_ALL (DROP_UNBOUND | \
4896 DROP_BOUND | \
4897 DROP_RETIRE | \
4898 DROP_ACTIVE)
4899static int
4900i915_drop_caches_get(void *data, u64 *val)
4901{
4902 *val = DROP_ALL;
4903
4904 return 0;
4905}
4906
4907static int
4908i915_drop_caches_set(void *data, u64 val)
4909{
4910 struct drm_device *dev = data;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 int ret;
4913
4914 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4915
4916 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4917 * on ioctls on -EAGAIN. */
4918 ret = mutex_lock_interruptible(&dev->struct_mutex);
4919 if (ret)
4920 return ret;
4921
4922 if (val & DROP_ACTIVE) {
4923 ret = i915_gpu_idle(dev);
4924 if (ret)
4925 goto unlock;
4926 }
4927
4928 if (val & (DROP_RETIRE | DROP_ACTIVE))
4929 i915_gem_retire_requests(dev_priv);
4930
4931 if (val & DROP_BOUND)
4932 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4933
4934 if (val & DROP_UNBOUND)
4935 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4936
4937unlock:
4938 mutex_unlock(&dev->struct_mutex);
4939
4940 return ret;
4941}
4942
4943DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4944 i915_drop_caches_get, i915_drop_caches_set,
4945 "0x%08llx\n");
4946
4947static int
4948i915_max_freq_get(void *data, u64 *val)
4949{
4950 struct drm_device *dev = data;
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952 int ret;
4953
4954 if (INTEL_INFO(dev)->gen < 6)
4955 return -ENODEV;
4956
4957 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4958
4959 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4960 if (ret)
4961 return ret;
4962
4963 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4964 mutex_unlock(&dev_priv->rps.hw_lock);
4965
4966 return 0;
4967}
4968
4969static int
4970i915_max_freq_set(void *data, u64 val)
4971{
4972 struct drm_device *dev = data;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 u32 hw_max, hw_min;
4975 int ret;
4976
4977 if (INTEL_INFO(dev)->gen < 6)
4978 return -ENODEV;
4979
4980 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4981
4982 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4983
4984 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4985 if (ret)
4986 return ret;
4987
4988 /*
4989 * Turbo will still be enabled, but won't go above the set value.
4990 */
4991 val = intel_freq_opcode(dev_priv, val);
4992
4993 hw_max = dev_priv->rps.max_freq;
4994 hw_min = dev_priv->rps.min_freq;
4995
4996 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4997 mutex_unlock(&dev_priv->rps.hw_lock);
4998 return -EINVAL;
4999 }
5000
5001 dev_priv->rps.max_freq_softlimit = val;
5002
5003 intel_set_rps(dev_priv, val);
5004
5005 mutex_unlock(&dev_priv->rps.hw_lock);
5006
5007 return 0;
5008}
5009
5010DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5011 i915_max_freq_get, i915_max_freq_set,
5012 "%llu\n");
5013
5014static int
5015i915_min_freq_get(void *data, u64 *val)
5016{
5017 struct drm_device *dev = data;
5018 struct drm_i915_private *dev_priv = dev->dev_private;
5019 int ret;
5020
5021 if (INTEL_INFO(dev)->gen < 6)
5022 return -ENODEV;
5023
5024 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5025
5026 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5027 if (ret)
5028 return ret;
5029
5030 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5031 mutex_unlock(&dev_priv->rps.hw_lock);
5032
5033 return 0;
5034}
5035
5036static int
5037i915_min_freq_set(void *data, u64 val)
5038{
5039 struct drm_device *dev = data;
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041 u32 hw_max, hw_min;
5042 int ret;
5043
5044 if (INTEL_INFO(dev)->gen < 6)
5045 return -ENODEV;
5046
5047 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5048
5049 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5050
5051 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5052 if (ret)
5053 return ret;
5054
5055 /*
5056 * Turbo will still be enabled, but won't go below the set value.
5057 */
5058 val = intel_freq_opcode(dev_priv, val);
5059
5060 hw_max = dev_priv->rps.max_freq;
5061 hw_min = dev_priv->rps.min_freq;
5062
5063 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5064 mutex_unlock(&dev_priv->rps.hw_lock);
5065 return -EINVAL;
5066 }
5067
5068 dev_priv->rps.min_freq_softlimit = val;
5069
5070 intel_set_rps(dev_priv, val);
5071
5072 mutex_unlock(&dev_priv->rps.hw_lock);
5073
5074 return 0;
5075}
5076
5077DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5078 i915_min_freq_get, i915_min_freq_set,
5079 "%llu\n");
5080
5081static int
5082i915_cache_sharing_get(void *data, u64 *val)
5083{
5084 struct drm_device *dev = data;
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 u32 snpcr;
5087 int ret;
5088
5089 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5090 return -ENODEV;
5091
5092 ret = mutex_lock_interruptible(&dev->struct_mutex);
5093 if (ret)
5094 return ret;
5095 intel_runtime_pm_get(dev_priv);
5096
5097 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5098
5099 intel_runtime_pm_put(dev_priv);
5100 mutex_unlock(&dev_priv->dev->struct_mutex);
5101
5102 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5103
5104 return 0;
5105}
5106
5107static int
5108i915_cache_sharing_set(void *data, u64 val)
5109{
5110 struct drm_device *dev = data;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 u32 snpcr;
5113
5114 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5115 return -ENODEV;
5116
5117 if (val > 3)
5118 return -EINVAL;
5119
5120 intel_runtime_pm_get(dev_priv);
5121 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5122
5123 /* Update the cache sharing policy here as well */
5124 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5125 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5126 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5127 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5128
5129 intel_runtime_pm_put(dev_priv);
5130 return 0;
5131}
5132
5133DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5134 i915_cache_sharing_get, i915_cache_sharing_set,
5135 "%llu\n");
5136
5137struct sseu_dev_status {
5138 unsigned int slice_total;
5139 unsigned int subslice_total;
5140 unsigned int subslice_per_slice;
5141 unsigned int eu_total;
5142 unsigned int eu_per_subslice;
5143};
5144
5145static void cherryview_sseu_device_status(struct drm_device *dev,
5146 struct sseu_dev_status *stat)
5147{
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5149 int ss_max = 2;
5150 int ss;
5151 u32 sig1[ss_max], sig2[ss_max];
5152
5153 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5154 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5155 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5156 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5157
5158 for (ss = 0; ss < ss_max; ss++) {
5159 unsigned int eu_cnt;
5160
5161 if (sig1[ss] & CHV_SS_PG_ENABLE)
5162 /* skip disabled subslice */
5163 continue;
5164
5165 stat->slice_total = 1;
5166 stat->subslice_per_slice++;
5167 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5168 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5169 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5170 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5171 stat->eu_total += eu_cnt;
5172 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5173 }
5174 stat->subslice_total = stat->subslice_per_slice;
5175}
5176
5177static void gen9_sseu_device_status(struct drm_device *dev,
5178 struct sseu_dev_status *stat)
5179{
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 int s_max = 3, ss_max = 4;
5182 int s, ss;
5183 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5184
5185 /* BXT has a single slice and at most 3 subslices. */
5186 if (IS_BROXTON(dev)) {
5187 s_max = 1;
5188 ss_max = 3;
5189 }
5190
5191 for (s = 0; s < s_max; s++) {
5192 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5193 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5194 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5195 }
5196
5197 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5198 GEN9_PGCTL_SSA_EU19_ACK |
5199 GEN9_PGCTL_SSA_EU210_ACK |
5200 GEN9_PGCTL_SSA_EU311_ACK;
5201 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5202 GEN9_PGCTL_SSB_EU19_ACK |
5203 GEN9_PGCTL_SSB_EU210_ACK |
5204 GEN9_PGCTL_SSB_EU311_ACK;
5205
5206 for (s = 0; s < s_max; s++) {
5207 unsigned int ss_cnt = 0;
5208
5209 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5210 /* skip disabled slice */
5211 continue;
5212
5213 stat->slice_total++;
5214
5215 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5216 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5217
5218 for (ss = 0; ss < ss_max; ss++) {
5219 unsigned int eu_cnt;
5220
5221 if (IS_BROXTON(dev) &&
5222 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5223 /* skip disabled subslice */
5224 continue;
5225
5226 if (IS_BROXTON(dev))
5227 ss_cnt++;
5228
5229 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5230 eu_mask[ss%2]);
5231 stat->eu_total += eu_cnt;
5232 stat->eu_per_subslice = max(stat->eu_per_subslice,
5233 eu_cnt);
5234 }
5235
5236 stat->subslice_total += ss_cnt;
5237 stat->subslice_per_slice = max(stat->subslice_per_slice,
5238 ss_cnt);
5239 }
5240}
5241
5242static void broadwell_sseu_device_status(struct drm_device *dev,
5243 struct sseu_dev_status *stat)
5244{
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 int s;
5247 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5248
5249 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5250
5251 if (stat->slice_total) {
5252 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5253 stat->subslice_total = stat->slice_total *
5254 stat->subslice_per_slice;
5255 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5256 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5257
5258 /* subtract fused off EU(s) from enabled slice(s) */
5259 for (s = 0; s < stat->slice_total; s++) {
5260 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5261
5262 stat->eu_total -= hweight8(subslice_7eu);
5263 }
5264 }
5265}
5266
5267static int i915_sseu_status(struct seq_file *m, void *unused)
5268{
5269 struct drm_info_node *node = (struct drm_info_node *) m->private;
5270 struct drm_device *dev = node->minor->dev;
5271 struct sseu_dev_status stat;
5272
5273 if (INTEL_INFO(dev)->gen < 8)
5274 return -ENODEV;
5275
5276 seq_puts(m, "SSEU Device Info\n");
5277 seq_printf(m, " Available Slice Total: %u\n",
5278 INTEL_INFO(dev)->slice_total);
5279 seq_printf(m, " Available Subslice Total: %u\n",
5280 INTEL_INFO(dev)->subslice_total);
5281 seq_printf(m, " Available Subslice Per Slice: %u\n",
5282 INTEL_INFO(dev)->subslice_per_slice);
5283 seq_printf(m, " Available EU Total: %u\n",
5284 INTEL_INFO(dev)->eu_total);
5285 seq_printf(m, " Available EU Per Subslice: %u\n",
5286 INTEL_INFO(dev)->eu_per_subslice);
5287 seq_printf(m, " Has Slice Power Gating: %s\n",
5288 yesno(INTEL_INFO(dev)->has_slice_pg));
5289 seq_printf(m, " Has Subslice Power Gating: %s\n",
5290 yesno(INTEL_INFO(dev)->has_subslice_pg));
5291 seq_printf(m, " Has EU Power Gating: %s\n",
5292 yesno(INTEL_INFO(dev)->has_eu_pg));
5293
5294 seq_puts(m, "SSEU Device Status\n");
5295 memset(&stat, 0, sizeof(stat));
5296 if (IS_CHERRYVIEW(dev)) {
5297 cherryview_sseu_device_status(dev, &stat);
5298 } else if (IS_BROADWELL(dev)) {
5299 broadwell_sseu_device_status(dev, &stat);
5300 } else if (INTEL_INFO(dev)->gen >= 9) {
5301 gen9_sseu_device_status(dev, &stat);
5302 }
5303 seq_printf(m, " Enabled Slice Total: %u\n",
5304 stat.slice_total);
5305 seq_printf(m, " Enabled Subslice Total: %u\n",
5306 stat.subslice_total);
5307 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5308 stat.subslice_per_slice);
5309 seq_printf(m, " Enabled EU Total: %u\n",
5310 stat.eu_total);
5311 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5312 stat.eu_per_subslice);
5313
5314 return 0;
5315}
5316
5317static int i915_forcewake_open(struct inode *inode, struct file *file)
5318{
5319 struct drm_device *dev = inode->i_private;
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321
5322 if (INTEL_INFO(dev)->gen < 6)
5323 return 0;
5324
5325 intel_runtime_pm_get(dev_priv);
5326 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5327
5328 return 0;
5329}
5330
5331static int i915_forcewake_release(struct inode *inode, struct file *file)
5332{
5333 struct drm_device *dev = inode->i_private;
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335
5336 if (INTEL_INFO(dev)->gen < 6)
5337 return 0;
5338
5339 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5340 intel_runtime_pm_put(dev_priv);
5341
5342 return 0;
5343}
5344
5345static const struct file_operations i915_forcewake_fops = {
5346 .owner = THIS_MODULE,
5347 .open = i915_forcewake_open,
5348 .release = i915_forcewake_release,
5349};
5350
5351static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5352{
5353 struct drm_device *dev = minor->dev;
5354 struct dentry *ent;
5355
5356 ent = debugfs_create_file("i915_forcewake_user",
5357 S_IRUSR,
5358 root, dev,
5359 &i915_forcewake_fops);
5360 if (!ent)
5361 return -ENOMEM;
5362
5363 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5364}
5365
5366static int i915_debugfs_create(struct dentry *root,
5367 struct drm_minor *minor,
5368 const char *name,
5369 const struct file_operations *fops)
5370{
5371 struct drm_device *dev = minor->dev;
5372 struct dentry *ent;
5373
5374 ent = debugfs_create_file(name,
5375 S_IRUGO | S_IWUSR,
5376 root, dev,
5377 fops);
5378 if (!ent)
5379 return -ENOMEM;
5380
5381 return drm_add_fake_info_node(minor, ent, fops);
5382}
5383
5384static const struct drm_info_list i915_debugfs_list[] = {
5385 {"i915_capabilities", i915_capabilities, 0},
5386 {"i915_gem_objects", i915_gem_object_info, 0},
5387 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5388 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5389 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5390 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5391 {"i915_gem_stolen", i915_gem_stolen_list_info },
5392 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5393 {"i915_gem_request", i915_gem_request_info, 0},
5394 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5395 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5396 {"i915_gem_interrupt", i915_interrupt_info, 0},
5397 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5398 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5399 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5400 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5401 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5402 {"i915_guc_info", i915_guc_info, 0},
5403 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5404 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5405 {"i915_frequency_info", i915_frequency_info, 0},
5406 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5407 {"i915_drpc_info", i915_drpc_info, 0},
5408 {"i915_emon_status", i915_emon_status, 0},
5409 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5410 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5411 {"i915_fbc_status", i915_fbc_status, 0},
5412 {"i915_ips_status", i915_ips_status, 0},
5413 {"i915_sr_status", i915_sr_status, 0},
5414 {"i915_opregion", i915_opregion, 0},
5415 {"i915_vbt", i915_vbt, 0},
5416 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5417 {"i915_context_status", i915_context_status, 0},
5418 {"i915_dump_lrc", i915_dump_lrc, 0},
5419 {"i915_execlists", i915_execlists, 0},
5420 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5421 {"i915_swizzle_info", i915_swizzle_info, 0},
5422 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5423 {"i915_llc", i915_llc, 0},
5424 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5425 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5426 {"i915_energy_uJ", i915_energy_uJ, 0},
5427 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5428 {"i915_power_domain_info", i915_power_domain_info, 0},
5429 {"i915_dmc_info", i915_dmc_info, 0},
5430 {"i915_display_info", i915_display_info, 0},
5431 {"i915_semaphore_status", i915_semaphore_status, 0},
5432 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5433 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5434 {"i915_wa_registers", i915_wa_registers, 0},
5435 {"i915_ddb_info", i915_ddb_info, 0},
5436 {"i915_sseu_status", i915_sseu_status, 0},
5437 {"i915_drrs_status", i915_drrs_status, 0},
5438 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5439};
5440#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5441
5442static const struct i915_debugfs_files {
5443 const char *name;
5444 const struct file_operations *fops;
5445} i915_debugfs_files[] = {
5446 {"i915_wedged", &i915_wedged_fops},
5447 {"i915_max_freq", &i915_max_freq_fops},
5448 {"i915_min_freq", &i915_min_freq_fops},
5449 {"i915_cache_sharing", &i915_cache_sharing_fops},
5450 {"i915_ring_stop", &i915_ring_stop_fops},
5451 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5452 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5453 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5454 {"i915_error_state", &i915_error_state_fops},
5455 {"i915_next_seqno", &i915_next_seqno_fops},
5456 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5457 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5458 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5459 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5460 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5461 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5462 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5463 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5464};
5465
5466void intel_display_crc_init(struct drm_device *dev)
5467{
5468 struct drm_i915_private *dev_priv = dev->dev_private;
5469 enum pipe pipe;
5470
5471 for_each_pipe(dev_priv, pipe) {
5472 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5473
5474 pipe_crc->opened = false;
5475 spin_lock_init(&pipe_crc->lock);
5476 init_waitqueue_head(&pipe_crc->wq);
5477 }
5478}
5479
5480int i915_debugfs_init(struct drm_minor *minor)
5481{
5482 int ret, i;
5483
5484 ret = i915_forcewake_create(minor->debugfs_root, minor);
5485 if (ret)
5486 return ret;
5487
5488 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5489 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5490 if (ret)
5491 return ret;
5492 }
5493
5494 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5495 ret = i915_debugfs_create(minor->debugfs_root, minor,
5496 i915_debugfs_files[i].name,
5497 i915_debugfs_files[i].fops);
5498 if (ret)
5499 return ret;
5500 }
5501
5502 return drm_debugfs_create_files(i915_debugfs_list,
5503 I915_DEBUGFS_ENTRIES,
5504 minor->debugfs_root, minor);
5505}
5506
5507void i915_debugfs_cleanup(struct drm_minor *minor)
5508{
5509 int i;
5510
5511 drm_debugfs_remove_files(i915_debugfs_list,
5512 I915_DEBUGFS_ENTRIES, minor);
5513
5514 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5515 1, minor);
5516
5517 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5518 struct drm_info_list *info_list =
5519 (struct drm_info_list *)&i915_pipe_crc_data[i];
5520
5521 drm_debugfs_remove_files(info_list, 1, minor);
5522 }
5523
5524 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5525 struct drm_info_list *info_list =
5526 (struct drm_info_list *) i915_debugfs_files[i].fops;
5527
5528 drm_debugfs_remove_files(info_list, 1, minor);
5529 }
5530}
5531
5532struct dpcd_block {
5533 /* DPCD dump start address. */
5534 unsigned int offset;
5535 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5536 unsigned int end;
5537 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5538 size_t size;
5539 /* Only valid for eDP. */
5540 bool edp;
5541};
5542
5543static const struct dpcd_block i915_dpcd_debug[] = {
5544 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5545 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5546 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5547 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5548 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5549 { .offset = DP_SET_POWER },
5550 { .offset = DP_EDP_DPCD_REV },
5551 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5552 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5553 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5554};
5555
5556static int i915_dpcd_show(struct seq_file *m, void *data)
5557{
5558 struct drm_connector *connector = m->private;
5559 struct intel_dp *intel_dp =
5560 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5561 uint8_t buf[16];
5562 ssize_t err;
5563 int i;
5564
5565 if (connector->status != connector_status_connected)
5566 return -ENODEV;
5567
5568 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5569 const struct dpcd_block *b = &i915_dpcd_debug[i];
5570 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5571
5572 if (b->edp &&
5573 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5574 continue;
5575
5576 /* low tech for now */
5577 if (WARN_ON(size > sizeof(buf)))
5578 continue;
5579
5580 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5581 if (err <= 0) {
5582 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5583 size, b->offset, err);
5584 continue;
5585 }
5586
5587 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5588 }
5589
5590 return 0;
5591}
5592
5593static int i915_dpcd_open(struct inode *inode, struct file *file)
5594{
5595 return single_open(file, i915_dpcd_show, inode->i_private);
5596}
5597
5598static const struct file_operations i915_dpcd_fops = {
5599 .owner = THIS_MODULE,
5600 .open = i915_dpcd_open,
5601 .read = seq_read,
5602 .llseek = seq_lseek,
5603 .release = single_release,
5604};
5605
5606/**
5607 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5608 * @connector: pointer to a registered drm_connector
5609 *
5610 * Cleanup will be done by drm_connector_unregister() through a call to
5611 * drm_debugfs_connector_remove().
5612 *
5613 * Returns 0 on success, negative error codes on error.
5614 */
5615int i915_debugfs_connector_add(struct drm_connector *connector)
5616{
5617 struct dentry *root = connector->debugfs_entry;
5618
5619 /* The connector must have been registered beforehands. */
5620 if (!root)
5621 return -ENODEV;
5622
5623 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5624 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5625 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5626 &i915_dpcd_fops);
5627
5628 return 0;
5629}
Linux kernel - Deliverables
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