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drm/i915: Ignore stuck requests when considering hangs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/circ_buf.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/slab.h>
34#include <linux/export.h>
35#include <linux/list_sort.h>
36#include <asm/msr-index.h>
37#include <drm/drmP.h>
38#include "intel_drv.h"
39#include "intel_ringbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
44{
45 return to_i915(node->minor->dev);
46}
47
48/* As the drm_debugfs_init() routines are called before dev->dev_private is
49 * allocated we need to hook into the minor for release. */
50static int
51drm_add_fake_info_node(struct drm_minor *minor,
52 struct dentry *ent,
53 const void *key)
54{
55 struct drm_info_node *node;
56
57 node = kmalloc(sizeof(*node), GFP_KERNEL);
58 if (node == NULL) {
59 debugfs_remove(ent);
60 return -ENOMEM;
61 }
62
63 node->minor = minor;
64 node->dent = ent;
65 node->info_ent = (void *)key;
66
67 mutex_lock(&minor->debugfs_lock);
68 list_add(&node->list, &minor->debugfs_list);
69 mutex_unlock(&minor->debugfs_lock);
70
71 return 0;
72}
73
74static int i915_capabilities(struct seq_file *m, void *data)
75{
76 struct drm_i915_private *dev_priv = node_to_i915(m->private);
77 const struct intel_device_info *info = INTEL_INFO(dev_priv);
78
79 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
80 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
81#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
82#define SEP_SEMICOLON ;
83 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
84#undef PRINT_FLAG
85#undef SEP_SEMICOLON
86
87 return 0;
88}
89
90static char get_active_flag(struct drm_i915_gem_object *obj)
91{
92 return i915_gem_object_is_active(obj) ? '*' : ' ';
93}
94
95static char get_pin_flag(struct drm_i915_gem_object *obj)
96{
97 return obj->pin_display ? 'p' : ' ';
98}
99
100static char get_tiling_flag(struct drm_i915_gem_object *obj)
101{
102 switch (i915_gem_object_get_tiling(obj)) {
103 default:
104 case I915_TILING_NONE: return ' ';
105 case I915_TILING_X: return 'X';
106 case I915_TILING_Y: return 'Y';
107 }
108}
109
110static char get_global_flag(struct drm_i915_gem_object *obj)
111{
112 return i915_gem_object_to_ggtt(obj, NULL) ? 'g' : ' ';
113}
114
115static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
116{
117 return obj->mapping ? 'M' : ' ';
118}
119
120static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
121{
122 u64 size = 0;
123 struct i915_vma *vma;
124
125 list_for_each_entry(vma, &obj->vma_list, obj_link) {
126 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
127 size += vma->node.size;
128 }
129
130 return size;
131}
132
133static void
134describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
135{
136 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
137 struct intel_engine_cs *engine;
138 struct i915_vma *vma;
139 unsigned int frontbuffer_bits;
140 int pin_count = 0;
141 enum intel_engine_id id;
142
143 lockdep_assert_held(&obj->base.dev->struct_mutex);
144
145 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
146 &obj->base,
147 get_active_flag(obj),
148 get_pin_flag(obj),
149 get_tiling_flag(obj),
150 get_global_flag(obj),
151 get_pin_mapped_flag(obj),
152 obj->base.size / 1024,
153 obj->base.read_domains,
154 obj->base.write_domain);
155 for_each_engine_id(engine, dev_priv, id)
156 seq_printf(m, "%x ",
157 i915_gem_active_get_seqno(&obj->last_read[id],
158 &obj->base.dev->struct_mutex));
159 seq_printf(m, "] %x %s%s%s",
160 i915_gem_active_get_seqno(&obj->last_write,
161 &obj->base.dev->struct_mutex),
162 i915_cache_level_str(dev_priv, obj->cache_level),
163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
168 if (i915_vma_is_pinned(vma))
169 pin_count++;
170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
172 if (obj->pin_display)
173 seq_printf(m, " (display)");
174 list_for_each_entry(vma, &obj->vma_list, obj_link) {
175 if (!drm_mm_node_allocated(&vma->node))
176 continue;
177
178 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
179 i915_vma_is_ggtt(vma) ? "g" : "pp",
180 vma->node.start, vma->node.size);
181 if (i915_vma_is_ggtt(vma))
182 seq_printf(m, ", type: %u", vma->ggtt_view.type);
183 if (vma->fence)
184 seq_printf(m, " , fence: %d%s",
185 vma->fence->id,
186 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
187 seq_puts(m, ")");
188 }
189 if (obj->stolen)
190 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
191 if (obj->pin_display || obj->fault_mappable) {
192 char s[3], *t = s;
193 if (obj->pin_display)
194 *t++ = 'p';
195 if (obj->fault_mappable)
196 *t++ = 'f';
197 *t = '\0';
198 seq_printf(m, " (%s mappable)", s);
199 }
200
201 engine = i915_gem_active_get_engine(&obj->last_write,
202 &dev_priv->drm.struct_mutex);
203 if (engine)
204 seq_printf(m, " (%s)", engine->name);
205
206 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
207 if (frontbuffer_bits)
208 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
209}
210
211static int obj_rank_by_stolen(void *priv,
212 struct list_head *A, struct list_head *B)
213{
214 struct drm_i915_gem_object *a =
215 container_of(A, struct drm_i915_gem_object, obj_exec_link);
216 struct drm_i915_gem_object *b =
217 container_of(B, struct drm_i915_gem_object, obj_exec_link);
218
219 if (a->stolen->start < b->stolen->start)
220 return -1;
221 if (a->stolen->start > b->stolen->start)
222 return 1;
223 return 0;
224}
225
226static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
227{
228 struct drm_i915_private *dev_priv = node_to_i915(m->private);
229 struct drm_device *dev = &dev_priv->drm;
230 struct drm_i915_gem_object *obj;
231 u64 total_obj_size, total_gtt_size;
232 LIST_HEAD(stolen);
233 int count, ret;
234
235 ret = mutex_lock_interruptible(&dev->struct_mutex);
236 if (ret)
237 return ret;
238
239 total_obj_size = total_gtt_size = count = 0;
240 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
241 if (obj->stolen == NULL)
242 continue;
243
244 list_add(&obj->obj_exec_link, &stolen);
245
246 total_obj_size += obj->base.size;
247 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
248 count++;
249 }
250 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
251 if (obj->stolen == NULL)
252 continue;
253
254 list_add(&obj->obj_exec_link, &stolen);
255
256 total_obj_size += obj->base.size;
257 count++;
258 }
259 list_sort(NULL, &stolen, obj_rank_by_stolen);
260 seq_puts(m, "Stolen:\n");
261 while (!list_empty(&stolen)) {
262 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
263 seq_puts(m, " ");
264 describe_obj(m, obj);
265 seq_putc(m, '\n');
266 list_del_init(&obj->obj_exec_link);
267 }
268 mutex_unlock(&dev->struct_mutex);
269
270 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
271 count, total_obj_size, total_gtt_size);
272 return 0;
273}
274
275struct file_stats {
276 struct drm_i915_file_private *file_priv;
277 unsigned long count;
278 u64 total, unbound;
279 u64 global, shared;
280 u64 active, inactive;
281};
282
283static int per_file_stats(int id, void *ptr, void *data)
284{
285 struct drm_i915_gem_object *obj = ptr;
286 struct file_stats *stats = data;
287 struct i915_vma *vma;
288
289 stats->count++;
290 stats->total += obj->base.size;
291 if (!obj->bind_count)
292 stats->unbound += obj->base.size;
293 if (obj->base.name || obj->base.dma_buf)
294 stats->shared += obj->base.size;
295
296 list_for_each_entry(vma, &obj->vma_list, obj_link) {
297 if (!drm_mm_node_allocated(&vma->node))
298 continue;
299
300 if (i915_vma_is_ggtt(vma)) {
301 stats->global += vma->node.size;
302 } else {
303 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
304
305 if (ppgtt->base.file != stats->file_priv)
306 continue;
307 }
308
309 if (i915_vma_is_active(vma))
310 stats->active += vma->node.size;
311 else
312 stats->inactive += vma->node.size;
313 }
314
315 return 0;
316}
317
318#define print_file_stats(m, name, stats) do { \
319 if (stats.count) \
320 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
321 name, \
322 stats.count, \
323 stats.total, \
324 stats.active, \
325 stats.inactive, \
326 stats.global, \
327 stats.shared, \
328 stats.unbound); \
329} while (0)
330
331static void print_batch_pool_stats(struct seq_file *m,
332 struct drm_i915_private *dev_priv)
333{
334 struct drm_i915_gem_object *obj;
335 struct file_stats stats;
336 struct intel_engine_cs *engine;
337 int j;
338
339 memset(&stats, 0, sizeof(stats));
340
341 for_each_engine(engine, dev_priv) {
342 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
343 list_for_each_entry(obj,
344 &engine->batch_pool.cache_list[j],
345 batch_pool_link)
346 per_file_stats(0, obj, &stats);
347 }
348 }
349
350 print_file_stats(m, "[k]batch pool", stats);
351}
352
353static int per_file_ctx_stats(int id, void *ptr, void *data)
354{
355 struct i915_gem_context *ctx = ptr;
356 int n;
357
358 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
359 if (ctx->engine[n].state)
360 per_file_stats(0, ctx->engine[n].state->obj, data);
361 if (ctx->engine[n].ring)
362 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
363 }
364
365 return 0;
366}
367
368static void print_context_stats(struct seq_file *m,
369 struct drm_i915_private *dev_priv)
370{
371 struct drm_device *dev = &dev_priv->drm;
372 struct file_stats stats;
373 struct drm_file *file;
374
375 memset(&stats, 0, sizeof(stats));
376
377 mutex_lock(&dev->struct_mutex);
378 if (dev_priv->kernel_context)
379 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
380
381 list_for_each_entry(file, &dev->filelist, lhead) {
382 struct drm_i915_file_private *fpriv = file->driver_priv;
383 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
384 }
385 mutex_unlock(&dev->struct_mutex);
386
387 print_file_stats(m, "[k]contexts", stats);
388}
389
390static int i915_gem_object_info(struct seq_file *m, void *data)
391{
392 struct drm_i915_private *dev_priv = node_to_i915(m->private);
393 struct drm_device *dev = &dev_priv->drm;
394 struct i915_ggtt *ggtt = &dev_priv->ggtt;
395 u32 count, mapped_count, purgeable_count, dpy_count;
396 u64 size, mapped_size, purgeable_size, dpy_size;
397 struct drm_i915_gem_object *obj;
398 struct drm_file *file;
399 int ret;
400
401 ret = mutex_lock_interruptible(&dev->struct_mutex);
402 if (ret)
403 return ret;
404
405 seq_printf(m, "%u objects, %zu bytes\n",
406 dev_priv->mm.object_count,
407 dev_priv->mm.object_memory);
408
409 size = count = 0;
410 mapped_size = mapped_count = 0;
411 purgeable_size = purgeable_count = 0;
412 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
413 size += obj->base.size;
414 ++count;
415
416 if (obj->madv == I915_MADV_DONTNEED) {
417 purgeable_size += obj->base.size;
418 ++purgeable_count;
419 }
420
421 if (obj->mapping) {
422 mapped_count++;
423 mapped_size += obj->base.size;
424 }
425 }
426 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
427
428 size = count = dpy_size = dpy_count = 0;
429 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
430 size += obj->base.size;
431 ++count;
432
433 if (obj->pin_display) {
434 dpy_size += obj->base.size;
435 ++dpy_count;
436 }
437
438 if (obj->madv == I915_MADV_DONTNEED) {
439 purgeable_size += obj->base.size;
440 ++purgeable_count;
441 }
442
443 if (obj->mapping) {
444 mapped_count++;
445 mapped_size += obj->base.size;
446 }
447 }
448 seq_printf(m, "%u bound objects, %llu bytes\n",
449 count, size);
450 seq_printf(m, "%u purgeable objects, %llu bytes\n",
451 purgeable_count, purgeable_size);
452 seq_printf(m, "%u mapped objects, %llu bytes\n",
453 mapped_count, mapped_size);
454 seq_printf(m, "%u display objects (pinned), %llu bytes\n",
455 dpy_count, dpy_size);
456
457 seq_printf(m, "%llu [%llu] gtt total\n",
458 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
459
460 seq_putc(m, '\n');
461 print_batch_pool_stats(m, dev_priv);
462 mutex_unlock(&dev->struct_mutex);
463
464 mutex_lock(&dev->filelist_mutex);
465 print_context_stats(m, dev_priv);
466 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
467 struct file_stats stats;
468 struct drm_i915_file_private *file_priv = file->driver_priv;
469 struct drm_i915_gem_request *request;
470 struct task_struct *task;
471
472 memset(&stats, 0, sizeof(stats));
473 stats.file_priv = file->driver_priv;
474 spin_lock(&file->table_lock);
475 idr_for_each(&file->object_idr, per_file_stats, &stats);
476 spin_unlock(&file->table_lock);
477 /*
478 * Although we have a valid reference on file->pid, that does
479 * not guarantee that the task_struct who called get_pid() is
480 * still alive (e.g. get_pid(current) => fork() => exit()).
481 * Therefore, we need to protect this ->comm access using RCU.
482 */
483 mutex_lock(&dev->struct_mutex);
484 request = list_first_entry_or_null(&file_priv->mm.request_list,
485 struct drm_i915_gem_request,
486 client_list);
487 rcu_read_lock();
488 task = pid_task(request && request->ctx->pid ?
489 request->ctx->pid : file->pid,
490 PIDTYPE_PID);
491 print_file_stats(m, task ? task->comm : "<unknown>", stats);
492 rcu_read_unlock();
493 mutex_unlock(&dev->struct_mutex);
494 }
495 mutex_unlock(&dev->filelist_mutex);
496
497 return 0;
498}
499
500static int i915_gem_gtt_info(struct seq_file *m, void *data)
501{
502 struct drm_info_node *node = m->private;
503 struct drm_i915_private *dev_priv = node_to_i915(node);
504 struct drm_device *dev = &dev_priv->drm;
505 bool show_pin_display_only = !!node->info_ent->data;
506 struct drm_i915_gem_object *obj;
507 u64 total_obj_size, total_gtt_size;
508 int count, ret;
509
510 ret = mutex_lock_interruptible(&dev->struct_mutex);
511 if (ret)
512 return ret;
513
514 total_obj_size = total_gtt_size = count = 0;
515 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
516 if (show_pin_display_only && !obj->pin_display)
517 continue;
518
519 seq_puts(m, " ");
520 describe_obj(m, obj);
521 seq_putc(m, '\n');
522 total_obj_size += obj->base.size;
523 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
524 count++;
525 }
526
527 mutex_unlock(&dev->struct_mutex);
528
529 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
530 count, total_obj_size, total_gtt_size);
531
532 return 0;
533}
534
535static int i915_gem_pageflip_info(struct seq_file *m, void *data)
536{
537 struct drm_i915_private *dev_priv = node_to_i915(m->private);
538 struct drm_device *dev = &dev_priv->drm;
539 struct intel_crtc *crtc;
540 int ret;
541
542 ret = mutex_lock_interruptible(&dev->struct_mutex);
543 if (ret)
544 return ret;
545
546 for_each_intel_crtc(dev, crtc) {
547 const char pipe = pipe_name(crtc->pipe);
548 const char plane = plane_name(crtc->plane);
549 struct intel_flip_work *work;
550
551 spin_lock_irq(&dev->event_lock);
552 work = crtc->flip_work;
553 if (work == NULL) {
554 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
555 pipe, plane);
556 } else {
557 u32 pending;
558 u32 addr;
559
560 pending = atomic_read(&work->pending);
561 if (pending) {
562 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
563 pipe, plane);
564 } else {
565 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
566 pipe, plane);
567 }
568 if (work->flip_queued_req) {
569 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
570
571 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
572 engine->name,
573 i915_gem_request_get_seqno(work->flip_queued_req),
574 dev_priv->next_seqno,
575 intel_engine_get_seqno(engine),
576 i915_gem_request_completed(work->flip_queued_req));
577 } else
578 seq_printf(m, "Flip not associated with any ring\n");
579 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
580 work->flip_queued_vblank,
581 work->flip_ready_vblank,
582 intel_crtc_get_vblank_counter(crtc));
583 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
584
585 if (INTEL_GEN(dev_priv) >= 4)
586 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
587 else
588 addr = I915_READ(DSPADDR(crtc->plane));
589 seq_printf(m, "Current scanout address 0x%08x\n", addr);
590
591 if (work->pending_flip_obj) {
592 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
593 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
594 }
595 }
596 spin_unlock_irq(&dev->event_lock);
597 }
598
599 mutex_unlock(&dev->struct_mutex);
600
601 return 0;
602}
603
604static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
605{
606 struct drm_i915_private *dev_priv = node_to_i915(m->private);
607 struct drm_device *dev = &dev_priv->drm;
608 struct drm_i915_gem_object *obj;
609 struct intel_engine_cs *engine;
610 int total = 0;
611 int ret, j;
612
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
614 if (ret)
615 return ret;
616
617 for_each_engine(engine, dev_priv) {
618 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
619 int count;
620
621 count = 0;
622 list_for_each_entry(obj,
623 &engine->batch_pool.cache_list[j],
624 batch_pool_link)
625 count++;
626 seq_printf(m, "%s cache[%d]: %d objects\n",
627 engine->name, j, count);
628
629 list_for_each_entry(obj,
630 &engine->batch_pool.cache_list[j],
631 batch_pool_link) {
632 seq_puts(m, " ");
633 describe_obj(m, obj);
634 seq_putc(m, '\n');
635 }
636
637 total += count;
638 }
639 }
640
641 seq_printf(m, "total: %d\n", total);
642
643 mutex_unlock(&dev->struct_mutex);
644
645 return 0;
646}
647
648static int i915_gem_request_info(struct seq_file *m, void *data)
649{
650 struct drm_i915_private *dev_priv = node_to_i915(m->private);
651 struct drm_device *dev = &dev_priv->drm;
652 struct intel_engine_cs *engine;
653 struct drm_i915_gem_request *req;
654 int ret, any;
655
656 ret = mutex_lock_interruptible(&dev->struct_mutex);
657 if (ret)
658 return ret;
659
660 any = 0;
661 for_each_engine(engine, dev_priv) {
662 int count;
663
664 count = 0;
665 list_for_each_entry(req, &engine->request_list, link)
666 count++;
667 if (count == 0)
668 continue;
669
670 seq_printf(m, "%s requests: %d\n", engine->name, count);
671 list_for_each_entry(req, &engine->request_list, link) {
672 struct pid *pid = req->ctx->pid;
673 struct task_struct *task;
674
675 rcu_read_lock();
676 task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
677 seq_printf(m, " %x @ %d: %s [%d]\n",
678 req->fence.seqno,
679 (int) (jiffies - req->emitted_jiffies),
680 task ? task->comm : "<unknown>",
681 task ? task->pid : -1);
682 rcu_read_unlock();
683 }
684
685 any++;
686 }
687 mutex_unlock(&dev->struct_mutex);
688
689 if (any == 0)
690 seq_puts(m, "No requests\n");
691
692 return 0;
693}
694
695static void i915_ring_seqno_info(struct seq_file *m,
696 struct intel_engine_cs *engine)
697{
698 struct intel_breadcrumbs *b = &engine->breadcrumbs;
699 struct rb_node *rb;
700
701 seq_printf(m, "Current sequence (%s): %x\n",
702 engine->name, intel_engine_get_seqno(engine));
703
704 spin_lock(&b->lock);
705 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
706 struct intel_wait *w = container_of(rb, typeof(*w), node);
707
708 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
709 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
710 }
711 spin_unlock(&b->lock);
712}
713
714static int i915_gem_seqno_info(struct seq_file *m, void *data)
715{
716 struct drm_i915_private *dev_priv = node_to_i915(m->private);
717 struct drm_device *dev = &dev_priv->drm;
718 struct intel_engine_cs *engine;
719 int ret;
720
721 ret = mutex_lock_interruptible(&dev->struct_mutex);
722 if (ret)
723 return ret;
724 intel_runtime_pm_get(dev_priv);
725
726 for_each_engine(engine, dev_priv)
727 i915_ring_seqno_info(m, engine);
728
729 intel_runtime_pm_put(dev_priv);
730 mutex_unlock(&dev->struct_mutex);
731
732 return 0;
733}
734
735
736static int i915_interrupt_info(struct seq_file *m, void *data)
737{
738 struct drm_i915_private *dev_priv = node_to_i915(m->private);
739 struct drm_device *dev = &dev_priv->drm;
740 struct intel_engine_cs *engine;
741 int ret, i, pipe;
742
743 ret = mutex_lock_interruptible(&dev->struct_mutex);
744 if (ret)
745 return ret;
746 intel_runtime_pm_get(dev_priv);
747
748 if (IS_CHERRYVIEW(dev_priv)) {
749 seq_printf(m, "Master Interrupt Control:\t%08x\n",
750 I915_READ(GEN8_MASTER_IRQ));
751
752 seq_printf(m, "Display IER:\t%08x\n",
753 I915_READ(VLV_IER));
754 seq_printf(m, "Display IIR:\t%08x\n",
755 I915_READ(VLV_IIR));
756 seq_printf(m, "Display IIR_RW:\t%08x\n",
757 I915_READ(VLV_IIR_RW));
758 seq_printf(m, "Display IMR:\t%08x\n",
759 I915_READ(VLV_IMR));
760 for_each_pipe(dev_priv, pipe)
761 seq_printf(m, "Pipe %c stat:\t%08x\n",
762 pipe_name(pipe),
763 I915_READ(PIPESTAT(pipe)));
764
765 seq_printf(m, "Port hotplug:\t%08x\n",
766 I915_READ(PORT_HOTPLUG_EN));
767 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
768 I915_READ(VLV_DPFLIPSTAT));
769 seq_printf(m, "DPINVGTT:\t%08x\n",
770 I915_READ(DPINVGTT));
771
772 for (i = 0; i < 4; i++) {
773 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
774 i, I915_READ(GEN8_GT_IMR(i)));
775 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
776 i, I915_READ(GEN8_GT_IIR(i)));
777 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
778 i, I915_READ(GEN8_GT_IER(i)));
779 }
780
781 seq_printf(m, "PCU interrupt mask:\t%08x\n",
782 I915_READ(GEN8_PCU_IMR));
783 seq_printf(m, "PCU interrupt identity:\t%08x\n",
784 I915_READ(GEN8_PCU_IIR));
785 seq_printf(m, "PCU interrupt enable:\t%08x\n",
786 I915_READ(GEN8_PCU_IER));
787 } else if (INTEL_GEN(dev_priv) >= 8) {
788 seq_printf(m, "Master Interrupt Control:\t%08x\n",
789 I915_READ(GEN8_MASTER_IRQ));
790
791 for (i = 0; i < 4; i++) {
792 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
793 i, I915_READ(GEN8_GT_IMR(i)));
794 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
795 i, I915_READ(GEN8_GT_IIR(i)));
796 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
797 i, I915_READ(GEN8_GT_IER(i)));
798 }
799
800 for_each_pipe(dev_priv, pipe) {
801 enum intel_display_power_domain power_domain;
802
803 power_domain = POWER_DOMAIN_PIPE(pipe);
804 if (!intel_display_power_get_if_enabled(dev_priv,
805 power_domain)) {
806 seq_printf(m, "Pipe %c power disabled\n",
807 pipe_name(pipe));
808 continue;
809 }
810 seq_printf(m, "Pipe %c IMR:\t%08x\n",
811 pipe_name(pipe),
812 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
813 seq_printf(m, "Pipe %c IIR:\t%08x\n",
814 pipe_name(pipe),
815 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
816 seq_printf(m, "Pipe %c IER:\t%08x\n",
817 pipe_name(pipe),
818 I915_READ(GEN8_DE_PIPE_IER(pipe)));
819
820 intel_display_power_put(dev_priv, power_domain);
821 }
822
823 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
824 I915_READ(GEN8_DE_PORT_IMR));
825 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
826 I915_READ(GEN8_DE_PORT_IIR));
827 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
828 I915_READ(GEN8_DE_PORT_IER));
829
830 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
831 I915_READ(GEN8_DE_MISC_IMR));
832 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
833 I915_READ(GEN8_DE_MISC_IIR));
834 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
835 I915_READ(GEN8_DE_MISC_IER));
836
837 seq_printf(m, "PCU interrupt mask:\t%08x\n",
838 I915_READ(GEN8_PCU_IMR));
839 seq_printf(m, "PCU interrupt identity:\t%08x\n",
840 I915_READ(GEN8_PCU_IIR));
841 seq_printf(m, "PCU interrupt enable:\t%08x\n",
842 I915_READ(GEN8_PCU_IER));
843 } else if (IS_VALLEYVIEW(dev_priv)) {
844 seq_printf(m, "Display IER:\t%08x\n",
845 I915_READ(VLV_IER));
846 seq_printf(m, "Display IIR:\t%08x\n",
847 I915_READ(VLV_IIR));
848 seq_printf(m, "Display IIR_RW:\t%08x\n",
849 I915_READ(VLV_IIR_RW));
850 seq_printf(m, "Display IMR:\t%08x\n",
851 I915_READ(VLV_IMR));
852 for_each_pipe(dev_priv, pipe)
853 seq_printf(m, "Pipe %c stat:\t%08x\n",
854 pipe_name(pipe),
855 I915_READ(PIPESTAT(pipe)));
856
857 seq_printf(m, "Master IER:\t%08x\n",
858 I915_READ(VLV_MASTER_IER));
859
860 seq_printf(m, "Render IER:\t%08x\n",
861 I915_READ(GTIER));
862 seq_printf(m, "Render IIR:\t%08x\n",
863 I915_READ(GTIIR));
864 seq_printf(m, "Render IMR:\t%08x\n",
865 I915_READ(GTIMR));
866
867 seq_printf(m, "PM IER:\t\t%08x\n",
868 I915_READ(GEN6_PMIER));
869 seq_printf(m, "PM IIR:\t\t%08x\n",
870 I915_READ(GEN6_PMIIR));
871 seq_printf(m, "PM IMR:\t\t%08x\n",
872 I915_READ(GEN6_PMIMR));
873
874 seq_printf(m, "Port hotplug:\t%08x\n",
875 I915_READ(PORT_HOTPLUG_EN));
876 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
877 I915_READ(VLV_DPFLIPSTAT));
878 seq_printf(m, "DPINVGTT:\t%08x\n",
879 I915_READ(DPINVGTT));
880
881 } else if (!HAS_PCH_SPLIT(dev_priv)) {
882 seq_printf(m, "Interrupt enable: %08x\n",
883 I915_READ(IER));
884 seq_printf(m, "Interrupt identity: %08x\n",
885 I915_READ(IIR));
886 seq_printf(m, "Interrupt mask: %08x\n",
887 I915_READ(IMR));
888 for_each_pipe(dev_priv, pipe)
889 seq_printf(m, "Pipe %c stat: %08x\n",
890 pipe_name(pipe),
891 I915_READ(PIPESTAT(pipe)));
892 } else {
893 seq_printf(m, "North Display Interrupt enable: %08x\n",
894 I915_READ(DEIER));
895 seq_printf(m, "North Display Interrupt identity: %08x\n",
896 I915_READ(DEIIR));
897 seq_printf(m, "North Display Interrupt mask: %08x\n",
898 I915_READ(DEIMR));
899 seq_printf(m, "South Display Interrupt enable: %08x\n",
900 I915_READ(SDEIER));
901 seq_printf(m, "South Display Interrupt identity: %08x\n",
902 I915_READ(SDEIIR));
903 seq_printf(m, "South Display Interrupt mask: %08x\n",
904 I915_READ(SDEIMR));
905 seq_printf(m, "Graphics Interrupt enable: %08x\n",
906 I915_READ(GTIER));
907 seq_printf(m, "Graphics Interrupt identity: %08x\n",
908 I915_READ(GTIIR));
909 seq_printf(m, "Graphics Interrupt mask: %08x\n",
910 I915_READ(GTIMR));
911 }
912 for_each_engine(engine, dev_priv) {
913 if (INTEL_GEN(dev_priv) >= 6) {
914 seq_printf(m,
915 "Graphics Interrupt mask (%s): %08x\n",
916 engine->name, I915_READ_IMR(engine));
917 }
918 i915_ring_seqno_info(m, engine);
919 }
920 intel_runtime_pm_put(dev_priv);
921 mutex_unlock(&dev->struct_mutex);
922
923 return 0;
924}
925
926static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
927{
928 struct drm_i915_private *dev_priv = node_to_i915(m->private);
929 struct drm_device *dev = &dev_priv->drm;
930 int i, ret;
931
932 ret = mutex_lock_interruptible(&dev->struct_mutex);
933 if (ret)
934 return ret;
935
936 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
937 for (i = 0; i < dev_priv->num_fence_regs; i++) {
938 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
939
940 seq_printf(m, "Fence %d, pin count = %d, object = ",
941 i, dev_priv->fence_regs[i].pin_count);
942 if (!vma)
943 seq_puts(m, "unused");
944 else
945 describe_obj(m, vma->obj);
946 seq_putc(m, '\n');
947 }
948
949 mutex_unlock(&dev->struct_mutex);
950 return 0;
951}
952
953static int i915_hws_info(struct seq_file *m, void *data)
954{
955 struct drm_info_node *node = m->private;
956 struct drm_i915_private *dev_priv = node_to_i915(node);
957 struct intel_engine_cs *engine;
958 const u32 *hws;
959 int i;
960
961 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
962 hws = engine->status_page.page_addr;
963 if (hws == NULL)
964 return 0;
965
966 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
967 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
968 i * 4,
969 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
970 }
971 return 0;
972}
973
974static ssize_t
975i915_error_state_write(struct file *filp,
976 const char __user *ubuf,
977 size_t cnt,
978 loff_t *ppos)
979{
980 struct i915_error_state_file_priv *error_priv = filp->private_data;
981 struct drm_device *dev = error_priv->dev;
982 int ret;
983
984 DRM_DEBUG_DRIVER("Resetting error state\n");
985
986 ret = mutex_lock_interruptible(&dev->struct_mutex);
987 if (ret)
988 return ret;
989
990 i915_destroy_error_state(dev);
991 mutex_unlock(&dev->struct_mutex);
992
993 return cnt;
994}
995
996static int i915_error_state_open(struct inode *inode, struct file *file)
997{
998 struct drm_i915_private *dev_priv = inode->i_private;
999 struct i915_error_state_file_priv *error_priv;
1000
1001 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1002 if (!error_priv)
1003 return -ENOMEM;
1004
1005 error_priv->dev = &dev_priv->drm;
1006
1007 i915_error_state_get(&dev_priv->drm, error_priv);
1008
1009 file->private_data = error_priv;
1010
1011 return 0;
1012}
1013
1014static int i915_error_state_release(struct inode *inode, struct file *file)
1015{
1016 struct i915_error_state_file_priv *error_priv = file->private_data;
1017
1018 i915_error_state_put(error_priv);
1019 kfree(error_priv);
1020
1021 return 0;
1022}
1023
1024static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1025 size_t count, loff_t *pos)
1026{
1027 struct i915_error_state_file_priv *error_priv = file->private_data;
1028 struct drm_i915_error_state_buf error_str;
1029 loff_t tmp_pos = 0;
1030 ssize_t ret_count = 0;
1031 int ret;
1032
1033 ret = i915_error_state_buf_init(&error_str,
1034 to_i915(error_priv->dev), count, *pos);
1035 if (ret)
1036 return ret;
1037
1038 ret = i915_error_state_to_str(&error_str, error_priv);
1039 if (ret)
1040 goto out;
1041
1042 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1043 error_str.buf,
1044 error_str.bytes);
1045
1046 if (ret_count < 0)
1047 ret = ret_count;
1048 else
1049 *pos = error_str.start + ret_count;
1050out:
1051 i915_error_state_buf_release(&error_str);
1052 return ret ?: ret_count;
1053}
1054
1055static const struct file_operations i915_error_state_fops = {
1056 .owner = THIS_MODULE,
1057 .open = i915_error_state_open,
1058 .read = i915_error_state_read,
1059 .write = i915_error_state_write,
1060 .llseek = default_llseek,
1061 .release = i915_error_state_release,
1062};
1063
1064static int
1065i915_next_seqno_get(void *data, u64 *val)
1066{
1067 struct drm_i915_private *dev_priv = data;
1068 int ret;
1069
1070 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1071 if (ret)
1072 return ret;
1073
1074 *val = dev_priv->next_seqno;
1075 mutex_unlock(&dev_priv->drm.struct_mutex);
1076
1077 return 0;
1078}
1079
1080static int
1081i915_next_seqno_set(void *data, u64 val)
1082{
1083 struct drm_i915_private *dev_priv = data;
1084 struct drm_device *dev = &dev_priv->drm;
1085 int ret;
1086
1087 ret = mutex_lock_interruptible(&dev->struct_mutex);
1088 if (ret)
1089 return ret;
1090
1091 ret = i915_gem_set_seqno(dev, val);
1092 mutex_unlock(&dev->struct_mutex);
1093
1094 return ret;
1095}
1096
1097DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1098 i915_next_seqno_get, i915_next_seqno_set,
1099 "0x%llx\n");
1100
1101static int i915_frequency_info(struct seq_file *m, void *unused)
1102{
1103 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1104 struct drm_device *dev = &dev_priv->drm;
1105 int ret = 0;
1106
1107 intel_runtime_pm_get(dev_priv);
1108
1109 if (IS_GEN5(dev_priv)) {
1110 u16 rgvswctl = I915_READ16(MEMSWCTL);
1111 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1112
1113 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1114 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1115 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1116 MEMSTAT_VID_SHIFT);
1117 seq_printf(m, "Current P-state: %d\n",
1118 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1119 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1120 u32 freq_sts;
1121
1122 mutex_lock(&dev_priv->rps.hw_lock);
1123 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1124 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1125 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1126
1127 seq_printf(m, "actual GPU freq: %d MHz\n",
1128 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1129
1130 seq_printf(m, "current GPU freq: %d MHz\n",
1131 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1132
1133 seq_printf(m, "max GPU freq: %d MHz\n",
1134 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1135
1136 seq_printf(m, "min GPU freq: %d MHz\n",
1137 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1138
1139 seq_printf(m, "idle GPU freq: %d MHz\n",
1140 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1141
1142 seq_printf(m,
1143 "efficient (RPe) frequency: %d MHz\n",
1144 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1145 mutex_unlock(&dev_priv->rps.hw_lock);
1146 } else if (INTEL_GEN(dev_priv) >= 6) {
1147 u32 rp_state_limits;
1148 u32 gt_perf_status;
1149 u32 rp_state_cap;
1150 u32 rpmodectl, rpinclimit, rpdeclimit;
1151 u32 rpstat, cagf, reqf;
1152 u32 rpupei, rpcurup, rpprevup;
1153 u32 rpdownei, rpcurdown, rpprevdown;
1154 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1155 int max_freq;
1156
1157 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1158 if (IS_BROXTON(dev_priv)) {
1159 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1160 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1161 } else {
1162 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1163 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1164 }
1165
1166 /* RPSTAT1 is in the GT power well */
1167 ret = mutex_lock_interruptible(&dev->struct_mutex);
1168 if (ret)
1169 goto out;
1170
1171 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1172
1173 reqf = I915_READ(GEN6_RPNSWREQ);
1174 if (IS_GEN9(dev_priv))
1175 reqf >>= 23;
1176 else {
1177 reqf &= ~GEN6_TURBO_DISABLE;
1178 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1179 reqf >>= 24;
1180 else
1181 reqf >>= 25;
1182 }
1183 reqf = intel_gpu_freq(dev_priv, reqf);
1184
1185 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1186 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1187 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1188
1189 rpstat = I915_READ(GEN6_RPSTAT1);
1190 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1191 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1192 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1193 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1194 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1195 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1196 if (IS_GEN9(dev_priv))
1197 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1198 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1199 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1200 else
1201 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1202 cagf = intel_gpu_freq(dev_priv, cagf);
1203
1204 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1205 mutex_unlock(&dev->struct_mutex);
1206
1207 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1208 pm_ier = I915_READ(GEN6_PMIER);
1209 pm_imr = I915_READ(GEN6_PMIMR);
1210 pm_isr = I915_READ(GEN6_PMISR);
1211 pm_iir = I915_READ(GEN6_PMIIR);
1212 pm_mask = I915_READ(GEN6_PMINTRMSK);
1213 } else {
1214 pm_ier = I915_READ(GEN8_GT_IER(2));
1215 pm_imr = I915_READ(GEN8_GT_IMR(2));
1216 pm_isr = I915_READ(GEN8_GT_ISR(2));
1217 pm_iir = I915_READ(GEN8_GT_IIR(2));
1218 pm_mask = I915_READ(GEN6_PMINTRMSK);
1219 }
1220 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1221 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1222 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1223 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1224 seq_printf(m, "Render p-state ratio: %d\n",
1225 (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1226 seq_printf(m, "Render p-state VID: %d\n",
1227 gt_perf_status & 0xff);
1228 seq_printf(m, "Render p-state limit: %d\n",
1229 rp_state_limits & 0xff);
1230 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1231 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1232 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1233 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1234 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1235 seq_printf(m, "CAGF: %dMHz\n", cagf);
1236 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1237 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1238 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1239 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1240 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1241 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1242 seq_printf(m, "Up threshold: %d%%\n",
1243 dev_priv->rps.up_threshold);
1244
1245 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1246 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1247 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1248 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1249 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1250 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1251 seq_printf(m, "Down threshold: %d%%\n",
1252 dev_priv->rps.down_threshold);
1253
1254 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1255 rp_state_cap >> 16) & 0xff;
1256 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1257 GEN9_FREQ_SCALER : 1);
1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259 intel_gpu_freq(dev_priv, max_freq));
1260
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
1262 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1263 GEN9_FREQ_SCALER : 1);
1264 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1265 intel_gpu_freq(dev_priv, max_freq));
1266
1267 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1268 rp_state_cap >> 0) & 0xff;
1269 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1270 GEN9_FREQ_SCALER : 1);
1271 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1272 intel_gpu_freq(dev_priv, max_freq));
1273 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1274 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1275
1276 seq_printf(m, "Current freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1278 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1279 seq_printf(m, "Idle freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1281 seq_printf(m, "Min freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1283 seq_printf(m, "Boost freq: %d MHz\n",
1284 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1285 seq_printf(m, "Max freq: %d MHz\n",
1286 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1287 seq_printf(m,
1288 "efficient (RPe) frequency: %d MHz\n",
1289 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1290 } else {
1291 seq_puts(m, "no P-state info available\n");
1292 }
1293
1294 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1295 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1296 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1297
1298out:
1299 intel_runtime_pm_put(dev_priv);
1300 return ret;
1301}
1302
1303static int i915_hangcheck_info(struct seq_file *m, void *unused)
1304{
1305 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1306 struct intel_engine_cs *engine;
1307 u64 acthd[I915_NUM_ENGINES];
1308 u32 seqno[I915_NUM_ENGINES];
1309 u32 instdone[I915_NUM_INSTDONE_REG];
1310 enum intel_engine_id id;
1311 int j;
1312
1313 if (!i915.enable_hangcheck) {
1314 seq_printf(m, "Hangcheck disabled\n");
1315 return 0;
1316 }
1317
1318 intel_runtime_pm_get(dev_priv);
1319
1320 for_each_engine_id(engine, dev_priv, id) {
1321 acthd[id] = intel_engine_get_active_head(engine);
1322 seqno[id] = intel_engine_get_seqno(engine);
1323 }
1324
1325 i915_get_extra_instdone(dev_priv, instdone);
1326
1327 intel_runtime_pm_put(dev_priv);
1328
1329 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1330 seq_printf(m, "Hangcheck active, fires in %dms\n",
1331 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1332 jiffies));
1333 } else
1334 seq_printf(m, "Hangcheck inactive\n");
1335
1336 for_each_engine_id(engine, dev_priv, id) {
1337 seq_printf(m, "%s:\n", engine->name);
1338 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1339 engine->hangcheck.seqno,
1340 seqno[id],
1341 engine->last_submitted_seqno);
1342 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1343 yesno(intel_engine_has_waiter(engine)),
1344 yesno(test_bit(engine->id,
1345 &dev_priv->gpu_error.missed_irq_rings)));
1346 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1347 (long long)engine->hangcheck.acthd,
1348 (long long)acthd[id]);
1349 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1350 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1351
1352 if (engine->id == RCS) {
1353 seq_puts(m, "\tinstdone read =");
1354
1355 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1356 seq_printf(m, " 0x%08x", instdone[j]);
1357
1358 seq_puts(m, "\n\tinstdone accu =");
1359
1360 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1361 seq_printf(m, " 0x%08x",
1362 engine->hangcheck.instdone[j]);
1363
1364 seq_puts(m, "\n");
1365 }
1366 }
1367
1368 return 0;
1369}
1370
1371static int ironlake_drpc_info(struct seq_file *m)
1372{
1373 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1374 struct drm_device *dev = &dev_priv->drm;
1375 u32 rgvmodectl, rstdbyctl;
1376 u16 crstandvid;
1377 int ret;
1378
1379 ret = mutex_lock_interruptible(&dev->struct_mutex);
1380 if (ret)
1381 return ret;
1382 intel_runtime_pm_get(dev_priv);
1383
1384 rgvmodectl = I915_READ(MEMMODECTL);
1385 rstdbyctl = I915_READ(RSTDBYCTL);
1386 crstandvid = I915_READ16(CRSTANDVID);
1387
1388 intel_runtime_pm_put(dev_priv);
1389 mutex_unlock(&dev->struct_mutex);
1390
1391 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1392 seq_printf(m, "Boost freq: %d\n",
1393 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394 MEMMODE_BOOST_FREQ_SHIFT);
1395 seq_printf(m, "HW control enabled: %s\n",
1396 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1397 seq_printf(m, "SW control enabled: %s\n",
1398 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1399 seq_printf(m, "Gated voltage change: %s\n",
1400 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1401 seq_printf(m, "Starting frequency: P%d\n",
1402 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1403 seq_printf(m, "Max P-state: P%d\n",
1404 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1405 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408 seq_printf(m, "Render standby enabled: %s\n",
1409 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1410 seq_puts(m, "Current RS state: ");
1411 switch (rstdbyctl & RSX_STATUS_MASK) {
1412 case RSX_STATUS_ON:
1413 seq_puts(m, "on\n");
1414 break;
1415 case RSX_STATUS_RC1:
1416 seq_puts(m, "RC1\n");
1417 break;
1418 case RSX_STATUS_RC1E:
1419 seq_puts(m, "RC1E\n");
1420 break;
1421 case RSX_STATUS_RS1:
1422 seq_puts(m, "RS1\n");
1423 break;
1424 case RSX_STATUS_RS2:
1425 seq_puts(m, "RS2 (RC6)\n");
1426 break;
1427 case RSX_STATUS_RS3:
1428 seq_puts(m, "RC3 (RC6+)\n");
1429 break;
1430 default:
1431 seq_puts(m, "unknown\n");
1432 break;
1433 }
1434
1435 return 0;
1436}
1437
1438static int i915_forcewake_domains(struct seq_file *m, void *data)
1439{
1440 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1441 struct intel_uncore_forcewake_domain *fw_domain;
1442
1443 spin_lock_irq(&dev_priv->uncore.lock);
1444 for_each_fw_domain(fw_domain, dev_priv) {
1445 seq_printf(m, "%s.wake_count = %u\n",
1446 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1447 fw_domain->wake_count);
1448 }
1449 spin_unlock_irq(&dev_priv->uncore.lock);
1450
1451 return 0;
1452}
1453
1454static int vlv_drpc_info(struct seq_file *m)
1455{
1456 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1457 u32 rpmodectl1, rcctl1, pw_status;
1458
1459 intel_runtime_pm_get(dev_priv);
1460
1461 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1462 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1463 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1464
1465 intel_runtime_pm_put(dev_priv);
1466
1467 seq_printf(m, "Video Turbo Mode: %s\n",
1468 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1469 seq_printf(m, "Turbo enabled: %s\n",
1470 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1471 seq_printf(m, "HW control enabled: %s\n",
1472 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1473 seq_printf(m, "SW control enabled: %s\n",
1474 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1475 GEN6_RP_MEDIA_SW_MODE));
1476 seq_printf(m, "RC6 Enabled: %s\n",
1477 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1478 GEN6_RC_CTL_EI_MODE(1))));
1479 seq_printf(m, "Render Power Well: %s\n",
1480 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1481 seq_printf(m, "Media Power Well: %s\n",
1482 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1483
1484 seq_printf(m, "Render RC6 residency since boot: %u\n",
1485 I915_READ(VLV_GT_RENDER_RC6));
1486 seq_printf(m, "Media RC6 residency since boot: %u\n",
1487 I915_READ(VLV_GT_MEDIA_RC6));
1488
1489 return i915_forcewake_domains(m, NULL);
1490}
1491
1492static int gen6_drpc_info(struct seq_file *m)
1493{
1494 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1495 struct drm_device *dev = &dev_priv->drm;
1496 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1497 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1498 unsigned forcewake_count;
1499 int count = 0, ret;
1500
1501 ret = mutex_lock_interruptible(&dev->struct_mutex);
1502 if (ret)
1503 return ret;
1504 intel_runtime_pm_get(dev_priv);
1505
1506 spin_lock_irq(&dev_priv->uncore.lock);
1507 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1508 spin_unlock_irq(&dev_priv->uncore.lock);
1509
1510 if (forcewake_count) {
1511 seq_puts(m, "RC information inaccurate because somebody "
1512 "holds a forcewake reference \n");
1513 } else {
1514 /* NB: we cannot use forcewake, else we read the wrong values */
1515 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1516 udelay(10);
1517 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1518 }
1519
1520 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1521 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1522
1523 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1524 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1525 if (INTEL_GEN(dev_priv) >= 9) {
1526 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1527 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1528 }
1529 mutex_unlock(&dev->struct_mutex);
1530 mutex_lock(&dev_priv->rps.hw_lock);
1531 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1532 mutex_unlock(&dev_priv->rps.hw_lock);
1533
1534 intel_runtime_pm_put(dev_priv);
1535
1536 seq_printf(m, "Video Turbo Mode: %s\n",
1537 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1538 seq_printf(m, "HW control enabled: %s\n",
1539 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1540 seq_printf(m, "SW control enabled: %s\n",
1541 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1542 GEN6_RP_MEDIA_SW_MODE));
1543 seq_printf(m, "RC1e Enabled: %s\n",
1544 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1545 seq_printf(m, "RC6 Enabled: %s\n",
1546 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1547 if (INTEL_GEN(dev_priv) >= 9) {
1548 seq_printf(m, "Render Well Gating Enabled: %s\n",
1549 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1550 seq_printf(m, "Media Well Gating Enabled: %s\n",
1551 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1552 }
1553 seq_printf(m, "Deep RC6 Enabled: %s\n",
1554 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1555 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1556 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1557 seq_puts(m, "Current RC state: ");
1558 switch (gt_core_status & GEN6_RCn_MASK) {
1559 case GEN6_RC0:
1560 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1561 seq_puts(m, "Core Power Down\n");
1562 else
1563 seq_puts(m, "on\n");
1564 break;
1565 case GEN6_RC3:
1566 seq_puts(m, "RC3\n");
1567 break;
1568 case GEN6_RC6:
1569 seq_puts(m, "RC6\n");
1570 break;
1571 case GEN6_RC7:
1572 seq_puts(m, "RC7\n");
1573 break;
1574 default:
1575 seq_puts(m, "Unknown\n");
1576 break;
1577 }
1578
1579 seq_printf(m, "Core Power Down: %s\n",
1580 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1581 if (INTEL_GEN(dev_priv) >= 9) {
1582 seq_printf(m, "Render Power Well: %s\n",
1583 (gen9_powergate_status &
1584 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1585 seq_printf(m, "Media Power Well: %s\n",
1586 (gen9_powergate_status &
1587 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1588 }
1589
1590 /* Not exactly sure what this is */
1591 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1592 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1593 seq_printf(m, "RC6 residency since boot: %u\n",
1594 I915_READ(GEN6_GT_GFX_RC6));
1595 seq_printf(m, "RC6+ residency since boot: %u\n",
1596 I915_READ(GEN6_GT_GFX_RC6p));
1597 seq_printf(m, "RC6++ residency since boot: %u\n",
1598 I915_READ(GEN6_GT_GFX_RC6pp));
1599
1600 seq_printf(m, "RC6 voltage: %dmV\n",
1601 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1602 seq_printf(m, "RC6+ voltage: %dmV\n",
1603 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1604 seq_printf(m, "RC6++ voltage: %dmV\n",
1605 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1606 return i915_forcewake_domains(m, NULL);
1607}
1608
1609static int i915_drpc_info(struct seq_file *m, void *unused)
1610{
1611 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1612
1613 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1614 return vlv_drpc_info(m);
1615 else if (INTEL_GEN(dev_priv) >= 6)
1616 return gen6_drpc_info(m);
1617 else
1618 return ironlake_drpc_info(m);
1619}
1620
1621static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1622{
1623 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1624
1625 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1626 dev_priv->fb_tracking.busy_bits);
1627
1628 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1629 dev_priv->fb_tracking.flip_bits);
1630
1631 return 0;
1632}
1633
1634static int i915_fbc_status(struct seq_file *m, void *unused)
1635{
1636 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637
1638 if (!HAS_FBC(dev_priv)) {
1639 seq_puts(m, "FBC unsupported on this chipset\n");
1640 return 0;
1641 }
1642
1643 intel_runtime_pm_get(dev_priv);
1644 mutex_lock(&dev_priv->fbc.lock);
1645
1646 if (intel_fbc_is_active(dev_priv))
1647 seq_puts(m, "FBC enabled\n");
1648 else
1649 seq_printf(m, "FBC disabled: %s\n",
1650 dev_priv->fbc.no_fbc_reason);
1651
1652 if (INTEL_GEN(dev_priv) >= 7)
1653 seq_printf(m, "Compressing: %s\n",
1654 yesno(I915_READ(FBC_STATUS2) &
1655 FBC_COMPRESSION_MASK));
1656
1657 mutex_unlock(&dev_priv->fbc.lock);
1658 intel_runtime_pm_put(dev_priv);
1659
1660 return 0;
1661}
1662
1663static int i915_fbc_fc_get(void *data, u64 *val)
1664{
1665 struct drm_i915_private *dev_priv = data;
1666
1667 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1668 return -ENODEV;
1669
1670 *val = dev_priv->fbc.false_color;
1671
1672 return 0;
1673}
1674
1675static int i915_fbc_fc_set(void *data, u64 val)
1676{
1677 struct drm_i915_private *dev_priv = data;
1678 u32 reg;
1679
1680 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1681 return -ENODEV;
1682
1683 mutex_lock(&dev_priv->fbc.lock);
1684
1685 reg = I915_READ(ILK_DPFC_CONTROL);
1686 dev_priv->fbc.false_color = val;
1687
1688 I915_WRITE(ILK_DPFC_CONTROL, val ?
1689 (reg | FBC_CTL_FALSE_COLOR) :
1690 (reg & ~FBC_CTL_FALSE_COLOR));
1691
1692 mutex_unlock(&dev_priv->fbc.lock);
1693 return 0;
1694}
1695
1696DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1697 i915_fbc_fc_get, i915_fbc_fc_set,
1698 "%llu\n");
1699
1700static int i915_ips_status(struct seq_file *m, void *unused)
1701{
1702 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1703
1704 if (!HAS_IPS(dev_priv)) {
1705 seq_puts(m, "not supported\n");
1706 return 0;
1707 }
1708
1709 intel_runtime_pm_get(dev_priv);
1710
1711 seq_printf(m, "Enabled by kernel parameter: %s\n",
1712 yesno(i915.enable_ips));
1713
1714 if (INTEL_GEN(dev_priv) >= 8) {
1715 seq_puts(m, "Currently: unknown\n");
1716 } else {
1717 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1718 seq_puts(m, "Currently: enabled\n");
1719 else
1720 seq_puts(m, "Currently: disabled\n");
1721 }
1722
1723 intel_runtime_pm_put(dev_priv);
1724
1725 return 0;
1726}
1727
1728static int i915_sr_status(struct seq_file *m, void *unused)
1729{
1730 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1731 bool sr_enabled = false;
1732
1733 intel_runtime_pm_get(dev_priv);
1734
1735 if (HAS_PCH_SPLIT(dev_priv))
1736 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1737 else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1738 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1739 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1740 else if (IS_I915GM(dev_priv))
1741 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1742 else if (IS_PINEVIEW(dev_priv))
1743 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1744 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1745 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1746
1747 intel_runtime_pm_put(dev_priv);
1748
1749 seq_printf(m, "self-refresh: %s\n",
1750 sr_enabled ? "enabled" : "disabled");
1751
1752 return 0;
1753}
1754
1755static int i915_emon_status(struct seq_file *m, void *unused)
1756{
1757 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1758 struct drm_device *dev = &dev_priv->drm;
1759 unsigned long temp, chipset, gfx;
1760 int ret;
1761
1762 if (!IS_GEN5(dev_priv))
1763 return -ENODEV;
1764
1765 ret = mutex_lock_interruptible(&dev->struct_mutex);
1766 if (ret)
1767 return ret;
1768
1769 temp = i915_mch_val(dev_priv);
1770 chipset = i915_chipset_val(dev_priv);
1771 gfx = i915_gfx_val(dev_priv);
1772 mutex_unlock(&dev->struct_mutex);
1773
1774 seq_printf(m, "GMCH temp: %ld\n", temp);
1775 seq_printf(m, "Chipset power: %ld\n", chipset);
1776 seq_printf(m, "GFX power: %ld\n", gfx);
1777 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1778
1779 return 0;
1780}
1781
1782static int i915_ring_freq_table(struct seq_file *m, void *unused)
1783{
1784 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1785 int ret = 0;
1786 int gpu_freq, ia_freq;
1787 unsigned int max_gpu_freq, min_gpu_freq;
1788
1789 if (!HAS_CORE_RING_FREQ(dev_priv)) {
1790 seq_puts(m, "unsupported on this chipset\n");
1791 return 0;
1792 }
1793
1794 intel_runtime_pm_get(dev_priv);
1795
1796 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1797 if (ret)
1798 goto out;
1799
1800 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1801 /* Convert GT frequency to 50 HZ units */
1802 min_gpu_freq =
1803 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1804 max_gpu_freq =
1805 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1806 } else {
1807 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1808 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1809 }
1810
1811 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1812
1813 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1814 ia_freq = gpu_freq;
1815 sandybridge_pcode_read(dev_priv,
1816 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1817 &ia_freq);
1818 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1819 intel_gpu_freq(dev_priv, (gpu_freq *
1820 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1821 GEN9_FREQ_SCALER : 1))),
1822 ((ia_freq >> 0) & 0xff) * 100,
1823 ((ia_freq >> 8) & 0xff) * 100);
1824 }
1825
1826 mutex_unlock(&dev_priv->rps.hw_lock);
1827
1828out:
1829 intel_runtime_pm_put(dev_priv);
1830 return ret;
1831}
1832
1833static int i915_opregion(struct seq_file *m, void *unused)
1834{
1835 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1836 struct drm_device *dev = &dev_priv->drm;
1837 struct intel_opregion *opregion = &dev_priv->opregion;
1838 int ret;
1839
1840 ret = mutex_lock_interruptible(&dev->struct_mutex);
1841 if (ret)
1842 goto out;
1843
1844 if (opregion->header)
1845 seq_write(m, opregion->header, OPREGION_SIZE);
1846
1847 mutex_unlock(&dev->struct_mutex);
1848
1849out:
1850 return 0;
1851}
1852
1853static int i915_vbt(struct seq_file *m, void *unused)
1854{
1855 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1856
1857 if (opregion->vbt)
1858 seq_write(m, opregion->vbt, opregion->vbt_size);
1859
1860 return 0;
1861}
1862
1863static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1864{
1865 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1866 struct drm_device *dev = &dev_priv->drm;
1867 struct intel_framebuffer *fbdev_fb = NULL;
1868 struct drm_framebuffer *drm_fb;
1869 int ret;
1870
1871 ret = mutex_lock_interruptible(&dev->struct_mutex);
1872 if (ret)
1873 return ret;
1874
1875#ifdef CONFIG_DRM_FBDEV_EMULATION
1876 if (dev_priv->fbdev) {
1877 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1878
1879 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880 fbdev_fb->base.width,
1881 fbdev_fb->base.height,
1882 fbdev_fb->base.depth,
1883 fbdev_fb->base.bits_per_pixel,
1884 fbdev_fb->base.modifier[0],
1885 drm_framebuffer_read_refcount(&fbdev_fb->base));
1886 describe_obj(m, fbdev_fb->obj);
1887 seq_putc(m, '\n');
1888 }
1889#endif
1890
1891 mutex_lock(&dev->mode_config.fb_lock);
1892 drm_for_each_fb(drm_fb, dev) {
1893 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1894 if (fb == fbdev_fb)
1895 continue;
1896
1897 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1898 fb->base.width,
1899 fb->base.height,
1900 fb->base.depth,
1901 fb->base.bits_per_pixel,
1902 fb->base.modifier[0],
1903 drm_framebuffer_read_refcount(&fb->base));
1904 describe_obj(m, fb->obj);
1905 seq_putc(m, '\n');
1906 }
1907 mutex_unlock(&dev->mode_config.fb_lock);
1908 mutex_unlock(&dev->struct_mutex);
1909
1910 return 0;
1911}
1912
1913static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1914{
1915 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1916 ring->space, ring->head, ring->tail,
1917 ring->last_retired_head);
1918}
1919
1920static int i915_context_status(struct seq_file *m, void *unused)
1921{
1922 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1923 struct drm_device *dev = &dev_priv->drm;
1924 struct intel_engine_cs *engine;
1925 struct i915_gem_context *ctx;
1926 int ret;
1927
1928 ret = mutex_lock_interruptible(&dev->struct_mutex);
1929 if (ret)
1930 return ret;
1931
1932 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1933 seq_printf(m, "HW context %u ", ctx->hw_id);
1934 if (ctx->pid) {
1935 struct task_struct *task;
1936
1937 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1938 if (task) {
1939 seq_printf(m, "(%s [%d]) ",
1940 task->comm, task->pid);
1941 put_task_struct(task);
1942 }
1943 } else if (IS_ERR(ctx->file_priv)) {
1944 seq_puts(m, "(deleted) ");
1945 } else {
1946 seq_puts(m, "(kernel) ");
1947 }
1948
1949 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1950 seq_putc(m, '\n');
1951
1952 for_each_engine(engine, dev_priv) {
1953 struct intel_context *ce = &ctx->engine[engine->id];
1954
1955 seq_printf(m, "%s: ", engine->name);
1956 seq_putc(m, ce->initialised ? 'I' : 'i');
1957 if (ce->state)
1958 describe_obj(m, ce->state->obj);
1959 if (ce->ring)
1960 describe_ctx_ring(m, ce->ring);
1961 seq_putc(m, '\n');
1962 }
1963
1964 seq_putc(m, '\n');
1965 }
1966
1967 mutex_unlock(&dev->struct_mutex);
1968
1969 return 0;
1970}
1971
1972static void i915_dump_lrc_obj(struct seq_file *m,
1973 struct i915_gem_context *ctx,
1974 struct intel_engine_cs *engine)
1975{
1976 struct i915_vma *vma = ctx->engine[engine->id].state;
1977 struct page *page;
1978 int j;
1979
1980 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1981
1982 if (!vma) {
1983 seq_puts(m, "\tFake context\n");
1984 return;
1985 }
1986
1987 if (vma->flags & I915_VMA_GLOBAL_BIND)
1988 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1989 i915_ggtt_offset(vma));
1990
1991 if (i915_gem_object_get_pages(vma->obj)) {
1992 seq_puts(m, "\tFailed to get pages for context object\n\n");
1993 return;
1994 }
1995
1996 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1997 if (page) {
1998 u32 *reg_state = kmap_atomic(page);
1999
2000 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2001 seq_printf(m,
2002 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2003 j * 4,
2004 reg_state[j], reg_state[j + 1],
2005 reg_state[j + 2], reg_state[j + 3]);
2006 }
2007 kunmap_atomic(reg_state);
2008 }
2009
2010 seq_putc(m, '\n');
2011}
2012
2013static int i915_dump_lrc(struct seq_file *m, void *unused)
2014{
2015 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2016 struct drm_device *dev = &dev_priv->drm;
2017 struct intel_engine_cs *engine;
2018 struct i915_gem_context *ctx;
2019 int ret;
2020
2021 if (!i915.enable_execlists) {
2022 seq_printf(m, "Logical Ring Contexts are disabled\n");
2023 return 0;
2024 }
2025
2026 ret = mutex_lock_interruptible(&dev->struct_mutex);
2027 if (ret)
2028 return ret;
2029
2030 list_for_each_entry(ctx, &dev_priv->context_list, link)
2031 for_each_engine(engine, dev_priv)
2032 i915_dump_lrc_obj(m, ctx, engine);
2033
2034 mutex_unlock(&dev->struct_mutex);
2035
2036 return 0;
2037}
2038
2039static int i915_execlists(struct seq_file *m, void *data)
2040{
2041 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2042 struct drm_device *dev = &dev_priv->drm;
2043 struct intel_engine_cs *engine;
2044 u32 status_pointer;
2045 u8 read_pointer;
2046 u8 write_pointer;
2047 u32 status;
2048 u32 ctx_id;
2049 struct list_head *cursor;
2050 int i, ret;
2051
2052 if (!i915.enable_execlists) {
2053 seq_puts(m, "Logical Ring Contexts are disabled\n");
2054 return 0;
2055 }
2056
2057 ret = mutex_lock_interruptible(&dev->struct_mutex);
2058 if (ret)
2059 return ret;
2060
2061 intel_runtime_pm_get(dev_priv);
2062
2063 for_each_engine(engine, dev_priv) {
2064 struct drm_i915_gem_request *head_req = NULL;
2065 int count = 0;
2066
2067 seq_printf(m, "%s\n", engine->name);
2068
2069 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2070 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2071 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2072 status, ctx_id);
2073
2074 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2075 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2076
2077 read_pointer = engine->next_context_status_buffer;
2078 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2079 if (read_pointer > write_pointer)
2080 write_pointer += GEN8_CSB_ENTRIES;
2081 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2082 read_pointer, write_pointer);
2083
2084 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2085 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2086 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2087
2088 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2089 i, status, ctx_id);
2090 }
2091
2092 spin_lock_bh(&engine->execlist_lock);
2093 list_for_each(cursor, &engine->execlist_queue)
2094 count++;
2095 head_req = list_first_entry_or_null(&engine->execlist_queue,
2096 struct drm_i915_gem_request,
2097 execlist_link);
2098 spin_unlock_bh(&engine->execlist_lock);
2099
2100 seq_printf(m, "\t%d requests in queue\n", count);
2101 if (head_req) {
2102 seq_printf(m, "\tHead request context: %u\n",
2103 head_req->ctx->hw_id);
2104 seq_printf(m, "\tHead request tail: %u\n",
2105 head_req->tail);
2106 }
2107
2108 seq_putc(m, '\n');
2109 }
2110
2111 intel_runtime_pm_put(dev_priv);
2112 mutex_unlock(&dev->struct_mutex);
2113
2114 return 0;
2115}
2116
2117static const char *swizzle_string(unsigned swizzle)
2118{
2119 switch (swizzle) {
2120 case I915_BIT_6_SWIZZLE_NONE:
2121 return "none";
2122 case I915_BIT_6_SWIZZLE_9:
2123 return "bit9";
2124 case I915_BIT_6_SWIZZLE_9_10:
2125 return "bit9/bit10";
2126 case I915_BIT_6_SWIZZLE_9_11:
2127 return "bit9/bit11";
2128 case I915_BIT_6_SWIZZLE_9_10_11:
2129 return "bit9/bit10/bit11";
2130 case I915_BIT_6_SWIZZLE_9_17:
2131 return "bit9/bit17";
2132 case I915_BIT_6_SWIZZLE_9_10_17:
2133 return "bit9/bit10/bit17";
2134 case I915_BIT_6_SWIZZLE_UNKNOWN:
2135 return "unknown";
2136 }
2137
2138 return "bug";
2139}
2140
2141static int i915_swizzle_info(struct seq_file *m, void *data)
2142{
2143 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2144 struct drm_device *dev = &dev_priv->drm;
2145 int ret;
2146
2147 ret = mutex_lock_interruptible(&dev->struct_mutex);
2148 if (ret)
2149 return ret;
2150 intel_runtime_pm_get(dev_priv);
2151
2152 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2153 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2154 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2155 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2156
2157 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2158 seq_printf(m, "DDC = 0x%08x\n",
2159 I915_READ(DCC));
2160 seq_printf(m, "DDC2 = 0x%08x\n",
2161 I915_READ(DCC2));
2162 seq_printf(m, "C0DRB3 = 0x%04x\n",
2163 I915_READ16(C0DRB3));
2164 seq_printf(m, "C1DRB3 = 0x%04x\n",
2165 I915_READ16(C1DRB3));
2166 } else if (INTEL_GEN(dev_priv) >= 6) {
2167 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2168 I915_READ(MAD_DIMM_C0));
2169 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2170 I915_READ(MAD_DIMM_C1));
2171 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2172 I915_READ(MAD_DIMM_C2));
2173 seq_printf(m, "TILECTL = 0x%08x\n",
2174 I915_READ(TILECTL));
2175 if (INTEL_GEN(dev_priv) >= 8)
2176 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2177 I915_READ(GAMTARBMODE));
2178 else
2179 seq_printf(m, "ARB_MODE = 0x%08x\n",
2180 I915_READ(ARB_MODE));
2181 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2182 I915_READ(DISP_ARB_CTL));
2183 }
2184
2185 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2186 seq_puts(m, "L-shaped memory detected\n");
2187
2188 intel_runtime_pm_put(dev_priv);
2189 mutex_unlock(&dev->struct_mutex);
2190
2191 return 0;
2192}
2193
2194static int per_file_ctx(int id, void *ptr, void *data)
2195{
2196 struct i915_gem_context *ctx = ptr;
2197 struct seq_file *m = data;
2198 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2199
2200 if (!ppgtt) {
2201 seq_printf(m, " no ppgtt for context %d\n",
2202 ctx->user_handle);
2203 return 0;
2204 }
2205
2206 if (i915_gem_context_is_default(ctx))
2207 seq_puts(m, " default context:\n");
2208 else
2209 seq_printf(m, " context %d:\n", ctx->user_handle);
2210 ppgtt->debug_dump(ppgtt, m);
2211
2212 return 0;
2213}
2214
2215static void gen8_ppgtt_info(struct seq_file *m,
2216 struct drm_i915_private *dev_priv)
2217{
2218 struct intel_engine_cs *engine;
2219 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2220 int i;
2221
2222 if (!ppgtt)
2223 return;
2224
2225 for_each_engine(engine, dev_priv) {
2226 seq_printf(m, "%s\n", engine->name);
2227 for (i = 0; i < 4; i++) {
2228 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2229 pdp <<= 32;
2230 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2231 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2232 }
2233 }
2234}
2235
2236static void gen6_ppgtt_info(struct seq_file *m,
2237 struct drm_i915_private *dev_priv)
2238{
2239 struct intel_engine_cs *engine;
2240
2241 if (IS_GEN6(dev_priv))
2242 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2243
2244 for_each_engine(engine, dev_priv) {
2245 seq_printf(m, "%s\n", engine->name);
2246 if (IS_GEN7(dev_priv))
2247 seq_printf(m, "GFX_MODE: 0x%08x\n",
2248 I915_READ(RING_MODE_GEN7(engine)));
2249 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2250 I915_READ(RING_PP_DIR_BASE(engine)));
2251 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2252 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2253 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2254 I915_READ(RING_PP_DIR_DCLV(engine)));
2255 }
2256 if (dev_priv->mm.aliasing_ppgtt) {
2257 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2258
2259 seq_puts(m, "aliasing PPGTT:\n");
2260 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2261
2262 ppgtt->debug_dump(ppgtt, m);
2263 }
2264
2265 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2266}
2267
2268static int i915_ppgtt_info(struct seq_file *m, void *data)
2269{
2270 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2271 struct drm_device *dev = &dev_priv->drm;
2272 struct drm_file *file;
2273
2274 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2275 if (ret)
2276 return ret;
2277 intel_runtime_pm_get(dev_priv);
2278
2279 if (INTEL_GEN(dev_priv) >= 8)
2280 gen8_ppgtt_info(m, dev_priv);
2281 else if (INTEL_GEN(dev_priv) >= 6)
2282 gen6_ppgtt_info(m, dev_priv);
2283
2284 mutex_lock(&dev->filelist_mutex);
2285 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2286 struct drm_i915_file_private *file_priv = file->driver_priv;
2287 struct task_struct *task;
2288
2289 task = get_pid_task(file->pid, PIDTYPE_PID);
2290 if (!task) {
2291 ret = -ESRCH;
2292 goto out_unlock;
2293 }
2294 seq_printf(m, "\nproc: %s\n", task->comm);
2295 put_task_struct(task);
2296 idr_for_each(&file_priv->context_idr, per_file_ctx,
2297 (void *)(unsigned long)m);
2298 }
2299out_unlock:
2300 mutex_unlock(&dev->filelist_mutex);
2301
2302 intel_runtime_pm_put(dev_priv);
2303 mutex_unlock(&dev->struct_mutex);
2304
2305 return ret;
2306}
2307
2308static int count_irq_waiters(struct drm_i915_private *i915)
2309{
2310 struct intel_engine_cs *engine;
2311 int count = 0;
2312
2313 for_each_engine(engine, i915)
2314 count += intel_engine_has_waiter(engine);
2315
2316 return count;
2317}
2318
2319static const char *rps_power_to_str(unsigned int power)
2320{
2321 static const char * const strings[] = {
2322 [LOW_POWER] = "low power",
2323 [BETWEEN] = "mixed",
2324 [HIGH_POWER] = "high power",
2325 };
2326
2327 if (power >= ARRAY_SIZE(strings) || !strings[power])
2328 return "unknown";
2329
2330 return strings[power];
2331}
2332
2333static int i915_rps_boost_info(struct seq_file *m, void *data)
2334{
2335 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2336 struct drm_device *dev = &dev_priv->drm;
2337 struct drm_file *file;
2338
2339 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2340 seq_printf(m, "GPU busy? %s [%x]\n",
2341 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2342 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2343 seq_printf(m, "Frequency requested %d\n",
2344 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2345 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2346 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2347 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2348 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2349 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2350 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2351 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2352 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2353 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2354
2355 mutex_lock(&dev->filelist_mutex);
2356 spin_lock(&dev_priv->rps.client_lock);
2357 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2358 struct drm_i915_file_private *file_priv = file->driver_priv;
2359 struct task_struct *task;
2360
2361 rcu_read_lock();
2362 task = pid_task(file->pid, PIDTYPE_PID);
2363 seq_printf(m, "%s [%d]: %d boosts%s\n",
2364 task ? task->comm : "<unknown>",
2365 task ? task->pid : -1,
2366 file_priv->rps.boosts,
2367 list_empty(&file_priv->rps.link) ? "" : ", active");
2368 rcu_read_unlock();
2369 }
2370 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2371 spin_unlock(&dev_priv->rps.client_lock);
2372 mutex_unlock(&dev->filelist_mutex);
2373
2374 if (INTEL_GEN(dev_priv) >= 6 &&
2375 dev_priv->rps.enabled &&
2376 dev_priv->gt.active_engines) {
2377 u32 rpup, rpupei;
2378 u32 rpdown, rpdownei;
2379
2380 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2381 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2382 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2383 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2384 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2385 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2386
2387 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2388 rps_power_to_str(dev_priv->rps.power));
2389 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2390 100 * rpup / rpupei,
2391 dev_priv->rps.up_threshold);
2392 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2393 100 * rpdown / rpdownei,
2394 dev_priv->rps.down_threshold);
2395 } else {
2396 seq_puts(m, "\nRPS Autotuning inactive\n");
2397 }
2398
2399 return 0;
2400}
2401
2402static int i915_llc(struct seq_file *m, void *data)
2403{
2404 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2405 const bool edram = INTEL_GEN(dev_priv) > 8;
2406
2407 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2408 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2409 intel_uncore_edram_size(dev_priv)/1024/1024);
2410
2411 return 0;
2412}
2413
2414static int i915_guc_load_status_info(struct seq_file *m, void *data)
2415{
2416 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2417 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2418 u32 tmp, i;
2419
2420 if (!HAS_GUC_UCODE(dev_priv))
2421 return 0;
2422
2423 seq_printf(m, "GuC firmware status:\n");
2424 seq_printf(m, "\tpath: %s\n",
2425 guc_fw->guc_fw_path);
2426 seq_printf(m, "\tfetch: %s\n",
2427 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2428 seq_printf(m, "\tload: %s\n",
2429 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2430 seq_printf(m, "\tversion wanted: %d.%d\n",
2431 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2432 seq_printf(m, "\tversion found: %d.%d\n",
2433 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2434 seq_printf(m, "\theader: offset is %d; size = %d\n",
2435 guc_fw->header_offset, guc_fw->header_size);
2436 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2437 guc_fw->ucode_offset, guc_fw->ucode_size);
2438 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2439 guc_fw->rsa_offset, guc_fw->rsa_size);
2440
2441 tmp = I915_READ(GUC_STATUS);
2442
2443 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2444 seq_printf(m, "\tBootrom status = 0x%x\n",
2445 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2446 seq_printf(m, "\tuKernel status = 0x%x\n",
2447 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2448 seq_printf(m, "\tMIA Core status = 0x%x\n",
2449 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2450 seq_puts(m, "\nScratch registers:\n");
2451 for (i = 0; i < 16; i++)
2452 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2453
2454 return 0;
2455}
2456
2457static void i915_guc_client_info(struct seq_file *m,
2458 struct drm_i915_private *dev_priv,
2459 struct i915_guc_client *client)
2460{
2461 struct intel_engine_cs *engine;
2462 enum intel_engine_id id;
2463 uint64_t tot = 0;
2464
2465 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2466 client->priority, client->ctx_index, client->proc_desc_offset);
2467 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2468 client->doorbell_id, client->doorbell_offset, client->cookie);
2469 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2470 client->wq_size, client->wq_offset, client->wq_tail);
2471
2472 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2473 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2474 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2475
2476 for_each_engine_id(engine, dev_priv, id) {
2477 u64 submissions = client->submissions[id];
2478 tot += submissions;
2479 seq_printf(m, "\tSubmissions: %llu %s\n",
2480 submissions, engine->name);
2481 }
2482 seq_printf(m, "\tTotal: %llu\n", tot);
2483}
2484
2485static int i915_guc_info(struct seq_file *m, void *data)
2486{
2487 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2488 struct drm_device *dev = &dev_priv->drm;
2489 struct intel_guc guc;
2490 struct i915_guc_client client = {};
2491 struct intel_engine_cs *engine;
2492 enum intel_engine_id id;
2493 u64 total = 0;
2494
2495 if (!HAS_GUC_SCHED(dev_priv))
2496 return 0;
2497
2498 if (mutex_lock_interruptible(&dev->struct_mutex))
2499 return 0;
2500
2501 /* Take a local copy of the GuC data, so we can dump it at leisure */
2502 guc = dev_priv->guc;
2503 if (guc.execbuf_client)
2504 client = *guc.execbuf_client;
2505
2506 mutex_unlock(&dev->struct_mutex);
2507
2508 seq_printf(m, "Doorbell map:\n");
2509 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2510 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2511
2512 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2513 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2514 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2515 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2516 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2517
2518 seq_printf(m, "\nGuC submissions:\n");
2519 for_each_engine_id(engine, dev_priv, id) {
2520 u64 submissions = guc.submissions[id];
2521 total += submissions;
2522 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2523 engine->name, submissions, guc.last_seqno[id]);
2524 }
2525 seq_printf(m, "\t%s: %llu\n", "Total", total);
2526
2527 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2528 i915_guc_client_info(m, dev_priv, &client);
2529
2530 /* Add more as required ... */
2531
2532 return 0;
2533}
2534
2535static int i915_guc_log_dump(struct seq_file *m, void *data)
2536{
2537 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2538 struct drm_i915_gem_object *obj;
2539 int i = 0, pg;
2540
2541 if (!dev_priv->guc.log_vma)
2542 return 0;
2543
2544 obj = dev_priv->guc.log_vma->obj;
2545 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2546 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2547
2548 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2549 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2550 *(log + i), *(log + i + 1),
2551 *(log + i + 2), *(log + i + 3));
2552
2553 kunmap_atomic(log);
2554 }
2555
2556 seq_putc(m, '\n');
2557
2558 return 0;
2559}
2560
2561static int i915_edp_psr_status(struct seq_file *m, void *data)
2562{
2563 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2564 u32 psrperf = 0;
2565 u32 stat[3];
2566 enum pipe pipe;
2567 bool enabled = false;
2568
2569 if (!HAS_PSR(dev_priv)) {
2570 seq_puts(m, "PSR not supported\n");
2571 return 0;
2572 }
2573
2574 intel_runtime_pm_get(dev_priv);
2575
2576 mutex_lock(&dev_priv->psr.lock);
2577 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2578 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2579 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2580 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2581 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2582 dev_priv->psr.busy_frontbuffer_bits);
2583 seq_printf(m, "Re-enable work scheduled: %s\n",
2584 yesno(work_busy(&dev_priv->psr.work.work)));
2585
2586 if (HAS_DDI(dev_priv))
2587 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2588 else {
2589 for_each_pipe(dev_priv, pipe) {
2590 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2591 VLV_EDP_PSR_CURR_STATE_MASK;
2592 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2593 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2594 enabled = true;
2595 }
2596 }
2597
2598 seq_printf(m, "Main link in standby mode: %s\n",
2599 yesno(dev_priv->psr.link_standby));
2600
2601 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2602
2603 if (!HAS_DDI(dev_priv))
2604 for_each_pipe(dev_priv, pipe) {
2605 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2606 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2607 seq_printf(m, " pipe %c", pipe_name(pipe));
2608 }
2609 seq_puts(m, "\n");
2610
2611 /*
2612 * VLV/CHV PSR has no kind of performance counter
2613 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2614 */
2615 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2616 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2617 EDP_PSR_PERF_CNT_MASK;
2618
2619 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2620 }
2621 mutex_unlock(&dev_priv->psr.lock);
2622
2623 intel_runtime_pm_put(dev_priv);
2624 return 0;
2625}
2626
2627static int i915_sink_crc(struct seq_file *m, void *data)
2628{
2629 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2630 struct drm_device *dev = &dev_priv->drm;
2631 struct intel_connector *connector;
2632 struct intel_dp *intel_dp = NULL;
2633 int ret;
2634 u8 crc[6];
2635
2636 drm_modeset_lock_all(dev);
2637 for_each_intel_connector(dev, connector) {
2638 struct drm_crtc *crtc;
2639
2640 if (!connector->base.state->best_encoder)
2641 continue;
2642
2643 crtc = connector->base.state->crtc;
2644 if (!crtc->state->active)
2645 continue;
2646
2647 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2648 continue;
2649
2650 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2651
2652 ret = intel_dp_sink_crc(intel_dp, crc);
2653 if (ret)
2654 goto out;
2655
2656 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2657 crc[0], crc[1], crc[2],
2658 crc[3], crc[4], crc[5]);
2659 goto out;
2660 }
2661 ret = -ENODEV;
2662out:
2663 drm_modeset_unlock_all(dev);
2664 return ret;
2665}
2666
2667static int i915_energy_uJ(struct seq_file *m, void *data)
2668{
2669 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2670 u64 power;
2671 u32 units;
2672
2673 if (INTEL_GEN(dev_priv) < 6)
2674 return -ENODEV;
2675
2676 intel_runtime_pm_get(dev_priv);
2677
2678 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2679 power = (power & 0x1f00) >> 8;
2680 units = 1000000 / (1 << power); /* convert to uJ */
2681 power = I915_READ(MCH_SECP_NRG_STTS);
2682 power *= units;
2683
2684 intel_runtime_pm_put(dev_priv);
2685
2686 seq_printf(m, "%llu", (long long unsigned)power);
2687
2688 return 0;
2689}
2690
2691static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2692{
2693 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2694 struct pci_dev *pdev = dev_priv->drm.pdev;
2695
2696 if (!HAS_RUNTIME_PM(dev_priv))
2697 seq_puts(m, "Runtime power management not supported\n");
2698
2699 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2700 seq_printf(m, "IRQs disabled: %s\n",
2701 yesno(!intel_irqs_enabled(dev_priv)));
2702#ifdef CONFIG_PM
2703 seq_printf(m, "Usage count: %d\n",
2704 atomic_read(&dev_priv->drm.dev->power.usage_count));
2705#else
2706 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2707#endif
2708 seq_printf(m, "PCI device power state: %s [%d]\n",
2709 pci_power_name(pdev->current_state),
2710 pdev->current_state);
2711
2712 return 0;
2713}
2714
2715static int i915_power_domain_info(struct seq_file *m, void *unused)
2716{
2717 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2718 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2719 int i;
2720
2721 mutex_lock(&power_domains->lock);
2722
2723 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2724 for (i = 0; i < power_domains->power_well_count; i++) {
2725 struct i915_power_well *power_well;
2726 enum intel_display_power_domain power_domain;
2727
2728 power_well = &power_domains->power_wells[i];
2729 seq_printf(m, "%-25s %d\n", power_well->name,
2730 power_well->count);
2731
2732 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2733 power_domain++) {
2734 if (!(BIT(power_domain) & power_well->domains))
2735 continue;
2736
2737 seq_printf(m, " %-23s %d\n",
2738 intel_display_power_domain_str(power_domain),
2739 power_domains->domain_use_count[power_domain]);
2740 }
2741 }
2742
2743 mutex_unlock(&power_domains->lock);
2744
2745 return 0;
2746}
2747
2748static int i915_dmc_info(struct seq_file *m, void *unused)
2749{
2750 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2751 struct intel_csr *csr;
2752
2753 if (!HAS_CSR(dev_priv)) {
2754 seq_puts(m, "not supported\n");
2755 return 0;
2756 }
2757
2758 csr = &dev_priv->csr;
2759
2760 intel_runtime_pm_get(dev_priv);
2761
2762 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2763 seq_printf(m, "path: %s\n", csr->fw_path);
2764
2765 if (!csr->dmc_payload)
2766 goto out;
2767
2768 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2769 CSR_VERSION_MINOR(csr->version));
2770
2771 if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2772 seq_printf(m, "DC3 -> DC5 count: %d\n",
2773 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2774 seq_printf(m, "DC5 -> DC6 count: %d\n",
2775 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2776 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2777 seq_printf(m, "DC3 -> DC5 count: %d\n",
2778 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2779 }
2780
2781out:
2782 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2783 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2784 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2785
2786 intel_runtime_pm_put(dev_priv);
2787
2788 return 0;
2789}
2790
2791static void intel_seq_print_mode(struct seq_file *m, int tabs,
2792 struct drm_display_mode *mode)
2793{
2794 int i;
2795
2796 for (i = 0; i < tabs; i++)
2797 seq_putc(m, '\t');
2798
2799 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800 mode->base.id, mode->name,
2801 mode->vrefresh, mode->clock,
2802 mode->hdisplay, mode->hsync_start,
2803 mode->hsync_end, mode->htotal,
2804 mode->vdisplay, mode->vsync_start,
2805 mode->vsync_end, mode->vtotal,
2806 mode->type, mode->flags);
2807}
2808
2809static void intel_encoder_info(struct seq_file *m,
2810 struct intel_crtc *intel_crtc,
2811 struct intel_encoder *intel_encoder)
2812{
2813 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2814 struct drm_device *dev = &dev_priv->drm;
2815 struct drm_crtc *crtc = &intel_crtc->base;
2816 struct intel_connector *intel_connector;
2817 struct drm_encoder *encoder;
2818
2819 encoder = &intel_encoder->base;
2820 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2821 encoder->base.id, encoder->name);
2822 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2823 struct drm_connector *connector = &intel_connector->base;
2824 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2825 connector->base.id,
2826 connector->name,
2827 drm_get_connector_status_name(connector->status));
2828 if (connector->status == connector_status_connected) {
2829 struct drm_display_mode *mode = &crtc->mode;
2830 seq_printf(m, ", mode:\n");
2831 intel_seq_print_mode(m, 2, mode);
2832 } else {
2833 seq_putc(m, '\n');
2834 }
2835 }
2836}
2837
2838static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2839{
2840 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2841 struct drm_device *dev = &dev_priv->drm;
2842 struct drm_crtc *crtc = &intel_crtc->base;
2843 struct intel_encoder *intel_encoder;
2844 struct drm_plane_state *plane_state = crtc->primary->state;
2845 struct drm_framebuffer *fb = plane_state->fb;
2846
2847 if (fb)
2848 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2849 fb->base.id, plane_state->src_x >> 16,
2850 plane_state->src_y >> 16, fb->width, fb->height);
2851 else
2852 seq_puts(m, "\tprimary plane disabled\n");
2853 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2854 intel_encoder_info(m, intel_crtc, intel_encoder);
2855}
2856
2857static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2858{
2859 struct drm_display_mode *mode = panel->fixed_mode;
2860
2861 seq_printf(m, "\tfixed mode:\n");
2862 intel_seq_print_mode(m, 2, mode);
2863}
2864
2865static void intel_dp_info(struct seq_file *m,
2866 struct intel_connector *intel_connector)
2867{
2868 struct intel_encoder *intel_encoder = intel_connector->encoder;
2869 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2870
2871 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2872 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2873 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2874 intel_panel_info(m, &intel_connector->panel);
2875}
2876
2877static void intel_hdmi_info(struct seq_file *m,
2878 struct intel_connector *intel_connector)
2879{
2880 struct intel_encoder *intel_encoder = intel_connector->encoder;
2881 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2882
2883 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2884}
2885
2886static void intel_lvds_info(struct seq_file *m,
2887 struct intel_connector *intel_connector)
2888{
2889 intel_panel_info(m, &intel_connector->panel);
2890}
2891
2892static void intel_connector_info(struct seq_file *m,
2893 struct drm_connector *connector)
2894{
2895 struct intel_connector *intel_connector = to_intel_connector(connector);
2896 struct intel_encoder *intel_encoder = intel_connector->encoder;
2897 struct drm_display_mode *mode;
2898
2899 seq_printf(m, "connector %d: type %s, status: %s\n",
2900 connector->base.id, connector->name,
2901 drm_get_connector_status_name(connector->status));
2902 if (connector->status == connector_status_connected) {
2903 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2904 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2905 connector->display_info.width_mm,
2906 connector->display_info.height_mm);
2907 seq_printf(m, "\tsubpixel order: %s\n",
2908 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2909 seq_printf(m, "\tCEA rev: %d\n",
2910 connector->display_info.cea_rev);
2911 }
2912
2913 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2914 return;
2915
2916 switch (connector->connector_type) {
2917 case DRM_MODE_CONNECTOR_DisplayPort:
2918 case DRM_MODE_CONNECTOR_eDP:
2919 intel_dp_info(m, intel_connector);
2920 break;
2921 case DRM_MODE_CONNECTOR_LVDS:
2922 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2923 intel_lvds_info(m, intel_connector);
2924 break;
2925 case DRM_MODE_CONNECTOR_HDMIA:
2926 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2927 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2928 intel_hdmi_info(m, intel_connector);
2929 break;
2930 default:
2931 break;
2932 }
2933
2934 seq_printf(m, "\tmodes:\n");
2935 list_for_each_entry(mode, &connector->modes, head)
2936 intel_seq_print_mode(m, 2, mode);
2937}
2938
2939static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2940{
2941 u32 state;
2942
2943 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2944 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2945 else
2946 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2947
2948 return state;
2949}
2950
2951static bool cursor_position(struct drm_i915_private *dev_priv,
2952 int pipe, int *x, int *y)
2953{
2954 u32 pos;
2955
2956 pos = I915_READ(CURPOS(pipe));
2957
2958 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2959 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2960 *x = -*x;
2961
2962 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2963 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2964 *y = -*y;
2965
2966 return cursor_active(dev_priv, pipe);
2967}
2968
2969static const char *plane_type(enum drm_plane_type type)
2970{
2971 switch (type) {
2972 case DRM_PLANE_TYPE_OVERLAY:
2973 return "OVL";
2974 case DRM_PLANE_TYPE_PRIMARY:
2975 return "PRI";
2976 case DRM_PLANE_TYPE_CURSOR:
2977 return "CUR";
2978 /*
2979 * Deliberately omitting default: to generate compiler warnings
2980 * when a new drm_plane_type gets added.
2981 */
2982 }
2983
2984 return "unknown";
2985}
2986
2987static const char *plane_rotation(unsigned int rotation)
2988{
2989 static char buf[48];
2990 /*
2991 * According to doc only one DRM_ROTATE_ is allowed but this
2992 * will print them all to visualize if the values are misused
2993 */
2994 snprintf(buf, sizeof(buf),
2995 "%s%s%s%s%s%s(0x%08x)",
2996 (rotation & DRM_ROTATE_0) ? "0 " : "",
2997 (rotation & DRM_ROTATE_90) ? "90 " : "",
2998 (rotation & DRM_ROTATE_180) ? "180 " : "",
2999 (rotation & DRM_ROTATE_270) ? "270 " : "",
3000 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3001 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3002 rotation);
3003
3004 return buf;
3005}
3006
3007static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3008{
3009 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3010 struct drm_device *dev = &dev_priv->drm;
3011 struct intel_plane *intel_plane;
3012
3013 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3014 struct drm_plane_state *state;
3015 struct drm_plane *plane = &intel_plane->base;
3016
3017 if (!plane->state) {
3018 seq_puts(m, "plane->state is NULL!\n");
3019 continue;
3020 }
3021
3022 state = plane->state;
3023
3024 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3025 plane->base.id,
3026 plane_type(intel_plane->base.type),
3027 state->crtc_x, state->crtc_y,
3028 state->crtc_w, state->crtc_h,
3029 (state->src_x >> 16),
3030 ((state->src_x & 0xffff) * 15625) >> 10,
3031 (state->src_y >> 16),
3032 ((state->src_y & 0xffff) * 15625) >> 10,
3033 (state->src_w >> 16),
3034 ((state->src_w & 0xffff) * 15625) >> 10,
3035 (state->src_h >> 16),
3036 ((state->src_h & 0xffff) * 15625) >> 10,
3037 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3038 plane_rotation(state->rotation));
3039 }
3040}
3041
3042static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3043{
3044 struct intel_crtc_state *pipe_config;
3045 int num_scalers = intel_crtc->num_scalers;
3046 int i;
3047
3048 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3049
3050 /* Not all platformas have a scaler */
3051 if (num_scalers) {
3052 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3053 num_scalers,
3054 pipe_config->scaler_state.scaler_users,
3055 pipe_config->scaler_state.scaler_id);
3056
3057 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3058 struct intel_scaler *sc =
3059 &pipe_config->scaler_state.scalers[i];
3060
3061 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3062 i, yesno(sc->in_use), sc->mode);
3063 }
3064 seq_puts(m, "\n");
3065 } else {
3066 seq_puts(m, "\tNo scalers available on this platform\n");
3067 }
3068}
3069
3070static int i915_display_info(struct seq_file *m, void *unused)
3071{
3072 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3073 struct drm_device *dev = &dev_priv->drm;
3074 struct intel_crtc *crtc;
3075 struct drm_connector *connector;
3076
3077 intel_runtime_pm_get(dev_priv);
3078 drm_modeset_lock_all(dev);
3079 seq_printf(m, "CRTC info\n");
3080 seq_printf(m, "---------\n");
3081 for_each_intel_crtc(dev, crtc) {
3082 bool active;
3083 struct intel_crtc_state *pipe_config;
3084 int x, y;
3085
3086 pipe_config = to_intel_crtc_state(crtc->base.state);
3087
3088 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3089 crtc->base.base.id, pipe_name(crtc->pipe),
3090 yesno(pipe_config->base.active),
3091 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3092 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3093
3094 if (pipe_config->base.active) {
3095 intel_crtc_info(m, crtc);
3096
3097 active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3098 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3099 yesno(crtc->cursor_base),
3100 x, y, crtc->base.cursor->state->crtc_w,
3101 crtc->base.cursor->state->crtc_h,
3102 crtc->cursor_addr, yesno(active));
3103 intel_scaler_info(m, crtc);
3104 intel_plane_info(m, crtc);
3105 }
3106
3107 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3108 yesno(!crtc->cpu_fifo_underrun_disabled),
3109 yesno(!crtc->pch_fifo_underrun_disabled));
3110 }
3111
3112 seq_printf(m, "\n");
3113 seq_printf(m, "Connector info\n");
3114 seq_printf(m, "--------------\n");
3115 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3116 intel_connector_info(m, connector);
3117 }
3118 drm_modeset_unlock_all(dev);
3119 intel_runtime_pm_put(dev_priv);
3120
3121 return 0;
3122}
3123
3124static int i915_semaphore_status(struct seq_file *m, void *unused)
3125{
3126 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3127 struct drm_device *dev = &dev_priv->drm;
3128 struct intel_engine_cs *engine;
3129 int num_rings = INTEL_INFO(dev_priv)->num_rings;
3130 enum intel_engine_id id;
3131 int j, ret;
3132
3133 if (!i915.semaphores) {
3134 seq_puts(m, "Semaphores are disabled\n");
3135 return 0;
3136 }
3137
3138 ret = mutex_lock_interruptible(&dev->struct_mutex);
3139 if (ret)
3140 return ret;
3141 intel_runtime_pm_get(dev_priv);
3142
3143 if (IS_BROADWELL(dev_priv)) {
3144 struct page *page;
3145 uint64_t *seqno;
3146
3147 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3148
3149 seqno = (uint64_t *)kmap_atomic(page);
3150 for_each_engine_id(engine, dev_priv, id) {
3151 uint64_t offset;
3152
3153 seq_printf(m, "%s\n", engine->name);
3154
3155 seq_puts(m, " Last signal:");
3156 for (j = 0; j < num_rings; j++) {
3157 offset = id * I915_NUM_ENGINES + j;
3158 seq_printf(m, "0x%08llx (0x%02llx) ",
3159 seqno[offset], offset * 8);
3160 }
3161 seq_putc(m, '\n');
3162
3163 seq_puts(m, " Last wait: ");
3164 for (j = 0; j < num_rings; j++) {
3165 offset = id + (j * I915_NUM_ENGINES);
3166 seq_printf(m, "0x%08llx (0x%02llx) ",
3167 seqno[offset], offset * 8);
3168 }
3169 seq_putc(m, '\n');
3170
3171 }
3172 kunmap_atomic(seqno);
3173 } else {
3174 seq_puts(m, " Last signal:");
3175 for_each_engine(engine, dev_priv)
3176 for (j = 0; j < num_rings; j++)
3177 seq_printf(m, "0x%08x\n",
3178 I915_READ(engine->semaphore.mbox.signal[j]));
3179 seq_putc(m, '\n');
3180 }
3181
3182 seq_puts(m, "\nSync seqno:\n");
3183 for_each_engine(engine, dev_priv) {
3184 for (j = 0; j < num_rings; j++)
3185 seq_printf(m, " 0x%08x ",
3186 engine->semaphore.sync_seqno[j]);
3187 seq_putc(m, '\n');
3188 }
3189 seq_putc(m, '\n');
3190
3191 intel_runtime_pm_put(dev_priv);
3192 mutex_unlock(&dev->struct_mutex);
3193 return 0;
3194}
3195
3196static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3197{
3198 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3199 struct drm_device *dev = &dev_priv->drm;
3200 int i;
3201
3202 drm_modeset_lock_all(dev);
3203 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3204 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3205
3206 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3207 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3208 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3209 seq_printf(m, " tracked hardware state:\n");
3210 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3211 seq_printf(m, " dpll_md: 0x%08x\n",
3212 pll->config.hw_state.dpll_md);
3213 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3214 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3215 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3216 }
3217 drm_modeset_unlock_all(dev);
3218
3219 return 0;
3220}
3221
3222static int i915_wa_registers(struct seq_file *m, void *unused)
3223{
3224 int i;
3225 int ret;
3226 struct intel_engine_cs *engine;
3227 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3228 struct drm_device *dev = &dev_priv->drm;
3229 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3230 enum intel_engine_id id;
3231
3232 ret = mutex_lock_interruptible(&dev->struct_mutex);
3233 if (ret)
3234 return ret;
3235
3236 intel_runtime_pm_get(dev_priv);
3237
3238 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3239 for_each_engine_id(engine, dev_priv, id)
3240 seq_printf(m, "HW whitelist count for %s: %d\n",
3241 engine->name, workarounds->hw_whitelist_count[id]);
3242 for (i = 0; i < workarounds->count; ++i) {
3243 i915_reg_t addr;
3244 u32 mask, value, read;
3245 bool ok;
3246
3247 addr = workarounds->reg[i].addr;
3248 mask = workarounds->reg[i].mask;
3249 value = workarounds->reg[i].value;
3250 read = I915_READ(addr);
3251 ok = (value & mask) == (read & mask);
3252 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3253 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3254 }
3255
3256 intel_runtime_pm_put(dev_priv);
3257 mutex_unlock(&dev->struct_mutex);
3258
3259 return 0;
3260}
3261
3262static int i915_ddb_info(struct seq_file *m, void *unused)
3263{
3264 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3265 struct drm_device *dev = &dev_priv->drm;
3266 struct skl_ddb_allocation *ddb;
3267 struct skl_ddb_entry *entry;
3268 enum pipe pipe;
3269 int plane;
3270
3271 if (INTEL_GEN(dev_priv) < 9)
3272 return 0;
3273
3274 drm_modeset_lock_all(dev);
3275
3276 ddb = &dev_priv->wm.skl_hw.ddb;
3277
3278 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3279
3280 for_each_pipe(dev_priv, pipe) {
3281 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3282
3283 for_each_plane(dev_priv, pipe, plane) {
3284 entry = &ddb->plane[pipe][plane];
3285 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3286 entry->start, entry->end,
3287 skl_ddb_entry_size(entry));
3288 }
3289
3290 entry = &ddb->plane[pipe][PLANE_CURSOR];
3291 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3292 entry->end, skl_ddb_entry_size(entry));
3293 }
3294
3295 drm_modeset_unlock_all(dev);
3296
3297 return 0;
3298}
3299
3300static void drrs_status_per_crtc(struct seq_file *m,
3301 struct drm_device *dev,
3302 struct intel_crtc *intel_crtc)
3303{
3304 struct drm_i915_private *dev_priv = to_i915(dev);
3305 struct i915_drrs *drrs = &dev_priv->drrs;
3306 int vrefresh = 0;
3307 struct drm_connector *connector;
3308
3309 drm_for_each_connector(connector, dev) {
3310 if (connector->state->crtc != &intel_crtc->base)
3311 continue;
3312
3313 seq_printf(m, "%s:\n", connector->name);
3314 }
3315
3316 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3317 seq_puts(m, "\tVBT: DRRS_type: Static");
3318 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3319 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3320 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3321 seq_puts(m, "\tVBT: DRRS_type: None");
3322 else
3323 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3324
3325 seq_puts(m, "\n\n");
3326
3327 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3328 struct intel_panel *panel;
3329
3330 mutex_lock(&drrs->mutex);
3331 /* DRRS Supported */
3332 seq_puts(m, "\tDRRS Supported: Yes\n");
3333
3334 /* disable_drrs() will make drrs->dp NULL */
3335 if (!drrs->dp) {
3336 seq_puts(m, "Idleness DRRS: Disabled");
3337 mutex_unlock(&drrs->mutex);
3338 return;
3339 }
3340
3341 panel = &drrs->dp->attached_connector->panel;
3342 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3343 drrs->busy_frontbuffer_bits);
3344
3345 seq_puts(m, "\n\t\t");
3346 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3347 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3348 vrefresh = panel->fixed_mode->vrefresh;
3349 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3350 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3351 vrefresh = panel->downclock_mode->vrefresh;
3352 } else {
3353 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3354 drrs->refresh_rate_type);
3355 mutex_unlock(&drrs->mutex);
3356 return;
3357 }
3358 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3359
3360 seq_puts(m, "\n\t\t");
3361 mutex_unlock(&drrs->mutex);
3362 } else {
3363 /* DRRS not supported. Print the VBT parameter*/
3364 seq_puts(m, "\tDRRS Supported : No");
3365 }
3366 seq_puts(m, "\n");
3367}
3368
3369static int i915_drrs_status(struct seq_file *m, void *unused)
3370{
3371 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3372 struct drm_device *dev = &dev_priv->drm;
3373 struct intel_crtc *intel_crtc;
3374 int active_crtc_cnt = 0;
3375
3376 drm_modeset_lock_all(dev);
3377 for_each_intel_crtc(dev, intel_crtc) {
3378 if (intel_crtc->base.state->active) {
3379 active_crtc_cnt++;
3380 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3381
3382 drrs_status_per_crtc(m, dev, intel_crtc);
3383 }
3384 }
3385 drm_modeset_unlock_all(dev);
3386
3387 if (!active_crtc_cnt)
3388 seq_puts(m, "No active crtc found\n");
3389
3390 return 0;
3391}
3392
3393struct pipe_crc_info {
3394 const char *name;
3395 struct drm_i915_private *dev_priv;
3396 enum pipe pipe;
3397};
3398
3399static int i915_dp_mst_info(struct seq_file *m, void *unused)
3400{
3401 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3402 struct drm_device *dev = &dev_priv->drm;
3403 struct intel_encoder *intel_encoder;
3404 struct intel_digital_port *intel_dig_port;
3405 struct drm_connector *connector;
3406
3407 drm_modeset_lock_all(dev);
3408 drm_for_each_connector(connector, dev) {
3409 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3410 continue;
3411
3412 intel_encoder = intel_attached_encoder(connector);
3413 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3414 continue;
3415
3416 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3417 if (!intel_dig_port->dp.can_mst)
3418 continue;
3419
3420 seq_printf(m, "MST Source Port %c\n",
3421 port_name(intel_dig_port->port));
3422 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3423 }
3424 drm_modeset_unlock_all(dev);
3425 return 0;
3426}
3427
3428static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3429{
3430 struct pipe_crc_info *info = inode->i_private;
3431 struct drm_i915_private *dev_priv = info->dev_priv;
3432 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3433
3434 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3435 return -ENODEV;
3436
3437 spin_lock_irq(&pipe_crc->lock);
3438
3439 if (pipe_crc->opened) {
3440 spin_unlock_irq(&pipe_crc->lock);
3441 return -EBUSY; /* already open */
3442 }
3443
3444 pipe_crc->opened = true;
3445 filep->private_data = inode->i_private;
3446
3447 spin_unlock_irq(&pipe_crc->lock);
3448
3449 return 0;
3450}
3451
3452static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3453{
3454 struct pipe_crc_info *info = inode->i_private;
3455 struct drm_i915_private *dev_priv = info->dev_priv;
3456 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3457
3458 spin_lock_irq(&pipe_crc->lock);
3459 pipe_crc->opened = false;
3460 spin_unlock_irq(&pipe_crc->lock);
3461
3462 return 0;
3463}
3464
3465/* (6 fields, 8 chars each, space separated (5) + '\n') */
3466#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3467/* account for \'0' */
3468#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3469
3470static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3471{
3472 assert_spin_locked(&pipe_crc->lock);
3473 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3474 INTEL_PIPE_CRC_ENTRIES_NR);
3475}
3476
3477static ssize_t
3478i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3479 loff_t *pos)
3480{
3481 struct pipe_crc_info *info = filep->private_data;
3482 struct drm_i915_private *dev_priv = info->dev_priv;
3483 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3484 char buf[PIPE_CRC_BUFFER_LEN];
3485 int n_entries;
3486 ssize_t bytes_read;
3487
3488 /*
3489 * Don't allow user space to provide buffers not big enough to hold
3490 * a line of data.
3491 */
3492 if (count < PIPE_CRC_LINE_LEN)
3493 return -EINVAL;
3494
3495 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3496 return 0;
3497
3498 /* nothing to read */
3499 spin_lock_irq(&pipe_crc->lock);
3500 while (pipe_crc_data_count(pipe_crc) == 0) {
3501 int ret;
3502
3503 if (filep->f_flags & O_NONBLOCK) {
3504 spin_unlock_irq(&pipe_crc->lock);
3505 return -EAGAIN;
3506 }
3507
3508 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3509 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3510 if (ret) {
3511 spin_unlock_irq(&pipe_crc->lock);
3512 return ret;
3513 }
3514 }
3515
3516 /* We now have one or more entries to read */
3517 n_entries = count / PIPE_CRC_LINE_LEN;
3518
3519 bytes_read = 0;
3520 while (n_entries > 0) {
3521 struct intel_pipe_crc_entry *entry =
3522 &pipe_crc->entries[pipe_crc->tail];
3523
3524 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3525 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3526 break;
3527
3528 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3529 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3530
3531 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3532 "%8u %8x %8x %8x %8x %8x\n",
3533 entry->frame, entry->crc[0],
3534 entry->crc[1], entry->crc[2],
3535 entry->crc[3], entry->crc[4]);
3536
3537 spin_unlock_irq(&pipe_crc->lock);
3538
3539 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3540 return -EFAULT;
3541
3542 user_buf += PIPE_CRC_LINE_LEN;
3543 n_entries--;
3544
3545 spin_lock_irq(&pipe_crc->lock);
3546 }
3547
3548 spin_unlock_irq(&pipe_crc->lock);
3549
3550 return bytes_read;
3551}
3552
3553static const struct file_operations i915_pipe_crc_fops = {
3554 .owner = THIS_MODULE,
3555 .open = i915_pipe_crc_open,
3556 .read = i915_pipe_crc_read,
3557 .release = i915_pipe_crc_release,
3558};
3559
3560static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3561 {
3562 .name = "i915_pipe_A_crc",
3563 .pipe = PIPE_A,
3564 },
3565 {
3566 .name = "i915_pipe_B_crc",
3567 .pipe = PIPE_B,
3568 },
3569 {
3570 .name = "i915_pipe_C_crc",
3571 .pipe = PIPE_C,
3572 },
3573};
3574
3575static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3576 enum pipe pipe)
3577{
3578 struct drm_i915_private *dev_priv = to_i915(minor->dev);
3579 struct dentry *ent;
3580 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3581
3582 info->dev_priv = dev_priv;
3583 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3584 &i915_pipe_crc_fops);
3585 if (!ent)
3586 return -ENOMEM;
3587
3588 return drm_add_fake_info_node(minor, ent, info);
3589}
3590
3591static const char * const pipe_crc_sources[] = {
3592 "none",
3593 "plane1",
3594 "plane2",
3595 "pf",
3596 "pipe",
3597 "TV",
3598 "DP-B",
3599 "DP-C",
3600 "DP-D",
3601 "auto",
3602};
3603
3604static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3605{
3606 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3607 return pipe_crc_sources[source];
3608}
3609
3610static int display_crc_ctl_show(struct seq_file *m, void *data)
3611{
3612 struct drm_i915_private *dev_priv = m->private;
3613 int i;
3614
3615 for (i = 0; i < I915_MAX_PIPES; i++)
3616 seq_printf(m, "%c %s\n", pipe_name(i),
3617 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3618
3619 return 0;
3620}
3621
3622static int display_crc_ctl_open(struct inode *inode, struct file *file)
3623{
3624 return single_open(file, display_crc_ctl_show, inode->i_private);
3625}
3626
3627static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3628 uint32_t *val)
3629{
3630 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3631 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3632
3633 switch (*source) {
3634 case INTEL_PIPE_CRC_SOURCE_PIPE:
3635 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3636 break;
3637 case INTEL_PIPE_CRC_SOURCE_NONE:
3638 *val = 0;
3639 break;
3640 default:
3641 return -EINVAL;
3642 }
3643
3644 return 0;
3645}
3646
3647static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3648 enum pipe pipe,
3649 enum intel_pipe_crc_source *source)
3650{
3651 struct drm_device *dev = &dev_priv->drm;
3652 struct intel_encoder *encoder;
3653 struct intel_crtc *crtc;
3654 struct intel_digital_port *dig_port;
3655 int ret = 0;
3656
3657 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3658
3659 drm_modeset_lock_all(dev);
3660 for_each_intel_encoder(dev, encoder) {
3661 if (!encoder->base.crtc)
3662 continue;
3663
3664 crtc = to_intel_crtc(encoder->base.crtc);
3665
3666 if (crtc->pipe != pipe)
3667 continue;
3668
3669 switch (encoder->type) {
3670 case INTEL_OUTPUT_TVOUT:
3671 *source = INTEL_PIPE_CRC_SOURCE_TV;
3672 break;
3673 case INTEL_OUTPUT_DP:
3674 case INTEL_OUTPUT_EDP:
3675 dig_port = enc_to_dig_port(&encoder->base);
3676 switch (dig_port->port) {
3677 case PORT_B:
3678 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3679 break;
3680 case PORT_C:
3681 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3682 break;
3683 case PORT_D:
3684 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3685 break;
3686 default:
3687 WARN(1, "nonexisting DP port %c\n",
3688 port_name(dig_port->port));
3689 break;
3690 }
3691 break;
3692 default:
3693 break;
3694 }
3695 }
3696 drm_modeset_unlock_all(dev);
3697
3698 return ret;
3699}
3700
3701static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3702 enum pipe pipe,
3703 enum intel_pipe_crc_source *source,
3704 uint32_t *val)
3705{
3706 bool need_stable_symbols = false;
3707
3708 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3709 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3710 if (ret)
3711 return ret;
3712 }
3713
3714 switch (*source) {
3715 case INTEL_PIPE_CRC_SOURCE_PIPE:
3716 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3717 break;
3718 case INTEL_PIPE_CRC_SOURCE_DP_B:
3719 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3720 need_stable_symbols = true;
3721 break;
3722 case INTEL_PIPE_CRC_SOURCE_DP_C:
3723 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3724 need_stable_symbols = true;
3725 break;
3726 case INTEL_PIPE_CRC_SOURCE_DP_D:
3727 if (!IS_CHERRYVIEW(dev_priv))
3728 return -EINVAL;
3729 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3730 need_stable_symbols = true;
3731 break;
3732 case INTEL_PIPE_CRC_SOURCE_NONE:
3733 *val = 0;
3734 break;
3735 default:
3736 return -EINVAL;
3737 }
3738
3739 /*
3740 * When the pipe CRC tap point is after the transcoders we need
3741 * to tweak symbol-level features to produce a deterministic series of
3742 * symbols for a given frame. We need to reset those features only once
3743 * a frame (instead of every nth symbol):
3744 * - DC-balance: used to ensure a better clock recovery from the data
3745 * link (SDVO)
3746 * - DisplayPort scrambling: used for EMI reduction
3747 */
3748 if (need_stable_symbols) {
3749 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3750
3751 tmp |= DC_BALANCE_RESET_VLV;
3752 switch (pipe) {
3753 case PIPE_A:
3754 tmp |= PIPE_A_SCRAMBLE_RESET;
3755 break;
3756 case PIPE_B:
3757 tmp |= PIPE_B_SCRAMBLE_RESET;
3758 break;
3759 case PIPE_C:
3760 tmp |= PIPE_C_SCRAMBLE_RESET;
3761 break;
3762 default:
3763 return -EINVAL;
3764 }
3765 I915_WRITE(PORT_DFT2_G4X, tmp);
3766 }
3767
3768 return 0;
3769}
3770
3771static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3772 enum pipe pipe,
3773 enum intel_pipe_crc_source *source,
3774 uint32_t *val)
3775{
3776 bool need_stable_symbols = false;
3777
3778 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3779 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3780 if (ret)
3781 return ret;
3782 }
3783
3784 switch (*source) {
3785 case INTEL_PIPE_CRC_SOURCE_PIPE:
3786 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3787 break;
3788 case INTEL_PIPE_CRC_SOURCE_TV:
3789 if (!SUPPORTS_TV(dev_priv))
3790 return -EINVAL;
3791 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3792 break;
3793 case INTEL_PIPE_CRC_SOURCE_DP_B:
3794 if (!IS_G4X(dev_priv))
3795 return -EINVAL;
3796 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3797 need_stable_symbols = true;
3798 break;
3799 case INTEL_PIPE_CRC_SOURCE_DP_C:
3800 if (!IS_G4X(dev_priv))
3801 return -EINVAL;
3802 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3803 need_stable_symbols = true;
3804 break;
3805 case INTEL_PIPE_CRC_SOURCE_DP_D:
3806 if (!IS_G4X(dev_priv))
3807 return -EINVAL;
3808 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3809 need_stable_symbols = true;
3810 break;
3811 case INTEL_PIPE_CRC_SOURCE_NONE:
3812 *val = 0;
3813 break;
3814 default:
3815 return -EINVAL;
3816 }
3817
3818 /*
3819 * When the pipe CRC tap point is after the transcoders we need
3820 * to tweak symbol-level features to produce a deterministic series of
3821 * symbols for a given frame. We need to reset those features only once
3822 * a frame (instead of every nth symbol):
3823 * - DC-balance: used to ensure a better clock recovery from the data
3824 * link (SDVO)
3825 * - DisplayPort scrambling: used for EMI reduction
3826 */
3827 if (need_stable_symbols) {
3828 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3829
3830 WARN_ON(!IS_G4X(dev_priv));
3831
3832 I915_WRITE(PORT_DFT_I9XX,
3833 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3834
3835 if (pipe == PIPE_A)
3836 tmp |= PIPE_A_SCRAMBLE_RESET;
3837 else
3838 tmp |= PIPE_B_SCRAMBLE_RESET;
3839
3840 I915_WRITE(PORT_DFT2_G4X, tmp);
3841 }
3842
3843 return 0;
3844}
3845
3846static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3847 enum pipe pipe)
3848{
3849 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3850
3851 switch (pipe) {
3852 case PIPE_A:
3853 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3854 break;
3855 case PIPE_B:
3856 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3857 break;
3858 case PIPE_C:
3859 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3860 break;
3861 default:
3862 return;
3863 }
3864 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3865 tmp &= ~DC_BALANCE_RESET_VLV;
3866 I915_WRITE(PORT_DFT2_G4X, tmp);
3867
3868}
3869
3870static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3871 enum pipe pipe)
3872{
3873 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3874
3875 if (pipe == PIPE_A)
3876 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3877 else
3878 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3879 I915_WRITE(PORT_DFT2_G4X, tmp);
3880
3881 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3882 I915_WRITE(PORT_DFT_I9XX,
3883 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3884 }
3885}
3886
3887static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3888 uint32_t *val)
3889{
3890 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3891 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3892
3893 switch (*source) {
3894 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3895 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3896 break;
3897 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3898 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3899 break;
3900 case INTEL_PIPE_CRC_SOURCE_PIPE:
3901 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3902 break;
3903 case INTEL_PIPE_CRC_SOURCE_NONE:
3904 *val = 0;
3905 break;
3906 default:
3907 return -EINVAL;
3908 }
3909
3910 return 0;
3911}
3912
3913static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
3914 bool enable)
3915{
3916 struct drm_device *dev = &dev_priv->drm;
3917 struct intel_crtc *crtc =
3918 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3919 struct intel_crtc_state *pipe_config;
3920 struct drm_atomic_state *state;
3921 int ret = 0;
3922
3923 drm_modeset_lock_all(dev);
3924 state = drm_atomic_state_alloc(dev);
3925 if (!state) {
3926 ret = -ENOMEM;
3927 goto out;
3928 }
3929
3930 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3931 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3932 if (IS_ERR(pipe_config)) {
3933 ret = PTR_ERR(pipe_config);
3934 goto out;
3935 }
3936
3937 pipe_config->pch_pfit.force_thru = enable;
3938 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3939 pipe_config->pch_pfit.enabled != enable)
3940 pipe_config->base.connectors_changed = true;
3941
3942 ret = drm_atomic_commit(state);
3943out:
3944 drm_modeset_unlock_all(dev);
3945 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3946 if (ret)
3947 drm_atomic_state_free(state);
3948}
3949
3950static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3951 enum pipe pipe,
3952 enum intel_pipe_crc_source *source,
3953 uint32_t *val)
3954{
3955 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3956 *source = INTEL_PIPE_CRC_SOURCE_PF;
3957
3958 switch (*source) {
3959 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3960 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3961 break;
3962 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3963 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3964 break;
3965 case INTEL_PIPE_CRC_SOURCE_PF:
3966 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
3967 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
3968
3969 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3970 break;
3971 case INTEL_PIPE_CRC_SOURCE_NONE:
3972 *val = 0;
3973 break;
3974 default:
3975 return -EINVAL;
3976 }
3977
3978 return 0;
3979}
3980
3981static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
3982 enum pipe pipe,
3983 enum intel_pipe_crc_source source)
3984{
3985 struct drm_device *dev = &dev_priv->drm;
3986 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3987 struct intel_crtc *crtc =
3988 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
3989 enum intel_display_power_domain power_domain;
3990 u32 val = 0; /* shut up gcc */
3991 int ret;
3992
3993 if (pipe_crc->source == source)
3994 return 0;
3995
3996 /* forbid changing the source without going back to 'none' */
3997 if (pipe_crc->source && source)
3998 return -EINVAL;
3999
4000 power_domain = POWER_DOMAIN_PIPE(pipe);
4001 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4002 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4003 return -EIO;
4004 }
4005
4006 if (IS_GEN2(dev_priv))
4007 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4008 else if (INTEL_GEN(dev_priv) < 5)
4009 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4010 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4011 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4012 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4013 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4014 else
4015 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4016
4017 if (ret != 0)
4018 goto out;
4019
4020 /* none -> real source transition */
4021 if (source) {
4022 struct intel_pipe_crc_entry *entries;
4023
4024 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4025 pipe_name(pipe), pipe_crc_source_name(source));
4026
4027 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4028 sizeof(pipe_crc->entries[0]),
4029 GFP_KERNEL);
4030 if (!entries) {
4031 ret = -ENOMEM;
4032 goto out;
4033 }
4034
4035 /*
4036 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4037 * enabled and disabled dynamically based on package C states,
4038 * user space can't make reliable use of the CRCs, so let's just
4039 * completely disable it.
4040 */
4041 hsw_disable_ips(crtc);
4042
4043 spin_lock_irq(&pipe_crc->lock);
4044 kfree(pipe_crc->entries);
4045 pipe_crc->entries = entries;
4046 pipe_crc->head = 0;
4047 pipe_crc->tail = 0;
4048 spin_unlock_irq(&pipe_crc->lock);
4049 }
4050
4051 pipe_crc->source = source;
4052
4053 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4054 POSTING_READ(PIPE_CRC_CTL(pipe));
4055
4056 /* real source -> none transition */
4057 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4058 struct intel_pipe_crc_entry *entries;
4059 struct intel_crtc *crtc =
4060 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4061
4062 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4063 pipe_name(pipe));
4064
4065 drm_modeset_lock(&crtc->base.mutex, NULL);
4066 if (crtc->base.state->active)
4067 intel_wait_for_vblank(dev, pipe);
4068 drm_modeset_unlock(&crtc->base.mutex);
4069
4070 spin_lock_irq(&pipe_crc->lock);
4071 entries = pipe_crc->entries;
4072 pipe_crc->entries = NULL;
4073 pipe_crc->head = 0;
4074 pipe_crc->tail = 0;
4075 spin_unlock_irq(&pipe_crc->lock);
4076
4077 kfree(entries);
4078
4079 if (IS_G4X(dev_priv))
4080 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4081 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4082 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4083 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4084 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4085
4086 hsw_enable_ips(crtc);
4087 }
4088
4089 ret = 0;
4090
4091out:
4092 intel_display_power_put(dev_priv, power_domain);
4093
4094 return ret;
4095}
4096
4097/*
4098 * Parse pipe CRC command strings:
4099 * command: wsp* object wsp+ name wsp+ source wsp*
4100 * object: 'pipe'
4101 * name: (A | B | C)
4102 * source: (none | plane1 | plane2 | pf)
4103 * wsp: (#0x20 | #0x9 | #0xA)+
4104 *
4105 * eg.:
4106 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4107 * "pipe A none" -> Stop CRC
4108 */
4109static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4110{
4111 int n_words = 0;
4112
4113 while (*buf) {
4114 char *end;
4115
4116 /* skip leading white space */
4117 buf = skip_spaces(buf);
4118 if (!*buf)
4119 break; /* end of buffer */
4120
4121 /* find end of word */
4122 for (end = buf; *end && !isspace(*end); end++)
4123 ;
4124
4125 if (n_words == max_words) {
4126 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4127 max_words);
4128 return -EINVAL; /* ran out of words[] before bytes */
4129 }
4130
4131 if (*end)
4132 *end++ = '\0';
4133 words[n_words++] = buf;
4134 buf = end;
4135 }
4136
4137 return n_words;
4138}
4139
4140enum intel_pipe_crc_object {
4141 PIPE_CRC_OBJECT_PIPE,
4142};
4143
4144static const char * const pipe_crc_objects[] = {
4145 "pipe",
4146};
4147
4148static int
4149display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4150{
4151 int i;
4152
4153 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4154 if (!strcmp(buf, pipe_crc_objects[i])) {
4155 *o = i;
4156 return 0;
4157 }
4158
4159 return -EINVAL;
4160}
4161
4162static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4163{
4164 const char name = buf[0];
4165
4166 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4167 return -EINVAL;
4168
4169 *pipe = name - 'A';
4170
4171 return 0;
4172}
4173
4174static int
4175display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4176{
4177 int i;
4178
4179 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4180 if (!strcmp(buf, pipe_crc_sources[i])) {
4181 *s = i;
4182 return 0;
4183 }
4184
4185 return -EINVAL;
4186}
4187
4188static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4189 char *buf, size_t len)
4190{
4191#define N_WORDS 3
4192 int n_words;
4193 char *words[N_WORDS];
4194 enum pipe pipe;
4195 enum intel_pipe_crc_object object;
4196 enum intel_pipe_crc_source source;
4197
4198 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4199 if (n_words != N_WORDS) {
4200 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4201 N_WORDS);
4202 return -EINVAL;
4203 }
4204
4205 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4206 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4207 return -EINVAL;
4208 }
4209
4210 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4211 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4212 return -EINVAL;
4213 }
4214
4215 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4216 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4217 return -EINVAL;
4218 }
4219
4220 return pipe_crc_set_source(dev_priv, pipe, source);
4221}
4222
4223static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4224 size_t len, loff_t *offp)
4225{
4226 struct seq_file *m = file->private_data;
4227 struct drm_i915_private *dev_priv = m->private;
4228 char *tmpbuf;
4229 int ret;
4230
4231 if (len == 0)
4232 return 0;
4233
4234 if (len > PAGE_SIZE - 1) {
4235 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4236 PAGE_SIZE);
4237 return -E2BIG;
4238 }
4239
4240 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4241 if (!tmpbuf)
4242 return -ENOMEM;
4243
4244 if (copy_from_user(tmpbuf, ubuf, len)) {
4245 ret = -EFAULT;
4246 goto out;
4247 }
4248 tmpbuf[len] = '\0';
4249
4250 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4251
4252out:
4253 kfree(tmpbuf);
4254 if (ret < 0)
4255 return ret;
4256
4257 *offp += len;
4258 return len;
4259}
4260
4261static const struct file_operations i915_display_crc_ctl_fops = {
4262 .owner = THIS_MODULE,
4263 .open = display_crc_ctl_open,
4264 .read = seq_read,
4265 .llseek = seq_lseek,
4266 .release = single_release,
4267 .write = display_crc_ctl_write
4268};
4269
4270static ssize_t i915_displayport_test_active_write(struct file *file,
4271 const char __user *ubuf,
4272 size_t len, loff_t *offp)
4273{
4274 char *input_buffer;
4275 int status = 0;
4276 struct drm_device *dev;
4277 struct drm_connector *connector;
4278 struct list_head *connector_list;
4279 struct intel_dp *intel_dp;
4280 int val = 0;
4281
4282 dev = ((struct seq_file *)file->private_data)->private;
4283
4284 connector_list = &dev->mode_config.connector_list;
4285
4286 if (len == 0)
4287 return 0;
4288
4289 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4290 if (!input_buffer)
4291 return -ENOMEM;
4292
4293 if (copy_from_user(input_buffer, ubuf, len)) {
4294 status = -EFAULT;
4295 goto out;
4296 }
4297
4298 input_buffer[len] = '\0';
4299 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4300
4301 list_for_each_entry(connector, connector_list, head) {
4302 if (connector->connector_type !=
4303 DRM_MODE_CONNECTOR_DisplayPort)
4304 continue;
4305
4306 if (connector->status == connector_status_connected &&
4307 connector->encoder != NULL) {
4308 intel_dp = enc_to_intel_dp(connector->encoder);
4309 status = kstrtoint(input_buffer, 10, &val);
4310 if (status < 0)
4311 goto out;
4312 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4313 /* To prevent erroneous activation of the compliance
4314 * testing code, only accept an actual value of 1 here
4315 */
4316 if (val == 1)
4317 intel_dp->compliance_test_active = 1;
4318 else
4319 intel_dp->compliance_test_active = 0;
4320 }
4321 }
4322out:
4323 kfree(input_buffer);
4324 if (status < 0)
4325 return status;
4326
4327 *offp += len;
4328 return len;
4329}
4330
4331static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4332{
4333 struct drm_device *dev = m->private;
4334 struct drm_connector *connector;
4335 struct list_head *connector_list = &dev->mode_config.connector_list;
4336 struct intel_dp *intel_dp;
4337
4338 list_for_each_entry(connector, connector_list, head) {
4339 if (connector->connector_type !=
4340 DRM_MODE_CONNECTOR_DisplayPort)
4341 continue;
4342
4343 if (connector->status == connector_status_connected &&
4344 connector->encoder != NULL) {
4345 intel_dp = enc_to_intel_dp(connector->encoder);
4346 if (intel_dp->compliance_test_active)
4347 seq_puts(m, "1");
4348 else
4349 seq_puts(m, "0");
4350 } else
4351 seq_puts(m, "0");
4352 }
4353
4354 return 0;
4355}
4356
4357static int i915_displayport_test_active_open(struct inode *inode,
4358 struct file *file)
4359{
4360 struct drm_i915_private *dev_priv = inode->i_private;
4361
4362 return single_open(file, i915_displayport_test_active_show,
4363 &dev_priv->drm);
4364}
4365
4366static const struct file_operations i915_displayport_test_active_fops = {
4367 .owner = THIS_MODULE,
4368 .open = i915_displayport_test_active_open,
4369 .read = seq_read,
4370 .llseek = seq_lseek,
4371 .release = single_release,
4372 .write = i915_displayport_test_active_write
4373};
4374
4375static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4376{
4377 struct drm_device *dev = m->private;
4378 struct drm_connector *connector;
4379 struct list_head *connector_list = &dev->mode_config.connector_list;
4380 struct intel_dp *intel_dp;
4381
4382 list_for_each_entry(connector, connector_list, head) {
4383 if (connector->connector_type !=
4384 DRM_MODE_CONNECTOR_DisplayPort)
4385 continue;
4386
4387 if (connector->status == connector_status_connected &&
4388 connector->encoder != NULL) {
4389 intel_dp = enc_to_intel_dp(connector->encoder);
4390 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4391 } else
4392 seq_puts(m, "0");
4393 }
4394
4395 return 0;
4396}
4397static int i915_displayport_test_data_open(struct inode *inode,
4398 struct file *file)
4399{
4400 struct drm_i915_private *dev_priv = inode->i_private;
4401
4402 return single_open(file, i915_displayport_test_data_show,
4403 &dev_priv->drm);
4404}
4405
4406static const struct file_operations i915_displayport_test_data_fops = {
4407 .owner = THIS_MODULE,
4408 .open = i915_displayport_test_data_open,
4409 .read = seq_read,
4410 .llseek = seq_lseek,
4411 .release = single_release
4412};
4413
4414static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4415{
4416 struct drm_device *dev = m->private;
4417 struct drm_connector *connector;
4418 struct list_head *connector_list = &dev->mode_config.connector_list;
4419 struct intel_dp *intel_dp;
4420
4421 list_for_each_entry(connector, connector_list, head) {
4422 if (connector->connector_type !=
4423 DRM_MODE_CONNECTOR_DisplayPort)
4424 continue;
4425
4426 if (connector->status == connector_status_connected &&
4427 connector->encoder != NULL) {
4428 intel_dp = enc_to_intel_dp(connector->encoder);
4429 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4430 } else
4431 seq_puts(m, "0");
4432 }
4433
4434 return 0;
4435}
4436
4437static int i915_displayport_test_type_open(struct inode *inode,
4438 struct file *file)
4439{
4440 struct drm_i915_private *dev_priv = inode->i_private;
4441
4442 return single_open(file, i915_displayport_test_type_show,
4443 &dev_priv->drm);
4444}
4445
4446static const struct file_operations i915_displayport_test_type_fops = {
4447 .owner = THIS_MODULE,
4448 .open = i915_displayport_test_type_open,
4449 .read = seq_read,
4450 .llseek = seq_lseek,
4451 .release = single_release
4452};
4453
4454static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4455{
4456 struct drm_i915_private *dev_priv = m->private;
4457 struct drm_device *dev = &dev_priv->drm;
4458 int level;
4459 int num_levels;
4460
4461 if (IS_CHERRYVIEW(dev_priv))
4462 num_levels = 3;
4463 else if (IS_VALLEYVIEW(dev_priv))
4464 num_levels = 1;
4465 else
4466 num_levels = ilk_wm_max_level(dev) + 1;
4467
4468 drm_modeset_lock_all(dev);
4469
4470 for (level = 0; level < num_levels; level++) {
4471 unsigned int latency = wm[level];
4472
4473 /*
4474 * - WM1+ latency values in 0.5us units
4475 * - latencies are in us on gen9/vlv/chv
4476 */
4477 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4478 IS_CHERRYVIEW(dev_priv))
4479 latency *= 10;
4480 else if (level > 0)
4481 latency *= 5;
4482
4483 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4484 level, wm[level], latency / 10, latency % 10);
4485 }
4486
4487 drm_modeset_unlock_all(dev);
4488}
4489
4490static int pri_wm_latency_show(struct seq_file *m, void *data)
4491{
4492 struct drm_i915_private *dev_priv = m->private;
4493 const uint16_t *latencies;
4494
4495 if (INTEL_GEN(dev_priv) >= 9)
4496 latencies = dev_priv->wm.skl_latency;
4497 else
4498 latencies = dev_priv->wm.pri_latency;
4499
4500 wm_latency_show(m, latencies);
4501
4502 return 0;
4503}
4504
4505static int spr_wm_latency_show(struct seq_file *m, void *data)
4506{
4507 struct drm_i915_private *dev_priv = m->private;
4508 const uint16_t *latencies;
4509
4510 if (INTEL_GEN(dev_priv) >= 9)
4511 latencies = dev_priv->wm.skl_latency;
4512 else
4513 latencies = dev_priv->wm.spr_latency;
4514
4515 wm_latency_show(m, latencies);
4516
4517 return 0;
4518}
4519
4520static int cur_wm_latency_show(struct seq_file *m, void *data)
4521{
4522 struct drm_i915_private *dev_priv = m->private;
4523 const uint16_t *latencies;
4524
4525 if (INTEL_GEN(dev_priv) >= 9)
4526 latencies = dev_priv->wm.skl_latency;
4527 else
4528 latencies = dev_priv->wm.cur_latency;
4529
4530 wm_latency_show(m, latencies);
4531
4532 return 0;
4533}
4534
4535static int pri_wm_latency_open(struct inode *inode, struct file *file)
4536{
4537 struct drm_i915_private *dev_priv = inode->i_private;
4538
4539 if (INTEL_GEN(dev_priv) < 5)
4540 return -ENODEV;
4541
4542 return single_open(file, pri_wm_latency_show, dev_priv);
4543}
4544
4545static int spr_wm_latency_open(struct inode *inode, struct file *file)
4546{
4547 struct drm_i915_private *dev_priv = inode->i_private;
4548
4549 if (HAS_GMCH_DISPLAY(dev_priv))
4550 return -ENODEV;
4551
4552 return single_open(file, spr_wm_latency_show, dev_priv);
4553}
4554
4555static int cur_wm_latency_open(struct inode *inode, struct file *file)
4556{
4557 struct drm_i915_private *dev_priv = inode->i_private;
4558
4559 if (HAS_GMCH_DISPLAY(dev_priv))
4560 return -ENODEV;
4561
4562 return single_open(file, cur_wm_latency_show, dev_priv);
4563}
4564
4565static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4566 size_t len, loff_t *offp, uint16_t wm[8])
4567{
4568 struct seq_file *m = file->private_data;
4569 struct drm_i915_private *dev_priv = m->private;
4570 struct drm_device *dev = &dev_priv->drm;
4571 uint16_t new[8] = { 0 };
4572 int num_levels;
4573 int level;
4574 int ret;
4575 char tmp[32];
4576
4577 if (IS_CHERRYVIEW(dev_priv))
4578 num_levels = 3;
4579 else if (IS_VALLEYVIEW(dev_priv))
4580 num_levels = 1;
4581 else
4582 num_levels = ilk_wm_max_level(dev) + 1;
4583
4584 if (len >= sizeof(tmp))
4585 return -EINVAL;
4586
4587 if (copy_from_user(tmp, ubuf, len))
4588 return -EFAULT;
4589
4590 tmp[len] = '\0';
4591
4592 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4593 &new[0], &new[1], &new[2], &new[3],
4594 &new[4], &new[5], &new[6], &new[7]);
4595 if (ret != num_levels)
4596 return -EINVAL;
4597
4598 drm_modeset_lock_all(dev);
4599
4600 for (level = 0; level < num_levels; level++)
4601 wm[level] = new[level];
4602
4603 drm_modeset_unlock_all(dev);
4604
4605 return len;
4606}
4607
4608
4609static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4610 size_t len, loff_t *offp)
4611{
4612 struct seq_file *m = file->private_data;
4613 struct drm_i915_private *dev_priv = m->private;
4614 uint16_t *latencies;
4615
4616 if (INTEL_GEN(dev_priv) >= 9)
4617 latencies = dev_priv->wm.skl_latency;
4618 else
4619 latencies = dev_priv->wm.pri_latency;
4620
4621 return wm_latency_write(file, ubuf, len, offp, latencies);
4622}
4623
4624static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4625 size_t len, loff_t *offp)
4626{
4627 struct seq_file *m = file->private_data;
4628 struct drm_i915_private *dev_priv = m->private;
4629 uint16_t *latencies;
4630
4631 if (INTEL_GEN(dev_priv) >= 9)
4632 latencies = dev_priv->wm.skl_latency;
4633 else
4634 latencies = dev_priv->wm.spr_latency;
4635
4636 return wm_latency_write(file, ubuf, len, offp, latencies);
4637}
4638
4639static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4640 size_t len, loff_t *offp)
4641{
4642 struct seq_file *m = file->private_data;
4643 struct drm_i915_private *dev_priv = m->private;
4644 uint16_t *latencies;
4645
4646 if (INTEL_GEN(dev_priv) >= 9)
4647 latencies = dev_priv->wm.skl_latency;
4648 else
4649 latencies = dev_priv->wm.cur_latency;
4650
4651 return wm_latency_write(file, ubuf, len, offp, latencies);
4652}
4653
4654static const struct file_operations i915_pri_wm_latency_fops = {
4655 .owner = THIS_MODULE,
4656 .open = pri_wm_latency_open,
4657 .read = seq_read,
4658 .llseek = seq_lseek,
4659 .release = single_release,
4660 .write = pri_wm_latency_write
4661};
4662
4663static const struct file_operations i915_spr_wm_latency_fops = {
4664 .owner = THIS_MODULE,
4665 .open = spr_wm_latency_open,
4666 .read = seq_read,
4667 .llseek = seq_lseek,
4668 .release = single_release,
4669 .write = spr_wm_latency_write
4670};
4671
4672static const struct file_operations i915_cur_wm_latency_fops = {
4673 .owner = THIS_MODULE,
4674 .open = cur_wm_latency_open,
4675 .read = seq_read,
4676 .llseek = seq_lseek,
4677 .release = single_release,
4678 .write = cur_wm_latency_write
4679};
4680
4681static int
4682i915_wedged_get(void *data, u64 *val)
4683{
4684 struct drm_i915_private *dev_priv = data;
4685
4686 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4687
4688 return 0;
4689}
4690
4691static int
4692i915_wedged_set(void *data, u64 val)
4693{
4694 struct drm_i915_private *dev_priv = data;
4695
4696 /*
4697 * There is no safeguard against this debugfs entry colliding
4698 * with the hangcheck calling same i915_handle_error() in
4699 * parallel, causing an explosion. For now we assume that the
4700 * test harness is responsible enough not to inject gpu hangs
4701 * while it is writing to 'i915_wedged'
4702 */
4703
4704 if (i915_reset_in_progress(&dev_priv->gpu_error))
4705 return -EAGAIN;
4706
4707 intel_runtime_pm_get(dev_priv);
4708
4709 i915_handle_error(dev_priv, val,
4710 "Manually setting wedged to %llu", val);
4711
4712 intel_runtime_pm_put(dev_priv);
4713
4714 return 0;
4715}
4716
4717DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4718 i915_wedged_get, i915_wedged_set,
4719 "%llu\n");
4720
4721static int
4722i915_ring_missed_irq_get(void *data, u64 *val)
4723{
4724 struct drm_i915_private *dev_priv = data;
4725
4726 *val = dev_priv->gpu_error.missed_irq_rings;
4727 return 0;
4728}
4729
4730static int
4731i915_ring_missed_irq_set(void *data, u64 val)
4732{
4733 struct drm_i915_private *dev_priv = data;
4734 struct drm_device *dev = &dev_priv->drm;
4735 int ret;
4736
4737 /* Lock against concurrent debugfs callers */
4738 ret = mutex_lock_interruptible(&dev->struct_mutex);
4739 if (ret)
4740 return ret;
4741 dev_priv->gpu_error.missed_irq_rings = val;
4742 mutex_unlock(&dev->struct_mutex);
4743
4744 return 0;
4745}
4746
4747DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4748 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4749 "0x%08llx\n");
4750
4751static int
4752i915_ring_test_irq_get(void *data, u64 *val)
4753{
4754 struct drm_i915_private *dev_priv = data;
4755
4756 *val = dev_priv->gpu_error.test_irq_rings;
4757
4758 return 0;
4759}
4760
4761static int
4762i915_ring_test_irq_set(void *data, u64 val)
4763{
4764 struct drm_i915_private *dev_priv = data;
4765
4766 val &= INTEL_INFO(dev_priv)->ring_mask;
4767 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4768 dev_priv->gpu_error.test_irq_rings = val;
4769
4770 return 0;
4771}
4772
4773DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4774 i915_ring_test_irq_get, i915_ring_test_irq_set,
4775 "0x%08llx\n");
4776
4777#define DROP_UNBOUND 0x1
4778#define DROP_BOUND 0x2
4779#define DROP_RETIRE 0x4
4780#define DROP_ACTIVE 0x8
4781#define DROP_ALL (DROP_UNBOUND | \
4782 DROP_BOUND | \
4783 DROP_RETIRE | \
4784 DROP_ACTIVE)
4785static int
4786i915_drop_caches_get(void *data, u64 *val)
4787{
4788 *val = DROP_ALL;
4789
4790 return 0;
4791}
4792
4793static int
4794i915_drop_caches_set(void *data, u64 val)
4795{
4796 struct drm_i915_private *dev_priv = data;
4797 struct drm_device *dev = &dev_priv->drm;
4798 int ret;
4799
4800 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4801
4802 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4803 * on ioctls on -EAGAIN. */
4804 ret = mutex_lock_interruptible(&dev->struct_mutex);
4805 if (ret)
4806 return ret;
4807
4808 if (val & DROP_ACTIVE) {
4809 ret = i915_gem_wait_for_idle(dev_priv, true);
4810 if (ret)
4811 goto unlock;
4812 }
4813
4814 if (val & (DROP_RETIRE | DROP_ACTIVE))
4815 i915_gem_retire_requests(dev_priv);
4816
4817 if (val & DROP_BOUND)
4818 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4819
4820 if (val & DROP_UNBOUND)
4821 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4822
4823unlock:
4824 mutex_unlock(&dev->struct_mutex);
4825
4826 return ret;
4827}
4828
4829DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4830 i915_drop_caches_get, i915_drop_caches_set,
4831 "0x%08llx\n");
4832
4833static int
4834i915_max_freq_get(void *data, u64 *val)
4835{
4836 struct drm_i915_private *dev_priv = data;
4837
4838 if (INTEL_GEN(dev_priv) < 6)
4839 return -ENODEV;
4840
4841 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4842 return 0;
4843}
4844
4845static int
4846i915_max_freq_set(void *data, u64 val)
4847{
4848 struct drm_i915_private *dev_priv = data;
4849 u32 hw_max, hw_min;
4850 int ret;
4851
4852 if (INTEL_GEN(dev_priv) < 6)
4853 return -ENODEV;
4854
4855 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4856
4857 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4858 if (ret)
4859 return ret;
4860
4861 /*
4862 * Turbo will still be enabled, but won't go above the set value.
4863 */
4864 val = intel_freq_opcode(dev_priv, val);
4865
4866 hw_max = dev_priv->rps.max_freq;
4867 hw_min = dev_priv->rps.min_freq;
4868
4869 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4870 mutex_unlock(&dev_priv->rps.hw_lock);
4871 return -EINVAL;
4872 }
4873
4874 dev_priv->rps.max_freq_softlimit = val;
4875
4876 intel_set_rps(dev_priv, val);
4877
4878 mutex_unlock(&dev_priv->rps.hw_lock);
4879
4880 return 0;
4881}
4882
4883DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4884 i915_max_freq_get, i915_max_freq_set,
4885 "%llu\n");
4886
4887static int
4888i915_min_freq_get(void *data, u64 *val)
4889{
4890 struct drm_i915_private *dev_priv = data;
4891
4892 if (INTEL_GEN(dev_priv) < 6)
4893 return -ENODEV;
4894
4895 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4896 return 0;
4897}
4898
4899static int
4900i915_min_freq_set(void *data, u64 val)
4901{
4902 struct drm_i915_private *dev_priv = data;
4903 u32 hw_max, hw_min;
4904 int ret;
4905
4906 if (INTEL_GEN(dev_priv) < 6)
4907 return -ENODEV;
4908
4909 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4910
4911 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4912 if (ret)
4913 return ret;
4914
4915 /*
4916 * Turbo will still be enabled, but won't go below the set value.
4917 */
4918 val = intel_freq_opcode(dev_priv, val);
4919
4920 hw_max = dev_priv->rps.max_freq;
4921 hw_min = dev_priv->rps.min_freq;
4922
4923 if (val < hw_min ||
4924 val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4925 mutex_unlock(&dev_priv->rps.hw_lock);
4926 return -EINVAL;
4927 }
4928
4929 dev_priv->rps.min_freq_softlimit = val;
4930
4931 intel_set_rps(dev_priv, val);
4932
4933 mutex_unlock(&dev_priv->rps.hw_lock);
4934
4935 return 0;
4936}
4937
4938DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4939 i915_min_freq_get, i915_min_freq_set,
4940 "%llu\n");
4941
4942static int
4943i915_cache_sharing_get(void *data, u64 *val)
4944{
4945 struct drm_i915_private *dev_priv = data;
4946 struct drm_device *dev = &dev_priv->drm;
4947 u32 snpcr;
4948 int ret;
4949
4950 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4951 return -ENODEV;
4952
4953 ret = mutex_lock_interruptible(&dev->struct_mutex);
4954 if (ret)
4955 return ret;
4956 intel_runtime_pm_get(dev_priv);
4957
4958 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4959
4960 intel_runtime_pm_put(dev_priv);
4961 mutex_unlock(&dev->struct_mutex);
4962
4963 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4964
4965 return 0;
4966}
4967
4968static int
4969i915_cache_sharing_set(void *data, u64 val)
4970{
4971 struct drm_i915_private *dev_priv = data;
4972 u32 snpcr;
4973
4974 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4975 return -ENODEV;
4976
4977 if (val > 3)
4978 return -EINVAL;
4979
4980 intel_runtime_pm_get(dev_priv);
4981 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4982
4983 /* Update the cache sharing policy here as well */
4984 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4985 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4986 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4987 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4988
4989 intel_runtime_pm_put(dev_priv);
4990 return 0;
4991}
4992
4993DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4994 i915_cache_sharing_get, i915_cache_sharing_set,
4995 "%llu\n");
4996
4997struct sseu_dev_status {
4998 unsigned int slice_total;
4999 unsigned int subslice_total;
5000 unsigned int subslice_per_slice;
5001 unsigned int eu_total;
5002 unsigned int eu_per_subslice;
5003};
5004
5005static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5006 struct sseu_dev_status *stat)
5007{
5008 int ss_max = 2;
5009 int ss;
5010 u32 sig1[ss_max], sig2[ss_max];
5011
5012 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5013 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5014 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5015 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5016
5017 for (ss = 0; ss < ss_max; ss++) {
5018 unsigned int eu_cnt;
5019
5020 if (sig1[ss] & CHV_SS_PG_ENABLE)
5021 /* skip disabled subslice */
5022 continue;
5023
5024 stat->slice_total = 1;
5025 stat->subslice_per_slice++;
5026 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5027 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5028 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5029 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5030 stat->eu_total += eu_cnt;
5031 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5032 }
5033 stat->subslice_total = stat->subslice_per_slice;
5034}
5035
5036static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5037 struct sseu_dev_status *stat)
5038{
5039 int s_max = 3, ss_max = 4;
5040 int s, ss;
5041 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5042
5043 /* BXT has a single slice and at most 3 subslices. */
5044 if (IS_BROXTON(dev_priv)) {
5045 s_max = 1;
5046 ss_max = 3;
5047 }
5048
5049 for (s = 0; s < s_max; s++) {
5050 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5051 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5052 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5053 }
5054
5055 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5056 GEN9_PGCTL_SSA_EU19_ACK |
5057 GEN9_PGCTL_SSA_EU210_ACK |
5058 GEN9_PGCTL_SSA_EU311_ACK;
5059 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5060 GEN9_PGCTL_SSB_EU19_ACK |
5061 GEN9_PGCTL_SSB_EU210_ACK |
5062 GEN9_PGCTL_SSB_EU311_ACK;
5063
5064 for (s = 0; s < s_max; s++) {
5065 unsigned int ss_cnt = 0;
5066
5067 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5068 /* skip disabled slice */
5069 continue;
5070
5071 stat->slice_total++;
5072
5073 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5074 ss_cnt = INTEL_INFO(dev_priv)->subslice_per_slice;
5075
5076 for (ss = 0; ss < ss_max; ss++) {
5077 unsigned int eu_cnt;
5078
5079 if (IS_BROXTON(dev_priv) &&
5080 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5081 /* skip disabled subslice */
5082 continue;
5083
5084 if (IS_BROXTON(dev_priv))
5085 ss_cnt++;
5086
5087 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5088 eu_mask[ss%2]);
5089 stat->eu_total += eu_cnt;
5090 stat->eu_per_subslice = max(stat->eu_per_subslice,
5091 eu_cnt);
5092 }
5093
5094 stat->subslice_total += ss_cnt;
5095 stat->subslice_per_slice = max(stat->subslice_per_slice,
5096 ss_cnt);
5097 }
5098}
5099
5100static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5101 struct sseu_dev_status *stat)
5102{
5103 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5104 int s;
5105
5106 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5107
5108 if (stat->slice_total) {
5109 stat->subslice_per_slice = INTEL_INFO(dev_priv)->subslice_per_slice;
5110 stat->subslice_total = stat->slice_total *
5111 stat->subslice_per_slice;
5112 stat->eu_per_subslice = INTEL_INFO(dev_priv)->eu_per_subslice;
5113 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5114
5115 /* subtract fused off EU(s) from enabled slice(s) */
5116 for (s = 0; s < stat->slice_total; s++) {
5117 u8 subslice_7eu = INTEL_INFO(dev_priv)->subslice_7eu[s];
5118
5119 stat->eu_total -= hweight8(subslice_7eu);
5120 }
5121 }
5122}
5123
5124static int i915_sseu_status(struct seq_file *m, void *unused)
5125{
5126 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5127 struct sseu_dev_status stat;
5128
5129 if (INTEL_GEN(dev_priv) < 8)
5130 return -ENODEV;
5131
5132 seq_puts(m, "SSEU Device Info\n");
5133 seq_printf(m, " Available Slice Total: %u\n",
5134 INTEL_INFO(dev_priv)->slice_total);
5135 seq_printf(m, " Available Subslice Total: %u\n",
5136 INTEL_INFO(dev_priv)->subslice_total);
5137 seq_printf(m, " Available Subslice Per Slice: %u\n",
5138 INTEL_INFO(dev_priv)->subslice_per_slice);
5139 seq_printf(m, " Available EU Total: %u\n",
5140 INTEL_INFO(dev_priv)->eu_total);
5141 seq_printf(m, " Available EU Per Subslice: %u\n",
5142 INTEL_INFO(dev_priv)->eu_per_subslice);
5143 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5144 if (HAS_POOLED_EU(dev_priv))
5145 seq_printf(m, " Min EU in pool: %u\n",
5146 INTEL_INFO(dev_priv)->min_eu_in_pool);
5147 seq_printf(m, " Has Slice Power Gating: %s\n",
5148 yesno(INTEL_INFO(dev_priv)->has_slice_pg));
5149 seq_printf(m, " Has Subslice Power Gating: %s\n",
5150 yesno(INTEL_INFO(dev_priv)->has_subslice_pg));
5151 seq_printf(m, " Has EU Power Gating: %s\n",
5152 yesno(INTEL_INFO(dev_priv)->has_eu_pg));
5153
5154 seq_puts(m, "SSEU Device Status\n");
5155 memset(&stat, 0, sizeof(stat));
5156
5157 intel_runtime_pm_get(dev_priv);
5158
5159 if (IS_CHERRYVIEW(dev_priv)) {
5160 cherryview_sseu_device_status(dev_priv, &stat);
5161 } else if (IS_BROADWELL(dev_priv)) {
5162 broadwell_sseu_device_status(dev_priv, &stat);
5163 } else if (INTEL_GEN(dev_priv) >= 9) {
5164 gen9_sseu_device_status(dev_priv, &stat);
5165 }
5166
5167 intel_runtime_pm_put(dev_priv);
5168
5169 seq_printf(m, " Enabled Slice Total: %u\n",
5170 stat.slice_total);
5171 seq_printf(m, " Enabled Subslice Total: %u\n",
5172 stat.subslice_total);
5173 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5174 stat.subslice_per_slice);
5175 seq_printf(m, " Enabled EU Total: %u\n",
5176 stat.eu_total);
5177 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5178 stat.eu_per_subslice);
5179
5180 return 0;
5181}
5182
5183static int i915_forcewake_open(struct inode *inode, struct file *file)
5184{
5185 struct drm_i915_private *dev_priv = inode->i_private;
5186
5187 if (INTEL_GEN(dev_priv) < 6)
5188 return 0;
5189
5190 intel_runtime_pm_get(dev_priv);
5191 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5192
5193 return 0;
5194}
5195
5196static int i915_forcewake_release(struct inode *inode, struct file *file)
5197{
5198 struct drm_i915_private *dev_priv = inode->i_private;
5199
5200 if (INTEL_GEN(dev_priv) < 6)
5201 return 0;
5202
5203 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5204 intel_runtime_pm_put(dev_priv);
5205
5206 return 0;
5207}
5208
5209static const struct file_operations i915_forcewake_fops = {
5210 .owner = THIS_MODULE,
5211 .open = i915_forcewake_open,
5212 .release = i915_forcewake_release,
5213};
5214
5215static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5216{
5217 struct dentry *ent;
5218
5219 ent = debugfs_create_file("i915_forcewake_user",
5220 S_IRUSR,
5221 root, to_i915(minor->dev),
5222 &i915_forcewake_fops);
5223 if (!ent)
5224 return -ENOMEM;
5225
5226 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5227}
5228
5229static int i915_debugfs_create(struct dentry *root,
5230 struct drm_minor *minor,
5231 const char *name,
5232 const struct file_operations *fops)
5233{
5234 struct dentry *ent;
5235
5236 ent = debugfs_create_file(name,
5237 S_IRUGO | S_IWUSR,
5238 root, to_i915(minor->dev),
5239 fops);
5240 if (!ent)
5241 return -ENOMEM;
5242
5243 return drm_add_fake_info_node(minor, ent, fops);
5244}
5245
5246static const struct drm_info_list i915_debugfs_list[] = {
5247 {"i915_capabilities", i915_capabilities, 0},
5248 {"i915_gem_objects", i915_gem_object_info, 0},
5249 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5250 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5251 {"i915_gem_stolen", i915_gem_stolen_list_info },
5252 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5253 {"i915_gem_request", i915_gem_request_info, 0},
5254 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5255 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5256 {"i915_gem_interrupt", i915_interrupt_info, 0},
5257 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5258 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5259 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5260 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5261 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5262 {"i915_guc_info", i915_guc_info, 0},
5263 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5264 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5265 {"i915_frequency_info", i915_frequency_info, 0},
5266 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5267 {"i915_drpc_info", i915_drpc_info, 0},
5268 {"i915_emon_status", i915_emon_status, 0},
5269 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5270 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5271 {"i915_fbc_status", i915_fbc_status, 0},
5272 {"i915_ips_status", i915_ips_status, 0},
5273 {"i915_sr_status", i915_sr_status, 0},
5274 {"i915_opregion", i915_opregion, 0},
5275 {"i915_vbt", i915_vbt, 0},
5276 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5277 {"i915_context_status", i915_context_status, 0},
5278 {"i915_dump_lrc", i915_dump_lrc, 0},
5279 {"i915_execlists", i915_execlists, 0},
5280 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5281 {"i915_swizzle_info", i915_swizzle_info, 0},
5282 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5283 {"i915_llc", i915_llc, 0},
5284 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5285 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5286 {"i915_energy_uJ", i915_energy_uJ, 0},
5287 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5288 {"i915_power_domain_info", i915_power_domain_info, 0},
5289 {"i915_dmc_info", i915_dmc_info, 0},
5290 {"i915_display_info", i915_display_info, 0},
5291 {"i915_semaphore_status", i915_semaphore_status, 0},
5292 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5293 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5294 {"i915_wa_registers", i915_wa_registers, 0},
5295 {"i915_ddb_info", i915_ddb_info, 0},
5296 {"i915_sseu_status", i915_sseu_status, 0},
5297 {"i915_drrs_status", i915_drrs_status, 0},
5298 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5299};
5300#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5301
5302static const struct i915_debugfs_files {
5303 const char *name;
5304 const struct file_operations *fops;
5305} i915_debugfs_files[] = {
5306 {"i915_wedged", &i915_wedged_fops},
5307 {"i915_max_freq", &i915_max_freq_fops},
5308 {"i915_min_freq", &i915_min_freq_fops},
5309 {"i915_cache_sharing", &i915_cache_sharing_fops},
5310 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5311 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5312 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5313 {"i915_error_state", &i915_error_state_fops},
5314 {"i915_next_seqno", &i915_next_seqno_fops},
5315 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5316 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5317 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5318 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5319 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5320 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5321 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5322 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5323};
5324
5325void intel_display_crc_init(struct drm_i915_private *dev_priv)
5326{
5327 enum pipe pipe;
5328
5329 for_each_pipe(dev_priv, pipe) {
5330 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5331
5332 pipe_crc->opened = false;
5333 spin_lock_init(&pipe_crc->lock);
5334 init_waitqueue_head(&pipe_crc->wq);
5335 }
5336}
5337
5338int i915_debugfs_register(struct drm_i915_private *dev_priv)
5339{
5340 struct drm_minor *minor = dev_priv->drm.primary;
5341 int ret, i;
5342
5343 ret = i915_forcewake_create(minor->debugfs_root, minor);
5344 if (ret)
5345 return ret;
5346
5347 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5348 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5349 if (ret)
5350 return ret;
5351 }
5352
5353 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5354 ret = i915_debugfs_create(minor->debugfs_root, minor,
5355 i915_debugfs_files[i].name,
5356 i915_debugfs_files[i].fops);
5357 if (ret)
5358 return ret;
5359 }
5360
5361 return drm_debugfs_create_files(i915_debugfs_list,
5362 I915_DEBUGFS_ENTRIES,
5363 minor->debugfs_root, minor);
5364}
5365
5366void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5367{
5368 struct drm_minor *minor = dev_priv->drm.primary;
5369 int i;
5370
5371 drm_debugfs_remove_files(i915_debugfs_list,
5372 I915_DEBUGFS_ENTRIES, minor);
5373
5374 drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5375 1, minor);
5376
5377 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5378 struct drm_info_list *info_list =
5379 (struct drm_info_list *)&i915_pipe_crc_data[i];
5380
5381 drm_debugfs_remove_files(info_list, 1, minor);
5382 }
5383
5384 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5385 struct drm_info_list *info_list =
5386 (struct drm_info_list *)i915_debugfs_files[i].fops;
5387
5388 drm_debugfs_remove_files(info_list, 1, minor);
5389 }
5390}
5391
5392struct dpcd_block {
5393 /* DPCD dump start address. */
5394 unsigned int offset;
5395 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5396 unsigned int end;
5397 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5398 size_t size;
5399 /* Only valid for eDP. */
5400 bool edp;
5401};
5402
5403static const struct dpcd_block i915_dpcd_debug[] = {
5404 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5405 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5406 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5407 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5408 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5409 { .offset = DP_SET_POWER },
5410 { .offset = DP_EDP_DPCD_REV },
5411 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5412 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5413 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5414};
5415
5416static int i915_dpcd_show(struct seq_file *m, void *data)
5417{
5418 struct drm_connector *connector = m->private;
5419 struct intel_dp *intel_dp =
5420 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5421 uint8_t buf[16];
5422 ssize_t err;
5423 int i;
5424
5425 if (connector->status != connector_status_connected)
5426 return -ENODEV;
5427
5428 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5429 const struct dpcd_block *b = &i915_dpcd_debug[i];
5430 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5431
5432 if (b->edp &&
5433 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5434 continue;
5435
5436 /* low tech for now */
5437 if (WARN_ON(size > sizeof(buf)))
5438 continue;
5439
5440 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5441 if (err <= 0) {
5442 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5443 size, b->offset, err);
5444 continue;
5445 }
5446
5447 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5448 }
5449
5450 return 0;
5451}
5452
5453static int i915_dpcd_open(struct inode *inode, struct file *file)
5454{
5455 return single_open(file, i915_dpcd_show, inode->i_private);
5456}
5457
5458static const struct file_operations i915_dpcd_fops = {
5459 .owner = THIS_MODULE,
5460 .open = i915_dpcd_open,
5461 .read = seq_read,
5462 .llseek = seq_lseek,
5463 .release = single_release,
5464};
5465
5466/**
5467 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5468 * @connector: pointer to a registered drm_connector
5469 *
5470 * Cleanup will be done by drm_connector_unregister() through a call to
5471 * drm_debugfs_connector_remove().
5472 *
5473 * Returns 0 on success, negative error codes on error.
5474 */
5475int i915_debugfs_connector_add(struct drm_connector *connector)
5476{
5477 struct dentry *root = connector->debugfs_entry;
5478
5479 /* The connector must have been registered beforehands. */
5480 if (!root)
5481 return -ENODEV;
5482
5483 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5484 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5485 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5486 &i915_dpcd_fops);
5487
5488 return 0;
5489}
Linux kernel - Deliverables
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