projects / deliverable / linux.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
drm/i915: Include active flag when describing objects in debugfs
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
... / ...
CommitLineData
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/circ_buf.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/slab.h>
34#include <linux/export.h>
35#include <linux/list_sort.h>
36#include <asm/msr-index.h>
37#include <drm/drmP.h>
38#include "intel_drv.h"
39#include "intel_ringbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47};
48
49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
93
94 return 0;
95}
96
97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98{
99 if (i915_gem_obj_is_pinned(obj))
100 return "p";
101 else
102 return " ";
103}
104
105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
106{
107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
113}
114
115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
118}
119
120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
123 struct i915_vma *vma;
124 int pin_count = 0;
125
126 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
127 &obj->base,
128 obj->active ? "*" : " ",
129 get_pin_flag(obj),
130 get_tiling_flag(obj),
131 get_global_flag(obj),
132 obj->base.size / 1024,
133 obj->base.read_domains,
134 obj->base.write_domain,
135 i915_gem_request_get_seqno(obj->last_read_req),
136 i915_gem_request_get_seqno(obj->last_write_req),
137 i915_gem_request_get_seqno(obj->last_fenced_req),
138 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
139 obj->dirty ? " dirty" : "",
140 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
141 if (obj->base.name)
142 seq_printf(m, " (name: %d)", obj->base.name);
143 list_for_each_entry(vma, &obj->vma_list, vma_link) {
144 if (vma->pin_count > 0)
145 pin_count++;
146 }
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
158 vma->node.start, vma->node.size,
159 vma->ggtt_view.type);
160 }
161 if (obj->stolen)
162 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
163 if (obj->pin_mappable || obj->fault_mappable) {
164 char s[3], *t = s;
165 if (obj->pin_mappable)
166 *t++ = 'p';
167 if (obj->fault_mappable)
168 *t++ = 'f';
169 *t = '\0';
170 seq_printf(m, " (%s mappable)", s);
171 }
172 if (obj->last_read_req != NULL)
173 seq_printf(m, " (%s)",
174 i915_gem_request_get_ring(obj->last_read_req)->name);
175 if (obj->frontbuffer_bits)
176 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
177}
178
179static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
180{
181 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
182 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
183 seq_putc(m, ' ');
184}
185
186static int i915_gem_object_list_info(struct seq_file *m, void *data)
187{
188 struct drm_info_node *node = m->private;
189 uintptr_t list = (uintptr_t) node->info_ent->data;
190 struct list_head *head;
191 struct drm_device *dev = node->minor->dev;
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct i915_address_space *vm = &dev_priv->gtt.base;
194 struct i915_vma *vma;
195 size_t total_obj_size, total_gtt_size;
196 int count, ret;
197
198 ret = mutex_lock_interruptible(&dev->struct_mutex);
199 if (ret)
200 return ret;
201
202 /* FIXME: the user of this interface might want more than just GGTT */
203 switch (list) {
204 case ACTIVE_LIST:
205 seq_puts(m, "Active:\n");
206 head = &vm->active_list;
207 break;
208 case INACTIVE_LIST:
209 seq_puts(m, "Inactive:\n");
210 head = &vm->inactive_list;
211 break;
212 default:
213 mutex_unlock(&dev->struct_mutex);
214 return -EINVAL;
215 }
216
217 total_obj_size = total_gtt_size = count = 0;
218 list_for_each_entry(vma, head, mm_list) {
219 seq_printf(m, " ");
220 describe_obj(m, vma->obj);
221 seq_printf(m, "\n");
222 total_obj_size += vma->obj->base.size;
223 total_gtt_size += vma->node.size;
224 count++;
225 }
226 mutex_unlock(&dev->struct_mutex);
227
228 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
229 count, total_obj_size, total_gtt_size);
230 return 0;
231}
232
233static int obj_rank_by_stolen(void *priv,
234 struct list_head *A, struct list_head *B)
235{
236 struct drm_i915_gem_object *a =
237 container_of(A, struct drm_i915_gem_object, obj_exec_link);
238 struct drm_i915_gem_object *b =
239 container_of(B, struct drm_i915_gem_object, obj_exec_link);
240
241 return a->stolen->start - b->stolen->start;
242}
243
244static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
245{
246 struct drm_info_node *node = m->private;
247 struct drm_device *dev = node->minor->dev;
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 struct drm_i915_gem_object *obj;
250 size_t total_obj_size, total_gtt_size;
251 LIST_HEAD(stolen);
252 int count, ret;
253
254 ret = mutex_lock_interruptible(&dev->struct_mutex);
255 if (ret)
256 return ret;
257
258 total_obj_size = total_gtt_size = count = 0;
259 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
260 if (obj->stolen == NULL)
261 continue;
262
263 list_add(&obj->obj_exec_link, &stolen);
264
265 total_obj_size += obj->base.size;
266 total_gtt_size += i915_gem_obj_ggtt_size(obj);
267 count++;
268 }
269 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
270 if (obj->stolen == NULL)
271 continue;
272
273 list_add(&obj->obj_exec_link, &stolen);
274
275 total_obj_size += obj->base.size;
276 count++;
277 }
278 list_sort(NULL, &stolen, obj_rank_by_stolen);
279 seq_puts(m, "Stolen:\n");
280 while (!list_empty(&stolen)) {
281 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
282 seq_puts(m, " ");
283 describe_obj(m, obj);
284 seq_putc(m, '\n');
285 list_del_init(&obj->obj_exec_link);
286 }
287 mutex_unlock(&dev->struct_mutex);
288
289 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
290 count, total_obj_size, total_gtt_size);
291 return 0;
292}
293
294#define count_objects(list, member) do { \
295 list_for_each_entry(obj, list, member) { \
296 size += i915_gem_obj_ggtt_size(obj); \
297 ++count; \
298 if (obj->map_and_fenceable) { \
299 mappable_size += i915_gem_obj_ggtt_size(obj); \
300 ++mappable_count; \
301 } \
302 } \
303} while (0)
304
305struct file_stats {
306 struct drm_i915_file_private *file_priv;
307 int count;
308 size_t total, unbound;
309 size_t global, shared;
310 size_t active, inactive;
311};
312
313static int per_file_stats(int id, void *ptr, void *data)
314{
315 struct drm_i915_gem_object *obj = ptr;
316 struct file_stats *stats = data;
317 struct i915_vma *vma;
318
319 stats->count++;
320 stats->total += obj->base.size;
321
322 if (obj->base.name || obj->base.dma_buf)
323 stats->shared += obj->base.size;
324
325 if (USES_FULL_PPGTT(obj->base.dev)) {
326 list_for_each_entry(vma, &obj->vma_list, vma_link) {
327 struct i915_hw_ppgtt *ppgtt;
328
329 if (!drm_mm_node_allocated(&vma->node))
330 continue;
331
332 if (i915_is_ggtt(vma->vm)) {
333 stats->global += obj->base.size;
334 continue;
335 }
336
337 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
338 if (ppgtt->file_priv != stats->file_priv)
339 continue;
340
341 if (obj->active) /* XXX per-vma statistic */
342 stats->active += obj->base.size;
343 else
344 stats->inactive += obj->base.size;
345
346 return 0;
347 }
348 } else {
349 if (i915_gem_obj_ggtt_bound(obj)) {
350 stats->global += obj->base.size;
351 if (obj->active)
352 stats->active += obj->base.size;
353 else
354 stats->inactive += obj->base.size;
355 return 0;
356 }
357 }
358
359 if (!list_empty(&obj->global_list))
360 stats->unbound += obj->base.size;
361
362 return 0;
363}
364
365#define print_file_stats(m, name, stats) \
366 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
367 name, \
368 stats.count, \
369 stats.total, \
370 stats.active, \
371 stats.inactive, \
372 stats.global, \
373 stats.shared, \
374 stats.unbound)
375
376static void print_batch_pool_stats(struct seq_file *m,
377 struct drm_i915_private *dev_priv)
378{
379 struct drm_i915_gem_object *obj;
380 struct file_stats stats;
381 struct intel_engine_cs *ring;
382 int i, j;
383
384 memset(&stats, 0, sizeof(stats));
385
386 for_each_ring(ring, dev_priv, i) {
387 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
388 list_for_each_entry(obj,
389 &ring->batch_pool.cache_list[j],
390 batch_pool_link)
391 per_file_stats(0, obj, &stats);
392 }
393 }
394
395 print_file_stats(m, "batch pool", stats);
396}
397
398#define count_vmas(list, member) do { \
399 list_for_each_entry(vma, list, member) { \
400 size += i915_gem_obj_ggtt_size(vma->obj); \
401 ++count; \
402 if (vma->obj->map_and_fenceable) { \
403 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
404 ++mappable_count; \
405 } \
406 } \
407} while (0)
408
409static int i915_gem_object_info(struct seq_file *m, void* data)
410{
411 struct drm_info_node *node = m->private;
412 struct drm_device *dev = node->minor->dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414 u32 count, mappable_count, purgeable_count;
415 size_t size, mappable_size, purgeable_size;
416 struct drm_i915_gem_object *obj;
417 struct i915_address_space *vm = &dev_priv->gtt.base;
418 struct drm_file *file;
419 struct i915_vma *vma;
420 int ret;
421
422 ret = mutex_lock_interruptible(&dev->struct_mutex);
423 if (ret)
424 return ret;
425
426 seq_printf(m, "%u objects, %zu bytes\n",
427 dev_priv->mm.object_count,
428 dev_priv->mm.object_memory);
429
430 size = count = mappable_size = mappable_count = 0;
431 count_objects(&dev_priv->mm.bound_list, global_list);
432 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
433 count, mappable_count, size, mappable_size);
434
435 size = count = mappable_size = mappable_count = 0;
436 count_vmas(&vm->active_list, mm_list);
437 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
438 count, mappable_count, size, mappable_size);
439
440 size = count = mappable_size = mappable_count = 0;
441 count_vmas(&vm->inactive_list, mm_list);
442 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
443 count, mappable_count, size, mappable_size);
444
445 size = count = purgeable_size = purgeable_count = 0;
446 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
447 size += obj->base.size, ++count;
448 if (obj->madv == I915_MADV_DONTNEED)
449 purgeable_size += obj->base.size, ++purgeable_count;
450 }
451 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
452
453 size = count = mappable_size = mappable_count = 0;
454 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
455 if (obj->fault_mappable) {
456 size += i915_gem_obj_ggtt_size(obj);
457 ++count;
458 }
459 if (obj->pin_mappable) {
460 mappable_size += i915_gem_obj_ggtt_size(obj);
461 ++mappable_count;
462 }
463 if (obj->madv == I915_MADV_DONTNEED) {
464 purgeable_size += obj->base.size;
465 ++purgeable_count;
466 }
467 }
468 seq_printf(m, "%u purgeable objects, %zu bytes\n",
469 purgeable_count, purgeable_size);
470 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
471 mappable_count, mappable_size);
472 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
473 count, size);
474
475 seq_printf(m, "%zu [%lu] gtt total\n",
476 dev_priv->gtt.base.total,
477 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
478
479 seq_putc(m, '\n');
480 print_batch_pool_stats(m, dev_priv);
481
482 seq_putc(m, '\n');
483 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
484 struct file_stats stats;
485 struct task_struct *task;
486
487 memset(&stats, 0, sizeof(stats));
488 stats.file_priv = file->driver_priv;
489 spin_lock(&file->table_lock);
490 idr_for_each(&file->object_idr, per_file_stats, &stats);
491 spin_unlock(&file->table_lock);
492 /*
493 * Although we have a valid reference on file->pid, that does
494 * not guarantee that the task_struct who called get_pid() is
495 * still alive (e.g. get_pid(current) => fork() => exit()).
496 * Therefore, we need to protect this ->comm access using RCU.
497 */
498 rcu_read_lock();
499 task = pid_task(file->pid, PIDTYPE_PID);
500 print_file_stats(m, task ? task->comm : "<unknown>", stats);
501 rcu_read_unlock();
502 }
503
504 mutex_unlock(&dev->struct_mutex);
505
506 return 0;
507}
508
509static int i915_gem_gtt_info(struct seq_file *m, void *data)
510{
511 struct drm_info_node *node = m->private;
512 struct drm_device *dev = node->minor->dev;
513 uintptr_t list = (uintptr_t) node->info_ent->data;
514 struct drm_i915_private *dev_priv = dev->dev_private;
515 struct drm_i915_gem_object *obj;
516 size_t total_obj_size, total_gtt_size;
517 int count, ret;
518
519 ret = mutex_lock_interruptible(&dev->struct_mutex);
520 if (ret)
521 return ret;
522
523 total_obj_size = total_gtt_size = count = 0;
524 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
525 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
526 continue;
527
528 seq_puts(m, " ");
529 describe_obj(m, obj);
530 seq_putc(m, '\n');
531 total_obj_size += obj->base.size;
532 total_gtt_size += i915_gem_obj_ggtt_size(obj);
533 count++;
534 }
535
536 mutex_unlock(&dev->struct_mutex);
537
538 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
539 count, total_obj_size, total_gtt_size);
540
541 return 0;
542}
543
544static int i915_gem_pageflip_info(struct seq_file *m, void *data)
545{
546 struct drm_info_node *node = m->private;
547 struct drm_device *dev = node->minor->dev;
548 struct drm_i915_private *dev_priv = dev->dev_private;
549 struct intel_crtc *crtc;
550 int ret;
551
552 ret = mutex_lock_interruptible(&dev->struct_mutex);
553 if (ret)
554 return ret;
555
556 for_each_intel_crtc(dev, crtc) {
557 const char pipe = pipe_name(crtc->pipe);
558 const char plane = plane_name(crtc->plane);
559 struct intel_unpin_work *work;
560
561 spin_lock_irq(&dev->event_lock);
562 work = crtc->unpin_work;
563 if (work == NULL) {
564 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
565 pipe, plane);
566 } else {
567 u32 addr;
568
569 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
570 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
571 pipe, plane);
572 } else {
573 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
574 pipe, plane);
575 }
576 if (work->flip_queued_req) {
577 struct intel_engine_cs *ring =
578 i915_gem_request_get_ring(work->flip_queued_req);
579
580 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
581 ring->name,
582 i915_gem_request_get_seqno(work->flip_queued_req),
583 dev_priv->next_seqno,
584 ring->get_seqno(ring, true),
585 i915_gem_request_completed(work->flip_queued_req, true));
586 } else
587 seq_printf(m, "Flip not associated with any ring\n");
588 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
589 work->flip_queued_vblank,
590 work->flip_ready_vblank,
591 drm_crtc_vblank_count(&crtc->base));
592 if (work->enable_stall_check)
593 seq_puts(m, "Stall check enabled, ");
594 else
595 seq_puts(m, "Stall check waiting for page flip ioctl, ");
596 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
597
598 if (INTEL_INFO(dev)->gen >= 4)
599 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
600 else
601 addr = I915_READ(DSPADDR(crtc->plane));
602 seq_printf(m, "Current scanout address 0x%08x\n", addr);
603
604 if (work->pending_flip_obj) {
605 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
606 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
607 }
608 }
609 spin_unlock_irq(&dev->event_lock);
610 }
611
612 mutex_unlock(&dev->struct_mutex);
613
614 return 0;
615}
616
617static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
618{
619 struct drm_info_node *node = m->private;
620 struct drm_device *dev = node->minor->dev;
621 struct drm_i915_private *dev_priv = dev->dev_private;
622 struct drm_i915_gem_object *obj;
623 struct intel_engine_cs *ring;
624 int total = 0;
625 int ret, i, j;
626
627 ret = mutex_lock_interruptible(&dev->struct_mutex);
628 if (ret)
629 return ret;
630
631 for_each_ring(ring, dev_priv, i) {
632 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
633 int count;
634
635 count = 0;
636 list_for_each_entry(obj,
637 &ring->batch_pool.cache_list[j],
638 batch_pool_link)
639 count++;
640 seq_printf(m, "%s cache[%d]: %d objects\n",
641 ring->name, j, count);
642
643 list_for_each_entry(obj,
644 &ring->batch_pool.cache_list[j],
645 batch_pool_link) {
646 seq_puts(m, " ");
647 describe_obj(m, obj);
648 seq_putc(m, '\n');
649 }
650
651 total += count;
652 }
653 }
654
655 seq_printf(m, "total: %d\n", total);
656
657 mutex_unlock(&dev->struct_mutex);
658
659 return 0;
660}
661
662static int i915_gem_request_info(struct seq_file *m, void *data)
663{
664 struct drm_info_node *node = m->private;
665 struct drm_device *dev = node->minor->dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
667 struct intel_engine_cs *ring;
668 struct drm_i915_gem_request *rq;
669 int ret, any, i;
670
671 ret = mutex_lock_interruptible(&dev->struct_mutex);
672 if (ret)
673 return ret;
674
675 any = 0;
676 for_each_ring(ring, dev_priv, i) {
677 int count;
678
679 count = 0;
680 list_for_each_entry(rq, &ring->request_list, list)
681 count++;
682 if (count == 0)
683 continue;
684
685 seq_printf(m, "%s requests: %d\n", ring->name, count);
686 list_for_each_entry(rq, &ring->request_list, list) {
687 struct task_struct *task;
688
689 rcu_read_lock();
690 task = NULL;
691 if (rq->pid)
692 task = pid_task(rq->pid, PIDTYPE_PID);
693 seq_printf(m, " %x @ %d: %s [%d]\n",
694 rq->seqno,
695 (int) (jiffies - rq->emitted_jiffies),
696 task ? task->comm : "<unknown>",
697 task ? task->pid : -1);
698 rcu_read_unlock();
699 }
700
701 any++;
702 }
703 mutex_unlock(&dev->struct_mutex);
704
705 if (any == 0)
706 seq_puts(m, "No requests\n");
707
708 return 0;
709}
710
711static void i915_ring_seqno_info(struct seq_file *m,
712 struct intel_engine_cs *ring)
713{
714 if (ring->get_seqno) {
715 seq_printf(m, "Current sequence (%s): %x\n",
716 ring->name, ring->get_seqno(ring, false));
717 }
718}
719
720static int i915_gem_seqno_info(struct seq_file *m, void *data)
721{
722 struct drm_info_node *node = m->private;
723 struct drm_device *dev = node->minor->dev;
724 struct drm_i915_private *dev_priv = dev->dev_private;
725 struct intel_engine_cs *ring;
726 int ret, i;
727
728 ret = mutex_lock_interruptible(&dev->struct_mutex);
729 if (ret)
730 return ret;
731 intel_runtime_pm_get(dev_priv);
732
733 for_each_ring(ring, dev_priv, i)
734 i915_ring_seqno_info(m, ring);
735
736 intel_runtime_pm_put(dev_priv);
737 mutex_unlock(&dev->struct_mutex);
738
739 return 0;
740}
741
742
743static int i915_interrupt_info(struct seq_file *m, void *data)
744{
745 struct drm_info_node *node = m->private;
746 struct drm_device *dev = node->minor->dev;
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 struct intel_engine_cs *ring;
749 int ret, i, pipe;
750
751 ret = mutex_lock_interruptible(&dev->struct_mutex);
752 if (ret)
753 return ret;
754 intel_runtime_pm_get(dev_priv);
755
756 if (IS_CHERRYVIEW(dev)) {
757 seq_printf(m, "Master Interrupt Control:\t%08x\n",
758 I915_READ(GEN8_MASTER_IRQ));
759
760 seq_printf(m, "Display IER:\t%08x\n",
761 I915_READ(VLV_IER));
762 seq_printf(m, "Display IIR:\t%08x\n",
763 I915_READ(VLV_IIR));
764 seq_printf(m, "Display IIR_RW:\t%08x\n",
765 I915_READ(VLV_IIR_RW));
766 seq_printf(m, "Display IMR:\t%08x\n",
767 I915_READ(VLV_IMR));
768 for_each_pipe(dev_priv, pipe)
769 seq_printf(m, "Pipe %c stat:\t%08x\n",
770 pipe_name(pipe),
771 I915_READ(PIPESTAT(pipe)));
772
773 seq_printf(m, "Port hotplug:\t%08x\n",
774 I915_READ(PORT_HOTPLUG_EN));
775 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
776 I915_READ(VLV_DPFLIPSTAT));
777 seq_printf(m, "DPINVGTT:\t%08x\n",
778 I915_READ(DPINVGTT));
779
780 for (i = 0; i < 4; i++) {
781 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
782 i, I915_READ(GEN8_GT_IMR(i)));
783 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
784 i, I915_READ(GEN8_GT_IIR(i)));
785 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
786 i, I915_READ(GEN8_GT_IER(i)));
787 }
788
789 seq_printf(m, "PCU interrupt mask:\t%08x\n",
790 I915_READ(GEN8_PCU_IMR));
791 seq_printf(m, "PCU interrupt identity:\t%08x\n",
792 I915_READ(GEN8_PCU_IIR));
793 seq_printf(m, "PCU interrupt enable:\t%08x\n",
794 I915_READ(GEN8_PCU_IER));
795 } else if (INTEL_INFO(dev)->gen >= 8) {
796 seq_printf(m, "Master Interrupt Control:\t%08x\n",
797 I915_READ(GEN8_MASTER_IRQ));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 for_each_pipe(dev_priv, pipe) {
809 if (!intel_display_power_is_enabled(dev_priv,
810 POWER_DOMAIN_PIPE(pipe))) {
811 seq_printf(m, "Pipe %c power disabled\n",
812 pipe_name(pipe));
813 continue;
814 }
815 seq_printf(m, "Pipe %c IMR:\t%08x\n",
816 pipe_name(pipe),
817 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
818 seq_printf(m, "Pipe %c IIR:\t%08x\n",
819 pipe_name(pipe),
820 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
821 seq_printf(m, "Pipe %c IER:\t%08x\n",
822 pipe_name(pipe),
823 I915_READ(GEN8_DE_PIPE_IER(pipe)));
824 }
825
826 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
827 I915_READ(GEN8_DE_PORT_IMR));
828 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
829 I915_READ(GEN8_DE_PORT_IIR));
830 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
831 I915_READ(GEN8_DE_PORT_IER));
832
833 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
834 I915_READ(GEN8_DE_MISC_IMR));
835 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
836 I915_READ(GEN8_DE_MISC_IIR));
837 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
838 I915_READ(GEN8_DE_MISC_IER));
839
840 seq_printf(m, "PCU interrupt mask:\t%08x\n",
841 I915_READ(GEN8_PCU_IMR));
842 seq_printf(m, "PCU interrupt identity:\t%08x\n",
843 I915_READ(GEN8_PCU_IIR));
844 seq_printf(m, "PCU interrupt enable:\t%08x\n",
845 I915_READ(GEN8_PCU_IER));
846 } else if (IS_VALLEYVIEW(dev)) {
847 seq_printf(m, "Display IER:\t%08x\n",
848 I915_READ(VLV_IER));
849 seq_printf(m, "Display IIR:\t%08x\n",
850 I915_READ(VLV_IIR));
851 seq_printf(m, "Display IIR_RW:\t%08x\n",
852 I915_READ(VLV_IIR_RW));
853 seq_printf(m, "Display IMR:\t%08x\n",
854 I915_READ(VLV_IMR));
855 for_each_pipe(dev_priv, pipe)
856 seq_printf(m, "Pipe %c stat:\t%08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
859
860 seq_printf(m, "Master IER:\t%08x\n",
861 I915_READ(VLV_MASTER_IER));
862
863 seq_printf(m, "Render IER:\t%08x\n",
864 I915_READ(GTIER));
865 seq_printf(m, "Render IIR:\t%08x\n",
866 I915_READ(GTIIR));
867 seq_printf(m, "Render IMR:\t%08x\n",
868 I915_READ(GTIMR));
869
870 seq_printf(m, "PM IER:\t\t%08x\n",
871 I915_READ(GEN6_PMIER));
872 seq_printf(m, "PM IIR:\t\t%08x\n",
873 I915_READ(GEN6_PMIIR));
874 seq_printf(m, "PM IMR:\t\t%08x\n",
875 I915_READ(GEN6_PMIMR));
876
877 seq_printf(m, "Port hotplug:\t%08x\n",
878 I915_READ(PORT_HOTPLUG_EN));
879 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
880 I915_READ(VLV_DPFLIPSTAT));
881 seq_printf(m, "DPINVGTT:\t%08x\n",
882 I915_READ(DPINVGTT));
883
884 } else if (!HAS_PCH_SPLIT(dev)) {
885 seq_printf(m, "Interrupt enable: %08x\n",
886 I915_READ(IER));
887 seq_printf(m, "Interrupt identity: %08x\n",
888 I915_READ(IIR));
889 seq_printf(m, "Interrupt mask: %08x\n",
890 I915_READ(IMR));
891 for_each_pipe(dev_priv, pipe)
892 seq_printf(m, "Pipe %c stat: %08x\n",
893 pipe_name(pipe),
894 I915_READ(PIPESTAT(pipe)));
895 } else {
896 seq_printf(m, "North Display Interrupt enable: %08x\n",
897 I915_READ(DEIER));
898 seq_printf(m, "North Display Interrupt identity: %08x\n",
899 I915_READ(DEIIR));
900 seq_printf(m, "North Display Interrupt mask: %08x\n",
901 I915_READ(DEIMR));
902 seq_printf(m, "South Display Interrupt enable: %08x\n",
903 I915_READ(SDEIER));
904 seq_printf(m, "South Display Interrupt identity: %08x\n",
905 I915_READ(SDEIIR));
906 seq_printf(m, "South Display Interrupt mask: %08x\n",
907 I915_READ(SDEIMR));
908 seq_printf(m, "Graphics Interrupt enable: %08x\n",
909 I915_READ(GTIER));
910 seq_printf(m, "Graphics Interrupt identity: %08x\n",
911 I915_READ(GTIIR));
912 seq_printf(m, "Graphics Interrupt mask: %08x\n",
913 I915_READ(GTIMR));
914 }
915 for_each_ring(ring, dev_priv, i) {
916 if (INTEL_INFO(dev)->gen >= 6) {
917 seq_printf(m,
918 "Graphics Interrupt mask (%s): %08x\n",
919 ring->name, I915_READ_IMR(ring));
920 }
921 i915_ring_seqno_info(m, ring);
922 }
923 intel_runtime_pm_put(dev_priv);
924 mutex_unlock(&dev->struct_mutex);
925
926 return 0;
927}
928
929static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
930{
931 struct drm_info_node *node = m->private;
932 struct drm_device *dev = node->minor->dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 int i, ret;
935
936 ret = mutex_lock_interruptible(&dev->struct_mutex);
937 if (ret)
938 return ret;
939
940 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
941 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
942 for (i = 0; i < dev_priv->num_fence_regs; i++) {
943 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
944
945 seq_printf(m, "Fence %d, pin count = %d, object = ",
946 i, dev_priv->fence_regs[i].pin_count);
947 if (obj == NULL)
948 seq_puts(m, "unused");
949 else
950 describe_obj(m, obj);
951 seq_putc(m, '\n');
952 }
953
954 mutex_unlock(&dev->struct_mutex);
955 return 0;
956}
957
958static int i915_hws_info(struct seq_file *m, void *data)
959{
960 struct drm_info_node *node = m->private;
961 struct drm_device *dev = node->minor->dev;
962 struct drm_i915_private *dev_priv = dev->dev_private;
963 struct intel_engine_cs *ring;
964 const u32 *hws;
965 int i;
966
967 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
968 hws = ring->status_page.page_addr;
969 if (hws == NULL)
970 return 0;
971
972 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
973 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
974 i * 4,
975 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
976 }
977 return 0;
978}
979
980static ssize_t
981i915_error_state_write(struct file *filp,
982 const char __user *ubuf,
983 size_t cnt,
984 loff_t *ppos)
985{
986 struct i915_error_state_file_priv *error_priv = filp->private_data;
987 struct drm_device *dev = error_priv->dev;
988 int ret;
989
990 DRM_DEBUG_DRIVER("Resetting error state\n");
991
992 ret = mutex_lock_interruptible(&dev->struct_mutex);
993 if (ret)
994 return ret;
995
996 i915_destroy_error_state(dev);
997 mutex_unlock(&dev->struct_mutex);
998
999 return cnt;
1000}
1001
1002static int i915_error_state_open(struct inode *inode, struct file *file)
1003{
1004 struct drm_device *dev = inode->i_private;
1005 struct i915_error_state_file_priv *error_priv;
1006
1007 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1008 if (!error_priv)
1009 return -ENOMEM;
1010
1011 error_priv->dev = dev;
1012
1013 i915_error_state_get(dev, error_priv);
1014
1015 file->private_data = error_priv;
1016
1017 return 0;
1018}
1019
1020static int i915_error_state_release(struct inode *inode, struct file *file)
1021{
1022 struct i915_error_state_file_priv *error_priv = file->private_data;
1023
1024 i915_error_state_put(error_priv);
1025 kfree(error_priv);
1026
1027 return 0;
1028}
1029
1030static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1031 size_t count, loff_t *pos)
1032{
1033 struct i915_error_state_file_priv *error_priv = file->private_data;
1034 struct drm_i915_error_state_buf error_str;
1035 loff_t tmp_pos = 0;
1036 ssize_t ret_count = 0;
1037 int ret;
1038
1039 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1040 if (ret)
1041 return ret;
1042
1043 ret = i915_error_state_to_str(&error_str, error_priv);
1044 if (ret)
1045 goto out;
1046
1047 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1048 error_str.buf,
1049 error_str.bytes);
1050
1051 if (ret_count < 0)
1052 ret = ret_count;
1053 else
1054 *pos = error_str.start + ret_count;
1055out:
1056 i915_error_state_buf_release(&error_str);
1057 return ret ?: ret_count;
1058}
1059
1060static const struct file_operations i915_error_state_fops = {
1061 .owner = THIS_MODULE,
1062 .open = i915_error_state_open,
1063 .read = i915_error_state_read,
1064 .write = i915_error_state_write,
1065 .llseek = default_llseek,
1066 .release = i915_error_state_release,
1067};
1068
1069static int
1070i915_next_seqno_get(void *data, u64 *val)
1071{
1072 struct drm_device *dev = data;
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074 int ret;
1075
1076 ret = mutex_lock_interruptible(&dev->struct_mutex);
1077 if (ret)
1078 return ret;
1079
1080 *val = dev_priv->next_seqno;
1081 mutex_unlock(&dev->struct_mutex);
1082
1083 return 0;
1084}
1085
1086static int
1087i915_next_seqno_set(void *data, u64 val)
1088{
1089 struct drm_device *dev = data;
1090 int ret;
1091
1092 ret = mutex_lock_interruptible(&dev->struct_mutex);
1093 if (ret)
1094 return ret;
1095
1096 ret = i915_gem_set_seqno(dev, val);
1097 mutex_unlock(&dev->struct_mutex);
1098
1099 return ret;
1100}
1101
1102DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1103 i915_next_seqno_get, i915_next_seqno_set,
1104 "0x%llx\n");
1105
1106static int i915_frequency_info(struct seq_file *m, void *unused)
1107{
1108 struct drm_info_node *node = m->private;
1109 struct drm_device *dev = node->minor->dev;
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 int ret = 0;
1112
1113 intel_runtime_pm_get(dev_priv);
1114
1115 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1116
1117 if (IS_GEN5(dev)) {
1118 u16 rgvswctl = I915_READ16(MEMSWCTL);
1119 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1120
1121 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1122 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1123 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1124 MEMSTAT_VID_SHIFT);
1125 seq_printf(m, "Current P-state: %d\n",
1126 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1127 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1128 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1129 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1130 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1131 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1132 u32 rpmodectl, rpinclimit, rpdeclimit;
1133 u32 rpstat, cagf, reqf;
1134 u32 rpupei, rpcurup, rpprevup;
1135 u32 rpdownei, rpcurdown, rpprevdown;
1136 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1137 int max_freq;
1138
1139 /* RPSTAT1 is in the GT power well */
1140 ret = mutex_lock_interruptible(&dev->struct_mutex);
1141 if (ret)
1142 goto out;
1143
1144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1145
1146 reqf = I915_READ(GEN6_RPNSWREQ);
1147 if (IS_GEN9(dev))
1148 reqf >>= 23;
1149 else {
1150 reqf &= ~GEN6_TURBO_DISABLE;
1151 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1152 reqf >>= 24;
1153 else
1154 reqf >>= 25;
1155 }
1156 reqf = intel_gpu_freq(dev_priv, reqf);
1157
1158 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1159 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1160 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1161
1162 rpstat = I915_READ(GEN6_RPSTAT1);
1163 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1164 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1165 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1166 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1167 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1168 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1169 if (IS_GEN9(dev))
1170 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1172 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1173 else
1174 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1175 cagf = intel_gpu_freq(dev_priv, cagf);
1176
1177 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1178 mutex_unlock(&dev->struct_mutex);
1179
1180 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1181 pm_ier = I915_READ(GEN6_PMIER);
1182 pm_imr = I915_READ(GEN6_PMIMR);
1183 pm_isr = I915_READ(GEN6_PMISR);
1184 pm_iir = I915_READ(GEN6_PMIIR);
1185 pm_mask = I915_READ(GEN6_PMINTRMSK);
1186 } else {
1187 pm_ier = I915_READ(GEN8_GT_IER(2));
1188 pm_imr = I915_READ(GEN8_GT_IMR(2));
1189 pm_isr = I915_READ(GEN8_GT_ISR(2));
1190 pm_iir = I915_READ(GEN8_GT_IIR(2));
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1192 }
1193 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1194 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1195 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1196 seq_printf(m, "Render p-state ratio: %d\n",
1197 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1198 seq_printf(m, "Render p-state VID: %d\n",
1199 gt_perf_status & 0xff);
1200 seq_printf(m, "Render p-state limit: %d\n",
1201 rp_state_limits & 0xff);
1202 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1203 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1204 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1205 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1206 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1207 seq_printf(m, "CAGF: %dMHz\n", cagf);
1208 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1209 GEN6_CURICONT_MASK);
1210 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1211 GEN6_CURBSYTAVG_MASK);
1212 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1213 GEN6_CURBSYTAVG_MASK);
1214 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1215 GEN6_CURIAVG_MASK);
1216 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1217 GEN6_CURBSYTAVG_MASK);
1218 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1219 GEN6_CURBSYTAVG_MASK);
1220
1221 max_freq = (rp_state_cap & 0xff0000) >> 16;
1222 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1223 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1224 intel_gpu_freq(dev_priv, max_freq));
1225
1226 max_freq = (rp_state_cap & 0xff00) >> 8;
1227 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1228 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1229 intel_gpu_freq(dev_priv, max_freq));
1230
1231 max_freq = rp_state_cap & 0xff;
1232 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1233 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1234 intel_gpu_freq(dev_priv, max_freq));
1235
1236 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1237 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1238
1239 seq_printf(m, "Idle freq: %d MHz\n",
1240 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1241 } else if (IS_VALLEYVIEW(dev)) {
1242 u32 freq_sts;
1243
1244 mutex_lock(&dev_priv->rps.hw_lock);
1245 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1246 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1247 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1248
1249 seq_printf(m, "max GPU freq: %d MHz\n",
1250 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1251
1252 seq_printf(m, "min GPU freq: %d MHz\n",
1253 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1254
1255 seq_printf(m, "idle GPU freq: %d MHz\n",
1256 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1257
1258 seq_printf(m,
1259 "efficient (RPe) frequency: %d MHz\n",
1260 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1261
1262 seq_printf(m, "current GPU freq: %d MHz\n",
1263 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1264 mutex_unlock(&dev_priv->rps.hw_lock);
1265 } else {
1266 seq_puts(m, "no P-state info available\n");
1267 }
1268
1269out:
1270 intel_runtime_pm_put(dev_priv);
1271 return ret;
1272}
1273
1274static int i915_hangcheck_info(struct seq_file *m, void *unused)
1275{
1276 struct drm_info_node *node = m->private;
1277 struct drm_device *dev = node->minor->dev;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279 struct intel_engine_cs *ring;
1280 u64 acthd[I915_NUM_RINGS];
1281 u32 seqno[I915_NUM_RINGS];
1282 int i;
1283
1284 if (!i915.enable_hangcheck) {
1285 seq_printf(m, "Hangcheck disabled\n");
1286 return 0;
1287 }
1288
1289 intel_runtime_pm_get(dev_priv);
1290
1291 for_each_ring(ring, dev_priv, i) {
1292 seqno[i] = ring->get_seqno(ring, false);
1293 acthd[i] = intel_ring_get_active_head(ring);
1294 }
1295
1296 intel_runtime_pm_put(dev_priv);
1297
1298 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1299 seq_printf(m, "Hangcheck active, fires in %dms\n",
1300 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1301 jiffies));
1302 } else
1303 seq_printf(m, "Hangcheck inactive\n");
1304
1305 for_each_ring(ring, dev_priv, i) {
1306 seq_printf(m, "%s:\n", ring->name);
1307 seq_printf(m, "\tseqno = %x [current %x]\n",
1308 ring->hangcheck.seqno, seqno[i]);
1309 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1310 (long long)ring->hangcheck.acthd,
1311 (long long)acthd[i]);
1312 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1313 (long long)ring->hangcheck.max_acthd);
1314 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1315 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1316 }
1317
1318 return 0;
1319}
1320
1321static int ironlake_drpc_info(struct seq_file *m)
1322{
1323 struct drm_info_node *node = m->private;
1324 struct drm_device *dev = node->minor->dev;
1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 u32 rgvmodectl, rstdbyctl;
1327 u16 crstandvid;
1328 int ret;
1329
1330 ret = mutex_lock_interruptible(&dev->struct_mutex);
1331 if (ret)
1332 return ret;
1333 intel_runtime_pm_get(dev_priv);
1334
1335 rgvmodectl = I915_READ(MEMMODECTL);
1336 rstdbyctl = I915_READ(RSTDBYCTL);
1337 crstandvid = I915_READ16(CRSTANDVID);
1338
1339 intel_runtime_pm_put(dev_priv);
1340 mutex_unlock(&dev->struct_mutex);
1341
1342 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1343 "yes" : "no");
1344 seq_printf(m, "Boost freq: %d\n",
1345 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1346 MEMMODE_BOOST_FREQ_SHIFT);
1347 seq_printf(m, "HW control enabled: %s\n",
1348 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1349 seq_printf(m, "SW control enabled: %s\n",
1350 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1351 seq_printf(m, "Gated voltage change: %s\n",
1352 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1353 seq_printf(m, "Starting frequency: P%d\n",
1354 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1355 seq_printf(m, "Max P-state: P%d\n",
1356 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1357 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1358 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1359 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1360 seq_printf(m, "Render standby enabled: %s\n",
1361 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1362 seq_puts(m, "Current RS state: ");
1363 switch (rstdbyctl & RSX_STATUS_MASK) {
1364 case RSX_STATUS_ON:
1365 seq_puts(m, "on\n");
1366 break;
1367 case RSX_STATUS_RC1:
1368 seq_puts(m, "RC1\n");
1369 break;
1370 case RSX_STATUS_RC1E:
1371 seq_puts(m, "RC1E\n");
1372 break;
1373 case RSX_STATUS_RS1:
1374 seq_puts(m, "RS1\n");
1375 break;
1376 case RSX_STATUS_RS2:
1377 seq_puts(m, "RS2 (RC6)\n");
1378 break;
1379 case RSX_STATUS_RS3:
1380 seq_puts(m, "RC3 (RC6+)\n");
1381 break;
1382 default:
1383 seq_puts(m, "unknown\n");
1384 break;
1385 }
1386
1387 return 0;
1388}
1389
1390static int i915_forcewake_domains(struct seq_file *m, void *data)
1391{
1392 struct drm_info_node *node = m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 struct intel_uncore_forcewake_domain *fw_domain;
1396 int i;
1397
1398 spin_lock_irq(&dev_priv->uncore.lock);
1399 for_each_fw_domain(fw_domain, dev_priv, i) {
1400 seq_printf(m, "%s.wake_count = %u\n",
1401 intel_uncore_forcewake_domain_to_str(i),
1402 fw_domain->wake_count);
1403 }
1404 spin_unlock_irq(&dev_priv->uncore.lock);
1405
1406 return 0;
1407}
1408
1409static int vlv_drpc_info(struct seq_file *m)
1410{
1411 struct drm_info_node *node = m->private;
1412 struct drm_device *dev = node->minor->dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 u32 rpmodectl1, rcctl1, pw_status;
1415
1416 intel_runtime_pm_get(dev_priv);
1417
1418 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1419 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1420 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1421
1422 intel_runtime_pm_put(dev_priv);
1423
1424 seq_printf(m, "Video Turbo Mode: %s\n",
1425 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1426 seq_printf(m, "Turbo enabled: %s\n",
1427 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1428 seq_printf(m, "HW control enabled: %s\n",
1429 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1430 seq_printf(m, "SW control enabled: %s\n",
1431 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1432 GEN6_RP_MEDIA_SW_MODE));
1433 seq_printf(m, "RC6 Enabled: %s\n",
1434 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1435 GEN6_RC_CTL_EI_MODE(1))));
1436 seq_printf(m, "Render Power Well: %s\n",
1437 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1438 seq_printf(m, "Media Power Well: %s\n",
1439 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1440
1441 seq_printf(m, "Render RC6 residency since boot: %u\n",
1442 I915_READ(VLV_GT_RENDER_RC6));
1443 seq_printf(m, "Media RC6 residency since boot: %u\n",
1444 I915_READ(VLV_GT_MEDIA_RC6));
1445
1446 return i915_forcewake_domains(m, NULL);
1447}
1448
1449static int gen6_drpc_info(struct seq_file *m)
1450{
1451 struct drm_info_node *node = m->private;
1452 struct drm_device *dev = node->minor->dev;
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1454 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1455 unsigned forcewake_count;
1456 int count = 0, ret;
1457
1458 ret = mutex_lock_interruptible(&dev->struct_mutex);
1459 if (ret)
1460 return ret;
1461 intel_runtime_pm_get(dev_priv);
1462
1463 spin_lock_irq(&dev_priv->uncore.lock);
1464 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1465 spin_unlock_irq(&dev_priv->uncore.lock);
1466
1467 if (forcewake_count) {
1468 seq_puts(m, "RC information inaccurate because somebody "
1469 "holds a forcewake reference \n");
1470 } else {
1471 /* NB: we cannot use forcewake, else we read the wrong values */
1472 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1473 udelay(10);
1474 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1475 }
1476
1477 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1478 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1479
1480 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1481 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1482 mutex_unlock(&dev->struct_mutex);
1483 mutex_lock(&dev_priv->rps.hw_lock);
1484 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1485 mutex_unlock(&dev_priv->rps.hw_lock);
1486
1487 intel_runtime_pm_put(dev_priv);
1488
1489 seq_printf(m, "Video Turbo Mode: %s\n",
1490 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1491 seq_printf(m, "HW control enabled: %s\n",
1492 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1493 seq_printf(m, "SW control enabled: %s\n",
1494 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1495 GEN6_RP_MEDIA_SW_MODE));
1496 seq_printf(m, "RC1e Enabled: %s\n",
1497 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1498 seq_printf(m, "RC6 Enabled: %s\n",
1499 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1500 seq_printf(m, "Deep RC6 Enabled: %s\n",
1501 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1502 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1503 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1504 seq_puts(m, "Current RC state: ");
1505 switch (gt_core_status & GEN6_RCn_MASK) {
1506 case GEN6_RC0:
1507 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1508 seq_puts(m, "Core Power Down\n");
1509 else
1510 seq_puts(m, "on\n");
1511 break;
1512 case GEN6_RC3:
1513 seq_puts(m, "RC3\n");
1514 break;
1515 case GEN6_RC6:
1516 seq_puts(m, "RC6\n");
1517 break;
1518 case GEN6_RC7:
1519 seq_puts(m, "RC7\n");
1520 break;
1521 default:
1522 seq_puts(m, "Unknown\n");
1523 break;
1524 }
1525
1526 seq_printf(m, "Core Power Down: %s\n",
1527 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1528
1529 /* Not exactly sure what this is */
1530 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1531 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1532 seq_printf(m, "RC6 residency since boot: %u\n",
1533 I915_READ(GEN6_GT_GFX_RC6));
1534 seq_printf(m, "RC6+ residency since boot: %u\n",
1535 I915_READ(GEN6_GT_GFX_RC6p));
1536 seq_printf(m, "RC6++ residency since boot: %u\n",
1537 I915_READ(GEN6_GT_GFX_RC6pp));
1538
1539 seq_printf(m, "RC6 voltage: %dmV\n",
1540 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1541 seq_printf(m, "RC6+ voltage: %dmV\n",
1542 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1543 seq_printf(m, "RC6++ voltage: %dmV\n",
1544 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1545 return 0;
1546}
1547
1548static int i915_drpc_info(struct seq_file *m, void *unused)
1549{
1550 struct drm_info_node *node = m->private;
1551 struct drm_device *dev = node->minor->dev;
1552
1553 if (IS_VALLEYVIEW(dev))
1554 return vlv_drpc_info(m);
1555 else if (INTEL_INFO(dev)->gen >= 6)
1556 return gen6_drpc_info(m);
1557 else
1558 return ironlake_drpc_info(m);
1559}
1560
1561static int i915_fbc_status(struct seq_file *m, void *unused)
1562{
1563 struct drm_info_node *node = m->private;
1564 struct drm_device *dev = node->minor->dev;
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!HAS_FBC(dev)) {
1568 seq_puts(m, "FBC unsupported on this chipset\n");
1569 return 0;
1570 }
1571
1572 intel_runtime_pm_get(dev_priv);
1573
1574 if (intel_fbc_enabled(dev)) {
1575 seq_puts(m, "FBC enabled\n");
1576 } else {
1577 seq_puts(m, "FBC disabled: ");
1578 switch (dev_priv->fbc.no_fbc_reason) {
1579 case FBC_OK:
1580 seq_puts(m, "FBC actived, but currently disabled in hardware");
1581 break;
1582 case FBC_UNSUPPORTED:
1583 seq_puts(m, "unsupported by this chipset");
1584 break;
1585 case FBC_NO_OUTPUT:
1586 seq_puts(m, "no outputs");
1587 break;
1588 case FBC_STOLEN_TOO_SMALL:
1589 seq_puts(m, "not enough stolen memory");
1590 break;
1591 case FBC_UNSUPPORTED_MODE:
1592 seq_puts(m, "mode not supported");
1593 break;
1594 case FBC_MODE_TOO_LARGE:
1595 seq_puts(m, "mode too large");
1596 break;
1597 case FBC_BAD_PLANE:
1598 seq_puts(m, "FBC unsupported on plane");
1599 break;
1600 case FBC_NOT_TILED:
1601 seq_puts(m, "scanout buffer not tiled");
1602 break;
1603 case FBC_MULTIPLE_PIPES:
1604 seq_puts(m, "multiple pipes are enabled");
1605 break;
1606 case FBC_MODULE_PARAM:
1607 seq_puts(m, "disabled per module param (default off)");
1608 break;
1609 case FBC_CHIP_DEFAULT:
1610 seq_puts(m, "disabled per chip default");
1611 break;
1612 default:
1613 seq_puts(m, "unknown reason");
1614 }
1615 seq_putc(m, '\n');
1616 }
1617
1618 intel_runtime_pm_put(dev_priv);
1619
1620 return 0;
1621}
1622
1623static int i915_fbc_fc_get(void *data, u64 *val)
1624{
1625 struct drm_device *dev = data;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627
1628 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1629 return -ENODEV;
1630
1631 drm_modeset_lock_all(dev);
1632 *val = dev_priv->fbc.false_color;
1633 drm_modeset_unlock_all(dev);
1634
1635 return 0;
1636}
1637
1638static int i915_fbc_fc_set(void *data, u64 val)
1639{
1640 struct drm_device *dev = data;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 reg;
1643
1644 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1645 return -ENODEV;
1646
1647 drm_modeset_lock_all(dev);
1648
1649 reg = I915_READ(ILK_DPFC_CONTROL);
1650 dev_priv->fbc.false_color = val;
1651
1652 I915_WRITE(ILK_DPFC_CONTROL, val ?
1653 (reg | FBC_CTL_FALSE_COLOR) :
1654 (reg & ~FBC_CTL_FALSE_COLOR));
1655
1656 drm_modeset_unlock_all(dev);
1657 return 0;
1658}
1659
1660DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1661 i915_fbc_fc_get, i915_fbc_fc_set,
1662 "%llu\n");
1663
1664static int i915_ips_status(struct seq_file *m, void *unused)
1665{
1666 struct drm_info_node *node = m->private;
1667 struct drm_device *dev = node->minor->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669
1670 if (!HAS_IPS(dev)) {
1671 seq_puts(m, "not supported\n");
1672 return 0;
1673 }
1674
1675 intel_runtime_pm_get(dev_priv);
1676
1677 seq_printf(m, "Enabled by kernel parameter: %s\n",
1678 yesno(i915.enable_ips));
1679
1680 if (INTEL_INFO(dev)->gen >= 8) {
1681 seq_puts(m, "Currently: unknown\n");
1682 } else {
1683 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1684 seq_puts(m, "Currently: enabled\n");
1685 else
1686 seq_puts(m, "Currently: disabled\n");
1687 }
1688
1689 intel_runtime_pm_put(dev_priv);
1690
1691 return 0;
1692}
1693
1694static int i915_sr_status(struct seq_file *m, void *unused)
1695{
1696 struct drm_info_node *node = m->private;
1697 struct drm_device *dev = node->minor->dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 bool sr_enabled = false;
1700
1701 intel_runtime_pm_get(dev_priv);
1702
1703 if (HAS_PCH_SPLIT(dev))
1704 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1705 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1706 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1707 else if (IS_I915GM(dev))
1708 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1709 else if (IS_PINEVIEW(dev))
1710 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1711
1712 intel_runtime_pm_put(dev_priv);
1713
1714 seq_printf(m, "self-refresh: %s\n",
1715 sr_enabled ? "enabled" : "disabled");
1716
1717 return 0;
1718}
1719
1720static int i915_emon_status(struct seq_file *m, void *unused)
1721{
1722 struct drm_info_node *node = m->private;
1723 struct drm_device *dev = node->minor->dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 unsigned long temp, chipset, gfx;
1726 int ret;
1727
1728 if (!IS_GEN5(dev))
1729 return -ENODEV;
1730
1731 ret = mutex_lock_interruptible(&dev->struct_mutex);
1732 if (ret)
1733 return ret;
1734
1735 temp = i915_mch_val(dev_priv);
1736 chipset = i915_chipset_val(dev_priv);
1737 gfx = i915_gfx_val(dev_priv);
1738 mutex_unlock(&dev->struct_mutex);
1739
1740 seq_printf(m, "GMCH temp: %ld\n", temp);
1741 seq_printf(m, "Chipset power: %ld\n", chipset);
1742 seq_printf(m, "GFX power: %ld\n", gfx);
1743 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1744
1745 return 0;
1746}
1747
1748static int i915_ring_freq_table(struct seq_file *m, void *unused)
1749{
1750 struct drm_info_node *node = m->private;
1751 struct drm_device *dev = node->minor->dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 int ret = 0;
1754 int gpu_freq, ia_freq;
1755
1756 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1757 seq_puts(m, "unsupported on this chipset\n");
1758 return 0;
1759 }
1760
1761 intel_runtime_pm_get(dev_priv);
1762
1763 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1764
1765 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1766 if (ret)
1767 goto out;
1768
1769 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1770
1771 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1772 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1773 gpu_freq++) {
1774 ia_freq = gpu_freq;
1775 sandybridge_pcode_read(dev_priv,
1776 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1777 &ia_freq);
1778 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1779 intel_gpu_freq(dev_priv, gpu_freq),
1780 ((ia_freq >> 0) & 0xff) * 100,
1781 ((ia_freq >> 8) & 0xff) * 100);
1782 }
1783
1784 mutex_unlock(&dev_priv->rps.hw_lock);
1785
1786out:
1787 intel_runtime_pm_put(dev_priv);
1788 return ret;
1789}
1790
1791static int i915_opregion(struct seq_file *m, void *unused)
1792{
1793 struct drm_info_node *node = m->private;
1794 struct drm_device *dev = node->minor->dev;
1795 struct drm_i915_private *dev_priv = dev->dev_private;
1796 struct intel_opregion *opregion = &dev_priv->opregion;
1797 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1798 int ret;
1799
1800 if (data == NULL)
1801 return -ENOMEM;
1802
1803 ret = mutex_lock_interruptible(&dev->struct_mutex);
1804 if (ret)
1805 goto out;
1806
1807 if (opregion->header) {
1808 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1809 seq_write(m, data, OPREGION_SIZE);
1810 }
1811
1812 mutex_unlock(&dev->struct_mutex);
1813
1814out:
1815 kfree(data);
1816 return 0;
1817}
1818
1819static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1820{
1821 struct drm_info_node *node = m->private;
1822 struct drm_device *dev = node->minor->dev;
1823 struct intel_fbdev *ifbdev = NULL;
1824 struct intel_framebuffer *fb;
1825
1826#ifdef CONFIG_DRM_I915_FBDEV
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828
1829 ifbdev = dev_priv->fbdev;
1830 fb = to_intel_framebuffer(ifbdev->helper.fb);
1831
1832 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1833 fb->base.width,
1834 fb->base.height,
1835 fb->base.depth,
1836 fb->base.bits_per_pixel,
1837 fb->base.modifier[0],
1838 atomic_read(&fb->base.refcount.refcount));
1839 describe_obj(m, fb->obj);
1840 seq_putc(m, '\n');
1841#endif
1842
1843 mutex_lock(&dev->mode_config.fb_lock);
1844 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1845 if (ifbdev && &fb->base == ifbdev->helper.fb)
1846 continue;
1847
1848 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1849 fb->base.width,
1850 fb->base.height,
1851 fb->base.depth,
1852 fb->base.bits_per_pixel,
1853 fb->base.modifier[0],
1854 atomic_read(&fb->base.refcount.refcount));
1855 describe_obj(m, fb->obj);
1856 seq_putc(m, '\n');
1857 }
1858 mutex_unlock(&dev->mode_config.fb_lock);
1859
1860 return 0;
1861}
1862
1863static void describe_ctx_ringbuf(struct seq_file *m,
1864 struct intel_ringbuffer *ringbuf)
1865{
1866 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1867 ringbuf->space, ringbuf->head, ringbuf->tail,
1868 ringbuf->last_retired_head);
1869}
1870
1871static int i915_context_status(struct seq_file *m, void *unused)
1872{
1873 struct drm_info_node *node = m->private;
1874 struct drm_device *dev = node->minor->dev;
1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876 struct intel_engine_cs *ring;
1877 struct intel_context *ctx;
1878 int ret, i;
1879
1880 ret = mutex_lock_interruptible(&dev->struct_mutex);
1881 if (ret)
1882 return ret;
1883
1884 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1885 if (!i915.enable_execlists &&
1886 ctx->legacy_hw_ctx.rcs_state == NULL)
1887 continue;
1888
1889 seq_puts(m, "HW context ");
1890 describe_ctx(m, ctx);
1891 for_each_ring(ring, dev_priv, i) {
1892 if (ring->default_context == ctx)
1893 seq_printf(m, "(default context %s) ",
1894 ring->name);
1895 }
1896
1897 if (i915.enable_execlists) {
1898 seq_putc(m, '\n');
1899 for_each_ring(ring, dev_priv, i) {
1900 struct drm_i915_gem_object *ctx_obj =
1901 ctx->engine[i].state;
1902 struct intel_ringbuffer *ringbuf =
1903 ctx->engine[i].ringbuf;
1904
1905 seq_printf(m, "%s: ", ring->name);
1906 if (ctx_obj)
1907 describe_obj(m, ctx_obj);
1908 if (ringbuf)
1909 describe_ctx_ringbuf(m, ringbuf);
1910 seq_putc(m, '\n');
1911 }
1912 } else {
1913 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1914 }
1915
1916 seq_putc(m, '\n');
1917 }
1918
1919 mutex_unlock(&dev->struct_mutex);
1920
1921 return 0;
1922}
1923
1924static void i915_dump_lrc_obj(struct seq_file *m,
1925 struct intel_engine_cs *ring,
1926 struct drm_i915_gem_object *ctx_obj)
1927{
1928 struct page *page;
1929 uint32_t *reg_state;
1930 int j;
1931 unsigned long ggtt_offset = 0;
1932
1933 if (ctx_obj == NULL) {
1934 seq_printf(m, "Context on %s with no gem object\n",
1935 ring->name);
1936 return;
1937 }
1938
1939 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1940 intel_execlists_ctx_id(ctx_obj));
1941
1942 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1943 seq_puts(m, "\tNot bound in GGTT\n");
1944 else
1945 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1946
1947 if (i915_gem_object_get_pages(ctx_obj)) {
1948 seq_puts(m, "\tFailed to get pages for context object\n");
1949 return;
1950 }
1951
1952 page = i915_gem_object_get_page(ctx_obj, 1);
1953 if (!WARN_ON(page == NULL)) {
1954 reg_state = kmap_atomic(page);
1955
1956 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1957 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1958 ggtt_offset + 4096 + (j * 4),
1959 reg_state[j], reg_state[j + 1],
1960 reg_state[j + 2], reg_state[j + 3]);
1961 }
1962 kunmap_atomic(reg_state);
1963 }
1964
1965 seq_putc(m, '\n');
1966}
1967
1968static int i915_dump_lrc(struct seq_file *m, void *unused)
1969{
1970 struct drm_info_node *node = (struct drm_info_node *) m->private;
1971 struct drm_device *dev = node->minor->dev;
1972 struct drm_i915_private *dev_priv = dev->dev_private;
1973 struct intel_engine_cs *ring;
1974 struct intel_context *ctx;
1975 int ret, i;
1976
1977 if (!i915.enable_execlists) {
1978 seq_printf(m, "Logical Ring Contexts are disabled\n");
1979 return 0;
1980 }
1981
1982 ret = mutex_lock_interruptible(&dev->struct_mutex);
1983 if (ret)
1984 return ret;
1985
1986 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1987 for_each_ring(ring, dev_priv, i) {
1988 if (ring->default_context != ctx)
1989 i915_dump_lrc_obj(m, ring,
1990 ctx->engine[i].state);
1991 }
1992 }
1993
1994 mutex_unlock(&dev->struct_mutex);
1995
1996 return 0;
1997}
1998
1999static int i915_execlists(struct seq_file *m, void *data)
2000{
2001 struct drm_info_node *node = (struct drm_info_node *)m->private;
2002 struct drm_device *dev = node->minor->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_engine_cs *ring;
2005 u32 status_pointer;
2006 u8 read_pointer;
2007 u8 write_pointer;
2008 u32 status;
2009 u32 ctx_id;
2010 struct list_head *cursor;
2011 int ring_id, i;
2012 int ret;
2013
2014 if (!i915.enable_execlists) {
2015 seq_puts(m, "Logical Ring Contexts are disabled\n");
2016 return 0;
2017 }
2018
2019 ret = mutex_lock_interruptible(&dev->struct_mutex);
2020 if (ret)
2021 return ret;
2022
2023 intel_runtime_pm_get(dev_priv);
2024
2025 for_each_ring(ring, dev_priv, ring_id) {
2026 struct drm_i915_gem_request *head_req = NULL;
2027 int count = 0;
2028 unsigned long flags;
2029
2030 seq_printf(m, "%s\n", ring->name);
2031
2032 status = I915_READ(RING_EXECLIST_STATUS(ring));
2033 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2034 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2035 status, ctx_id);
2036
2037 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2038 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2039
2040 read_pointer = ring->next_context_status_buffer;
2041 write_pointer = status_pointer & 0x07;
2042 if (read_pointer > write_pointer)
2043 write_pointer += 6;
2044 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2045 read_pointer, write_pointer);
2046
2047 for (i = 0; i < 6; i++) {
2048 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2049 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2050
2051 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2052 i, status, ctx_id);
2053 }
2054
2055 spin_lock_irqsave(&ring->execlist_lock, flags);
2056 list_for_each(cursor, &ring->execlist_queue)
2057 count++;
2058 head_req = list_first_entry_or_null(&ring->execlist_queue,
2059 struct drm_i915_gem_request, execlist_link);
2060 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2061
2062 seq_printf(m, "\t%d requests in queue\n", count);
2063 if (head_req) {
2064 struct drm_i915_gem_object *ctx_obj;
2065
2066 ctx_obj = head_req->ctx->engine[ring_id].state;
2067 seq_printf(m, "\tHead request id: %u\n",
2068 intel_execlists_ctx_id(ctx_obj));
2069 seq_printf(m, "\tHead request tail: %u\n",
2070 head_req->tail);
2071 }
2072
2073 seq_putc(m, '\n');
2074 }
2075
2076 intel_runtime_pm_put(dev_priv);
2077 mutex_unlock(&dev->struct_mutex);
2078
2079 return 0;
2080}
2081
2082static const char *swizzle_string(unsigned swizzle)
2083{
2084 switch (swizzle) {
2085 case I915_BIT_6_SWIZZLE_NONE:
2086 return "none";
2087 case I915_BIT_6_SWIZZLE_9:
2088 return "bit9";
2089 case I915_BIT_6_SWIZZLE_9_10:
2090 return "bit9/bit10";
2091 case I915_BIT_6_SWIZZLE_9_11:
2092 return "bit9/bit11";
2093 case I915_BIT_6_SWIZZLE_9_10_11:
2094 return "bit9/bit10/bit11";
2095 case I915_BIT_6_SWIZZLE_9_17:
2096 return "bit9/bit17";
2097 case I915_BIT_6_SWIZZLE_9_10_17:
2098 return "bit9/bit10/bit17";
2099 case I915_BIT_6_SWIZZLE_UNKNOWN:
2100 return "unknown";
2101 }
2102
2103 return "bug";
2104}
2105
2106static int i915_swizzle_info(struct seq_file *m, void *data)
2107{
2108 struct drm_info_node *node = m->private;
2109 struct drm_device *dev = node->minor->dev;
2110 struct drm_i915_private *dev_priv = dev->dev_private;
2111 int ret;
2112
2113 ret = mutex_lock_interruptible(&dev->struct_mutex);
2114 if (ret)
2115 return ret;
2116 intel_runtime_pm_get(dev_priv);
2117
2118 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2119 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2120 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2121 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2122
2123 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2124 seq_printf(m, "DDC = 0x%08x\n",
2125 I915_READ(DCC));
2126 seq_printf(m, "DDC2 = 0x%08x\n",
2127 I915_READ(DCC2));
2128 seq_printf(m, "C0DRB3 = 0x%04x\n",
2129 I915_READ16(C0DRB3));
2130 seq_printf(m, "C1DRB3 = 0x%04x\n",
2131 I915_READ16(C1DRB3));
2132 } else if (INTEL_INFO(dev)->gen >= 6) {
2133 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2134 I915_READ(MAD_DIMM_C0));
2135 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2136 I915_READ(MAD_DIMM_C1));
2137 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2138 I915_READ(MAD_DIMM_C2));
2139 seq_printf(m, "TILECTL = 0x%08x\n",
2140 I915_READ(TILECTL));
2141 if (INTEL_INFO(dev)->gen >= 8)
2142 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2143 I915_READ(GAMTARBMODE));
2144 else
2145 seq_printf(m, "ARB_MODE = 0x%08x\n",
2146 I915_READ(ARB_MODE));
2147 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2148 I915_READ(DISP_ARB_CTL));
2149 }
2150
2151 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2152 seq_puts(m, "L-shaped memory detected\n");
2153
2154 intel_runtime_pm_put(dev_priv);
2155 mutex_unlock(&dev->struct_mutex);
2156
2157 return 0;
2158}
2159
2160static int per_file_ctx(int id, void *ptr, void *data)
2161{
2162 struct intel_context *ctx = ptr;
2163 struct seq_file *m = data;
2164 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2165
2166 if (!ppgtt) {
2167 seq_printf(m, " no ppgtt for context %d\n",
2168 ctx->user_handle);
2169 return 0;
2170 }
2171
2172 if (i915_gem_context_is_default(ctx))
2173 seq_puts(m, " default context:\n");
2174 else
2175 seq_printf(m, " context %d:\n", ctx->user_handle);
2176 ppgtt->debug_dump(ppgtt, m);
2177
2178 return 0;
2179}
2180
2181static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2182{
2183 struct drm_i915_private *dev_priv = dev->dev_private;
2184 struct intel_engine_cs *ring;
2185 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2186 int unused, i;
2187
2188 if (!ppgtt)
2189 return;
2190
2191 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2192 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2193 for_each_ring(ring, dev_priv, unused) {
2194 seq_printf(m, "%s\n", ring->name);
2195 for (i = 0; i < 4; i++) {
2196 u32 offset = 0x270 + i * 8;
2197 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2198 pdp <<= 32;
2199 pdp |= I915_READ(ring->mmio_base + offset);
2200 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2201 }
2202 }
2203}
2204
2205static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2206{
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_engine_cs *ring;
2209 struct drm_file *file;
2210 int i;
2211
2212 if (INTEL_INFO(dev)->gen == 6)
2213 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2214
2215 for_each_ring(ring, dev_priv, i) {
2216 seq_printf(m, "%s\n", ring->name);
2217 if (INTEL_INFO(dev)->gen == 7)
2218 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2219 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2220 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2221 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2222 }
2223 if (dev_priv->mm.aliasing_ppgtt) {
2224 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2225
2226 seq_puts(m, "aliasing PPGTT:\n");
2227 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
2228
2229 ppgtt->debug_dump(ppgtt, m);
2230 }
2231
2232 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2233 struct drm_i915_file_private *file_priv = file->driver_priv;
2234
2235 seq_printf(m, "proc: %s\n",
2236 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2237 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2238 }
2239 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2240}
2241
2242static int i915_ppgtt_info(struct seq_file *m, void *data)
2243{
2244 struct drm_info_node *node = m->private;
2245 struct drm_device *dev = node->minor->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2249 if (ret)
2250 return ret;
2251 intel_runtime_pm_get(dev_priv);
2252
2253 if (INTEL_INFO(dev)->gen >= 8)
2254 gen8_ppgtt_info(m, dev);
2255 else if (INTEL_INFO(dev)->gen >= 6)
2256 gen6_ppgtt_info(m, dev);
2257
2258 intel_runtime_pm_put(dev_priv);
2259 mutex_unlock(&dev->struct_mutex);
2260
2261 return 0;
2262}
2263
2264static int i915_rps_boost_info(struct seq_file *m, void *data)
2265{
2266 struct drm_info_node *node = m->private;
2267 struct drm_device *dev = node->minor->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct drm_file *file;
2270 int ret;
2271
2272 ret = mutex_lock_interruptible(&dev->struct_mutex);
2273 if (ret)
2274 return ret;
2275
2276 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2277 if (ret)
2278 goto unlock;
2279
2280 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2281 struct drm_i915_file_private *file_priv = file->driver_priv;
2282 struct task_struct *task;
2283
2284 rcu_read_lock();
2285 task = pid_task(file->pid, PIDTYPE_PID);
2286 seq_printf(m, "%s [%d]: %d boosts%s\n",
2287 task ? task->comm : "<unknown>",
2288 task ? task->pid : -1,
2289 file_priv->rps_boosts,
2290 list_empty(&file_priv->rps_boost) ? "" : ", active");
2291 rcu_read_unlock();
2292 }
2293 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2294
2295 mutex_unlock(&dev_priv->rps.hw_lock);
2296unlock:
2297 mutex_unlock(&dev->struct_mutex);
2298
2299 return ret;
2300}
2301
2302static int i915_llc(struct seq_file *m, void *data)
2303{
2304 struct drm_info_node *node = m->private;
2305 struct drm_device *dev = node->minor->dev;
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307
2308 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2309 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2310 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2311
2312 return 0;
2313}
2314
2315static int i915_edp_psr_status(struct seq_file *m, void *data)
2316{
2317 struct drm_info_node *node = m->private;
2318 struct drm_device *dev = node->minor->dev;
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320 u32 psrperf = 0;
2321 u32 stat[3];
2322 enum pipe pipe;
2323 bool enabled = false;
2324
2325 if (!HAS_PSR(dev)) {
2326 seq_puts(m, "PSR not supported\n");
2327 return 0;
2328 }
2329
2330 intel_runtime_pm_get(dev_priv);
2331
2332 mutex_lock(&dev_priv->psr.lock);
2333 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2334 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2335 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2336 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2337 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2338 dev_priv->psr.busy_frontbuffer_bits);
2339 seq_printf(m, "Re-enable work scheduled: %s\n",
2340 yesno(work_busy(&dev_priv->psr.work.work)));
2341
2342 if (HAS_DDI(dev))
2343 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2344 else {
2345 for_each_pipe(dev_priv, pipe) {
2346 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2347 VLV_EDP_PSR_CURR_STATE_MASK;
2348 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2349 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2350 enabled = true;
2351 }
2352 }
2353 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2354
2355 if (!HAS_DDI(dev))
2356 for_each_pipe(dev_priv, pipe) {
2357 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2358 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2359 seq_printf(m, " pipe %c", pipe_name(pipe));
2360 }
2361 seq_puts(m, "\n");
2362
2363 seq_printf(m, "Link standby: %s\n",
2364 yesno((bool)dev_priv->psr.link_standby));
2365
2366 /* CHV PSR has no kind of performance counter */
2367 if (HAS_DDI(dev)) {
2368 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2369 EDP_PSR_PERF_CNT_MASK;
2370
2371 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2372 }
2373 mutex_unlock(&dev_priv->psr.lock);
2374
2375 intel_runtime_pm_put(dev_priv);
2376 return 0;
2377}
2378
2379static int i915_sink_crc(struct seq_file *m, void *data)
2380{
2381 struct drm_info_node *node = m->private;
2382 struct drm_device *dev = node->minor->dev;
2383 struct intel_encoder *encoder;
2384 struct intel_connector *connector;
2385 struct intel_dp *intel_dp = NULL;
2386 int ret;
2387 u8 crc[6];
2388
2389 drm_modeset_lock_all(dev);
2390 for_each_intel_connector(dev, connector) {
2391
2392 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2393 continue;
2394
2395 if (!connector->base.encoder)
2396 continue;
2397
2398 encoder = to_intel_encoder(connector->base.encoder);
2399 if (encoder->type != INTEL_OUTPUT_EDP)
2400 continue;
2401
2402 intel_dp = enc_to_intel_dp(&encoder->base);
2403
2404 ret = intel_dp_sink_crc(intel_dp, crc);
2405 if (ret)
2406 goto out;
2407
2408 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2409 crc[0], crc[1], crc[2],
2410 crc[3], crc[4], crc[5]);
2411 goto out;
2412 }
2413 ret = -ENODEV;
2414out:
2415 drm_modeset_unlock_all(dev);
2416 return ret;
2417}
2418
2419static int i915_energy_uJ(struct seq_file *m, void *data)
2420{
2421 struct drm_info_node *node = m->private;
2422 struct drm_device *dev = node->minor->dev;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 u64 power;
2425 u32 units;
2426
2427 if (INTEL_INFO(dev)->gen < 6)
2428 return -ENODEV;
2429
2430 intel_runtime_pm_get(dev_priv);
2431
2432 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2433 power = (power & 0x1f00) >> 8;
2434 units = 1000000 / (1 << power); /* convert to uJ */
2435 power = I915_READ(MCH_SECP_NRG_STTS);
2436 power *= units;
2437
2438 intel_runtime_pm_put(dev_priv);
2439
2440 seq_printf(m, "%llu", (long long unsigned)power);
2441
2442 return 0;
2443}
2444
2445static int i915_pc8_status(struct seq_file *m, void *unused)
2446{
2447 struct drm_info_node *node = m->private;
2448 struct drm_device *dev = node->minor->dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450
2451 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2452 seq_puts(m, "not supported\n");
2453 return 0;
2454 }
2455
2456 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2457 seq_printf(m, "IRQs disabled: %s\n",
2458 yesno(!intel_irqs_enabled(dev_priv)));
2459
2460 return 0;
2461}
2462
2463static const char *power_domain_str(enum intel_display_power_domain domain)
2464{
2465 switch (domain) {
2466 case POWER_DOMAIN_PIPE_A:
2467 return "PIPE_A";
2468 case POWER_DOMAIN_PIPE_B:
2469 return "PIPE_B";
2470 case POWER_DOMAIN_PIPE_C:
2471 return "PIPE_C";
2472 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2473 return "PIPE_A_PANEL_FITTER";
2474 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2475 return "PIPE_B_PANEL_FITTER";
2476 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2477 return "PIPE_C_PANEL_FITTER";
2478 case POWER_DOMAIN_TRANSCODER_A:
2479 return "TRANSCODER_A";
2480 case POWER_DOMAIN_TRANSCODER_B:
2481 return "TRANSCODER_B";
2482 case POWER_DOMAIN_TRANSCODER_C:
2483 return "TRANSCODER_C";
2484 case POWER_DOMAIN_TRANSCODER_EDP:
2485 return "TRANSCODER_EDP";
2486 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2487 return "PORT_DDI_A_2_LANES";
2488 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2489 return "PORT_DDI_A_4_LANES";
2490 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2491 return "PORT_DDI_B_2_LANES";
2492 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2493 return "PORT_DDI_B_4_LANES";
2494 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2495 return "PORT_DDI_C_2_LANES";
2496 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2497 return "PORT_DDI_C_4_LANES";
2498 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2499 return "PORT_DDI_D_2_LANES";
2500 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2501 return "PORT_DDI_D_4_LANES";
2502 case POWER_DOMAIN_PORT_DSI:
2503 return "PORT_DSI";
2504 case POWER_DOMAIN_PORT_CRT:
2505 return "PORT_CRT";
2506 case POWER_DOMAIN_PORT_OTHER:
2507 return "PORT_OTHER";
2508 case POWER_DOMAIN_VGA:
2509 return "VGA";
2510 case POWER_DOMAIN_AUDIO:
2511 return "AUDIO";
2512 case POWER_DOMAIN_PLLS:
2513 return "PLLS";
2514 case POWER_DOMAIN_AUX_A:
2515 return "AUX_A";
2516 case POWER_DOMAIN_AUX_B:
2517 return "AUX_B";
2518 case POWER_DOMAIN_AUX_C:
2519 return "AUX_C";
2520 case POWER_DOMAIN_AUX_D:
2521 return "AUX_D";
2522 case POWER_DOMAIN_INIT:
2523 return "INIT";
2524 default:
2525 MISSING_CASE(domain);
2526 return "?";
2527 }
2528}
2529
2530static int i915_power_domain_info(struct seq_file *m, void *unused)
2531{
2532 struct drm_info_node *node = m->private;
2533 struct drm_device *dev = node->minor->dev;
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2536 int i;
2537
2538 mutex_lock(&power_domains->lock);
2539
2540 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2541 for (i = 0; i < power_domains->power_well_count; i++) {
2542 struct i915_power_well *power_well;
2543 enum intel_display_power_domain power_domain;
2544
2545 power_well = &power_domains->power_wells[i];
2546 seq_printf(m, "%-25s %d\n", power_well->name,
2547 power_well->count);
2548
2549 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2550 power_domain++) {
2551 if (!(BIT(power_domain) & power_well->domains))
2552 continue;
2553
2554 seq_printf(m, " %-23s %d\n",
2555 power_domain_str(power_domain),
2556 power_domains->domain_use_count[power_domain]);
2557 }
2558 }
2559
2560 mutex_unlock(&power_domains->lock);
2561
2562 return 0;
2563}
2564
2565static void intel_seq_print_mode(struct seq_file *m, int tabs,
2566 struct drm_display_mode *mode)
2567{
2568 int i;
2569
2570 for (i = 0; i < tabs; i++)
2571 seq_putc(m, '\t');
2572
2573 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2574 mode->base.id, mode->name,
2575 mode->vrefresh, mode->clock,
2576 mode->hdisplay, mode->hsync_start,
2577 mode->hsync_end, mode->htotal,
2578 mode->vdisplay, mode->vsync_start,
2579 mode->vsync_end, mode->vtotal,
2580 mode->type, mode->flags);
2581}
2582
2583static void intel_encoder_info(struct seq_file *m,
2584 struct intel_crtc *intel_crtc,
2585 struct intel_encoder *intel_encoder)
2586{
2587 struct drm_info_node *node = m->private;
2588 struct drm_device *dev = node->minor->dev;
2589 struct drm_crtc *crtc = &intel_crtc->base;
2590 struct intel_connector *intel_connector;
2591 struct drm_encoder *encoder;
2592
2593 encoder = &intel_encoder->base;
2594 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2595 encoder->base.id, encoder->name);
2596 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2597 struct drm_connector *connector = &intel_connector->base;
2598 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2599 connector->base.id,
2600 connector->name,
2601 drm_get_connector_status_name(connector->status));
2602 if (connector->status == connector_status_connected) {
2603 struct drm_display_mode *mode = &crtc->mode;
2604 seq_printf(m, ", mode:\n");
2605 intel_seq_print_mode(m, 2, mode);
2606 } else {
2607 seq_putc(m, '\n');
2608 }
2609 }
2610}
2611
2612static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2613{
2614 struct drm_info_node *node = m->private;
2615 struct drm_device *dev = node->minor->dev;
2616 struct drm_crtc *crtc = &intel_crtc->base;
2617 struct intel_encoder *intel_encoder;
2618
2619 if (crtc->primary->fb)
2620 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2621 crtc->primary->fb->base.id, crtc->x, crtc->y,
2622 crtc->primary->fb->width, crtc->primary->fb->height);
2623 else
2624 seq_puts(m, "\tprimary plane disabled\n");
2625 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2626 intel_encoder_info(m, intel_crtc, intel_encoder);
2627}
2628
2629static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2630{
2631 struct drm_display_mode *mode = panel->fixed_mode;
2632
2633 seq_printf(m, "\tfixed mode:\n");
2634 intel_seq_print_mode(m, 2, mode);
2635}
2636
2637static void intel_dp_info(struct seq_file *m,
2638 struct intel_connector *intel_connector)
2639{
2640 struct intel_encoder *intel_encoder = intel_connector->encoder;
2641 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2642
2643 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2644 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2645 "no");
2646 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2647 intel_panel_info(m, &intel_connector->panel);
2648}
2649
2650static void intel_hdmi_info(struct seq_file *m,
2651 struct intel_connector *intel_connector)
2652{
2653 struct intel_encoder *intel_encoder = intel_connector->encoder;
2654 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2655
2656 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2657 "no");
2658}
2659
2660static void intel_lvds_info(struct seq_file *m,
2661 struct intel_connector *intel_connector)
2662{
2663 intel_panel_info(m, &intel_connector->panel);
2664}
2665
2666static void intel_connector_info(struct seq_file *m,
2667 struct drm_connector *connector)
2668{
2669 struct intel_connector *intel_connector = to_intel_connector(connector);
2670 struct intel_encoder *intel_encoder = intel_connector->encoder;
2671 struct drm_display_mode *mode;
2672
2673 seq_printf(m, "connector %d: type %s, status: %s\n",
2674 connector->base.id, connector->name,
2675 drm_get_connector_status_name(connector->status));
2676 if (connector->status == connector_status_connected) {
2677 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2678 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2679 connector->display_info.width_mm,
2680 connector->display_info.height_mm);
2681 seq_printf(m, "\tsubpixel order: %s\n",
2682 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2683 seq_printf(m, "\tCEA rev: %d\n",
2684 connector->display_info.cea_rev);
2685 }
2686 if (intel_encoder) {
2687 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2688 intel_encoder->type == INTEL_OUTPUT_EDP)
2689 intel_dp_info(m, intel_connector);
2690 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2691 intel_hdmi_info(m, intel_connector);
2692 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2693 intel_lvds_info(m, intel_connector);
2694 }
2695
2696 seq_printf(m, "\tmodes:\n");
2697 list_for_each_entry(mode, &connector->modes, head)
2698 intel_seq_print_mode(m, 2, mode);
2699}
2700
2701static bool cursor_active(struct drm_device *dev, int pipe)
2702{
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 u32 state;
2705
2706 if (IS_845G(dev) || IS_I865G(dev))
2707 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2708 else
2709 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2710
2711 return state;
2712}
2713
2714static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2715{
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 u32 pos;
2718
2719 pos = I915_READ(CURPOS(pipe));
2720
2721 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2722 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2723 *x = -*x;
2724
2725 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2726 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2727 *y = -*y;
2728
2729 return cursor_active(dev, pipe);
2730}
2731
2732static int i915_display_info(struct seq_file *m, void *unused)
2733{
2734 struct drm_info_node *node = m->private;
2735 struct drm_device *dev = node->minor->dev;
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 struct intel_crtc *crtc;
2738 struct drm_connector *connector;
2739
2740 intel_runtime_pm_get(dev_priv);
2741 drm_modeset_lock_all(dev);
2742 seq_printf(m, "CRTC info\n");
2743 seq_printf(m, "---------\n");
2744 for_each_intel_crtc(dev, crtc) {
2745 bool active;
2746 int x, y;
2747
2748 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2749 crtc->base.base.id, pipe_name(crtc->pipe),
2750 yesno(crtc->active), crtc->config->pipe_src_w,
2751 crtc->config->pipe_src_h);
2752 if (crtc->active) {
2753 intel_crtc_info(m, crtc);
2754
2755 active = cursor_position(dev, crtc->pipe, &x, &y);
2756 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2757 yesno(crtc->cursor_base),
2758 x, y, crtc->base.cursor->state->crtc_w,
2759 crtc->base.cursor->state->crtc_h,
2760 crtc->cursor_addr, yesno(active));
2761 }
2762
2763 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2764 yesno(!crtc->cpu_fifo_underrun_disabled),
2765 yesno(!crtc->pch_fifo_underrun_disabled));
2766 }
2767
2768 seq_printf(m, "\n");
2769 seq_printf(m, "Connector info\n");
2770 seq_printf(m, "--------------\n");
2771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2772 intel_connector_info(m, connector);
2773 }
2774 drm_modeset_unlock_all(dev);
2775 intel_runtime_pm_put(dev_priv);
2776
2777 return 0;
2778}
2779
2780static int i915_semaphore_status(struct seq_file *m, void *unused)
2781{
2782 struct drm_info_node *node = (struct drm_info_node *) m->private;
2783 struct drm_device *dev = node->minor->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_engine_cs *ring;
2786 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2787 int i, j, ret;
2788
2789 if (!i915_semaphore_is_enabled(dev)) {
2790 seq_puts(m, "Semaphores are disabled\n");
2791 return 0;
2792 }
2793
2794 ret = mutex_lock_interruptible(&dev->struct_mutex);
2795 if (ret)
2796 return ret;
2797 intel_runtime_pm_get(dev_priv);
2798
2799 if (IS_BROADWELL(dev)) {
2800 struct page *page;
2801 uint64_t *seqno;
2802
2803 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2804
2805 seqno = (uint64_t *)kmap_atomic(page);
2806 for_each_ring(ring, dev_priv, i) {
2807 uint64_t offset;
2808
2809 seq_printf(m, "%s\n", ring->name);
2810
2811 seq_puts(m, " Last signal:");
2812 for (j = 0; j < num_rings; j++) {
2813 offset = i * I915_NUM_RINGS + j;
2814 seq_printf(m, "0x%08llx (0x%02llx) ",
2815 seqno[offset], offset * 8);
2816 }
2817 seq_putc(m, '\n');
2818
2819 seq_puts(m, " Last wait: ");
2820 for (j = 0; j < num_rings; j++) {
2821 offset = i + (j * I915_NUM_RINGS);
2822 seq_printf(m, "0x%08llx (0x%02llx) ",
2823 seqno[offset], offset * 8);
2824 }
2825 seq_putc(m, '\n');
2826
2827 }
2828 kunmap_atomic(seqno);
2829 } else {
2830 seq_puts(m, " Last signal:");
2831 for_each_ring(ring, dev_priv, i)
2832 for (j = 0; j < num_rings; j++)
2833 seq_printf(m, "0x%08x\n",
2834 I915_READ(ring->semaphore.mbox.signal[j]));
2835 seq_putc(m, '\n');
2836 }
2837
2838 seq_puts(m, "\nSync seqno:\n");
2839 for_each_ring(ring, dev_priv, i) {
2840 for (j = 0; j < num_rings; j++) {
2841 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2842 }
2843 seq_putc(m, '\n');
2844 }
2845 seq_putc(m, '\n');
2846
2847 intel_runtime_pm_put(dev_priv);
2848 mutex_unlock(&dev->struct_mutex);
2849 return 0;
2850}
2851
2852static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2853{
2854 struct drm_info_node *node = (struct drm_info_node *) m->private;
2855 struct drm_device *dev = node->minor->dev;
2856 struct drm_i915_private *dev_priv = dev->dev_private;
2857 int i;
2858
2859 drm_modeset_lock_all(dev);
2860 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2861 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2862
2863 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2864 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2865 pll->config.crtc_mask, pll->active, yesno(pll->on));
2866 seq_printf(m, " tracked hardware state:\n");
2867 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2868 seq_printf(m, " dpll_md: 0x%08x\n",
2869 pll->config.hw_state.dpll_md);
2870 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2871 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2872 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2873 }
2874 drm_modeset_unlock_all(dev);
2875
2876 return 0;
2877}
2878
2879static int i915_wa_registers(struct seq_file *m, void *unused)
2880{
2881 int i;
2882 int ret;
2883 struct drm_info_node *node = (struct drm_info_node *) m->private;
2884 struct drm_device *dev = node->minor->dev;
2885 struct drm_i915_private *dev_priv = dev->dev_private;
2886
2887 ret = mutex_lock_interruptible(&dev->struct_mutex);
2888 if (ret)
2889 return ret;
2890
2891 intel_runtime_pm_get(dev_priv);
2892
2893 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2894 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2895 u32 addr, mask, value, read;
2896 bool ok;
2897
2898 addr = dev_priv->workarounds.reg[i].addr;
2899 mask = dev_priv->workarounds.reg[i].mask;
2900 value = dev_priv->workarounds.reg[i].value;
2901 read = I915_READ(addr);
2902 ok = (value & mask) == (read & mask);
2903 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2904 addr, value, mask, read, ok ? "OK" : "FAIL");
2905 }
2906
2907 intel_runtime_pm_put(dev_priv);
2908 mutex_unlock(&dev->struct_mutex);
2909
2910 return 0;
2911}
2912
2913static int i915_ddb_info(struct seq_file *m, void *unused)
2914{
2915 struct drm_info_node *node = m->private;
2916 struct drm_device *dev = node->minor->dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 struct skl_ddb_allocation *ddb;
2919 struct skl_ddb_entry *entry;
2920 enum pipe pipe;
2921 int plane;
2922
2923 if (INTEL_INFO(dev)->gen < 9)
2924 return 0;
2925
2926 drm_modeset_lock_all(dev);
2927
2928 ddb = &dev_priv->wm.skl_hw.ddb;
2929
2930 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2931
2932 for_each_pipe(dev_priv, pipe) {
2933 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2934
2935 for_each_plane(dev_priv, pipe, plane) {
2936 entry = &ddb->plane[pipe][plane];
2937 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2938 entry->start, entry->end,
2939 skl_ddb_entry_size(entry));
2940 }
2941
2942 entry = &ddb->cursor[pipe];
2943 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2944 entry->end, skl_ddb_entry_size(entry));
2945 }
2946
2947 drm_modeset_unlock_all(dev);
2948
2949 return 0;
2950}
2951
2952static void drrs_status_per_crtc(struct seq_file *m,
2953 struct drm_device *dev, struct intel_crtc *intel_crtc)
2954{
2955 struct intel_encoder *intel_encoder;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 struct i915_drrs *drrs = &dev_priv->drrs;
2958 int vrefresh = 0;
2959
2960 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2961 /* Encoder connected on this CRTC */
2962 switch (intel_encoder->type) {
2963 case INTEL_OUTPUT_EDP:
2964 seq_puts(m, "eDP:\n");
2965 break;
2966 case INTEL_OUTPUT_DSI:
2967 seq_puts(m, "DSI:\n");
2968 break;
2969 case INTEL_OUTPUT_HDMI:
2970 seq_puts(m, "HDMI:\n");
2971 break;
2972 case INTEL_OUTPUT_DISPLAYPORT:
2973 seq_puts(m, "DP:\n");
2974 break;
2975 default:
2976 seq_printf(m, "Other encoder (id=%d).\n",
2977 intel_encoder->type);
2978 return;
2979 }
2980 }
2981
2982 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2983 seq_puts(m, "\tVBT: DRRS_type: Static");
2984 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2985 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2986 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2987 seq_puts(m, "\tVBT: DRRS_type: None");
2988 else
2989 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
2990
2991 seq_puts(m, "\n\n");
2992
2993 if (intel_crtc->config->has_drrs) {
2994 struct intel_panel *panel;
2995
2996 mutex_lock(&drrs->mutex);
2997 /* DRRS Supported */
2998 seq_puts(m, "\tDRRS Supported: Yes\n");
2999
3000 /* disable_drrs() will make drrs->dp NULL */
3001 if (!drrs->dp) {
3002 seq_puts(m, "Idleness DRRS: Disabled");
3003 mutex_unlock(&drrs->mutex);
3004 return;
3005 }
3006
3007 panel = &drrs->dp->attached_connector->panel;
3008 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3009 drrs->busy_frontbuffer_bits);
3010
3011 seq_puts(m, "\n\t\t");
3012 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3013 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3014 vrefresh = panel->fixed_mode->vrefresh;
3015 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3016 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3017 vrefresh = panel->downclock_mode->vrefresh;
3018 } else {
3019 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3020 drrs->refresh_rate_type);
3021 mutex_unlock(&drrs->mutex);
3022 return;
3023 }
3024 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3025
3026 seq_puts(m, "\n\t\t");
3027 mutex_unlock(&drrs->mutex);
3028 } else {
3029 /* DRRS not supported. Print the VBT parameter*/
3030 seq_puts(m, "\tDRRS Supported : No");
3031 }
3032 seq_puts(m, "\n");
3033}
3034
3035static int i915_drrs_status(struct seq_file *m, void *unused)
3036{
3037 struct drm_info_node *node = m->private;
3038 struct drm_device *dev = node->minor->dev;
3039 struct intel_crtc *intel_crtc;
3040 int active_crtc_cnt = 0;
3041
3042 for_each_intel_crtc(dev, intel_crtc) {
3043 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3044
3045 if (intel_crtc->active) {
3046 active_crtc_cnt++;
3047 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3048
3049 drrs_status_per_crtc(m, dev, intel_crtc);
3050 }
3051
3052 drm_modeset_unlock(&intel_crtc->base.mutex);
3053 }
3054
3055 if (!active_crtc_cnt)
3056 seq_puts(m, "No active crtc found\n");
3057
3058 return 0;
3059}
3060
3061struct pipe_crc_info {
3062 const char *name;
3063 struct drm_device *dev;
3064 enum pipe pipe;
3065};
3066
3067static int i915_dp_mst_info(struct seq_file *m, void *unused)
3068{
3069 struct drm_info_node *node = (struct drm_info_node *) m->private;
3070 struct drm_device *dev = node->minor->dev;
3071 struct drm_encoder *encoder;
3072 struct intel_encoder *intel_encoder;
3073 struct intel_digital_port *intel_dig_port;
3074 drm_modeset_lock_all(dev);
3075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3076 intel_encoder = to_intel_encoder(encoder);
3077 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3078 continue;
3079 intel_dig_port = enc_to_dig_port(encoder);
3080 if (!intel_dig_port->dp.can_mst)
3081 continue;
3082
3083 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3084 }
3085 drm_modeset_unlock_all(dev);
3086 return 0;
3087}
3088
3089static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3090{
3091 struct pipe_crc_info *info = inode->i_private;
3092 struct drm_i915_private *dev_priv = info->dev->dev_private;
3093 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3094
3095 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3096 return -ENODEV;
3097
3098 spin_lock_irq(&pipe_crc->lock);
3099
3100 if (pipe_crc->opened) {
3101 spin_unlock_irq(&pipe_crc->lock);
3102 return -EBUSY; /* already open */
3103 }
3104
3105 pipe_crc->opened = true;
3106 filep->private_data = inode->i_private;
3107
3108 spin_unlock_irq(&pipe_crc->lock);
3109
3110 return 0;
3111}
3112
3113static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3114{
3115 struct pipe_crc_info *info = inode->i_private;
3116 struct drm_i915_private *dev_priv = info->dev->dev_private;
3117 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3118
3119 spin_lock_irq(&pipe_crc->lock);
3120 pipe_crc->opened = false;
3121 spin_unlock_irq(&pipe_crc->lock);
3122
3123 return 0;
3124}
3125
3126/* (6 fields, 8 chars each, space separated (5) + '\n') */
3127#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3128/* account for \'0' */
3129#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3130
3131static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3132{
3133 assert_spin_locked(&pipe_crc->lock);
3134 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3135 INTEL_PIPE_CRC_ENTRIES_NR);
3136}
3137
3138static ssize_t
3139i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3140 loff_t *pos)
3141{
3142 struct pipe_crc_info *info = filep->private_data;
3143 struct drm_device *dev = info->dev;
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3146 char buf[PIPE_CRC_BUFFER_LEN];
3147 int n_entries;
3148 ssize_t bytes_read;
3149
3150 /*
3151 * Don't allow user space to provide buffers not big enough to hold
3152 * a line of data.
3153 */
3154 if (count < PIPE_CRC_LINE_LEN)
3155 return -EINVAL;
3156
3157 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3158 return 0;
3159
3160 /* nothing to read */
3161 spin_lock_irq(&pipe_crc->lock);
3162 while (pipe_crc_data_count(pipe_crc) == 0) {
3163 int ret;
3164
3165 if (filep->f_flags & O_NONBLOCK) {
3166 spin_unlock_irq(&pipe_crc->lock);
3167 return -EAGAIN;
3168 }
3169
3170 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3171 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3172 if (ret) {
3173 spin_unlock_irq(&pipe_crc->lock);
3174 return ret;
3175 }
3176 }
3177
3178 /* We now have one or more entries to read */
3179 n_entries = count / PIPE_CRC_LINE_LEN;
3180
3181 bytes_read = 0;
3182 while (n_entries > 0) {
3183 struct intel_pipe_crc_entry *entry =
3184 &pipe_crc->entries[pipe_crc->tail];
3185 int ret;
3186
3187 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3188 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3189 break;
3190
3191 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3192 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3193
3194 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3195 "%8u %8x %8x %8x %8x %8x\n",
3196 entry->frame, entry->crc[0],
3197 entry->crc[1], entry->crc[2],
3198 entry->crc[3], entry->crc[4]);
3199
3200 spin_unlock_irq(&pipe_crc->lock);
3201
3202 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3203 if (ret == PIPE_CRC_LINE_LEN)
3204 return -EFAULT;
3205
3206 user_buf += PIPE_CRC_LINE_LEN;
3207 n_entries--;
3208
3209 spin_lock_irq(&pipe_crc->lock);
3210 }
3211
3212 spin_unlock_irq(&pipe_crc->lock);
3213
3214 return bytes_read;
3215}
3216
3217static const struct file_operations i915_pipe_crc_fops = {
3218 .owner = THIS_MODULE,
3219 .open = i915_pipe_crc_open,
3220 .read = i915_pipe_crc_read,
3221 .release = i915_pipe_crc_release,
3222};
3223
3224static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3225 {
3226 .name = "i915_pipe_A_crc",
3227 .pipe = PIPE_A,
3228 },
3229 {
3230 .name = "i915_pipe_B_crc",
3231 .pipe = PIPE_B,
3232 },
3233 {
3234 .name = "i915_pipe_C_crc",
3235 .pipe = PIPE_C,
3236 },
3237};
3238
3239static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3240 enum pipe pipe)
3241{
3242 struct drm_device *dev = minor->dev;
3243 struct dentry *ent;
3244 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3245
3246 info->dev = dev;
3247 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3248 &i915_pipe_crc_fops);
3249 if (!ent)
3250 return -ENOMEM;
3251
3252 return drm_add_fake_info_node(minor, ent, info);
3253}
3254
3255static const char * const pipe_crc_sources[] = {
3256 "none",
3257 "plane1",
3258 "plane2",
3259 "pf",
3260 "pipe",
3261 "TV",
3262 "DP-B",
3263 "DP-C",
3264 "DP-D",
3265 "auto",
3266};
3267
3268static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3269{
3270 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3271 return pipe_crc_sources[source];
3272}
3273
3274static int display_crc_ctl_show(struct seq_file *m, void *data)
3275{
3276 struct drm_device *dev = m->private;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 int i;
3279
3280 for (i = 0; i < I915_MAX_PIPES; i++)
3281 seq_printf(m, "%c %s\n", pipe_name(i),
3282 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3283
3284 return 0;
3285}
3286
3287static int display_crc_ctl_open(struct inode *inode, struct file *file)
3288{
3289 struct drm_device *dev = inode->i_private;
3290
3291 return single_open(file, display_crc_ctl_show, dev);
3292}
3293
3294static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3295 uint32_t *val)
3296{
3297 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3298 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3299
3300 switch (*source) {
3301 case INTEL_PIPE_CRC_SOURCE_PIPE:
3302 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3303 break;
3304 case INTEL_PIPE_CRC_SOURCE_NONE:
3305 *val = 0;
3306 break;
3307 default:
3308 return -EINVAL;
3309 }
3310
3311 return 0;
3312}
3313
3314static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3315 enum intel_pipe_crc_source *source)
3316{
3317 struct intel_encoder *encoder;
3318 struct intel_crtc *crtc;
3319 struct intel_digital_port *dig_port;
3320 int ret = 0;
3321
3322 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3323
3324 drm_modeset_lock_all(dev);
3325 for_each_intel_encoder(dev, encoder) {
3326 if (!encoder->base.crtc)
3327 continue;
3328
3329 crtc = to_intel_crtc(encoder->base.crtc);
3330
3331 if (crtc->pipe != pipe)
3332 continue;
3333
3334 switch (encoder->type) {
3335 case INTEL_OUTPUT_TVOUT:
3336 *source = INTEL_PIPE_CRC_SOURCE_TV;
3337 break;
3338 case INTEL_OUTPUT_DISPLAYPORT:
3339 case INTEL_OUTPUT_EDP:
3340 dig_port = enc_to_dig_port(&encoder->base);
3341 switch (dig_port->port) {
3342 case PORT_B:
3343 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3344 break;
3345 case PORT_C:
3346 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3347 break;
3348 case PORT_D:
3349 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3350 break;
3351 default:
3352 WARN(1, "nonexisting DP port %c\n",
3353 port_name(dig_port->port));
3354 break;
3355 }
3356 break;
3357 default:
3358 break;
3359 }
3360 }
3361 drm_modeset_unlock_all(dev);
3362
3363 return ret;
3364}
3365
3366static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3367 enum pipe pipe,
3368 enum intel_pipe_crc_source *source,
3369 uint32_t *val)
3370{
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3372 bool need_stable_symbols = false;
3373
3374 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3375 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3376 if (ret)
3377 return ret;
3378 }
3379
3380 switch (*source) {
3381 case INTEL_PIPE_CRC_SOURCE_PIPE:
3382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3383 break;
3384 case INTEL_PIPE_CRC_SOURCE_DP_B:
3385 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3386 need_stable_symbols = true;
3387 break;
3388 case INTEL_PIPE_CRC_SOURCE_DP_C:
3389 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3390 need_stable_symbols = true;
3391 break;
3392 case INTEL_PIPE_CRC_SOURCE_DP_D:
3393 if (!IS_CHERRYVIEW(dev))
3394 return -EINVAL;
3395 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3396 need_stable_symbols = true;
3397 break;
3398 case INTEL_PIPE_CRC_SOURCE_NONE:
3399 *val = 0;
3400 break;
3401 default:
3402 return -EINVAL;
3403 }
3404
3405 /*
3406 * When the pipe CRC tap point is after the transcoders we need
3407 * to tweak symbol-level features to produce a deterministic series of
3408 * symbols for a given frame. We need to reset those features only once
3409 * a frame (instead of every nth symbol):
3410 * - DC-balance: used to ensure a better clock recovery from the data
3411 * link (SDVO)
3412 * - DisplayPort scrambling: used for EMI reduction
3413 */
3414 if (need_stable_symbols) {
3415 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3416
3417 tmp |= DC_BALANCE_RESET_VLV;
3418 switch (pipe) {
3419 case PIPE_A:
3420 tmp |= PIPE_A_SCRAMBLE_RESET;
3421 break;
3422 case PIPE_B:
3423 tmp |= PIPE_B_SCRAMBLE_RESET;
3424 break;
3425 case PIPE_C:
3426 tmp |= PIPE_C_SCRAMBLE_RESET;
3427 break;
3428 default:
3429 return -EINVAL;
3430 }
3431 I915_WRITE(PORT_DFT2_G4X, tmp);
3432 }
3433
3434 return 0;
3435}
3436
3437static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3438 enum pipe pipe,
3439 enum intel_pipe_crc_source *source,
3440 uint32_t *val)
3441{
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 bool need_stable_symbols = false;
3444
3445 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3446 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3447 if (ret)
3448 return ret;
3449 }
3450
3451 switch (*source) {
3452 case INTEL_PIPE_CRC_SOURCE_PIPE:
3453 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3454 break;
3455 case INTEL_PIPE_CRC_SOURCE_TV:
3456 if (!SUPPORTS_TV(dev))
3457 return -EINVAL;
3458 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3459 break;
3460 case INTEL_PIPE_CRC_SOURCE_DP_B:
3461 if (!IS_G4X(dev))
3462 return -EINVAL;
3463 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3464 need_stable_symbols = true;
3465 break;
3466 case INTEL_PIPE_CRC_SOURCE_DP_C:
3467 if (!IS_G4X(dev))
3468 return -EINVAL;
3469 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3470 need_stable_symbols = true;
3471 break;
3472 case INTEL_PIPE_CRC_SOURCE_DP_D:
3473 if (!IS_G4X(dev))
3474 return -EINVAL;
3475 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3476 need_stable_symbols = true;
3477 break;
3478 case INTEL_PIPE_CRC_SOURCE_NONE:
3479 *val = 0;
3480 break;
3481 default:
3482 return -EINVAL;
3483 }
3484
3485 /*
3486 * When the pipe CRC tap point is after the transcoders we need
3487 * to tweak symbol-level features to produce a deterministic series of
3488 * symbols for a given frame. We need to reset those features only once
3489 * a frame (instead of every nth symbol):
3490 * - DC-balance: used to ensure a better clock recovery from the data
3491 * link (SDVO)
3492 * - DisplayPort scrambling: used for EMI reduction
3493 */
3494 if (need_stable_symbols) {
3495 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3496
3497 WARN_ON(!IS_G4X(dev));
3498
3499 I915_WRITE(PORT_DFT_I9XX,
3500 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3501
3502 if (pipe == PIPE_A)
3503 tmp |= PIPE_A_SCRAMBLE_RESET;
3504 else
3505 tmp |= PIPE_B_SCRAMBLE_RESET;
3506
3507 I915_WRITE(PORT_DFT2_G4X, tmp);
3508 }
3509
3510 return 0;
3511}
3512
3513static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3514 enum pipe pipe)
3515{
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3518
3519 switch (pipe) {
3520 case PIPE_A:
3521 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3522 break;
3523 case PIPE_B:
3524 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3525 break;
3526 case PIPE_C:
3527 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3528 break;
3529 default:
3530 return;
3531 }
3532 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3533 tmp &= ~DC_BALANCE_RESET_VLV;
3534 I915_WRITE(PORT_DFT2_G4X, tmp);
3535
3536}
3537
3538static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3539 enum pipe pipe)
3540{
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3543
3544 if (pipe == PIPE_A)
3545 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3546 else
3547 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3548 I915_WRITE(PORT_DFT2_G4X, tmp);
3549
3550 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3551 I915_WRITE(PORT_DFT_I9XX,
3552 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3553 }
3554}
3555
3556static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3557 uint32_t *val)
3558{
3559 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3560 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3561
3562 switch (*source) {
3563 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3564 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3565 break;
3566 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3567 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3568 break;
3569 case INTEL_PIPE_CRC_SOURCE_PIPE:
3570 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3571 break;
3572 case INTEL_PIPE_CRC_SOURCE_NONE:
3573 *val = 0;
3574 break;
3575 default:
3576 return -EINVAL;
3577 }
3578
3579 return 0;
3580}
3581
3582static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3583{
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 struct intel_crtc *crtc =
3586 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3587
3588 drm_modeset_lock_all(dev);
3589 /*
3590 * If we use the eDP transcoder we need to make sure that we don't
3591 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3592 * relevant on hsw with pipe A when using the always-on power well
3593 * routing.
3594 */
3595 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3596 !crtc->config->pch_pfit.enabled) {
3597 crtc->config->pch_pfit.force_thru = true;
3598
3599 intel_display_power_get(dev_priv,
3600 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3601
3602 dev_priv->display.crtc_disable(&crtc->base);
3603 dev_priv->display.crtc_enable(&crtc->base);
3604 }
3605 drm_modeset_unlock_all(dev);
3606}
3607
3608static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3609{
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *crtc =
3612 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3613
3614 drm_modeset_lock_all(dev);
3615 /*
3616 * If we use the eDP transcoder we need to make sure that we don't
3617 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3618 * relevant on hsw with pipe A when using the always-on power well
3619 * routing.
3620 */
3621 if (crtc->config->pch_pfit.force_thru) {
3622 crtc->config->pch_pfit.force_thru = false;
3623
3624 dev_priv->display.crtc_disable(&crtc->base);
3625 dev_priv->display.crtc_enable(&crtc->base);
3626
3627 intel_display_power_put(dev_priv,
3628 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3629 }
3630 drm_modeset_unlock_all(dev);
3631}
3632
3633static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3634 enum pipe pipe,
3635 enum intel_pipe_crc_source *source,
3636 uint32_t *val)
3637{
3638 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3639 *source = INTEL_PIPE_CRC_SOURCE_PF;
3640
3641 switch (*source) {
3642 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3643 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3644 break;
3645 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3646 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3647 break;
3648 case INTEL_PIPE_CRC_SOURCE_PF:
3649 if (IS_HASWELL(dev) && pipe == PIPE_A)
3650 hsw_trans_edp_pipe_A_crc_wa(dev);
3651
3652 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3653 break;
3654 case INTEL_PIPE_CRC_SOURCE_NONE:
3655 *val = 0;
3656 break;
3657 default:
3658 return -EINVAL;
3659 }
3660
3661 return 0;
3662}
3663
3664static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3665 enum intel_pipe_crc_source source)
3666{
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3669 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3670 pipe));
3671 u32 val = 0; /* shut up gcc */
3672 int ret;
3673
3674 if (pipe_crc->source == source)
3675 return 0;
3676
3677 /* forbid changing the source without going back to 'none' */
3678 if (pipe_crc->source && source)
3679 return -EINVAL;
3680
3681 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3682 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3683 return -EIO;
3684 }
3685
3686 if (IS_GEN2(dev))
3687 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3688 else if (INTEL_INFO(dev)->gen < 5)
3689 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3690 else if (IS_VALLEYVIEW(dev))
3691 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3692 else if (IS_GEN5(dev) || IS_GEN6(dev))
3693 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3694 else
3695 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3696
3697 if (ret != 0)
3698 return ret;
3699
3700 /* none -> real source transition */
3701 if (source) {
3702 struct intel_pipe_crc_entry *entries;
3703
3704 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3705 pipe_name(pipe), pipe_crc_source_name(source));
3706
3707 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3708 sizeof(pipe_crc->entries[0]),
3709 GFP_KERNEL);
3710 if (!entries)
3711 return -ENOMEM;
3712
3713 /*
3714 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3715 * enabled and disabled dynamically based on package C states,
3716 * user space can't make reliable use of the CRCs, so let's just
3717 * completely disable it.
3718 */
3719 hsw_disable_ips(crtc);
3720
3721 spin_lock_irq(&pipe_crc->lock);
3722 kfree(pipe_crc->entries);
3723 pipe_crc->entries = entries;
3724 pipe_crc->head = 0;
3725 pipe_crc->tail = 0;
3726 spin_unlock_irq(&pipe_crc->lock);
3727 }
3728
3729 pipe_crc->source = source;
3730
3731 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3732 POSTING_READ(PIPE_CRC_CTL(pipe));
3733
3734 /* real source -> none transition */
3735 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3736 struct intel_pipe_crc_entry *entries;
3737 struct intel_crtc *crtc =
3738 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3739
3740 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3741 pipe_name(pipe));
3742
3743 drm_modeset_lock(&crtc->base.mutex, NULL);
3744 if (crtc->active)
3745 intel_wait_for_vblank(dev, pipe);
3746 drm_modeset_unlock(&crtc->base.mutex);
3747
3748 spin_lock_irq(&pipe_crc->lock);
3749 entries = pipe_crc->entries;
3750 pipe_crc->entries = NULL;
3751 pipe_crc->head = 0;
3752 pipe_crc->tail = 0;
3753 spin_unlock_irq(&pipe_crc->lock);
3754
3755 kfree(entries);
3756
3757 if (IS_G4X(dev))
3758 g4x_undo_pipe_scramble_reset(dev, pipe);
3759 else if (IS_VALLEYVIEW(dev))
3760 vlv_undo_pipe_scramble_reset(dev, pipe);
3761 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3762 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3763
3764 hsw_enable_ips(crtc);
3765 }
3766
3767 return 0;
3768}
3769
3770/*
3771 * Parse pipe CRC command strings:
3772 * command: wsp* object wsp+ name wsp+ source wsp*
3773 * object: 'pipe'
3774 * name: (A | B | C)
3775 * source: (none | plane1 | plane2 | pf)
3776 * wsp: (#0x20 | #0x9 | #0xA)+
3777 *
3778 * eg.:
3779 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3780 * "pipe A none" -> Stop CRC
3781 */
3782static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3783{
3784 int n_words = 0;
3785
3786 while (*buf) {
3787 char *end;
3788
3789 /* skip leading white space */
3790 buf = skip_spaces(buf);
3791 if (!*buf)
3792 break; /* end of buffer */
3793
3794 /* find end of word */
3795 for (end = buf; *end && !isspace(*end); end++)
3796 ;
3797
3798 if (n_words == max_words) {
3799 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3800 max_words);
3801 return -EINVAL; /* ran out of words[] before bytes */
3802 }
3803
3804 if (*end)
3805 *end++ = '\0';
3806 words[n_words++] = buf;
3807 buf = end;
3808 }
3809
3810 return n_words;
3811}
3812
3813enum intel_pipe_crc_object {
3814 PIPE_CRC_OBJECT_PIPE,
3815};
3816
3817static const char * const pipe_crc_objects[] = {
3818 "pipe",
3819};
3820
3821static int
3822display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3823{
3824 int i;
3825
3826 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3827 if (!strcmp(buf, pipe_crc_objects[i])) {
3828 *o = i;
3829 return 0;
3830 }
3831
3832 return -EINVAL;
3833}
3834
3835static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3836{
3837 const char name = buf[0];
3838
3839 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3840 return -EINVAL;
3841
3842 *pipe = name - 'A';
3843
3844 return 0;
3845}
3846
3847static int
3848display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3849{
3850 int i;
3851
3852 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3853 if (!strcmp(buf, pipe_crc_sources[i])) {
3854 *s = i;
3855 return 0;
3856 }
3857
3858 return -EINVAL;
3859}
3860
3861static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3862{
3863#define N_WORDS 3
3864 int n_words;
3865 char *words[N_WORDS];
3866 enum pipe pipe;
3867 enum intel_pipe_crc_object object;
3868 enum intel_pipe_crc_source source;
3869
3870 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3871 if (n_words != N_WORDS) {
3872 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3873 N_WORDS);
3874 return -EINVAL;
3875 }
3876
3877 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3878 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3879 return -EINVAL;
3880 }
3881
3882 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3883 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3884 return -EINVAL;
3885 }
3886
3887 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3888 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3889 return -EINVAL;
3890 }
3891
3892 return pipe_crc_set_source(dev, pipe, source);
3893}
3894
3895static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3896 size_t len, loff_t *offp)
3897{
3898 struct seq_file *m = file->private_data;
3899 struct drm_device *dev = m->private;
3900 char *tmpbuf;
3901 int ret;
3902
3903 if (len == 0)
3904 return 0;
3905
3906 if (len > PAGE_SIZE - 1) {
3907 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3908 PAGE_SIZE);
3909 return -E2BIG;
3910 }
3911
3912 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3913 if (!tmpbuf)
3914 return -ENOMEM;
3915
3916 if (copy_from_user(tmpbuf, ubuf, len)) {
3917 ret = -EFAULT;
3918 goto out;
3919 }
3920 tmpbuf[len] = '\0';
3921
3922 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3923
3924out:
3925 kfree(tmpbuf);
3926 if (ret < 0)
3927 return ret;
3928
3929 *offp += len;
3930 return len;
3931}
3932
3933static const struct file_operations i915_display_crc_ctl_fops = {
3934 .owner = THIS_MODULE,
3935 .open = display_crc_ctl_open,
3936 .read = seq_read,
3937 .llseek = seq_lseek,
3938 .release = single_release,
3939 .write = display_crc_ctl_write
3940};
3941
3942static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3943{
3944 struct drm_device *dev = m->private;
3945 int num_levels = ilk_wm_max_level(dev) + 1;
3946 int level;
3947
3948 drm_modeset_lock_all(dev);
3949
3950 for (level = 0; level < num_levels; level++) {
3951 unsigned int latency = wm[level];
3952
3953 /*
3954 * - WM1+ latency values in 0.5us units
3955 * - latencies are in us on gen9
3956 */
3957 if (INTEL_INFO(dev)->gen >= 9)
3958 latency *= 10;
3959 else if (level > 0)
3960 latency *= 5;
3961
3962 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3963 level, wm[level], latency / 10, latency % 10);
3964 }
3965
3966 drm_modeset_unlock_all(dev);
3967}
3968
3969static int pri_wm_latency_show(struct seq_file *m, void *data)
3970{
3971 struct drm_device *dev = m->private;
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973 const uint16_t *latencies;
3974
3975 if (INTEL_INFO(dev)->gen >= 9)
3976 latencies = dev_priv->wm.skl_latency;
3977 else
3978 latencies = to_i915(dev)->wm.pri_latency;
3979
3980 wm_latency_show(m, latencies);
3981
3982 return 0;
3983}
3984
3985static int spr_wm_latency_show(struct seq_file *m, void *data)
3986{
3987 struct drm_device *dev = m->private;
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 const uint16_t *latencies;
3990
3991 if (INTEL_INFO(dev)->gen >= 9)
3992 latencies = dev_priv->wm.skl_latency;
3993 else
3994 latencies = to_i915(dev)->wm.spr_latency;
3995
3996 wm_latency_show(m, latencies);
3997
3998 return 0;
3999}
4000
4001static int cur_wm_latency_show(struct seq_file *m, void *data)
4002{
4003 struct drm_device *dev = m->private;
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005 const uint16_t *latencies;
4006
4007 if (INTEL_INFO(dev)->gen >= 9)
4008 latencies = dev_priv->wm.skl_latency;
4009 else
4010 latencies = to_i915(dev)->wm.cur_latency;
4011
4012 wm_latency_show(m, latencies);
4013
4014 return 0;
4015}
4016
4017static int pri_wm_latency_open(struct inode *inode, struct file *file)
4018{
4019 struct drm_device *dev = inode->i_private;
4020
4021 if (HAS_GMCH_DISPLAY(dev))
4022 return -ENODEV;
4023
4024 return single_open(file, pri_wm_latency_show, dev);
4025}
4026
4027static int spr_wm_latency_open(struct inode *inode, struct file *file)
4028{
4029 struct drm_device *dev = inode->i_private;
4030
4031 if (HAS_GMCH_DISPLAY(dev))
4032 return -ENODEV;
4033
4034 return single_open(file, spr_wm_latency_show, dev);
4035}
4036
4037static int cur_wm_latency_open(struct inode *inode, struct file *file)
4038{
4039 struct drm_device *dev = inode->i_private;
4040
4041 if (HAS_GMCH_DISPLAY(dev))
4042 return -ENODEV;
4043
4044 return single_open(file, cur_wm_latency_show, dev);
4045}
4046
4047static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4048 size_t len, loff_t *offp, uint16_t wm[8])
4049{
4050 struct seq_file *m = file->private_data;
4051 struct drm_device *dev = m->private;
4052 uint16_t new[8] = { 0 };
4053 int num_levels = ilk_wm_max_level(dev) + 1;
4054 int level;
4055 int ret;
4056 char tmp[32];
4057
4058 if (len >= sizeof(tmp))
4059 return -EINVAL;
4060
4061 if (copy_from_user(tmp, ubuf, len))
4062 return -EFAULT;
4063
4064 tmp[len] = '\0';
4065
4066 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4067 &new[0], &new[1], &new[2], &new[3],
4068 &new[4], &new[5], &new[6], &new[7]);
4069 if (ret != num_levels)
4070 return -EINVAL;
4071
4072 drm_modeset_lock_all(dev);
4073
4074 for (level = 0; level < num_levels; level++)
4075 wm[level] = new[level];
4076
4077 drm_modeset_unlock_all(dev);
4078
4079 return len;
4080}
4081
4082
4083static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4084 size_t len, loff_t *offp)
4085{
4086 struct seq_file *m = file->private_data;
4087 struct drm_device *dev = m->private;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 uint16_t *latencies;
4090
4091 if (INTEL_INFO(dev)->gen >= 9)
4092 latencies = dev_priv->wm.skl_latency;
4093 else
4094 latencies = to_i915(dev)->wm.pri_latency;
4095
4096 return wm_latency_write(file, ubuf, len, offp, latencies);
4097}
4098
4099static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4100 size_t len, loff_t *offp)
4101{
4102 struct seq_file *m = file->private_data;
4103 struct drm_device *dev = m->private;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 uint16_t *latencies;
4106
4107 if (INTEL_INFO(dev)->gen >= 9)
4108 latencies = dev_priv->wm.skl_latency;
4109 else
4110 latencies = to_i915(dev)->wm.spr_latency;
4111
4112 return wm_latency_write(file, ubuf, len, offp, latencies);
4113}
4114
4115static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4116 size_t len, loff_t *offp)
4117{
4118 struct seq_file *m = file->private_data;
4119 struct drm_device *dev = m->private;
4120 struct drm_i915_private *dev_priv = dev->dev_private;
4121 uint16_t *latencies;
4122
4123 if (INTEL_INFO(dev)->gen >= 9)
4124 latencies = dev_priv->wm.skl_latency;
4125 else
4126 latencies = to_i915(dev)->wm.cur_latency;
4127
4128 return wm_latency_write(file, ubuf, len, offp, latencies);
4129}
4130
4131static const struct file_operations i915_pri_wm_latency_fops = {
4132 .owner = THIS_MODULE,
4133 .open = pri_wm_latency_open,
4134 .read = seq_read,
4135 .llseek = seq_lseek,
4136 .release = single_release,
4137 .write = pri_wm_latency_write
4138};
4139
4140static const struct file_operations i915_spr_wm_latency_fops = {
4141 .owner = THIS_MODULE,
4142 .open = spr_wm_latency_open,
4143 .read = seq_read,
4144 .llseek = seq_lseek,
4145 .release = single_release,
4146 .write = spr_wm_latency_write
4147};
4148
4149static const struct file_operations i915_cur_wm_latency_fops = {
4150 .owner = THIS_MODULE,
4151 .open = cur_wm_latency_open,
4152 .read = seq_read,
4153 .llseek = seq_lseek,
4154 .release = single_release,
4155 .write = cur_wm_latency_write
4156};
4157
4158static int
4159i915_wedged_get(void *data, u64 *val)
4160{
4161 struct drm_device *dev = data;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163
4164 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4165
4166 return 0;
4167}
4168
4169static int
4170i915_wedged_set(void *data, u64 val)
4171{
4172 struct drm_device *dev = data;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174
4175 /*
4176 * There is no safeguard against this debugfs entry colliding
4177 * with the hangcheck calling same i915_handle_error() in
4178 * parallel, causing an explosion. For now we assume that the
4179 * test harness is responsible enough not to inject gpu hangs
4180 * while it is writing to 'i915_wedged'
4181 */
4182
4183 if (i915_reset_in_progress(&dev_priv->gpu_error))
4184 return -EAGAIN;
4185
4186 intel_runtime_pm_get(dev_priv);
4187
4188 i915_handle_error(dev, val,
4189 "Manually setting wedged to %llu", val);
4190
4191 intel_runtime_pm_put(dev_priv);
4192
4193 return 0;
4194}
4195
4196DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4197 i915_wedged_get, i915_wedged_set,
4198 "%llu\n");
4199
4200static int
4201i915_ring_stop_get(void *data, u64 *val)
4202{
4203 struct drm_device *dev = data;
4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205
4206 *val = dev_priv->gpu_error.stop_rings;
4207
4208 return 0;
4209}
4210
4211static int
4212i915_ring_stop_set(void *data, u64 val)
4213{
4214 struct drm_device *dev = data;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 int ret;
4217
4218 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4219
4220 ret = mutex_lock_interruptible(&dev->struct_mutex);
4221 if (ret)
4222 return ret;
4223
4224 dev_priv->gpu_error.stop_rings = val;
4225 mutex_unlock(&dev->struct_mutex);
4226
4227 return 0;
4228}
4229
4230DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4231 i915_ring_stop_get, i915_ring_stop_set,
4232 "0x%08llx\n");
4233
4234static int
4235i915_ring_missed_irq_get(void *data, u64 *val)
4236{
4237 struct drm_device *dev = data;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239
4240 *val = dev_priv->gpu_error.missed_irq_rings;
4241 return 0;
4242}
4243
4244static int
4245i915_ring_missed_irq_set(void *data, u64 val)
4246{
4247 struct drm_device *dev = data;
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 int ret;
4250
4251 /* Lock against concurrent debugfs callers */
4252 ret = mutex_lock_interruptible(&dev->struct_mutex);
4253 if (ret)
4254 return ret;
4255 dev_priv->gpu_error.missed_irq_rings = val;
4256 mutex_unlock(&dev->struct_mutex);
4257
4258 return 0;
4259}
4260
4261DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4262 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4263 "0x%08llx\n");
4264
4265static int
4266i915_ring_test_irq_get(void *data, u64 *val)
4267{
4268 struct drm_device *dev = data;
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270
4271 *val = dev_priv->gpu_error.test_irq_rings;
4272
4273 return 0;
4274}
4275
4276static int
4277i915_ring_test_irq_set(void *data, u64 val)
4278{
4279 struct drm_device *dev = data;
4280 struct drm_i915_private *dev_priv = dev->dev_private;
4281 int ret;
4282
4283 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4284
4285 /* Lock against concurrent debugfs callers */
4286 ret = mutex_lock_interruptible(&dev->struct_mutex);
4287 if (ret)
4288 return ret;
4289
4290 dev_priv->gpu_error.test_irq_rings = val;
4291 mutex_unlock(&dev->struct_mutex);
4292
4293 return 0;
4294}
4295
4296DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4297 i915_ring_test_irq_get, i915_ring_test_irq_set,
4298 "0x%08llx\n");
4299
4300#define DROP_UNBOUND 0x1
4301#define DROP_BOUND 0x2
4302#define DROP_RETIRE 0x4
4303#define DROP_ACTIVE 0x8
4304#define DROP_ALL (DROP_UNBOUND | \
4305 DROP_BOUND | \
4306 DROP_RETIRE | \
4307 DROP_ACTIVE)
4308static int
4309i915_drop_caches_get(void *data, u64 *val)
4310{
4311 *val = DROP_ALL;
4312
4313 return 0;
4314}
4315
4316static int
4317i915_drop_caches_set(void *data, u64 val)
4318{
4319 struct drm_device *dev = data;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 int ret;
4322
4323 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4324
4325 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4326 * on ioctls on -EAGAIN. */
4327 ret = mutex_lock_interruptible(&dev->struct_mutex);
4328 if (ret)
4329 return ret;
4330
4331 if (val & DROP_ACTIVE) {
4332 ret = i915_gpu_idle(dev);
4333 if (ret)
4334 goto unlock;
4335 }
4336
4337 if (val & (DROP_RETIRE | DROP_ACTIVE))
4338 i915_gem_retire_requests(dev);
4339
4340 if (val & DROP_BOUND)
4341 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4342
4343 if (val & DROP_UNBOUND)
4344 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4345
4346unlock:
4347 mutex_unlock(&dev->struct_mutex);
4348
4349 return ret;
4350}
4351
4352DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4353 i915_drop_caches_get, i915_drop_caches_set,
4354 "0x%08llx\n");
4355
4356static int
4357i915_max_freq_get(void *data, u64 *val)
4358{
4359 struct drm_device *dev = data;
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 int ret;
4362
4363 if (INTEL_INFO(dev)->gen < 6)
4364 return -ENODEV;
4365
4366 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4367
4368 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4369 if (ret)
4370 return ret;
4371
4372 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4373 mutex_unlock(&dev_priv->rps.hw_lock);
4374
4375 return 0;
4376}
4377
4378static int
4379i915_max_freq_set(void *data, u64 val)
4380{
4381 struct drm_device *dev = data;
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 u32 hw_max, hw_min;
4384 int ret;
4385
4386 if (INTEL_INFO(dev)->gen < 6)
4387 return -ENODEV;
4388
4389 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4390
4391 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4392
4393 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4394 if (ret)
4395 return ret;
4396
4397 /*
4398 * Turbo will still be enabled, but won't go above the set value.
4399 */
4400 val = intel_freq_opcode(dev_priv, val);
4401
4402 hw_max = dev_priv->rps.max_freq;
4403 hw_min = dev_priv->rps.min_freq;
4404
4405 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4406 mutex_unlock(&dev_priv->rps.hw_lock);
4407 return -EINVAL;
4408 }
4409
4410 dev_priv->rps.max_freq_softlimit = val;
4411
4412 intel_set_rps(dev, val);
4413
4414 mutex_unlock(&dev_priv->rps.hw_lock);
4415
4416 return 0;
4417}
4418
4419DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4420 i915_max_freq_get, i915_max_freq_set,
4421 "%llu\n");
4422
4423static int
4424i915_min_freq_get(void *data, u64 *val)
4425{
4426 struct drm_device *dev = data;
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4428 int ret;
4429
4430 if (INTEL_INFO(dev)->gen < 6)
4431 return -ENODEV;
4432
4433 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4434
4435 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4436 if (ret)
4437 return ret;
4438
4439 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4440 mutex_unlock(&dev_priv->rps.hw_lock);
4441
4442 return 0;
4443}
4444
4445static int
4446i915_min_freq_set(void *data, u64 val)
4447{
4448 struct drm_device *dev = data;
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450 u32 hw_max, hw_min;
4451 int ret;
4452
4453 if (INTEL_INFO(dev)->gen < 6)
4454 return -ENODEV;
4455
4456 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4457
4458 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4459
4460 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4461 if (ret)
4462 return ret;
4463
4464 /*
4465 * Turbo will still be enabled, but won't go below the set value.
4466 */
4467 val = intel_freq_opcode(dev_priv, val);
4468
4469 hw_max = dev_priv->rps.max_freq;
4470 hw_min = dev_priv->rps.min_freq;
4471
4472 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4473 mutex_unlock(&dev_priv->rps.hw_lock);
4474 return -EINVAL;
4475 }
4476
4477 dev_priv->rps.min_freq_softlimit = val;
4478
4479 intel_set_rps(dev, val);
4480
4481 mutex_unlock(&dev_priv->rps.hw_lock);
4482
4483 return 0;
4484}
4485
4486DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4487 i915_min_freq_get, i915_min_freq_set,
4488 "%llu\n");
4489
4490static int
4491i915_cache_sharing_get(void *data, u64 *val)
4492{
4493 struct drm_device *dev = data;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 u32 snpcr;
4496 int ret;
4497
4498 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4499 return -ENODEV;
4500
4501 ret = mutex_lock_interruptible(&dev->struct_mutex);
4502 if (ret)
4503 return ret;
4504 intel_runtime_pm_get(dev_priv);
4505
4506 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4507
4508 intel_runtime_pm_put(dev_priv);
4509 mutex_unlock(&dev_priv->dev->struct_mutex);
4510
4511 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4512
4513 return 0;
4514}
4515
4516static int
4517i915_cache_sharing_set(void *data, u64 val)
4518{
4519 struct drm_device *dev = data;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 u32 snpcr;
4522
4523 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4524 return -ENODEV;
4525
4526 if (val > 3)
4527 return -EINVAL;
4528
4529 intel_runtime_pm_get(dev_priv);
4530 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4531
4532 /* Update the cache sharing policy here as well */
4533 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4534 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4535 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4536 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4537
4538 intel_runtime_pm_put(dev_priv);
4539 return 0;
4540}
4541
4542DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4543 i915_cache_sharing_get, i915_cache_sharing_set,
4544 "%llu\n");
4545
4546static int i915_sseu_status(struct seq_file *m, void *unused)
4547{
4548 struct drm_info_node *node = (struct drm_info_node *) m->private;
4549 struct drm_device *dev = node->minor->dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
4552
4553 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4554 return -ENODEV;
4555
4556 seq_puts(m, "SSEU Device Info\n");
4557 seq_printf(m, " Available Slice Total: %u\n",
4558 INTEL_INFO(dev)->slice_total);
4559 seq_printf(m, " Available Subslice Total: %u\n",
4560 INTEL_INFO(dev)->subslice_total);
4561 seq_printf(m, " Available Subslice Per Slice: %u\n",
4562 INTEL_INFO(dev)->subslice_per_slice);
4563 seq_printf(m, " Available EU Total: %u\n",
4564 INTEL_INFO(dev)->eu_total);
4565 seq_printf(m, " Available EU Per Subslice: %u\n",
4566 INTEL_INFO(dev)->eu_per_subslice);
4567 seq_printf(m, " Has Slice Power Gating: %s\n",
4568 yesno(INTEL_INFO(dev)->has_slice_pg));
4569 seq_printf(m, " Has Subslice Power Gating: %s\n",
4570 yesno(INTEL_INFO(dev)->has_subslice_pg));
4571 seq_printf(m, " Has EU Power Gating: %s\n",
4572 yesno(INTEL_INFO(dev)->has_eu_pg));
4573
4574 seq_puts(m, "SSEU Device Status\n");
4575 if (IS_CHERRYVIEW(dev)) {
4576 const int ss_max = 2;
4577 int ss;
4578 u32 sig1[ss_max], sig2[ss_max];
4579
4580 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4581 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4582 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4583 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4584
4585 for (ss = 0; ss < ss_max; ss++) {
4586 unsigned int eu_cnt;
4587
4588 if (sig1[ss] & CHV_SS_PG_ENABLE)
4589 /* skip disabled subslice */
4590 continue;
4591
4592 s_tot = 1;
4593 ss_per++;
4594 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4595 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4596 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4597 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4598 eu_tot += eu_cnt;
4599 eu_per = max(eu_per, eu_cnt);
4600 }
4601 ss_tot = ss_per;
4602 } else if (IS_SKYLAKE(dev)) {
4603 const int s_max = 3, ss_max = 4;
4604 int s, ss;
4605 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4606
4607 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4608 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4609 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4610 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4611 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4612 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4613 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4614 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4615 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4616 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4617 GEN9_PGCTL_SSA_EU19_ACK |
4618 GEN9_PGCTL_SSA_EU210_ACK |
4619 GEN9_PGCTL_SSA_EU311_ACK;
4620 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4621 GEN9_PGCTL_SSB_EU19_ACK |
4622 GEN9_PGCTL_SSB_EU210_ACK |
4623 GEN9_PGCTL_SSB_EU311_ACK;
4624
4625 for (s = 0; s < s_max; s++) {
4626 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4627 /* skip disabled slice */
4628 continue;
4629
4630 s_tot++;
4631 ss_per = INTEL_INFO(dev)->subslice_per_slice;
4632 ss_tot += ss_per;
4633 for (ss = 0; ss < ss_max; ss++) {
4634 unsigned int eu_cnt;
4635
4636 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4637 eu_mask[ss%2]);
4638 eu_tot += eu_cnt;
4639 eu_per = max(eu_per, eu_cnt);
4640 }
4641 }
4642 }
4643 seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
4644 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
4645 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
4646 seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
4647 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
4648
4649 return 0;
4650}
4651
4652static int i915_forcewake_open(struct inode *inode, struct file *file)
4653{
4654 struct drm_device *dev = inode->i_private;
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656
4657 if (INTEL_INFO(dev)->gen < 6)
4658 return 0;
4659
4660 intel_runtime_pm_get(dev_priv);
4661 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4662
4663 return 0;
4664}
4665
4666static int i915_forcewake_release(struct inode *inode, struct file *file)
4667{
4668 struct drm_device *dev = inode->i_private;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 if (INTEL_INFO(dev)->gen < 6)
4672 return 0;
4673
4674 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4675 intel_runtime_pm_put(dev_priv);
4676
4677 return 0;
4678}
4679
4680static const struct file_operations i915_forcewake_fops = {
4681 .owner = THIS_MODULE,
4682 .open = i915_forcewake_open,
4683 .release = i915_forcewake_release,
4684};
4685
4686static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4687{
4688 struct drm_device *dev = minor->dev;
4689 struct dentry *ent;
4690
4691 ent = debugfs_create_file("i915_forcewake_user",
4692 S_IRUSR,
4693 root, dev,
4694 &i915_forcewake_fops);
4695 if (!ent)
4696 return -ENOMEM;
4697
4698 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4699}
4700
4701static int i915_debugfs_create(struct dentry *root,
4702 struct drm_minor *minor,
4703 const char *name,
4704 const struct file_operations *fops)
4705{
4706 struct drm_device *dev = minor->dev;
4707 struct dentry *ent;
4708
4709 ent = debugfs_create_file(name,
4710 S_IRUGO | S_IWUSR,
4711 root, dev,
4712 fops);
4713 if (!ent)
4714 return -ENOMEM;
4715
4716 return drm_add_fake_info_node(minor, ent, fops);
4717}
4718
4719static const struct drm_info_list i915_debugfs_list[] = {
4720 {"i915_capabilities", i915_capabilities, 0},
4721 {"i915_gem_objects", i915_gem_object_info, 0},
4722 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4723 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4724 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4725 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4726 {"i915_gem_stolen", i915_gem_stolen_list_info },
4727 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4728 {"i915_gem_request", i915_gem_request_info, 0},
4729 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4730 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4731 {"i915_gem_interrupt", i915_interrupt_info, 0},
4732 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4733 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4734 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4735 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4736 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4737 {"i915_frequency_info", i915_frequency_info, 0},
4738 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4739 {"i915_drpc_info", i915_drpc_info, 0},
4740 {"i915_emon_status", i915_emon_status, 0},
4741 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4742 {"i915_fbc_status", i915_fbc_status, 0},
4743 {"i915_ips_status", i915_ips_status, 0},
4744 {"i915_sr_status", i915_sr_status, 0},
4745 {"i915_opregion", i915_opregion, 0},
4746 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4747 {"i915_context_status", i915_context_status, 0},
4748 {"i915_dump_lrc", i915_dump_lrc, 0},
4749 {"i915_execlists", i915_execlists, 0},
4750 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4751 {"i915_swizzle_info", i915_swizzle_info, 0},
4752 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4753 {"i915_llc", i915_llc, 0},
4754 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4755 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4756 {"i915_energy_uJ", i915_energy_uJ, 0},
4757 {"i915_pc8_status", i915_pc8_status, 0},
4758 {"i915_power_domain_info", i915_power_domain_info, 0},
4759 {"i915_display_info", i915_display_info, 0},
4760 {"i915_semaphore_status", i915_semaphore_status, 0},
4761 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4762 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4763 {"i915_wa_registers", i915_wa_registers, 0},
4764 {"i915_ddb_info", i915_ddb_info, 0},
4765 {"i915_sseu_status", i915_sseu_status, 0},
4766 {"i915_drrs_status", i915_drrs_status, 0},
4767 {"i915_rps_boost_info", i915_rps_boost_info, 0},
4768};
4769#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4770
4771static const struct i915_debugfs_files {
4772 const char *name;
4773 const struct file_operations *fops;
4774} i915_debugfs_files[] = {
4775 {"i915_wedged", &i915_wedged_fops},
4776 {"i915_max_freq", &i915_max_freq_fops},
4777 {"i915_min_freq", &i915_min_freq_fops},
4778 {"i915_cache_sharing", &i915_cache_sharing_fops},
4779 {"i915_ring_stop", &i915_ring_stop_fops},
4780 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4781 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4782 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4783 {"i915_error_state", &i915_error_state_fops},
4784 {"i915_next_seqno", &i915_next_seqno_fops},
4785 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4786 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4787 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4788 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4789 {"i915_fbc_false_color", &i915_fbc_fc_fops},
4790};
4791
4792void intel_display_crc_init(struct drm_device *dev)
4793{
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 enum pipe pipe;
4796
4797 for_each_pipe(dev_priv, pipe) {
4798 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4799
4800 pipe_crc->opened = false;
4801 spin_lock_init(&pipe_crc->lock);
4802 init_waitqueue_head(&pipe_crc->wq);
4803 }
4804}
4805
4806int i915_debugfs_init(struct drm_minor *minor)
4807{
4808 int ret, i;
4809
4810 ret = i915_forcewake_create(minor->debugfs_root, minor);
4811 if (ret)
4812 return ret;
4813
4814 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4815 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4816 if (ret)
4817 return ret;
4818 }
4819
4820 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4821 ret = i915_debugfs_create(minor->debugfs_root, minor,
4822 i915_debugfs_files[i].name,
4823 i915_debugfs_files[i].fops);
4824 if (ret)
4825 return ret;
4826 }
4827
4828 return drm_debugfs_create_files(i915_debugfs_list,
4829 I915_DEBUGFS_ENTRIES,
4830 minor->debugfs_root, minor);
4831}
4832
4833void i915_debugfs_cleanup(struct drm_minor *minor)
4834{
4835 int i;
4836
4837 drm_debugfs_remove_files(i915_debugfs_list,
4838 I915_DEBUGFS_ENTRIES, minor);
4839
4840 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4841 1, minor);
4842
4843 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4844 struct drm_info_list *info_list =
4845 (struct drm_info_list *)&i915_pipe_crc_data[i];
4846
4847 drm_debugfs_remove_files(info_list, 1, minor);
4848 }
4849
4850 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4851 struct drm_info_list *info_list =
4852 (struct drm_info_list *) i915_debugfs_files[i].fops;
4853
4854 drm_debugfs_remove_files(info_list, 1, minor);
4855 }
4856}
4857
4858struct dpcd_block {
4859 /* DPCD dump start address. */
4860 unsigned int offset;
4861 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4862 unsigned int end;
4863 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4864 size_t size;
4865 /* Only valid for eDP. */
4866 bool edp;
4867};
4868
4869static const struct dpcd_block i915_dpcd_debug[] = {
4870 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4871 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4872 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4873 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4874 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4875 { .offset = DP_SET_POWER },
4876 { .offset = DP_EDP_DPCD_REV },
4877 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4878 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4879 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4880};
4881
4882static int i915_dpcd_show(struct seq_file *m, void *data)
4883{
4884 struct drm_connector *connector = m->private;
4885 struct intel_dp *intel_dp =
4886 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4887 uint8_t buf[16];
4888 ssize_t err;
4889 int i;
4890
4891 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4892 const struct dpcd_block *b = &i915_dpcd_debug[i];
4893 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4894
4895 if (b->edp &&
4896 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4897 continue;
4898
4899 /* low tech for now */
4900 if (WARN_ON(size > sizeof(buf)))
4901 continue;
4902
4903 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4904 if (err <= 0) {
4905 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4906 size, b->offset, err);
4907 continue;
4908 }
4909
4910 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4911 };
4912
4913 return 0;
4914}
4915
4916static int i915_dpcd_open(struct inode *inode, struct file *file)
4917{
4918 return single_open(file, i915_dpcd_show, inode->i_private);
4919}
4920
4921static const struct file_operations i915_dpcd_fops = {
4922 .owner = THIS_MODULE,
4923 .open = i915_dpcd_open,
4924 .read = seq_read,
4925 .llseek = seq_lseek,
4926 .release = single_release,
4927};
4928
4929/**
4930 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4931 * @connector: pointer to a registered drm_connector
4932 *
4933 * Cleanup will be done by drm_connector_unregister() through a call to
4934 * drm_debugfs_connector_remove().
4935 *
4936 * Returns 0 on success, negative error codes on error.
4937 */
4938int i915_debugfs_connector_add(struct drm_connector *connector)
4939{
4940 struct dentry *root = connector->debugfs_entry;
4941
4942 /* The connector must have been registered beforehands. */
4943 if (!root)
4944 return -ENODEV;
4945
4946 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4947 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4948 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
4949 &i915_dpcd_fops);
4950
4951 return 0;
4952}
Linux kernel - Deliverables
This page took 0.044545 seconds and 5 git commands to generate.