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drm/i915: export error state ref handling
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/debugfs.h>
31#include <linux/slab.h>
32#include <linux/export.h>
33#include <generated/utsrelease.h>
34#include <drm/drmP.h>
35#include "intel_drv.h"
36#include "intel_ringbuffer.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39
40#define DRM_I915_RING_DEBUG 1
41
42
43#if defined(CONFIG_DEBUG_FS)
44
45enum {
46 ACTIVE_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49};
50
51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
56static int i915_capabilities(struct seq_file *m, void *data)
57{
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
64#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65#define SEP_SEMICOLON ;
66 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
67#undef PRINT_FLAG
68#undef SEP_SEMICOLON
69
70 return 0;
71}
72
73static const char *get_pin_flag(struct drm_i915_gem_object *obj)
74{
75 if (obj->user_pin_count > 0)
76 return "P";
77 else if (obj->pin_count > 0)
78 return "p";
79 else
80 return " ";
81}
82
83static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
84{
85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
91}
92
93static const char *cache_level_str(int type)
94{
95 switch (type) {
96 case I915_CACHE_NONE: return " uncached";
97 case I915_CACHE_LLC: return " snooped (LLC)";
98 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
99 default: return "";
100 }
101}
102
103static void
104describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
105{
106 seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s",
107 &obj->base,
108 get_pin_flag(obj),
109 get_tiling_flag(obj),
110 obj->base.size / 1024,
111 obj->base.read_domains,
112 obj->base.write_domain,
113 obj->last_read_seqno,
114 obj->last_write_seqno,
115 obj->last_fenced_seqno,
116 cache_level_str(obj->cache_level),
117 obj->dirty ? " dirty" : "",
118 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
119 if (obj->base.name)
120 seq_printf(m, " (name: %d)", obj->base.name);
121 if (obj->pin_count)
122 seq_printf(m, " (pinned x %d)", obj->pin_count);
123 if (obj->fence_reg != I915_FENCE_REG_NONE)
124 seq_printf(m, " (fence: %d)", obj->fence_reg);
125 if (obj->gtt_space != NULL)
126 seq_printf(m, " (gtt offset: %08x, size: %08x)",
127 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
128 if (obj->stolen)
129 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
130 if (obj->pin_mappable || obj->fault_mappable) {
131 char s[3], *t = s;
132 if (obj->pin_mappable)
133 *t++ = 'p';
134 if (obj->fault_mappable)
135 *t++ = 'f';
136 *t = '\0';
137 seq_printf(m, " (%s mappable)", s);
138 }
139 if (obj->ring != NULL)
140 seq_printf(m, " (%s)", obj->ring->name);
141}
142
143static int i915_gem_object_list_info(struct seq_file *m, void *data)
144{
145 struct drm_info_node *node = (struct drm_info_node *) m->private;
146 uintptr_t list = (uintptr_t) node->info_ent->data;
147 struct list_head *head;
148 struct drm_device *dev = node->minor->dev;
149 drm_i915_private_t *dev_priv = dev->dev_private;
150 struct drm_i915_gem_object *obj;
151 size_t total_obj_size, total_gtt_size;
152 int count, ret;
153
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 if (ret)
156 return ret;
157
158 switch (list) {
159 case ACTIVE_LIST:
160 seq_puts(m, "Active:\n");
161 head = &dev_priv->mm.active_list;
162 break;
163 case INACTIVE_LIST:
164 seq_puts(m, "Inactive:\n");
165 head = &dev_priv->mm.inactive_list;
166 break;
167 default:
168 mutex_unlock(&dev->struct_mutex);
169 return -EINVAL;
170 }
171
172 total_obj_size = total_gtt_size = count = 0;
173 list_for_each_entry(obj, head, mm_list) {
174 seq_puts(m, " ");
175 describe_obj(m, obj);
176 seq_putc(m, '\n');
177 total_obj_size += obj->base.size;
178 total_gtt_size += obj->gtt_space->size;
179 count++;
180 }
181 mutex_unlock(&dev->struct_mutex);
182
183 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
184 count, total_obj_size, total_gtt_size);
185 return 0;
186}
187
188#define count_objects(list, member) do { \
189 list_for_each_entry(obj, list, member) { \
190 size += obj->gtt_space->size; \
191 ++count; \
192 if (obj->map_and_fenceable) { \
193 mappable_size += obj->gtt_space->size; \
194 ++mappable_count; \
195 } \
196 } \
197} while (0)
198
199struct file_stats {
200 int count;
201 size_t total, active, inactive, unbound;
202};
203
204static int per_file_stats(int id, void *ptr, void *data)
205{
206 struct drm_i915_gem_object *obj = ptr;
207 struct file_stats *stats = data;
208
209 stats->count++;
210 stats->total += obj->base.size;
211
212 if (obj->gtt_space) {
213 if (!list_empty(&obj->ring_list))
214 stats->active += obj->base.size;
215 else
216 stats->inactive += obj->base.size;
217 } else {
218 if (!list_empty(&obj->global_list))
219 stats->unbound += obj->base.size;
220 }
221
222 return 0;
223}
224
225static int i915_gem_object_info(struct seq_file *m, void *data)
226{
227 struct drm_info_node *node = (struct drm_info_node *) m->private;
228 struct drm_device *dev = node->minor->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 u32 count, mappable_count, purgeable_count;
231 size_t size, mappable_size, purgeable_size;
232 struct drm_i915_gem_object *obj;
233 struct drm_file *file;
234 int ret;
235
236 ret = mutex_lock_interruptible(&dev->struct_mutex);
237 if (ret)
238 return ret;
239
240 seq_printf(m, "%u objects, %zu bytes\n",
241 dev_priv->mm.object_count,
242 dev_priv->mm.object_memory);
243
244 size = count = mappable_size = mappable_count = 0;
245 count_objects(&dev_priv->mm.bound_list, global_list);
246 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
247 count, mappable_count, size, mappable_size);
248
249 size = count = mappable_size = mappable_count = 0;
250 count_objects(&dev_priv->mm.active_list, mm_list);
251 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
252 count, mappable_count, size, mappable_size);
253
254 size = count = mappable_size = mappable_count = 0;
255 count_objects(&dev_priv->mm.inactive_list, mm_list);
256 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
257 count, mappable_count, size, mappable_size);
258
259 size = count = purgeable_size = purgeable_count = 0;
260 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
261 size += obj->base.size, ++count;
262 if (obj->madv == I915_MADV_DONTNEED)
263 purgeable_size += obj->base.size, ++purgeable_count;
264 }
265 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
266
267 size = count = mappable_size = mappable_count = 0;
268 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
269 if (obj->fault_mappable) {
270 size += obj->gtt_space->size;
271 ++count;
272 }
273 if (obj->pin_mappable) {
274 mappable_size += obj->gtt_space->size;
275 ++mappable_count;
276 }
277 if (obj->madv == I915_MADV_DONTNEED) {
278 purgeable_size += obj->base.size;
279 ++purgeable_count;
280 }
281 }
282 seq_printf(m, "%u purgeable objects, %zu bytes\n",
283 purgeable_count, purgeable_size);
284 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
285 mappable_count, mappable_size);
286 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
287 count, size);
288
289 seq_printf(m, "%zu [%lu] gtt total\n",
290 dev_priv->gtt.total,
291 dev_priv->gtt.mappable_end - dev_priv->gtt.start);
292
293 seq_putc(m, '\n');
294 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
295 struct file_stats stats;
296
297 memset(&stats, 0, sizeof(stats));
298 idr_for_each(&file->object_idr, per_file_stats, &stats);
299 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
300 get_pid_task(file->pid, PIDTYPE_PID)->comm,
301 stats.count,
302 stats.total,
303 stats.active,
304 stats.inactive,
305 stats.unbound);
306 }
307
308 mutex_unlock(&dev->struct_mutex);
309
310 return 0;
311}
312
313static int i915_gem_gtt_info(struct seq_file *m, void *data)
314{
315 struct drm_info_node *node = (struct drm_info_node *) m->private;
316 struct drm_device *dev = node->minor->dev;
317 uintptr_t list = (uintptr_t) node->info_ent->data;
318 struct drm_i915_private *dev_priv = dev->dev_private;
319 struct drm_i915_gem_object *obj;
320 size_t total_obj_size, total_gtt_size;
321 int count, ret;
322
323 ret = mutex_lock_interruptible(&dev->struct_mutex);
324 if (ret)
325 return ret;
326
327 total_obj_size = total_gtt_size = count = 0;
328 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
329 if (list == PINNED_LIST && obj->pin_count == 0)
330 continue;
331
332 seq_puts(m, " ");
333 describe_obj(m, obj);
334 seq_putc(m, '\n');
335 total_obj_size += obj->base.size;
336 total_gtt_size += obj->gtt_space->size;
337 count++;
338 }
339
340 mutex_unlock(&dev->struct_mutex);
341
342 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
343 count, total_obj_size, total_gtt_size);
344
345 return 0;
346}
347
348static int i915_gem_pageflip_info(struct seq_file *m, void *data)
349{
350 struct drm_info_node *node = (struct drm_info_node *) m->private;
351 struct drm_device *dev = node->minor->dev;
352 unsigned long flags;
353 struct intel_crtc *crtc;
354
355 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
356 const char pipe = pipe_name(crtc->pipe);
357 const char plane = plane_name(crtc->plane);
358 struct intel_unpin_work *work;
359
360 spin_lock_irqsave(&dev->event_lock, flags);
361 work = crtc->unpin_work;
362 if (work == NULL) {
363 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
364 pipe, plane);
365 } else {
366 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
367 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
368 pipe, plane);
369 } else {
370 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
371 pipe, plane);
372 }
373 if (work->enable_stall_check)
374 seq_puts(m, "Stall check enabled, ");
375 else
376 seq_puts(m, "Stall check waiting for page flip ioctl, ");
377 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
378
379 if (work->old_fb_obj) {
380 struct drm_i915_gem_object *obj = work->old_fb_obj;
381 if (obj)
382 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
383 }
384 if (work->pending_flip_obj) {
385 struct drm_i915_gem_object *obj = work->pending_flip_obj;
386 if (obj)
387 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
388 }
389 }
390 spin_unlock_irqrestore(&dev->event_lock, flags);
391 }
392
393 return 0;
394}
395
396static int i915_gem_request_info(struct seq_file *m, void *data)
397{
398 struct drm_info_node *node = (struct drm_info_node *) m->private;
399 struct drm_device *dev = node->minor->dev;
400 drm_i915_private_t *dev_priv = dev->dev_private;
401 struct intel_ring_buffer *ring;
402 struct drm_i915_gem_request *gem_request;
403 int ret, count, i;
404
405 ret = mutex_lock_interruptible(&dev->struct_mutex);
406 if (ret)
407 return ret;
408
409 count = 0;
410 for_each_ring(ring, dev_priv, i) {
411 if (list_empty(&ring->request_list))
412 continue;
413
414 seq_printf(m, "%s requests:\n", ring->name);
415 list_for_each_entry(gem_request,
416 &ring->request_list,
417 list) {
418 seq_printf(m, " %d @ %d\n",
419 gem_request->seqno,
420 (int) (jiffies - gem_request->emitted_jiffies));
421 }
422 count++;
423 }
424 mutex_unlock(&dev->struct_mutex);
425
426 if (count == 0)
427 seq_puts(m, "No requests\n");
428
429 return 0;
430}
431
432static void i915_ring_seqno_info(struct seq_file *m,
433 struct intel_ring_buffer *ring)
434{
435 if (ring->get_seqno) {
436 seq_printf(m, "Current sequence (%s): %u\n",
437 ring->name, ring->get_seqno(ring, false));
438 }
439}
440
441static int i915_gem_seqno_info(struct seq_file *m, void *data)
442{
443 struct drm_info_node *node = (struct drm_info_node *) m->private;
444 struct drm_device *dev = node->minor->dev;
445 drm_i915_private_t *dev_priv = dev->dev_private;
446 struct intel_ring_buffer *ring;
447 int ret, i;
448
449 ret = mutex_lock_interruptible(&dev->struct_mutex);
450 if (ret)
451 return ret;
452
453 for_each_ring(ring, dev_priv, i)
454 i915_ring_seqno_info(m, ring);
455
456 mutex_unlock(&dev->struct_mutex);
457
458 return 0;
459}
460
461
462static int i915_interrupt_info(struct seq_file *m, void *data)
463{
464 struct drm_info_node *node = (struct drm_info_node *) m->private;
465 struct drm_device *dev = node->minor->dev;
466 drm_i915_private_t *dev_priv = dev->dev_private;
467 struct intel_ring_buffer *ring;
468 int ret, i, pipe;
469
470 ret = mutex_lock_interruptible(&dev->struct_mutex);
471 if (ret)
472 return ret;
473
474 if (IS_VALLEYVIEW(dev)) {
475 seq_printf(m, "Display IER:\t%08x\n",
476 I915_READ(VLV_IER));
477 seq_printf(m, "Display IIR:\t%08x\n",
478 I915_READ(VLV_IIR));
479 seq_printf(m, "Display IIR_RW:\t%08x\n",
480 I915_READ(VLV_IIR_RW));
481 seq_printf(m, "Display IMR:\t%08x\n",
482 I915_READ(VLV_IMR));
483 for_each_pipe(pipe)
484 seq_printf(m, "Pipe %c stat:\t%08x\n",
485 pipe_name(pipe),
486 I915_READ(PIPESTAT(pipe)));
487
488 seq_printf(m, "Master IER:\t%08x\n",
489 I915_READ(VLV_MASTER_IER));
490
491 seq_printf(m, "Render IER:\t%08x\n",
492 I915_READ(GTIER));
493 seq_printf(m, "Render IIR:\t%08x\n",
494 I915_READ(GTIIR));
495 seq_printf(m, "Render IMR:\t%08x\n",
496 I915_READ(GTIMR));
497
498 seq_printf(m, "PM IER:\t\t%08x\n",
499 I915_READ(GEN6_PMIER));
500 seq_printf(m, "PM IIR:\t\t%08x\n",
501 I915_READ(GEN6_PMIIR));
502 seq_printf(m, "PM IMR:\t\t%08x\n",
503 I915_READ(GEN6_PMIMR));
504
505 seq_printf(m, "Port hotplug:\t%08x\n",
506 I915_READ(PORT_HOTPLUG_EN));
507 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
508 I915_READ(VLV_DPFLIPSTAT));
509 seq_printf(m, "DPINVGTT:\t%08x\n",
510 I915_READ(DPINVGTT));
511
512 } else if (!HAS_PCH_SPLIT(dev)) {
513 seq_printf(m, "Interrupt enable: %08x\n",
514 I915_READ(IER));
515 seq_printf(m, "Interrupt identity: %08x\n",
516 I915_READ(IIR));
517 seq_printf(m, "Interrupt mask: %08x\n",
518 I915_READ(IMR));
519 for_each_pipe(pipe)
520 seq_printf(m, "Pipe %c stat: %08x\n",
521 pipe_name(pipe),
522 I915_READ(PIPESTAT(pipe)));
523 } else {
524 seq_printf(m, "North Display Interrupt enable: %08x\n",
525 I915_READ(DEIER));
526 seq_printf(m, "North Display Interrupt identity: %08x\n",
527 I915_READ(DEIIR));
528 seq_printf(m, "North Display Interrupt mask: %08x\n",
529 I915_READ(DEIMR));
530 seq_printf(m, "South Display Interrupt enable: %08x\n",
531 I915_READ(SDEIER));
532 seq_printf(m, "South Display Interrupt identity: %08x\n",
533 I915_READ(SDEIIR));
534 seq_printf(m, "South Display Interrupt mask: %08x\n",
535 I915_READ(SDEIMR));
536 seq_printf(m, "Graphics Interrupt enable: %08x\n",
537 I915_READ(GTIER));
538 seq_printf(m, "Graphics Interrupt identity: %08x\n",
539 I915_READ(GTIIR));
540 seq_printf(m, "Graphics Interrupt mask: %08x\n",
541 I915_READ(GTIMR));
542 }
543 seq_printf(m, "Interrupts received: %d\n",
544 atomic_read(&dev_priv->irq_received));
545 for_each_ring(ring, dev_priv, i) {
546 if (IS_GEN6(dev) || IS_GEN7(dev)) {
547 seq_printf(m,
548 "Graphics Interrupt mask (%s): %08x\n",
549 ring->name, I915_READ_IMR(ring));
550 }
551 i915_ring_seqno_info(m, ring);
552 }
553 mutex_unlock(&dev->struct_mutex);
554
555 return 0;
556}
557
558static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
559{
560 struct drm_info_node *node = (struct drm_info_node *) m->private;
561 struct drm_device *dev = node->minor->dev;
562 drm_i915_private_t *dev_priv = dev->dev_private;
563 int i, ret;
564
565 ret = mutex_lock_interruptible(&dev->struct_mutex);
566 if (ret)
567 return ret;
568
569 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
570 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
571 for (i = 0; i < dev_priv->num_fence_regs; i++) {
572 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
573
574 seq_printf(m, "Fence %d, pin count = %d, object = ",
575 i, dev_priv->fence_regs[i].pin_count);
576 if (obj == NULL)
577 seq_puts(m, "unused");
578 else
579 describe_obj(m, obj);
580 seq_putc(m, '\n');
581 }
582
583 mutex_unlock(&dev->struct_mutex);
584 return 0;
585}
586
587static int i915_hws_info(struct seq_file *m, void *data)
588{
589 struct drm_info_node *node = (struct drm_info_node *) m->private;
590 struct drm_device *dev = node->minor->dev;
591 drm_i915_private_t *dev_priv = dev->dev_private;
592 struct intel_ring_buffer *ring;
593 const u32 *hws;
594 int i;
595
596 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
597 hws = ring->status_page.page_addr;
598 if (hws == NULL)
599 return 0;
600
601 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
602 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
603 i * 4,
604 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
605 }
606 return 0;
607}
608
609static const char *ring_str(int ring)
610{
611 switch (ring) {
612 case RCS: return "render";
613 case VCS: return "bsd";
614 case BCS: return "blt";
615 case VECS: return "vebox";
616 default: return "";
617 }
618}
619
620static const char *pin_flag(int pinned)
621{
622 if (pinned > 0)
623 return " P";
624 else if (pinned < 0)
625 return " p";
626 else
627 return "";
628}
629
630static const char *tiling_flag(int tiling)
631{
632 switch (tiling) {
633 default:
634 case I915_TILING_NONE: return "";
635 case I915_TILING_X: return " X";
636 case I915_TILING_Y: return " Y";
637 }
638}
639
640static const char *dirty_flag(int dirty)
641{
642 return dirty ? " dirty" : "";
643}
644
645static const char *purgeable_flag(int purgeable)
646{
647 return purgeable ? " purgeable" : "";
648}
649
650static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
651{
652
653 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
654 e->err = -ENOSPC;
655 return false;
656 }
657
658 if (e->bytes == e->size - 1 || e->err)
659 return false;
660
661 return true;
662}
663
664static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
665 unsigned len)
666{
667 if (e->pos + len <= e->start) {
668 e->pos += len;
669 return false;
670 }
671
672 /* First vsnprintf needs to fit in its entirety for memmove */
673 if (len >= e->size) {
674 e->err = -EIO;
675 return false;
676 }
677
678 return true;
679}
680
681static void __i915_error_advance(struct drm_i915_error_state_buf *e,
682 unsigned len)
683{
684 /* If this is first printf in this window, adjust it so that
685 * start position matches start of the buffer
686 */
687
688 if (e->pos < e->start) {
689 const size_t off = e->start - e->pos;
690
691 /* Should not happen but be paranoid */
692 if (off > len || e->bytes) {
693 e->err = -EIO;
694 return;
695 }
696
697 memmove(e->buf, e->buf + off, len - off);
698 e->bytes = len - off;
699 e->pos = e->start;
700 return;
701 }
702
703 e->bytes += len;
704 e->pos += len;
705}
706
707static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
708 const char *f, va_list args)
709{
710 unsigned len;
711
712 if (!__i915_error_ok(e))
713 return;
714
715 /* Seek the first printf which is hits start position */
716 if (e->pos < e->start) {
717 len = vsnprintf(NULL, 0, f, args);
718 if (!__i915_error_seek(e, len))
719 return;
720 }
721
722 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
723 if (len >= e->size - e->bytes)
724 len = e->size - e->bytes - 1;
725
726 __i915_error_advance(e, len);
727}
728
729static void i915_error_puts(struct drm_i915_error_state_buf *e,
730 const char *str)
731{
732 unsigned len;
733
734 if (!__i915_error_ok(e))
735 return;
736
737 len = strlen(str);
738
739 /* Seek the first printf which is hits start position */
740 if (e->pos < e->start) {
741 if (!__i915_error_seek(e, len))
742 return;
743 }
744
745 if (len >= e->size - e->bytes)
746 len = e->size - e->bytes - 1;
747 memcpy(e->buf + e->bytes, str, len);
748
749 __i915_error_advance(e, len);
750}
751
752void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
753{
754 va_list args;
755
756 va_start(args, f);
757 i915_error_vprintf(e, f, args);
758 va_end(args);
759}
760
761#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
762#define err_puts(e, s) i915_error_puts(e, s)
763
764static void print_error_buffers(struct drm_i915_error_state_buf *m,
765 const char *name,
766 struct drm_i915_error_buffer *err,
767 int count)
768{
769 err_printf(m, "%s [%d]:\n", name, count);
770
771 while (count--) {
772 err_printf(m, " %08x %8u %02x %02x %x %x",
773 err->gtt_offset,
774 err->size,
775 err->read_domains,
776 err->write_domain,
777 err->rseqno, err->wseqno);
778 err_puts(m, pin_flag(err->pinned));
779 err_puts(m, tiling_flag(err->tiling));
780 err_puts(m, dirty_flag(err->dirty));
781 err_puts(m, purgeable_flag(err->purgeable));
782 err_puts(m, err->ring != -1 ? " " : "");
783 err_puts(m, ring_str(err->ring));
784 err_puts(m, cache_level_str(err->cache_level));
785
786 if (err->name)
787 err_printf(m, " (name: %d)", err->name);
788 if (err->fence_reg != I915_FENCE_REG_NONE)
789 err_printf(m, " (fence: %d)", err->fence_reg);
790
791 err_puts(m, "\n");
792 err++;
793 }
794}
795
796static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
797 struct drm_device *dev,
798 struct drm_i915_error_state *error,
799 unsigned ring)
800{
801 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
802 err_printf(m, "%s command stream:\n", ring_str(ring));
803 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
804 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
805 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
806 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
807 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
808 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
809 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
810 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
811 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
812
813 if (INTEL_INFO(dev)->gen >= 4)
814 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
815 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
816 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
817 if (INTEL_INFO(dev)->gen >= 6) {
818 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
819 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
820 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
821 error->semaphore_mboxes[ring][0],
822 error->semaphore_seqno[ring][0]);
823 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
824 error->semaphore_mboxes[ring][1],
825 error->semaphore_seqno[ring][1]);
826 }
827 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
828 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
829 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
830 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
831}
832
833int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
834 const struct i915_error_state_file_priv *error_priv)
835{
836 struct drm_device *dev = error_priv->dev;
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 struct drm_i915_error_state *error = error_priv->error;
839 struct intel_ring_buffer *ring;
840 int i, j, page, offset, elt;
841
842 if (!error) {
843 err_printf(m, "no error state collected\n");
844 goto out;
845 }
846
847 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
848 error->time.tv_usec);
849 err_printf(m, "Kernel: " UTS_RELEASE "\n");
850 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
851 err_printf(m, "EIR: 0x%08x\n", error->eir);
852 err_printf(m, "IER: 0x%08x\n", error->ier);
853 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
854 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
855 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
856 err_printf(m, "CCID: 0x%08x\n", error->ccid);
857
858 for (i = 0; i < dev_priv->num_fence_regs; i++)
859 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
860
861 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
862 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
863 error->extra_instdone[i]);
864
865 if (INTEL_INFO(dev)->gen >= 6) {
866 err_printf(m, "ERROR: 0x%08x\n", error->error);
867 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
868 }
869
870 if (INTEL_INFO(dev)->gen == 7)
871 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
872
873 for_each_ring(ring, dev_priv, i)
874 i915_ring_error_state(m, dev, error, i);
875
876 if (error->active_bo)
877 print_error_buffers(m, "Active",
878 error->active_bo,
879 error->active_bo_count);
880
881 if (error->pinned_bo)
882 print_error_buffers(m, "Pinned",
883 error->pinned_bo,
884 error->pinned_bo_count);
885
886 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
887 struct drm_i915_error_object *obj;
888
889 if ((obj = error->ring[i].batchbuffer)) {
890 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
891 dev_priv->ring[i].name,
892 obj->gtt_offset);
893 offset = 0;
894 for (page = 0; page < obj->page_count; page++) {
895 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
896 err_printf(m, "%08x : %08x\n", offset,
897 obj->pages[page][elt]);
898 offset += 4;
899 }
900 }
901 }
902
903 if (error->ring[i].num_requests) {
904 err_printf(m, "%s --- %d requests\n",
905 dev_priv->ring[i].name,
906 error->ring[i].num_requests);
907 for (j = 0; j < error->ring[i].num_requests; j++) {
908 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
909 error->ring[i].requests[j].seqno,
910 error->ring[i].requests[j].jiffies,
911 error->ring[i].requests[j].tail);
912 }
913 }
914
915 if ((obj = error->ring[i].ringbuffer)) {
916 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
917 dev_priv->ring[i].name,
918 obj->gtt_offset);
919 offset = 0;
920 for (page = 0; page < obj->page_count; page++) {
921 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
922 err_printf(m, "%08x : %08x\n",
923 offset,
924 obj->pages[page][elt]);
925 offset += 4;
926 }
927 }
928 }
929
930 obj = error->ring[i].ctx;
931 if (obj) {
932 err_printf(m, "%s --- HW Context = 0x%08x\n",
933 dev_priv->ring[i].name,
934 obj->gtt_offset);
935 offset = 0;
936 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
937 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
938 offset,
939 obj->pages[0][elt],
940 obj->pages[0][elt+1],
941 obj->pages[0][elt+2],
942 obj->pages[0][elt+3]);
943 offset += 16;
944 }
945 }
946 }
947
948 if (error->overlay)
949 intel_overlay_print_error_state(m, error->overlay);
950
951 if (error->display)
952 intel_display_print_error_state(m, dev, error->display);
953
954out:
955 if (m->bytes == 0 && m->err)
956 return m->err;
957
958 return 0;
959}
960
961static ssize_t
962i915_error_state_write(struct file *filp,
963 const char __user *ubuf,
964 size_t cnt,
965 loff_t *ppos)
966{
967 struct i915_error_state_file_priv *error_priv = filp->private_data;
968 struct drm_device *dev = error_priv->dev;
969 int ret;
970
971 DRM_DEBUG_DRIVER("Resetting error state\n");
972
973 ret = mutex_lock_interruptible(&dev->struct_mutex);
974 if (ret)
975 return ret;
976
977 i915_destroy_error_state(dev);
978 mutex_unlock(&dev->struct_mutex);
979
980 return cnt;
981}
982
983void i915_error_state_get(struct drm_device *dev,
984 struct i915_error_state_file_priv *error_priv)
985{
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 unsigned long flags;
988
989 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
990 error_priv->error = dev_priv->gpu_error.first_error;
991 if (error_priv->error)
992 kref_get(&error_priv->error->ref);
993 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
994
995}
996
997void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
998{
999 if (error_priv->error)
1000 kref_put(&error_priv->error->ref, i915_error_state_free);
1001}
1002
1003static int i915_error_state_open(struct inode *inode, struct file *file)
1004{
1005 struct drm_device *dev = inode->i_private;
1006 struct i915_error_state_file_priv *error_priv;
1007
1008 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1009 if (!error_priv)
1010 return -ENOMEM;
1011
1012 error_priv->dev = dev;
1013
1014 i915_error_state_get(dev, error_priv);
1015
1016 file->private_data = error_priv;
1017
1018 return 0;
1019}
1020
1021static int i915_error_state_release(struct inode *inode, struct file *file)
1022{
1023 struct i915_error_state_file_priv *error_priv = file->private_data;
1024
1025 i915_error_state_put(error_priv);
1026 kfree(error_priv);
1027
1028 return 0;
1029}
1030
1031static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1032 size_t count, loff_t *pos)
1033{
1034 struct i915_error_state_file_priv *error_priv = file->private_data;
1035 struct drm_i915_error_state_buf error_str;
1036 loff_t tmp_pos = 0;
1037 ssize_t ret_count = 0;
1038 int ret = 0;
1039
1040 memset(&error_str, 0, sizeof(error_str));
1041
1042 /* We need to have enough room to store any i915_error_state printf
1043 * so that we can move it to start position.
1044 */
1045 error_str.size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
1046 error_str.buf = kmalloc(error_str.size,
1047 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
1048
1049 if (error_str.buf == NULL) {
1050 error_str.size = PAGE_SIZE;
1051 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
1052 }
1053
1054 if (error_str.buf == NULL) {
1055 error_str.size = 128;
1056 error_str.buf = kmalloc(error_str.size, GFP_TEMPORARY);
1057 }
1058
1059 if (error_str.buf == NULL)
1060 return -ENOMEM;
1061
1062 error_str.start = *pos;
1063
1064 ret = i915_error_state_to_str(&error_str, error_priv);
1065 if (ret)
1066 goto out;
1067
1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069 error_str.buf,
1070 error_str.bytes);
1071
1072 if (ret_count < 0)
1073 ret = ret_count;
1074 else
1075 *pos = error_str.start + ret_count;
1076out:
1077 kfree(error_str.buf);
1078 return ret ?: ret_count;
1079}
1080
1081static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
1084 .read = i915_error_state_read,
1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1088};
1089
1090static int
1091i915_next_seqno_get(void *data, u64 *val)
1092{
1093 struct drm_device *dev = data;
1094 drm_i915_private_t *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
1100
1101 *val = dev_priv->next_seqno;
1102 mutex_unlock(&dev->struct_mutex);
1103
1104 return 0;
1105}
1106
1107static int
1108i915_next_seqno_set(void *data, u64 val)
1109{
1110 struct drm_device *dev = data;
1111 int ret;
1112
1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 if (ret)
1115 return ret;
1116
1117 ret = i915_gem_set_seqno(dev, val);
1118 mutex_unlock(&dev->struct_mutex);
1119
1120 return ret;
1121}
1122
1123DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
1125 "0x%llx\n");
1126
1127static int i915_rstdby_delays(struct seq_file *m, void *unused)
1128{
1129 struct drm_info_node *node = (struct drm_info_node *) m->private;
1130 struct drm_device *dev = node->minor->dev;
1131 drm_i915_private_t *dev_priv = dev->dev_private;
1132 u16 crstanddelay;
1133 int ret;
1134
1135 ret = mutex_lock_interruptible(&dev->struct_mutex);
1136 if (ret)
1137 return ret;
1138
1139 crstanddelay = I915_READ16(CRSTANDVID);
1140
1141 mutex_unlock(&dev->struct_mutex);
1142
1143 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1144
1145 return 0;
1146}
1147
1148static int i915_cur_delayinfo(struct seq_file *m, void *unused)
1149{
1150 struct drm_info_node *node = (struct drm_info_node *) m->private;
1151 struct drm_device *dev = node->minor->dev;
1152 drm_i915_private_t *dev_priv = dev->dev_private;
1153 int ret;
1154
1155 if (IS_GEN5(dev)) {
1156 u16 rgvswctl = I915_READ16(MEMSWCTL);
1157 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1158
1159 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1160 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1161 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1162 MEMSTAT_VID_SHIFT);
1163 seq_printf(m, "Current P-state: %d\n",
1164 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1165 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1166 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1167 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1168 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1169 u32 rpstat, cagf;
1170 u32 rpupei, rpcurup, rpprevup;
1171 u32 rpdownei, rpcurdown, rpprevdown;
1172 int max_freq;
1173
1174 /* RPSTAT1 is in the GT power well */
1175 ret = mutex_lock_interruptible(&dev->struct_mutex);
1176 if (ret)
1177 return ret;
1178
1179 gen6_gt_force_wake_get(dev_priv);
1180
1181 rpstat = I915_READ(GEN6_RPSTAT1);
1182 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1183 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1184 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1185 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1186 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1187 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1188 if (IS_HASWELL(dev))
1189 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1190 else
1191 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1192 cagf *= GT_FREQUENCY_MULTIPLIER;
1193
1194 gen6_gt_force_wake_put(dev_priv);
1195 mutex_unlock(&dev->struct_mutex);
1196
1197 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1198 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1199 seq_printf(m, "Render p-state ratio: %d\n",
1200 (gt_perf_status & 0xff00) >> 8);
1201 seq_printf(m, "Render p-state VID: %d\n",
1202 gt_perf_status & 0xff);
1203 seq_printf(m, "Render p-state limit: %d\n",
1204 rp_state_limits & 0xff);
1205 seq_printf(m, "CAGF: %dMHz\n", cagf);
1206 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1207 GEN6_CURICONT_MASK);
1208 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1209 GEN6_CURBSYTAVG_MASK);
1210 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1211 GEN6_CURBSYTAVG_MASK);
1212 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1213 GEN6_CURIAVG_MASK);
1214 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1215 GEN6_CURBSYTAVG_MASK);
1216 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1217 GEN6_CURBSYTAVG_MASK);
1218
1219 max_freq = (rp_state_cap & 0xff0000) >> 16;
1220 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1221 max_freq * GT_FREQUENCY_MULTIPLIER);
1222
1223 max_freq = (rp_state_cap & 0xff00) >> 8;
1224 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1225 max_freq * GT_FREQUENCY_MULTIPLIER);
1226
1227 max_freq = rp_state_cap & 0xff;
1228 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1229 max_freq * GT_FREQUENCY_MULTIPLIER);
1230
1231 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1232 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1233 } else if (IS_VALLEYVIEW(dev)) {
1234 u32 freq_sts, val;
1235
1236 mutex_lock(&dev_priv->rps.hw_lock);
1237 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1238 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1239 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1240
1241 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
1242 seq_printf(m, "max GPU freq: %d MHz\n",
1243 vlv_gpu_freq(dev_priv->mem_freq, val));
1244
1245 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
1246 seq_printf(m, "min GPU freq: %d MHz\n",
1247 vlv_gpu_freq(dev_priv->mem_freq, val));
1248
1249 seq_printf(m, "current GPU freq: %d MHz\n",
1250 vlv_gpu_freq(dev_priv->mem_freq,
1251 (freq_sts >> 8) & 0xff));
1252 mutex_unlock(&dev_priv->rps.hw_lock);
1253 } else {
1254 seq_puts(m, "no P-state info available\n");
1255 }
1256
1257 return 0;
1258}
1259
1260static int i915_delayfreq_table(struct seq_file *m, void *unused)
1261{
1262 struct drm_info_node *node = (struct drm_info_node *) m->private;
1263 struct drm_device *dev = node->minor->dev;
1264 drm_i915_private_t *dev_priv = dev->dev_private;
1265 u32 delayfreq;
1266 int ret, i;
1267
1268 ret = mutex_lock_interruptible(&dev->struct_mutex);
1269 if (ret)
1270 return ret;
1271
1272 for (i = 0; i < 16; i++) {
1273 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1274 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1275 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1276 }
1277
1278 mutex_unlock(&dev->struct_mutex);
1279
1280 return 0;
1281}
1282
1283static inline int MAP_TO_MV(int map)
1284{
1285 return 1250 - (map * 25);
1286}
1287
1288static int i915_inttoext_table(struct seq_file *m, void *unused)
1289{
1290 struct drm_info_node *node = (struct drm_info_node *) m->private;
1291 struct drm_device *dev = node->minor->dev;
1292 drm_i915_private_t *dev_priv = dev->dev_private;
1293 u32 inttoext;
1294 int ret, i;
1295
1296 ret = mutex_lock_interruptible(&dev->struct_mutex);
1297 if (ret)
1298 return ret;
1299
1300 for (i = 1; i <= 32; i++) {
1301 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1302 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1303 }
1304
1305 mutex_unlock(&dev->struct_mutex);
1306
1307 return 0;
1308}
1309
1310static int ironlake_drpc_info(struct seq_file *m)
1311{
1312 struct drm_info_node *node = (struct drm_info_node *) m->private;
1313 struct drm_device *dev = node->minor->dev;
1314 drm_i915_private_t *dev_priv = dev->dev_private;
1315 u32 rgvmodectl, rstdbyctl;
1316 u16 crstandvid;
1317 int ret;
1318
1319 ret = mutex_lock_interruptible(&dev->struct_mutex);
1320 if (ret)
1321 return ret;
1322
1323 rgvmodectl = I915_READ(MEMMODECTL);
1324 rstdbyctl = I915_READ(RSTDBYCTL);
1325 crstandvid = I915_READ16(CRSTANDVID);
1326
1327 mutex_unlock(&dev->struct_mutex);
1328
1329 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1330 "yes" : "no");
1331 seq_printf(m, "Boost freq: %d\n",
1332 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1333 MEMMODE_BOOST_FREQ_SHIFT);
1334 seq_printf(m, "HW control enabled: %s\n",
1335 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1336 seq_printf(m, "SW control enabled: %s\n",
1337 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1338 seq_printf(m, "Gated voltage change: %s\n",
1339 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1340 seq_printf(m, "Starting frequency: P%d\n",
1341 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1342 seq_printf(m, "Max P-state: P%d\n",
1343 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1344 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1345 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1346 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1347 seq_printf(m, "Render standby enabled: %s\n",
1348 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1349 seq_puts(m, "Current RS state: ");
1350 switch (rstdbyctl & RSX_STATUS_MASK) {
1351 case RSX_STATUS_ON:
1352 seq_puts(m, "on\n");
1353 break;
1354 case RSX_STATUS_RC1:
1355 seq_puts(m, "RC1\n");
1356 break;
1357 case RSX_STATUS_RC1E:
1358 seq_puts(m, "RC1E\n");
1359 break;
1360 case RSX_STATUS_RS1:
1361 seq_puts(m, "RS1\n");
1362 break;
1363 case RSX_STATUS_RS2:
1364 seq_puts(m, "RS2 (RC6)\n");
1365 break;
1366 case RSX_STATUS_RS3:
1367 seq_puts(m, "RC3 (RC6+)\n");
1368 break;
1369 default:
1370 seq_puts(m, "unknown\n");
1371 break;
1372 }
1373
1374 return 0;
1375}
1376
1377static int gen6_drpc_info(struct seq_file *m)
1378{
1379
1380 struct drm_info_node *node = (struct drm_info_node *) m->private;
1381 struct drm_device *dev = node->minor->dev;
1382 struct drm_i915_private *dev_priv = dev->dev_private;
1383 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1384 unsigned forcewake_count;
1385 int count = 0, ret;
1386
1387 ret = mutex_lock_interruptible(&dev->struct_mutex);
1388 if (ret)
1389 return ret;
1390
1391 spin_lock_irq(&dev_priv->gt_lock);
1392 forcewake_count = dev_priv->forcewake_count;
1393 spin_unlock_irq(&dev_priv->gt_lock);
1394
1395 if (forcewake_count) {
1396 seq_puts(m, "RC information inaccurate because somebody "
1397 "holds a forcewake reference \n");
1398 } else {
1399 /* NB: we cannot use forcewake, else we read the wrong values */
1400 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1401 udelay(10);
1402 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1403 }
1404
1405 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1406 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1407
1408 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1409 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1410 mutex_unlock(&dev->struct_mutex);
1411 mutex_lock(&dev_priv->rps.hw_lock);
1412 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1413 mutex_unlock(&dev_priv->rps.hw_lock);
1414
1415 seq_printf(m, "Video Turbo Mode: %s\n",
1416 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1417 seq_printf(m, "HW control enabled: %s\n",
1418 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1419 seq_printf(m, "SW control enabled: %s\n",
1420 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1421 GEN6_RP_MEDIA_SW_MODE));
1422 seq_printf(m, "RC1e Enabled: %s\n",
1423 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1424 seq_printf(m, "RC6 Enabled: %s\n",
1425 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1426 seq_printf(m, "Deep RC6 Enabled: %s\n",
1427 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1428 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1429 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1430 seq_puts(m, "Current RC state: ");
1431 switch (gt_core_status & GEN6_RCn_MASK) {
1432 case GEN6_RC0:
1433 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1434 seq_puts(m, "Core Power Down\n");
1435 else
1436 seq_puts(m, "on\n");
1437 break;
1438 case GEN6_RC3:
1439 seq_puts(m, "RC3\n");
1440 break;
1441 case GEN6_RC6:
1442 seq_puts(m, "RC6\n");
1443 break;
1444 case GEN6_RC7:
1445 seq_puts(m, "RC7\n");
1446 break;
1447 default:
1448 seq_puts(m, "Unknown\n");
1449 break;
1450 }
1451
1452 seq_printf(m, "Core Power Down: %s\n",
1453 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1454
1455 /* Not exactly sure what this is */
1456 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1457 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1458 seq_printf(m, "RC6 residency since boot: %u\n",
1459 I915_READ(GEN6_GT_GFX_RC6));
1460 seq_printf(m, "RC6+ residency since boot: %u\n",
1461 I915_READ(GEN6_GT_GFX_RC6p));
1462 seq_printf(m, "RC6++ residency since boot: %u\n",
1463 I915_READ(GEN6_GT_GFX_RC6pp));
1464
1465 seq_printf(m, "RC6 voltage: %dmV\n",
1466 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1467 seq_printf(m, "RC6+ voltage: %dmV\n",
1468 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1469 seq_printf(m, "RC6++ voltage: %dmV\n",
1470 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1471 return 0;
1472}
1473
1474static int i915_drpc_info(struct seq_file *m, void *unused)
1475{
1476 struct drm_info_node *node = (struct drm_info_node *) m->private;
1477 struct drm_device *dev = node->minor->dev;
1478
1479 if (IS_GEN6(dev) || IS_GEN7(dev))
1480 return gen6_drpc_info(m);
1481 else
1482 return ironlake_drpc_info(m);
1483}
1484
1485static int i915_fbc_status(struct seq_file *m, void *unused)
1486{
1487 struct drm_info_node *node = (struct drm_info_node *) m->private;
1488 struct drm_device *dev = node->minor->dev;
1489 drm_i915_private_t *dev_priv = dev->dev_private;
1490
1491 if (!I915_HAS_FBC(dev)) {
1492 seq_puts(m, "FBC unsupported on this chipset\n");
1493 return 0;
1494 }
1495
1496 if (intel_fbc_enabled(dev)) {
1497 seq_puts(m, "FBC enabled\n");
1498 } else {
1499 seq_puts(m, "FBC disabled: ");
1500 switch (dev_priv->fbc.no_fbc_reason) {
1501 case FBC_NO_OUTPUT:
1502 seq_puts(m, "no outputs");
1503 break;
1504 case FBC_STOLEN_TOO_SMALL:
1505 seq_puts(m, "not enough stolen memory");
1506 break;
1507 case FBC_UNSUPPORTED_MODE:
1508 seq_puts(m, "mode not supported");
1509 break;
1510 case FBC_MODE_TOO_LARGE:
1511 seq_puts(m, "mode too large");
1512 break;
1513 case FBC_BAD_PLANE:
1514 seq_puts(m, "FBC unsupported on plane");
1515 break;
1516 case FBC_NOT_TILED:
1517 seq_puts(m, "scanout buffer not tiled");
1518 break;
1519 case FBC_MULTIPLE_PIPES:
1520 seq_puts(m, "multiple pipes are enabled");
1521 break;
1522 case FBC_MODULE_PARAM:
1523 seq_puts(m, "disabled per module param (default off)");
1524 break;
1525 case FBC_CHIP_DEFAULT:
1526 seq_puts(m, "disabled per chip default");
1527 break;
1528 default:
1529 seq_puts(m, "unknown reason");
1530 }
1531 seq_putc(m, '\n');
1532 }
1533 return 0;
1534}
1535
1536static int i915_ips_status(struct seq_file *m, void *unused)
1537{
1538 struct drm_info_node *node = (struct drm_info_node *) m->private;
1539 struct drm_device *dev = node->minor->dev;
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541
1542 if (!HAS_IPS(dev)) {
1543 seq_puts(m, "not supported\n");
1544 return 0;
1545 }
1546
1547 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1548 seq_puts(m, "enabled\n");
1549 else
1550 seq_puts(m, "disabled\n");
1551
1552 return 0;
1553}
1554
1555static int i915_sr_status(struct seq_file *m, void *unused)
1556{
1557 struct drm_info_node *node = (struct drm_info_node *) m->private;
1558 struct drm_device *dev = node->minor->dev;
1559 drm_i915_private_t *dev_priv = dev->dev_private;
1560 bool sr_enabled = false;
1561
1562 if (HAS_PCH_SPLIT(dev))
1563 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1564 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1565 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1566 else if (IS_I915GM(dev))
1567 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1568 else if (IS_PINEVIEW(dev))
1569 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1570
1571 seq_printf(m, "self-refresh: %s\n",
1572 sr_enabled ? "enabled" : "disabled");
1573
1574 return 0;
1575}
1576
1577static int i915_emon_status(struct seq_file *m, void *unused)
1578{
1579 struct drm_info_node *node = (struct drm_info_node *) m->private;
1580 struct drm_device *dev = node->minor->dev;
1581 drm_i915_private_t *dev_priv = dev->dev_private;
1582 unsigned long temp, chipset, gfx;
1583 int ret;
1584
1585 if (!IS_GEN5(dev))
1586 return -ENODEV;
1587
1588 ret = mutex_lock_interruptible(&dev->struct_mutex);
1589 if (ret)
1590 return ret;
1591
1592 temp = i915_mch_val(dev_priv);
1593 chipset = i915_chipset_val(dev_priv);
1594 gfx = i915_gfx_val(dev_priv);
1595 mutex_unlock(&dev->struct_mutex);
1596
1597 seq_printf(m, "GMCH temp: %ld\n", temp);
1598 seq_printf(m, "Chipset power: %ld\n", chipset);
1599 seq_printf(m, "GFX power: %ld\n", gfx);
1600 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1601
1602 return 0;
1603}
1604
1605static int i915_ring_freq_table(struct seq_file *m, void *unused)
1606{
1607 struct drm_info_node *node = (struct drm_info_node *) m->private;
1608 struct drm_device *dev = node->minor->dev;
1609 drm_i915_private_t *dev_priv = dev->dev_private;
1610 int ret;
1611 int gpu_freq, ia_freq;
1612
1613 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1614 seq_puts(m, "unsupported on this chipset\n");
1615 return 0;
1616 }
1617
1618 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1619 if (ret)
1620 return ret;
1621
1622 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1623
1624 for (gpu_freq = dev_priv->rps.min_delay;
1625 gpu_freq <= dev_priv->rps.max_delay;
1626 gpu_freq++) {
1627 ia_freq = gpu_freq;
1628 sandybridge_pcode_read(dev_priv,
1629 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1630 &ia_freq);
1631 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1632 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1633 ((ia_freq >> 0) & 0xff) * 100,
1634 ((ia_freq >> 8) & 0xff) * 100);
1635 }
1636
1637 mutex_unlock(&dev_priv->rps.hw_lock);
1638
1639 return 0;
1640}
1641
1642static int i915_gfxec(struct seq_file *m, void *unused)
1643{
1644 struct drm_info_node *node = (struct drm_info_node *) m->private;
1645 struct drm_device *dev = node->minor->dev;
1646 drm_i915_private_t *dev_priv = dev->dev_private;
1647 int ret;
1648
1649 ret = mutex_lock_interruptible(&dev->struct_mutex);
1650 if (ret)
1651 return ret;
1652
1653 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1654
1655 mutex_unlock(&dev->struct_mutex);
1656
1657 return 0;
1658}
1659
1660static int i915_opregion(struct seq_file *m, void *unused)
1661{
1662 struct drm_info_node *node = (struct drm_info_node *) m->private;
1663 struct drm_device *dev = node->minor->dev;
1664 drm_i915_private_t *dev_priv = dev->dev_private;
1665 struct intel_opregion *opregion = &dev_priv->opregion;
1666 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1667 int ret;
1668
1669 if (data == NULL)
1670 return -ENOMEM;
1671
1672 ret = mutex_lock_interruptible(&dev->struct_mutex);
1673 if (ret)
1674 goto out;
1675
1676 if (opregion->header) {
1677 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1678 seq_write(m, data, OPREGION_SIZE);
1679 }
1680
1681 mutex_unlock(&dev->struct_mutex);
1682
1683out:
1684 kfree(data);
1685 return 0;
1686}
1687
1688static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1689{
1690 struct drm_info_node *node = (struct drm_info_node *) m->private;
1691 struct drm_device *dev = node->minor->dev;
1692 drm_i915_private_t *dev_priv = dev->dev_private;
1693 struct intel_fbdev *ifbdev;
1694 struct intel_framebuffer *fb;
1695 int ret;
1696
1697 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1698 if (ret)
1699 return ret;
1700
1701 ifbdev = dev_priv->fbdev;
1702 fb = to_intel_framebuffer(ifbdev->helper.fb);
1703
1704 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1705 fb->base.width,
1706 fb->base.height,
1707 fb->base.depth,
1708 fb->base.bits_per_pixel,
1709 atomic_read(&fb->base.refcount.refcount));
1710 describe_obj(m, fb->obj);
1711 seq_putc(m, '\n');
1712 mutex_unlock(&dev->mode_config.mutex);
1713
1714 mutex_lock(&dev->mode_config.fb_lock);
1715 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1716 if (&fb->base == ifbdev->helper.fb)
1717 continue;
1718
1719 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1720 fb->base.width,
1721 fb->base.height,
1722 fb->base.depth,
1723 fb->base.bits_per_pixel,
1724 atomic_read(&fb->base.refcount.refcount));
1725 describe_obj(m, fb->obj);
1726 seq_putc(m, '\n');
1727 }
1728 mutex_unlock(&dev->mode_config.fb_lock);
1729
1730 return 0;
1731}
1732
1733static int i915_context_status(struct seq_file *m, void *unused)
1734{
1735 struct drm_info_node *node = (struct drm_info_node *) m->private;
1736 struct drm_device *dev = node->minor->dev;
1737 drm_i915_private_t *dev_priv = dev->dev_private;
1738 struct intel_ring_buffer *ring;
1739 int ret, i;
1740
1741 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1742 if (ret)
1743 return ret;
1744
1745 if (dev_priv->ips.pwrctx) {
1746 seq_puts(m, "power context ");
1747 describe_obj(m, dev_priv->ips.pwrctx);
1748 seq_putc(m, '\n');
1749 }
1750
1751 if (dev_priv->ips.renderctx) {
1752 seq_puts(m, "render context ");
1753 describe_obj(m, dev_priv->ips.renderctx);
1754 seq_putc(m, '\n');
1755 }
1756
1757 for_each_ring(ring, dev_priv, i) {
1758 if (ring->default_context) {
1759 seq_printf(m, "HW default context %s ring ", ring->name);
1760 describe_obj(m, ring->default_context->obj);
1761 seq_putc(m, '\n');
1762 }
1763 }
1764
1765 mutex_unlock(&dev->mode_config.mutex);
1766
1767 return 0;
1768}
1769
1770static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1771{
1772 struct drm_info_node *node = (struct drm_info_node *) m->private;
1773 struct drm_device *dev = node->minor->dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 unsigned forcewake_count;
1776
1777 spin_lock_irq(&dev_priv->gt_lock);
1778 forcewake_count = dev_priv->forcewake_count;
1779 spin_unlock_irq(&dev_priv->gt_lock);
1780
1781 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1782
1783 return 0;
1784}
1785
1786static const char *swizzle_string(unsigned swizzle)
1787{
1788 switch (swizzle) {
1789 case I915_BIT_6_SWIZZLE_NONE:
1790 return "none";
1791 case I915_BIT_6_SWIZZLE_9:
1792 return "bit9";
1793 case I915_BIT_6_SWIZZLE_9_10:
1794 return "bit9/bit10";
1795 case I915_BIT_6_SWIZZLE_9_11:
1796 return "bit9/bit11";
1797 case I915_BIT_6_SWIZZLE_9_10_11:
1798 return "bit9/bit10/bit11";
1799 case I915_BIT_6_SWIZZLE_9_17:
1800 return "bit9/bit17";
1801 case I915_BIT_6_SWIZZLE_9_10_17:
1802 return "bit9/bit10/bit17";
1803 case I915_BIT_6_SWIZZLE_UNKNOWN:
1804 return "unknown";
1805 }
1806
1807 return "bug";
1808}
1809
1810static int i915_swizzle_info(struct seq_file *m, void *data)
1811{
1812 struct drm_info_node *node = (struct drm_info_node *) m->private;
1813 struct drm_device *dev = node->minor->dev;
1814 struct drm_i915_private *dev_priv = dev->dev_private;
1815 int ret;
1816
1817 ret = mutex_lock_interruptible(&dev->struct_mutex);
1818 if (ret)
1819 return ret;
1820
1821 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1822 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1823 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1824 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1825
1826 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1827 seq_printf(m, "DDC = 0x%08x\n",
1828 I915_READ(DCC));
1829 seq_printf(m, "C0DRB3 = 0x%04x\n",
1830 I915_READ16(C0DRB3));
1831 seq_printf(m, "C1DRB3 = 0x%04x\n",
1832 I915_READ16(C1DRB3));
1833 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1834 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1835 I915_READ(MAD_DIMM_C0));
1836 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1837 I915_READ(MAD_DIMM_C1));
1838 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1839 I915_READ(MAD_DIMM_C2));
1840 seq_printf(m, "TILECTL = 0x%08x\n",
1841 I915_READ(TILECTL));
1842 seq_printf(m, "ARB_MODE = 0x%08x\n",
1843 I915_READ(ARB_MODE));
1844 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1845 I915_READ(DISP_ARB_CTL));
1846 }
1847 mutex_unlock(&dev->struct_mutex);
1848
1849 return 0;
1850}
1851
1852static int i915_ppgtt_info(struct seq_file *m, void *data)
1853{
1854 struct drm_info_node *node = (struct drm_info_node *) m->private;
1855 struct drm_device *dev = node->minor->dev;
1856 struct drm_i915_private *dev_priv = dev->dev_private;
1857 struct intel_ring_buffer *ring;
1858 int i, ret;
1859
1860
1861 ret = mutex_lock_interruptible(&dev->struct_mutex);
1862 if (ret)
1863 return ret;
1864 if (INTEL_INFO(dev)->gen == 6)
1865 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1866
1867 for_each_ring(ring, dev_priv, i) {
1868 seq_printf(m, "%s\n", ring->name);
1869 if (INTEL_INFO(dev)->gen == 7)
1870 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1871 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1872 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1873 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1874 }
1875 if (dev_priv->mm.aliasing_ppgtt) {
1876 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1877
1878 seq_puts(m, "aliasing PPGTT:\n");
1879 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1880 }
1881 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1882 mutex_unlock(&dev->struct_mutex);
1883
1884 return 0;
1885}
1886
1887static int i915_dpio_info(struct seq_file *m, void *data)
1888{
1889 struct drm_info_node *node = (struct drm_info_node *) m->private;
1890 struct drm_device *dev = node->minor->dev;
1891 struct drm_i915_private *dev_priv = dev->dev_private;
1892 int ret;
1893
1894
1895 if (!IS_VALLEYVIEW(dev)) {
1896 seq_puts(m, "unsupported\n");
1897 return 0;
1898 }
1899
1900 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1901 if (ret)
1902 return ret;
1903
1904 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1905
1906 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1907 vlv_dpio_read(dev_priv, _DPIO_DIV_A));
1908 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1909 vlv_dpio_read(dev_priv, _DPIO_DIV_B));
1910
1911 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1912 vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
1913 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1914 vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
1915
1916 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1917 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1918 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1919 vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1920
1921 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1922 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
1923 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1924 vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
1925
1926 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1927 vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1928
1929 mutex_unlock(&dev_priv->dpio_lock);
1930
1931 return 0;
1932}
1933
1934static int
1935i915_wedged_get(void *data, u64 *val)
1936{
1937 struct drm_device *dev = data;
1938 drm_i915_private_t *dev_priv = dev->dev_private;
1939
1940 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1941
1942 return 0;
1943}
1944
1945static int
1946i915_wedged_set(void *data, u64 val)
1947{
1948 struct drm_device *dev = data;
1949
1950 DRM_INFO("Manually setting wedged to %llu\n", val);
1951 i915_handle_error(dev, val);
1952
1953 return 0;
1954}
1955
1956DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1957 i915_wedged_get, i915_wedged_set,
1958 "%llu\n");
1959
1960static int
1961i915_ring_stop_get(void *data, u64 *val)
1962{
1963 struct drm_device *dev = data;
1964 drm_i915_private_t *dev_priv = dev->dev_private;
1965
1966 *val = dev_priv->gpu_error.stop_rings;
1967
1968 return 0;
1969}
1970
1971static int
1972i915_ring_stop_set(void *data, u64 val)
1973{
1974 struct drm_device *dev = data;
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 int ret;
1977
1978 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1979
1980 ret = mutex_lock_interruptible(&dev->struct_mutex);
1981 if (ret)
1982 return ret;
1983
1984 dev_priv->gpu_error.stop_rings = val;
1985 mutex_unlock(&dev->struct_mutex);
1986
1987 return 0;
1988}
1989
1990DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1991 i915_ring_stop_get, i915_ring_stop_set,
1992 "0x%08llx\n");
1993
1994#define DROP_UNBOUND 0x1
1995#define DROP_BOUND 0x2
1996#define DROP_RETIRE 0x4
1997#define DROP_ACTIVE 0x8
1998#define DROP_ALL (DROP_UNBOUND | \
1999 DROP_BOUND | \
2000 DROP_RETIRE | \
2001 DROP_ACTIVE)
2002static int
2003i915_drop_caches_get(void *data, u64 *val)
2004{
2005 *val = DROP_ALL;
2006
2007 return 0;
2008}
2009
2010static int
2011i915_drop_caches_set(void *data, u64 val)
2012{
2013 struct drm_device *dev = data;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 struct drm_i915_gem_object *obj, *next;
2016 int ret;
2017
2018 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
2019
2020 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2021 * on ioctls on -EAGAIN. */
2022 ret = mutex_lock_interruptible(&dev->struct_mutex);
2023 if (ret)
2024 return ret;
2025
2026 if (val & DROP_ACTIVE) {
2027 ret = i915_gpu_idle(dev);
2028 if (ret)
2029 goto unlock;
2030 }
2031
2032 if (val & (DROP_RETIRE | DROP_ACTIVE))
2033 i915_gem_retire_requests(dev);
2034
2035 if (val & DROP_BOUND) {
2036 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
2037 if (obj->pin_count == 0) {
2038 ret = i915_gem_object_unbind(obj);
2039 if (ret)
2040 goto unlock;
2041 }
2042 }
2043
2044 if (val & DROP_UNBOUND) {
2045 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2046 global_list)
2047 if (obj->pages_pin_count == 0) {
2048 ret = i915_gem_object_put_pages(obj);
2049 if (ret)
2050 goto unlock;
2051 }
2052 }
2053
2054unlock:
2055 mutex_unlock(&dev->struct_mutex);
2056
2057 return ret;
2058}
2059
2060DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2061 i915_drop_caches_get, i915_drop_caches_set,
2062 "0x%08llx\n");
2063
2064static int
2065i915_max_freq_get(void *data, u64 *val)
2066{
2067 struct drm_device *dev = data;
2068 drm_i915_private_t *dev_priv = dev->dev_private;
2069 int ret;
2070
2071 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2072 return -ENODEV;
2073
2074 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2075 if (ret)
2076 return ret;
2077
2078 if (IS_VALLEYVIEW(dev))
2079 *val = vlv_gpu_freq(dev_priv->mem_freq,
2080 dev_priv->rps.max_delay);
2081 else
2082 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2083 mutex_unlock(&dev_priv->rps.hw_lock);
2084
2085 return 0;
2086}
2087
2088static int
2089i915_max_freq_set(void *data, u64 val)
2090{
2091 struct drm_device *dev = data;
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 int ret;
2094
2095 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2096 return -ENODEV;
2097
2098 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2099
2100 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2101 if (ret)
2102 return ret;
2103
2104 /*
2105 * Turbo will still be enabled, but won't go above the set value.
2106 */
2107 if (IS_VALLEYVIEW(dev)) {
2108 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2109 dev_priv->rps.max_delay = val;
2110 gen6_set_rps(dev, val);
2111 } else {
2112 do_div(val, GT_FREQUENCY_MULTIPLIER);
2113 dev_priv->rps.max_delay = val;
2114 gen6_set_rps(dev, val);
2115 }
2116
2117 mutex_unlock(&dev_priv->rps.hw_lock);
2118
2119 return 0;
2120}
2121
2122DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2123 i915_max_freq_get, i915_max_freq_set,
2124 "%llu\n");
2125
2126static int
2127i915_min_freq_get(void *data, u64 *val)
2128{
2129 struct drm_device *dev = data;
2130 drm_i915_private_t *dev_priv = dev->dev_private;
2131 int ret;
2132
2133 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2134 return -ENODEV;
2135
2136 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2137 if (ret)
2138 return ret;
2139
2140 if (IS_VALLEYVIEW(dev))
2141 *val = vlv_gpu_freq(dev_priv->mem_freq,
2142 dev_priv->rps.min_delay);
2143 else
2144 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2145 mutex_unlock(&dev_priv->rps.hw_lock);
2146
2147 return 0;
2148}
2149
2150static int
2151i915_min_freq_set(void *data, u64 val)
2152{
2153 struct drm_device *dev = data;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 int ret;
2156
2157 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2158 return -ENODEV;
2159
2160 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2161
2162 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2163 if (ret)
2164 return ret;
2165
2166 /*
2167 * Turbo will still be enabled, but won't go below the set value.
2168 */
2169 if (IS_VALLEYVIEW(dev)) {
2170 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2171 dev_priv->rps.min_delay = val;
2172 valleyview_set_rps(dev, val);
2173 } else {
2174 do_div(val, GT_FREQUENCY_MULTIPLIER);
2175 dev_priv->rps.min_delay = val;
2176 gen6_set_rps(dev, val);
2177 }
2178 mutex_unlock(&dev_priv->rps.hw_lock);
2179
2180 return 0;
2181}
2182
2183DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2184 i915_min_freq_get, i915_min_freq_set,
2185 "%llu\n");
2186
2187static int
2188i915_cache_sharing_get(void *data, u64 *val)
2189{
2190 struct drm_device *dev = data;
2191 drm_i915_private_t *dev_priv = dev->dev_private;
2192 u32 snpcr;
2193 int ret;
2194
2195 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2196 return -ENODEV;
2197
2198 ret = mutex_lock_interruptible(&dev->struct_mutex);
2199 if (ret)
2200 return ret;
2201
2202 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2203 mutex_unlock(&dev_priv->dev->struct_mutex);
2204
2205 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2206
2207 return 0;
2208}
2209
2210static int
2211i915_cache_sharing_set(void *data, u64 val)
2212{
2213 struct drm_device *dev = data;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 u32 snpcr;
2216
2217 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2218 return -ENODEV;
2219
2220 if (val > 3)
2221 return -EINVAL;
2222
2223 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2224
2225 /* Update the cache sharing policy here as well */
2226 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2227 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2228 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2229 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2230
2231 return 0;
2232}
2233
2234DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2235 i915_cache_sharing_get, i915_cache_sharing_set,
2236 "%llu\n");
2237
2238/* As the drm_debugfs_init() routines are called before dev->dev_private is
2239 * allocated we need to hook into the minor for release. */
2240static int
2241drm_add_fake_info_node(struct drm_minor *minor,
2242 struct dentry *ent,
2243 const void *key)
2244{
2245 struct drm_info_node *node;
2246
2247 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
2248 if (node == NULL) {
2249 debugfs_remove(ent);
2250 return -ENOMEM;
2251 }
2252
2253 node->minor = minor;
2254 node->dent = ent;
2255 node->info_ent = (void *) key;
2256
2257 mutex_lock(&minor->debugfs_lock);
2258 list_add(&node->list, &minor->debugfs_list);
2259 mutex_unlock(&minor->debugfs_lock);
2260
2261 return 0;
2262}
2263
2264static int i915_forcewake_open(struct inode *inode, struct file *file)
2265{
2266 struct drm_device *dev = inode->i_private;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268
2269 if (INTEL_INFO(dev)->gen < 6)
2270 return 0;
2271
2272 gen6_gt_force_wake_get(dev_priv);
2273
2274 return 0;
2275}
2276
2277static int i915_forcewake_release(struct inode *inode, struct file *file)
2278{
2279 struct drm_device *dev = inode->i_private;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281
2282 if (INTEL_INFO(dev)->gen < 6)
2283 return 0;
2284
2285 gen6_gt_force_wake_put(dev_priv);
2286
2287 return 0;
2288}
2289
2290static const struct file_operations i915_forcewake_fops = {
2291 .owner = THIS_MODULE,
2292 .open = i915_forcewake_open,
2293 .release = i915_forcewake_release,
2294};
2295
2296static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2297{
2298 struct drm_device *dev = minor->dev;
2299 struct dentry *ent;
2300
2301 ent = debugfs_create_file("i915_forcewake_user",
2302 S_IRUSR,
2303 root, dev,
2304 &i915_forcewake_fops);
2305 if (IS_ERR(ent))
2306 return PTR_ERR(ent);
2307
2308 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2309}
2310
2311static int i915_debugfs_create(struct dentry *root,
2312 struct drm_minor *minor,
2313 const char *name,
2314 const struct file_operations *fops)
2315{
2316 struct drm_device *dev = minor->dev;
2317 struct dentry *ent;
2318
2319 ent = debugfs_create_file(name,
2320 S_IRUGO | S_IWUSR,
2321 root, dev,
2322 fops);
2323 if (IS_ERR(ent))
2324 return PTR_ERR(ent);
2325
2326 return drm_add_fake_info_node(minor, ent, fops);
2327}
2328
2329static struct drm_info_list i915_debugfs_list[] = {
2330 {"i915_capabilities", i915_capabilities, 0},
2331 {"i915_gem_objects", i915_gem_object_info, 0},
2332 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2333 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2334 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2335 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2336 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2337 {"i915_gem_request", i915_gem_request_info, 0},
2338 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2339 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2340 {"i915_gem_interrupt", i915_interrupt_info, 0},
2341 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2342 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2343 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2344 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2345 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2346 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2347 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2348 {"i915_inttoext_table", i915_inttoext_table, 0},
2349 {"i915_drpc_info", i915_drpc_info, 0},
2350 {"i915_emon_status", i915_emon_status, 0},
2351 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2352 {"i915_gfxec", i915_gfxec, 0},
2353 {"i915_fbc_status", i915_fbc_status, 0},
2354 {"i915_ips_status", i915_ips_status, 0},
2355 {"i915_sr_status", i915_sr_status, 0},
2356 {"i915_opregion", i915_opregion, 0},
2357 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2358 {"i915_context_status", i915_context_status, 0},
2359 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2360 {"i915_swizzle_info", i915_swizzle_info, 0},
2361 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2362 {"i915_dpio", i915_dpio_info, 0},
2363};
2364#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2365
2366int i915_debugfs_init(struct drm_minor *minor)
2367{
2368 int ret;
2369
2370 ret = i915_debugfs_create(minor->debugfs_root, minor,
2371 "i915_wedged",
2372 &i915_wedged_fops);
2373 if (ret)
2374 return ret;
2375
2376 ret = i915_forcewake_create(minor->debugfs_root, minor);
2377 if (ret)
2378 return ret;
2379
2380 ret = i915_debugfs_create(minor->debugfs_root, minor,
2381 "i915_max_freq",
2382 &i915_max_freq_fops);
2383 if (ret)
2384 return ret;
2385
2386 ret = i915_debugfs_create(minor->debugfs_root, minor,
2387 "i915_min_freq",
2388 &i915_min_freq_fops);
2389 if (ret)
2390 return ret;
2391
2392 ret = i915_debugfs_create(minor->debugfs_root, minor,
2393 "i915_cache_sharing",
2394 &i915_cache_sharing_fops);
2395 if (ret)
2396 return ret;
2397
2398 ret = i915_debugfs_create(minor->debugfs_root, minor,
2399 "i915_ring_stop",
2400 &i915_ring_stop_fops);
2401 if (ret)
2402 return ret;
2403
2404 ret = i915_debugfs_create(minor->debugfs_root, minor,
2405 "i915_gem_drop_caches",
2406 &i915_drop_caches_fops);
2407 if (ret)
2408 return ret;
2409
2410 ret = i915_debugfs_create(minor->debugfs_root, minor,
2411 "i915_error_state",
2412 &i915_error_state_fops);
2413 if (ret)
2414 return ret;
2415
2416 ret = i915_debugfs_create(minor->debugfs_root, minor,
2417 "i915_next_seqno",
2418 &i915_next_seqno_fops);
2419 if (ret)
2420 return ret;
2421
2422 return drm_debugfs_create_files(i915_debugfs_list,
2423 I915_DEBUGFS_ENTRIES,
2424 minor->debugfs_root, minor);
2425}
2426
2427void i915_debugfs_cleanup(struct drm_minor *minor)
2428{
2429 drm_debugfs_remove_files(i915_debugfs_list,
2430 I915_DEBUGFS_ENTRIES, minor);
2431 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2432 1, minor);
2433 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2434 1, minor);
2435 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2436 1, minor);
2437 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2438 1, minor);
2439 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2440 1, minor);
2441 drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
2442 1, minor);
2443 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2444 1, minor);
2445 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2446 1, minor);
2447 drm_debugfs_remove_files((struct drm_info_list *) &i915_next_seqno_fops,
2448 1, minor);
2449}
2450
2451#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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