projects / deliverable / linux.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
drm/i915: use lower aux clock divider on non-ULT HSW
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
... / ...
CommitLineData
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include "i915_reg.h"
36#include "intel_bios.h"
37#include "intel_ringbuffer.h"
38#include <linux/io-mapping.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41#include <drm/intel-gtt.h>
42#include <linux/backlight.h>
43#include <linux/intel-iommu.h>
44#include <linux/kref.h>
45#include <linux/pm_qos.h>
46
47/* General customization:
48 */
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
54#define DRIVER_DATE "20080730"
55
56enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
59 PIPE_C,
60 I915_MAX_PIPES
61};
62#define pipe_name(p) ((p) + 'A')
63
64enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69};
70#define transcoder_name(t) ((t) + 'A')
71
72enum plane {
73 PLANE_A = 0,
74 PLANE_B,
75 PLANE_C,
76};
77#define plane_name(p) ((p) + 'A')
78
79enum port {
80 PORT_A = 0,
81 PORT_B,
82 PORT_C,
83 PORT_D,
84 PORT_E,
85 I915_MAX_PORTS
86};
87#define port_name(p) ((p) + 'A')
88
89enum hpd_pin {
90 HPD_NONE = 0,
91 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
92 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
93 HPD_CRT,
94 HPD_SDVO_B,
95 HPD_SDVO_C,
96 HPD_PORT_B,
97 HPD_PORT_C,
98 HPD_PORT_D,
99 HPD_NUM_PINS
100};
101
102#define I915_GEM_GPU_DOMAINS \
103 (I915_GEM_DOMAIN_RENDER | \
104 I915_GEM_DOMAIN_SAMPLER | \
105 I915_GEM_DOMAIN_COMMAND | \
106 I915_GEM_DOMAIN_INSTRUCTION | \
107 I915_GEM_DOMAIN_VERTEX)
108
109#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
110
111#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
112 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
113 if ((intel_encoder)->base.crtc == (__crtc))
114
115struct intel_pch_pll {
116 int refcount; /* count of number of CRTCs sharing this PLL */
117 int active; /* count of number of active CRTCs (i.e. DPMS on) */
118 bool on; /* is the PLL actually active? Disabled during modeset */
119 int pll_reg;
120 int fp0_reg;
121 int fp1_reg;
122};
123#define I915_NUM_PLLS 2
124
125/* Used by dp and fdi links */
126struct intel_link_m_n {
127 uint32_t tu;
128 uint32_t gmch_m;
129 uint32_t gmch_n;
130 uint32_t link_m;
131 uint32_t link_n;
132};
133
134void intel_link_compute_m_n(int bpp, int nlanes,
135 int pixel_clock, int link_clock,
136 struct intel_link_m_n *m_n);
137
138struct intel_ddi_plls {
139 int spll_refcount;
140 int wrpll1_refcount;
141 int wrpll2_refcount;
142};
143
144/* Interface history:
145 *
146 * 1.1: Original.
147 * 1.2: Add Power Management
148 * 1.3: Add vblank support
149 * 1.4: Fix cmdbuffer path, add heap destroy
150 * 1.5: Add vblank pipe configuration
151 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
152 * - Support vertical blank on secondary display pipe
153 */
154#define DRIVER_MAJOR 1
155#define DRIVER_MINOR 6
156#define DRIVER_PATCHLEVEL 0
157
158#define WATCH_COHERENCY 0
159#define WATCH_LISTS 0
160#define WATCH_GTT 0
161
162#define I915_GEM_PHYS_CURSOR_0 1
163#define I915_GEM_PHYS_CURSOR_1 2
164#define I915_GEM_PHYS_OVERLAY_REGS 3
165#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
166
167struct drm_i915_gem_phys_object {
168 int id;
169 struct page **page_list;
170 drm_dma_handle_t *handle;
171 struct drm_i915_gem_object *cur_obj;
172};
173
174struct opregion_header;
175struct opregion_acpi;
176struct opregion_swsci;
177struct opregion_asle;
178struct drm_i915_private;
179
180struct intel_opregion {
181 struct opregion_header __iomem *header;
182 struct opregion_acpi __iomem *acpi;
183 struct opregion_swsci __iomem *swsci;
184 struct opregion_asle __iomem *asle;
185 void __iomem *vbt;
186 u32 __iomem *lid_state;
187};
188#define OPREGION_SIZE (8*1024)
189
190struct intel_overlay;
191struct intel_overlay_error_state;
192
193struct drm_i915_master_private {
194 drm_local_map_t *sarea;
195 struct _drm_i915_sarea *sarea_priv;
196};
197#define I915_FENCE_REG_NONE -1
198#define I915_MAX_NUM_FENCES 16
199/* 16 fences + sign bit for FENCE_REG_NONE */
200#define I915_MAX_NUM_FENCE_BITS 5
201
202struct drm_i915_fence_reg {
203 struct list_head lru_list;
204 struct drm_i915_gem_object *obj;
205 int pin_count;
206};
207
208struct sdvo_device_mapping {
209 u8 initialized;
210 u8 dvo_port;
211 u8 slave_addr;
212 u8 dvo_wiring;
213 u8 i2c_pin;
214 u8 ddc_pin;
215};
216
217struct intel_display_error_state;
218
219struct drm_i915_error_state {
220 struct kref ref;
221 u32 eir;
222 u32 pgtbl_er;
223 u32 ier;
224 u32 ccid;
225 u32 derrmr;
226 u32 forcewake;
227 bool waiting[I915_NUM_RINGS];
228 u32 pipestat[I915_MAX_PIPES];
229 u32 tail[I915_NUM_RINGS];
230 u32 head[I915_NUM_RINGS];
231 u32 ctl[I915_NUM_RINGS];
232 u32 ipeir[I915_NUM_RINGS];
233 u32 ipehr[I915_NUM_RINGS];
234 u32 instdone[I915_NUM_RINGS];
235 u32 acthd[I915_NUM_RINGS];
236 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
237 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
238 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
239 /* our own tracking of ring head and tail */
240 u32 cpu_ring_head[I915_NUM_RINGS];
241 u32 cpu_ring_tail[I915_NUM_RINGS];
242 u32 error; /* gen6+ */
243 u32 err_int; /* gen7 */
244 u32 instpm[I915_NUM_RINGS];
245 u32 instps[I915_NUM_RINGS];
246 u32 extra_instdone[I915_NUM_INSTDONE_REG];
247 u32 seqno[I915_NUM_RINGS];
248 u64 bbaddr;
249 u32 fault_reg[I915_NUM_RINGS];
250 u32 done_reg;
251 u32 faddr[I915_NUM_RINGS];
252 u64 fence[I915_MAX_NUM_FENCES];
253 struct timeval time;
254 struct drm_i915_error_ring {
255 struct drm_i915_error_object {
256 int page_count;
257 u32 gtt_offset;
258 u32 *pages[0];
259 } *ringbuffer, *batchbuffer, *ctx;
260 struct drm_i915_error_request {
261 long jiffies;
262 u32 seqno;
263 u32 tail;
264 } *requests;
265 int num_requests;
266 } ring[I915_NUM_RINGS];
267 struct drm_i915_error_buffer {
268 u32 size;
269 u32 name;
270 u32 rseqno, wseqno;
271 u32 gtt_offset;
272 u32 read_domains;
273 u32 write_domain;
274 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
275 s32 pinned:2;
276 u32 tiling:2;
277 u32 dirty:1;
278 u32 purgeable:1;
279 s32 ring:4;
280 u32 cache_level:2;
281 } *active_bo, *pinned_bo;
282 u32 active_bo_count, pinned_bo_count;
283 struct intel_overlay_error_state *overlay;
284 struct intel_display_error_state *display;
285};
286
287struct intel_crtc_config;
288struct intel_crtc;
289
290struct drm_i915_display_funcs {
291 bool (*fbc_enabled)(struct drm_device *dev);
292 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
293 void (*disable_fbc)(struct drm_device *dev);
294 int (*get_display_clock_speed)(struct drm_device *dev);
295 int (*get_fifo_size)(struct drm_device *dev, int plane);
296 void (*update_wm)(struct drm_device *dev);
297 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
298 uint32_t sprite_width, int pixel_size);
299 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
300 struct drm_display_mode *mode);
301 void (*modeset_global_resources)(struct drm_device *dev);
302 /* Returns the active state of the crtc, and if the crtc is active,
303 * fills out the pipe-config with the hw state. */
304 bool (*get_pipe_config)(struct intel_crtc *,
305 struct intel_crtc_config *);
306 int (*crtc_mode_set)(struct drm_crtc *crtc,
307 int x, int y,
308 struct drm_framebuffer *old_fb);
309 void (*crtc_enable)(struct drm_crtc *crtc);
310 void (*crtc_disable)(struct drm_crtc *crtc);
311 void (*off)(struct drm_crtc *crtc);
312 void (*write_eld)(struct drm_connector *connector,
313 struct drm_crtc *crtc);
314 void (*fdi_link_train)(struct drm_crtc *crtc);
315 void (*init_clock_gating)(struct drm_device *dev);
316 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
317 struct drm_framebuffer *fb,
318 struct drm_i915_gem_object *obj);
319 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
320 int x, int y);
321 void (*hpd_irq_setup)(struct drm_device *dev);
322 /* clock updates for mode set */
323 /* cursor updates */
324 /* render clock increase/decrease */
325 /* display clock increase/decrease */
326 /* pll clock increase/decrease */
327};
328
329struct drm_i915_gt_funcs {
330 void (*force_wake_get)(struct drm_i915_private *dev_priv);
331 void (*force_wake_put)(struct drm_i915_private *dev_priv);
332};
333
334#define DEV_INFO_FLAGS \
335 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
336 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
337 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
338 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
339 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
340 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
341 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
342 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
343 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
344 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
345 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
346 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
347 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
348 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
349 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
350 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
351 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
352 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
353 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
354 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
355 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
356 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
357 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
358 DEV_INFO_FLAG(has_llc)
359
360struct intel_device_info {
361 u32 display_mmio_offset;
362 u8 num_pipes:3;
363 u8 gen;
364 u8 is_mobile:1;
365 u8 is_i85x:1;
366 u8 is_i915g:1;
367 u8 is_i945gm:1;
368 u8 is_g33:1;
369 u8 need_gfx_hws:1;
370 u8 is_g4x:1;
371 u8 is_pineview:1;
372 u8 is_broadwater:1;
373 u8 is_crestline:1;
374 u8 is_ivybridge:1;
375 u8 is_valleyview:1;
376 u8 has_force_wake:1;
377 u8 is_haswell:1;
378 u8 has_fbc:1;
379 u8 has_pipe_cxsr:1;
380 u8 has_hotplug:1;
381 u8 cursor_needs_physical:1;
382 u8 has_overlay:1;
383 u8 overlay_needs_physical:1;
384 u8 supports_tv:1;
385 u8 has_bsd_ring:1;
386 u8 has_blt_ring:1;
387 u8 has_llc:1;
388};
389
390enum i915_cache_level {
391 I915_CACHE_NONE = 0,
392 I915_CACHE_LLC,
393 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
394};
395
396/* The Graphics Translation Table is the way in which GEN hardware translates a
397 * Graphics Virtual Address into a Physical Address. In addition to the normal
398 * collateral associated with any va->pa translations GEN hardware also has a
399 * portion of the GTT which can be mapped by the CPU and remain both coherent
400 * and correct (in cases like swizzling). That region is referred to as GMADR in
401 * the spec.
402 */
403struct i915_gtt {
404 unsigned long start; /* Start offset of used GTT */
405 size_t total; /* Total size GTT can map */
406 size_t stolen_size; /* Total size of stolen memory */
407
408 unsigned long mappable_end; /* End offset that we can CPU map */
409 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
410 phys_addr_t mappable_base; /* PA of our GMADR */
411
412 /** "Graphics Stolen Memory" holds the global PTEs */
413 void __iomem *gsm;
414
415 bool do_idle_maps;
416 dma_addr_t scratch_page_dma;
417 struct page *scratch_page;
418
419 /* global gtt ops */
420 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
421 size_t *stolen, phys_addr_t *mappable_base,
422 unsigned long *mappable_end);
423 void (*gtt_remove)(struct drm_device *dev);
424 void (*gtt_clear_range)(struct drm_device *dev,
425 unsigned int first_entry,
426 unsigned int num_entries);
427 void (*gtt_insert_entries)(struct drm_device *dev,
428 struct sg_table *st,
429 unsigned int pg_start,
430 enum i915_cache_level cache_level);
431};
432#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
433
434#define I915_PPGTT_PD_ENTRIES 512
435#define I915_PPGTT_PT_ENTRIES 1024
436struct i915_hw_ppgtt {
437 struct drm_device *dev;
438 unsigned num_pd_entries;
439 struct page **pt_pages;
440 uint32_t pd_offset;
441 dma_addr_t *pt_dma_addr;
442 dma_addr_t scratch_page_dma_addr;
443
444 /* pte functions, mirroring the interface of the global gtt. */
445 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
446 unsigned int first_entry,
447 unsigned int num_entries);
448 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
449 struct sg_table *st,
450 unsigned int pg_start,
451 enum i915_cache_level cache_level);
452 int (*enable)(struct drm_device *dev);
453 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
454};
455
456
457/* This must match up with the value previously used for execbuf2.rsvd1. */
458#define DEFAULT_CONTEXT_ID 0
459struct i915_hw_context {
460 int id;
461 bool is_initialized;
462 struct drm_i915_file_private *file_priv;
463 struct intel_ring_buffer *ring;
464 struct drm_i915_gem_object *obj;
465};
466
467enum no_fbc_reason {
468 FBC_NO_OUTPUT, /* no outputs enabled to compress */
469 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
470 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
471 FBC_MODE_TOO_LARGE, /* mode too large for compression */
472 FBC_BAD_PLANE, /* fbc not supported on plane */
473 FBC_NOT_TILED, /* buffer not tiled */
474 FBC_MULTIPLE_PIPES, /* more than one pipe active */
475 FBC_MODULE_PARAM,
476};
477
478enum intel_pch {
479 PCH_NONE = 0, /* No PCH present */
480 PCH_IBX, /* Ibexpeak PCH */
481 PCH_CPT, /* Cougarpoint PCH */
482 PCH_LPT, /* Lynxpoint PCH */
483 PCH_NOP,
484};
485
486enum intel_sbi_destination {
487 SBI_ICLK,
488 SBI_MPHY,
489};
490
491#define QUIRK_PIPEA_FORCE (1<<0)
492#define QUIRK_LVDS_SSC_DISABLE (1<<1)
493#define QUIRK_INVERT_BRIGHTNESS (1<<2)
494
495struct intel_fbdev;
496struct intel_fbc_work;
497
498struct intel_gmbus {
499 struct i2c_adapter adapter;
500 u32 force_bit;
501 u32 reg0;
502 u32 gpio_reg;
503 struct i2c_algo_bit_data bit_algo;
504 struct drm_i915_private *dev_priv;
505};
506
507struct i915_suspend_saved_registers {
508 u8 saveLBB;
509 u32 saveDSPACNTR;
510 u32 saveDSPBCNTR;
511 u32 saveDSPARB;
512 u32 savePIPEACONF;
513 u32 savePIPEBCONF;
514 u32 savePIPEASRC;
515 u32 savePIPEBSRC;
516 u32 saveFPA0;
517 u32 saveFPA1;
518 u32 saveDPLL_A;
519 u32 saveDPLL_A_MD;
520 u32 saveHTOTAL_A;
521 u32 saveHBLANK_A;
522 u32 saveHSYNC_A;
523 u32 saveVTOTAL_A;
524 u32 saveVBLANK_A;
525 u32 saveVSYNC_A;
526 u32 saveBCLRPAT_A;
527 u32 saveTRANSACONF;
528 u32 saveTRANS_HTOTAL_A;
529 u32 saveTRANS_HBLANK_A;
530 u32 saveTRANS_HSYNC_A;
531 u32 saveTRANS_VTOTAL_A;
532 u32 saveTRANS_VBLANK_A;
533 u32 saveTRANS_VSYNC_A;
534 u32 savePIPEASTAT;
535 u32 saveDSPASTRIDE;
536 u32 saveDSPASIZE;
537 u32 saveDSPAPOS;
538 u32 saveDSPAADDR;
539 u32 saveDSPASURF;
540 u32 saveDSPATILEOFF;
541 u32 savePFIT_PGM_RATIOS;
542 u32 saveBLC_HIST_CTL;
543 u32 saveBLC_PWM_CTL;
544 u32 saveBLC_PWM_CTL2;
545 u32 saveBLC_CPU_PWM_CTL;
546 u32 saveBLC_CPU_PWM_CTL2;
547 u32 saveFPB0;
548 u32 saveFPB1;
549 u32 saveDPLL_B;
550 u32 saveDPLL_B_MD;
551 u32 saveHTOTAL_B;
552 u32 saveHBLANK_B;
553 u32 saveHSYNC_B;
554 u32 saveVTOTAL_B;
555 u32 saveVBLANK_B;
556 u32 saveVSYNC_B;
557 u32 saveBCLRPAT_B;
558 u32 saveTRANSBCONF;
559 u32 saveTRANS_HTOTAL_B;
560 u32 saveTRANS_HBLANK_B;
561 u32 saveTRANS_HSYNC_B;
562 u32 saveTRANS_VTOTAL_B;
563 u32 saveTRANS_VBLANK_B;
564 u32 saveTRANS_VSYNC_B;
565 u32 savePIPEBSTAT;
566 u32 saveDSPBSTRIDE;
567 u32 saveDSPBSIZE;
568 u32 saveDSPBPOS;
569 u32 saveDSPBADDR;
570 u32 saveDSPBSURF;
571 u32 saveDSPBTILEOFF;
572 u32 saveVGA0;
573 u32 saveVGA1;
574 u32 saveVGA_PD;
575 u32 saveVGACNTRL;
576 u32 saveADPA;
577 u32 saveLVDS;
578 u32 savePP_ON_DELAYS;
579 u32 savePP_OFF_DELAYS;
580 u32 saveDVOA;
581 u32 saveDVOB;
582 u32 saveDVOC;
583 u32 savePP_ON;
584 u32 savePP_OFF;
585 u32 savePP_CONTROL;
586 u32 savePP_DIVISOR;
587 u32 savePFIT_CONTROL;
588 u32 save_palette_a[256];
589 u32 save_palette_b[256];
590 u32 saveDPFC_CB_BASE;
591 u32 saveFBC_CFB_BASE;
592 u32 saveFBC_LL_BASE;
593 u32 saveFBC_CONTROL;
594 u32 saveFBC_CONTROL2;
595 u32 saveIER;
596 u32 saveIIR;
597 u32 saveIMR;
598 u32 saveDEIER;
599 u32 saveDEIMR;
600 u32 saveGTIER;
601 u32 saveGTIMR;
602 u32 saveFDI_RXA_IMR;
603 u32 saveFDI_RXB_IMR;
604 u32 saveCACHE_MODE_0;
605 u32 saveMI_ARB_STATE;
606 u32 saveSWF0[16];
607 u32 saveSWF1[16];
608 u32 saveSWF2[3];
609 u8 saveMSR;
610 u8 saveSR[8];
611 u8 saveGR[25];
612 u8 saveAR_INDEX;
613 u8 saveAR[21];
614 u8 saveDACMASK;
615 u8 saveCR[37];
616 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
617 u32 saveCURACNTR;
618 u32 saveCURAPOS;
619 u32 saveCURABASE;
620 u32 saveCURBCNTR;
621 u32 saveCURBPOS;
622 u32 saveCURBBASE;
623 u32 saveCURSIZE;
624 u32 saveDP_B;
625 u32 saveDP_C;
626 u32 saveDP_D;
627 u32 savePIPEA_GMCH_DATA_M;
628 u32 savePIPEB_GMCH_DATA_M;
629 u32 savePIPEA_GMCH_DATA_N;
630 u32 savePIPEB_GMCH_DATA_N;
631 u32 savePIPEA_DP_LINK_M;
632 u32 savePIPEB_DP_LINK_M;
633 u32 savePIPEA_DP_LINK_N;
634 u32 savePIPEB_DP_LINK_N;
635 u32 saveFDI_RXA_CTL;
636 u32 saveFDI_TXA_CTL;
637 u32 saveFDI_RXB_CTL;
638 u32 saveFDI_TXB_CTL;
639 u32 savePFA_CTL_1;
640 u32 savePFB_CTL_1;
641 u32 savePFA_WIN_SZ;
642 u32 savePFB_WIN_SZ;
643 u32 savePFA_WIN_POS;
644 u32 savePFB_WIN_POS;
645 u32 savePCH_DREF_CONTROL;
646 u32 saveDISP_ARB_CTL;
647 u32 savePIPEA_DATA_M1;
648 u32 savePIPEA_DATA_N1;
649 u32 savePIPEA_LINK_M1;
650 u32 savePIPEA_LINK_N1;
651 u32 savePIPEB_DATA_M1;
652 u32 savePIPEB_DATA_N1;
653 u32 savePIPEB_LINK_M1;
654 u32 savePIPEB_LINK_N1;
655 u32 saveMCHBAR_RENDER_STANDBY;
656 u32 savePCH_PORT_HOTPLUG;
657};
658
659struct intel_gen6_power_mgmt {
660 struct work_struct work;
661 u32 pm_iir;
662 /* lock - irqsave spinlock that protectects the work_struct and
663 * pm_iir. */
664 spinlock_t lock;
665
666 /* The below variables an all the rps hw state are protected by
667 * dev->struct mutext. */
668 u8 cur_delay;
669 u8 min_delay;
670 u8 max_delay;
671
672 struct delayed_work delayed_resume_work;
673
674 /*
675 * Protects RPS/RC6 register access and PCU communication.
676 * Must be taken after struct_mutex if nested.
677 */
678 struct mutex hw_lock;
679};
680
681/* defined intel_pm.c */
682extern spinlock_t mchdev_lock;
683
684struct intel_ilk_power_mgmt {
685 u8 cur_delay;
686 u8 min_delay;
687 u8 max_delay;
688 u8 fmax;
689 u8 fstart;
690
691 u64 last_count1;
692 unsigned long last_time1;
693 unsigned long chipset_power;
694 u64 last_count2;
695 struct timespec last_time2;
696 unsigned long gfx_power;
697 u8 corr;
698
699 int c_m;
700 int r_t;
701
702 struct drm_i915_gem_object *pwrctx;
703 struct drm_i915_gem_object *renderctx;
704};
705
706struct i915_dri1_state {
707 unsigned allow_batchbuffer : 1;
708 u32 __iomem *gfx_hws_cpu_addr;
709
710 unsigned int cpp;
711 int back_offset;
712 int front_offset;
713 int current_page;
714 int page_flipping;
715
716 uint32_t counter;
717};
718
719struct intel_l3_parity {
720 u32 *remap_info;
721 struct work_struct error_work;
722};
723
724struct i915_gem_mm {
725 /** Memory allocator for GTT stolen memory */
726 struct drm_mm stolen;
727 /** Memory allocator for GTT */
728 struct drm_mm gtt_space;
729 /** List of all objects in gtt_space. Used to restore gtt
730 * mappings on resume */
731 struct list_head bound_list;
732 /**
733 * List of objects which are not bound to the GTT (thus
734 * are idle and not used by the GPU) but still have
735 * (presumably uncached) pages still attached.
736 */
737 struct list_head unbound_list;
738
739 /** Usable portion of the GTT for GEM */
740 unsigned long stolen_base; /* limited to low memory (32-bit) */
741
742 int gtt_mtrr;
743
744 /** PPGTT used for aliasing the PPGTT with the GTT */
745 struct i915_hw_ppgtt *aliasing_ppgtt;
746
747 struct shrinker inactive_shrinker;
748 bool shrinker_no_lock_stealing;
749
750 /**
751 * List of objects currently involved in rendering.
752 *
753 * Includes buffers having the contents of their GPU caches
754 * flushed, not necessarily primitives. last_rendering_seqno
755 * represents when the rendering involved will be completed.
756 *
757 * A reference is held on the buffer while on this list.
758 */
759 struct list_head active_list;
760
761 /**
762 * LRU list of objects which are not in the ringbuffer and
763 * are ready to unbind, but are still in the GTT.
764 *
765 * last_rendering_seqno is 0 while an object is in this list.
766 *
767 * A reference is not held on the buffer while on this list,
768 * as merely being GTT-bound shouldn't prevent its being
769 * freed, and we'll pull it off the list in the free path.
770 */
771 struct list_head inactive_list;
772
773 /** LRU list of objects with fence regs on them. */
774 struct list_head fence_list;
775
776 /**
777 * We leave the user IRQ off as much as possible,
778 * but this means that requests will finish and never
779 * be retired once the system goes idle. Set a timer to
780 * fire periodically while the ring is running. When it
781 * fires, go retire requests.
782 */
783 struct delayed_work retire_work;
784
785 /**
786 * Are we in a non-interruptible section of code like
787 * modesetting?
788 */
789 bool interruptible;
790
791 /**
792 * Flag if the X Server, and thus DRM, is not currently in
793 * control of the device.
794 *
795 * This is set between LeaveVT and EnterVT. It needs to be
796 * replaced with a semaphore. It also needs to be
797 * transitioned away from for kernel modesetting.
798 */
799 int suspended;
800
801 /** Bit 6 swizzling required for X tiling */
802 uint32_t bit_6_swizzle_x;
803 /** Bit 6 swizzling required for Y tiling */
804 uint32_t bit_6_swizzle_y;
805
806 /* storage for physical objects */
807 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
808
809 /* accounting, useful for userland debugging */
810 size_t object_memory;
811 u32 object_count;
812};
813
814struct i915_gpu_error {
815 /* For hangcheck timer */
816#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
817#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
818 struct timer_list hangcheck_timer;
819 int hangcheck_count;
820 uint32_t last_acthd[I915_NUM_RINGS];
821 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
822
823 /* For reset and error_state handling. */
824 spinlock_t lock;
825 /* Protected by the above dev->gpu_error.lock. */
826 struct drm_i915_error_state *first_error;
827 struct work_struct work;
828
829 unsigned long last_reset;
830
831 /**
832 * State variable and reset counter controlling the reset flow
833 *
834 * Upper bits are for the reset counter. This counter is used by the
835 * wait_seqno code to race-free noticed that a reset event happened and
836 * that it needs to restart the entire ioctl (since most likely the
837 * seqno it waited for won't ever signal anytime soon).
838 *
839 * This is important for lock-free wait paths, where no contended lock
840 * naturally enforces the correct ordering between the bail-out of the
841 * waiter and the gpu reset work code.
842 *
843 * Lowest bit controls the reset state machine: Set means a reset is in
844 * progress. This state will (presuming we don't have any bugs) decay
845 * into either unset (successful reset) or the special WEDGED value (hw
846 * terminally sour). All waiters on the reset_queue will be woken when
847 * that happens.
848 */
849 atomic_t reset_counter;
850
851 /**
852 * Special values/flags for reset_counter
853 *
854 * Note that the code relies on
855 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
856 * being true.
857 */
858#define I915_RESET_IN_PROGRESS_FLAG 1
859#define I915_WEDGED 0xffffffff
860
861 /**
862 * Waitqueue to signal when the reset has completed. Used by clients
863 * that wait for dev_priv->mm.wedged to settle.
864 */
865 wait_queue_head_t reset_queue;
866
867 /* For gpu hang simulation. */
868 unsigned int stop_rings;
869};
870
871enum modeset_restore {
872 MODESET_ON_LID_OPEN,
873 MODESET_DONE,
874 MODESET_SUSPENDED,
875};
876
877typedef struct drm_i915_private {
878 struct drm_device *dev;
879 struct kmem_cache *slab;
880
881 const struct intel_device_info *info;
882
883 int relative_constants_mode;
884
885 void __iomem *regs;
886
887 struct drm_i915_gt_funcs gt;
888 /** gt_fifo_count and the subsequent register write are synchronized
889 * with dev->struct_mutex. */
890 unsigned gt_fifo_count;
891 /** forcewake_count is protected by gt_lock */
892 unsigned forcewake_count;
893 /** gt_lock is also taken in irq contexts. */
894 spinlock_t gt_lock;
895
896 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
897
898
899 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
900 * controller on different i2c buses. */
901 struct mutex gmbus_mutex;
902
903 /**
904 * Base address of the gmbus and gpio block.
905 */
906 uint32_t gpio_mmio_base;
907
908 wait_queue_head_t gmbus_wait_queue;
909
910 struct pci_dev *bridge_dev;
911 struct intel_ring_buffer ring[I915_NUM_RINGS];
912 uint32_t last_seqno, next_seqno;
913
914 drm_dma_handle_t *status_page_dmah;
915 struct resource mch_res;
916
917 atomic_t irq_received;
918
919 /* protects the irq masks */
920 spinlock_t irq_lock;
921
922 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
923 struct pm_qos_request pm_qos;
924
925 /* DPIO indirect register protection */
926 struct mutex dpio_lock;
927
928 /** Cached value of IMR to avoid reads in updating the bitfield */
929 u32 irq_mask;
930 u32 gt_irq_mask;
931
932 struct work_struct hotplug_work;
933 bool enable_hotplug_processing;
934
935 int num_pch_pll;
936 int num_plane;
937
938 unsigned long cfb_size;
939 unsigned int cfb_fb;
940 enum plane cfb_plane;
941 int cfb_y;
942 struct intel_fbc_work *fbc_work;
943
944 struct intel_opregion opregion;
945
946 /* overlay */
947 struct intel_overlay *overlay;
948 unsigned int sprite_scaling_enabled;
949
950 /* backlight */
951 struct {
952 int level;
953 bool enabled;
954 struct backlight_device *device;
955 } backlight;
956
957 /* LVDS info */
958 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
959 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
960
961 /* Feature bits from the VBIOS */
962 unsigned int int_tv_support:1;
963 unsigned int lvds_dither:1;
964 unsigned int lvds_vbt:1;
965 unsigned int int_crt_support:1;
966 unsigned int lvds_use_ssc:1;
967 unsigned int display_clock_mode:1;
968 int lvds_ssc_freq;
969 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
970 struct {
971 int rate;
972 int lanes;
973 int preemphasis;
974 int vswing;
975
976 bool initialized;
977 bool support;
978 int bpp;
979 struct edp_power_seq pps;
980 } edp;
981 bool no_aux_handshake;
982
983 int crt_ddc_pin;
984 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
985 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
986 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
987
988 unsigned int fsb_freq, mem_freq, is_ddr3;
989
990 struct workqueue_struct *wq;
991
992 /* Display functions */
993 struct drm_i915_display_funcs display;
994
995 /* PCH chipset type */
996 enum intel_pch pch_type;
997 unsigned short pch_id;
998
999 unsigned long quirks;
1000
1001 enum modeset_restore modeset_restore;
1002 struct mutex modeset_restore_lock;
1003
1004 struct i915_gtt gtt;
1005
1006 struct i915_gem_mm mm;
1007
1008 /* Kernel Modesetting */
1009
1010 struct sdvo_device_mapping sdvo_mappings[2];
1011 /* indicate whether the LVDS_BORDER should be enabled or not */
1012 unsigned int lvds_border_bits;
1013 /* Panel fitter placement and size for Ironlake+ */
1014 u32 pch_pf_pos, pch_pf_size;
1015
1016 struct drm_crtc *plane_to_crtc_mapping[3];
1017 struct drm_crtc *pipe_to_crtc_mapping[3];
1018 wait_queue_head_t pending_flip_queue;
1019
1020 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
1021 struct intel_ddi_plls ddi_plls;
1022
1023 /* Reclocking support */
1024 bool render_reclock_avail;
1025 bool lvds_downclock_avail;
1026 /* indicates the reduced downclock for LVDS*/
1027 int lvds_downclock;
1028 u16 orig_clock;
1029 int child_dev_num;
1030 struct child_device_config *child_dev;
1031
1032 bool mchbar_need_disable;
1033
1034 struct intel_l3_parity l3_parity;
1035
1036 /* gen6+ rps state */
1037 struct intel_gen6_power_mgmt rps;
1038
1039 /* ilk-only ips/rps state. Everything in here is protected by the global
1040 * mchdev_lock in intel_pm.c */
1041 struct intel_ilk_power_mgmt ips;
1042
1043 enum no_fbc_reason no_fbc_reason;
1044
1045 struct drm_mm_node *compressed_fb;
1046 struct drm_mm_node *compressed_llb;
1047
1048 struct i915_gpu_error gpu_error;
1049
1050 /* list of fbdev register on this device */
1051 struct intel_fbdev *fbdev;
1052
1053 /*
1054 * The console may be contended at resume, but we don't
1055 * want it to block on it.
1056 */
1057 struct work_struct console_resume_work;
1058
1059 struct drm_property *broadcast_rgb_property;
1060 struct drm_property *force_audio_property;
1061
1062 bool hw_contexts_disabled;
1063 uint32_t hw_context_size;
1064
1065 u32 fdi_rx_config;
1066
1067 struct i915_suspend_saved_registers regfile;
1068
1069 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1070 * here! */
1071 struct i915_dri1_state dri1;
1072} drm_i915_private_t;
1073
1074/* Iterate over initialised rings */
1075#define for_each_ring(ring__, dev_priv__, i__) \
1076 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1077 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1078
1079enum hdmi_force_audio {
1080 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1081 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1082 HDMI_AUDIO_AUTO, /* trust EDID */
1083 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1084};
1085
1086#define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1087
1088struct drm_i915_gem_object_ops {
1089 /* Interface between the GEM object and its backing storage.
1090 * get_pages() is called once prior to the use of the associated set
1091 * of pages before to binding them into the GTT, and put_pages() is
1092 * called after we no longer need them. As we expect there to be
1093 * associated cost with migrating pages between the backing storage
1094 * and making them available for the GPU (e.g. clflush), we may hold
1095 * onto the pages after they are no longer referenced by the GPU
1096 * in case they may be used again shortly (for example migrating the
1097 * pages to a different memory domain within the GTT). put_pages()
1098 * will therefore most likely be called when the object itself is
1099 * being released or under memory pressure (where we attempt to
1100 * reap pages for the shrinker).
1101 */
1102 int (*get_pages)(struct drm_i915_gem_object *);
1103 void (*put_pages)(struct drm_i915_gem_object *);
1104};
1105
1106struct drm_i915_gem_object {
1107 struct drm_gem_object base;
1108
1109 const struct drm_i915_gem_object_ops *ops;
1110
1111 /** Current space allocated to this object in the GTT, if any. */
1112 struct drm_mm_node *gtt_space;
1113 /** Stolen memory for this object, instead of being backed by shmem. */
1114 struct drm_mm_node *stolen;
1115 struct list_head gtt_list;
1116
1117 /** This object's place on the active/inactive lists */
1118 struct list_head ring_list;
1119 struct list_head mm_list;
1120 /** This object's place in the batchbuffer or on the eviction list */
1121 struct list_head exec_list;
1122
1123 /**
1124 * This is set if the object is on the active lists (has pending
1125 * rendering and so a non-zero seqno), and is not set if it i s on
1126 * inactive (ready to be unbound) list.
1127 */
1128 unsigned int active:1;
1129
1130 /**
1131 * This is set if the object has been written to since last bound
1132 * to the GTT
1133 */
1134 unsigned int dirty:1;
1135
1136 /**
1137 * Fence register bits (if any) for this object. Will be set
1138 * as needed when mapped into the GTT.
1139 * Protected by dev->struct_mutex.
1140 */
1141 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1142
1143 /**
1144 * Advice: are the backing pages purgeable?
1145 */
1146 unsigned int madv:2;
1147
1148 /**
1149 * Current tiling mode for the object.
1150 */
1151 unsigned int tiling_mode:2;
1152 /**
1153 * Whether the tiling parameters for the currently associated fence
1154 * register have changed. Note that for the purposes of tracking
1155 * tiling changes we also treat the unfenced register, the register
1156 * slot that the object occupies whilst it executes a fenced
1157 * command (such as BLT on gen2/3), as a "fence".
1158 */
1159 unsigned int fence_dirty:1;
1160
1161 /** How many users have pinned this object in GTT space. The following
1162 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1163 * (via user_pin_count), execbuffer (objects are not allowed multiple
1164 * times for the same batchbuffer), and the framebuffer code. When
1165 * switching/pageflipping, the framebuffer code has at most two buffers
1166 * pinned per crtc.
1167 *
1168 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1169 * bits with absolutely no headroom. So use 4 bits. */
1170 unsigned int pin_count:4;
1171#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1172
1173 /**
1174 * Is the object at the current location in the gtt mappable and
1175 * fenceable? Used to avoid costly recalculations.
1176 */
1177 unsigned int map_and_fenceable:1;
1178
1179 /**
1180 * Whether the current gtt mapping needs to be mappable (and isn't just
1181 * mappable by accident). Track pin and fault separate for a more
1182 * accurate mappable working set.
1183 */
1184 unsigned int fault_mappable:1;
1185 unsigned int pin_mappable:1;
1186
1187 /*
1188 * Is the GPU currently using a fence to access this buffer,
1189 */
1190 unsigned int pending_fenced_gpu_access:1;
1191 unsigned int fenced_gpu_access:1;
1192
1193 unsigned int cache_level:2;
1194
1195 unsigned int has_aliasing_ppgtt_mapping:1;
1196 unsigned int has_global_gtt_mapping:1;
1197 unsigned int has_dma_mapping:1;
1198
1199 struct sg_table *pages;
1200 int pages_pin_count;
1201
1202 /* prime dma-buf support */
1203 void *dma_buf_vmapping;
1204 int vmapping_count;
1205
1206 /**
1207 * Used for performing relocations during execbuffer insertion.
1208 */
1209 struct hlist_node exec_node;
1210 unsigned long exec_handle;
1211 struct drm_i915_gem_exec_object2 *exec_entry;
1212
1213 /**
1214 * Current offset of the object in GTT space.
1215 *
1216 * This is the same as gtt_space->start
1217 */
1218 uint32_t gtt_offset;
1219
1220 struct intel_ring_buffer *ring;
1221
1222 /** Breadcrumb of last rendering to the buffer. */
1223 uint32_t last_read_seqno;
1224 uint32_t last_write_seqno;
1225 /** Breadcrumb of last fenced GPU access to the buffer. */
1226 uint32_t last_fenced_seqno;
1227
1228 /** Current tiling stride for the object, if it's tiled. */
1229 uint32_t stride;
1230
1231 /** Record of address bit 17 of each page at last unbind. */
1232 unsigned long *bit_17;
1233
1234 /** User space pin count and filp owning the pin */
1235 uint32_t user_pin_count;
1236 struct drm_file *pin_filp;
1237
1238 /** for phy allocated objects */
1239 struct drm_i915_gem_phys_object *phys_obj;
1240};
1241#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1242
1243#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1244
1245/**
1246 * Request queue structure.
1247 *
1248 * The request queue allows us to note sequence numbers that have been emitted
1249 * and may be associated with active buffers to be retired.
1250 *
1251 * By keeping this list, we can avoid having to do questionable
1252 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1253 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1254 */
1255struct drm_i915_gem_request {
1256 /** On Which ring this request was generated */
1257 struct intel_ring_buffer *ring;
1258
1259 /** GEM sequence number associated with this request. */
1260 uint32_t seqno;
1261
1262 /** Postion in the ringbuffer of the end of the request */
1263 u32 tail;
1264
1265 /** Time at which this request was emitted, in jiffies. */
1266 unsigned long emitted_jiffies;
1267
1268 /** global list entry for this request */
1269 struct list_head list;
1270
1271 struct drm_i915_file_private *file_priv;
1272 /** file_priv list entry for this request */
1273 struct list_head client_list;
1274};
1275
1276struct drm_i915_file_private {
1277 struct {
1278 spinlock_t lock;
1279 struct list_head request_list;
1280 } mm;
1281 struct idr context_idr;
1282};
1283
1284#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1285
1286#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1287#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1288#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1289#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1290#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1291#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1292#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1293#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1294#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1295#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1296#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1297#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1298#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1299#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1300#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1301#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1302#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1303#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1304#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1305#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1306 (dev)->pci_device == 0x0152 || \
1307 (dev)->pci_device == 0x015a)
1308#define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1309 (dev)->pci_device == 0x0106 || \
1310 (dev)->pci_device == 0x010A)
1311#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1312#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1313#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1314#define IS_ULT(dev) (IS_HASWELL(dev) && \
1315 ((dev)->pci_device & 0xFF00) == 0x0A00)
1316
1317/*
1318 * The genX designation typically refers to the render engine, so render
1319 * capability related checks should use IS_GEN, while display and other checks
1320 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1321 * chips, etc.).
1322 */
1323#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1324#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1325#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1326#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1327#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1328#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1329
1330#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1331#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1332#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1333#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1334
1335#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1336#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1337
1338#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1339#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1340
1341/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1342#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1343
1344/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1345 * rows, which changed the alignment requirements and fence programming.
1346 */
1347#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1348 IS_I915GM(dev)))
1349#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1350#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1351#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1352#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1353#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1354#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1355/* dsparb controlled by hw only */
1356#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1357
1358#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1359#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1360#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1361
1362#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1363
1364#define HAS_DDI(dev) (IS_HASWELL(dev))
1365#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1366
1367#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1368#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1369#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1370#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1371#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1372#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1373
1374#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1375#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1376#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1377#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1378#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1379#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1380
1381#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1382
1383#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1384
1385#define GT_FREQUENCY_MULTIPLIER 50
1386
1387#include "i915_trace.h"
1388
1389/**
1390 * RC6 is a special power stage which allows the GPU to enter an very
1391 * low-voltage mode when idle, using down to 0V while at this stage. This
1392 * stage is entered automatically when the GPU is idle when RC6 support is
1393 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1394 *
1395 * There are different RC6 modes available in Intel GPU, which differentiate
1396 * among each other with the latency required to enter and leave RC6 and
1397 * voltage consumed by the GPU in different states.
1398 *
1399 * The combination of the following flags define which states GPU is allowed
1400 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1401 * RC6pp is deepest RC6. Their support by hardware varies according to the
1402 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1403 * which brings the most power savings; deeper states save more power, but
1404 * require higher latency to switch to and wake up.
1405 */
1406#define INTEL_RC6_ENABLE (1<<0)
1407#define INTEL_RC6p_ENABLE (1<<1)
1408#define INTEL_RC6pp_ENABLE (1<<2)
1409
1410extern struct drm_ioctl_desc i915_ioctls[];
1411extern int i915_max_ioctl;
1412extern unsigned int i915_fbpercrtc __always_unused;
1413extern int i915_panel_ignore_lid __read_mostly;
1414extern unsigned int i915_powersave __read_mostly;
1415extern int i915_semaphores __read_mostly;
1416extern unsigned int i915_lvds_downclock __read_mostly;
1417extern int i915_lvds_channel_mode __read_mostly;
1418extern int i915_panel_use_ssc __read_mostly;
1419extern int i915_vbt_sdvo_panel_type __read_mostly;
1420extern int i915_enable_rc6 __read_mostly;
1421extern int i915_enable_fbc __read_mostly;
1422extern bool i915_enable_hangcheck __read_mostly;
1423extern int i915_enable_ppgtt __read_mostly;
1424extern unsigned int i915_preliminary_hw_support __read_mostly;
1425extern int i915_disable_power_well __read_mostly;
1426
1427extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1428extern int i915_resume(struct drm_device *dev);
1429extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1430extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1431
1432 /* i915_dma.c */
1433void i915_update_dri1_breadcrumb(struct drm_device *dev);
1434extern void i915_kernel_lost_context(struct drm_device * dev);
1435extern int i915_driver_load(struct drm_device *, unsigned long flags);
1436extern int i915_driver_unload(struct drm_device *);
1437extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1438extern void i915_driver_lastclose(struct drm_device * dev);
1439extern void i915_driver_preclose(struct drm_device *dev,
1440 struct drm_file *file_priv);
1441extern void i915_driver_postclose(struct drm_device *dev,
1442 struct drm_file *file_priv);
1443extern int i915_driver_device_is_agp(struct drm_device * dev);
1444#ifdef CONFIG_COMPAT
1445extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1446 unsigned long arg);
1447#endif
1448extern int i915_emit_box(struct drm_device *dev,
1449 struct drm_clip_rect *box,
1450 int DR1, int DR4);
1451extern int intel_gpu_reset(struct drm_device *dev);
1452extern int i915_reset(struct drm_device *dev);
1453extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1454extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1455extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1456extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1457
1458extern void intel_console_resume(struct work_struct *work);
1459
1460/* i915_irq.c */
1461void i915_hangcheck_elapsed(unsigned long data);
1462void i915_handle_error(struct drm_device *dev, bool wedged);
1463
1464extern void intel_irq_init(struct drm_device *dev);
1465extern void intel_hpd_init(struct drm_device *dev);
1466extern void intel_gt_init(struct drm_device *dev);
1467extern void intel_gt_reset(struct drm_device *dev);
1468
1469void i915_error_state_free(struct kref *error_ref);
1470
1471void
1472i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1473
1474void
1475i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1476
1477void intel_enable_asle(struct drm_device *dev);
1478
1479#ifdef CONFIG_DEBUG_FS
1480extern void i915_destroy_error_state(struct drm_device *dev);
1481#else
1482#define i915_destroy_error_state(x)
1483#endif
1484
1485
1486/* i915_gem.c */
1487int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1488 struct drm_file *file_priv);
1489int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1490 struct drm_file *file_priv);
1491int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1492 struct drm_file *file_priv);
1493int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1494 struct drm_file *file_priv);
1495int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1496 struct drm_file *file_priv);
1497int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1498 struct drm_file *file_priv);
1499int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file_priv);
1501int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1502 struct drm_file *file_priv);
1503int i915_gem_execbuffer(struct drm_device *dev, void *data,
1504 struct drm_file *file_priv);
1505int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1506 struct drm_file *file_priv);
1507int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1508 struct drm_file *file_priv);
1509int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1510 struct drm_file *file_priv);
1511int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *file_priv);
1513int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1514 struct drm_file *file);
1515int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1516 struct drm_file *file);
1517int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1518 struct drm_file *file_priv);
1519int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1520 struct drm_file *file_priv);
1521int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1522 struct drm_file *file_priv);
1523int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1524 struct drm_file *file_priv);
1525int i915_gem_set_tiling(struct drm_device *dev, void *data,
1526 struct drm_file *file_priv);
1527int i915_gem_get_tiling(struct drm_device *dev, void *data,
1528 struct drm_file *file_priv);
1529int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1530 struct drm_file *file_priv);
1531int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1532 struct drm_file *file_priv);
1533void i915_gem_load(struct drm_device *dev);
1534void *i915_gem_object_alloc(struct drm_device *dev);
1535void i915_gem_object_free(struct drm_i915_gem_object *obj);
1536int i915_gem_init_object(struct drm_gem_object *obj);
1537void i915_gem_object_init(struct drm_i915_gem_object *obj,
1538 const struct drm_i915_gem_object_ops *ops);
1539struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1540 size_t size);
1541void i915_gem_free_object(struct drm_gem_object *obj);
1542
1543int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1544 uint32_t alignment,
1545 bool map_and_fenceable,
1546 bool nonblocking);
1547void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1548int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1549int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1550void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1551void i915_gem_lastclose(struct drm_device *dev);
1552
1553int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1554static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1555{
1556 struct sg_page_iter sg_iter;
1557
1558 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1559 return sg_page_iter_page(&sg_iter);
1560
1561 return NULL;
1562}
1563static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1564{
1565 BUG_ON(obj->pages == NULL);
1566 obj->pages_pin_count++;
1567}
1568static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1569{
1570 BUG_ON(obj->pages_pin_count == 0);
1571 obj->pages_pin_count--;
1572}
1573
1574int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1575int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1576 struct intel_ring_buffer *to);
1577void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1578 struct intel_ring_buffer *ring);
1579
1580int i915_gem_dumb_create(struct drm_file *file_priv,
1581 struct drm_device *dev,
1582 struct drm_mode_create_dumb *args);
1583int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1584 uint32_t handle, uint64_t *offset);
1585int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1586 uint32_t handle);
1587/**
1588 * Returns true if seq1 is later than seq2.
1589 */
1590static inline bool
1591i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1592{
1593 return (int32_t)(seq1 - seq2) >= 0;
1594}
1595
1596int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1597int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1598int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1599int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1600
1601static inline bool
1602i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1603{
1604 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1605 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1606 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1607 return true;
1608 } else
1609 return false;
1610}
1611
1612static inline void
1613i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1614{
1615 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1616 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1617 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1618 }
1619}
1620
1621void i915_gem_retire_requests(struct drm_device *dev);
1622void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1623int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1624 bool interruptible);
1625static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1626{
1627 return unlikely(atomic_read(&error->reset_counter)
1628 & I915_RESET_IN_PROGRESS_FLAG);
1629}
1630
1631static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1632{
1633 return atomic_read(&error->reset_counter) == I915_WEDGED;
1634}
1635
1636void i915_gem_reset(struct drm_device *dev);
1637void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1638int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1639 uint32_t read_domains,
1640 uint32_t write_domain);
1641int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1642int __must_check i915_gem_init(struct drm_device *dev);
1643int __must_check i915_gem_init_hw(struct drm_device *dev);
1644void i915_gem_l3_remap(struct drm_device *dev);
1645void i915_gem_init_swizzling(struct drm_device *dev);
1646void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1647int __must_check i915_gpu_idle(struct drm_device *dev);
1648int __must_check i915_gem_idle(struct drm_device *dev);
1649int i915_add_request(struct intel_ring_buffer *ring,
1650 struct drm_file *file,
1651 u32 *seqno);
1652int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1653 uint32_t seqno);
1654int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1655int __must_check
1656i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1657 bool write);
1658int __must_check
1659i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1660int __must_check
1661i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1662 u32 alignment,
1663 struct intel_ring_buffer *pipelined);
1664int i915_gem_attach_phys_object(struct drm_device *dev,
1665 struct drm_i915_gem_object *obj,
1666 int id,
1667 int align);
1668void i915_gem_detach_phys_object(struct drm_device *dev,
1669 struct drm_i915_gem_object *obj);
1670void i915_gem_free_all_phys_object(struct drm_device *dev);
1671void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1672
1673uint32_t
1674i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1675uint32_t
1676i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1677 int tiling_mode, bool fenced);
1678
1679int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1680 enum i915_cache_level cache_level);
1681
1682struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1683 struct dma_buf *dma_buf);
1684
1685struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1686 struct drm_gem_object *gem_obj, int flags);
1687
1688/* i915_gem_context.c */
1689void i915_gem_context_init(struct drm_device *dev);
1690void i915_gem_context_fini(struct drm_device *dev);
1691void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1692int i915_switch_context(struct intel_ring_buffer *ring,
1693 struct drm_file *file, int to_id);
1694int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1695 struct drm_file *file);
1696int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1697 struct drm_file *file);
1698
1699/* i915_gem_gtt.c */
1700void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1701void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1702 struct drm_i915_gem_object *obj,
1703 enum i915_cache_level cache_level);
1704void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1705 struct drm_i915_gem_object *obj);
1706
1707void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1708int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1709void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1710 enum i915_cache_level cache_level);
1711void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1712void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1713void i915_gem_init_global_gtt(struct drm_device *dev);
1714void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1715 unsigned long mappable_end, unsigned long end);
1716int i915_gem_gtt_init(struct drm_device *dev);
1717static inline void i915_gem_chipset_flush(struct drm_device *dev)
1718{
1719 if (INTEL_INFO(dev)->gen < 6)
1720 intel_gtt_chipset_flush();
1721}
1722
1723
1724/* i915_gem_evict.c */
1725int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1726 unsigned alignment,
1727 unsigned cache_level,
1728 bool mappable,
1729 bool nonblock);
1730int i915_gem_evict_everything(struct drm_device *dev);
1731
1732/* i915_gem_stolen.c */
1733int i915_gem_init_stolen(struct drm_device *dev);
1734int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1735void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1736void i915_gem_cleanup_stolen(struct drm_device *dev);
1737struct drm_i915_gem_object *
1738i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1739struct drm_i915_gem_object *
1740i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1741 u32 stolen_offset,
1742 u32 gtt_offset,
1743 u32 size);
1744void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1745
1746/* i915_gem_tiling.c */
1747inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1748{
1749 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1750
1751 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1752 obj->tiling_mode != I915_TILING_NONE;
1753}
1754
1755void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1756void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1757void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1758
1759/* i915_gem_debug.c */
1760void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1761 const char *where, uint32_t mark);
1762#if WATCH_LISTS
1763int i915_verify_lists(struct drm_device *dev);
1764#else
1765#define i915_verify_lists(dev) 0
1766#endif
1767void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1768 int handle);
1769void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1770 const char *where, uint32_t mark);
1771
1772/* i915_debugfs.c */
1773int i915_debugfs_init(struct drm_minor *minor);
1774void i915_debugfs_cleanup(struct drm_minor *minor);
1775
1776/* i915_suspend.c */
1777extern int i915_save_state(struct drm_device *dev);
1778extern int i915_restore_state(struct drm_device *dev);
1779
1780/* i915_ums.c */
1781void i915_save_display_reg(struct drm_device *dev);
1782void i915_restore_display_reg(struct drm_device *dev);
1783
1784/* i915_sysfs.c */
1785void i915_setup_sysfs(struct drm_device *dev_priv);
1786void i915_teardown_sysfs(struct drm_device *dev_priv);
1787
1788/* intel_i2c.c */
1789extern int intel_setup_gmbus(struct drm_device *dev);
1790extern void intel_teardown_gmbus(struct drm_device *dev);
1791extern inline bool intel_gmbus_is_port_valid(unsigned port)
1792{
1793 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1794}
1795
1796extern struct i2c_adapter *intel_gmbus_get_adapter(
1797 struct drm_i915_private *dev_priv, unsigned port);
1798extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1799extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1800extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1801{
1802 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1803}
1804extern void intel_i2c_reset(struct drm_device *dev);
1805
1806/* intel_opregion.c */
1807extern int intel_opregion_setup(struct drm_device *dev);
1808#ifdef CONFIG_ACPI
1809extern void intel_opregion_init(struct drm_device *dev);
1810extern void intel_opregion_fini(struct drm_device *dev);
1811extern void intel_opregion_asle_intr(struct drm_device *dev);
1812extern void intel_opregion_gse_intr(struct drm_device *dev);
1813extern void intel_opregion_enable_asle(struct drm_device *dev);
1814#else
1815static inline void intel_opregion_init(struct drm_device *dev) { return; }
1816static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1817static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1818static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1819static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1820#endif
1821
1822/* intel_acpi.c */
1823#ifdef CONFIG_ACPI
1824extern void intel_register_dsm_handler(void);
1825extern void intel_unregister_dsm_handler(void);
1826#else
1827static inline void intel_register_dsm_handler(void) { return; }
1828static inline void intel_unregister_dsm_handler(void) { return; }
1829#endif /* CONFIG_ACPI */
1830
1831/* modesetting */
1832extern void intel_modeset_init_hw(struct drm_device *dev);
1833extern void intel_modeset_init(struct drm_device *dev);
1834extern void intel_modeset_gem_init(struct drm_device *dev);
1835extern void intel_modeset_cleanup(struct drm_device *dev);
1836extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1837extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1838 bool force_restore);
1839extern void i915_redisable_vga(struct drm_device *dev);
1840extern bool intel_fbc_enabled(struct drm_device *dev);
1841extern void intel_disable_fbc(struct drm_device *dev);
1842extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1843extern void intel_init_pch_refclk(struct drm_device *dev);
1844extern void gen6_set_rps(struct drm_device *dev, u8 val);
1845extern void intel_detect_pch(struct drm_device *dev);
1846extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1847extern int intel_enable_rc6(const struct drm_device *dev);
1848
1849extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1850int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *file);
1852
1853/* overlay */
1854#ifdef CONFIG_DEBUG_FS
1855extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1856extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1857
1858extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1859extern void intel_display_print_error_state(struct seq_file *m,
1860 struct drm_device *dev,
1861 struct intel_display_error_state *error);
1862#endif
1863
1864/* On SNB platform, before reading ring registers forcewake bit
1865 * must be set to prevent GT core from power down and stale values being
1866 * returned.
1867 */
1868void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1869void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1870int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1871
1872int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1873int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1874int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
1875int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1876
1877#define __i915_read(x, y) \
1878 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1879
1880__i915_read(8, b)
1881__i915_read(16, w)
1882__i915_read(32, l)
1883__i915_read(64, q)
1884#undef __i915_read
1885
1886#define __i915_write(x, y) \
1887 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1888
1889__i915_write(8, b)
1890__i915_write(16, w)
1891__i915_write(32, l)
1892__i915_write(64, q)
1893#undef __i915_write
1894
1895#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1896#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1897
1898#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1899#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1900#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1901#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1902
1903#define I915_READ(reg) i915_read32(dev_priv, (reg))
1904#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1905#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1906#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1907
1908#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1909#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1910
1911#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1912#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1913
1914/* "Broadcast RGB" property */
1915#define INTEL_BROADCAST_RGB_AUTO 0
1916#define INTEL_BROADCAST_RGB_FULL 1
1917#define INTEL_BROADCAST_RGB_LIMITED 2
1918
1919static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1920{
1921 if (HAS_PCH_SPLIT(dev))
1922 return CPU_VGACNTRL;
1923 else if (IS_VALLEYVIEW(dev))
1924 return VLV_VGACNTRL;
1925 else
1926 return VGACNTRL;
1927}
1928
1929static inline void __user *to_user_ptr(u64 address)
1930{
1931 return (void __user *)(uintptr_t)address;
1932}
1933
1934#endif
Linux kernel - Deliverables
This page took 0.029757 seconds and 5 git commands to generate.