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drm/i915: Remove the global irq wait queue
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "i915_trace.h"
36#include "intel_ringbuffer.h"
37#include <linux/io-mapping.h>
38#include <linux/i2c.h>
39#include <drm/intel-gtt.h>
40
41/* General customization:
42 */
43
44#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45
46#define DRIVER_NAME "i915"
47#define DRIVER_DESC "Intel Graphics"
48#define DRIVER_DATE "20080730"
49
50enum pipe {
51 PIPE_A = 0,
52 PIPE_B,
53};
54
55enum plane {
56 PLANE_A = 0,
57 PLANE_B,
58};
59
60#define I915_NUM_PIPE 2
61
62#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
63
64/* Interface history:
65 *
66 * 1.1: Original.
67 * 1.2: Add Power Management
68 * 1.3: Add vblank support
69 * 1.4: Fix cmdbuffer path, add heap destroy
70 * 1.5: Add vblank pipe configuration
71 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
72 * - Support vertical blank on secondary display pipe
73 */
74#define DRIVER_MAJOR 1
75#define DRIVER_MINOR 6
76#define DRIVER_PATCHLEVEL 0
77
78#define WATCH_COHERENCY 0
79#define WATCH_EXEC 0
80#define WATCH_RELOC 0
81#define WATCH_LISTS 0
82#define WATCH_PWRITE 0
83
84#define I915_GEM_PHYS_CURSOR_0 1
85#define I915_GEM_PHYS_CURSOR_1 2
86#define I915_GEM_PHYS_OVERLAY_REGS 3
87#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88
89struct drm_i915_gem_phys_object {
90 int id;
91 struct page **page_list;
92 drm_dma_handle_t *handle;
93 struct drm_gem_object *cur_obj;
94};
95
96struct mem_block {
97 struct mem_block *next;
98 struct mem_block *prev;
99 int start;
100 int size;
101 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
102};
103
104struct opregion_header;
105struct opregion_acpi;
106struct opregion_swsci;
107struct opregion_asle;
108
109struct intel_opregion {
110 struct opregion_header *header;
111 struct opregion_acpi *acpi;
112 struct opregion_swsci *swsci;
113 struct opregion_asle *asle;
114 void *vbt;
115};
116#define OPREGION_SIZE (8*1024)
117
118struct intel_overlay;
119struct intel_overlay_error_state;
120
121struct drm_i915_master_private {
122 drm_local_map_t *sarea;
123 struct _drm_i915_sarea *sarea_priv;
124};
125#define I915_FENCE_REG_NONE -1
126
127struct drm_i915_fence_reg {
128 struct drm_gem_object *obj;
129 struct list_head lru_list;
130 bool gpu;
131};
132
133struct sdvo_device_mapping {
134 u8 initialized;
135 u8 dvo_port;
136 u8 slave_addr;
137 u8 dvo_wiring;
138 u8 i2c_pin;
139 u8 i2c_speed;
140 u8 ddc_pin;
141};
142
143struct drm_i915_error_state {
144 u32 eir;
145 u32 pgtbl_er;
146 u32 pipeastat;
147 u32 pipebstat;
148 u32 ipeir;
149 u32 ipehr;
150 u32 instdone;
151 u32 acthd;
152 u32 error; /* gen6+ */
153 u32 bcs_acthd; /* gen6+ blt engine */
154 u32 bcs_ipehr;
155 u32 bcs_ipeir;
156 u32 bcs_instdone;
157 u32 bcs_seqno;
158 u32 vcs_acthd; /* gen6+ bsd engine */
159 u32 vcs_ipehr;
160 u32 vcs_ipeir;
161 u32 vcs_instdone;
162 u32 vcs_seqno;
163 u32 instpm;
164 u32 instps;
165 u32 instdone1;
166 u32 seqno;
167 u64 bbaddr;
168 struct timeval time;
169 struct drm_i915_error_object {
170 int page_count;
171 u32 gtt_offset;
172 u32 *pages[0];
173 } *ringbuffer, *batchbuffer[2];
174 struct drm_i915_error_buffer {
175 size_t size;
176 u32 name;
177 u32 seqno;
178 u32 gtt_offset;
179 u32 read_domains;
180 u32 write_domain;
181 u32 fence_reg;
182 s32 pinned:2;
183 u32 tiling:2;
184 u32 dirty:1;
185 u32 purgeable:1;
186 u32 ring:4;
187 } *active_bo;
188 u32 active_bo_count;
189 struct intel_overlay_error_state *overlay;
190};
191
192struct drm_i915_display_funcs {
193 void (*dpms)(struct drm_crtc *crtc, int mode);
194 bool (*fbc_enabled)(struct drm_device *dev);
195 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
196 void (*disable_fbc)(struct drm_device *dev);
197 int (*get_display_clock_speed)(struct drm_device *dev);
198 int (*get_fifo_size)(struct drm_device *dev, int plane);
199 void (*update_wm)(struct drm_device *dev, int planea_clock,
200 int planeb_clock, int sr_hdisplay, int sr_htotal,
201 int pixel_size);
202 /* clock updates for mode set */
203 /* cursor updates */
204 /* render clock increase/decrease */
205 /* display clock increase/decrease */
206 /* pll clock increase/decrease */
207 /* clock gating init */
208};
209
210struct intel_device_info {
211 u8 gen;
212 u8 is_mobile : 1;
213 u8 is_i85x : 1;
214 u8 is_i915g : 1;
215 u8 is_i945gm : 1;
216 u8 is_g33 : 1;
217 u8 need_gfx_hws : 1;
218 u8 is_g4x : 1;
219 u8 is_pineview : 1;
220 u8 is_broadwater : 1;
221 u8 is_crestline : 1;
222 u8 has_fbc : 1;
223 u8 has_rc6 : 1;
224 u8 has_pipe_cxsr : 1;
225 u8 has_hotplug : 1;
226 u8 cursor_needs_physical : 1;
227 u8 has_overlay : 1;
228 u8 overlay_needs_physical : 1;
229 u8 supports_tv : 1;
230 u8 has_bsd_ring : 1;
231 u8 has_blt_ring : 1;
232};
233
234enum no_fbc_reason {
235 FBC_NO_OUTPUT, /* no outputs enabled to compress */
236 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
237 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
238 FBC_MODE_TOO_LARGE, /* mode too large for compression */
239 FBC_BAD_PLANE, /* fbc not supported on plane */
240 FBC_NOT_TILED, /* buffer not tiled */
241 FBC_MULTIPLE_PIPES, /* more than one pipe active */
242};
243
244enum intel_pch {
245 PCH_IBX, /* Ibexpeak PCH */
246 PCH_CPT, /* Cougarpoint PCH */
247};
248
249#define QUIRK_PIPEA_FORCE (1<<0)
250
251struct intel_fbdev;
252
253typedef struct drm_i915_private {
254 struct drm_device *dev;
255
256 const struct intel_device_info *info;
257
258 int has_gem;
259
260 void __iomem *regs;
261
262 struct intel_gmbus {
263 struct i2c_adapter adapter;
264 struct i2c_adapter *force_bit;
265 u32 reg0;
266 } *gmbus;
267
268 struct pci_dev *bridge_dev;
269 struct intel_ring_buffer render_ring;
270 struct intel_ring_buffer bsd_ring;
271 struct intel_ring_buffer blt_ring;
272 uint32_t next_seqno;
273
274 drm_dma_handle_t *status_page_dmah;
275 void *seqno_page;
276 dma_addr_t dma_status_page;
277 uint32_t counter;
278 unsigned int seqno_gfx_addr;
279 drm_local_map_t hws_map;
280 struct drm_gem_object *seqno_obj;
281 struct drm_gem_object *pwrctx;
282 struct drm_gem_object *renderctx;
283
284 struct resource mch_res;
285
286 unsigned int cpp;
287 int back_offset;
288 int front_offset;
289 int current_page;
290 int page_flipping;
291
292 atomic_t irq_received;
293 /** Protects user_irq_refcount and irq_mask_reg */
294 spinlock_t user_irq_lock;
295 u32 trace_irq_seqno;
296 /** Cached value of IMR to avoid reads in updating the bitfield */
297 u32 irq_mask_reg;
298 u32 pipestat[2];
299 /** splitted irq regs for graphics and display engine on Ironlake,
300 irq_mask_reg is still used for display irq. */
301 u32 gt_irq_mask_reg;
302 u32 gt_irq_enable_reg;
303 u32 de_irq_enable_reg;
304 u32 pch_irq_mask_reg;
305 u32 pch_irq_enable_reg;
306
307 u32 hotplug_supported_mask;
308 struct work_struct hotplug_work;
309
310 int tex_lru_log_granularity;
311 int allow_batchbuffer;
312 struct mem_block *agp_heap;
313 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
314 int vblank_pipe;
315 int num_pipe;
316
317 /* For hangcheck timer */
318#define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
319 struct timer_list hangcheck_timer;
320 int hangcheck_count;
321 uint32_t last_acthd;
322 uint32_t last_instdone;
323 uint32_t last_instdone1;
324
325 unsigned long cfb_size;
326 unsigned long cfb_pitch;
327 unsigned long cfb_offset;
328 int cfb_fence;
329 int cfb_plane;
330 int cfb_y;
331
332 int irq_enabled;
333
334 struct intel_opregion opregion;
335
336 /* overlay */
337 struct intel_overlay *overlay;
338
339 /* LVDS info */
340 int backlight_level; /* restore backlight to this value */
341 struct drm_display_mode *panel_fixed_mode;
342 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
343 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
344
345 /* Feature bits from the VBIOS */
346 unsigned int int_tv_support:1;
347 unsigned int lvds_dither:1;
348 unsigned int lvds_vbt:1;
349 unsigned int int_crt_support:1;
350 unsigned int lvds_use_ssc:1;
351 int lvds_ssc_freq;
352 struct {
353 int rate;
354 int lanes;
355 int preemphasis;
356 int vswing;
357
358 bool initialized;
359 bool support;
360 int bpp;
361 struct edp_power_seq pps;
362 } edp;
363 bool no_aux_handshake;
364
365 struct notifier_block lid_notifier;
366
367 int crt_ddc_pin;
368 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
369 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
370 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
371
372 unsigned int fsb_freq, mem_freq, is_ddr3;
373
374 spinlock_t error_lock;
375 struct drm_i915_error_state *first_error;
376 struct work_struct error_work;
377 struct completion error_completion;
378 struct workqueue_struct *wq;
379
380 /* Display functions */
381 struct drm_i915_display_funcs display;
382
383 /* PCH chipset type */
384 enum intel_pch pch_type;
385
386 unsigned long quirks;
387
388 /* Register state */
389 bool modeset_on_lid;
390 u8 saveLBB;
391 u32 saveDSPACNTR;
392 u32 saveDSPBCNTR;
393 u32 saveDSPARB;
394 u32 saveHWS;
395 u32 savePIPEACONF;
396 u32 savePIPEBCONF;
397 u32 savePIPEASRC;
398 u32 savePIPEBSRC;
399 u32 saveFPA0;
400 u32 saveFPA1;
401 u32 saveDPLL_A;
402 u32 saveDPLL_A_MD;
403 u32 saveHTOTAL_A;
404 u32 saveHBLANK_A;
405 u32 saveHSYNC_A;
406 u32 saveVTOTAL_A;
407 u32 saveVBLANK_A;
408 u32 saveVSYNC_A;
409 u32 saveBCLRPAT_A;
410 u32 saveTRANSACONF;
411 u32 saveTRANS_HTOTAL_A;
412 u32 saveTRANS_HBLANK_A;
413 u32 saveTRANS_HSYNC_A;
414 u32 saveTRANS_VTOTAL_A;
415 u32 saveTRANS_VBLANK_A;
416 u32 saveTRANS_VSYNC_A;
417 u32 savePIPEASTAT;
418 u32 saveDSPASTRIDE;
419 u32 saveDSPASIZE;
420 u32 saveDSPAPOS;
421 u32 saveDSPAADDR;
422 u32 saveDSPASURF;
423 u32 saveDSPATILEOFF;
424 u32 savePFIT_PGM_RATIOS;
425 u32 saveBLC_HIST_CTL;
426 u32 saveBLC_PWM_CTL;
427 u32 saveBLC_PWM_CTL2;
428 u32 saveBLC_CPU_PWM_CTL;
429 u32 saveBLC_CPU_PWM_CTL2;
430 u32 saveFPB0;
431 u32 saveFPB1;
432 u32 saveDPLL_B;
433 u32 saveDPLL_B_MD;
434 u32 saveHTOTAL_B;
435 u32 saveHBLANK_B;
436 u32 saveHSYNC_B;
437 u32 saveVTOTAL_B;
438 u32 saveVBLANK_B;
439 u32 saveVSYNC_B;
440 u32 saveBCLRPAT_B;
441 u32 saveTRANSBCONF;
442 u32 saveTRANS_HTOTAL_B;
443 u32 saveTRANS_HBLANK_B;
444 u32 saveTRANS_HSYNC_B;
445 u32 saveTRANS_VTOTAL_B;
446 u32 saveTRANS_VBLANK_B;
447 u32 saveTRANS_VSYNC_B;
448 u32 savePIPEBSTAT;
449 u32 saveDSPBSTRIDE;
450 u32 saveDSPBSIZE;
451 u32 saveDSPBPOS;
452 u32 saveDSPBADDR;
453 u32 saveDSPBSURF;
454 u32 saveDSPBTILEOFF;
455 u32 saveVGA0;
456 u32 saveVGA1;
457 u32 saveVGA_PD;
458 u32 saveVGACNTRL;
459 u32 saveADPA;
460 u32 saveLVDS;
461 u32 savePP_ON_DELAYS;
462 u32 savePP_OFF_DELAYS;
463 u32 saveDVOA;
464 u32 saveDVOB;
465 u32 saveDVOC;
466 u32 savePP_ON;
467 u32 savePP_OFF;
468 u32 savePP_CONTROL;
469 u32 savePP_DIVISOR;
470 u32 savePFIT_CONTROL;
471 u32 save_palette_a[256];
472 u32 save_palette_b[256];
473 u32 saveDPFC_CB_BASE;
474 u32 saveFBC_CFB_BASE;
475 u32 saveFBC_LL_BASE;
476 u32 saveFBC_CONTROL;
477 u32 saveFBC_CONTROL2;
478 u32 saveIER;
479 u32 saveIIR;
480 u32 saveIMR;
481 u32 saveDEIER;
482 u32 saveDEIMR;
483 u32 saveGTIER;
484 u32 saveGTIMR;
485 u32 saveFDI_RXA_IMR;
486 u32 saveFDI_RXB_IMR;
487 u32 saveCACHE_MODE_0;
488 u32 saveMI_ARB_STATE;
489 u32 saveSWF0[16];
490 u32 saveSWF1[16];
491 u32 saveSWF2[3];
492 u8 saveMSR;
493 u8 saveSR[8];
494 u8 saveGR[25];
495 u8 saveAR_INDEX;
496 u8 saveAR[21];
497 u8 saveDACMASK;
498 u8 saveCR[37];
499 uint64_t saveFENCE[16];
500 u32 saveCURACNTR;
501 u32 saveCURAPOS;
502 u32 saveCURABASE;
503 u32 saveCURBCNTR;
504 u32 saveCURBPOS;
505 u32 saveCURBBASE;
506 u32 saveCURSIZE;
507 u32 saveDP_B;
508 u32 saveDP_C;
509 u32 saveDP_D;
510 u32 savePIPEA_GMCH_DATA_M;
511 u32 savePIPEB_GMCH_DATA_M;
512 u32 savePIPEA_GMCH_DATA_N;
513 u32 savePIPEB_GMCH_DATA_N;
514 u32 savePIPEA_DP_LINK_M;
515 u32 savePIPEB_DP_LINK_M;
516 u32 savePIPEA_DP_LINK_N;
517 u32 savePIPEB_DP_LINK_N;
518 u32 saveFDI_RXA_CTL;
519 u32 saveFDI_TXA_CTL;
520 u32 saveFDI_RXB_CTL;
521 u32 saveFDI_TXB_CTL;
522 u32 savePFA_CTL_1;
523 u32 savePFB_CTL_1;
524 u32 savePFA_WIN_SZ;
525 u32 savePFB_WIN_SZ;
526 u32 savePFA_WIN_POS;
527 u32 savePFB_WIN_POS;
528 u32 savePCH_DREF_CONTROL;
529 u32 saveDISP_ARB_CTL;
530 u32 savePIPEA_DATA_M1;
531 u32 savePIPEA_DATA_N1;
532 u32 savePIPEA_LINK_M1;
533 u32 savePIPEA_LINK_N1;
534 u32 savePIPEB_DATA_M1;
535 u32 savePIPEB_DATA_N1;
536 u32 savePIPEB_LINK_M1;
537 u32 savePIPEB_LINK_N1;
538 u32 saveMCHBAR_RENDER_STANDBY;
539
540 struct {
541 /** Bridge to intel-gtt-ko */
542 struct intel_gtt *gtt;
543 /** Memory allocator for GTT stolen memory */
544 struct drm_mm vram;
545 /** Memory allocator for GTT */
546 struct drm_mm gtt_space;
547 /** End of mappable part of GTT */
548 unsigned long gtt_mappable_end;
549
550 struct io_mapping *gtt_mapping;
551 int gtt_mtrr;
552
553 struct shrinker inactive_shrinker;
554
555 /**
556 * List of objects currently involved in rendering.
557 *
558 * Includes buffers having the contents of their GPU caches
559 * flushed, not necessarily primitives. last_rendering_seqno
560 * represents when the rendering involved will be completed.
561 *
562 * A reference is held on the buffer while on this list.
563 */
564 struct list_head active_list;
565
566 /**
567 * List of objects which are not in the ringbuffer but which
568 * still have a write_domain which needs to be flushed before
569 * unbinding.
570 *
571 * last_rendering_seqno is 0 while an object is in this list.
572 *
573 * A reference is held on the buffer while on this list.
574 */
575 struct list_head flushing_list;
576
577 /**
578 * LRU list of objects which are not in the ringbuffer and
579 * are ready to unbind, but are still in the GTT.
580 *
581 * last_rendering_seqno is 0 while an object is in this list.
582 *
583 * A reference is not held on the buffer while on this list,
584 * as merely being GTT-bound shouldn't prevent its being
585 * freed, and we'll pull it off the list in the free path.
586 */
587 struct list_head inactive_list;
588
589 /**
590 * LRU list of objects which are not in the ringbuffer but
591 * are still pinned in the GTT.
592 */
593 struct list_head pinned_list;
594
595 /** LRU list of objects with fence regs on them. */
596 struct list_head fence_list;
597
598 /**
599 * List of objects currently pending being freed.
600 *
601 * These objects are no longer in use, but due to a signal
602 * we were prevented from freeing them at the appointed time.
603 */
604 struct list_head deferred_free_list;
605
606 /**
607 * We leave the user IRQ off as much as possible,
608 * but this means that requests will finish and never
609 * be retired once the system goes idle. Set a timer to
610 * fire periodically while the ring is running. When it
611 * fires, go retire requests.
612 */
613 struct delayed_work retire_work;
614
615 /**
616 * Flag if the X Server, and thus DRM, is not currently in
617 * control of the device.
618 *
619 * This is set between LeaveVT and EnterVT. It needs to be
620 * replaced with a semaphore. It also needs to be
621 * transitioned away from for kernel modesetting.
622 */
623 int suspended;
624
625 /**
626 * Flag if the hardware appears to be wedged.
627 *
628 * This is set when attempts to idle the device timeout.
629 * It prevents command submission from occuring and makes
630 * every pending request fail
631 */
632 atomic_t wedged;
633
634 /** Bit 6 swizzling required for X tiling */
635 uint32_t bit_6_swizzle_x;
636 /** Bit 6 swizzling required for Y tiling */
637 uint32_t bit_6_swizzle_y;
638
639 /* storage for physical objects */
640 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
641
642 /* accounting, useful for userland debugging */
643 size_t object_memory;
644 size_t pin_memory;
645 size_t gtt_memory;
646 size_t gtt_mappable_memory;
647 size_t mappable_gtt_used;
648 size_t mappable_gtt_total;
649 size_t gtt_total;
650 u32 object_count;
651 u32 pin_count;
652 u32 gtt_mappable_count;
653 u32 gtt_count;
654 } mm;
655 struct sdvo_device_mapping sdvo_mappings[2];
656 /* indicate whether the LVDS_BORDER should be enabled or not */
657 unsigned int lvds_border_bits;
658 /* Panel fitter placement and size for Ironlake+ */
659 u32 pch_pf_pos, pch_pf_size;
660
661 struct drm_crtc *plane_to_crtc_mapping[2];
662 struct drm_crtc *pipe_to_crtc_mapping[2];
663 wait_queue_head_t pending_flip_queue;
664 bool flip_pending_is_done;
665
666 /* Reclocking support */
667 bool render_reclock_avail;
668 bool lvds_downclock_avail;
669 /* indicates the reduced downclock for LVDS*/
670 int lvds_downclock;
671 struct work_struct idle_work;
672 struct timer_list idle_timer;
673 bool busy;
674 u16 orig_clock;
675 int child_dev_num;
676 struct child_device_config *child_dev;
677 struct drm_connector *int_lvds_connector;
678
679 bool mchbar_need_disable;
680
681 u8 cur_delay;
682 u8 min_delay;
683 u8 max_delay;
684 u8 fmax;
685 u8 fstart;
686
687 u64 last_count1;
688 unsigned long last_time1;
689 u64 last_count2;
690 struct timespec last_time2;
691 unsigned long gfx_power;
692 int c_m;
693 int r_t;
694 u8 corr;
695 spinlock_t *mchdev_lock;
696
697 enum no_fbc_reason no_fbc_reason;
698
699 struct drm_mm_node *compressed_fb;
700 struct drm_mm_node *compressed_llb;
701
702 unsigned long last_gpu_reset;
703
704 /* list of fbdev register on this device */
705 struct intel_fbdev *fbdev;
706} drm_i915_private_t;
707
708/** driver private structure attached to each drm_gem_object */
709struct drm_i915_gem_object {
710 struct drm_gem_object base;
711
712 /** Current space allocated to this object in the GTT, if any. */
713 struct drm_mm_node *gtt_space;
714
715 /** This object's place on the active/flushing/inactive lists */
716 struct list_head ring_list;
717 struct list_head mm_list;
718 /** This object's place on GPU write list */
719 struct list_head gpu_write_list;
720 /** This object's place on eviction list */
721 struct list_head evict_list;
722
723 /**
724 * This is set if the object is on the active or flushing lists
725 * (has pending rendering), and is not set if it's on inactive (ready
726 * to be unbound).
727 */
728 unsigned int active : 1;
729
730 /**
731 * This is set if the object has been written to since last bound
732 * to the GTT
733 */
734 unsigned int dirty : 1;
735
736 /**
737 * Fence register bits (if any) for this object. Will be set
738 * as needed when mapped into the GTT.
739 * Protected by dev->struct_mutex.
740 *
741 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
742 */
743 signed int fence_reg : 5;
744
745 /**
746 * Used for checking the object doesn't appear more than once
747 * in an execbuffer object list.
748 */
749 unsigned int in_execbuffer : 1;
750
751 /**
752 * Advice: are the backing pages purgeable?
753 */
754 unsigned int madv : 2;
755
756 /**
757 * Current tiling mode for the object.
758 */
759 unsigned int tiling_mode : 2;
760
761 /** How many users have pinned this object in GTT space. The following
762 * users can each hold at most one reference: pwrite/pread, pin_ioctl
763 * (via user_pin_count), execbuffer (objects are not allowed multiple
764 * times for the same batchbuffer), and the framebuffer code. When
765 * switching/pageflipping, the framebuffer code has at most two buffers
766 * pinned per crtc.
767 *
768 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
769 * bits with absolutely no headroom. So use 4 bits. */
770 unsigned int pin_count : 4;
771#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
772
773 /**
774 * Is the object at the current location in the gtt mappable and
775 * fenceable? Used to avoid costly recalculations.
776 */
777 unsigned int map_and_fenceable : 1;
778
779 /**
780 * Whether the current gtt mapping needs to be mappable (and isn't just
781 * mappable by accident). Track pin and fault separate for a more
782 * accurate mappable working set.
783 */
784 unsigned int fault_mappable : 1;
785 unsigned int pin_mappable : 1;
786
787 /** AGP memory structure for our GTT binding. */
788 DRM_AGP_MEM *agp_mem;
789
790 struct page **pages;
791
792 /**
793 * Current offset of the object in GTT space.
794 *
795 * This is the same as gtt_space->start
796 */
797 uint32_t gtt_offset;
798
799 /* Which ring is refering to is this object */
800 struct intel_ring_buffer *ring;
801
802 /** Breadcrumb of last rendering to the buffer. */
803 uint32_t last_rendering_seqno;
804
805 /** Current tiling stride for the object, if it's tiled. */
806 uint32_t stride;
807
808 /** Record of address bit 17 of each page at last unbind. */
809 unsigned long *bit_17;
810
811 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
812 uint32_t agp_type;
813
814 /**
815 * If present, while GEM_DOMAIN_CPU is in the read domain this array
816 * flags which individual pages are valid.
817 */
818 uint8_t *page_cpu_valid;
819
820 /** User space pin count and filp owning the pin */
821 uint32_t user_pin_count;
822 struct drm_file *pin_filp;
823
824 /** for phy allocated objects */
825 struct drm_i915_gem_phys_object *phys_obj;
826
827 /**
828 * Number of crtcs where this object is currently the fb, but
829 * will be page flipped away on the next vblank. When it
830 * reaches 0, dev_priv->pending_flip_queue will be woken up.
831 */
832 atomic_t pending_flip;
833};
834
835#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
836
837/**
838 * Request queue structure.
839 *
840 * The request queue allows us to note sequence numbers that have been emitted
841 * and may be associated with active buffers to be retired.
842 *
843 * By keeping this list, we can avoid having to do questionable
844 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
845 * an emission time with seqnos for tracking how far ahead of the GPU we are.
846 */
847struct drm_i915_gem_request {
848 /** On Which ring this request was generated */
849 struct intel_ring_buffer *ring;
850
851 /** GEM sequence number associated with this request. */
852 uint32_t seqno;
853
854 /** Time at which this request was emitted, in jiffies. */
855 unsigned long emitted_jiffies;
856
857 /** global list entry for this request */
858 struct list_head list;
859
860 struct drm_i915_file_private *file_priv;
861 /** file_priv list entry for this request */
862 struct list_head client_list;
863};
864
865struct drm_i915_file_private {
866 struct {
867 struct spinlock lock;
868 struct list_head request_list;
869 } mm;
870};
871
872enum intel_chip_family {
873 CHIP_I8XX = 0x01,
874 CHIP_I9XX = 0x02,
875 CHIP_I915 = 0x04,
876 CHIP_I965 = 0x08,
877};
878
879extern struct drm_ioctl_desc i915_ioctls[];
880extern int i915_max_ioctl;
881extern unsigned int i915_fbpercrtc;
882extern unsigned int i915_powersave;
883extern unsigned int i915_lvds_downclock;
884
885extern int i915_suspend(struct drm_device *dev, pm_message_t state);
886extern int i915_resume(struct drm_device *dev);
887extern void i915_save_display(struct drm_device *dev);
888extern void i915_restore_display(struct drm_device *dev);
889extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
890extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
891
892 /* i915_dma.c */
893extern void i915_kernel_lost_context(struct drm_device * dev);
894extern int i915_driver_load(struct drm_device *, unsigned long flags);
895extern int i915_driver_unload(struct drm_device *);
896extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
897extern void i915_driver_lastclose(struct drm_device * dev);
898extern void i915_driver_preclose(struct drm_device *dev,
899 struct drm_file *file_priv);
900extern void i915_driver_postclose(struct drm_device *dev,
901 struct drm_file *file_priv);
902extern int i915_driver_device_is_agp(struct drm_device * dev);
903extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
904 unsigned long arg);
905extern int i915_emit_box(struct drm_device *dev,
906 struct drm_clip_rect *boxes,
907 int i, int DR1, int DR4);
908extern int i915_reset(struct drm_device *dev, u8 flags);
909extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
910extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
911extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
912extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
913
914
915/* i915_irq.c */
916void i915_hangcheck_elapsed(unsigned long data);
917void i915_handle_error(struct drm_device *dev, bool wedged);
918extern int i915_irq_emit(struct drm_device *dev, void *data,
919 struct drm_file *file_priv);
920extern int i915_irq_wait(struct drm_device *dev, void *data,
921 struct drm_file *file_priv);
922void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
923extern void i915_enable_interrupt (struct drm_device *dev);
924
925extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
926extern void i915_driver_irq_preinstall(struct drm_device * dev);
927extern int i915_driver_irq_postinstall(struct drm_device *dev);
928extern void i915_driver_irq_uninstall(struct drm_device * dev);
929extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
930 struct drm_file *file_priv);
931extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
932 struct drm_file *file_priv);
933extern int i915_enable_vblank(struct drm_device *dev, int crtc);
934extern void i915_disable_vblank(struct drm_device *dev, int crtc);
935extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
936extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
937extern int i915_vblank_swap(struct drm_device *dev, void *data,
938 struct drm_file *file_priv);
939extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
940extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
941extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
942 u32 mask);
943extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
944 u32 mask);
945
946void
947i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
948
949void
950i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
951
952void intel_enable_asle (struct drm_device *dev);
953
954#ifdef CONFIG_DEBUG_FS
955extern void i915_destroy_error_state(struct drm_device *dev);
956#else
957#define i915_destroy_error_state(x)
958#endif
959
960
961/* i915_mem.c */
962extern int i915_mem_alloc(struct drm_device *dev, void *data,
963 struct drm_file *file_priv);
964extern int i915_mem_free(struct drm_device *dev, void *data,
965 struct drm_file *file_priv);
966extern int i915_mem_init_heap(struct drm_device *dev, void *data,
967 struct drm_file *file_priv);
968extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
969 struct drm_file *file_priv);
970extern void i915_mem_takedown(struct mem_block **heap);
971extern void i915_mem_release(struct drm_device * dev,
972 struct drm_file *file_priv, struct mem_block *heap);
973/* i915_gem.c */
974int i915_gem_check_is_wedged(struct drm_device *dev);
975int i915_gem_init_ioctl(struct drm_device *dev, void *data,
976 struct drm_file *file_priv);
977int i915_gem_create_ioctl(struct drm_device *dev, void *data,
978 struct drm_file *file_priv);
979int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
980 struct drm_file *file_priv);
981int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
982 struct drm_file *file_priv);
983int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *file_priv);
985int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
986 struct drm_file *file_priv);
987int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
988 struct drm_file *file_priv);
989int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *file_priv);
991int i915_gem_execbuffer(struct drm_device *dev, void *data,
992 struct drm_file *file_priv);
993int i915_gem_execbuffer2(struct drm_device *dev, void *data,
994 struct drm_file *file_priv);
995int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file_priv);
997int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
998 struct drm_file *file_priv);
999int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1000 struct drm_file *file_priv);
1001int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1002 struct drm_file *file_priv);
1003int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1004 struct drm_file *file_priv);
1005int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv);
1007int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv);
1009int i915_gem_set_tiling(struct drm_device *dev, void *data,
1010 struct drm_file *file_priv);
1011int i915_gem_get_tiling(struct drm_device *dev, void *data,
1012 struct drm_file *file_priv);
1013int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *file_priv);
1015void i915_gem_load(struct drm_device *dev);
1016int i915_gem_init_object(struct drm_gem_object *obj);
1017struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
1018 size_t size);
1019void i915_gem_free_object(struct drm_gem_object *obj);
1020int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
1021 bool map_and_fenceable);
1022void i915_gem_object_unpin(struct drm_gem_object *obj);
1023int i915_gem_object_unbind(struct drm_gem_object *obj);
1024void i915_gem_release_mmap(struct drm_gem_object *obj);
1025void i915_gem_lastclose(struct drm_device *dev);
1026
1027/**
1028 * Returns true if seq1 is later than seq2.
1029 */
1030static inline bool
1031i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1032{
1033 return (int32_t)(seq1 - seq2) >= 0;
1034}
1035
1036int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
1037 bool interruptible);
1038int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
1039 bool interruptible);
1040void i915_gem_retire_requests(struct drm_device *dev);
1041void i915_gem_reset(struct drm_device *dev);
1042void i915_gem_clflush_object(struct drm_gem_object *obj);
1043int i915_gem_object_set_domain(struct drm_gem_object *obj,
1044 uint32_t read_domains,
1045 uint32_t write_domain);
1046int i915_gem_init_ringbuffer(struct drm_device *dev);
1047void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1048int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1049 unsigned long mappable_end, unsigned long end);
1050int i915_gpu_idle(struct drm_device *dev);
1051int i915_gem_idle(struct drm_device *dev);
1052int i915_add_request(struct drm_device *dev,
1053 struct drm_file *file_priv,
1054 struct drm_i915_gem_request *request,
1055 struct intel_ring_buffer *ring);
1056int i915_do_wait_request(struct drm_device *dev,
1057 uint32_t seqno,
1058 bool interruptible,
1059 struct intel_ring_buffer *ring);
1060int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1061int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
1062 int write);
1063int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
1064 bool pipelined);
1065int i915_gem_attach_phys_object(struct drm_device *dev,
1066 struct drm_gem_object *obj,
1067 int id,
1068 int align);
1069void i915_gem_detach_phys_object(struct drm_device *dev,
1070 struct drm_gem_object *obj);
1071void i915_gem_free_all_phys_object(struct drm_device *dev);
1072void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
1073
1074/* i915_gem_evict.c */
1075int i915_gem_evict_something(struct drm_device *dev, int min_size,
1076 unsigned alignment, bool mappable);
1077int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1078int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only);
1079
1080/* i915_gem_tiling.c */
1081void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1082void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
1083void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
1084
1085/* i915_gem_debug.c */
1086void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1087 const char *where, uint32_t mark);
1088#if WATCH_LISTS
1089int i915_verify_lists(struct drm_device *dev);
1090#else
1091#define i915_verify_lists(dev) 0
1092#endif
1093void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1094void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1095 const char *where, uint32_t mark);
1096
1097/* i915_debugfs.c */
1098int i915_debugfs_init(struct drm_minor *minor);
1099void i915_debugfs_cleanup(struct drm_minor *minor);
1100
1101/* i915_suspend.c */
1102extern int i915_save_state(struct drm_device *dev);
1103extern int i915_restore_state(struct drm_device *dev);
1104
1105/* i915_suspend.c */
1106extern int i915_save_state(struct drm_device *dev);
1107extern int i915_restore_state(struct drm_device *dev);
1108
1109/* intel_i2c.c */
1110extern int intel_setup_gmbus(struct drm_device *dev);
1111extern void intel_teardown_gmbus(struct drm_device *dev);
1112extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1113extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1114extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1115{
1116 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1117}
1118extern void intel_i2c_reset(struct drm_device *dev);
1119
1120/* intel_opregion.c */
1121extern int intel_opregion_setup(struct drm_device *dev);
1122#ifdef CONFIG_ACPI
1123extern void intel_opregion_init(struct drm_device *dev);
1124extern void intel_opregion_fini(struct drm_device *dev);
1125extern void intel_opregion_asle_intr(struct drm_device *dev);
1126extern void intel_opregion_gse_intr(struct drm_device *dev);
1127extern void intel_opregion_enable_asle(struct drm_device *dev);
1128#else
1129static inline void intel_opregion_init(struct drm_device *dev) { return; }
1130static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1131static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1132static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1133static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1134#endif
1135
1136/* intel_acpi.c */
1137#ifdef CONFIG_ACPI
1138extern void intel_register_dsm_handler(void);
1139extern void intel_unregister_dsm_handler(void);
1140#else
1141static inline void intel_register_dsm_handler(void) { return; }
1142static inline void intel_unregister_dsm_handler(void) { return; }
1143#endif /* CONFIG_ACPI */
1144
1145/* modesetting */
1146extern void intel_modeset_init(struct drm_device *dev);
1147extern void intel_modeset_cleanup(struct drm_device *dev);
1148extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1149extern void i8xx_disable_fbc(struct drm_device *dev);
1150extern void g4x_disable_fbc(struct drm_device *dev);
1151extern void ironlake_disable_fbc(struct drm_device *dev);
1152extern void intel_disable_fbc(struct drm_device *dev);
1153extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1154extern bool intel_fbc_enabled(struct drm_device *dev);
1155extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1156extern void intel_detect_pch (struct drm_device *dev);
1157extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1158
1159/* overlay */
1160#ifdef CONFIG_DEBUG_FS
1161extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1162extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1163#endif
1164
1165/**
1166 * Lock test for when it's just for synchronization of ring access.
1167 *
1168 * In that case, we don't need to do it when GEM is initialized as nobody else
1169 * has access to the ring.
1170 */
1171#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1172 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1173 == NULL) \
1174 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1175} while (0)
1176
1177static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg, int len)
1178{
1179 u64 val = 0;
1180
1181 switch (len) {
1182 case 8:
1183 val = readq(dev_priv->regs + reg);
1184 break;
1185 case 4:
1186 val = readl(dev_priv->regs + reg);
1187 break;
1188 case 2:
1189 val = readw(dev_priv->regs + reg);
1190 break;
1191 case 1:
1192 val = readb(dev_priv->regs + reg);
1193 break;
1194 }
1195 trace_i915_reg_rw('R', reg, val, len);
1196
1197 return val;
1198}
1199
1200static inline void
1201i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1202{
1203 /* Trace down the write operation before the real write */
1204 trace_i915_reg_rw('W', reg, val, len);
1205 switch (len) {
1206 case 8:
1207 writeq(val, dev_priv->regs + reg);
1208 break;
1209 case 4:
1210 writel(val, dev_priv->regs + reg);
1211 break;
1212 case 2:
1213 writew(val, dev_priv->regs + reg);
1214 break;
1215 case 1:
1216 writeb(val, dev_priv->regs + reg);
1217 break;
1218 }
1219}
1220
1221#define I915_READ(reg) i915_read(dev_priv, (reg), 4)
1222#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4)
1223#define I915_READ16(reg) i915_read(dev_priv, (reg), 2)
1224#define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2)
1225#define I915_READ8(reg) i915_read(dev_priv, (reg), 1)
1226#define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1)
1227#define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8)
1228#define I915_READ64(reg) i915_read(dev_priv, (reg), 8)
1229
1230#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1231#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1232#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1233#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1234
1235#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1236#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1237
1238
1239#define BEGIN_LP_RING(n) \
1240 intel_ring_begin(&dev_priv->render_ring, (n))
1241
1242#define OUT_RING(x) \
1243 intel_ring_emit(&dev_priv->render_ring, x)
1244
1245#define ADVANCE_LP_RING() \
1246 intel_ring_advance(&dev_priv->render_ring)
1247
1248/**
1249 * Reads a dword out of the status page, which is written to from the command
1250 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1251 * MI_STORE_DATA_IMM.
1252 *
1253 * The following dwords have a reserved meaning:
1254 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1255 * 0x04: ring 0 head pointer
1256 * 0x05: ring 1 head pointer (915-class)
1257 * 0x06: ring 2 head pointer (915-class)
1258 * 0x10-0x1b: Context status DWords (GM45)
1259 * 0x1f: Last written status offset. (GM45)
1260 *
1261 * The area from dword 0x20 to 0x3ff is available for driver usage.
1262 */
1263#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1264 (dev_priv->render_ring.status_page.page_addr))[reg])
1265#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1266#define I915_GEM_HWS_INDEX 0x20
1267#define I915_BREADCRUMB_INDEX 0x21
1268
1269#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1270
1271#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1272#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1273#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1274#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1275#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1276#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1277#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1278#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1279#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1280#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1281#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1282#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1283#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1284#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1285#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1286#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1287#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1288#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1289#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1290
1291#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1292#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1293#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1294#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1295#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1296
1297#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1298#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1299#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1300
1301#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1302#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1303
1304/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1305 * rows, which changed the alignment requirements and fence programming.
1306 */
1307#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1308 IS_I915GM(dev)))
1309#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1310#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1311#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1312#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1313#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1314#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1315/* dsparb controlled by hw only */
1316#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1317
1318#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1319#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1320#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1321#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1322
1323#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1324#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1325
1326#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1327#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1328#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1329
1330#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1331
1332#endif
Linux kernel - Deliverables
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