| 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
| 3 | /* |
| 4 | * |
| 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
| 33 | #include <uapi/drm/i915_drm.h> |
| 34 | |
| 35 | #include "i915_reg.h" |
| 36 | #include "intel_bios.h" |
| 37 | #include "intel_ringbuffer.h" |
| 38 | #include <linux/io-mapping.h> |
| 39 | #include <linux/i2c.h> |
| 40 | #include <linux/i2c-algo-bit.h> |
| 41 | #include <drm/intel-gtt.h> |
| 42 | #include <linux/backlight.h> |
| 43 | #include <linux/intel-iommu.h> |
| 44 | #include <linux/kref.h> |
| 45 | #include <linux/pm_qos.h> |
| 46 | |
| 47 | /* General customization: |
| 48 | */ |
| 49 | |
| 50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 51 | |
| 52 | #define DRIVER_NAME "i915" |
| 53 | #define DRIVER_DESC "Intel Graphics" |
| 54 | #define DRIVER_DATE "20080730" |
| 55 | |
| 56 | enum pipe { |
| 57 | PIPE_A = 0, |
| 58 | PIPE_B, |
| 59 | PIPE_C, |
| 60 | I915_MAX_PIPES |
| 61 | }; |
| 62 | #define pipe_name(p) ((p) + 'A') |
| 63 | |
| 64 | enum transcoder { |
| 65 | TRANSCODER_A = 0, |
| 66 | TRANSCODER_B, |
| 67 | TRANSCODER_C, |
| 68 | TRANSCODER_EDP = 0xF, |
| 69 | }; |
| 70 | #define transcoder_name(t) ((t) + 'A') |
| 71 | |
| 72 | enum plane { |
| 73 | PLANE_A = 0, |
| 74 | PLANE_B, |
| 75 | PLANE_C, |
| 76 | }; |
| 77 | #define plane_name(p) ((p) + 'A') |
| 78 | |
| 79 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
| 80 | |
| 81 | enum port { |
| 82 | PORT_A = 0, |
| 83 | PORT_B, |
| 84 | PORT_C, |
| 85 | PORT_D, |
| 86 | PORT_E, |
| 87 | I915_MAX_PORTS |
| 88 | }; |
| 89 | #define port_name(p) ((p) + 'A') |
| 90 | |
| 91 | enum intel_display_power_domain { |
| 92 | POWER_DOMAIN_PIPE_A, |
| 93 | POWER_DOMAIN_PIPE_B, |
| 94 | POWER_DOMAIN_PIPE_C, |
| 95 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
| 96 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
| 97 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
| 98 | POWER_DOMAIN_TRANSCODER_A, |
| 99 | POWER_DOMAIN_TRANSCODER_B, |
| 100 | POWER_DOMAIN_TRANSCODER_C, |
| 101 | POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF, |
| 102 | }; |
| 103 | |
| 104 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
| 105 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
| 106 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
| 107 | #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A) |
| 108 | |
| 109 | enum hpd_pin { |
| 110 | HPD_NONE = 0, |
| 111 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
| 112 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
| 113 | HPD_CRT, |
| 114 | HPD_SDVO_B, |
| 115 | HPD_SDVO_C, |
| 116 | HPD_PORT_B, |
| 117 | HPD_PORT_C, |
| 118 | HPD_PORT_D, |
| 119 | HPD_NUM_PINS |
| 120 | }; |
| 121 | |
| 122 | #define I915_GEM_GPU_DOMAINS \ |
| 123 | (I915_GEM_DOMAIN_RENDER | \ |
| 124 | I915_GEM_DOMAIN_SAMPLER | \ |
| 125 | I915_GEM_DOMAIN_COMMAND | \ |
| 126 | I915_GEM_DOMAIN_INSTRUCTION | \ |
| 127 | I915_GEM_DOMAIN_VERTEX) |
| 128 | |
| 129 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
| 130 | |
| 131 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
| 132 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
| 133 | if ((intel_encoder)->base.crtc == (__crtc)) |
| 134 | |
| 135 | struct drm_i915_private; |
| 136 | |
| 137 | enum intel_dpll_id { |
| 138 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
| 139 | /* real shared dpll ids must be >= 0 */ |
| 140 | DPLL_ID_PCH_PLL_A, |
| 141 | DPLL_ID_PCH_PLL_B, |
| 142 | }; |
| 143 | #define I915_NUM_PLLS 2 |
| 144 | |
| 145 | struct intel_dpll_hw_state { |
| 146 | uint32_t dpll; |
| 147 | uint32_t dpll_md; |
| 148 | uint32_t fp0; |
| 149 | uint32_t fp1; |
| 150 | }; |
| 151 | |
| 152 | struct intel_shared_dpll { |
| 153 | int refcount; /* count of number of CRTCs sharing this PLL */ |
| 154 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 155 | bool on; /* is the PLL actually active? Disabled during modeset */ |
| 156 | const char *name; |
| 157 | /* should match the index in the dev_priv->shared_dplls array */ |
| 158 | enum intel_dpll_id id; |
| 159 | struct intel_dpll_hw_state hw_state; |
| 160 | void (*mode_set)(struct drm_i915_private *dev_priv, |
| 161 | struct intel_shared_dpll *pll); |
| 162 | void (*enable)(struct drm_i915_private *dev_priv, |
| 163 | struct intel_shared_dpll *pll); |
| 164 | void (*disable)(struct drm_i915_private *dev_priv, |
| 165 | struct intel_shared_dpll *pll); |
| 166 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 167 | struct intel_shared_dpll *pll, |
| 168 | struct intel_dpll_hw_state *hw_state); |
| 169 | }; |
| 170 | |
| 171 | /* Used by dp and fdi links */ |
| 172 | struct intel_link_m_n { |
| 173 | uint32_t tu; |
| 174 | uint32_t gmch_m; |
| 175 | uint32_t gmch_n; |
| 176 | uint32_t link_m; |
| 177 | uint32_t link_n; |
| 178 | }; |
| 179 | |
| 180 | void intel_link_compute_m_n(int bpp, int nlanes, |
| 181 | int pixel_clock, int link_clock, |
| 182 | struct intel_link_m_n *m_n); |
| 183 | |
| 184 | struct intel_ddi_plls { |
| 185 | int spll_refcount; |
| 186 | int wrpll1_refcount; |
| 187 | int wrpll2_refcount; |
| 188 | }; |
| 189 | |
| 190 | /* Interface history: |
| 191 | * |
| 192 | * 1.1: Original. |
| 193 | * 1.2: Add Power Management |
| 194 | * 1.3: Add vblank support |
| 195 | * 1.4: Fix cmdbuffer path, add heap destroy |
| 196 | * 1.5: Add vblank pipe configuration |
| 197 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 198 | * - Support vertical blank on secondary display pipe |
| 199 | */ |
| 200 | #define DRIVER_MAJOR 1 |
| 201 | #define DRIVER_MINOR 6 |
| 202 | #define DRIVER_PATCHLEVEL 0 |
| 203 | |
| 204 | #define WATCH_COHERENCY 0 |
| 205 | #define WATCH_LISTS 0 |
| 206 | #define WATCH_GTT 0 |
| 207 | |
| 208 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 209 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 210 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 211 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 212 | |
| 213 | struct drm_i915_gem_phys_object { |
| 214 | int id; |
| 215 | struct page **page_list; |
| 216 | drm_dma_handle_t *handle; |
| 217 | struct drm_i915_gem_object *cur_obj; |
| 218 | }; |
| 219 | |
| 220 | struct opregion_header; |
| 221 | struct opregion_acpi; |
| 222 | struct opregion_swsci; |
| 223 | struct opregion_asle; |
| 224 | |
| 225 | struct intel_opregion { |
| 226 | struct opregion_header __iomem *header; |
| 227 | struct opregion_acpi __iomem *acpi; |
| 228 | struct opregion_swsci __iomem *swsci; |
| 229 | struct opregion_asle __iomem *asle; |
| 230 | void __iomem *vbt; |
| 231 | u32 __iomem *lid_state; |
| 232 | }; |
| 233 | #define OPREGION_SIZE (8*1024) |
| 234 | |
| 235 | struct intel_overlay; |
| 236 | struct intel_overlay_error_state; |
| 237 | |
| 238 | struct drm_i915_master_private { |
| 239 | drm_local_map_t *sarea; |
| 240 | struct _drm_i915_sarea *sarea_priv; |
| 241 | }; |
| 242 | #define I915_FENCE_REG_NONE -1 |
| 243 | #define I915_MAX_NUM_FENCES 32 |
| 244 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
| 245 | #define I915_MAX_NUM_FENCE_BITS 6 |
| 246 | |
| 247 | struct drm_i915_fence_reg { |
| 248 | struct list_head lru_list; |
| 249 | struct drm_i915_gem_object *obj; |
| 250 | int pin_count; |
| 251 | }; |
| 252 | |
| 253 | struct sdvo_device_mapping { |
| 254 | u8 initialized; |
| 255 | u8 dvo_port; |
| 256 | u8 slave_addr; |
| 257 | u8 dvo_wiring; |
| 258 | u8 i2c_pin; |
| 259 | u8 ddc_pin; |
| 260 | }; |
| 261 | |
| 262 | struct intel_display_error_state; |
| 263 | |
| 264 | struct drm_i915_error_state { |
| 265 | struct kref ref; |
| 266 | u32 eir; |
| 267 | u32 pgtbl_er; |
| 268 | u32 ier; |
| 269 | u32 ccid; |
| 270 | u32 derrmr; |
| 271 | u32 forcewake; |
| 272 | bool waiting[I915_NUM_RINGS]; |
| 273 | u32 pipestat[I915_MAX_PIPES]; |
| 274 | u32 tail[I915_NUM_RINGS]; |
| 275 | u32 head[I915_NUM_RINGS]; |
| 276 | u32 ctl[I915_NUM_RINGS]; |
| 277 | u32 ipeir[I915_NUM_RINGS]; |
| 278 | u32 ipehr[I915_NUM_RINGS]; |
| 279 | u32 instdone[I915_NUM_RINGS]; |
| 280 | u32 acthd[I915_NUM_RINGS]; |
| 281 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
| 282 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
| 283 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
| 284 | /* our own tracking of ring head and tail */ |
| 285 | u32 cpu_ring_head[I915_NUM_RINGS]; |
| 286 | u32 cpu_ring_tail[I915_NUM_RINGS]; |
| 287 | u32 error; /* gen6+ */ |
| 288 | u32 err_int; /* gen7 */ |
| 289 | u32 instpm[I915_NUM_RINGS]; |
| 290 | u32 instps[I915_NUM_RINGS]; |
| 291 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
| 292 | u32 seqno[I915_NUM_RINGS]; |
| 293 | u64 bbaddr; |
| 294 | u32 fault_reg[I915_NUM_RINGS]; |
| 295 | u32 done_reg; |
| 296 | u32 faddr[I915_NUM_RINGS]; |
| 297 | u64 fence[I915_MAX_NUM_FENCES]; |
| 298 | struct timeval time; |
| 299 | struct drm_i915_error_ring { |
| 300 | struct drm_i915_error_object { |
| 301 | int page_count; |
| 302 | u32 gtt_offset; |
| 303 | u32 *pages[0]; |
| 304 | } *ringbuffer, *batchbuffer, *ctx; |
| 305 | struct drm_i915_error_request { |
| 306 | long jiffies; |
| 307 | u32 seqno; |
| 308 | u32 tail; |
| 309 | } *requests; |
| 310 | int num_requests; |
| 311 | } ring[I915_NUM_RINGS]; |
| 312 | struct drm_i915_error_buffer { |
| 313 | u32 size; |
| 314 | u32 name; |
| 315 | u32 rseqno, wseqno; |
| 316 | u32 gtt_offset; |
| 317 | u32 read_domains; |
| 318 | u32 write_domain; |
| 319 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
| 320 | s32 pinned:2; |
| 321 | u32 tiling:2; |
| 322 | u32 dirty:1; |
| 323 | u32 purgeable:1; |
| 324 | s32 ring:4; |
| 325 | u32 cache_level:2; |
| 326 | } *active_bo, *pinned_bo; |
| 327 | u32 active_bo_count, pinned_bo_count; |
| 328 | struct intel_overlay_error_state *overlay; |
| 329 | struct intel_display_error_state *display; |
| 330 | }; |
| 331 | |
| 332 | struct intel_crtc_config; |
| 333 | struct intel_crtc; |
| 334 | struct intel_limit; |
| 335 | struct dpll; |
| 336 | |
| 337 | struct drm_i915_display_funcs { |
| 338 | bool (*fbc_enabled)(struct drm_device *dev); |
| 339 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
| 340 | void (*disable_fbc)(struct drm_device *dev); |
| 341 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 342 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
| 343 | /** |
| 344 | * find_dpll() - Find the best values for the PLL |
| 345 | * @limit: limits for the PLL |
| 346 | * @crtc: current CRTC |
| 347 | * @target: target frequency in kHz |
| 348 | * @refclk: reference clock frequency in kHz |
| 349 | * @match_clock: if provided, @best_clock P divider must |
| 350 | * match the P divider from @match_clock |
| 351 | * used for LVDS downclocking |
| 352 | * @best_clock: best PLL values found |
| 353 | * |
| 354 | * Returns true on success, false on failure. |
| 355 | */ |
| 356 | bool (*find_dpll)(const struct intel_limit *limit, |
| 357 | struct drm_crtc *crtc, |
| 358 | int target, int refclk, |
| 359 | struct dpll *match_clock, |
| 360 | struct dpll *best_clock); |
| 361 | void (*update_wm)(struct drm_device *dev); |
| 362 | void (*update_sprite_wm)(struct drm_device *dev, int pipe, |
| 363 | uint32_t sprite_width, int pixel_size, |
| 364 | bool enable); |
| 365 | void (*modeset_global_resources)(struct drm_device *dev); |
| 366 | /* Returns the active state of the crtc, and if the crtc is active, |
| 367 | * fills out the pipe-config with the hw state. */ |
| 368 | bool (*get_pipe_config)(struct intel_crtc *, |
| 369 | struct intel_crtc_config *); |
| 370 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
| 371 | int x, int y, |
| 372 | struct drm_framebuffer *old_fb); |
| 373 | void (*crtc_enable)(struct drm_crtc *crtc); |
| 374 | void (*crtc_disable)(struct drm_crtc *crtc); |
| 375 | void (*off)(struct drm_crtc *crtc); |
| 376 | void (*write_eld)(struct drm_connector *connector, |
| 377 | struct drm_crtc *crtc); |
| 378 | void (*fdi_link_train)(struct drm_crtc *crtc); |
| 379 | void (*init_clock_gating)(struct drm_device *dev); |
| 380 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
| 381 | struct drm_framebuffer *fb, |
| 382 | struct drm_i915_gem_object *obj); |
| 383 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 384 | int x, int y); |
| 385 | void (*hpd_irq_setup)(struct drm_device *dev); |
| 386 | /* clock updates for mode set */ |
| 387 | /* cursor updates */ |
| 388 | /* render clock increase/decrease */ |
| 389 | /* display clock increase/decrease */ |
| 390 | /* pll clock increase/decrease */ |
| 391 | }; |
| 392 | |
| 393 | struct drm_i915_gt_funcs { |
| 394 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
| 395 | void (*force_wake_put)(struct drm_i915_private *dev_priv); |
| 396 | }; |
| 397 | |
| 398 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
| 399 | func(is_mobile) sep \ |
| 400 | func(is_i85x) sep \ |
| 401 | func(is_i915g) sep \ |
| 402 | func(is_i945gm) sep \ |
| 403 | func(is_g33) sep \ |
| 404 | func(need_gfx_hws) sep \ |
| 405 | func(is_g4x) sep \ |
| 406 | func(is_pineview) sep \ |
| 407 | func(is_broadwater) sep \ |
| 408 | func(is_crestline) sep \ |
| 409 | func(is_ivybridge) sep \ |
| 410 | func(is_valleyview) sep \ |
| 411 | func(is_haswell) sep \ |
| 412 | func(has_force_wake) sep \ |
| 413 | func(has_fbc) sep \ |
| 414 | func(has_pipe_cxsr) sep \ |
| 415 | func(has_hotplug) sep \ |
| 416 | func(cursor_needs_physical) sep \ |
| 417 | func(has_overlay) sep \ |
| 418 | func(overlay_needs_physical) sep \ |
| 419 | func(supports_tv) sep \ |
| 420 | func(has_bsd_ring) sep \ |
| 421 | func(has_blt_ring) sep \ |
| 422 | func(has_vebox_ring) sep \ |
| 423 | func(has_llc) sep \ |
| 424 | func(has_ddi) sep \ |
| 425 | func(has_fpga_dbg) |
| 426 | |
| 427 | #define DEFINE_FLAG(name) u8 name:1 |
| 428 | #define SEP_SEMICOLON ; |
| 429 | |
| 430 | struct intel_device_info { |
| 431 | u32 display_mmio_offset; |
| 432 | u8 num_pipes:3; |
| 433 | u8 gen; |
| 434 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
| 435 | }; |
| 436 | |
| 437 | #undef DEFINE_FLAG |
| 438 | #undef SEP_SEMICOLON |
| 439 | |
| 440 | enum i915_cache_level { |
| 441 | I915_CACHE_NONE = 0, |
| 442 | I915_CACHE_LLC, |
| 443 | I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */ |
| 444 | }; |
| 445 | |
| 446 | typedef uint32_t gen6_gtt_pte_t; |
| 447 | |
| 448 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
| 449 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
| 450 | * collateral associated with any va->pa translations GEN hardware also has a |
| 451 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
| 452 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
| 453 | * the spec. |
| 454 | */ |
| 455 | struct i915_gtt { |
| 456 | unsigned long start; /* Start offset of used GTT */ |
| 457 | size_t total; /* Total size GTT can map */ |
| 458 | size_t stolen_size; /* Total size of stolen memory */ |
| 459 | |
| 460 | unsigned long mappable_end; /* End offset that we can CPU map */ |
| 461 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
| 462 | phys_addr_t mappable_base; /* PA of our GMADR */ |
| 463 | |
| 464 | /** "Graphics Stolen Memory" holds the global PTEs */ |
| 465 | void __iomem *gsm; |
| 466 | |
| 467 | bool do_idle_maps; |
| 468 | struct { |
| 469 | dma_addr_t addr; |
| 470 | struct page *page; |
| 471 | } scratch; |
| 472 | |
| 473 | /* global gtt ops */ |
| 474 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
| 475 | size_t *stolen, phys_addr_t *mappable_base, |
| 476 | unsigned long *mappable_end); |
| 477 | void (*gtt_remove)(struct drm_device *dev); |
| 478 | void (*gtt_clear_range)(struct drm_device *dev, |
| 479 | unsigned int first_entry, |
| 480 | unsigned int num_entries); |
| 481 | void (*gtt_insert_entries)(struct drm_device *dev, |
| 482 | struct sg_table *st, |
| 483 | unsigned int pg_start, |
| 484 | enum i915_cache_level cache_level); |
| 485 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
| 486 | dma_addr_t addr, |
| 487 | enum i915_cache_level level); |
| 488 | }; |
| 489 | #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT) |
| 490 | |
| 491 | struct i915_hw_ppgtt { |
| 492 | struct drm_device *dev; |
| 493 | unsigned num_pd_entries; |
| 494 | struct page **pt_pages; |
| 495 | uint32_t pd_offset; |
| 496 | dma_addr_t *pt_dma_addr; |
| 497 | |
| 498 | /* pte functions, mirroring the interface of the global gtt. */ |
| 499 | void (*clear_range)(struct i915_hw_ppgtt *ppgtt, |
| 500 | unsigned int first_entry, |
| 501 | unsigned int num_entries); |
| 502 | void (*insert_entries)(struct i915_hw_ppgtt *ppgtt, |
| 503 | struct sg_table *st, |
| 504 | unsigned int pg_start, |
| 505 | enum i915_cache_level cache_level); |
| 506 | gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev, |
| 507 | dma_addr_t addr, |
| 508 | enum i915_cache_level level); |
| 509 | int (*enable)(struct drm_device *dev); |
| 510 | void (*cleanup)(struct i915_hw_ppgtt *ppgtt); |
| 511 | }; |
| 512 | |
| 513 | struct i915_ctx_hang_stats { |
| 514 | /* This context had batch pending when hang was declared */ |
| 515 | unsigned batch_pending; |
| 516 | |
| 517 | /* This context had batch active when hang was declared */ |
| 518 | unsigned batch_active; |
| 519 | }; |
| 520 | |
| 521 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
| 522 | #define DEFAULT_CONTEXT_ID 0 |
| 523 | struct i915_hw_context { |
| 524 | struct kref ref; |
| 525 | int id; |
| 526 | bool is_initialized; |
| 527 | struct drm_i915_file_private *file_priv; |
| 528 | struct intel_ring_buffer *ring; |
| 529 | struct drm_i915_gem_object *obj; |
| 530 | struct i915_ctx_hang_stats hang_stats; |
| 531 | }; |
| 532 | |
| 533 | enum no_fbc_reason { |
| 534 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
| 535 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
| 536 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 537 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 538 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 539 | FBC_NOT_TILED, /* buffer not tiled */ |
| 540 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
| 541 | FBC_MODULE_PARAM, |
| 542 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
| 543 | }; |
| 544 | |
| 545 | enum intel_pch { |
| 546 | PCH_NONE = 0, /* No PCH present */ |
| 547 | PCH_IBX, /* Ibexpeak PCH */ |
| 548 | PCH_CPT, /* Cougarpoint PCH */ |
| 549 | PCH_LPT, /* Lynxpoint PCH */ |
| 550 | PCH_NOP, |
| 551 | }; |
| 552 | |
| 553 | enum intel_sbi_destination { |
| 554 | SBI_ICLK, |
| 555 | SBI_MPHY, |
| 556 | }; |
| 557 | |
| 558 | #define QUIRK_PIPEA_FORCE (1<<0) |
| 559 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
| 560 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
| 561 | |
| 562 | struct intel_fbdev; |
| 563 | struct intel_fbc_work; |
| 564 | |
| 565 | struct intel_gmbus { |
| 566 | struct i2c_adapter adapter; |
| 567 | u32 force_bit; |
| 568 | u32 reg0; |
| 569 | u32 gpio_reg; |
| 570 | struct i2c_algo_bit_data bit_algo; |
| 571 | struct drm_i915_private *dev_priv; |
| 572 | }; |
| 573 | |
| 574 | struct i915_suspend_saved_registers { |
| 575 | u8 saveLBB; |
| 576 | u32 saveDSPACNTR; |
| 577 | u32 saveDSPBCNTR; |
| 578 | u32 saveDSPARB; |
| 579 | u32 savePIPEACONF; |
| 580 | u32 savePIPEBCONF; |
| 581 | u32 savePIPEASRC; |
| 582 | u32 savePIPEBSRC; |
| 583 | u32 saveFPA0; |
| 584 | u32 saveFPA1; |
| 585 | u32 saveDPLL_A; |
| 586 | u32 saveDPLL_A_MD; |
| 587 | u32 saveHTOTAL_A; |
| 588 | u32 saveHBLANK_A; |
| 589 | u32 saveHSYNC_A; |
| 590 | u32 saveVTOTAL_A; |
| 591 | u32 saveVBLANK_A; |
| 592 | u32 saveVSYNC_A; |
| 593 | u32 saveBCLRPAT_A; |
| 594 | u32 saveTRANSACONF; |
| 595 | u32 saveTRANS_HTOTAL_A; |
| 596 | u32 saveTRANS_HBLANK_A; |
| 597 | u32 saveTRANS_HSYNC_A; |
| 598 | u32 saveTRANS_VTOTAL_A; |
| 599 | u32 saveTRANS_VBLANK_A; |
| 600 | u32 saveTRANS_VSYNC_A; |
| 601 | u32 savePIPEASTAT; |
| 602 | u32 saveDSPASTRIDE; |
| 603 | u32 saveDSPASIZE; |
| 604 | u32 saveDSPAPOS; |
| 605 | u32 saveDSPAADDR; |
| 606 | u32 saveDSPASURF; |
| 607 | u32 saveDSPATILEOFF; |
| 608 | u32 savePFIT_PGM_RATIOS; |
| 609 | u32 saveBLC_HIST_CTL; |
| 610 | u32 saveBLC_PWM_CTL; |
| 611 | u32 saveBLC_PWM_CTL2; |
| 612 | u32 saveBLC_CPU_PWM_CTL; |
| 613 | u32 saveBLC_CPU_PWM_CTL2; |
| 614 | u32 saveFPB0; |
| 615 | u32 saveFPB1; |
| 616 | u32 saveDPLL_B; |
| 617 | u32 saveDPLL_B_MD; |
| 618 | u32 saveHTOTAL_B; |
| 619 | u32 saveHBLANK_B; |
| 620 | u32 saveHSYNC_B; |
| 621 | u32 saveVTOTAL_B; |
| 622 | u32 saveVBLANK_B; |
| 623 | u32 saveVSYNC_B; |
| 624 | u32 saveBCLRPAT_B; |
| 625 | u32 saveTRANSBCONF; |
| 626 | u32 saveTRANS_HTOTAL_B; |
| 627 | u32 saveTRANS_HBLANK_B; |
| 628 | u32 saveTRANS_HSYNC_B; |
| 629 | u32 saveTRANS_VTOTAL_B; |
| 630 | u32 saveTRANS_VBLANK_B; |
| 631 | u32 saveTRANS_VSYNC_B; |
| 632 | u32 savePIPEBSTAT; |
| 633 | u32 saveDSPBSTRIDE; |
| 634 | u32 saveDSPBSIZE; |
| 635 | u32 saveDSPBPOS; |
| 636 | u32 saveDSPBADDR; |
| 637 | u32 saveDSPBSURF; |
| 638 | u32 saveDSPBTILEOFF; |
| 639 | u32 saveVGA0; |
| 640 | u32 saveVGA1; |
| 641 | u32 saveVGA_PD; |
| 642 | u32 saveVGACNTRL; |
| 643 | u32 saveADPA; |
| 644 | u32 saveLVDS; |
| 645 | u32 savePP_ON_DELAYS; |
| 646 | u32 savePP_OFF_DELAYS; |
| 647 | u32 saveDVOA; |
| 648 | u32 saveDVOB; |
| 649 | u32 saveDVOC; |
| 650 | u32 savePP_ON; |
| 651 | u32 savePP_OFF; |
| 652 | u32 savePP_CONTROL; |
| 653 | u32 savePP_DIVISOR; |
| 654 | u32 savePFIT_CONTROL; |
| 655 | u32 save_palette_a[256]; |
| 656 | u32 save_palette_b[256]; |
| 657 | u32 saveDPFC_CB_BASE; |
| 658 | u32 saveFBC_CFB_BASE; |
| 659 | u32 saveFBC_LL_BASE; |
| 660 | u32 saveFBC_CONTROL; |
| 661 | u32 saveFBC_CONTROL2; |
| 662 | u32 saveIER; |
| 663 | u32 saveIIR; |
| 664 | u32 saveIMR; |
| 665 | u32 saveDEIER; |
| 666 | u32 saveDEIMR; |
| 667 | u32 saveGTIER; |
| 668 | u32 saveGTIMR; |
| 669 | u32 saveFDI_RXA_IMR; |
| 670 | u32 saveFDI_RXB_IMR; |
| 671 | u32 saveCACHE_MODE_0; |
| 672 | u32 saveMI_ARB_STATE; |
| 673 | u32 saveSWF0[16]; |
| 674 | u32 saveSWF1[16]; |
| 675 | u32 saveSWF2[3]; |
| 676 | u8 saveMSR; |
| 677 | u8 saveSR[8]; |
| 678 | u8 saveGR[25]; |
| 679 | u8 saveAR_INDEX; |
| 680 | u8 saveAR[21]; |
| 681 | u8 saveDACMASK; |
| 682 | u8 saveCR[37]; |
| 683 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
| 684 | u32 saveCURACNTR; |
| 685 | u32 saveCURAPOS; |
| 686 | u32 saveCURABASE; |
| 687 | u32 saveCURBCNTR; |
| 688 | u32 saveCURBPOS; |
| 689 | u32 saveCURBBASE; |
| 690 | u32 saveCURSIZE; |
| 691 | u32 saveDP_B; |
| 692 | u32 saveDP_C; |
| 693 | u32 saveDP_D; |
| 694 | u32 savePIPEA_GMCH_DATA_M; |
| 695 | u32 savePIPEB_GMCH_DATA_M; |
| 696 | u32 savePIPEA_GMCH_DATA_N; |
| 697 | u32 savePIPEB_GMCH_DATA_N; |
| 698 | u32 savePIPEA_DP_LINK_M; |
| 699 | u32 savePIPEB_DP_LINK_M; |
| 700 | u32 savePIPEA_DP_LINK_N; |
| 701 | u32 savePIPEB_DP_LINK_N; |
| 702 | u32 saveFDI_RXA_CTL; |
| 703 | u32 saveFDI_TXA_CTL; |
| 704 | u32 saveFDI_RXB_CTL; |
| 705 | u32 saveFDI_TXB_CTL; |
| 706 | u32 savePFA_CTL_1; |
| 707 | u32 savePFB_CTL_1; |
| 708 | u32 savePFA_WIN_SZ; |
| 709 | u32 savePFB_WIN_SZ; |
| 710 | u32 savePFA_WIN_POS; |
| 711 | u32 savePFB_WIN_POS; |
| 712 | u32 savePCH_DREF_CONTROL; |
| 713 | u32 saveDISP_ARB_CTL; |
| 714 | u32 savePIPEA_DATA_M1; |
| 715 | u32 savePIPEA_DATA_N1; |
| 716 | u32 savePIPEA_LINK_M1; |
| 717 | u32 savePIPEA_LINK_N1; |
| 718 | u32 savePIPEB_DATA_M1; |
| 719 | u32 savePIPEB_DATA_N1; |
| 720 | u32 savePIPEB_LINK_M1; |
| 721 | u32 savePIPEB_LINK_N1; |
| 722 | u32 saveMCHBAR_RENDER_STANDBY; |
| 723 | u32 savePCH_PORT_HOTPLUG; |
| 724 | }; |
| 725 | |
| 726 | struct intel_gen6_power_mgmt { |
| 727 | struct work_struct work; |
| 728 | struct delayed_work vlv_work; |
| 729 | u32 pm_iir; |
| 730 | /* lock - irqsave spinlock that protectects the work_struct and |
| 731 | * pm_iir. */ |
| 732 | spinlock_t lock; |
| 733 | |
| 734 | /* The below variables an all the rps hw state are protected by |
| 735 | * dev->struct mutext. */ |
| 736 | u8 cur_delay; |
| 737 | u8 min_delay; |
| 738 | u8 max_delay; |
| 739 | u8 rpe_delay; |
| 740 | u8 hw_max; |
| 741 | |
| 742 | struct delayed_work delayed_resume_work; |
| 743 | |
| 744 | /* |
| 745 | * Protects RPS/RC6 register access and PCU communication. |
| 746 | * Must be taken after struct_mutex if nested. |
| 747 | */ |
| 748 | struct mutex hw_lock; |
| 749 | }; |
| 750 | |
| 751 | /* defined intel_pm.c */ |
| 752 | extern spinlock_t mchdev_lock; |
| 753 | |
| 754 | struct intel_ilk_power_mgmt { |
| 755 | u8 cur_delay; |
| 756 | u8 min_delay; |
| 757 | u8 max_delay; |
| 758 | u8 fmax; |
| 759 | u8 fstart; |
| 760 | |
| 761 | u64 last_count1; |
| 762 | unsigned long last_time1; |
| 763 | unsigned long chipset_power; |
| 764 | u64 last_count2; |
| 765 | struct timespec last_time2; |
| 766 | unsigned long gfx_power; |
| 767 | u8 corr; |
| 768 | |
| 769 | int c_m; |
| 770 | int r_t; |
| 771 | |
| 772 | struct drm_i915_gem_object *pwrctx; |
| 773 | struct drm_i915_gem_object *renderctx; |
| 774 | }; |
| 775 | |
| 776 | /* Power well structure for haswell */ |
| 777 | struct i915_power_well { |
| 778 | struct drm_device *device; |
| 779 | spinlock_t lock; |
| 780 | /* power well enable/disable usage count */ |
| 781 | int count; |
| 782 | int i915_request; |
| 783 | }; |
| 784 | |
| 785 | struct i915_dri1_state { |
| 786 | unsigned allow_batchbuffer : 1; |
| 787 | u32 __iomem *gfx_hws_cpu_addr; |
| 788 | |
| 789 | unsigned int cpp; |
| 790 | int back_offset; |
| 791 | int front_offset; |
| 792 | int current_page; |
| 793 | int page_flipping; |
| 794 | |
| 795 | uint32_t counter; |
| 796 | }; |
| 797 | |
| 798 | struct intel_l3_parity { |
| 799 | u32 *remap_info; |
| 800 | struct work_struct error_work; |
| 801 | }; |
| 802 | |
| 803 | struct i915_gem_mm { |
| 804 | /** Memory allocator for GTT stolen memory */ |
| 805 | struct drm_mm stolen; |
| 806 | /** Memory allocator for GTT */ |
| 807 | struct drm_mm gtt_space; |
| 808 | /** List of all objects in gtt_space. Used to restore gtt |
| 809 | * mappings on resume */ |
| 810 | struct list_head bound_list; |
| 811 | /** |
| 812 | * List of objects which are not bound to the GTT (thus |
| 813 | * are idle and not used by the GPU) but still have |
| 814 | * (presumably uncached) pages still attached. |
| 815 | */ |
| 816 | struct list_head unbound_list; |
| 817 | |
| 818 | /** Usable portion of the GTT for GEM */ |
| 819 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
| 820 | |
| 821 | int gtt_mtrr; |
| 822 | |
| 823 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
| 824 | struct i915_hw_ppgtt *aliasing_ppgtt; |
| 825 | |
| 826 | struct shrinker inactive_shrinker; |
| 827 | bool shrinker_no_lock_stealing; |
| 828 | |
| 829 | /** |
| 830 | * List of objects currently involved in rendering. |
| 831 | * |
| 832 | * Includes buffers having the contents of their GPU caches |
| 833 | * flushed, not necessarily primitives. last_rendering_seqno |
| 834 | * represents when the rendering involved will be completed. |
| 835 | * |
| 836 | * A reference is held on the buffer while on this list. |
| 837 | */ |
| 838 | struct list_head active_list; |
| 839 | |
| 840 | /** |
| 841 | * LRU list of objects which are not in the ringbuffer and |
| 842 | * are ready to unbind, but are still in the GTT. |
| 843 | * |
| 844 | * last_rendering_seqno is 0 while an object is in this list. |
| 845 | * |
| 846 | * A reference is not held on the buffer while on this list, |
| 847 | * as merely being GTT-bound shouldn't prevent its being |
| 848 | * freed, and we'll pull it off the list in the free path. |
| 849 | */ |
| 850 | struct list_head inactive_list; |
| 851 | |
| 852 | /** LRU list of objects with fence regs on them. */ |
| 853 | struct list_head fence_list; |
| 854 | |
| 855 | /** |
| 856 | * We leave the user IRQ off as much as possible, |
| 857 | * but this means that requests will finish and never |
| 858 | * be retired once the system goes idle. Set a timer to |
| 859 | * fire periodically while the ring is running. When it |
| 860 | * fires, go retire requests. |
| 861 | */ |
| 862 | struct delayed_work retire_work; |
| 863 | |
| 864 | /** |
| 865 | * Are we in a non-interruptible section of code like |
| 866 | * modesetting? |
| 867 | */ |
| 868 | bool interruptible; |
| 869 | |
| 870 | /** |
| 871 | * Flag if the X Server, and thus DRM, is not currently in |
| 872 | * control of the device. |
| 873 | * |
| 874 | * This is set between LeaveVT and EnterVT. It needs to be |
| 875 | * replaced with a semaphore. It also needs to be |
| 876 | * transitioned away from for kernel modesetting. |
| 877 | */ |
| 878 | int suspended; |
| 879 | |
| 880 | /** Bit 6 swizzling required for X tiling */ |
| 881 | uint32_t bit_6_swizzle_x; |
| 882 | /** Bit 6 swizzling required for Y tiling */ |
| 883 | uint32_t bit_6_swizzle_y; |
| 884 | |
| 885 | /* storage for physical objects */ |
| 886 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
| 887 | |
| 888 | /* accounting, useful for userland debugging */ |
| 889 | size_t object_memory; |
| 890 | u32 object_count; |
| 891 | }; |
| 892 | |
| 893 | struct drm_i915_error_state_buf { |
| 894 | unsigned bytes; |
| 895 | unsigned size; |
| 896 | int err; |
| 897 | u8 *buf; |
| 898 | loff_t start; |
| 899 | loff_t pos; |
| 900 | }; |
| 901 | |
| 902 | struct i915_gpu_error { |
| 903 | /* For hangcheck timer */ |
| 904 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
| 905 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
| 906 | struct timer_list hangcheck_timer; |
| 907 | |
| 908 | /* For reset and error_state handling. */ |
| 909 | spinlock_t lock; |
| 910 | /* Protected by the above dev->gpu_error.lock. */ |
| 911 | struct drm_i915_error_state *first_error; |
| 912 | struct work_struct work; |
| 913 | |
| 914 | unsigned long last_reset; |
| 915 | |
| 916 | /** |
| 917 | * State variable and reset counter controlling the reset flow |
| 918 | * |
| 919 | * Upper bits are for the reset counter. This counter is used by the |
| 920 | * wait_seqno code to race-free noticed that a reset event happened and |
| 921 | * that it needs to restart the entire ioctl (since most likely the |
| 922 | * seqno it waited for won't ever signal anytime soon). |
| 923 | * |
| 924 | * This is important for lock-free wait paths, where no contended lock |
| 925 | * naturally enforces the correct ordering between the bail-out of the |
| 926 | * waiter and the gpu reset work code. |
| 927 | * |
| 928 | * Lowest bit controls the reset state machine: Set means a reset is in |
| 929 | * progress. This state will (presuming we don't have any bugs) decay |
| 930 | * into either unset (successful reset) or the special WEDGED value (hw |
| 931 | * terminally sour). All waiters on the reset_queue will be woken when |
| 932 | * that happens. |
| 933 | */ |
| 934 | atomic_t reset_counter; |
| 935 | |
| 936 | /** |
| 937 | * Special values/flags for reset_counter |
| 938 | * |
| 939 | * Note that the code relies on |
| 940 | * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG |
| 941 | * being true. |
| 942 | */ |
| 943 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
| 944 | #define I915_WEDGED 0xffffffff |
| 945 | |
| 946 | /** |
| 947 | * Waitqueue to signal when the reset has completed. Used by clients |
| 948 | * that wait for dev_priv->mm.wedged to settle. |
| 949 | */ |
| 950 | wait_queue_head_t reset_queue; |
| 951 | |
| 952 | /* For gpu hang simulation. */ |
| 953 | unsigned int stop_rings; |
| 954 | }; |
| 955 | |
| 956 | enum modeset_restore { |
| 957 | MODESET_ON_LID_OPEN, |
| 958 | MODESET_DONE, |
| 959 | MODESET_SUSPENDED, |
| 960 | }; |
| 961 | |
| 962 | struct intel_vbt_data { |
| 963 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 964 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
| 965 | |
| 966 | /* Feature bits */ |
| 967 | unsigned int int_tv_support:1; |
| 968 | unsigned int lvds_dither:1; |
| 969 | unsigned int lvds_vbt:1; |
| 970 | unsigned int int_crt_support:1; |
| 971 | unsigned int lvds_use_ssc:1; |
| 972 | unsigned int display_clock_mode:1; |
| 973 | unsigned int fdi_rx_polarity_inverted:1; |
| 974 | int lvds_ssc_freq; |
| 975 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
| 976 | |
| 977 | /* eDP */ |
| 978 | int edp_rate; |
| 979 | int edp_lanes; |
| 980 | int edp_preemphasis; |
| 981 | int edp_vswing; |
| 982 | bool edp_initialized; |
| 983 | bool edp_support; |
| 984 | int edp_bpp; |
| 985 | struct edp_power_seq edp_pps; |
| 986 | |
| 987 | int crt_ddc_pin; |
| 988 | |
| 989 | int child_dev_num; |
| 990 | struct child_device_config *child_dev; |
| 991 | }; |
| 992 | |
| 993 | typedef struct drm_i915_private { |
| 994 | struct drm_device *dev; |
| 995 | struct kmem_cache *slab; |
| 996 | |
| 997 | const struct intel_device_info *info; |
| 998 | |
| 999 | int relative_constants_mode; |
| 1000 | |
| 1001 | void __iomem *regs; |
| 1002 | |
| 1003 | struct drm_i915_gt_funcs gt; |
| 1004 | /** gt_fifo_count and the subsequent register write are synchronized |
| 1005 | * with dev->struct_mutex. */ |
| 1006 | unsigned gt_fifo_count; |
| 1007 | /** forcewake_count is protected by gt_lock */ |
| 1008 | unsigned forcewake_count; |
| 1009 | /** gt_lock is also taken in irq contexts. */ |
| 1010 | spinlock_t gt_lock; |
| 1011 | |
| 1012 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
| 1013 | |
| 1014 | |
| 1015 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
| 1016 | * controller on different i2c buses. */ |
| 1017 | struct mutex gmbus_mutex; |
| 1018 | |
| 1019 | /** |
| 1020 | * Base address of the gmbus and gpio block. |
| 1021 | */ |
| 1022 | uint32_t gpio_mmio_base; |
| 1023 | |
| 1024 | wait_queue_head_t gmbus_wait_queue; |
| 1025 | |
| 1026 | struct pci_dev *bridge_dev; |
| 1027 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
| 1028 | uint32_t last_seqno, next_seqno; |
| 1029 | |
| 1030 | drm_dma_handle_t *status_page_dmah; |
| 1031 | struct resource mch_res; |
| 1032 | |
| 1033 | atomic_t irq_received; |
| 1034 | |
| 1035 | /* protects the irq masks */ |
| 1036 | spinlock_t irq_lock; |
| 1037 | |
| 1038 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
| 1039 | struct pm_qos_request pm_qos; |
| 1040 | |
| 1041 | /* DPIO indirect register protection */ |
| 1042 | struct mutex dpio_lock; |
| 1043 | |
| 1044 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
| 1045 | u32 irq_mask; |
| 1046 | u32 gt_irq_mask; |
| 1047 | |
| 1048 | struct work_struct hotplug_work; |
| 1049 | bool enable_hotplug_processing; |
| 1050 | struct { |
| 1051 | unsigned long hpd_last_jiffies; |
| 1052 | int hpd_cnt; |
| 1053 | enum { |
| 1054 | HPD_ENABLED = 0, |
| 1055 | HPD_DISABLED = 1, |
| 1056 | HPD_MARK_DISABLED = 2 |
| 1057 | } hpd_mark; |
| 1058 | } hpd_stats[HPD_NUM_PINS]; |
| 1059 | u32 hpd_event_bits; |
| 1060 | struct timer_list hotplug_reenable_timer; |
| 1061 | |
| 1062 | int num_plane; |
| 1063 | |
| 1064 | unsigned long cfb_size; |
| 1065 | unsigned int cfb_fb; |
| 1066 | enum plane cfb_plane; |
| 1067 | int cfb_y; |
| 1068 | struct intel_fbc_work *fbc_work; |
| 1069 | |
| 1070 | struct intel_opregion opregion; |
| 1071 | struct intel_vbt_data vbt; |
| 1072 | |
| 1073 | /* overlay */ |
| 1074 | struct intel_overlay *overlay; |
| 1075 | unsigned int sprite_scaling_enabled; |
| 1076 | |
| 1077 | /* backlight */ |
| 1078 | struct { |
| 1079 | int level; |
| 1080 | bool enabled; |
| 1081 | spinlock_t lock; /* bl registers and the above bl fields */ |
| 1082 | struct backlight_device *device; |
| 1083 | } backlight; |
| 1084 | |
| 1085 | /* LVDS info */ |
| 1086 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 1087 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
| 1088 | bool no_aux_handshake; |
| 1089 | |
| 1090 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
| 1091 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 1092 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 1093 | |
| 1094 | unsigned int fsb_freq, mem_freq, is_ddr3; |
| 1095 | |
| 1096 | struct workqueue_struct *wq; |
| 1097 | |
| 1098 | /* Display functions */ |
| 1099 | struct drm_i915_display_funcs display; |
| 1100 | |
| 1101 | /* PCH chipset type */ |
| 1102 | enum intel_pch pch_type; |
| 1103 | unsigned short pch_id; |
| 1104 | |
| 1105 | unsigned long quirks; |
| 1106 | |
| 1107 | enum modeset_restore modeset_restore; |
| 1108 | struct mutex modeset_restore_lock; |
| 1109 | |
| 1110 | struct i915_gtt gtt; |
| 1111 | |
| 1112 | struct i915_gem_mm mm; |
| 1113 | |
| 1114 | /* Kernel Modesetting */ |
| 1115 | |
| 1116 | struct sdvo_device_mapping sdvo_mappings[2]; |
| 1117 | |
| 1118 | struct drm_crtc *plane_to_crtc_mapping[3]; |
| 1119 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
| 1120 | wait_queue_head_t pending_flip_queue; |
| 1121 | |
| 1122 | int num_shared_dpll; |
| 1123 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
| 1124 | struct intel_ddi_plls ddi_plls; |
| 1125 | |
| 1126 | /* Reclocking support */ |
| 1127 | bool render_reclock_avail; |
| 1128 | bool lvds_downclock_avail; |
| 1129 | /* indicates the reduced downclock for LVDS*/ |
| 1130 | int lvds_downclock; |
| 1131 | u16 orig_clock; |
| 1132 | |
| 1133 | bool mchbar_need_disable; |
| 1134 | |
| 1135 | struct intel_l3_parity l3_parity; |
| 1136 | |
| 1137 | /* gen6+ rps state */ |
| 1138 | struct intel_gen6_power_mgmt rps; |
| 1139 | |
| 1140 | /* ilk-only ips/rps state. Everything in here is protected by the global |
| 1141 | * mchdev_lock in intel_pm.c */ |
| 1142 | struct intel_ilk_power_mgmt ips; |
| 1143 | |
| 1144 | /* Haswell power well */ |
| 1145 | struct i915_power_well power_well; |
| 1146 | |
| 1147 | enum no_fbc_reason no_fbc_reason; |
| 1148 | |
| 1149 | struct drm_mm_node *compressed_fb; |
| 1150 | struct drm_mm_node *compressed_llb; |
| 1151 | |
| 1152 | struct i915_gpu_error gpu_error; |
| 1153 | |
| 1154 | struct drm_i915_gem_object *vlv_pctx; |
| 1155 | |
| 1156 | /* list of fbdev register on this device */ |
| 1157 | struct intel_fbdev *fbdev; |
| 1158 | |
| 1159 | /* |
| 1160 | * The console may be contended at resume, but we don't |
| 1161 | * want it to block on it. |
| 1162 | */ |
| 1163 | struct work_struct console_resume_work; |
| 1164 | |
| 1165 | struct drm_property *broadcast_rgb_property; |
| 1166 | struct drm_property *force_audio_property; |
| 1167 | |
| 1168 | bool hw_contexts_disabled; |
| 1169 | uint32_t hw_context_size; |
| 1170 | |
| 1171 | u32 fdi_rx_config; |
| 1172 | |
| 1173 | struct i915_suspend_saved_registers regfile; |
| 1174 | |
| 1175 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
| 1176 | * here! */ |
| 1177 | struct i915_dri1_state dri1; |
| 1178 | } drm_i915_private_t; |
| 1179 | |
| 1180 | /* Iterate over initialised rings */ |
| 1181 | #define for_each_ring(ring__, dev_priv__, i__) \ |
| 1182 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
| 1183 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
| 1184 | |
| 1185 | enum hdmi_force_audio { |
| 1186 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
| 1187 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
| 1188 | HDMI_AUDIO_AUTO, /* trust EDID */ |
| 1189 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
| 1190 | }; |
| 1191 | |
| 1192 | #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1) |
| 1193 | |
| 1194 | struct drm_i915_gem_object_ops { |
| 1195 | /* Interface between the GEM object and its backing storage. |
| 1196 | * get_pages() is called once prior to the use of the associated set |
| 1197 | * of pages before to binding them into the GTT, and put_pages() is |
| 1198 | * called after we no longer need them. As we expect there to be |
| 1199 | * associated cost with migrating pages between the backing storage |
| 1200 | * and making them available for the GPU (e.g. clflush), we may hold |
| 1201 | * onto the pages after they are no longer referenced by the GPU |
| 1202 | * in case they may be used again shortly (for example migrating the |
| 1203 | * pages to a different memory domain within the GTT). put_pages() |
| 1204 | * will therefore most likely be called when the object itself is |
| 1205 | * being released or under memory pressure (where we attempt to |
| 1206 | * reap pages for the shrinker). |
| 1207 | */ |
| 1208 | int (*get_pages)(struct drm_i915_gem_object *); |
| 1209 | void (*put_pages)(struct drm_i915_gem_object *); |
| 1210 | }; |
| 1211 | |
| 1212 | struct drm_i915_gem_object { |
| 1213 | struct drm_gem_object base; |
| 1214 | |
| 1215 | const struct drm_i915_gem_object_ops *ops; |
| 1216 | |
| 1217 | /** Current space allocated to this object in the GTT, if any. */ |
| 1218 | struct drm_mm_node *gtt_space; |
| 1219 | /** Stolen memory for this object, instead of being backed by shmem. */ |
| 1220 | struct drm_mm_node *stolen; |
| 1221 | struct list_head global_list; |
| 1222 | |
| 1223 | /** This object's place on the active/inactive lists */ |
| 1224 | struct list_head ring_list; |
| 1225 | struct list_head mm_list; |
| 1226 | /** This object's place in the batchbuffer or on the eviction list */ |
| 1227 | struct list_head exec_list; |
| 1228 | |
| 1229 | /** |
| 1230 | * This is set if the object is on the active lists (has pending |
| 1231 | * rendering and so a non-zero seqno), and is not set if it i s on |
| 1232 | * inactive (ready to be unbound) list. |
| 1233 | */ |
| 1234 | unsigned int active:1; |
| 1235 | |
| 1236 | /** |
| 1237 | * This is set if the object has been written to since last bound |
| 1238 | * to the GTT |
| 1239 | */ |
| 1240 | unsigned int dirty:1; |
| 1241 | |
| 1242 | /** |
| 1243 | * Fence register bits (if any) for this object. Will be set |
| 1244 | * as needed when mapped into the GTT. |
| 1245 | * Protected by dev->struct_mutex. |
| 1246 | */ |
| 1247 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
| 1248 | |
| 1249 | /** |
| 1250 | * Advice: are the backing pages purgeable? |
| 1251 | */ |
| 1252 | unsigned int madv:2; |
| 1253 | |
| 1254 | /** |
| 1255 | * Current tiling mode for the object. |
| 1256 | */ |
| 1257 | unsigned int tiling_mode:2; |
| 1258 | /** |
| 1259 | * Whether the tiling parameters for the currently associated fence |
| 1260 | * register have changed. Note that for the purposes of tracking |
| 1261 | * tiling changes we also treat the unfenced register, the register |
| 1262 | * slot that the object occupies whilst it executes a fenced |
| 1263 | * command (such as BLT on gen2/3), as a "fence". |
| 1264 | */ |
| 1265 | unsigned int fence_dirty:1; |
| 1266 | |
| 1267 | /** How many users have pinned this object in GTT space. The following |
| 1268 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 1269 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 1270 | * times for the same batchbuffer), and the framebuffer code. When |
| 1271 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 1272 | * pinned per crtc. |
| 1273 | * |
| 1274 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 1275 | * bits with absolutely no headroom. So use 4 bits. */ |
| 1276 | unsigned int pin_count:4; |
| 1277 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
| 1278 | |
| 1279 | /** |
| 1280 | * Is the object at the current location in the gtt mappable and |
| 1281 | * fenceable? Used to avoid costly recalculations. |
| 1282 | */ |
| 1283 | unsigned int map_and_fenceable:1; |
| 1284 | |
| 1285 | /** |
| 1286 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 1287 | * mappable by accident). Track pin and fault separate for a more |
| 1288 | * accurate mappable working set. |
| 1289 | */ |
| 1290 | unsigned int fault_mappable:1; |
| 1291 | unsigned int pin_mappable:1; |
| 1292 | |
| 1293 | /* |
| 1294 | * Is the GPU currently using a fence to access this buffer, |
| 1295 | */ |
| 1296 | unsigned int pending_fenced_gpu_access:1; |
| 1297 | unsigned int fenced_gpu_access:1; |
| 1298 | |
| 1299 | unsigned int cache_level:2; |
| 1300 | |
| 1301 | unsigned int has_aliasing_ppgtt_mapping:1; |
| 1302 | unsigned int has_global_gtt_mapping:1; |
| 1303 | unsigned int has_dma_mapping:1; |
| 1304 | |
| 1305 | struct sg_table *pages; |
| 1306 | int pages_pin_count; |
| 1307 | |
| 1308 | /* prime dma-buf support */ |
| 1309 | void *dma_buf_vmapping; |
| 1310 | int vmapping_count; |
| 1311 | |
| 1312 | /** |
| 1313 | * Used for performing relocations during execbuffer insertion. |
| 1314 | */ |
| 1315 | struct hlist_node exec_node; |
| 1316 | unsigned long exec_handle; |
| 1317 | struct drm_i915_gem_exec_object2 *exec_entry; |
| 1318 | |
| 1319 | /** |
| 1320 | * Current offset of the object in GTT space. |
| 1321 | * |
| 1322 | * This is the same as gtt_space->start |
| 1323 | */ |
| 1324 | uint32_t gtt_offset; |
| 1325 | |
| 1326 | struct intel_ring_buffer *ring; |
| 1327 | |
| 1328 | /** Breadcrumb of last rendering to the buffer. */ |
| 1329 | uint32_t last_read_seqno; |
| 1330 | uint32_t last_write_seqno; |
| 1331 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
| 1332 | uint32_t last_fenced_seqno; |
| 1333 | |
| 1334 | /** Current tiling stride for the object, if it's tiled. */ |
| 1335 | uint32_t stride; |
| 1336 | |
| 1337 | /** Record of address bit 17 of each page at last unbind. */ |
| 1338 | unsigned long *bit_17; |
| 1339 | |
| 1340 | /** User space pin count and filp owning the pin */ |
| 1341 | uint32_t user_pin_count; |
| 1342 | struct drm_file *pin_filp; |
| 1343 | |
| 1344 | /** for phy allocated objects */ |
| 1345 | struct drm_i915_gem_phys_object *phys_obj; |
| 1346 | }; |
| 1347 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
| 1348 | |
| 1349 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
| 1350 | |
| 1351 | /** |
| 1352 | * Request queue structure. |
| 1353 | * |
| 1354 | * The request queue allows us to note sequence numbers that have been emitted |
| 1355 | * and may be associated with active buffers to be retired. |
| 1356 | * |
| 1357 | * By keeping this list, we can avoid having to do questionable |
| 1358 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 1359 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 1360 | */ |
| 1361 | struct drm_i915_gem_request { |
| 1362 | /** On Which ring this request was generated */ |
| 1363 | struct intel_ring_buffer *ring; |
| 1364 | |
| 1365 | /** GEM sequence number associated with this request. */ |
| 1366 | uint32_t seqno; |
| 1367 | |
| 1368 | /** Position in the ringbuffer of the start of the request */ |
| 1369 | u32 head; |
| 1370 | |
| 1371 | /** Position in the ringbuffer of the end of the request */ |
| 1372 | u32 tail; |
| 1373 | |
| 1374 | /** Context related to this request */ |
| 1375 | struct i915_hw_context *ctx; |
| 1376 | |
| 1377 | /** Batch buffer related to this request if any */ |
| 1378 | struct drm_i915_gem_object *batch_obj; |
| 1379 | |
| 1380 | /** Time at which this request was emitted, in jiffies. */ |
| 1381 | unsigned long emitted_jiffies; |
| 1382 | |
| 1383 | /** global list entry for this request */ |
| 1384 | struct list_head list; |
| 1385 | |
| 1386 | struct drm_i915_file_private *file_priv; |
| 1387 | /** file_priv list entry for this request */ |
| 1388 | struct list_head client_list; |
| 1389 | }; |
| 1390 | |
| 1391 | struct drm_i915_file_private { |
| 1392 | struct { |
| 1393 | spinlock_t lock; |
| 1394 | struct list_head request_list; |
| 1395 | } mm; |
| 1396 | struct idr context_idr; |
| 1397 | |
| 1398 | struct i915_ctx_hang_stats hang_stats; |
| 1399 | }; |
| 1400 | |
| 1401 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
| 1402 | |
| 1403 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) |
| 1404 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) |
| 1405 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
| 1406 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) |
| 1407 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
| 1408 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
| 1409 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) |
| 1410 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 1411 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 1412 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
| 1413 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
| 1414 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
| 1415 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) |
| 1416 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) |
| 1417 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 1418 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
| 1419 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
| 1420 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) |
| 1421 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
| 1422 | #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ |
| 1423 | (dev)->pci_device == 0x0152 || \ |
| 1424 | (dev)->pci_device == 0x015a) |
| 1425 | #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ |
| 1426 | (dev)->pci_device == 0x0106 || \ |
| 1427 | (dev)->pci_device == 0x010A) |
| 1428 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
| 1429 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
| 1430 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
| 1431 | #define IS_ULT(dev) (IS_HASWELL(dev) && \ |
| 1432 | ((dev)->pci_device & 0xFF00) == 0x0A00) |
| 1433 | |
| 1434 | /* |
| 1435 | * The genX designation typically refers to the render engine, so render |
| 1436 | * capability related checks should use IS_GEN, while display and other checks |
| 1437 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
| 1438 | * chips, etc.). |
| 1439 | */ |
| 1440 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 1441 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 1442 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 1443 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 1444 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
| 1445 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
| 1446 | |
| 1447 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) |
| 1448 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) |
| 1449 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring) |
| 1450 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
| 1451 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 1452 | |
| 1453 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
| 1454 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
| 1455 | |
| 1456 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
| 1457 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 1458 | |
| 1459 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
| 1460 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
| 1461 | |
| 1462 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 1463 | * rows, which changed the alignment requirements and fence programming. |
| 1464 | */ |
| 1465 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 1466 | IS_I915GM(dev))) |
| 1467 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 1468 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 1469 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 1470 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) |
| 1471 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 1472 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
| 1473 | /* dsparb controlled by hw only */ |
| 1474 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
| 1475 | |
| 1476 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 1477 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
| 1478 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
| 1479 | |
| 1480 | #define HAS_IPS(dev) (IS_ULT(dev)) |
| 1481 | |
| 1482 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) |
| 1483 | |
| 1484 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
| 1485 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) |
| 1486 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
| 1487 | |
| 1488 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
| 1489 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 1490 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 1491 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
| 1492 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
| 1493 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
| 1494 | |
| 1495 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) |
| 1496 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
| 1497 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 1498 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
| 1499 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
| 1500 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
| 1501 | |
| 1502 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
| 1503 | |
| 1504 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 1505 | |
| 1506 | #define GT_FREQUENCY_MULTIPLIER 50 |
| 1507 | |
| 1508 | #include "i915_trace.h" |
| 1509 | |
| 1510 | /** |
| 1511 | * RC6 is a special power stage which allows the GPU to enter an very |
| 1512 | * low-voltage mode when idle, using down to 0V while at this stage. This |
| 1513 | * stage is entered automatically when the GPU is idle when RC6 support is |
| 1514 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
| 1515 | * |
| 1516 | * There are different RC6 modes available in Intel GPU, which differentiate |
| 1517 | * among each other with the latency required to enter and leave RC6 and |
| 1518 | * voltage consumed by the GPU in different states. |
| 1519 | * |
| 1520 | * The combination of the following flags define which states GPU is allowed |
| 1521 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
| 1522 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
| 1523 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
| 1524 | * which brings the most power savings; deeper states save more power, but |
| 1525 | * require higher latency to switch to and wake up. |
| 1526 | */ |
| 1527 | #define INTEL_RC6_ENABLE (1<<0) |
| 1528 | #define INTEL_RC6p_ENABLE (1<<1) |
| 1529 | #define INTEL_RC6pp_ENABLE (1<<2) |
| 1530 | |
| 1531 | extern struct drm_ioctl_desc i915_ioctls[]; |
| 1532 | extern int i915_max_ioctl; |
| 1533 | extern unsigned int i915_fbpercrtc __always_unused; |
| 1534 | extern int i915_panel_ignore_lid __read_mostly; |
| 1535 | extern unsigned int i915_powersave __read_mostly; |
| 1536 | extern int i915_semaphores __read_mostly; |
| 1537 | extern unsigned int i915_lvds_downclock __read_mostly; |
| 1538 | extern int i915_lvds_channel_mode __read_mostly; |
| 1539 | extern int i915_panel_use_ssc __read_mostly; |
| 1540 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
| 1541 | extern int i915_enable_rc6 __read_mostly; |
| 1542 | extern int i915_enable_fbc __read_mostly; |
| 1543 | extern bool i915_enable_hangcheck __read_mostly; |
| 1544 | extern int i915_enable_ppgtt __read_mostly; |
| 1545 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
| 1546 | extern int i915_disable_power_well __read_mostly; |
| 1547 | extern int i915_enable_ips __read_mostly; |
| 1548 | |
| 1549 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 1550 | extern int i915_resume(struct drm_device *dev); |
| 1551 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 1552 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 1553 | |
| 1554 | /* i915_dma.c */ |
| 1555 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
| 1556 | extern void i915_kernel_lost_context(struct drm_device * dev); |
| 1557 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
| 1558 | extern int i915_driver_unload(struct drm_device *); |
| 1559 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
| 1560 | extern void i915_driver_lastclose(struct drm_device * dev); |
| 1561 | extern void i915_driver_preclose(struct drm_device *dev, |
| 1562 | struct drm_file *file_priv); |
| 1563 | extern void i915_driver_postclose(struct drm_device *dev, |
| 1564 | struct drm_file *file_priv); |
| 1565 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
| 1566 | #ifdef CONFIG_COMPAT |
| 1567 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 1568 | unsigned long arg); |
| 1569 | #endif |
| 1570 | extern int i915_emit_box(struct drm_device *dev, |
| 1571 | struct drm_clip_rect *box, |
| 1572 | int DR1, int DR4); |
| 1573 | extern int intel_gpu_reset(struct drm_device *dev); |
| 1574 | extern int i915_reset(struct drm_device *dev); |
| 1575 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 1576 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 1577 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 1578 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 1579 | |
| 1580 | extern void intel_console_resume(struct work_struct *work); |
| 1581 | |
| 1582 | /* i915_irq.c */ |
| 1583 | void i915_hangcheck_elapsed(unsigned long data); |
| 1584 | void i915_handle_error(struct drm_device *dev, bool wedged); |
| 1585 | |
| 1586 | extern void intel_irq_init(struct drm_device *dev); |
| 1587 | extern void intel_hpd_init(struct drm_device *dev); |
| 1588 | extern void intel_gt_init(struct drm_device *dev); |
| 1589 | extern void intel_gt_reset(struct drm_device *dev); |
| 1590 | |
| 1591 | void i915_error_state_free(struct kref *error_ref); |
| 1592 | |
| 1593 | void |
| 1594 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 1595 | |
| 1596 | void |
| 1597 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); |
| 1598 | |
| 1599 | #ifdef CONFIG_DEBUG_FS |
| 1600 | extern void i915_destroy_error_state(struct drm_device *dev); |
| 1601 | #else |
| 1602 | #define i915_destroy_error_state(x) |
| 1603 | #endif |
| 1604 | |
| 1605 | |
| 1606 | /* i915_gem.c */ |
| 1607 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 1608 | struct drm_file *file_priv); |
| 1609 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1610 | struct drm_file *file_priv); |
| 1611 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1612 | struct drm_file *file_priv); |
| 1613 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1614 | struct drm_file *file_priv); |
| 1615 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1616 | struct drm_file *file_priv); |
| 1617 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1618 | struct drm_file *file_priv); |
| 1619 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1620 | struct drm_file *file_priv); |
| 1621 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1622 | struct drm_file *file_priv); |
| 1623 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1624 | struct drm_file *file_priv); |
| 1625 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1626 | struct drm_file *file_priv); |
| 1627 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1628 | struct drm_file *file_priv); |
| 1629 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1630 | struct drm_file *file_priv); |
| 1631 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1632 | struct drm_file *file_priv); |
| 1633 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 1634 | struct drm_file *file); |
| 1635 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 1636 | struct drm_file *file); |
| 1637 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 1638 | struct drm_file *file_priv); |
| 1639 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 1640 | struct drm_file *file_priv); |
| 1641 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 1642 | struct drm_file *file_priv); |
| 1643 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 1644 | struct drm_file *file_priv); |
| 1645 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 1646 | struct drm_file *file_priv); |
| 1647 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 1648 | struct drm_file *file_priv); |
| 1649 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 1650 | struct drm_file *file_priv); |
| 1651 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
| 1652 | struct drm_file *file_priv); |
| 1653 | void i915_gem_load(struct drm_device *dev); |
| 1654 | void *i915_gem_object_alloc(struct drm_device *dev); |
| 1655 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
| 1656 | int i915_gem_init_object(struct drm_gem_object *obj); |
| 1657 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 1658 | const struct drm_i915_gem_object_ops *ops); |
| 1659 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 1660 | size_t size); |
| 1661 | void i915_gem_free_object(struct drm_gem_object *obj); |
| 1662 | |
| 1663 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 1664 | uint32_t alignment, |
| 1665 | bool map_and_fenceable, |
| 1666 | bool nonblocking); |
| 1667 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
| 1668 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
| 1669 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
| 1670 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
| 1671 | void i915_gem_lastclose(struct drm_device *dev); |
| 1672 | |
| 1673 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
| 1674 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
| 1675 | { |
| 1676 | struct sg_page_iter sg_iter; |
| 1677 | |
| 1678 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
| 1679 | return sg_page_iter_page(&sg_iter); |
| 1680 | |
| 1681 | return NULL; |
| 1682 | } |
| 1683 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
| 1684 | { |
| 1685 | BUG_ON(obj->pages == NULL); |
| 1686 | obj->pages_pin_count++; |
| 1687 | } |
| 1688 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
| 1689 | { |
| 1690 | BUG_ON(obj->pages_pin_count == 0); |
| 1691 | obj->pages_pin_count--; |
| 1692 | } |
| 1693 | |
| 1694 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
| 1695 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 1696 | struct intel_ring_buffer *to); |
| 1697 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
| 1698 | struct intel_ring_buffer *ring); |
| 1699 | |
| 1700 | int i915_gem_dumb_create(struct drm_file *file_priv, |
| 1701 | struct drm_device *dev, |
| 1702 | struct drm_mode_create_dumb *args); |
| 1703 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
| 1704 | uint32_t handle, uint64_t *offset); |
| 1705 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, |
| 1706 | uint32_t handle); |
| 1707 | /** |
| 1708 | * Returns true if seq1 is later than seq2. |
| 1709 | */ |
| 1710 | static inline bool |
| 1711 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1712 | { |
| 1713 | return (int32_t)(seq1 - seq2) >= 0; |
| 1714 | } |
| 1715 | |
| 1716 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
| 1717 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
| 1718 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
| 1719 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
| 1720 | |
| 1721 | static inline bool |
| 1722 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 1723 | { |
| 1724 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1725 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1726 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
| 1727 | return true; |
| 1728 | } else |
| 1729 | return false; |
| 1730 | } |
| 1731 | |
| 1732 | static inline void |
| 1733 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 1734 | { |
| 1735 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1736 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1737 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
| 1738 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 1739 | } |
| 1740 | } |
| 1741 | |
| 1742 | void i915_gem_retire_requests(struct drm_device *dev); |
| 1743 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
| 1744 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
| 1745 | bool interruptible); |
| 1746 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
| 1747 | { |
| 1748 | return unlikely(atomic_read(&error->reset_counter) |
| 1749 | & I915_RESET_IN_PROGRESS_FLAG); |
| 1750 | } |
| 1751 | |
| 1752 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
| 1753 | { |
| 1754 | return atomic_read(&error->reset_counter) == I915_WEDGED; |
| 1755 | } |
| 1756 | |
| 1757 | void i915_gem_reset(struct drm_device *dev); |
| 1758 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
| 1759 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
| 1760 | uint32_t read_domains, |
| 1761 | uint32_t write_domain); |
| 1762 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
| 1763 | int __must_check i915_gem_init(struct drm_device *dev); |
| 1764 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
| 1765 | void i915_gem_l3_remap(struct drm_device *dev); |
| 1766 | void i915_gem_init_swizzling(struct drm_device *dev); |
| 1767 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
| 1768 | int __must_check i915_gpu_idle(struct drm_device *dev); |
| 1769 | int __must_check i915_gem_idle(struct drm_device *dev); |
| 1770 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 1771 | struct drm_file *file, |
| 1772 | struct drm_i915_gem_object *batch_obj, |
| 1773 | u32 *seqno); |
| 1774 | #define i915_add_request(ring, seqno) \ |
| 1775 | __i915_add_request(ring, NULL, NULL, seqno) |
| 1776 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
| 1777 | uint32_t seqno); |
| 1778 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
| 1779 | int __must_check |
| 1780 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 1781 | bool write); |
| 1782 | int __must_check |
| 1783 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
| 1784 | int __must_check |
| 1785 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 1786 | u32 alignment, |
| 1787 | struct intel_ring_buffer *pipelined); |
| 1788 | int i915_gem_attach_phys_object(struct drm_device *dev, |
| 1789 | struct drm_i915_gem_object *obj, |
| 1790 | int id, |
| 1791 | int align); |
| 1792 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 1793 | struct drm_i915_gem_object *obj); |
| 1794 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
| 1795 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
| 1796 | |
| 1797 | uint32_t |
| 1798 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
| 1799 | uint32_t |
| 1800 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1801 | int tiling_mode, bool fenced); |
| 1802 | |
| 1803 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 1804 | enum i915_cache_level cache_level); |
| 1805 | |
| 1806 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
| 1807 | struct dma_buf *dma_buf); |
| 1808 | |
| 1809 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
| 1810 | struct drm_gem_object *gem_obj, int flags); |
| 1811 | |
| 1812 | /* i915_gem_context.c */ |
| 1813 | void i915_gem_context_init(struct drm_device *dev); |
| 1814 | void i915_gem_context_fini(struct drm_device *dev); |
| 1815 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
| 1816 | int i915_switch_context(struct intel_ring_buffer *ring, |
| 1817 | struct drm_file *file, int to_id); |
| 1818 | void i915_gem_context_free(struct kref *ctx_ref); |
| 1819 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) |
| 1820 | { |
| 1821 | kref_get(&ctx->ref); |
| 1822 | } |
| 1823 | |
| 1824 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) |
| 1825 | { |
| 1826 | kref_put(&ctx->ref, i915_gem_context_free); |
| 1827 | } |
| 1828 | |
| 1829 | struct i915_ctx_hang_stats * __must_check |
| 1830 | i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring, |
| 1831 | struct drm_file *file, |
| 1832 | u32 id); |
| 1833 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 1834 | struct drm_file *file); |
| 1835 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 1836 | struct drm_file *file); |
| 1837 | |
| 1838 | /* i915_gem_gtt.c */ |
| 1839 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
| 1840 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
| 1841 | struct drm_i915_gem_object *obj, |
| 1842 | enum i915_cache_level cache_level); |
| 1843 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, |
| 1844 | struct drm_i915_gem_object *obj); |
| 1845 | |
| 1846 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
| 1847 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
| 1848 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
| 1849 | enum i915_cache_level cache_level); |
| 1850 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
| 1851 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
| 1852 | void i915_gem_init_global_gtt(struct drm_device *dev); |
| 1853 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
| 1854 | unsigned long mappable_end, unsigned long end); |
| 1855 | int i915_gem_gtt_init(struct drm_device *dev); |
| 1856 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
| 1857 | { |
| 1858 | if (INTEL_INFO(dev)->gen < 6) |
| 1859 | intel_gtt_chipset_flush(); |
| 1860 | } |
| 1861 | |
| 1862 | |
| 1863 | /* i915_gem_evict.c */ |
| 1864 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
| 1865 | unsigned alignment, |
| 1866 | unsigned cache_level, |
| 1867 | bool mappable, |
| 1868 | bool nonblock); |
| 1869 | int i915_gem_evict_everything(struct drm_device *dev); |
| 1870 | |
| 1871 | /* i915_gem_stolen.c */ |
| 1872 | int i915_gem_init_stolen(struct drm_device *dev); |
| 1873 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
| 1874 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
| 1875 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
| 1876 | struct drm_i915_gem_object * |
| 1877 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
| 1878 | struct drm_i915_gem_object * |
| 1879 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
| 1880 | u32 stolen_offset, |
| 1881 | u32 gtt_offset, |
| 1882 | u32 size); |
| 1883 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
| 1884 | |
| 1885 | /* i915_gem_tiling.c */ |
| 1886 | inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
| 1887 | { |
| 1888 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
| 1889 | |
| 1890 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 1891 | obj->tiling_mode != I915_TILING_NONE; |
| 1892 | } |
| 1893 | |
| 1894 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
| 1895 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 1896 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 1897 | |
| 1898 | /* i915_gem_debug.c */ |
| 1899 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
| 1900 | const char *where, uint32_t mark); |
| 1901 | #if WATCH_LISTS |
| 1902 | int i915_verify_lists(struct drm_device *dev); |
| 1903 | #else |
| 1904 | #define i915_verify_lists(dev) 0 |
| 1905 | #endif |
| 1906 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
| 1907 | int handle); |
| 1908 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
| 1909 | const char *where, uint32_t mark); |
| 1910 | |
| 1911 | /* i915_debugfs.c */ |
| 1912 | int i915_debugfs_init(struct drm_minor *minor); |
| 1913 | void i915_debugfs_cleanup(struct drm_minor *minor); |
| 1914 | __printf(2, 3) |
| 1915 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
| 1916 | |
| 1917 | /* i915_suspend.c */ |
| 1918 | extern int i915_save_state(struct drm_device *dev); |
| 1919 | extern int i915_restore_state(struct drm_device *dev); |
| 1920 | |
| 1921 | /* i915_ums.c */ |
| 1922 | void i915_save_display_reg(struct drm_device *dev); |
| 1923 | void i915_restore_display_reg(struct drm_device *dev); |
| 1924 | |
| 1925 | /* i915_sysfs.c */ |
| 1926 | void i915_setup_sysfs(struct drm_device *dev_priv); |
| 1927 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
| 1928 | |
| 1929 | /* intel_i2c.c */ |
| 1930 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 1931 | extern void intel_teardown_gmbus(struct drm_device *dev); |
| 1932 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
| 1933 | { |
| 1934 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
| 1935 | } |
| 1936 | |
| 1937 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
| 1938 | struct drm_i915_private *dev_priv, unsigned port); |
| 1939 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 1940 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
| 1941 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
| 1942 | { |
| 1943 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 1944 | } |
| 1945 | extern void intel_i2c_reset(struct drm_device *dev); |
| 1946 | |
| 1947 | /* intel_opregion.c */ |
| 1948 | extern int intel_opregion_setup(struct drm_device *dev); |
| 1949 | #ifdef CONFIG_ACPI |
| 1950 | extern void intel_opregion_init(struct drm_device *dev); |
| 1951 | extern void intel_opregion_fini(struct drm_device *dev); |
| 1952 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
| 1953 | #else |
| 1954 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 1955 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
| 1956 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
| 1957 | #endif |
| 1958 | |
| 1959 | /* intel_acpi.c */ |
| 1960 | #ifdef CONFIG_ACPI |
| 1961 | extern void intel_register_dsm_handler(void); |
| 1962 | extern void intel_unregister_dsm_handler(void); |
| 1963 | #else |
| 1964 | static inline void intel_register_dsm_handler(void) { return; } |
| 1965 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 1966 | #endif /* CONFIG_ACPI */ |
| 1967 | |
| 1968 | /* modesetting */ |
| 1969 | extern void intel_modeset_init_hw(struct drm_device *dev); |
| 1970 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
| 1971 | extern void intel_modeset_init(struct drm_device *dev); |
| 1972 | extern void intel_modeset_gem_init(struct drm_device *dev); |
| 1973 | extern void intel_modeset_cleanup(struct drm_device *dev); |
| 1974 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
| 1975 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 1976 | bool force_restore); |
| 1977 | extern void i915_redisable_vga(struct drm_device *dev); |
| 1978 | extern bool intel_fbc_enabled(struct drm_device *dev); |
| 1979 | extern void intel_disable_fbc(struct drm_device *dev); |
| 1980 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
| 1981 | extern void intel_init_pch_refclk(struct drm_device *dev); |
| 1982 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
| 1983 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
| 1984 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); |
| 1985 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); |
| 1986 | extern void intel_detect_pch(struct drm_device *dev); |
| 1987 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
| 1988 | extern int intel_enable_rc6(const struct drm_device *dev); |
| 1989 | |
| 1990 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
| 1991 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
| 1992 | struct drm_file *file); |
| 1993 | |
| 1994 | /* overlay */ |
| 1995 | #ifdef CONFIG_DEBUG_FS |
| 1996 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
| 1997 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
| 1998 | struct intel_overlay_error_state *error); |
| 1999 | |
| 2000 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
| 2001 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
| 2002 | struct drm_device *dev, |
| 2003 | struct intel_display_error_state *error); |
| 2004 | #endif |
| 2005 | |
| 2006 | /* On SNB platform, before reading ring registers forcewake bit |
| 2007 | * must be set to prevent GT core from power down and stale values being |
| 2008 | * returned. |
| 2009 | */ |
| 2010 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
| 2011 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); |
| 2012 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
| 2013 | |
| 2014 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
| 2015 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
| 2016 | |
| 2017 | /* intel_sideband.c */ |
| 2018 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
| 2019 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
| 2020 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
| 2021 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); |
| 2022 | void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); |
| 2023 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 2024 | enum intel_sbi_destination destination); |
| 2025 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 2026 | enum intel_sbi_destination destination); |
| 2027 | |
| 2028 | int vlv_gpu_freq(int ddr_freq, int val); |
| 2029 | int vlv_freq_opcode(int ddr_freq, int val); |
| 2030 | |
| 2031 | #define __i915_read(x, y) \ |
| 2032 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
| 2033 | |
| 2034 | __i915_read(8, b) |
| 2035 | __i915_read(16, w) |
| 2036 | __i915_read(32, l) |
| 2037 | __i915_read(64, q) |
| 2038 | #undef __i915_read |
| 2039 | |
| 2040 | #define __i915_write(x, y) \ |
| 2041 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
| 2042 | |
| 2043 | __i915_write(8, b) |
| 2044 | __i915_write(16, w) |
| 2045 | __i915_write(32, l) |
| 2046 | __i915_write(64, q) |
| 2047 | #undef __i915_write |
| 2048 | |
| 2049 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) |
| 2050 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) |
| 2051 | |
| 2052 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) |
| 2053 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) |
| 2054 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) |
| 2055 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) |
| 2056 | |
| 2057 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) |
| 2058 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) |
| 2059 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
| 2060 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) |
| 2061 | |
| 2062 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) |
| 2063 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) |
| 2064 | |
| 2065 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 2066 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 2067 | |
| 2068 | /* "Broadcast RGB" property */ |
| 2069 | #define INTEL_BROADCAST_RGB_AUTO 0 |
| 2070 | #define INTEL_BROADCAST_RGB_FULL 1 |
| 2071 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
| 2072 | |
| 2073 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
| 2074 | { |
| 2075 | if (HAS_PCH_SPLIT(dev)) |
| 2076 | return CPU_VGACNTRL; |
| 2077 | else if (IS_VALLEYVIEW(dev)) |
| 2078 | return VLV_VGACNTRL; |
| 2079 | else |
| 2080 | return VGACNTRL; |
| 2081 | } |
| 2082 | |
| 2083 | static inline void __user *to_user_ptr(u64 address) |
| 2084 | { |
| 2085 | return (void __user *)(uintptr_t)address; |
| 2086 | } |
| 2087 | |
| 2088 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
| 2089 | { |
| 2090 | unsigned long j = msecs_to_jiffies(m); |
| 2091 | |
| 2092 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2093 | } |
| 2094 | |
| 2095 | static inline unsigned long |
| 2096 | timespec_to_jiffies_timeout(const struct timespec *value) |
| 2097 | { |
| 2098 | unsigned long j = timespec_to_jiffies(value); |
| 2099 | |
| 2100 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2101 | } |
| 2102 | |
| 2103 | #endif |