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drm/i915: Use a device flag for non-interruptible phases
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include "i915_reg.h"
34#include "intel_bios.h"
35#include "intel_ringbuffer.h"
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/pm_qos_params.h>
39#include <drm/intel-gtt.h>
40
41/* General customization:
42 */
43
44#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45
46#define DRIVER_NAME "i915"
47#define DRIVER_DESC "Intel Graphics"
48#define DRIVER_DATE "20080730"
49
50enum pipe {
51 PIPE_A = 0,
52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
55};
56#define pipe_name(p) ((p) + 'A')
57
58enum plane {
59 PLANE_A = 0,
60 PLANE_B,
61 PLANE_C,
62};
63#define plane_name(p) ((p) + 'A')
64
65#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66
67#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
69/* Interface history:
70 *
71 * 1.1: Original.
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
78 */
79#define DRIVER_MAJOR 1
80#define DRIVER_MINOR 6
81#define DRIVER_PATCHLEVEL 0
82
83#define WATCH_COHERENCY 0
84#define WATCH_LISTS 0
85
86#define I915_GEM_PHYS_CURSOR_0 1
87#define I915_GEM_PHYS_CURSOR_1 2
88#define I915_GEM_PHYS_OVERLAY_REGS 3
89#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90
91struct drm_i915_gem_phys_object {
92 int id;
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
96};
97
98struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
104};
105
106struct opregion_header;
107struct opregion_acpi;
108struct opregion_swsci;
109struct opregion_asle;
110
111struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 void *vbt;
117 u32 __iomem *lid_state;
118};
119#define OPREGION_SIZE (8*1024)
120
121struct intel_overlay;
122struct intel_overlay_error_state;
123
124struct drm_i915_master_private {
125 drm_local_map_t *sarea;
126 struct _drm_i915_sarea *sarea_priv;
127};
128#define I915_FENCE_REG_NONE -1
129
130struct drm_i915_fence_reg {
131 struct list_head lru_list;
132 struct drm_i915_gem_object *obj;
133 uint32_t setup_seqno;
134};
135
136struct sdvo_device_mapping {
137 u8 initialized;
138 u8 dvo_port;
139 u8 slave_addr;
140 u8 dvo_wiring;
141 u8 i2c_pin;
142 u8 i2c_speed;
143 u8 ddc_pin;
144};
145
146struct intel_display_error_state;
147
148struct drm_i915_error_state {
149 u32 eir;
150 u32 pgtbl_er;
151 u32 pipestat[I915_MAX_PIPES];
152 u32 ipeir;
153 u32 ipehr;
154 u32 instdone;
155 u32 acthd;
156 u32 error; /* gen6+ */
157 u32 bcs_acthd; /* gen6+ blt engine */
158 u32 bcs_ipehr;
159 u32 bcs_ipeir;
160 u32 bcs_instdone;
161 u32 bcs_seqno;
162 u32 vcs_acthd; /* gen6+ bsd engine */
163 u32 vcs_ipehr;
164 u32 vcs_ipeir;
165 u32 vcs_instdone;
166 u32 vcs_seqno;
167 u32 instpm;
168 u32 instps;
169 u32 instdone1;
170 u32 seqno;
171 u64 bbaddr;
172 u64 fence[16];
173 struct timeval time;
174 struct drm_i915_error_object {
175 int page_count;
176 u32 gtt_offset;
177 u32 *pages[0];
178 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
179 struct drm_i915_error_buffer {
180 u32 size;
181 u32 name;
182 u32 seqno;
183 u32 gtt_offset;
184 u32 read_domains;
185 u32 write_domain;
186 s32 fence_reg:5;
187 s32 pinned:2;
188 u32 tiling:2;
189 u32 dirty:1;
190 u32 purgeable:1;
191 u32 ring:4;
192 u32 agp_type:1;
193 } *active_bo, *pinned_bo;
194 u32 active_bo_count, pinned_bo_count;
195 struct intel_overlay_error_state *overlay;
196 struct intel_display_error_state *display;
197};
198
199struct drm_i915_display_funcs {
200 void (*dpms)(struct drm_crtc *crtc, int mode);
201 bool (*fbc_enabled)(struct drm_device *dev);
202 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
203 void (*disable_fbc)(struct drm_device *dev);
204 int (*get_display_clock_speed)(struct drm_device *dev);
205 int (*get_fifo_size)(struct drm_device *dev, int plane);
206 void (*update_wm)(struct drm_device *dev);
207 /* clock updates for mode set */
208 /* cursor updates */
209 /* render clock increase/decrease */
210 /* display clock increase/decrease */
211 /* pll clock increase/decrease */
212 /* clock gating init */
213};
214
215struct intel_device_info {
216 u8 gen;
217 u8 is_mobile : 1;
218 u8 is_i85x : 1;
219 u8 is_i915g : 1;
220 u8 is_i945gm : 1;
221 u8 is_g33 : 1;
222 u8 need_gfx_hws : 1;
223 u8 is_g4x : 1;
224 u8 is_pineview : 1;
225 u8 is_broadwater : 1;
226 u8 is_crestline : 1;
227 u8 has_fbc : 1;
228 u8 has_pipe_cxsr : 1;
229 u8 has_hotplug : 1;
230 u8 cursor_needs_physical : 1;
231 u8 has_overlay : 1;
232 u8 overlay_needs_physical : 1;
233 u8 supports_tv : 1;
234 u8 has_bsd_ring : 1;
235 u8 has_blt_ring : 1;
236};
237
238enum no_fbc_reason {
239 FBC_NO_OUTPUT, /* no outputs enabled to compress */
240 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
241 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
242 FBC_MODE_TOO_LARGE, /* mode too large for compression */
243 FBC_BAD_PLANE, /* fbc not supported on plane */
244 FBC_NOT_TILED, /* buffer not tiled */
245 FBC_MULTIPLE_PIPES, /* more than one pipe active */
246};
247
248enum intel_pch {
249 PCH_IBX, /* Ibexpeak PCH */
250 PCH_CPT, /* Cougarpoint PCH */
251};
252
253#define QUIRK_PIPEA_FORCE (1<<0)
254
255struct intel_fbdev;
256
257typedef struct drm_i915_private {
258 struct drm_device *dev;
259
260 const struct intel_device_info *info;
261
262 int has_gem;
263 int relative_constants_mode;
264
265 void __iomem *regs;
266
267 struct intel_gmbus {
268 struct i2c_adapter adapter;
269 struct i2c_adapter *force_bit;
270 u32 reg0;
271 } *gmbus;
272
273 struct pci_dev *bridge_dev;
274 struct intel_ring_buffer ring[I915_NUM_RINGS];
275 uint32_t next_seqno;
276
277 drm_dma_handle_t *status_page_dmah;
278 dma_addr_t dma_status_page;
279 uint32_t counter;
280 drm_local_map_t hws_map;
281 struct drm_i915_gem_object *pwrctx;
282 struct drm_i915_gem_object *renderctx;
283
284 struct resource mch_res;
285
286 unsigned int cpp;
287 int back_offset;
288 int front_offset;
289 int current_page;
290 int page_flipping;
291
292 atomic_t irq_received;
293
294 /* protects the irq masks */
295 spinlock_t irq_lock;
296 /** Cached value of IMR to avoid reads in updating the bitfield */
297 u32 pipestat[2];
298 u32 irq_mask;
299 u32 gt_irq_mask;
300 u32 pch_irq_mask;
301
302 u32 hotplug_supported_mask;
303 struct work_struct hotplug_work;
304
305 int tex_lru_log_granularity;
306 int allow_batchbuffer;
307 struct mem_block *agp_heap;
308 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
309 int vblank_pipe;
310 int num_pipe;
311
312 atomic_t vblank_enabled;
313 struct pm_qos_request_list vblank_pm_qos;
314 struct work_struct vblank_work;
315
316 /* For hangcheck timer */
317#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
318 struct timer_list hangcheck_timer;
319 int hangcheck_count;
320 uint32_t last_acthd;
321 uint32_t last_instdone;
322 uint32_t last_instdone1;
323
324 unsigned long cfb_size;
325 unsigned long cfb_pitch;
326 unsigned long cfb_offset;
327 int cfb_fence;
328 int cfb_plane;
329 int cfb_y;
330
331 struct intel_opregion opregion;
332
333 /* overlay */
334 struct intel_overlay *overlay;
335
336 /* LVDS info */
337 int backlight_level; /* restore backlight to this value */
338 bool backlight_enabled;
339 struct drm_display_mode *panel_fixed_mode;
340 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
341 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
342
343 /* Feature bits from the VBIOS */
344 unsigned int int_tv_support:1;
345 unsigned int lvds_dither:1;
346 unsigned int lvds_vbt:1;
347 unsigned int int_crt_support:1;
348 unsigned int lvds_use_ssc:1;
349 int lvds_ssc_freq;
350 struct {
351 int rate;
352 int lanes;
353 int preemphasis;
354 int vswing;
355
356 bool initialized;
357 bool support;
358 int bpp;
359 struct edp_power_seq pps;
360 } edp;
361 bool no_aux_handshake;
362
363 struct notifier_block lid_notifier;
364
365 int crt_ddc_pin;
366 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
367 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
368 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
369
370 unsigned int fsb_freq, mem_freq, is_ddr3;
371
372 spinlock_t error_lock;
373 struct drm_i915_error_state *first_error;
374 struct work_struct error_work;
375 struct completion error_completion;
376 struct workqueue_struct *wq;
377
378 /* Display functions */
379 struct drm_i915_display_funcs display;
380
381 /* PCH chipset type */
382 enum intel_pch pch_type;
383
384 unsigned long quirks;
385
386 /* Register state */
387 bool modeset_on_lid;
388 u8 saveLBB;
389 u32 saveDSPACNTR;
390 u32 saveDSPBCNTR;
391 u32 saveDSPARB;
392 u32 saveHWS;
393 u32 savePIPEACONF;
394 u32 savePIPEBCONF;
395 u32 savePIPEASRC;
396 u32 savePIPEBSRC;
397 u32 saveFPA0;
398 u32 saveFPA1;
399 u32 saveDPLL_A;
400 u32 saveDPLL_A_MD;
401 u32 saveHTOTAL_A;
402 u32 saveHBLANK_A;
403 u32 saveHSYNC_A;
404 u32 saveVTOTAL_A;
405 u32 saveVBLANK_A;
406 u32 saveVSYNC_A;
407 u32 saveBCLRPAT_A;
408 u32 saveTRANSACONF;
409 u32 saveTRANS_HTOTAL_A;
410 u32 saveTRANS_HBLANK_A;
411 u32 saveTRANS_HSYNC_A;
412 u32 saveTRANS_VTOTAL_A;
413 u32 saveTRANS_VBLANK_A;
414 u32 saveTRANS_VSYNC_A;
415 u32 savePIPEASTAT;
416 u32 saveDSPASTRIDE;
417 u32 saveDSPASIZE;
418 u32 saveDSPAPOS;
419 u32 saveDSPAADDR;
420 u32 saveDSPASURF;
421 u32 saveDSPATILEOFF;
422 u32 savePFIT_PGM_RATIOS;
423 u32 saveBLC_HIST_CTL;
424 u32 saveBLC_PWM_CTL;
425 u32 saveBLC_PWM_CTL2;
426 u32 saveBLC_CPU_PWM_CTL;
427 u32 saveBLC_CPU_PWM_CTL2;
428 u32 saveFPB0;
429 u32 saveFPB1;
430 u32 saveDPLL_B;
431 u32 saveDPLL_B_MD;
432 u32 saveHTOTAL_B;
433 u32 saveHBLANK_B;
434 u32 saveHSYNC_B;
435 u32 saveVTOTAL_B;
436 u32 saveVBLANK_B;
437 u32 saveVSYNC_B;
438 u32 saveBCLRPAT_B;
439 u32 saveTRANSBCONF;
440 u32 saveTRANS_HTOTAL_B;
441 u32 saveTRANS_HBLANK_B;
442 u32 saveTRANS_HSYNC_B;
443 u32 saveTRANS_VTOTAL_B;
444 u32 saveTRANS_VBLANK_B;
445 u32 saveTRANS_VSYNC_B;
446 u32 savePIPEBSTAT;
447 u32 saveDSPBSTRIDE;
448 u32 saveDSPBSIZE;
449 u32 saveDSPBPOS;
450 u32 saveDSPBADDR;
451 u32 saveDSPBSURF;
452 u32 saveDSPBTILEOFF;
453 u32 saveVGA0;
454 u32 saveVGA1;
455 u32 saveVGA_PD;
456 u32 saveVGACNTRL;
457 u32 saveADPA;
458 u32 saveLVDS;
459 u32 savePP_ON_DELAYS;
460 u32 savePP_OFF_DELAYS;
461 u32 saveDVOA;
462 u32 saveDVOB;
463 u32 saveDVOC;
464 u32 savePP_ON;
465 u32 savePP_OFF;
466 u32 savePP_CONTROL;
467 u32 savePP_DIVISOR;
468 u32 savePFIT_CONTROL;
469 u32 save_palette_a[256];
470 u32 save_palette_b[256];
471 u32 saveDPFC_CB_BASE;
472 u32 saveFBC_CFB_BASE;
473 u32 saveFBC_LL_BASE;
474 u32 saveFBC_CONTROL;
475 u32 saveFBC_CONTROL2;
476 u32 saveIER;
477 u32 saveIIR;
478 u32 saveIMR;
479 u32 saveDEIER;
480 u32 saveDEIMR;
481 u32 saveGTIER;
482 u32 saveGTIMR;
483 u32 saveFDI_RXA_IMR;
484 u32 saveFDI_RXB_IMR;
485 u32 saveCACHE_MODE_0;
486 u32 saveMI_ARB_STATE;
487 u32 saveSWF0[16];
488 u32 saveSWF1[16];
489 u32 saveSWF2[3];
490 u8 saveMSR;
491 u8 saveSR[8];
492 u8 saveGR[25];
493 u8 saveAR_INDEX;
494 u8 saveAR[21];
495 u8 saveDACMASK;
496 u8 saveCR[37];
497 uint64_t saveFENCE[16];
498 u32 saveCURACNTR;
499 u32 saveCURAPOS;
500 u32 saveCURABASE;
501 u32 saveCURBCNTR;
502 u32 saveCURBPOS;
503 u32 saveCURBBASE;
504 u32 saveCURSIZE;
505 u32 saveDP_B;
506 u32 saveDP_C;
507 u32 saveDP_D;
508 u32 savePIPEA_GMCH_DATA_M;
509 u32 savePIPEB_GMCH_DATA_M;
510 u32 savePIPEA_GMCH_DATA_N;
511 u32 savePIPEB_GMCH_DATA_N;
512 u32 savePIPEA_DP_LINK_M;
513 u32 savePIPEB_DP_LINK_M;
514 u32 savePIPEA_DP_LINK_N;
515 u32 savePIPEB_DP_LINK_N;
516 u32 saveFDI_RXA_CTL;
517 u32 saveFDI_TXA_CTL;
518 u32 saveFDI_RXB_CTL;
519 u32 saveFDI_TXB_CTL;
520 u32 savePFA_CTL_1;
521 u32 savePFB_CTL_1;
522 u32 savePFA_WIN_SZ;
523 u32 savePFB_WIN_SZ;
524 u32 savePFA_WIN_POS;
525 u32 savePFB_WIN_POS;
526 u32 savePCH_DREF_CONTROL;
527 u32 saveDISP_ARB_CTL;
528 u32 savePIPEA_DATA_M1;
529 u32 savePIPEA_DATA_N1;
530 u32 savePIPEA_LINK_M1;
531 u32 savePIPEA_LINK_N1;
532 u32 savePIPEB_DATA_M1;
533 u32 savePIPEB_DATA_N1;
534 u32 savePIPEB_LINK_M1;
535 u32 savePIPEB_LINK_N1;
536 u32 saveMCHBAR_RENDER_STANDBY;
537
538 struct {
539 /** Bridge to intel-gtt-ko */
540 const struct intel_gtt *gtt;
541 /** Memory allocator for GTT stolen memory */
542 struct drm_mm stolen;
543 /** Memory allocator for GTT */
544 struct drm_mm gtt_space;
545 /** List of all objects in gtt_space. Used to restore gtt
546 * mappings on resume */
547 struct list_head gtt_list;
548
549 /** Usable portion of the GTT for GEM */
550 unsigned long gtt_start;
551 unsigned long gtt_mappable_end;
552 unsigned long gtt_end;
553
554 struct io_mapping *gtt_mapping;
555 int gtt_mtrr;
556
557 struct shrinker inactive_shrinker;
558
559 /**
560 * List of objects currently involved in rendering.
561 *
562 * Includes buffers having the contents of their GPU caches
563 * flushed, not necessarily primitives. last_rendering_seqno
564 * represents when the rendering involved will be completed.
565 *
566 * A reference is held on the buffer while on this list.
567 */
568 struct list_head active_list;
569
570 /**
571 * List of objects which are not in the ringbuffer but which
572 * still have a write_domain which needs to be flushed before
573 * unbinding.
574 *
575 * last_rendering_seqno is 0 while an object is in this list.
576 *
577 * A reference is held on the buffer while on this list.
578 */
579 struct list_head flushing_list;
580
581 /**
582 * LRU list of objects which are not in the ringbuffer and
583 * are ready to unbind, but are still in the GTT.
584 *
585 * last_rendering_seqno is 0 while an object is in this list.
586 *
587 * A reference is not held on the buffer while on this list,
588 * as merely being GTT-bound shouldn't prevent its being
589 * freed, and we'll pull it off the list in the free path.
590 */
591 struct list_head inactive_list;
592
593 /**
594 * LRU list of objects which are not in the ringbuffer but
595 * are still pinned in the GTT.
596 */
597 struct list_head pinned_list;
598
599 /** LRU list of objects with fence regs on them. */
600 struct list_head fence_list;
601
602 /**
603 * List of objects currently pending being freed.
604 *
605 * These objects are no longer in use, but due to a signal
606 * we were prevented from freeing them at the appointed time.
607 */
608 struct list_head deferred_free_list;
609
610 /**
611 * We leave the user IRQ off as much as possible,
612 * but this means that requests will finish and never
613 * be retired once the system goes idle. Set a timer to
614 * fire periodically while the ring is running. When it
615 * fires, go retire requests.
616 */
617 struct delayed_work retire_work;
618
619 /**
620 * Are we in a non-interruptible section of code like
621 * modesetting?
622 */
623 bool interruptible;
624
625 /**
626 * Flag if the X Server, and thus DRM, is not currently in
627 * control of the device.
628 *
629 * This is set between LeaveVT and EnterVT. It needs to be
630 * replaced with a semaphore. It also needs to be
631 * transitioned away from for kernel modesetting.
632 */
633 int suspended;
634
635 /**
636 * Flag if the hardware appears to be wedged.
637 *
638 * This is set when attempts to idle the device timeout.
639 * It prevents command submission from occuring and makes
640 * every pending request fail
641 */
642 atomic_t wedged;
643
644 /** Bit 6 swizzling required for X tiling */
645 uint32_t bit_6_swizzle_x;
646 /** Bit 6 swizzling required for Y tiling */
647 uint32_t bit_6_swizzle_y;
648
649 /* storage for physical objects */
650 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
651
652 /* accounting, useful for userland debugging */
653 size_t gtt_total;
654 size_t mappable_gtt_total;
655 size_t object_memory;
656 u32 object_count;
657 } mm;
658 struct sdvo_device_mapping sdvo_mappings[2];
659 /* indicate whether the LVDS_BORDER should be enabled or not */
660 unsigned int lvds_border_bits;
661 /* Panel fitter placement and size for Ironlake+ */
662 u32 pch_pf_pos, pch_pf_size;
663 int panel_t3, panel_t12;
664
665 struct drm_crtc *plane_to_crtc_mapping[2];
666 struct drm_crtc *pipe_to_crtc_mapping[2];
667 wait_queue_head_t pending_flip_queue;
668 bool flip_pending_is_done;
669
670 /* Reclocking support */
671 bool render_reclock_avail;
672 bool lvds_downclock_avail;
673 /* indicates the reduced downclock for LVDS*/
674 int lvds_downclock;
675 struct work_struct idle_work;
676 struct timer_list idle_timer;
677 bool busy;
678 u16 orig_clock;
679 int child_dev_num;
680 struct child_device_config *child_dev;
681 struct drm_connector *int_lvds_connector;
682
683 bool mchbar_need_disable;
684
685 u8 cur_delay;
686 u8 min_delay;
687 u8 max_delay;
688 u8 fmax;
689 u8 fstart;
690
691 u64 last_count1;
692 unsigned long last_time1;
693 u64 last_count2;
694 struct timespec last_time2;
695 unsigned long gfx_power;
696 int c_m;
697 int r_t;
698 u8 corr;
699 spinlock_t *mchdev_lock;
700
701 enum no_fbc_reason no_fbc_reason;
702
703 struct drm_mm_node *compressed_fb;
704 struct drm_mm_node *compressed_llb;
705
706 unsigned long last_gpu_reset;
707
708 /* list of fbdev register on this device */
709 struct intel_fbdev *fbdev;
710} drm_i915_private_t;
711
712struct drm_i915_gem_object {
713 struct drm_gem_object base;
714
715 /** Current space allocated to this object in the GTT, if any. */
716 struct drm_mm_node *gtt_space;
717 struct list_head gtt_list;
718
719 /** This object's place on the active/flushing/inactive lists */
720 struct list_head ring_list;
721 struct list_head mm_list;
722 /** This object's place on GPU write list */
723 struct list_head gpu_write_list;
724 /** This object's place in the batchbuffer or on the eviction list */
725 struct list_head exec_list;
726
727 /**
728 * This is set if the object is on the active or flushing lists
729 * (has pending rendering), and is not set if it's on inactive (ready
730 * to be unbound).
731 */
732 unsigned int active : 1;
733
734 /**
735 * This is set if the object has been written to since last bound
736 * to the GTT
737 */
738 unsigned int dirty : 1;
739
740 /**
741 * This is set if the object has been written to since the last
742 * GPU flush.
743 */
744 unsigned int pending_gpu_write : 1;
745
746 /**
747 * Fence register bits (if any) for this object. Will be set
748 * as needed when mapped into the GTT.
749 * Protected by dev->struct_mutex.
750 *
751 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
752 */
753 signed int fence_reg : 5;
754
755 /**
756 * Advice: are the backing pages purgeable?
757 */
758 unsigned int madv : 2;
759
760 /**
761 * Current tiling mode for the object.
762 */
763 unsigned int tiling_mode : 2;
764 unsigned int tiling_changed : 1;
765
766 /** How many users have pinned this object in GTT space. The following
767 * users can each hold at most one reference: pwrite/pread, pin_ioctl
768 * (via user_pin_count), execbuffer (objects are not allowed multiple
769 * times for the same batchbuffer), and the framebuffer code. When
770 * switching/pageflipping, the framebuffer code has at most two buffers
771 * pinned per crtc.
772 *
773 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
774 * bits with absolutely no headroom. So use 4 bits. */
775 unsigned int pin_count : 4;
776#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
777
778 /**
779 * Is the object at the current location in the gtt mappable and
780 * fenceable? Used to avoid costly recalculations.
781 */
782 unsigned int map_and_fenceable : 1;
783
784 /**
785 * Whether the current gtt mapping needs to be mappable (and isn't just
786 * mappable by accident). Track pin and fault separate for a more
787 * accurate mappable working set.
788 */
789 unsigned int fault_mappable : 1;
790 unsigned int pin_mappable : 1;
791
792 /*
793 * Is the GPU currently using a fence to access this buffer,
794 */
795 unsigned int pending_fenced_gpu_access:1;
796 unsigned int fenced_gpu_access:1;
797
798 struct page **pages;
799
800 /**
801 * DMAR support
802 */
803 struct scatterlist *sg_list;
804 int num_sg;
805
806 /**
807 * Used for performing relocations during execbuffer insertion.
808 */
809 struct hlist_node exec_node;
810 unsigned long exec_handle;
811 struct drm_i915_gem_exec_object2 *exec_entry;
812
813 /**
814 * Current offset of the object in GTT space.
815 *
816 * This is the same as gtt_space->start
817 */
818 uint32_t gtt_offset;
819
820 /** Breadcrumb of last rendering to the buffer. */
821 uint32_t last_rendering_seqno;
822 struct intel_ring_buffer *ring;
823
824 /** Breadcrumb of last fenced GPU access to the buffer. */
825 uint32_t last_fenced_seqno;
826 struct intel_ring_buffer *last_fenced_ring;
827
828 /** Current tiling stride for the object, if it's tiled. */
829 uint32_t stride;
830
831 /** Record of address bit 17 of each page at last unbind. */
832 unsigned long *bit_17;
833
834 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
835 uint32_t agp_type;
836
837 /**
838 * If present, while GEM_DOMAIN_CPU is in the read domain this array
839 * flags which individual pages are valid.
840 */
841 uint8_t *page_cpu_valid;
842
843 /** User space pin count and filp owning the pin */
844 uint32_t user_pin_count;
845 struct drm_file *pin_filp;
846
847 /** for phy allocated objects */
848 struct drm_i915_gem_phys_object *phys_obj;
849
850 /**
851 * Number of crtcs where this object is currently the fb, but
852 * will be page flipped away on the next vblank. When it
853 * reaches 0, dev_priv->pending_flip_queue will be woken up.
854 */
855 atomic_t pending_flip;
856};
857
858#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
859
860/**
861 * Request queue structure.
862 *
863 * The request queue allows us to note sequence numbers that have been emitted
864 * and may be associated with active buffers to be retired.
865 *
866 * By keeping this list, we can avoid having to do questionable
867 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
868 * an emission time with seqnos for tracking how far ahead of the GPU we are.
869 */
870struct drm_i915_gem_request {
871 /** On Which ring this request was generated */
872 struct intel_ring_buffer *ring;
873
874 /** GEM sequence number associated with this request. */
875 uint32_t seqno;
876
877 /** Time at which this request was emitted, in jiffies. */
878 unsigned long emitted_jiffies;
879
880 /** global list entry for this request */
881 struct list_head list;
882
883 struct drm_i915_file_private *file_priv;
884 /** file_priv list entry for this request */
885 struct list_head client_list;
886};
887
888struct drm_i915_file_private {
889 struct {
890 struct spinlock lock;
891 struct list_head request_list;
892 } mm;
893};
894
895enum intel_chip_family {
896 CHIP_I8XX = 0x01,
897 CHIP_I9XX = 0x02,
898 CHIP_I915 = 0x04,
899 CHIP_I965 = 0x08,
900};
901
902#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
903
904#define IS_I830(dev) ((dev)->pci_device == 0x3577)
905#define IS_845G(dev) ((dev)->pci_device == 0x2562)
906#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
907#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
908#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
909#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
910#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
911#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
912#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
913#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
914#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
915#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
916#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
917#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
918#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
919#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
920#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
921#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
922#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
923
924#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
925#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
926#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
927#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
928#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
929
930#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
931#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
932#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
933
934#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
935#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
936
937/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
938 * rows, which changed the alignment requirements and fence programming.
939 */
940#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
941 IS_I915GM(dev)))
942#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
943#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
944#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
945#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
946#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
947#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
948/* dsparb controlled by hw only */
949#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
950
951#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
952#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
953#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
954
955#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
956#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
957
958#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
959#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
960#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
961
962#include "i915_trace.h"
963
964extern struct drm_ioctl_desc i915_ioctls[];
965extern int i915_max_ioctl;
966extern unsigned int i915_fbpercrtc;
967extern int i915_panel_ignore_lid;
968extern unsigned int i915_powersave;
969extern unsigned int i915_lvds_downclock;
970extern unsigned int i915_panel_use_ssc;
971extern int i915_vbt_sdvo_panel_type;
972extern unsigned int i915_enable_rc6;
973
974extern int i915_suspend(struct drm_device *dev, pm_message_t state);
975extern int i915_resume(struct drm_device *dev);
976extern void i915_save_display(struct drm_device *dev);
977extern void i915_restore_display(struct drm_device *dev);
978extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
979extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
980
981 /* i915_dma.c */
982extern void i915_kernel_lost_context(struct drm_device * dev);
983extern int i915_driver_load(struct drm_device *, unsigned long flags);
984extern int i915_driver_unload(struct drm_device *);
985extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
986extern void i915_driver_lastclose(struct drm_device * dev);
987extern void i915_driver_preclose(struct drm_device *dev,
988 struct drm_file *file_priv);
989extern void i915_driver_postclose(struct drm_device *dev,
990 struct drm_file *file_priv);
991extern int i915_driver_device_is_agp(struct drm_device * dev);
992extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
993 unsigned long arg);
994extern int i915_emit_box(struct drm_device *dev,
995 struct drm_clip_rect *box,
996 int DR1, int DR4);
997extern int i915_reset(struct drm_device *dev, u8 flags);
998extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
999extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1000extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1001extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1002
1003
1004/* i915_irq.c */
1005void i915_hangcheck_elapsed(unsigned long data);
1006void i915_handle_error(struct drm_device *dev, bool wedged);
1007extern int i915_irq_emit(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv);
1009extern int i915_irq_wait(struct drm_device *dev, void *data,
1010 struct drm_file *file_priv);
1011
1012extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1013extern void i915_driver_irq_preinstall(struct drm_device * dev);
1014extern int i915_driver_irq_postinstall(struct drm_device *dev);
1015extern void i915_driver_irq_uninstall(struct drm_device * dev);
1016extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv);
1018extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1019 struct drm_file *file_priv);
1020extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1021extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1022extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1023extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1024extern int i915_vblank_swap(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv);
1026
1027void
1028i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1029
1030void
1031i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1032
1033void intel_enable_asle (struct drm_device *dev);
1034int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1035 int *max_error,
1036 struct timeval *vblank_time,
1037 unsigned flags);
1038
1039int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1040 int *vpos, int *hpos);
1041
1042#ifdef CONFIG_DEBUG_FS
1043extern void i915_destroy_error_state(struct drm_device *dev);
1044#else
1045#define i915_destroy_error_state(x)
1046#endif
1047
1048
1049/* i915_mem.c */
1050extern int i915_mem_alloc(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv);
1052extern int i915_mem_free(struct drm_device *dev, void *data,
1053 struct drm_file *file_priv);
1054extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv);
1056extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1057 struct drm_file *file_priv);
1058extern void i915_mem_takedown(struct mem_block **heap);
1059extern void i915_mem_release(struct drm_device * dev,
1060 struct drm_file *file_priv, struct mem_block *heap);
1061/* i915_gem.c */
1062int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1063 struct drm_file *file_priv);
1064int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1065 struct drm_file *file_priv);
1066int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv);
1068int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv);
1070int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1071 struct drm_file *file_priv);
1072int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1073 struct drm_file *file_priv);
1074int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv);
1076int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078int i915_gem_execbuffer(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv);
1080int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv);
1082int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1084int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1085 struct drm_file *file_priv);
1086int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv);
1096int i915_gem_set_tiling(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv);
1098int i915_gem_get_tiling(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv);
1102void i915_gem_load(struct drm_device *dev);
1103int i915_gem_init_object(struct drm_gem_object *obj);
1104int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1105 uint32_t invalidate_domains,
1106 uint32_t flush_domains);
1107struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1108 size_t size);
1109void i915_gem_free_object(struct drm_gem_object *obj);
1110int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1111 uint32_t alignment,
1112 bool map_and_fenceable);
1113void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1114int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1115void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1116void i915_gem_lastclose(struct drm_device *dev);
1117
1118int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1119int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1120void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1121 struct intel_ring_buffer *ring,
1122 u32 seqno);
1123
1124/**
1125 * Returns true if seq1 is later than seq2.
1126 */
1127static inline bool
1128i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1129{
1130 return (int32_t)(seq1 - seq2) >= 0;
1131}
1132
1133static inline u32
1134i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1135{
1136 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1137 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1138}
1139
1140int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1141 struct intel_ring_buffer *pipelined);
1142int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1143
1144void i915_gem_retire_requests(struct drm_device *dev);
1145void i915_gem_reset(struct drm_device *dev);
1146void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1147int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1148 uint32_t read_domains,
1149 uint32_t write_domain);
1150int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
1151int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1152void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1153void i915_gem_do_init(struct drm_device *dev,
1154 unsigned long start,
1155 unsigned long mappable_end,
1156 unsigned long end);
1157int __must_check i915_gpu_idle(struct drm_device *dev);
1158int __must_check i915_gem_idle(struct drm_device *dev);
1159int __must_check i915_add_request(struct intel_ring_buffer *ring,
1160 struct drm_file *file,
1161 struct drm_i915_gem_request *request);
1162int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1163 uint32_t seqno);
1164int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1165int __must_check
1166i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1167 bool write);
1168int __must_check
1169i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1170 struct intel_ring_buffer *pipelined);
1171int i915_gem_attach_phys_object(struct drm_device *dev,
1172 struct drm_i915_gem_object *obj,
1173 int id,
1174 int align);
1175void i915_gem_detach_phys_object(struct drm_device *dev,
1176 struct drm_i915_gem_object *obj);
1177void i915_gem_free_all_phys_object(struct drm_device *dev);
1178void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1179
1180/* i915_gem_gtt.c */
1181void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1182int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1183void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1184
1185/* i915_gem_evict.c */
1186int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1187 unsigned alignment, bool mappable);
1188int __must_check i915_gem_evict_everything(struct drm_device *dev,
1189 bool purgeable_only);
1190int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1191 bool purgeable_only);
1192
1193/* i915_gem_tiling.c */
1194void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1195void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1196void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1197
1198/* i915_gem_debug.c */
1199void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1200 const char *where, uint32_t mark);
1201#if WATCH_LISTS
1202int i915_verify_lists(struct drm_device *dev);
1203#else
1204#define i915_verify_lists(dev) 0
1205#endif
1206void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1207 int handle);
1208void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1209 const char *where, uint32_t mark);
1210
1211/* i915_debugfs.c */
1212int i915_debugfs_init(struct drm_minor *minor);
1213void i915_debugfs_cleanup(struct drm_minor *minor);
1214
1215/* i915_suspend.c */
1216extern int i915_save_state(struct drm_device *dev);
1217extern int i915_restore_state(struct drm_device *dev);
1218
1219/* i915_suspend.c */
1220extern int i915_save_state(struct drm_device *dev);
1221extern int i915_restore_state(struct drm_device *dev);
1222
1223/* intel_i2c.c */
1224extern int intel_setup_gmbus(struct drm_device *dev);
1225extern void intel_teardown_gmbus(struct drm_device *dev);
1226extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1227extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1228extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1229{
1230 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1231}
1232extern void intel_i2c_reset(struct drm_device *dev);
1233
1234/* intel_opregion.c */
1235extern int intel_opregion_setup(struct drm_device *dev);
1236#ifdef CONFIG_ACPI
1237extern void intel_opregion_init(struct drm_device *dev);
1238extern void intel_opregion_fini(struct drm_device *dev);
1239extern void intel_opregion_asle_intr(struct drm_device *dev);
1240extern void intel_opregion_gse_intr(struct drm_device *dev);
1241extern void intel_opregion_enable_asle(struct drm_device *dev);
1242#else
1243static inline void intel_opregion_init(struct drm_device *dev) { return; }
1244static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1245static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1246static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1247static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1248#endif
1249
1250/* intel_acpi.c */
1251#ifdef CONFIG_ACPI
1252extern void intel_register_dsm_handler(void);
1253extern void intel_unregister_dsm_handler(void);
1254#else
1255static inline void intel_register_dsm_handler(void) { return; }
1256static inline void intel_unregister_dsm_handler(void) { return; }
1257#endif /* CONFIG_ACPI */
1258
1259/* modesetting */
1260extern void intel_modeset_init(struct drm_device *dev);
1261extern void intel_modeset_cleanup(struct drm_device *dev);
1262extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1263extern void i8xx_disable_fbc(struct drm_device *dev);
1264extern void g4x_disable_fbc(struct drm_device *dev);
1265extern void ironlake_disable_fbc(struct drm_device *dev);
1266extern void intel_disable_fbc(struct drm_device *dev);
1267extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1268extern bool intel_fbc_enabled(struct drm_device *dev);
1269extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1270extern void ironlake_enable_rc6(struct drm_device *dev);
1271extern void gen6_set_rps(struct drm_device *dev, u8 val);
1272extern void intel_detect_pch (struct drm_device *dev);
1273extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1274
1275/* overlay */
1276#ifdef CONFIG_DEBUG_FS
1277extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1278extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1279
1280extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1281extern void intel_display_print_error_state(struct seq_file *m,
1282 struct drm_device *dev,
1283 struct intel_display_error_state *error);
1284#endif
1285
1286#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1287
1288#define BEGIN_LP_RING(n) \
1289 intel_ring_begin(LP_RING(dev_priv), (n))
1290
1291#define OUT_RING(x) \
1292 intel_ring_emit(LP_RING(dev_priv), x)
1293
1294#define ADVANCE_LP_RING() \
1295 intel_ring_advance(LP_RING(dev_priv))
1296
1297/**
1298 * Lock test for when it's just for synchronization of ring access.
1299 *
1300 * In that case, we don't need to do it when GEM is initialized as nobody else
1301 * has access to the ring.
1302 */
1303#define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1304 if (LP_RING(dev->dev_private)->obj == NULL) \
1305 LOCK_TEST_WITH_RETURN(dev, file); \
1306} while (0)
1307
1308
1309#define __i915_read(x, y) \
1310static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1311 u##x val = read##y(dev_priv->regs + reg); \
1312 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1313 return val; \
1314}
1315__i915_read(8, b)
1316__i915_read(16, w)
1317__i915_read(32, l)
1318__i915_read(64, q)
1319#undef __i915_read
1320
1321#define __i915_write(x, y) \
1322static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1323 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1324 write##y(val, dev_priv->regs + reg); \
1325}
1326__i915_write(8, b)
1327__i915_write(16, w)
1328__i915_write(32, l)
1329__i915_write(64, q)
1330#undef __i915_write
1331
1332#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1333#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1334
1335#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1336#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1337#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1338#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1339
1340#define I915_READ(reg) i915_read32(dev_priv, (reg))
1341#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1342#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1343#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1344
1345#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1346#define I915_READ64(reg) i915_read64(dev_priv, (reg))
1347
1348#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1349#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1350
1351
1352/* On SNB platform, before reading ring registers forcewake bit
1353 * must be set to prevent GT core from power down and stale values being
1354 * returned.
1355 */
1356void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
1357void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
1358static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1359{
1360 u32 val;
1361
1362 if (dev_priv->info->gen >= 6) {
1363 __gen6_force_wake_get(dev_priv);
1364 val = I915_READ(reg);
1365 __gen6_force_wake_put(dev_priv);
1366 } else
1367 val = I915_READ(reg);
1368
1369 return val;
1370}
1371
1372#endif
Linux kernel - Deliverables
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