| 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <drm/drmP.h> |
| 29 | #include <drm/drm_vma_manager.h> |
| 30 | #include <drm/i915_drm.h> |
| 31 | #include "i915_drv.h" |
| 32 | #include "i915_trace.h" |
| 33 | #include "intel_drv.h" |
| 34 | #include <linux/oom.h> |
| 35 | #include <linux/shmem_fs.h> |
| 36 | #include <linux/slab.h> |
| 37 | #include <linux/swap.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/dma-buf.h> |
| 40 | |
| 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 43 | bool force); |
| 44 | static __must_check int |
| 45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 46 | bool readonly); |
| 47 | static void |
| 48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); |
| 49 | |
| 50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 51 | struct drm_i915_gem_object *obj); |
| 52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 53 | struct drm_i915_fence_reg *fence, |
| 54 | bool enable); |
| 55 | |
| 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
| 57 | struct shrink_control *sc); |
| 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
| 59 | struct shrink_control *sc); |
| 60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
| 61 | unsigned long event, |
| 62 | void *ptr); |
| 63 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 64 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
| 65 | |
| 66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 67 | enum i915_cache_level level) |
| 68 | { |
| 69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 70 | } |
| 71 | |
| 72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 73 | { |
| 74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 75 | return true; |
| 76 | |
| 77 | return obj->pin_display; |
| 78 | } |
| 79 | |
| 80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 81 | { |
| 82 | if (obj->tiling_mode) |
| 83 | i915_gem_release_mmap(obj); |
| 84 | |
| 85 | /* As we do not have an associated fence register, we will force |
| 86 | * a tiling change if we ever need to acquire one. |
| 87 | */ |
| 88 | obj->fence_dirty = false; |
| 89 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 90 | } |
| 91 | |
| 92 | /* some bookkeeping */ |
| 93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 94 | size_t size) |
| 95 | { |
| 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
| 97 | dev_priv->mm.object_count++; |
| 98 | dev_priv->mm.object_memory += size; |
| 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
| 100 | } |
| 101 | |
| 102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 103 | size_t size) |
| 104 | { |
| 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
| 106 | dev_priv->mm.object_count--; |
| 107 | dev_priv->mm.object_memory -= size; |
| 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
| 109 | } |
| 110 | |
| 111 | static int |
| 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
| 113 | { |
| 114 | int ret; |
| 115 | |
| 116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 117 | i915_terminally_wedged(error)) |
| 118 | if (EXIT_COND) |
| 119 | return 0; |
| 120 | |
| 121 | /* |
| 122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 123 | * userspace. If it takes that long something really bad is going on and |
| 124 | * we should simply try to bail out and fail as gracefully as possible. |
| 125 | */ |
| 126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 127 | EXIT_COND, |
| 128 | 10*HZ); |
| 129 | if (ret == 0) { |
| 130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 131 | return -EIO; |
| 132 | } else if (ret < 0) { |
| 133 | return ret; |
| 134 | } |
| 135 | #undef EXIT_COND |
| 136 | |
| 137 | return 0; |
| 138 | } |
| 139 | |
| 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 141 | { |
| 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 143 | int ret; |
| 144 | |
| 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 146 | if (ret) |
| 147 | return ret; |
| 148 | |
| 149 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 150 | if (ret) |
| 151 | return ret; |
| 152 | |
| 153 | WARN_ON(i915_verify_lists(dev)); |
| 154 | return 0; |
| 155 | } |
| 156 | |
| 157 | static inline bool |
| 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
| 159 | { |
| 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
| 161 | } |
| 162 | |
| 163 | int |
| 164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 165 | struct drm_file *file) |
| 166 | { |
| 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 168 | struct drm_i915_gem_init *args = data; |
| 169 | |
| 170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 171 | return -ENODEV; |
| 172 | |
| 173 | if (args->gtt_start >= args->gtt_end || |
| 174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 175 | return -EINVAL; |
| 176 | |
| 177 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 178 | if (INTEL_INFO(dev)->gen >= 5) |
| 179 | return -ENODEV; |
| 180 | |
| 181 | mutex_lock(&dev->struct_mutex); |
| 182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
| 183 | args->gtt_end); |
| 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
| 185 | mutex_unlock(&dev->struct_mutex); |
| 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | int |
| 191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 192 | struct drm_file *file) |
| 193 | { |
| 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 195 | struct drm_i915_gem_get_aperture *args = data; |
| 196 | struct drm_i915_gem_object *obj; |
| 197 | size_t pinned; |
| 198 | |
| 199 | pinned = 0; |
| 200 | mutex_lock(&dev->struct_mutex); |
| 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 202 | if (i915_gem_obj_is_pinned(obj)) |
| 203 | pinned += i915_gem_obj_ggtt_size(obj); |
| 204 | mutex_unlock(&dev->struct_mutex); |
| 205 | |
| 206 | args->aper_size = dev_priv->gtt.base.total; |
| 207 | args->aper_available_size = args->aper_size - pinned; |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj) |
| 213 | { |
| 214 | drm_dma_handle_t *phys = obj->phys_handle; |
| 215 | |
| 216 | if (!phys) |
| 217 | return; |
| 218 | |
| 219 | if (obj->madv == I915_MADV_WILLNEED) { |
| 220 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 221 | char *vaddr = phys->vaddr; |
| 222 | int i; |
| 223 | |
| 224 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 225 | struct page *page = shmem_read_mapping_page(mapping, i); |
| 226 | if (!IS_ERR(page)) { |
| 227 | char *dst = kmap_atomic(page); |
| 228 | memcpy(dst, vaddr, PAGE_SIZE); |
| 229 | drm_clflush_virt_range(dst, PAGE_SIZE); |
| 230 | kunmap_atomic(dst); |
| 231 | |
| 232 | set_page_dirty(page); |
| 233 | mark_page_accessed(page); |
| 234 | page_cache_release(page); |
| 235 | } |
| 236 | vaddr += PAGE_SIZE; |
| 237 | } |
| 238 | i915_gem_chipset_flush(obj->base.dev); |
| 239 | } |
| 240 | |
| 241 | #ifdef CONFIG_X86 |
| 242 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); |
| 243 | #endif |
| 244 | drm_pci_free(obj->base.dev, phys); |
| 245 | obj->phys_handle = NULL; |
| 246 | } |
| 247 | |
| 248 | int |
| 249 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 250 | int align) |
| 251 | { |
| 252 | drm_dma_handle_t *phys; |
| 253 | struct address_space *mapping; |
| 254 | char *vaddr; |
| 255 | int i; |
| 256 | |
| 257 | if (obj->phys_handle) { |
| 258 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 259 | return -EBUSY; |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | if (obj->madv != I915_MADV_WILLNEED) |
| 265 | return -EFAULT; |
| 266 | |
| 267 | if (obj->base.filp == NULL) |
| 268 | return -EINVAL; |
| 269 | |
| 270 | /* create a new object */ |
| 271 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 272 | if (!phys) |
| 273 | return -ENOMEM; |
| 274 | |
| 275 | vaddr = phys->vaddr; |
| 276 | #ifdef CONFIG_X86 |
| 277 | set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE); |
| 278 | #endif |
| 279 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 280 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 281 | struct page *page; |
| 282 | char *src; |
| 283 | |
| 284 | page = shmem_read_mapping_page(mapping, i); |
| 285 | if (IS_ERR(page)) { |
| 286 | #ifdef CONFIG_X86 |
| 287 | set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE); |
| 288 | #endif |
| 289 | drm_pci_free(obj->base.dev, phys); |
| 290 | return PTR_ERR(page); |
| 291 | } |
| 292 | |
| 293 | src = kmap_atomic(page); |
| 294 | memcpy(vaddr, src, PAGE_SIZE); |
| 295 | kunmap_atomic(src); |
| 296 | |
| 297 | mark_page_accessed(page); |
| 298 | page_cache_release(page); |
| 299 | |
| 300 | vaddr += PAGE_SIZE; |
| 301 | } |
| 302 | |
| 303 | obj->phys_handle = phys; |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static int |
| 308 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 309 | struct drm_i915_gem_pwrite *args, |
| 310 | struct drm_file *file_priv) |
| 311 | { |
| 312 | struct drm_device *dev = obj->base.dev; |
| 313 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 314 | char __user *user_data = to_user_ptr(args->data_ptr); |
| 315 | |
| 316 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 317 | unsigned long unwritten; |
| 318 | |
| 319 | /* The physical object once assigned is fixed for the lifetime |
| 320 | * of the obj, so we can safely drop the lock and continue |
| 321 | * to access vaddr. |
| 322 | */ |
| 323 | mutex_unlock(&dev->struct_mutex); |
| 324 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 325 | mutex_lock(&dev->struct_mutex); |
| 326 | if (unwritten) |
| 327 | return -EFAULT; |
| 328 | } |
| 329 | |
| 330 | i915_gem_chipset_flush(dev); |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 335 | { |
| 336 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 337 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
| 338 | } |
| 339 | |
| 340 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 341 | { |
| 342 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 343 | kmem_cache_free(dev_priv->slab, obj); |
| 344 | } |
| 345 | |
| 346 | static int |
| 347 | i915_gem_create(struct drm_file *file, |
| 348 | struct drm_device *dev, |
| 349 | uint64_t size, |
| 350 | uint32_t *handle_p) |
| 351 | { |
| 352 | struct drm_i915_gem_object *obj; |
| 353 | int ret; |
| 354 | u32 handle; |
| 355 | |
| 356 | size = roundup(size, PAGE_SIZE); |
| 357 | if (size == 0) |
| 358 | return -EINVAL; |
| 359 | |
| 360 | /* Allocate the new object */ |
| 361 | obj = i915_gem_alloc_object(dev, size); |
| 362 | if (obj == NULL) |
| 363 | return -ENOMEM; |
| 364 | |
| 365 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
| 366 | /* drop reference from allocate - handle holds it now */ |
| 367 | drm_gem_object_unreference_unlocked(&obj->base); |
| 368 | if (ret) |
| 369 | return ret; |
| 370 | |
| 371 | *handle_p = handle; |
| 372 | return 0; |
| 373 | } |
| 374 | |
| 375 | int |
| 376 | i915_gem_dumb_create(struct drm_file *file, |
| 377 | struct drm_device *dev, |
| 378 | struct drm_mode_create_dumb *args) |
| 379 | { |
| 380 | /* have to work out size/pitch and return them */ |
| 381 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
| 382 | args->size = args->pitch * args->height; |
| 383 | return i915_gem_create(file, dev, |
| 384 | args->size, &args->handle); |
| 385 | } |
| 386 | |
| 387 | /** |
| 388 | * Creates a new mm object and returns a handle to it. |
| 389 | */ |
| 390 | int |
| 391 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 392 | struct drm_file *file) |
| 393 | { |
| 394 | struct drm_i915_gem_create *args = data; |
| 395 | |
| 396 | return i915_gem_create(file, dev, |
| 397 | args->size, &args->handle); |
| 398 | } |
| 399 | |
| 400 | static inline int |
| 401 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 402 | const char *gpu_vaddr, int gpu_offset, |
| 403 | int length) |
| 404 | { |
| 405 | int ret, cpu_offset = 0; |
| 406 | |
| 407 | while (length > 0) { |
| 408 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 409 | int this_length = min(cacheline_end - gpu_offset, length); |
| 410 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 411 | |
| 412 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 413 | gpu_vaddr + swizzled_gpu_offset, |
| 414 | this_length); |
| 415 | if (ret) |
| 416 | return ret + length; |
| 417 | |
| 418 | cpu_offset += this_length; |
| 419 | gpu_offset += this_length; |
| 420 | length -= this_length; |
| 421 | } |
| 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | static inline int |
| 427 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 428 | const char __user *cpu_vaddr, |
| 429 | int length) |
| 430 | { |
| 431 | int ret, cpu_offset = 0; |
| 432 | |
| 433 | while (length > 0) { |
| 434 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 435 | int this_length = min(cacheline_end - gpu_offset, length); |
| 436 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 437 | |
| 438 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 439 | cpu_vaddr + cpu_offset, |
| 440 | this_length); |
| 441 | if (ret) |
| 442 | return ret + length; |
| 443 | |
| 444 | cpu_offset += this_length; |
| 445 | gpu_offset += this_length; |
| 446 | length -= this_length; |
| 447 | } |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | /* |
| 453 | * Pins the specified object's pages and synchronizes the object with |
| 454 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 455 | * flush the object from the CPU cache. |
| 456 | */ |
| 457 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 458 | int *needs_clflush) |
| 459 | { |
| 460 | int ret; |
| 461 | |
| 462 | *needs_clflush = 0; |
| 463 | |
| 464 | if (!obj->base.filp) |
| 465 | return -EINVAL; |
| 466 | |
| 467 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 468 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 469 | * read domain and manually flush cachelines (if required). This |
| 470 | * optimizes for the case when the gpu will dirty the data |
| 471 | * anyway again before the next pread happens. */ |
| 472 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 473 | obj->cache_level); |
| 474 | ret = i915_gem_object_wait_rendering(obj, true); |
| 475 | if (ret) |
| 476 | return ret; |
| 477 | |
| 478 | i915_gem_object_retire(obj); |
| 479 | } |
| 480 | |
| 481 | ret = i915_gem_object_get_pages(obj); |
| 482 | if (ret) |
| 483 | return ret; |
| 484 | |
| 485 | i915_gem_object_pin_pages(obj); |
| 486 | |
| 487 | return ret; |
| 488 | } |
| 489 | |
| 490 | /* Per-page copy function for the shmem pread fastpath. |
| 491 | * Flushes invalid cachelines before reading the target if |
| 492 | * needs_clflush is set. */ |
| 493 | static int |
| 494 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 495 | char __user *user_data, |
| 496 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 497 | { |
| 498 | char *vaddr; |
| 499 | int ret; |
| 500 | |
| 501 | if (unlikely(page_do_bit17_swizzling)) |
| 502 | return -EINVAL; |
| 503 | |
| 504 | vaddr = kmap_atomic(page); |
| 505 | if (needs_clflush) |
| 506 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 507 | page_length); |
| 508 | ret = __copy_to_user_inatomic(user_data, |
| 509 | vaddr + shmem_page_offset, |
| 510 | page_length); |
| 511 | kunmap_atomic(vaddr); |
| 512 | |
| 513 | return ret ? -EFAULT : 0; |
| 514 | } |
| 515 | |
| 516 | static void |
| 517 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 518 | bool swizzled) |
| 519 | { |
| 520 | if (unlikely(swizzled)) { |
| 521 | unsigned long start = (unsigned long) addr; |
| 522 | unsigned long end = (unsigned long) addr + length; |
| 523 | |
| 524 | /* For swizzling simply ensure that we always flush both |
| 525 | * channels. Lame, but simple and it works. Swizzled |
| 526 | * pwrite/pread is far from a hotpath - current userspace |
| 527 | * doesn't use it at all. */ |
| 528 | start = round_down(start, 128); |
| 529 | end = round_up(end, 128); |
| 530 | |
| 531 | drm_clflush_virt_range((void *)start, end - start); |
| 532 | } else { |
| 533 | drm_clflush_virt_range(addr, length); |
| 534 | } |
| 535 | |
| 536 | } |
| 537 | |
| 538 | /* Only difference to the fast-path function is that this can handle bit17 |
| 539 | * and uses non-atomic copy and kmap functions. */ |
| 540 | static int |
| 541 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 542 | char __user *user_data, |
| 543 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 544 | { |
| 545 | char *vaddr; |
| 546 | int ret; |
| 547 | |
| 548 | vaddr = kmap(page); |
| 549 | if (needs_clflush) |
| 550 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 551 | page_length, |
| 552 | page_do_bit17_swizzling); |
| 553 | |
| 554 | if (page_do_bit17_swizzling) |
| 555 | ret = __copy_to_user_swizzled(user_data, |
| 556 | vaddr, shmem_page_offset, |
| 557 | page_length); |
| 558 | else |
| 559 | ret = __copy_to_user(user_data, |
| 560 | vaddr + shmem_page_offset, |
| 561 | page_length); |
| 562 | kunmap(page); |
| 563 | |
| 564 | return ret ? - EFAULT : 0; |
| 565 | } |
| 566 | |
| 567 | static int |
| 568 | i915_gem_shmem_pread(struct drm_device *dev, |
| 569 | struct drm_i915_gem_object *obj, |
| 570 | struct drm_i915_gem_pread *args, |
| 571 | struct drm_file *file) |
| 572 | { |
| 573 | char __user *user_data; |
| 574 | ssize_t remain; |
| 575 | loff_t offset; |
| 576 | int shmem_page_offset, page_length, ret = 0; |
| 577 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
| 578 | int prefaulted = 0; |
| 579 | int needs_clflush = 0; |
| 580 | struct sg_page_iter sg_iter; |
| 581 | |
| 582 | user_data = to_user_ptr(args->data_ptr); |
| 583 | remain = args->size; |
| 584 | |
| 585 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 586 | |
| 587 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
| 588 | if (ret) |
| 589 | return ret; |
| 590 | |
| 591 | offset = args->offset; |
| 592 | |
| 593 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 594 | offset >> PAGE_SHIFT) { |
| 595 | struct page *page = sg_page_iter_page(&sg_iter); |
| 596 | |
| 597 | if (remain <= 0) |
| 598 | break; |
| 599 | |
| 600 | /* Operation in this page |
| 601 | * |
| 602 | * shmem_page_offset = offset within page in shmem file |
| 603 | * page_length = bytes to copy for this page |
| 604 | */ |
| 605 | shmem_page_offset = offset_in_page(offset); |
| 606 | page_length = remain; |
| 607 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 608 | page_length = PAGE_SIZE - shmem_page_offset; |
| 609 | |
| 610 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 611 | (page_to_phys(page) & (1 << 17)) != 0; |
| 612 | |
| 613 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 614 | user_data, page_do_bit17_swizzling, |
| 615 | needs_clflush); |
| 616 | if (ret == 0) |
| 617 | goto next_page; |
| 618 | |
| 619 | mutex_unlock(&dev->struct_mutex); |
| 620 | |
| 621 | if (likely(!i915.prefault_disable) && !prefaulted) { |
| 622 | ret = fault_in_multipages_writeable(user_data, remain); |
| 623 | /* Userspace is tricking us, but we've already clobbered |
| 624 | * its pages with the prefault and promised to write the |
| 625 | * data up to the first fault. Hence ignore any errors |
| 626 | * and just continue. */ |
| 627 | (void)ret; |
| 628 | prefaulted = 1; |
| 629 | } |
| 630 | |
| 631 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 632 | user_data, page_do_bit17_swizzling, |
| 633 | needs_clflush); |
| 634 | |
| 635 | mutex_lock(&dev->struct_mutex); |
| 636 | |
| 637 | if (ret) |
| 638 | goto out; |
| 639 | |
| 640 | next_page: |
| 641 | remain -= page_length; |
| 642 | user_data += page_length; |
| 643 | offset += page_length; |
| 644 | } |
| 645 | |
| 646 | out: |
| 647 | i915_gem_object_unpin_pages(obj); |
| 648 | |
| 649 | return ret; |
| 650 | } |
| 651 | |
| 652 | /** |
| 653 | * Reads data from the object referenced by handle. |
| 654 | * |
| 655 | * On error, the contents of *data are undefined. |
| 656 | */ |
| 657 | int |
| 658 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 659 | struct drm_file *file) |
| 660 | { |
| 661 | struct drm_i915_gem_pread *args = data; |
| 662 | struct drm_i915_gem_object *obj; |
| 663 | int ret = 0; |
| 664 | |
| 665 | if (args->size == 0) |
| 666 | return 0; |
| 667 | |
| 668 | if (!access_ok(VERIFY_WRITE, |
| 669 | to_user_ptr(args->data_ptr), |
| 670 | args->size)) |
| 671 | return -EFAULT; |
| 672 | |
| 673 | ret = i915_mutex_lock_interruptible(dev); |
| 674 | if (ret) |
| 675 | return ret; |
| 676 | |
| 677 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 678 | if (&obj->base == NULL) { |
| 679 | ret = -ENOENT; |
| 680 | goto unlock; |
| 681 | } |
| 682 | |
| 683 | /* Bounds check source. */ |
| 684 | if (args->offset > obj->base.size || |
| 685 | args->size > obj->base.size - args->offset) { |
| 686 | ret = -EINVAL; |
| 687 | goto out; |
| 688 | } |
| 689 | |
| 690 | /* prime objects have no backing filp to GEM pread/pwrite |
| 691 | * pages from. |
| 692 | */ |
| 693 | if (!obj->base.filp) { |
| 694 | ret = -EINVAL; |
| 695 | goto out; |
| 696 | } |
| 697 | |
| 698 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 699 | |
| 700 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
| 701 | |
| 702 | out: |
| 703 | drm_gem_object_unreference(&obj->base); |
| 704 | unlock: |
| 705 | mutex_unlock(&dev->struct_mutex); |
| 706 | return ret; |
| 707 | } |
| 708 | |
| 709 | /* This is the fast write path which cannot handle |
| 710 | * page faults in the source data |
| 711 | */ |
| 712 | |
| 713 | static inline int |
| 714 | fast_user_write(struct io_mapping *mapping, |
| 715 | loff_t page_base, int page_offset, |
| 716 | char __user *user_data, |
| 717 | int length) |
| 718 | { |
| 719 | void __iomem *vaddr_atomic; |
| 720 | void *vaddr; |
| 721 | unsigned long unwritten; |
| 722 | |
| 723 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 724 | /* We can use the cpu mem copy function because this is X86. */ |
| 725 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 726 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
| 727 | user_data, length); |
| 728 | io_mapping_unmap_atomic(vaddr_atomic); |
| 729 | return unwritten; |
| 730 | } |
| 731 | |
| 732 | /** |
| 733 | * This is the fast pwrite path, where we copy the data directly from the |
| 734 | * user into the GTT, uncached. |
| 735 | */ |
| 736 | static int |
| 737 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 738 | struct drm_i915_gem_object *obj, |
| 739 | struct drm_i915_gem_pwrite *args, |
| 740 | struct drm_file *file) |
| 741 | { |
| 742 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 743 | ssize_t remain; |
| 744 | loff_t offset, page_base; |
| 745 | char __user *user_data; |
| 746 | int page_offset, page_length, ret; |
| 747 | |
| 748 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
| 749 | if (ret) |
| 750 | goto out; |
| 751 | |
| 752 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 753 | if (ret) |
| 754 | goto out_unpin; |
| 755 | |
| 756 | ret = i915_gem_object_put_fence(obj); |
| 757 | if (ret) |
| 758 | goto out_unpin; |
| 759 | |
| 760 | user_data = to_user_ptr(args->data_ptr); |
| 761 | remain = args->size; |
| 762 | |
| 763 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
| 764 | |
| 765 | while (remain > 0) { |
| 766 | /* Operation in this page |
| 767 | * |
| 768 | * page_base = page offset within aperture |
| 769 | * page_offset = offset within page |
| 770 | * page_length = bytes to copy for this page |
| 771 | */ |
| 772 | page_base = offset & PAGE_MASK; |
| 773 | page_offset = offset_in_page(offset); |
| 774 | page_length = remain; |
| 775 | if ((page_offset + remain) > PAGE_SIZE) |
| 776 | page_length = PAGE_SIZE - page_offset; |
| 777 | |
| 778 | /* If we get a fault while copying data, then (presumably) our |
| 779 | * source page isn't available. Return the error and we'll |
| 780 | * retry in the slow path. |
| 781 | */ |
| 782 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
| 783 | page_offset, user_data, page_length)) { |
| 784 | ret = -EFAULT; |
| 785 | goto out_unpin; |
| 786 | } |
| 787 | |
| 788 | remain -= page_length; |
| 789 | user_data += page_length; |
| 790 | offset += page_length; |
| 791 | } |
| 792 | |
| 793 | out_unpin: |
| 794 | i915_gem_object_ggtt_unpin(obj); |
| 795 | out: |
| 796 | return ret; |
| 797 | } |
| 798 | |
| 799 | /* Per-page copy function for the shmem pwrite fastpath. |
| 800 | * Flushes invalid cachelines before writing to the target if |
| 801 | * needs_clflush_before is set and flushes out any written cachelines after |
| 802 | * writing if needs_clflush is set. */ |
| 803 | static int |
| 804 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 805 | char __user *user_data, |
| 806 | bool page_do_bit17_swizzling, |
| 807 | bool needs_clflush_before, |
| 808 | bool needs_clflush_after) |
| 809 | { |
| 810 | char *vaddr; |
| 811 | int ret; |
| 812 | |
| 813 | if (unlikely(page_do_bit17_swizzling)) |
| 814 | return -EINVAL; |
| 815 | |
| 816 | vaddr = kmap_atomic(page); |
| 817 | if (needs_clflush_before) |
| 818 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 819 | page_length); |
| 820 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 821 | user_data, page_length); |
| 822 | if (needs_clflush_after) |
| 823 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 824 | page_length); |
| 825 | kunmap_atomic(vaddr); |
| 826 | |
| 827 | return ret ? -EFAULT : 0; |
| 828 | } |
| 829 | |
| 830 | /* Only difference to the fast-path function is that this can handle bit17 |
| 831 | * and uses non-atomic copy and kmap functions. */ |
| 832 | static int |
| 833 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 834 | char __user *user_data, |
| 835 | bool page_do_bit17_swizzling, |
| 836 | bool needs_clflush_before, |
| 837 | bool needs_clflush_after) |
| 838 | { |
| 839 | char *vaddr; |
| 840 | int ret; |
| 841 | |
| 842 | vaddr = kmap(page); |
| 843 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
| 844 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 845 | page_length, |
| 846 | page_do_bit17_swizzling); |
| 847 | if (page_do_bit17_swizzling) |
| 848 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
| 849 | user_data, |
| 850 | page_length); |
| 851 | else |
| 852 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 853 | user_data, |
| 854 | page_length); |
| 855 | if (needs_clflush_after) |
| 856 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 857 | page_length, |
| 858 | page_do_bit17_swizzling); |
| 859 | kunmap(page); |
| 860 | |
| 861 | return ret ? -EFAULT : 0; |
| 862 | } |
| 863 | |
| 864 | static int |
| 865 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 866 | struct drm_i915_gem_object *obj, |
| 867 | struct drm_i915_gem_pwrite *args, |
| 868 | struct drm_file *file) |
| 869 | { |
| 870 | ssize_t remain; |
| 871 | loff_t offset; |
| 872 | char __user *user_data; |
| 873 | int shmem_page_offset, page_length, ret = 0; |
| 874 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
| 875 | int hit_slowpath = 0; |
| 876 | int needs_clflush_after = 0; |
| 877 | int needs_clflush_before = 0; |
| 878 | struct sg_page_iter sg_iter; |
| 879 | |
| 880 | user_data = to_user_ptr(args->data_ptr); |
| 881 | remain = args->size; |
| 882 | |
| 883 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 884 | |
| 885 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 886 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 887 | * write domain and manually flush cachelines (if required). This |
| 888 | * optimizes for the case when the gpu will use the data |
| 889 | * right away and we therefore have to clflush anyway. */ |
| 890 | needs_clflush_after = cpu_write_needs_clflush(obj); |
| 891 | ret = i915_gem_object_wait_rendering(obj, false); |
| 892 | if (ret) |
| 893 | return ret; |
| 894 | |
| 895 | i915_gem_object_retire(obj); |
| 896 | } |
| 897 | /* Same trick applies to invalidate partially written cachelines read |
| 898 | * before writing. */ |
| 899 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 900 | needs_clflush_before = |
| 901 | !cpu_cache_is_coherent(dev, obj->cache_level); |
| 902 | |
| 903 | ret = i915_gem_object_get_pages(obj); |
| 904 | if (ret) |
| 905 | return ret; |
| 906 | |
| 907 | i915_gem_object_pin_pages(obj); |
| 908 | |
| 909 | offset = args->offset; |
| 910 | obj->dirty = 1; |
| 911 | |
| 912 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 913 | offset >> PAGE_SHIFT) { |
| 914 | struct page *page = sg_page_iter_page(&sg_iter); |
| 915 | int partial_cacheline_write; |
| 916 | |
| 917 | if (remain <= 0) |
| 918 | break; |
| 919 | |
| 920 | /* Operation in this page |
| 921 | * |
| 922 | * shmem_page_offset = offset within page in shmem file |
| 923 | * page_length = bytes to copy for this page |
| 924 | */ |
| 925 | shmem_page_offset = offset_in_page(offset); |
| 926 | |
| 927 | page_length = remain; |
| 928 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 929 | page_length = PAGE_SIZE - shmem_page_offset; |
| 930 | |
| 931 | /* If we don't overwrite a cacheline completely we need to be |
| 932 | * careful to have up-to-date data by first clflushing. Don't |
| 933 | * overcomplicate things and flush the entire patch. */ |
| 934 | partial_cacheline_write = needs_clflush_before && |
| 935 | ((shmem_page_offset | page_length) |
| 936 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 937 | |
| 938 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 939 | (page_to_phys(page) & (1 << 17)) != 0; |
| 940 | |
| 941 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 942 | user_data, page_do_bit17_swizzling, |
| 943 | partial_cacheline_write, |
| 944 | needs_clflush_after); |
| 945 | if (ret == 0) |
| 946 | goto next_page; |
| 947 | |
| 948 | hit_slowpath = 1; |
| 949 | mutex_unlock(&dev->struct_mutex); |
| 950 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 951 | user_data, page_do_bit17_swizzling, |
| 952 | partial_cacheline_write, |
| 953 | needs_clflush_after); |
| 954 | |
| 955 | mutex_lock(&dev->struct_mutex); |
| 956 | |
| 957 | if (ret) |
| 958 | goto out; |
| 959 | |
| 960 | next_page: |
| 961 | remain -= page_length; |
| 962 | user_data += page_length; |
| 963 | offset += page_length; |
| 964 | } |
| 965 | |
| 966 | out: |
| 967 | i915_gem_object_unpin_pages(obj); |
| 968 | |
| 969 | if (hit_slowpath) { |
| 970 | /* |
| 971 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 972 | * cachelines in-line while writing and the object moved |
| 973 | * out of the cpu write domain while we've dropped the lock. |
| 974 | */ |
| 975 | if (!needs_clflush_after && |
| 976 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 977 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 978 | i915_gem_chipset_flush(dev); |
| 979 | } |
| 980 | } |
| 981 | |
| 982 | if (needs_clflush_after) |
| 983 | i915_gem_chipset_flush(dev); |
| 984 | |
| 985 | return ret; |
| 986 | } |
| 987 | |
| 988 | /** |
| 989 | * Writes data to the object referenced by handle. |
| 990 | * |
| 991 | * On error, the contents of the buffer that were to be modified are undefined. |
| 992 | */ |
| 993 | int |
| 994 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 995 | struct drm_file *file) |
| 996 | { |
| 997 | struct drm_i915_gem_pwrite *args = data; |
| 998 | struct drm_i915_gem_object *obj; |
| 999 | int ret; |
| 1000 | |
| 1001 | if (args->size == 0) |
| 1002 | return 0; |
| 1003 | |
| 1004 | if (!access_ok(VERIFY_READ, |
| 1005 | to_user_ptr(args->data_ptr), |
| 1006 | args->size)) |
| 1007 | return -EFAULT; |
| 1008 | |
| 1009 | if (likely(!i915.prefault_disable)) { |
| 1010 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1011 | args->size); |
| 1012 | if (ret) |
| 1013 | return -EFAULT; |
| 1014 | } |
| 1015 | |
| 1016 | ret = i915_mutex_lock_interruptible(dev); |
| 1017 | if (ret) |
| 1018 | return ret; |
| 1019 | |
| 1020 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1021 | if (&obj->base == NULL) { |
| 1022 | ret = -ENOENT; |
| 1023 | goto unlock; |
| 1024 | } |
| 1025 | |
| 1026 | /* Bounds check destination. */ |
| 1027 | if (args->offset > obj->base.size || |
| 1028 | args->size > obj->base.size - args->offset) { |
| 1029 | ret = -EINVAL; |
| 1030 | goto out; |
| 1031 | } |
| 1032 | |
| 1033 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1034 | * pages from. |
| 1035 | */ |
| 1036 | if (!obj->base.filp) { |
| 1037 | ret = -EINVAL; |
| 1038 | goto out; |
| 1039 | } |
| 1040 | |
| 1041 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1042 | |
| 1043 | ret = -EFAULT; |
| 1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1045 | * it would end up going through the fenced access, and we'll get |
| 1046 | * different detiling behavior between reading and writing. |
| 1047 | * pread/pwrite currently are reading and writing from the CPU |
| 1048 | * perspective, requiring manual detiling by the client. |
| 1049 | */ |
| 1050 | if (obj->phys_handle) { |
| 1051 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1052 | goto out; |
| 1053 | } |
| 1054 | |
| 1055 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1056 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1057 | cpu_write_needs_clflush(obj)) { |
| 1058 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1059 | /* Note that the gtt paths might fail with non-page-backed user |
| 1060 | * pointers (e.g. gtt mappings when moving data between |
| 1061 | * textures). Fallback to the shmem path in that case. */ |
| 1062 | } |
| 1063 | |
| 1064 | if (ret == -EFAULT || ret == -ENOSPC) |
| 1065 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1066 | |
| 1067 | out: |
| 1068 | drm_gem_object_unreference(&obj->base); |
| 1069 | unlock: |
| 1070 | mutex_unlock(&dev->struct_mutex); |
| 1071 | return ret; |
| 1072 | } |
| 1073 | |
| 1074 | int |
| 1075 | i915_gem_check_wedge(struct i915_gpu_error *error, |
| 1076 | bool interruptible) |
| 1077 | { |
| 1078 | if (i915_reset_in_progress(error)) { |
| 1079 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1080 | * -EIO unconditionally for these. */ |
| 1081 | if (!interruptible) |
| 1082 | return -EIO; |
| 1083 | |
| 1084 | /* Recovery complete, but the reset failed ... */ |
| 1085 | if (i915_terminally_wedged(error)) |
| 1086 | return -EIO; |
| 1087 | |
| 1088 | return -EAGAIN; |
| 1089 | } |
| 1090 | |
| 1091 | return 0; |
| 1092 | } |
| 1093 | |
| 1094 | /* |
| 1095 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 1096 | * equal. |
| 1097 | */ |
| 1098 | int |
| 1099 | i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno) |
| 1100 | { |
| 1101 | int ret; |
| 1102 | |
| 1103 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 1104 | |
| 1105 | ret = 0; |
| 1106 | if (seqno == ring->outstanding_lazy_seqno) |
| 1107 | ret = i915_add_request(ring, NULL); |
| 1108 | |
| 1109 | return ret; |
| 1110 | } |
| 1111 | |
| 1112 | static void fake_irq(unsigned long data) |
| 1113 | { |
| 1114 | wake_up_process((struct task_struct *)data); |
| 1115 | } |
| 1116 | |
| 1117 | static bool missed_irq(struct drm_i915_private *dev_priv, |
| 1118 | struct intel_engine_cs *ring) |
| 1119 | { |
| 1120 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
| 1121 | } |
| 1122 | |
| 1123 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
| 1124 | { |
| 1125 | if (file_priv == NULL) |
| 1126 | return true; |
| 1127 | |
| 1128 | return !atomic_xchg(&file_priv->rps_wait_boost, true); |
| 1129 | } |
| 1130 | |
| 1131 | /** |
| 1132 | * __wait_seqno - wait until execution of seqno has finished |
| 1133 | * @ring: the ring expected to report seqno |
| 1134 | * @seqno: duh! |
| 1135 | * @reset_counter: reset sequence associated with the given seqno |
| 1136 | * @interruptible: do an interruptible wait (normally yes) |
| 1137 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1138 | * |
| 1139 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1140 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1141 | * locks are involved, it is sufficient to read the reset_counter before |
| 1142 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1143 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1144 | * inserted. |
| 1145 | * |
| 1146 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 1147 | * errno with remaining time filled in timeout argument. |
| 1148 | */ |
| 1149 | static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
| 1150 | unsigned reset_counter, |
| 1151 | bool interruptible, |
| 1152 | struct timespec *timeout, |
| 1153 | struct drm_i915_file_private *file_priv) |
| 1154 | { |
| 1155 | struct drm_device *dev = ring->dev; |
| 1156 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1157 | const bool irq_test_in_progress = |
| 1158 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
| 1159 | struct timespec before, now; |
| 1160 | DEFINE_WAIT(wait); |
| 1161 | unsigned long timeout_expire; |
| 1162 | int ret; |
| 1163 | |
| 1164 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
| 1165 | |
| 1166 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 1167 | return 0; |
| 1168 | |
| 1169 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
| 1170 | |
| 1171 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
| 1172 | gen6_rps_boost(dev_priv); |
| 1173 | if (file_priv) |
| 1174 | mod_delayed_work(dev_priv->wq, |
| 1175 | &file_priv->mm.idle_work, |
| 1176 | msecs_to_jiffies(100)); |
| 1177 | } |
| 1178 | |
| 1179 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
| 1180 | return -ENODEV; |
| 1181 | |
| 1182 | /* Record current time in case interrupted by signal, or wedged */ |
| 1183 | trace_i915_gem_request_wait_begin(ring, seqno); |
| 1184 | getrawmonotonic(&before); |
| 1185 | for (;;) { |
| 1186 | struct timer_list timer; |
| 1187 | |
| 1188 | prepare_to_wait(&ring->irq_queue, &wait, |
| 1189 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
| 1190 | |
| 1191 | /* We need to check whether any gpu reset happened in between |
| 1192 | * the caller grabbing the seqno and now ... */ |
| 1193 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
| 1194 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
| 1195 | * is truely gone. */ |
| 1196 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1197 | if (ret == 0) |
| 1198 | ret = -EAGAIN; |
| 1199 | break; |
| 1200 | } |
| 1201 | |
| 1202 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
| 1203 | ret = 0; |
| 1204 | break; |
| 1205 | } |
| 1206 | |
| 1207 | if (interruptible && signal_pending(current)) { |
| 1208 | ret = -ERESTARTSYS; |
| 1209 | break; |
| 1210 | } |
| 1211 | |
| 1212 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
| 1213 | ret = -ETIME; |
| 1214 | break; |
| 1215 | } |
| 1216 | |
| 1217 | timer.function = NULL; |
| 1218 | if (timeout || missed_irq(dev_priv, ring)) { |
| 1219 | unsigned long expire; |
| 1220 | |
| 1221 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
| 1222 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
| 1223 | mod_timer(&timer, expire); |
| 1224 | } |
| 1225 | |
| 1226 | io_schedule(); |
| 1227 | |
| 1228 | if (timer.function) { |
| 1229 | del_singleshot_timer_sync(&timer); |
| 1230 | destroy_timer_on_stack(&timer); |
| 1231 | } |
| 1232 | } |
| 1233 | getrawmonotonic(&now); |
| 1234 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1235 | |
| 1236 | if (!irq_test_in_progress) |
| 1237 | ring->irq_put(ring); |
| 1238 | |
| 1239 | finish_wait(&ring->irq_queue, &wait); |
| 1240 | |
| 1241 | if (timeout) { |
| 1242 | struct timespec sleep_time = timespec_sub(now, before); |
| 1243 | *timeout = timespec_sub(*timeout, sleep_time); |
| 1244 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
| 1245 | set_normalized_timespec(timeout, 0, 0); |
| 1246 | } |
| 1247 | |
| 1248 | return ret; |
| 1249 | } |
| 1250 | |
| 1251 | /** |
| 1252 | * Waits for a sequence number to be signaled, and cleans up the |
| 1253 | * request and object lists appropriately for that event. |
| 1254 | */ |
| 1255 | int |
| 1256 | i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno) |
| 1257 | { |
| 1258 | struct drm_device *dev = ring->dev; |
| 1259 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1260 | bool interruptible = dev_priv->mm.interruptible; |
| 1261 | int ret; |
| 1262 | |
| 1263 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1264 | BUG_ON(seqno == 0); |
| 1265 | |
| 1266 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1267 | if (ret) |
| 1268 | return ret; |
| 1269 | |
| 1270 | ret = i915_gem_check_olr(ring, seqno); |
| 1271 | if (ret) |
| 1272 | return ret; |
| 1273 | |
| 1274 | return __wait_seqno(ring, seqno, |
| 1275 | atomic_read(&dev_priv->gpu_error.reset_counter), |
| 1276 | interruptible, NULL, NULL); |
| 1277 | } |
| 1278 | |
| 1279 | static int |
| 1280 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
| 1281 | struct intel_engine_cs *ring) |
| 1282 | { |
| 1283 | if (!obj->active) |
| 1284 | return 0; |
| 1285 | |
| 1286 | /* Manually manage the write flush as we may have not yet |
| 1287 | * retired the buffer. |
| 1288 | * |
| 1289 | * Note that the last_write_seqno is always the earlier of |
| 1290 | * the two (read/write) seqno, so if we haved successfully waited, |
| 1291 | * we know we have passed the last write. |
| 1292 | */ |
| 1293 | obj->last_write_seqno = 0; |
| 1294 | |
| 1295 | return 0; |
| 1296 | } |
| 1297 | |
| 1298 | /** |
| 1299 | * Ensures that all rendering to the object has completed and the object is |
| 1300 | * safe to unbind from the GTT or access from the CPU. |
| 1301 | */ |
| 1302 | static __must_check int |
| 1303 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1304 | bool readonly) |
| 1305 | { |
| 1306 | struct intel_engine_cs *ring = obj->ring; |
| 1307 | u32 seqno; |
| 1308 | int ret; |
| 1309 | |
| 1310 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1311 | if (seqno == 0) |
| 1312 | return 0; |
| 1313 | |
| 1314 | ret = i915_wait_seqno(ring, seqno); |
| 1315 | if (ret) |
| 1316 | return ret; |
| 1317 | |
| 1318 | return i915_gem_object_wait_rendering__tail(obj, ring); |
| 1319 | } |
| 1320 | |
| 1321 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1322 | * as the object state may change during this call. |
| 1323 | */ |
| 1324 | static __must_check int |
| 1325 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1326 | struct drm_i915_file_private *file_priv, |
| 1327 | bool readonly) |
| 1328 | { |
| 1329 | struct drm_device *dev = obj->base.dev; |
| 1330 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1331 | struct intel_engine_cs *ring = obj->ring; |
| 1332 | unsigned reset_counter; |
| 1333 | u32 seqno; |
| 1334 | int ret; |
| 1335 | |
| 1336 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1337 | BUG_ON(!dev_priv->mm.interruptible); |
| 1338 | |
| 1339 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1340 | if (seqno == 0) |
| 1341 | return 0; |
| 1342 | |
| 1343 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
| 1344 | if (ret) |
| 1345 | return ret; |
| 1346 | |
| 1347 | ret = i915_gem_check_olr(ring, seqno); |
| 1348 | if (ret) |
| 1349 | return ret; |
| 1350 | |
| 1351 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 1352 | mutex_unlock(&dev->struct_mutex); |
| 1353 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
| 1354 | mutex_lock(&dev->struct_mutex); |
| 1355 | if (ret) |
| 1356 | return ret; |
| 1357 | |
| 1358 | return i915_gem_object_wait_rendering__tail(obj, ring); |
| 1359 | } |
| 1360 | |
| 1361 | /** |
| 1362 | * Called when user space prepares to use an object with the CPU, either |
| 1363 | * through the mmap ioctl's mapping or a GTT mapping. |
| 1364 | */ |
| 1365 | int |
| 1366 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1367 | struct drm_file *file) |
| 1368 | { |
| 1369 | struct drm_i915_gem_set_domain *args = data; |
| 1370 | struct drm_i915_gem_object *obj; |
| 1371 | uint32_t read_domains = args->read_domains; |
| 1372 | uint32_t write_domain = args->write_domain; |
| 1373 | int ret; |
| 1374 | |
| 1375 | /* Only handle setting domains to types used by the CPU. */ |
| 1376 | if (write_domain & I915_GEM_GPU_DOMAINS) |
| 1377 | return -EINVAL; |
| 1378 | |
| 1379 | if (read_domains & I915_GEM_GPU_DOMAINS) |
| 1380 | return -EINVAL; |
| 1381 | |
| 1382 | /* Having something in the write domain implies it's in the read |
| 1383 | * domain, and only that read domain. Enforce that in the request. |
| 1384 | */ |
| 1385 | if (write_domain != 0 && read_domains != write_domain) |
| 1386 | return -EINVAL; |
| 1387 | |
| 1388 | ret = i915_mutex_lock_interruptible(dev); |
| 1389 | if (ret) |
| 1390 | return ret; |
| 1391 | |
| 1392 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1393 | if (&obj->base == NULL) { |
| 1394 | ret = -ENOENT; |
| 1395 | goto unlock; |
| 1396 | } |
| 1397 | |
| 1398 | /* Try to flush the object off the GPU without holding the lock. |
| 1399 | * We will repeat the flush holding the lock in the normal manner |
| 1400 | * to catch cases where we are gazumped. |
| 1401 | */ |
| 1402 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
| 1403 | file->driver_priv, |
| 1404 | !write_domain); |
| 1405 | if (ret) |
| 1406 | goto unref; |
| 1407 | |
| 1408 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1409 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
| 1410 | |
| 1411 | /* Silently promote "you're not bound, there was nothing to do" |
| 1412 | * to success, since the client was just asking us to |
| 1413 | * make sure everything was done. |
| 1414 | */ |
| 1415 | if (ret == -EINVAL) |
| 1416 | ret = 0; |
| 1417 | } else { |
| 1418 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
| 1419 | } |
| 1420 | |
| 1421 | unref: |
| 1422 | drm_gem_object_unreference(&obj->base); |
| 1423 | unlock: |
| 1424 | mutex_unlock(&dev->struct_mutex); |
| 1425 | return ret; |
| 1426 | } |
| 1427 | |
| 1428 | /** |
| 1429 | * Called when user space has done writes to this buffer |
| 1430 | */ |
| 1431 | int |
| 1432 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1433 | struct drm_file *file) |
| 1434 | { |
| 1435 | struct drm_i915_gem_sw_finish *args = data; |
| 1436 | struct drm_i915_gem_object *obj; |
| 1437 | int ret = 0; |
| 1438 | |
| 1439 | ret = i915_mutex_lock_interruptible(dev); |
| 1440 | if (ret) |
| 1441 | return ret; |
| 1442 | |
| 1443 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1444 | if (&obj->base == NULL) { |
| 1445 | ret = -ENOENT; |
| 1446 | goto unlock; |
| 1447 | } |
| 1448 | |
| 1449 | /* Pinned buffers may be scanout, so flush the cache */ |
| 1450 | if (obj->pin_display) |
| 1451 | i915_gem_object_flush_cpu_write_domain(obj, true); |
| 1452 | |
| 1453 | drm_gem_object_unreference(&obj->base); |
| 1454 | unlock: |
| 1455 | mutex_unlock(&dev->struct_mutex); |
| 1456 | return ret; |
| 1457 | } |
| 1458 | |
| 1459 | /** |
| 1460 | * Maps the contents of an object, returning the address it is mapped |
| 1461 | * into. |
| 1462 | * |
| 1463 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1464 | * imply a ref on the object itself. |
| 1465 | */ |
| 1466 | int |
| 1467 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1468 | struct drm_file *file) |
| 1469 | { |
| 1470 | struct drm_i915_gem_mmap *args = data; |
| 1471 | struct drm_gem_object *obj; |
| 1472 | unsigned long addr; |
| 1473 | |
| 1474 | obj = drm_gem_object_lookup(dev, file, args->handle); |
| 1475 | if (obj == NULL) |
| 1476 | return -ENOENT; |
| 1477 | |
| 1478 | /* prime objects have no backing filp to GEM mmap |
| 1479 | * pages from. |
| 1480 | */ |
| 1481 | if (!obj->filp) { |
| 1482 | drm_gem_object_unreference_unlocked(obj); |
| 1483 | return -EINVAL; |
| 1484 | } |
| 1485 | |
| 1486 | addr = vm_mmap(obj->filp, 0, args->size, |
| 1487 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1488 | args->offset); |
| 1489 | drm_gem_object_unreference_unlocked(obj); |
| 1490 | if (IS_ERR((void *)addr)) |
| 1491 | return addr; |
| 1492 | |
| 1493 | args->addr_ptr = (uint64_t) addr; |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | /** |
| 1499 | * i915_gem_fault - fault a page into the GTT |
| 1500 | * vma: VMA in question |
| 1501 | * vmf: fault info |
| 1502 | * |
| 1503 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1504 | * from userspace. The fault handler takes care of binding the object to |
| 1505 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1506 | * only if needed based on whether the old reg is still valid or the object |
| 1507 | * is tiled) and inserting a new PTE into the faulting process. |
| 1508 | * |
| 1509 | * Note that the faulting process may involve evicting existing objects |
| 1510 | * from the GTT and/or fence registers to make room. So performance may |
| 1511 | * suffer if the GTT working set is large or there are few fence registers |
| 1512 | * left. |
| 1513 | */ |
| 1514 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1515 | { |
| 1516 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1517 | struct drm_device *dev = obj->base.dev; |
| 1518 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1519 | pgoff_t page_offset; |
| 1520 | unsigned long pfn; |
| 1521 | int ret = 0; |
| 1522 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
| 1523 | |
| 1524 | intel_runtime_pm_get(dev_priv); |
| 1525 | |
| 1526 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1527 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1528 | PAGE_SHIFT; |
| 1529 | |
| 1530 | ret = i915_mutex_lock_interruptible(dev); |
| 1531 | if (ret) |
| 1532 | goto out; |
| 1533 | |
| 1534 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1535 | |
| 1536 | /* Try to flush the object off the GPU first without holding the lock. |
| 1537 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1538 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1539 | * where we are gazumped. |
| 1540 | */ |
| 1541 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1542 | if (ret) |
| 1543 | goto unlock; |
| 1544 | |
| 1545 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1546 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1547 | ret = -EFAULT; |
| 1548 | goto unlock; |
| 1549 | } |
| 1550 | |
| 1551 | /* Now bind it into the GTT if needed */ |
| 1552 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
| 1553 | if (ret) |
| 1554 | goto unlock; |
| 1555 | |
| 1556 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1557 | if (ret) |
| 1558 | goto unpin; |
| 1559 | |
| 1560 | ret = i915_gem_object_get_fence(obj); |
| 1561 | if (ret) |
| 1562 | goto unpin; |
| 1563 | |
| 1564 | /* Finally, remap it using the new GTT offset */ |
| 1565 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
| 1566 | pfn >>= PAGE_SHIFT; |
| 1567 | |
| 1568 | if (!obj->fault_mappable) { |
| 1569 | unsigned long size = min_t(unsigned long, |
| 1570 | vma->vm_end - vma->vm_start, |
| 1571 | obj->base.size); |
| 1572 | int i; |
| 1573 | |
| 1574 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
| 1575 | ret = vm_insert_pfn(vma, |
| 1576 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1577 | pfn + i); |
| 1578 | if (ret) |
| 1579 | break; |
| 1580 | } |
| 1581 | |
| 1582 | obj->fault_mappable = true; |
| 1583 | } else |
| 1584 | ret = vm_insert_pfn(vma, |
| 1585 | (unsigned long)vmf->virtual_address, |
| 1586 | pfn + page_offset); |
| 1587 | unpin: |
| 1588 | i915_gem_object_ggtt_unpin(obj); |
| 1589 | unlock: |
| 1590 | mutex_unlock(&dev->struct_mutex); |
| 1591 | out: |
| 1592 | switch (ret) { |
| 1593 | case -EIO: |
| 1594 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1595 | * chance to clean up the mess. Otherwise return the proper |
| 1596 | * SIGBUS. */ |
| 1597 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
| 1598 | ret = VM_FAULT_SIGBUS; |
| 1599 | break; |
| 1600 | } |
| 1601 | case -EAGAIN: |
| 1602 | /* |
| 1603 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1604 | * handler to reset everything when re-faulting in |
| 1605 | * i915_mutex_lock_interruptible. |
| 1606 | */ |
| 1607 | case 0: |
| 1608 | case -ERESTARTSYS: |
| 1609 | case -EINTR: |
| 1610 | case -EBUSY: |
| 1611 | /* |
| 1612 | * EBUSY is ok: this just means that another thread |
| 1613 | * already did the job. |
| 1614 | */ |
| 1615 | ret = VM_FAULT_NOPAGE; |
| 1616 | break; |
| 1617 | case -ENOMEM: |
| 1618 | ret = VM_FAULT_OOM; |
| 1619 | break; |
| 1620 | case -ENOSPC: |
| 1621 | case -EFAULT: |
| 1622 | ret = VM_FAULT_SIGBUS; |
| 1623 | break; |
| 1624 | default: |
| 1625 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
| 1626 | ret = VM_FAULT_SIGBUS; |
| 1627 | break; |
| 1628 | } |
| 1629 | |
| 1630 | intel_runtime_pm_put(dev_priv); |
| 1631 | return ret; |
| 1632 | } |
| 1633 | |
| 1634 | /** |
| 1635 | * i915_gem_release_mmap - remove physical page mappings |
| 1636 | * @obj: obj in question |
| 1637 | * |
| 1638 | * Preserve the reservation of the mmapping with the DRM core code, but |
| 1639 | * relinquish ownership of the pages back to the system. |
| 1640 | * |
| 1641 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1642 | * object through the GTT and then lose the fence register due to |
| 1643 | * resource pressure. Similarly if the object has been moved out of the |
| 1644 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1645 | * mapping will then trigger a page fault on the next user access, allowing |
| 1646 | * fixup by i915_gem_fault(). |
| 1647 | */ |
| 1648 | void |
| 1649 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
| 1650 | { |
| 1651 | if (!obj->fault_mappable) |
| 1652 | return; |
| 1653 | |
| 1654 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1655 | obj->base.dev->anon_inode->i_mapping); |
| 1656 | obj->fault_mappable = false; |
| 1657 | } |
| 1658 | |
| 1659 | void |
| 1660 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1661 | { |
| 1662 | struct drm_i915_gem_object *obj; |
| 1663 | |
| 1664 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1665 | i915_gem_release_mmap(obj); |
| 1666 | } |
| 1667 | |
| 1668 | uint32_t |
| 1669 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
| 1670 | { |
| 1671 | uint32_t gtt_size; |
| 1672 | |
| 1673 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1674 | tiling_mode == I915_TILING_NONE) |
| 1675 | return size; |
| 1676 | |
| 1677 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1678 | if (INTEL_INFO(dev)->gen == 3) |
| 1679 | gtt_size = 1024*1024; |
| 1680 | else |
| 1681 | gtt_size = 512*1024; |
| 1682 | |
| 1683 | while (gtt_size < size) |
| 1684 | gtt_size <<= 1; |
| 1685 | |
| 1686 | return gtt_size; |
| 1687 | } |
| 1688 | |
| 1689 | /** |
| 1690 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1691 | * @obj: object to check |
| 1692 | * |
| 1693 | * Return the required GTT alignment for an object, taking into account |
| 1694 | * potential fence register mapping. |
| 1695 | */ |
| 1696 | uint32_t |
| 1697 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1698 | int tiling_mode, bool fenced) |
| 1699 | { |
| 1700 | /* |
| 1701 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1702 | * if a fence register is needed for the object. |
| 1703 | */ |
| 1704 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
| 1705 | tiling_mode == I915_TILING_NONE) |
| 1706 | return 4096; |
| 1707 | |
| 1708 | /* |
| 1709 | * Previous chips need to be aligned to the size of the smallest |
| 1710 | * fence register that can contain the object. |
| 1711 | */ |
| 1712 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
| 1713 | } |
| 1714 | |
| 1715 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1716 | { |
| 1717 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1718 | int ret; |
| 1719 | |
| 1720 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
| 1721 | return 0; |
| 1722 | |
| 1723 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1724 | |
| 1725 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1726 | if (ret != -ENOSPC) |
| 1727 | goto out; |
| 1728 | |
| 1729 | /* Badly fragmented mmap space? The only way we can recover |
| 1730 | * space is by destroying unwanted objects. We can't randomly release |
| 1731 | * mmap_offsets as userspace expects them to be persistent for the |
| 1732 | * lifetime of the objects. The closest we can is to release the |
| 1733 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1734 | * which prevents userspace from ever using that object again. |
| 1735 | */ |
| 1736 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1737 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1738 | if (ret != -ENOSPC) |
| 1739 | goto out; |
| 1740 | |
| 1741 | i915_gem_shrink_all(dev_priv); |
| 1742 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1743 | out: |
| 1744 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1745 | |
| 1746 | return ret; |
| 1747 | } |
| 1748 | |
| 1749 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1750 | { |
| 1751 | drm_gem_free_mmap_offset(&obj->base); |
| 1752 | } |
| 1753 | |
| 1754 | int |
| 1755 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1756 | struct drm_device *dev, |
| 1757 | uint32_t handle, |
| 1758 | uint64_t *offset) |
| 1759 | { |
| 1760 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1761 | struct drm_i915_gem_object *obj; |
| 1762 | int ret; |
| 1763 | |
| 1764 | ret = i915_mutex_lock_interruptible(dev); |
| 1765 | if (ret) |
| 1766 | return ret; |
| 1767 | |
| 1768 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
| 1769 | if (&obj->base == NULL) { |
| 1770 | ret = -ENOENT; |
| 1771 | goto unlock; |
| 1772 | } |
| 1773 | |
| 1774 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
| 1775 | ret = -E2BIG; |
| 1776 | goto out; |
| 1777 | } |
| 1778 | |
| 1779 | if (obj->madv != I915_MADV_WILLNEED) { |
| 1780 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
| 1781 | ret = -EFAULT; |
| 1782 | goto out; |
| 1783 | } |
| 1784 | |
| 1785 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1786 | if (ret) |
| 1787 | goto out; |
| 1788 | |
| 1789 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
| 1790 | |
| 1791 | out: |
| 1792 | drm_gem_object_unreference(&obj->base); |
| 1793 | unlock: |
| 1794 | mutex_unlock(&dev->struct_mutex); |
| 1795 | return ret; |
| 1796 | } |
| 1797 | |
| 1798 | /** |
| 1799 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1800 | * @dev: DRM device |
| 1801 | * @data: GTT mapping ioctl data |
| 1802 | * @file: GEM object info |
| 1803 | * |
| 1804 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1805 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1806 | * up so we can get faults in the handler above. |
| 1807 | * |
| 1808 | * The fault handler will take care of binding the object into the GTT |
| 1809 | * (since it may have been evicted to make room for something), allocating |
| 1810 | * a fence register, and mapping the appropriate aperture address into |
| 1811 | * userspace. |
| 1812 | */ |
| 1813 | int |
| 1814 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1815 | struct drm_file *file) |
| 1816 | { |
| 1817 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1818 | |
| 1819 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1820 | } |
| 1821 | |
| 1822 | static inline int |
| 1823 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1824 | { |
| 1825 | return obj->madv == I915_MADV_DONTNEED; |
| 1826 | } |
| 1827 | |
| 1828 | /* Immediately discard the backing storage */ |
| 1829 | static void |
| 1830 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
| 1831 | { |
| 1832 | i915_gem_object_free_mmap_offset(obj); |
| 1833 | |
| 1834 | if (obj->base.filp == NULL) |
| 1835 | return; |
| 1836 | |
| 1837 | /* Our goal here is to return as much of the memory as |
| 1838 | * is possible back to the system as we are called from OOM. |
| 1839 | * To do this we must instruct the shmfs to drop all of its |
| 1840 | * backing pages, *now*. |
| 1841 | */ |
| 1842 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
| 1843 | obj->madv = __I915_MADV_PURGED; |
| 1844 | } |
| 1845 | |
| 1846 | /* Try to discard unwanted pages */ |
| 1847 | static void |
| 1848 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
| 1849 | { |
| 1850 | struct address_space *mapping; |
| 1851 | |
| 1852 | switch (obj->madv) { |
| 1853 | case I915_MADV_DONTNEED: |
| 1854 | i915_gem_object_truncate(obj); |
| 1855 | case __I915_MADV_PURGED: |
| 1856 | return; |
| 1857 | } |
| 1858 | |
| 1859 | if (obj->base.filp == NULL) |
| 1860 | return; |
| 1861 | |
| 1862 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 1863 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
| 1864 | } |
| 1865 | |
| 1866 | static void |
| 1867 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
| 1868 | { |
| 1869 | struct sg_page_iter sg_iter; |
| 1870 | int ret; |
| 1871 | |
| 1872 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 1873 | |
| 1874 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1875 | if (ret) { |
| 1876 | /* In the event of a disaster, abandon all caches and |
| 1877 | * hope for the best. |
| 1878 | */ |
| 1879 | WARN_ON(ret != -EIO); |
| 1880 | i915_gem_clflush_object(obj, true); |
| 1881 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1882 | } |
| 1883 | |
| 1884 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 1885 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1886 | |
| 1887 | if (obj->madv == I915_MADV_DONTNEED) |
| 1888 | obj->dirty = 0; |
| 1889 | |
| 1890 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
| 1891 | struct page *page = sg_page_iter_page(&sg_iter); |
| 1892 | |
| 1893 | if (obj->dirty) |
| 1894 | set_page_dirty(page); |
| 1895 | |
| 1896 | if (obj->madv == I915_MADV_WILLNEED) |
| 1897 | mark_page_accessed(page); |
| 1898 | |
| 1899 | page_cache_release(page); |
| 1900 | } |
| 1901 | obj->dirty = 0; |
| 1902 | |
| 1903 | sg_free_table(obj->pages); |
| 1904 | kfree(obj->pages); |
| 1905 | } |
| 1906 | |
| 1907 | int |
| 1908 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1909 | { |
| 1910 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1911 | |
| 1912 | if (obj->pages == NULL) |
| 1913 | return 0; |
| 1914 | |
| 1915 | if (obj->pages_pin_count) |
| 1916 | return -EBUSY; |
| 1917 | |
| 1918 | BUG_ON(i915_gem_obj_bound_any(obj)); |
| 1919 | |
| 1920 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 1921 | * array, hence protect them from being reaped by removing them from gtt |
| 1922 | * lists early. */ |
| 1923 | list_del(&obj->global_list); |
| 1924 | |
| 1925 | ops->put_pages(obj); |
| 1926 | obj->pages = NULL; |
| 1927 | |
| 1928 | i915_gem_object_invalidate(obj); |
| 1929 | |
| 1930 | return 0; |
| 1931 | } |
| 1932 | |
| 1933 | static unsigned long |
| 1934 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
| 1935 | bool purgeable_only) |
| 1936 | { |
| 1937 | struct list_head still_in_list; |
| 1938 | struct drm_i915_gem_object *obj; |
| 1939 | unsigned long count = 0; |
| 1940 | |
| 1941 | /* |
| 1942 | * As we may completely rewrite the (un)bound list whilst unbinding |
| 1943 | * (due to retiring requests) we have to strictly process only |
| 1944 | * one element of the list at the time, and recheck the list |
| 1945 | * on every iteration. |
| 1946 | * |
| 1947 | * In particular, we must hold a reference whilst removing the |
| 1948 | * object as we may end up waiting for and/or retiring the objects. |
| 1949 | * This might release the final reference (held by the active list) |
| 1950 | * and result in the object being freed from under us. This is |
| 1951 | * similar to the precautions the eviction code must take whilst |
| 1952 | * removing objects. |
| 1953 | * |
| 1954 | * Also note that although these lists do not hold a reference to |
| 1955 | * the object we can safely grab one here: The final object |
| 1956 | * unreferencing and the bound_list are both protected by the |
| 1957 | * dev->struct_mutex and so we won't ever be able to observe an |
| 1958 | * object on the bound_list with a reference count equals 0. |
| 1959 | */ |
| 1960 | INIT_LIST_HEAD(&still_in_list); |
| 1961 | while (count < target && !list_empty(&dev_priv->mm.unbound_list)) { |
| 1962 | obj = list_first_entry(&dev_priv->mm.unbound_list, |
| 1963 | typeof(*obj), global_list); |
| 1964 | list_move_tail(&obj->global_list, &still_in_list); |
| 1965 | |
| 1966 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
| 1967 | continue; |
| 1968 | |
| 1969 | drm_gem_object_reference(&obj->base); |
| 1970 | |
| 1971 | if (i915_gem_object_put_pages(obj) == 0) |
| 1972 | count += obj->base.size >> PAGE_SHIFT; |
| 1973 | |
| 1974 | drm_gem_object_unreference(&obj->base); |
| 1975 | } |
| 1976 | list_splice(&still_in_list, &dev_priv->mm.unbound_list); |
| 1977 | |
| 1978 | INIT_LIST_HEAD(&still_in_list); |
| 1979 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
| 1980 | struct i915_vma *vma, *v; |
| 1981 | |
| 1982 | obj = list_first_entry(&dev_priv->mm.bound_list, |
| 1983 | typeof(*obj), global_list); |
| 1984 | list_move_tail(&obj->global_list, &still_in_list); |
| 1985 | |
| 1986 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
| 1987 | continue; |
| 1988 | |
| 1989 | drm_gem_object_reference(&obj->base); |
| 1990 | |
| 1991 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
| 1992 | if (i915_vma_unbind(vma)) |
| 1993 | break; |
| 1994 | |
| 1995 | if (i915_gem_object_put_pages(obj) == 0) |
| 1996 | count += obj->base.size >> PAGE_SHIFT; |
| 1997 | |
| 1998 | drm_gem_object_unreference(&obj->base); |
| 1999 | } |
| 2000 | list_splice(&still_in_list, &dev_priv->mm.bound_list); |
| 2001 | |
| 2002 | return count; |
| 2003 | } |
| 2004 | |
| 2005 | static unsigned long |
| 2006 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 2007 | { |
| 2008 | return __i915_gem_shrink(dev_priv, target, true); |
| 2009 | } |
| 2010 | |
| 2011 | static unsigned long |
| 2012 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 2013 | { |
| 2014 | i915_gem_evict_everything(dev_priv->dev); |
| 2015 | return __i915_gem_shrink(dev_priv, LONG_MAX, false); |
| 2016 | } |
| 2017 | |
| 2018 | static int |
| 2019 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
| 2020 | { |
| 2021 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2022 | int page_count, i; |
| 2023 | struct address_space *mapping; |
| 2024 | struct sg_table *st; |
| 2025 | struct scatterlist *sg; |
| 2026 | struct sg_page_iter sg_iter; |
| 2027 | struct page *page; |
| 2028 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
| 2029 | gfp_t gfp; |
| 2030 | |
| 2031 | /* Assert that the object is not currently in any GPU domain. As it |
| 2032 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2033 | * a GPU cache |
| 2034 | */ |
| 2035 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2036 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2037 | |
| 2038 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2039 | if (st == NULL) |
| 2040 | return -ENOMEM; |
| 2041 | |
| 2042 | page_count = obj->base.size / PAGE_SIZE; |
| 2043 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
| 2044 | kfree(st); |
| 2045 | return -ENOMEM; |
| 2046 | } |
| 2047 | |
| 2048 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2049 | * at this point until we release them. |
| 2050 | * |
| 2051 | * Fail silently without starting the shrinker |
| 2052 | */ |
| 2053 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 2054 | gfp = mapping_gfp_mask(mapping); |
| 2055 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
| 2056 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 2057 | sg = st->sgl; |
| 2058 | st->nents = 0; |
| 2059 | for (i = 0; i < page_count; i++) { |
| 2060 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2061 | if (IS_ERR(page)) { |
| 2062 | i915_gem_purge(dev_priv, page_count); |
| 2063 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2064 | } |
| 2065 | if (IS_ERR(page)) { |
| 2066 | /* We've tried hard to allocate the memory by reaping |
| 2067 | * our own buffer, now let the real VM do its job and |
| 2068 | * go down in flames if truly OOM. |
| 2069 | */ |
| 2070 | i915_gem_shrink_all(dev_priv); |
| 2071 | page = shmem_read_mapping_page(mapping, i); |
| 2072 | if (IS_ERR(page)) |
| 2073 | goto err_pages; |
| 2074 | } |
| 2075 | #ifdef CONFIG_SWIOTLB |
| 2076 | if (swiotlb_nr_tbl()) { |
| 2077 | st->nents++; |
| 2078 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2079 | sg = sg_next(sg); |
| 2080 | continue; |
| 2081 | } |
| 2082 | #endif |
| 2083 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2084 | if (i) |
| 2085 | sg = sg_next(sg); |
| 2086 | st->nents++; |
| 2087 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2088 | } else { |
| 2089 | sg->length += PAGE_SIZE; |
| 2090 | } |
| 2091 | last_pfn = page_to_pfn(page); |
| 2092 | |
| 2093 | /* Check that the i965g/gm workaround works. */ |
| 2094 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
| 2095 | } |
| 2096 | #ifdef CONFIG_SWIOTLB |
| 2097 | if (!swiotlb_nr_tbl()) |
| 2098 | #endif |
| 2099 | sg_mark_end(sg); |
| 2100 | obj->pages = st; |
| 2101 | |
| 2102 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2103 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2104 | |
| 2105 | return 0; |
| 2106 | |
| 2107 | err_pages: |
| 2108 | sg_mark_end(sg); |
| 2109 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
| 2110 | page_cache_release(sg_page_iter_page(&sg_iter)); |
| 2111 | sg_free_table(st); |
| 2112 | kfree(st); |
| 2113 | |
| 2114 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2115 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2116 | * ENOMEM for a genuine allocation failure. |
| 2117 | * |
| 2118 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2119 | * space and so want to translate the error from shmemfs back to our |
| 2120 | * usual understanding of ENOMEM. |
| 2121 | */ |
| 2122 | if (PTR_ERR(page) == -ENOSPC) |
| 2123 | return -ENOMEM; |
| 2124 | else |
| 2125 | return PTR_ERR(page); |
| 2126 | } |
| 2127 | |
| 2128 | /* Ensure that the associated pages are gathered from the backing storage |
| 2129 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2130 | * multiple times before they are released by a single call to |
| 2131 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2132 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2133 | * or as the object is itself released. |
| 2134 | */ |
| 2135 | int |
| 2136 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2137 | { |
| 2138 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2139 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2140 | int ret; |
| 2141 | |
| 2142 | if (obj->pages) |
| 2143 | return 0; |
| 2144 | |
| 2145 | if (obj->madv != I915_MADV_WILLNEED) { |
| 2146 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
| 2147 | return -EFAULT; |
| 2148 | } |
| 2149 | |
| 2150 | BUG_ON(obj->pages_pin_count); |
| 2151 | |
| 2152 | ret = ops->get_pages(obj); |
| 2153 | if (ret) |
| 2154 | return ret; |
| 2155 | |
| 2156 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
| 2157 | return 0; |
| 2158 | } |
| 2159 | |
| 2160 | static void |
| 2161 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
| 2162 | struct intel_engine_cs *ring) |
| 2163 | { |
| 2164 | u32 seqno = intel_ring_get_seqno(ring); |
| 2165 | |
| 2166 | BUG_ON(ring == NULL); |
| 2167 | if (obj->ring != ring && obj->last_write_seqno) { |
| 2168 | /* Keep the seqno relative to the current ring */ |
| 2169 | obj->last_write_seqno = seqno; |
| 2170 | } |
| 2171 | obj->ring = ring; |
| 2172 | |
| 2173 | /* Add a reference if we're newly entering the active list. */ |
| 2174 | if (!obj->active) { |
| 2175 | drm_gem_object_reference(&obj->base); |
| 2176 | obj->active = 1; |
| 2177 | } |
| 2178 | |
| 2179 | list_move_tail(&obj->ring_list, &ring->active_list); |
| 2180 | |
| 2181 | obj->last_read_seqno = seqno; |
| 2182 | } |
| 2183 | |
| 2184 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2185 | struct intel_engine_cs *ring) |
| 2186 | { |
| 2187 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
| 2188 | return i915_gem_object_move_to_active(vma->obj, ring); |
| 2189 | } |
| 2190 | |
| 2191 | static void |
| 2192 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 2193 | { |
| 2194 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2195 | struct i915_address_space *vm; |
| 2196 | struct i915_vma *vma; |
| 2197 | |
| 2198 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
| 2199 | BUG_ON(!obj->active); |
| 2200 | |
| 2201 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 2202 | vma = i915_gem_obj_to_vma(obj, vm); |
| 2203 | if (vma && !list_empty(&vma->mm_list)) |
| 2204 | list_move_tail(&vma->mm_list, &vm->inactive_list); |
| 2205 | } |
| 2206 | |
| 2207 | intel_fb_obj_flush(obj, true); |
| 2208 | |
| 2209 | list_del_init(&obj->ring_list); |
| 2210 | obj->ring = NULL; |
| 2211 | |
| 2212 | obj->last_read_seqno = 0; |
| 2213 | obj->last_write_seqno = 0; |
| 2214 | obj->base.write_domain = 0; |
| 2215 | |
| 2216 | obj->last_fenced_seqno = 0; |
| 2217 | |
| 2218 | obj->active = 0; |
| 2219 | drm_gem_object_unreference(&obj->base); |
| 2220 | |
| 2221 | WARN_ON(i915_verify_lists(dev)); |
| 2222 | } |
| 2223 | |
| 2224 | static void |
| 2225 | i915_gem_object_retire(struct drm_i915_gem_object *obj) |
| 2226 | { |
| 2227 | struct intel_engine_cs *ring = obj->ring; |
| 2228 | |
| 2229 | if (ring == NULL) |
| 2230 | return; |
| 2231 | |
| 2232 | if (i915_seqno_passed(ring->get_seqno(ring, true), |
| 2233 | obj->last_read_seqno)) |
| 2234 | i915_gem_object_move_to_inactive(obj); |
| 2235 | } |
| 2236 | |
| 2237 | static int |
| 2238 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
| 2239 | { |
| 2240 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2241 | struct intel_engine_cs *ring; |
| 2242 | int ret, i, j; |
| 2243 | |
| 2244 | /* Carefully retire all requests without writing to the rings */ |
| 2245 | for_each_ring(ring, dev_priv, i) { |
| 2246 | ret = intel_ring_idle(ring); |
| 2247 | if (ret) |
| 2248 | return ret; |
| 2249 | } |
| 2250 | i915_gem_retire_requests(dev); |
| 2251 | |
| 2252 | /* Finally reset hw state */ |
| 2253 | for_each_ring(ring, dev_priv, i) { |
| 2254 | intel_ring_init_seqno(ring, seqno); |
| 2255 | |
| 2256 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
| 2257 | ring->semaphore.sync_seqno[j] = 0; |
| 2258 | } |
| 2259 | |
| 2260 | return 0; |
| 2261 | } |
| 2262 | |
| 2263 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2264 | { |
| 2265 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2266 | int ret; |
| 2267 | |
| 2268 | if (seqno == 0) |
| 2269 | return -EINVAL; |
| 2270 | |
| 2271 | /* HWS page needs to be set less than what we |
| 2272 | * will inject to ring |
| 2273 | */ |
| 2274 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2275 | if (ret) |
| 2276 | return ret; |
| 2277 | |
| 2278 | /* Carefully set the last_seqno value so that wrap |
| 2279 | * detection still works |
| 2280 | */ |
| 2281 | dev_priv->next_seqno = seqno; |
| 2282 | dev_priv->last_seqno = seqno - 1; |
| 2283 | if (dev_priv->last_seqno == 0) |
| 2284 | dev_priv->last_seqno--; |
| 2285 | |
| 2286 | return 0; |
| 2287 | } |
| 2288 | |
| 2289 | int |
| 2290 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
| 2291 | { |
| 2292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2293 | |
| 2294 | /* reserve 0 for non-seqno */ |
| 2295 | if (dev_priv->next_seqno == 0) { |
| 2296 | int ret = i915_gem_init_seqno(dev, 0); |
| 2297 | if (ret) |
| 2298 | return ret; |
| 2299 | |
| 2300 | dev_priv->next_seqno = 1; |
| 2301 | } |
| 2302 | |
| 2303 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
| 2304 | return 0; |
| 2305 | } |
| 2306 | |
| 2307 | int __i915_add_request(struct intel_engine_cs *ring, |
| 2308 | struct drm_file *file, |
| 2309 | struct drm_i915_gem_object *obj, |
| 2310 | u32 *out_seqno) |
| 2311 | { |
| 2312 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 2313 | struct drm_i915_gem_request *request; |
| 2314 | u32 request_ring_position, request_start; |
| 2315 | int ret; |
| 2316 | |
| 2317 | request_start = intel_ring_get_tail(ring->buffer); |
| 2318 | /* |
| 2319 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2320 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2321 | * things up similar to emitting the lazy request. The difference here |
| 2322 | * is that the flush _must_ happen before the next request, no matter |
| 2323 | * what. |
| 2324 | */ |
| 2325 | ret = intel_ring_flush_all_caches(ring); |
| 2326 | if (ret) |
| 2327 | return ret; |
| 2328 | |
| 2329 | request = ring->preallocated_lazy_request; |
| 2330 | if (WARN_ON(request == NULL)) |
| 2331 | return -ENOMEM; |
| 2332 | |
| 2333 | /* Record the position of the start of the request so that |
| 2334 | * should we detect the updated seqno part-way through the |
| 2335 | * GPU processing the request, we never over-estimate the |
| 2336 | * position of the head. |
| 2337 | */ |
| 2338 | request_ring_position = intel_ring_get_tail(ring->buffer); |
| 2339 | |
| 2340 | ret = ring->add_request(ring); |
| 2341 | if (ret) |
| 2342 | return ret; |
| 2343 | |
| 2344 | request->seqno = intel_ring_get_seqno(ring); |
| 2345 | request->ring = ring; |
| 2346 | request->head = request_start; |
| 2347 | request->tail = request_ring_position; |
| 2348 | |
| 2349 | /* Whilst this request exists, batch_obj will be on the |
| 2350 | * active_list, and so will hold the active reference. Only when this |
| 2351 | * request is retired will the the batch_obj be moved onto the |
| 2352 | * inactive_list and lose its active reference. Hence we do not need |
| 2353 | * to explicitly hold another reference here. |
| 2354 | */ |
| 2355 | request->batch_obj = obj; |
| 2356 | |
| 2357 | /* Hold a reference to the current context so that we can inspect |
| 2358 | * it later in case a hangcheck error event fires. |
| 2359 | */ |
| 2360 | request->ctx = ring->last_context; |
| 2361 | if (request->ctx) |
| 2362 | i915_gem_context_reference(request->ctx); |
| 2363 | |
| 2364 | request->emitted_jiffies = jiffies; |
| 2365 | list_add_tail(&request->list, &ring->request_list); |
| 2366 | request->file_priv = NULL; |
| 2367 | |
| 2368 | if (file) { |
| 2369 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2370 | |
| 2371 | spin_lock(&file_priv->mm.lock); |
| 2372 | request->file_priv = file_priv; |
| 2373 | list_add_tail(&request->client_list, |
| 2374 | &file_priv->mm.request_list); |
| 2375 | spin_unlock(&file_priv->mm.lock); |
| 2376 | } |
| 2377 | |
| 2378 | trace_i915_gem_request_add(ring, request->seqno); |
| 2379 | ring->outstanding_lazy_seqno = 0; |
| 2380 | ring->preallocated_lazy_request = NULL; |
| 2381 | |
| 2382 | if (!dev_priv->ums.mm_suspended) { |
| 2383 | i915_queue_hangcheck(ring->dev); |
| 2384 | |
| 2385 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
| 2386 | queue_delayed_work(dev_priv->wq, |
| 2387 | &dev_priv->mm.retire_work, |
| 2388 | round_jiffies_up_relative(HZ)); |
| 2389 | intel_mark_busy(dev_priv->dev); |
| 2390 | } |
| 2391 | |
| 2392 | if (out_seqno) |
| 2393 | *out_seqno = request->seqno; |
| 2394 | return 0; |
| 2395 | } |
| 2396 | |
| 2397 | static inline void |
| 2398 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
| 2399 | { |
| 2400 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 2401 | |
| 2402 | if (!file_priv) |
| 2403 | return; |
| 2404 | |
| 2405 | spin_lock(&file_priv->mm.lock); |
| 2406 | list_del(&request->client_list); |
| 2407 | request->file_priv = NULL; |
| 2408 | spin_unlock(&file_priv->mm.lock); |
| 2409 | } |
| 2410 | |
| 2411 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
| 2412 | const struct intel_context *ctx) |
| 2413 | { |
| 2414 | unsigned long elapsed; |
| 2415 | |
| 2416 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2417 | |
| 2418 | if (ctx->hang_stats.banned) |
| 2419 | return true; |
| 2420 | |
| 2421 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
| 2422 | if (!i915_gem_context_is_default(ctx)) { |
| 2423 | DRM_DEBUG("context hanging too fast, banning!\n"); |
| 2424 | return true; |
| 2425 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2426 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2427 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
| 2428 | return true; |
| 2429 | } |
| 2430 | } |
| 2431 | |
| 2432 | return false; |
| 2433 | } |
| 2434 | |
| 2435 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
| 2436 | struct intel_context *ctx, |
| 2437 | const bool guilty) |
| 2438 | { |
| 2439 | struct i915_ctx_hang_stats *hs; |
| 2440 | |
| 2441 | if (WARN_ON(!ctx)) |
| 2442 | return; |
| 2443 | |
| 2444 | hs = &ctx->hang_stats; |
| 2445 | |
| 2446 | if (guilty) { |
| 2447 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
| 2448 | hs->batch_active++; |
| 2449 | hs->guilty_ts = get_seconds(); |
| 2450 | } else { |
| 2451 | hs->batch_pending++; |
| 2452 | } |
| 2453 | } |
| 2454 | |
| 2455 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
| 2456 | { |
| 2457 | list_del(&request->list); |
| 2458 | i915_gem_request_remove_from_client(request); |
| 2459 | |
| 2460 | if (request->ctx) |
| 2461 | i915_gem_context_unreference(request->ctx); |
| 2462 | |
| 2463 | kfree(request); |
| 2464 | } |
| 2465 | |
| 2466 | struct drm_i915_gem_request * |
| 2467 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
| 2468 | { |
| 2469 | struct drm_i915_gem_request *request; |
| 2470 | u32 completed_seqno; |
| 2471 | |
| 2472 | completed_seqno = ring->get_seqno(ring, false); |
| 2473 | |
| 2474 | list_for_each_entry(request, &ring->request_list, list) { |
| 2475 | if (i915_seqno_passed(completed_seqno, request->seqno)) |
| 2476 | continue; |
| 2477 | |
| 2478 | return request; |
| 2479 | } |
| 2480 | |
| 2481 | return NULL; |
| 2482 | } |
| 2483 | |
| 2484 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
| 2485 | struct intel_engine_cs *ring) |
| 2486 | { |
| 2487 | struct drm_i915_gem_request *request; |
| 2488 | bool ring_hung; |
| 2489 | |
| 2490 | request = i915_gem_find_active_request(ring); |
| 2491 | |
| 2492 | if (request == NULL) |
| 2493 | return; |
| 2494 | |
| 2495 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2496 | |
| 2497 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
| 2498 | |
| 2499 | list_for_each_entry_continue(request, &ring->request_list, list) |
| 2500 | i915_set_reset_status(dev_priv, request->ctx, false); |
| 2501 | } |
| 2502 | |
| 2503 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
| 2504 | struct intel_engine_cs *ring) |
| 2505 | { |
| 2506 | while (!list_empty(&ring->active_list)) { |
| 2507 | struct drm_i915_gem_object *obj; |
| 2508 | |
| 2509 | obj = list_first_entry(&ring->active_list, |
| 2510 | struct drm_i915_gem_object, |
| 2511 | ring_list); |
| 2512 | |
| 2513 | i915_gem_object_move_to_inactive(obj); |
| 2514 | } |
| 2515 | |
| 2516 | /* |
| 2517 | * We must free the requests after all the corresponding objects have |
| 2518 | * been moved off active lists. Which is the same order as the normal |
| 2519 | * retire_requests function does. This is important if object hold |
| 2520 | * implicit references on things like e.g. ppgtt address spaces through |
| 2521 | * the request. |
| 2522 | */ |
| 2523 | while (!list_empty(&ring->request_list)) { |
| 2524 | struct drm_i915_gem_request *request; |
| 2525 | |
| 2526 | request = list_first_entry(&ring->request_list, |
| 2527 | struct drm_i915_gem_request, |
| 2528 | list); |
| 2529 | |
| 2530 | i915_gem_free_request(request); |
| 2531 | } |
| 2532 | |
| 2533 | /* These may not have been flush before the reset, do so now */ |
| 2534 | kfree(ring->preallocated_lazy_request); |
| 2535 | ring->preallocated_lazy_request = NULL; |
| 2536 | ring->outstanding_lazy_seqno = 0; |
| 2537 | } |
| 2538 | |
| 2539 | void i915_gem_restore_fences(struct drm_device *dev) |
| 2540 | { |
| 2541 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2542 | int i; |
| 2543 | |
| 2544 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
| 2545 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
| 2546 | |
| 2547 | /* |
| 2548 | * Commit delayed tiling changes if we have an object still |
| 2549 | * attached to the fence, otherwise just clear the fence. |
| 2550 | */ |
| 2551 | if (reg->obj) { |
| 2552 | i915_gem_object_update_fence(reg->obj, reg, |
| 2553 | reg->obj->tiling_mode); |
| 2554 | } else { |
| 2555 | i915_gem_write_fence(dev, i, NULL); |
| 2556 | } |
| 2557 | } |
| 2558 | } |
| 2559 | |
| 2560 | void i915_gem_reset(struct drm_device *dev) |
| 2561 | { |
| 2562 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2563 | struct intel_engine_cs *ring; |
| 2564 | int i; |
| 2565 | |
| 2566 | /* |
| 2567 | * Before we free the objects from the requests, we need to inspect |
| 2568 | * them for finding the guilty party. As the requests only borrow |
| 2569 | * their reference to the objects, the inspection must be done first. |
| 2570 | */ |
| 2571 | for_each_ring(ring, dev_priv, i) |
| 2572 | i915_gem_reset_ring_status(dev_priv, ring); |
| 2573 | |
| 2574 | for_each_ring(ring, dev_priv, i) |
| 2575 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
| 2576 | |
| 2577 | i915_gem_context_reset(dev); |
| 2578 | |
| 2579 | i915_gem_restore_fences(dev); |
| 2580 | } |
| 2581 | |
| 2582 | /** |
| 2583 | * This function clears the request list as sequence numbers are passed. |
| 2584 | */ |
| 2585 | void |
| 2586 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
| 2587 | { |
| 2588 | uint32_t seqno; |
| 2589 | |
| 2590 | if (list_empty(&ring->request_list)) |
| 2591 | return; |
| 2592 | |
| 2593 | WARN_ON(i915_verify_lists(ring->dev)); |
| 2594 | |
| 2595 | seqno = ring->get_seqno(ring, true); |
| 2596 | |
| 2597 | /* Move any buffers on the active list that are no longer referenced |
| 2598 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2599 | * before we free the context associated with the requests. |
| 2600 | */ |
| 2601 | while (!list_empty(&ring->active_list)) { |
| 2602 | struct drm_i915_gem_object *obj; |
| 2603 | |
| 2604 | obj = list_first_entry(&ring->active_list, |
| 2605 | struct drm_i915_gem_object, |
| 2606 | ring_list); |
| 2607 | |
| 2608 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
| 2609 | break; |
| 2610 | |
| 2611 | i915_gem_object_move_to_inactive(obj); |
| 2612 | } |
| 2613 | |
| 2614 | |
| 2615 | while (!list_empty(&ring->request_list)) { |
| 2616 | struct drm_i915_gem_request *request; |
| 2617 | |
| 2618 | request = list_first_entry(&ring->request_list, |
| 2619 | struct drm_i915_gem_request, |
| 2620 | list); |
| 2621 | |
| 2622 | if (!i915_seqno_passed(seqno, request->seqno)) |
| 2623 | break; |
| 2624 | |
| 2625 | trace_i915_gem_request_retire(ring, request->seqno); |
| 2626 | /* We know the GPU must have read the request to have |
| 2627 | * sent us the seqno + interrupt, so use the position |
| 2628 | * of tail of the request to update the last known position |
| 2629 | * of the GPU head. |
| 2630 | */ |
| 2631 | ring->buffer->last_retired_head = request->tail; |
| 2632 | |
| 2633 | i915_gem_free_request(request); |
| 2634 | } |
| 2635 | |
| 2636 | if (unlikely(ring->trace_irq_seqno && |
| 2637 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
| 2638 | ring->irq_put(ring); |
| 2639 | ring->trace_irq_seqno = 0; |
| 2640 | } |
| 2641 | |
| 2642 | WARN_ON(i915_verify_lists(ring->dev)); |
| 2643 | } |
| 2644 | |
| 2645 | bool |
| 2646 | i915_gem_retire_requests(struct drm_device *dev) |
| 2647 | { |
| 2648 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2649 | struct intel_engine_cs *ring; |
| 2650 | bool idle = true; |
| 2651 | int i; |
| 2652 | |
| 2653 | for_each_ring(ring, dev_priv, i) { |
| 2654 | i915_gem_retire_requests_ring(ring); |
| 2655 | idle &= list_empty(&ring->request_list); |
| 2656 | } |
| 2657 | |
| 2658 | if (idle) |
| 2659 | mod_delayed_work(dev_priv->wq, |
| 2660 | &dev_priv->mm.idle_work, |
| 2661 | msecs_to_jiffies(100)); |
| 2662 | |
| 2663 | return idle; |
| 2664 | } |
| 2665 | |
| 2666 | static void |
| 2667 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2668 | { |
| 2669 | struct drm_i915_private *dev_priv = |
| 2670 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 2671 | struct drm_device *dev = dev_priv->dev; |
| 2672 | bool idle; |
| 2673 | |
| 2674 | /* Come back later if the device is busy... */ |
| 2675 | idle = false; |
| 2676 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2677 | idle = i915_gem_retire_requests(dev); |
| 2678 | mutex_unlock(&dev->struct_mutex); |
| 2679 | } |
| 2680 | if (!idle) |
| 2681 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2682 | round_jiffies_up_relative(HZ)); |
| 2683 | } |
| 2684 | |
| 2685 | static void |
| 2686 | i915_gem_idle_work_handler(struct work_struct *work) |
| 2687 | { |
| 2688 | struct drm_i915_private *dev_priv = |
| 2689 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
| 2690 | |
| 2691 | intel_mark_idle(dev_priv->dev); |
| 2692 | } |
| 2693 | |
| 2694 | /** |
| 2695 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2696 | * write domains, emitting any outstanding lazy request and retiring and |
| 2697 | * completed requests. |
| 2698 | */ |
| 2699 | static int |
| 2700 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2701 | { |
| 2702 | int ret; |
| 2703 | |
| 2704 | if (obj->active) { |
| 2705 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
| 2706 | if (ret) |
| 2707 | return ret; |
| 2708 | |
| 2709 | i915_gem_retire_requests_ring(obj->ring); |
| 2710 | } |
| 2711 | |
| 2712 | return 0; |
| 2713 | } |
| 2714 | |
| 2715 | /** |
| 2716 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2717 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2718 | * |
| 2719 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2720 | * the timeout parameter. |
| 2721 | * -ETIME: object is still busy after timeout |
| 2722 | * -ERESTARTSYS: signal interrupted the wait |
| 2723 | * -ENONENT: object doesn't exist |
| 2724 | * Also possible, but rare: |
| 2725 | * -EAGAIN: GPU wedged |
| 2726 | * -ENOMEM: damn |
| 2727 | * -ENODEV: Internal IRQ fail |
| 2728 | * -E?: The add request failed |
| 2729 | * |
| 2730 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2731 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2732 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2733 | * without holding struct_mutex the object may become re-busied before this |
| 2734 | * function completes. A similar but shorter * race condition exists in the busy |
| 2735 | * ioctl |
| 2736 | */ |
| 2737 | int |
| 2738 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2739 | { |
| 2740 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2741 | struct drm_i915_gem_wait *args = data; |
| 2742 | struct drm_i915_gem_object *obj; |
| 2743 | struct intel_engine_cs *ring = NULL; |
| 2744 | struct timespec timeout_stack, *timeout = NULL; |
| 2745 | unsigned reset_counter; |
| 2746 | u32 seqno = 0; |
| 2747 | int ret = 0; |
| 2748 | |
| 2749 | if (args->timeout_ns >= 0) { |
| 2750 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2751 | timeout = &timeout_stack; |
| 2752 | } |
| 2753 | |
| 2754 | ret = i915_mutex_lock_interruptible(dev); |
| 2755 | if (ret) |
| 2756 | return ret; |
| 2757 | |
| 2758 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2759 | if (&obj->base == NULL) { |
| 2760 | mutex_unlock(&dev->struct_mutex); |
| 2761 | return -ENOENT; |
| 2762 | } |
| 2763 | |
| 2764 | /* Need to make sure the object gets inactive eventually. */ |
| 2765 | ret = i915_gem_object_flush_active(obj); |
| 2766 | if (ret) |
| 2767 | goto out; |
| 2768 | |
| 2769 | if (obj->active) { |
| 2770 | seqno = obj->last_read_seqno; |
| 2771 | ring = obj->ring; |
| 2772 | } |
| 2773 | |
| 2774 | if (seqno == 0) |
| 2775 | goto out; |
| 2776 | |
| 2777 | /* Do this after OLR check to make sure we make forward progress polling |
| 2778 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2779 | */ |
| 2780 | if (!args->timeout_ns) { |
| 2781 | ret = -ETIME; |
| 2782 | goto out; |
| 2783 | } |
| 2784 | |
| 2785 | drm_gem_object_unreference(&obj->base); |
| 2786 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 2787 | mutex_unlock(&dev->struct_mutex); |
| 2788 | |
| 2789 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
| 2790 | if (timeout) |
| 2791 | args->timeout_ns = timespec_to_ns(timeout); |
| 2792 | return ret; |
| 2793 | |
| 2794 | out: |
| 2795 | drm_gem_object_unreference(&obj->base); |
| 2796 | mutex_unlock(&dev->struct_mutex); |
| 2797 | return ret; |
| 2798 | } |
| 2799 | |
| 2800 | /** |
| 2801 | * i915_gem_object_sync - sync an object to a ring. |
| 2802 | * |
| 2803 | * @obj: object which may be in use on another ring. |
| 2804 | * @to: ring we wish to use the object on. May be NULL. |
| 2805 | * |
| 2806 | * This code is meant to abstract object synchronization with the GPU. |
| 2807 | * Calling with NULL implies synchronizing the object with the CPU |
| 2808 | * rather than a particular GPU ring. |
| 2809 | * |
| 2810 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2811 | */ |
| 2812 | int |
| 2813 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2814 | struct intel_engine_cs *to) |
| 2815 | { |
| 2816 | struct intel_engine_cs *from = obj->ring; |
| 2817 | u32 seqno; |
| 2818 | int ret, idx; |
| 2819 | |
| 2820 | if (from == NULL || to == from) |
| 2821 | return 0; |
| 2822 | |
| 2823 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
| 2824 | return i915_gem_object_wait_rendering(obj, false); |
| 2825 | |
| 2826 | idx = intel_ring_sync_index(from, to); |
| 2827 | |
| 2828 | seqno = obj->last_read_seqno; |
| 2829 | /* Optimization: Avoid semaphore sync when we are sure we already |
| 2830 | * waited for an object with higher seqno */ |
| 2831 | if (seqno <= from->semaphore.sync_seqno[idx]) |
| 2832 | return 0; |
| 2833 | |
| 2834 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2835 | if (ret) |
| 2836 | return ret; |
| 2837 | |
| 2838 | trace_i915_gem_ring_sync_to(from, to, seqno); |
| 2839 | ret = to->semaphore.sync_to(to, from, seqno); |
| 2840 | if (!ret) |
| 2841 | /* We use last_read_seqno because sync_to() |
| 2842 | * might have just caused seqno wrap under |
| 2843 | * the radar. |
| 2844 | */ |
| 2845 | from->semaphore.sync_seqno[idx] = obj->last_read_seqno; |
| 2846 | |
| 2847 | return ret; |
| 2848 | } |
| 2849 | |
| 2850 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2851 | { |
| 2852 | u32 old_write_domain, old_read_domains; |
| 2853 | |
| 2854 | /* Force a pagefault for domain tracking on next user access */ |
| 2855 | i915_gem_release_mmap(obj); |
| 2856 | |
| 2857 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2858 | return; |
| 2859 | |
| 2860 | /* Wait for any direct GTT access to complete */ |
| 2861 | mb(); |
| 2862 | |
| 2863 | old_read_domains = obj->base.read_domains; |
| 2864 | old_write_domain = obj->base.write_domain; |
| 2865 | |
| 2866 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2867 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2868 | |
| 2869 | trace_i915_gem_object_change_domain(obj, |
| 2870 | old_read_domains, |
| 2871 | old_write_domain); |
| 2872 | } |
| 2873 | |
| 2874 | int i915_vma_unbind(struct i915_vma *vma) |
| 2875 | { |
| 2876 | struct drm_i915_gem_object *obj = vma->obj; |
| 2877 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2878 | int ret; |
| 2879 | |
| 2880 | if (list_empty(&vma->vma_link)) |
| 2881 | return 0; |
| 2882 | |
| 2883 | if (!drm_mm_node_allocated(&vma->node)) { |
| 2884 | i915_gem_vma_destroy(vma); |
| 2885 | return 0; |
| 2886 | } |
| 2887 | |
| 2888 | if (vma->pin_count) |
| 2889 | return -EBUSY; |
| 2890 | |
| 2891 | BUG_ON(obj->pages == NULL); |
| 2892 | |
| 2893 | ret = i915_gem_object_finish_gpu(obj); |
| 2894 | if (ret) |
| 2895 | return ret; |
| 2896 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2897 | * should be safe and we need to cleanup or else we might |
| 2898 | * cause memory corruption through use-after-free. |
| 2899 | */ |
| 2900 | |
| 2901 | if (i915_is_ggtt(vma->vm)) { |
| 2902 | i915_gem_object_finish_gtt(obj); |
| 2903 | |
| 2904 | /* release the fence reg _after_ flushing */ |
| 2905 | ret = i915_gem_object_put_fence(obj); |
| 2906 | if (ret) |
| 2907 | return ret; |
| 2908 | } |
| 2909 | |
| 2910 | trace_i915_vma_unbind(vma); |
| 2911 | |
| 2912 | vma->unbind_vma(vma); |
| 2913 | |
| 2914 | list_del_init(&vma->mm_list); |
| 2915 | if (i915_is_ggtt(vma->vm)) |
| 2916 | obj->map_and_fenceable = false; |
| 2917 | |
| 2918 | drm_mm_remove_node(&vma->node); |
| 2919 | i915_gem_vma_destroy(vma); |
| 2920 | |
| 2921 | /* Since the unbound list is global, only move to that list if |
| 2922 | * no more VMAs exist. */ |
| 2923 | if (list_empty(&obj->vma_list)) { |
| 2924 | i915_gem_gtt_finish_object(obj); |
| 2925 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
| 2926 | } |
| 2927 | |
| 2928 | /* And finally now the object is completely decoupled from this vma, |
| 2929 | * we can drop its hold on the backing storage and allow it to be |
| 2930 | * reaped by the shrinker. |
| 2931 | */ |
| 2932 | i915_gem_object_unpin_pages(obj); |
| 2933 | |
| 2934 | return 0; |
| 2935 | } |
| 2936 | |
| 2937 | int i915_gpu_idle(struct drm_device *dev) |
| 2938 | { |
| 2939 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2940 | struct intel_engine_cs *ring; |
| 2941 | int ret, i; |
| 2942 | |
| 2943 | /* Flush everything onto the inactive list. */ |
| 2944 | for_each_ring(ring, dev_priv, i) { |
| 2945 | ret = i915_switch_context(ring, ring->default_context); |
| 2946 | if (ret) |
| 2947 | return ret; |
| 2948 | |
| 2949 | ret = intel_ring_idle(ring); |
| 2950 | if (ret) |
| 2951 | return ret; |
| 2952 | } |
| 2953 | |
| 2954 | return 0; |
| 2955 | } |
| 2956 | |
| 2957 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2958 | struct drm_i915_gem_object *obj) |
| 2959 | { |
| 2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2961 | int fence_reg; |
| 2962 | int fence_pitch_shift; |
| 2963 | |
| 2964 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2965 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 2966 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2967 | } else { |
| 2968 | fence_reg = FENCE_REG_965_0; |
| 2969 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 2970 | } |
| 2971 | |
| 2972 | fence_reg += reg * 8; |
| 2973 | |
| 2974 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 2975 | * we split the 64-bit update into two 32-bit writes. In order |
| 2976 | * for a partial fence not to be evaluated between writes, we |
| 2977 | * precede the update with write to turn off the fence register, |
| 2978 | * and only enable the fence as the last step. |
| 2979 | * |
| 2980 | * For extra levels of paranoia, we make sure each step lands |
| 2981 | * before applying the next step. |
| 2982 | */ |
| 2983 | I915_WRITE(fence_reg, 0); |
| 2984 | POSTING_READ(fence_reg); |
| 2985 | |
| 2986 | if (obj) { |
| 2987 | u32 size = i915_gem_obj_ggtt_size(obj); |
| 2988 | uint64_t val; |
| 2989 | |
| 2990 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
| 2991 | 0xfffff000) << 32; |
| 2992 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
| 2993 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
| 2994 | if (obj->tiling_mode == I915_TILING_Y) |
| 2995 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2996 | val |= I965_FENCE_REG_VALID; |
| 2997 | |
| 2998 | I915_WRITE(fence_reg + 4, val >> 32); |
| 2999 | POSTING_READ(fence_reg + 4); |
| 3000 | |
| 3001 | I915_WRITE(fence_reg + 0, val); |
| 3002 | POSTING_READ(fence_reg); |
| 3003 | } else { |
| 3004 | I915_WRITE(fence_reg + 4, 0); |
| 3005 | POSTING_READ(fence_reg + 4); |
| 3006 | } |
| 3007 | } |
| 3008 | |
| 3009 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 3010 | struct drm_i915_gem_object *obj) |
| 3011 | { |
| 3012 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3013 | u32 val; |
| 3014 | |
| 3015 | if (obj) { |
| 3016 | u32 size = i915_gem_obj_ggtt_size(obj); |
| 3017 | int pitch_val; |
| 3018 | int tile_width; |
| 3019 | |
| 3020 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
| 3021 | (size & -size) != size || |
| 3022 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3023 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 3024 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
| 3025 | |
| 3026 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 3027 | tile_width = 128; |
| 3028 | else |
| 3029 | tile_width = 512; |
| 3030 | |
| 3031 | /* Note: pitch better be a power of two tile widths */ |
| 3032 | pitch_val = obj->stride / tile_width; |
| 3033 | pitch_val = ffs(pitch_val) - 1; |
| 3034 | |
| 3035 | val = i915_gem_obj_ggtt_offset(obj); |
| 3036 | if (obj->tiling_mode == I915_TILING_Y) |
| 3037 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3038 | val |= I915_FENCE_SIZE_BITS(size); |
| 3039 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3040 | val |= I830_FENCE_REG_VALID; |
| 3041 | } else |
| 3042 | val = 0; |
| 3043 | |
| 3044 | if (reg < 8) |
| 3045 | reg = FENCE_REG_830_0 + reg * 4; |
| 3046 | else |
| 3047 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
| 3048 | |
| 3049 | I915_WRITE(reg, val); |
| 3050 | POSTING_READ(reg); |
| 3051 | } |
| 3052 | |
| 3053 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 3054 | struct drm_i915_gem_object *obj) |
| 3055 | { |
| 3056 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3057 | uint32_t val; |
| 3058 | |
| 3059 | if (obj) { |
| 3060 | u32 size = i915_gem_obj_ggtt_size(obj); |
| 3061 | uint32_t pitch_val; |
| 3062 | |
| 3063 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
| 3064 | (size & -size) != size || |
| 3065 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3066 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 3067 | i915_gem_obj_ggtt_offset(obj), size); |
| 3068 | |
| 3069 | pitch_val = obj->stride / 128; |
| 3070 | pitch_val = ffs(pitch_val) - 1; |
| 3071 | |
| 3072 | val = i915_gem_obj_ggtt_offset(obj); |
| 3073 | if (obj->tiling_mode == I915_TILING_Y) |
| 3074 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3075 | val |= I830_FENCE_SIZE_BITS(size); |
| 3076 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3077 | val |= I830_FENCE_REG_VALID; |
| 3078 | } else |
| 3079 | val = 0; |
| 3080 | |
| 3081 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 3082 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 3083 | } |
| 3084 | |
| 3085 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 3086 | { |
| 3087 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 3088 | } |
| 3089 | |
| 3090 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 3091 | struct drm_i915_gem_object *obj) |
| 3092 | { |
| 3093 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3094 | |
| 3095 | /* Ensure that all CPU reads are completed before installing a fence |
| 3096 | * and all writes before removing the fence. |
| 3097 | */ |
| 3098 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 3099 | mb(); |
| 3100 | |
| 3101 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 3102 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 3103 | obj->stride, obj->tiling_mode); |
| 3104 | |
| 3105 | switch (INTEL_INFO(dev)->gen) { |
| 3106 | case 8: |
| 3107 | case 7: |
| 3108 | case 6: |
| 3109 | case 5: |
| 3110 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 3111 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 3112 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
| 3113 | default: BUG(); |
| 3114 | } |
| 3115 | |
| 3116 | /* And similarly be paranoid that no direct access to this region |
| 3117 | * is reordered to before the fence is installed. |
| 3118 | */ |
| 3119 | if (i915_gem_object_needs_mb(obj)) |
| 3120 | mb(); |
| 3121 | } |
| 3122 | |
| 3123 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 3124 | struct drm_i915_fence_reg *fence) |
| 3125 | { |
| 3126 | return fence - dev_priv->fence_regs; |
| 3127 | } |
| 3128 | |
| 3129 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 3130 | struct drm_i915_fence_reg *fence, |
| 3131 | bool enable) |
| 3132 | { |
| 3133 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3134 | int reg = fence_number(dev_priv, fence); |
| 3135 | |
| 3136 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 3137 | |
| 3138 | if (enable) { |
| 3139 | obj->fence_reg = reg; |
| 3140 | fence->obj = obj; |
| 3141 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 3142 | } else { |
| 3143 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3144 | fence->obj = NULL; |
| 3145 | list_del_init(&fence->lru_list); |
| 3146 | } |
| 3147 | obj->fence_dirty = false; |
| 3148 | } |
| 3149 | |
| 3150 | static int |
| 3151 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
| 3152 | { |
| 3153 | if (obj->last_fenced_seqno) { |
| 3154 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
| 3155 | if (ret) |
| 3156 | return ret; |
| 3157 | |
| 3158 | obj->last_fenced_seqno = 0; |
| 3159 | } |
| 3160 | |
| 3161 | return 0; |
| 3162 | } |
| 3163 | |
| 3164 | int |
| 3165 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 3166 | { |
| 3167 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3168 | struct drm_i915_fence_reg *fence; |
| 3169 | int ret; |
| 3170 | |
| 3171 | ret = i915_gem_object_wait_fence(obj); |
| 3172 | if (ret) |
| 3173 | return ret; |
| 3174 | |
| 3175 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 3176 | return 0; |
| 3177 | |
| 3178 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 3179 | |
| 3180 | if (WARN_ON(fence->pin_count)) |
| 3181 | return -EBUSY; |
| 3182 | |
| 3183 | i915_gem_object_fence_lost(obj); |
| 3184 | i915_gem_object_update_fence(obj, fence, false); |
| 3185 | |
| 3186 | return 0; |
| 3187 | } |
| 3188 | |
| 3189 | static struct drm_i915_fence_reg * |
| 3190 | i915_find_fence_reg(struct drm_device *dev) |
| 3191 | { |
| 3192 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3193 | struct drm_i915_fence_reg *reg, *avail; |
| 3194 | int i; |
| 3195 | |
| 3196 | /* First try to find a free reg */ |
| 3197 | avail = NULL; |
| 3198 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 3199 | reg = &dev_priv->fence_regs[i]; |
| 3200 | if (!reg->obj) |
| 3201 | return reg; |
| 3202 | |
| 3203 | if (!reg->pin_count) |
| 3204 | avail = reg; |
| 3205 | } |
| 3206 | |
| 3207 | if (avail == NULL) |
| 3208 | goto deadlock; |
| 3209 | |
| 3210 | /* None available, try to steal one or wait for a user to finish */ |
| 3211 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
| 3212 | if (reg->pin_count) |
| 3213 | continue; |
| 3214 | |
| 3215 | return reg; |
| 3216 | } |
| 3217 | |
| 3218 | deadlock: |
| 3219 | /* Wait for completion of pending flips which consume fences */ |
| 3220 | if (intel_has_pending_fb_unpin(dev)) |
| 3221 | return ERR_PTR(-EAGAIN); |
| 3222 | |
| 3223 | return ERR_PTR(-EDEADLK); |
| 3224 | } |
| 3225 | |
| 3226 | /** |
| 3227 | * i915_gem_object_get_fence - set up fencing for an object |
| 3228 | * @obj: object to map through a fence reg |
| 3229 | * |
| 3230 | * When mapping objects through the GTT, userspace wants to be able to write |
| 3231 | * to them without having to worry about swizzling if the object is tiled. |
| 3232 | * This function walks the fence regs looking for a free one for @obj, |
| 3233 | * stealing one if it can't find any. |
| 3234 | * |
| 3235 | * It then sets up the reg based on the object's properties: address, pitch |
| 3236 | * and tiling format. |
| 3237 | * |
| 3238 | * For an untiled surface, this removes any existing fence. |
| 3239 | */ |
| 3240 | int |
| 3241 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
| 3242 | { |
| 3243 | struct drm_device *dev = obj->base.dev; |
| 3244 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3245 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
| 3246 | struct drm_i915_fence_reg *reg; |
| 3247 | int ret; |
| 3248 | |
| 3249 | /* Have we updated the tiling parameters upon the object and so |
| 3250 | * will need to serialise the write to the associated fence register? |
| 3251 | */ |
| 3252 | if (obj->fence_dirty) { |
| 3253 | ret = i915_gem_object_wait_fence(obj); |
| 3254 | if (ret) |
| 3255 | return ret; |
| 3256 | } |
| 3257 | |
| 3258 | /* Just update our place in the LRU if our fence is getting reused. */ |
| 3259 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3260 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 3261 | if (!obj->fence_dirty) { |
| 3262 | list_move_tail(®->lru_list, |
| 3263 | &dev_priv->mm.fence_list); |
| 3264 | return 0; |
| 3265 | } |
| 3266 | } else if (enable) { |
| 3267 | if (WARN_ON(!obj->map_and_fenceable)) |
| 3268 | return -EINVAL; |
| 3269 | |
| 3270 | reg = i915_find_fence_reg(dev); |
| 3271 | if (IS_ERR(reg)) |
| 3272 | return PTR_ERR(reg); |
| 3273 | |
| 3274 | if (reg->obj) { |
| 3275 | struct drm_i915_gem_object *old = reg->obj; |
| 3276 | |
| 3277 | ret = i915_gem_object_wait_fence(old); |
| 3278 | if (ret) |
| 3279 | return ret; |
| 3280 | |
| 3281 | i915_gem_object_fence_lost(old); |
| 3282 | } |
| 3283 | } else |
| 3284 | return 0; |
| 3285 | |
| 3286 | i915_gem_object_update_fence(obj, reg, enable); |
| 3287 | |
| 3288 | return 0; |
| 3289 | } |
| 3290 | |
| 3291 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 3292 | struct drm_mm_node *gtt_space, |
| 3293 | unsigned long cache_level) |
| 3294 | { |
| 3295 | struct drm_mm_node *other; |
| 3296 | |
| 3297 | /* On non-LLC machines we have to be careful when putting differing |
| 3298 | * types of snoopable memory together to avoid the prefetcher |
| 3299 | * crossing memory domains and dying. |
| 3300 | */ |
| 3301 | if (HAS_LLC(dev)) |
| 3302 | return true; |
| 3303 | |
| 3304 | if (!drm_mm_node_allocated(gtt_space)) |
| 3305 | return true; |
| 3306 | |
| 3307 | if (list_empty(>t_space->node_list)) |
| 3308 | return true; |
| 3309 | |
| 3310 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3311 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3312 | return false; |
| 3313 | |
| 3314 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3315 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3316 | return false; |
| 3317 | |
| 3318 | return true; |
| 3319 | } |
| 3320 | |
| 3321 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 3322 | { |
| 3323 | #if WATCH_GTT |
| 3324 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3325 | struct drm_i915_gem_object *obj; |
| 3326 | int err = 0; |
| 3327 | |
| 3328 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
| 3329 | if (obj->gtt_space == NULL) { |
| 3330 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 3331 | err++; |
| 3332 | continue; |
| 3333 | } |
| 3334 | |
| 3335 | if (obj->cache_level != obj->gtt_space->color) { |
| 3336 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
| 3337 | i915_gem_obj_ggtt_offset(obj), |
| 3338 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
| 3339 | obj->cache_level, |
| 3340 | obj->gtt_space->color); |
| 3341 | err++; |
| 3342 | continue; |
| 3343 | } |
| 3344 | |
| 3345 | if (!i915_gem_valid_gtt_space(dev, |
| 3346 | obj->gtt_space, |
| 3347 | obj->cache_level)) { |
| 3348 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
| 3349 | i915_gem_obj_ggtt_offset(obj), |
| 3350 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
| 3351 | obj->cache_level); |
| 3352 | err++; |
| 3353 | continue; |
| 3354 | } |
| 3355 | } |
| 3356 | |
| 3357 | WARN_ON(err); |
| 3358 | #endif |
| 3359 | } |
| 3360 | |
| 3361 | /** |
| 3362 | * Finds free space in the GTT aperture and binds the object there. |
| 3363 | */ |
| 3364 | static struct i915_vma * |
| 3365 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3366 | struct i915_address_space *vm, |
| 3367 | unsigned alignment, |
| 3368 | uint64_t flags) |
| 3369 | { |
| 3370 | struct drm_device *dev = obj->base.dev; |
| 3371 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3372 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
| 3373 | unsigned long start = |
| 3374 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3375 | unsigned long end = |
| 3376 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
| 3377 | struct i915_vma *vma; |
| 3378 | int ret; |
| 3379 | |
| 3380 | fence_size = i915_gem_get_gtt_size(dev, |
| 3381 | obj->base.size, |
| 3382 | obj->tiling_mode); |
| 3383 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3384 | obj->base.size, |
| 3385 | obj->tiling_mode, true); |
| 3386 | unfenced_alignment = |
| 3387 | i915_gem_get_gtt_alignment(dev, |
| 3388 | obj->base.size, |
| 3389 | obj->tiling_mode, false); |
| 3390 | |
| 3391 | if (alignment == 0) |
| 3392 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
| 3393 | unfenced_alignment; |
| 3394 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
| 3395 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
| 3396 | return ERR_PTR(-EINVAL); |
| 3397 | } |
| 3398 | |
| 3399 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
| 3400 | |
| 3401 | /* If the object is bigger than the entire aperture, reject it early |
| 3402 | * before evicting everything in a vain attempt to find space. |
| 3403 | */ |
| 3404 | if (obj->base.size > end) { |
| 3405 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", |
| 3406 | obj->base.size, |
| 3407 | flags & PIN_MAPPABLE ? "mappable" : "total", |
| 3408 | end); |
| 3409 | return ERR_PTR(-E2BIG); |
| 3410 | } |
| 3411 | |
| 3412 | ret = i915_gem_object_get_pages(obj); |
| 3413 | if (ret) |
| 3414 | return ERR_PTR(ret); |
| 3415 | |
| 3416 | i915_gem_object_pin_pages(obj); |
| 3417 | |
| 3418 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
| 3419 | if (IS_ERR(vma)) |
| 3420 | goto err_unpin; |
| 3421 | |
| 3422 | search_free: |
| 3423 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
| 3424 | size, alignment, |
| 3425 | obj->cache_level, |
| 3426 | start, end, |
| 3427 | DRM_MM_SEARCH_DEFAULT, |
| 3428 | DRM_MM_CREATE_DEFAULT); |
| 3429 | if (ret) { |
| 3430 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
| 3431 | obj->cache_level, |
| 3432 | start, end, |
| 3433 | flags); |
| 3434 | if (ret == 0) |
| 3435 | goto search_free; |
| 3436 | |
| 3437 | goto err_free_vma; |
| 3438 | } |
| 3439 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
| 3440 | obj->cache_level))) { |
| 3441 | ret = -EINVAL; |
| 3442 | goto err_remove_node; |
| 3443 | } |
| 3444 | |
| 3445 | ret = i915_gem_gtt_prepare_object(obj); |
| 3446 | if (ret) |
| 3447 | goto err_remove_node; |
| 3448 | |
| 3449 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
| 3450 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
| 3451 | |
| 3452 | if (i915_is_ggtt(vm)) { |
| 3453 | bool mappable, fenceable; |
| 3454 | |
| 3455 | fenceable = (vma->node.size == fence_size && |
| 3456 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 3457 | |
| 3458 | mappable = (vma->node.start + obj->base.size <= |
| 3459 | dev_priv->gtt.mappable_end); |
| 3460 | |
| 3461 | obj->map_and_fenceable = mappable && fenceable; |
| 3462 | } |
| 3463 | |
| 3464 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 3465 | |
| 3466 | trace_i915_vma_bind(vma, flags); |
| 3467 | vma->bind_vma(vma, obj->cache_level, |
| 3468 | flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); |
| 3469 | |
| 3470 | i915_gem_verify_gtt(dev); |
| 3471 | return vma; |
| 3472 | |
| 3473 | err_remove_node: |
| 3474 | drm_mm_remove_node(&vma->node); |
| 3475 | err_free_vma: |
| 3476 | i915_gem_vma_destroy(vma); |
| 3477 | vma = ERR_PTR(ret); |
| 3478 | err_unpin: |
| 3479 | i915_gem_object_unpin_pages(obj); |
| 3480 | return vma; |
| 3481 | } |
| 3482 | |
| 3483 | bool |
| 3484 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3485 | bool force) |
| 3486 | { |
| 3487 | /* If we don't have a page list set up, then we're not pinned |
| 3488 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3489 | * again at bind time. |
| 3490 | */ |
| 3491 | if (obj->pages == NULL) |
| 3492 | return false; |
| 3493 | |
| 3494 | /* |
| 3495 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3496 | * marked as wc by the system, or the system is cache-coherent. |
| 3497 | */ |
| 3498 | if (obj->stolen) |
| 3499 | return false; |
| 3500 | |
| 3501 | /* If the GPU is snooping the contents of the CPU cache, |
| 3502 | * we do not need to manually clear the CPU cache lines. However, |
| 3503 | * the caches are only snooped when the render cache is |
| 3504 | * flushed/invalidated. As we always have to emit invalidations |
| 3505 | * and flushes when moving into and out of the RENDER domain, correct |
| 3506 | * snooping behaviour occurs naturally as the result of our domain |
| 3507 | * tracking. |
| 3508 | */ |
| 3509 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 3510 | return false; |
| 3511 | |
| 3512 | trace_i915_gem_object_clflush(obj); |
| 3513 | drm_clflush_sg(obj->pages); |
| 3514 | |
| 3515 | return true; |
| 3516 | } |
| 3517 | |
| 3518 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3519 | static void |
| 3520 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
| 3521 | { |
| 3522 | uint32_t old_write_domain; |
| 3523 | |
| 3524 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
| 3525 | return; |
| 3526 | |
| 3527 | /* No actual flushing is required for the GTT write domain. Writes |
| 3528 | * to it immediately go to main memory as far as we know, so there's |
| 3529 | * no chipset flush. It also doesn't land in render cache. |
| 3530 | * |
| 3531 | * However, we do have to enforce the order so that all writes through |
| 3532 | * the GTT land before any writes to the device, such as updates to |
| 3533 | * the GATT itself. |
| 3534 | */ |
| 3535 | wmb(); |
| 3536 | |
| 3537 | old_write_domain = obj->base.write_domain; |
| 3538 | obj->base.write_domain = 0; |
| 3539 | |
| 3540 | intel_fb_obj_flush(obj, false); |
| 3541 | |
| 3542 | trace_i915_gem_object_change_domain(obj, |
| 3543 | obj->base.read_domains, |
| 3544 | old_write_domain); |
| 3545 | } |
| 3546 | |
| 3547 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3548 | static void |
| 3549 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 3550 | bool force) |
| 3551 | { |
| 3552 | uint32_t old_write_domain; |
| 3553 | |
| 3554 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
| 3555 | return; |
| 3556 | |
| 3557 | if (i915_gem_clflush_object(obj, force)) |
| 3558 | i915_gem_chipset_flush(obj->base.dev); |
| 3559 | |
| 3560 | old_write_domain = obj->base.write_domain; |
| 3561 | obj->base.write_domain = 0; |
| 3562 | |
| 3563 | intel_fb_obj_flush(obj, false); |
| 3564 | |
| 3565 | trace_i915_gem_object_change_domain(obj, |
| 3566 | obj->base.read_domains, |
| 3567 | old_write_domain); |
| 3568 | } |
| 3569 | |
| 3570 | /** |
| 3571 | * Moves a single object to the GTT read, and possibly write domain. |
| 3572 | * |
| 3573 | * This function returns when the move is complete, including waiting on |
| 3574 | * flushes to occur. |
| 3575 | */ |
| 3576 | int |
| 3577 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
| 3578 | { |
| 3579 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3580 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
| 3581 | uint32_t old_write_domain, old_read_domains; |
| 3582 | int ret; |
| 3583 | |
| 3584 | /* Not valid to be called on unbound objects. */ |
| 3585 | if (vma == NULL) |
| 3586 | return -EINVAL; |
| 3587 | |
| 3588 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3589 | return 0; |
| 3590 | |
| 3591 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 3592 | if (ret) |
| 3593 | return ret; |
| 3594 | |
| 3595 | i915_gem_object_retire(obj); |
| 3596 | i915_gem_object_flush_cpu_write_domain(obj, false); |
| 3597 | |
| 3598 | /* Serialise direct access to this object with the barriers for |
| 3599 | * coherent writes from the GPU, by effectively invalidating the |
| 3600 | * GTT domain upon first access. |
| 3601 | */ |
| 3602 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3603 | mb(); |
| 3604 | |
| 3605 | old_write_domain = obj->base.write_domain; |
| 3606 | old_read_domains = obj->base.read_domains; |
| 3607 | |
| 3608 | /* It should now be out of any other write domains, and we can update |
| 3609 | * the domain values for our changes. |
| 3610 | */ |
| 3611 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3612 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
| 3613 | if (write) { |
| 3614 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3615 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3616 | obj->dirty = 1; |
| 3617 | } |
| 3618 | |
| 3619 | if (write) |
| 3620 | intel_fb_obj_invalidate(obj, NULL); |
| 3621 | |
| 3622 | trace_i915_gem_object_change_domain(obj, |
| 3623 | old_read_domains, |
| 3624 | old_write_domain); |
| 3625 | |
| 3626 | /* And bump the LRU for this access */ |
| 3627 | if (i915_gem_object_is_inactive(obj)) |
| 3628 | list_move_tail(&vma->mm_list, |
| 3629 | &dev_priv->gtt.base.inactive_list); |
| 3630 | |
| 3631 | return 0; |
| 3632 | } |
| 3633 | |
| 3634 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3635 | enum i915_cache_level cache_level) |
| 3636 | { |
| 3637 | struct drm_device *dev = obj->base.dev; |
| 3638 | struct i915_vma *vma, *next; |
| 3639 | int ret; |
| 3640 | |
| 3641 | if (obj->cache_level == cache_level) |
| 3642 | return 0; |
| 3643 | |
| 3644 | if (i915_gem_obj_is_pinned(obj)) { |
| 3645 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3646 | return -EBUSY; |
| 3647 | } |
| 3648 | |
| 3649 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
| 3650 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
| 3651 | ret = i915_vma_unbind(vma); |
| 3652 | if (ret) |
| 3653 | return ret; |
| 3654 | } |
| 3655 | } |
| 3656 | |
| 3657 | if (i915_gem_obj_bound_any(obj)) { |
| 3658 | ret = i915_gem_object_finish_gpu(obj); |
| 3659 | if (ret) |
| 3660 | return ret; |
| 3661 | |
| 3662 | i915_gem_object_finish_gtt(obj); |
| 3663 | |
| 3664 | /* Before SandyBridge, you could not use tiling or fence |
| 3665 | * registers with snooped memory, so relinquish any fences |
| 3666 | * currently pointing to our region in the aperture. |
| 3667 | */ |
| 3668 | if (INTEL_INFO(dev)->gen < 6) { |
| 3669 | ret = i915_gem_object_put_fence(obj); |
| 3670 | if (ret) |
| 3671 | return ret; |
| 3672 | } |
| 3673 | |
| 3674 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3675 | if (drm_mm_node_allocated(&vma->node)) |
| 3676 | vma->bind_vma(vma, cache_level, |
| 3677 | obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); |
| 3678 | } |
| 3679 | |
| 3680 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3681 | vma->node.color = cache_level; |
| 3682 | obj->cache_level = cache_level; |
| 3683 | |
| 3684 | if (cpu_write_needs_clflush(obj)) { |
| 3685 | u32 old_read_domains, old_write_domain; |
| 3686 | |
| 3687 | /* If we're coming from LLC cached, then we haven't |
| 3688 | * actually been tracking whether the data is in the |
| 3689 | * CPU cache or not, since we only allow one bit set |
| 3690 | * in obj->write_domain and have been skipping the clflushes. |
| 3691 | * Just set it to the CPU cache for now. |
| 3692 | */ |
| 3693 | i915_gem_object_retire(obj); |
| 3694 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 3695 | |
| 3696 | old_read_domains = obj->base.read_domains; |
| 3697 | old_write_domain = obj->base.write_domain; |
| 3698 | |
| 3699 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3700 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3701 | |
| 3702 | trace_i915_gem_object_change_domain(obj, |
| 3703 | old_read_domains, |
| 3704 | old_write_domain); |
| 3705 | } |
| 3706 | |
| 3707 | i915_gem_verify_gtt(dev); |
| 3708 | return 0; |
| 3709 | } |
| 3710 | |
| 3711 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3712 | struct drm_file *file) |
| 3713 | { |
| 3714 | struct drm_i915_gem_caching *args = data; |
| 3715 | struct drm_i915_gem_object *obj; |
| 3716 | int ret; |
| 3717 | |
| 3718 | ret = i915_mutex_lock_interruptible(dev); |
| 3719 | if (ret) |
| 3720 | return ret; |
| 3721 | |
| 3722 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3723 | if (&obj->base == NULL) { |
| 3724 | ret = -ENOENT; |
| 3725 | goto unlock; |
| 3726 | } |
| 3727 | |
| 3728 | switch (obj->cache_level) { |
| 3729 | case I915_CACHE_LLC: |
| 3730 | case I915_CACHE_L3_LLC: |
| 3731 | args->caching = I915_CACHING_CACHED; |
| 3732 | break; |
| 3733 | |
| 3734 | case I915_CACHE_WT: |
| 3735 | args->caching = I915_CACHING_DISPLAY; |
| 3736 | break; |
| 3737 | |
| 3738 | default: |
| 3739 | args->caching = I915_CACHING_NONE; |
| 3740 | break; |
| 3741 | } |
| 3742 | |
| 3743 | drm_gem_object_unreference(&obj->base); |
| 3744 | unlock: |
| 3745 | mutex_unlock(&dev->struct_mutex); |
| 3746 | return ret; |
| 3747 | } |
| 3748 | |
| 3749 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3750 | struct drm_file *file) |
| 3751 | { |
| 3752 | struct drm_i915_gem_caching *args = data; |
| 3753 | struct drm_i915_gem_object *obj; |
| 3754 | enum i915_cache_level level; |
| 3755 | int ret; |
| 3756 | |
| 3757 | switch (args->caching) { |
| 3758 | case I915_CACHING_NONE: |
| 3759 | level = I915_CACHE_NONE; |
| 3760 | break; |
| 3761 | case I915_CACHING_CACHED: |
| 3762 | level = I915_CACHE_LLC; |
| 3763 | break; |
| 3764 | case I915_CACHING_DISPLAY: |
| 3765 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3766 | break; |
| 3767 | default: |
| 3768 | return -EINVAL; |
| 3769 | } |
| 3770 | |
| 3771 | ret = i915_mutex_lock_interruptible(dev); |
| 3772 | if (ret) |
| 3773 | return ret; |
| 3774 | |
| 3775 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3776 | if (&obj->base == NULL) { |
| 3777 | ret = -ENOENT; |
| 3778 | goto unlock; |
| 3779 | } |
| 3780 | |
| 3781 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3782 | |
| 3783 | drm_gem_object_unreference(&obj->base); |
| 3784 | unlock: |
| 3785 | mutex_unlock(&dev->struct_mutex); |
| 3786 | return ret; |
| 3787 | } |
| 3788 | |
| 3789 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
| 3790 | { |
| 3791 | struct i915_vma *vma; |
| 3792 | |
| 3793 | vma = i915_gem_obj_to_ggtt(obj); |
| 3794 | if (!vma) |
| 3795 | return false; |
| 3796 | |
| 3797 | /* There are 3 sources that pin objects: |
| 3798 | * 1. The display engine (scanouts, sprites, cursors); |
| 3799 | * 2. Reservations for execbuffer; |
| 3800 | * 3. The user. |
| 3801 | * |
| 3802 | * We can ignore reservations as we hold the struct_mutex and |
| 3803 | * are only called outside of the reservation path. The user |
| 3804 | * can only increment pin_count once, and so if after |
| 3805 | * subtracting the potential reference by the user, any pin_count |
| 3806 | * remains, it must be due to another use by the display engine. |
| 3807 | */ |
| 3808 | return vma->pin_count - !!obj->user_pin_count; |
| 3809 | } |
| 3810 | |
| 3811 | /* |
| 3812 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3813 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3814 | * any flushes to be pipelined (for pageflips). |
| 3815 | */ |
| 3816 | int |
| 3817 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3818 | u32 alignment, |
| 3819 | struct intel_engine_cs *pipelined) |
| 3820 | { |
| 3821 | u32 old_read_domains, old_write_domain; |
| 3822 | bool was_pin_display; |
| 3823 | int ret; |
| 3824 | |
| 3825 | if (pipelined != obj->ring) { |
| 3826 | ret = i915_gem_object_sync(obj, pipelined); |
| 3827 | if (ret) |
| 3828 | return ret; |
| 3829 | } |
| 3830 | |
| 3831 | /* Mark the pin_display early so that we account for the |
| 3832 | * display coherency whilst setting up the cache domains. |
| 3833 | */ |
| 3834 | was_pin_display = obj->pin_display; |
| 3835 | obj->pin_display = true; |
| 3836 | |
| 3837 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3838 | * a result, we make sure that the pinning that is about to occur is |
| 3839 | * done with uncached PTEs. This is lowest common denominator for all |
| 3840 | * chipsets. |
| 3841 | * |
| 3842 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3843 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3844 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3845 | */ |
| 3846 | ret = i915_gem_object_set_cache_level(obj, |
| 3847 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
| 3848 | if (ret) |
| 3849 | goto err_unpin_display; |
| 3850 | |
| 3851 | /* As the user may map the buffer once pinned in the display plane |
| 3852 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3853 | * always use map_and_fenceable for all scanout buffers. |
| 3854 | */ |
| 3855 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
| 3856 | if (ret) |
| 3857 | goto err_unpin_display; |
| 3858 | |
| 3859 | i915_gem_object_flush_cpu_write_domain(obj, true); |
| 3860 | |
| 3861 | old_write_domain = obj->base.write_domain; |
| 3862 | old_read_domains = obj->base.read_domains; |
| 3863 | |
| 3864 | /* It should now be out of any other write domains, and we can update |
| 3865 | * the domain values for our changes. |
| 3866 | */ |
| 3867 | obj->base.write_domain = 0; |
| 3868 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
| 3869 | |
| 3870 | trace_i915_gem_object_change_domain(obj, |
| 3871 | old_read_domains, |
| 3872 | old_write_domain); |
| 3873 | |
| 3874 | return 0; |
| 3875 | |
| 3876 | err_unpin_display: |
| 3877 | WARN_ON(was_pin_display != is_pin_display(obj)); |
| 3878 | obj->pin_display = was_pin_display; |
| 3879 | return ret; |
| 3880 | } |
| 3881 | |
| 3882 | void |
| 3883 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
| 3884 | { |
| 3885 | i915_gem_object_ggtt_unpin(obj); |
| 3886 | obj->pin_display = is_pin_display(obj); |
| 3887 | } |
| 3888 | |
| 3889 | int |
| 3890 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
| 3891 | { |
| 3892 | int ret; |
| 3893 | |
| 3894 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
| 3895 | return 0; |
| 3896 | |
| 3897 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3898 | if (ret) |
| 3899 | return ret; |
| 3900 | |
| 3901 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3902 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
| 3903 | return 0; |
| 3904 | } |
| 3905 | |
| 3906 | /** |
| 3907 | * Moves a single object to the CPU read, and possibly write domain. |
| 3908 | * |
| 3909 | * This function returns when the move is complete, including waiting on |
| 3910 | * flushes to occur. |
| 3911 | */ |
| 3912 | int |
| 3913 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
| 3914 | { |
| 3915 | uint32_t old_write_domain, old_read_domains; |
| 3916 | int ret; |
| 3917 | |
| 3918 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3919 | return 0; |
| 3920 | |
| 3921 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 3922 | if (ret) |
| 3923 | return ret; |
| 3924 | |
| 3925 | i915_gem_object_retire(obj); |
| 3926 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3927 | |
| 3928 | old_write_domain = obj->base.write_domain; |
| 3929 | old_read_domains = obj->base.read_domains; |
| 3930 | |
| 3931 | /* Flush the CPU cache if it's still invalid. */ |
| 3932 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 3933 | i915_gem_clflush_object(obj, false); |
| 3934 | |
| 3935 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
| 3936 | } |
| 3937 | |
| 3938 | /* It should now be out of any other write domains, and we can update |
| 3939 | * the domain values for our changes. |
| 3940 | */ |
| 3941 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3942 | |
| 3943 | /* If we're writing through the CPU, then the GPU read domains will |
| 3944 | * need to be invalidated at next use. |
| 3945 | */ |
| 3946 | if (write) { |
| 3947 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3948 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3949 | } |
| 3950 | |
| 3951 | if (write) |
| 3952 | intel_fb_obj_invalidate(obj, NULL); |
| 3953 | |
| 3954 | trace_i915_gem_object_change_domain(obj, |
| 3955 | old_read_domains, |
| 3956 | old_write_domain); |
| 3957 | |
| 3958 | return 0; |
| 3959 | } |
| 3960 | |
| 3961 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3962 | * emitted over 20 msec ago. |
| 3963 | * |
| 3964 | * Note that if we were to use the current jiffies each time around the loop, |
| 3965 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3966 | * render a frame was over 20ms. |
| 3967 | * |
| 3968 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3969 | * relatively low latency when blocking on a particular request to finish. |
| 3970 | */ |
| 3971 | static int |
| 3972 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
| 3973 | { |
| 3974 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3975 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 3976 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
| 3977 | struct drm_i915_gem_request *request; |
| 3978 | struct intel_engine_cs *ring = NULL; |
| 3979 | unsigned reset_counter; |
| 3980 | u32 seqno = 0; |
| 3981 | int ret; |
| 3982 | |
| 3983 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 3984 | if (ret) |
| 3985 | return ret; |
| 3986 | |
| 3987 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 3988 | if (ret) |
| 3989 | return ret; |
| 3990 | |
| 3991 | spin_lock(&file_priv->mm.lock); |
| 3992 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
| 3993 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3994 | break; |
| 3995 | |
| 3996 | ring = request->ring; |
| 3997 | seqno = request->seqno; |
| 3998 | } |
| 3999 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 4000 | spin_unlock(&file_priv->mm.lock); |
| 4001 | |
| 4002 | if (seqno == 0) |
| 4003 | return 0; |
| 4004 | |
| 4005 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
| 4006 | if (ret == 0) |
| 4007 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
| 4008 | |
| 4009 | return ret; |
| 4010 | } |
| 4011 | |
| 4012 | static bool |
| 4013 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4014 | { |
| 4015 | struct drm_i915_gem_object *obj = vma->obj; |
| 4016 | |
| 4017 | if (alignment && |
| 4018 | vma->node.start & (alignment - 1)) |
| 4019 | return true; |
| 4020 | |
| 4021 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4022 | return true; |
| 4023 | |
| 4024 | if (flags & PIN_OFFSET_BIAS && |
| 4025 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4026 | return true; |
| 4027 | |
| 4028 | return false; |
| 4029 | } |
| 4030 | |
| 4031 | int |
| 4032 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4033 | struct i915_address_space *vm, |
| 4034 | uint32_t alignment, |
| 4035 | uint64_t flags) |
| 4036 | { |
| 4037 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4038 | struct i915_vma *vma; |
| 4039 | int ret; |
| 4040 | |
| 4041 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4042 | return -ENODEV; |
| 4043 | |
| 4044 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
| 4045 | return -EINVAL; |
| 4046 | |
| 4047 | vma = i915_gem_obj_to_vma(obj, vm); |
| 4048 | if (vma) { |
| 4049 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4050 | return -EBUSY; |
| 4051 | |
| 4052 | if (i915_vma_misplaced(vma, alignment, flags)) { |
| 4053 | WARN(vma->pin_count, |
| 4054 | "bo is already pinned with incorrect alignment:" |
| 4055 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
| 4056 | " obj->map_and_fenceable=%d\n", |
| 4057 | i915_gem_obj_offset(obj, vm), alignment, |
| 4058 | !!(flags & PIN_MAPPABLE), |
| 4059 | obj->map_and_fenceable); |
| 4060 | ret = i915_vma_unbind(vma); |
| 4061 | if (ret) |
| 4062 | return ret; |
| 4063 | |
| 4064 | vma = NULL; |
| 4065 | } |
| 4066 | } |
| 4067 | |
| 4068 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
| 4069 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
| 4070 | if (IS_ERR(vma)) |
| 4071 | return PTR_ERR(vma); |
| 4072 | } |
| 4073 | |
| 4074 | if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) |
| 4075 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
| 4076 | |
| 4077 | vma->pin_count++; |
| 4078 | if (flags & PIN_MAPPABLE) |
| 4079 | obj->pin_mappable |= true; |
| 4080 | |
| 4081 | return 0; |
| 4082 | } |
| 4083 | |
| 4084 | void |
| 4085 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
| 4086 | { |
| 4087 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
| 4088 | |
| 4089 | BUG_ON(!vma); |
| 4090 | BUG_ON(vma->pin_count == 0); |
| 4091 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
| 4092 | |
| 4093 | if (--vma->pin_count == 0) |
| 4094 | obj->pin_mappable = false; |
| 4095 | } |
| 4096 | |
| 4097 | bool |
| 4098 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 4099 | { |
| 4100 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4101 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4102 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
| 4103 | |
| 4104 | WARN_ON(!ggtt_vma || |
| 4105 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
| 4106 | ggtt_vma->pin_count); |
| 4107 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
| 4108 | return true; |
| 4109 | } else |
| 4110 | return false; |
| 4111 | } |
| 4112 | |
| 4113 | void |
| 4114 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 4115 | { |
| 4116 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4117 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4118 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
| 4119 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 4120 | } |
| 4121 | } |
| 4122 | |
| 4123 | int |
| 4124 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4125 | struct drm_file *file) |
| 4126 | { |
| 4127 | struct drm_i915_gem_pin *args = data; |
| 4128 | struct drm_i915_gem_object *obj; |
| 4129 | int ret; |
| 4130 | |
| 4131 | if (INTEL_INFO(dev)->gen >= 6) |
| 4132 | return -ENODEV; |
| 4133 | |
| 4134 | ret = i915_mutex_lock_interruptible(dev); |
| 4135 | if (ret) |
| 4136 | return ret; |
| 4137 | |
| 4138 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4139 | if (&obj->base == NULL) { |
| 4140 | ret = -ENOENT; |
| 4141 | goto unlock; |
| 4142 | } |
| 4143 | |
| 4144 | if (obj->madv != I915_MADV_WILLNEED) { |
| 4145 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
| 4146 | ret = -EFAULT; |
| 4147 | goto out; |
| 4148 | } |
| 4149 | |
| 4150 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
| 4151 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4152 | args->handle); |
| 4153 | ret = -EINVAL; |
| 4154 | goto out; |
| 4155 | } |
| 4156 | |
| 4157 | if (obj->user_pin_count == ULONG_MAX) { |
| 4158 | ret = -EBUSY; |
| 4159 | goto out; |
| 4160 | } |
| 4161 | |
| 4162 | if (obj->user_pin_count == 0) { |
| 4163 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE); |
| 4164 | if (ret) |
| 4165 | goto out; |
| 4166 | } |
| 4167 | |
| 4168 | obj->user_pin_count++; |
| 4169 | obj->pin_filp = file; |
| 4170 | |
| 4171 | args->offset = i915_gem_obj_ggtt_offset(obj); |
| 4172 | out: |
| 4173 | drm_gem_object_unreference(&obj->base); |
| 4174 | unlock: |
| 4175 | mutex_unlock(&dev->struct_mutex); |
| 4176 | return ret; |
| 4177 | } |
| 4178 | |
| 4179 | int |
| 4180 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4181 | struct drm_file *file) |
| 4182 | { |
| 4183 | struct drm_i915_gem_pin *args = data; |
| 4184 | struct drm_i915_gem_object *obj; |
| 4185 | int ret; |
| 4186 | |
| 4187 | ret = i915_mutex_lock_interruptible(dev); |
| 4188 | if (ret) |
| 4189 | return ret; |
| 4190 | |
| 4191 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4192 | if (&obj->base == NULL) { |
| 4193 | ret = -ENOENT; |
| 4194 | goto unlock; |
| 4195 | } |
| 4196 | |
| 4197 | if (obj->pin_filp != file) { |
| 4198 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4199 | args->handle); |
| 4200 | ret = -EINVAL; |
| 4201 | goto out; |
| 4202 | } |
| 4203 | obj->user_pin_count--; |
| 4204 | if (obj->user_pin_count == 0) { |
| 4205 | obj->pin_filp = NULL; |
| 4206 | i915_gem_object_ggtt_unpin(obj); |
| 4207 | } |
| 4208 | |
| 4209 | out: |
| 4210 | drm_gem_object_unreference(&obj->base); |
| 4211 | unlock: |
| 4212 | mutex_unlock(&dev->struct_mutex); |
| 4213 | return ret; |
| 4214 | } |
| 4215 | |
| 4216 | int |
| 4217 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4218 | struct drm_file *file) |
| 4219 | { |
| 4220 | struct drm_i915_gem_busy *args = data; |
| 4221 | struct drm_i915_gem_object *obj; |
| 4222 | int ret; |
| 4223 | |
| 4224 | ret = i915_mutex_lock_interruptible(dev); |
| 4225 | if (ret) |
| 4226 | return ret; |
| 4227 | |
| 4228 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4229 | if (&obj->base == NULL) { |
| 4230 | ret = -ENOENT; |
| 4231 | goto unlock; |
| 4232 | } |
| 4233 | |
| 4234 | /* Count all active objects as busy, even if they are currently not used |
| 4235 | * by the gpu. Users of this interface expect objects to eventually |
| 4236 | * become non-busy without any further actions, therefore emit any |
| 4237 | * necessary flushes here. |
| 4238 | */ |
| 4239 | ret = i915_gem_object_flush_active(obj); |
| 4240 | |
| 4241 | args->busy = obj->active; |
| 4242 | if (obj->ring) { |
| 4243 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 4244 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 4245 | } |
| 4246 | |
| 4247 | drm_gem_object_unreference(&obj->base); |
| 4248 | unlock: |
| 4249 | mutex_unlock(&dev->struct_mutex); |
| 4250 | return ret; |
| 4251 | } |
| 4252 | |
| 4253 | int |
| 4254 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4255 | struct drm_file *file_priv) |
| 4256 | { |
| 4257 | return i915_gem_ring_throttle(dev, file_priv); |
| 4258 | } |
| 4259 | |
| 4260 | int |
| 4261 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4262 | struct drm_file *file_priv) |
| 4263 | { |
| 4264 | struct drm_i915_gem_madvise *args = data; |
| 4265 | struct drm_i915_gem_object *obj; |
| 4266 | int ret; |
| 4267 | |
| 4268 | switch (args->madv) { |
| 4269 | case I915_MADV_DONTNEED: |
| 4270 | case I915_MADV_WILLNEED: |
| 4271 | break; |
| 4272 | default: |
| 4273 | return -EINVAL; |
| 4274 | } |
| 4275 | |
| 4276 | ret = i915_mutex_lock_interruptible(dev); |
| 4277 | if (ret) |
| 4278 | return ret; |
| 4279 | |
| 4280 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
| 4281 | if (&obj->base == NULL) { |
| 4282 | ret = -ENOENT; |
| 4283 | goto unlock; |
| 4284 | } |
| 4285 | |
| 4286 | if (i915_gem_obj_is_pinned(obj)) { |
| 4287 | ret = -EINVAL; |
| 4288 | goto out; |
| 4289 | } |
| 4290 | |
| 4291 | if (obj->madv != __I915_MADV_PURGED) |
| 4292 | obj->madv = args->madv; |
| 4293 | |
| 4294 | /* if the object is no longer attached, discard its backing storage */ |
| 4295 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
| 4296 | i915_gem_object_truncate(obj); |
| 4297 | |
| 4298 | args->retained = obj->madv != __I915_MADV_PURGED; |
| 4299 | |
| 4300 | out: |
| 4301 | drm_gem_object_unreference(&obj->base); |
| 4302 | unlock: |
| 4303 | mutex_unlock(&dev->struct_mutex); |
| 4304 | return ret; |
| 4305 | } |
| 4306 | |
| 4307 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4308 | const struct drm_i915_gem_object_ops *ops) |
| 4309 | { |
| 4310 | INIT_LIST_HEAD(&obj->global_list); |
| 4311 | INIT_LIST_HEAD(&obj->ring_list); |
| 4312 | INIT_LIST_HEAD(&obj->obj_exec_link); |
| 4313 | INIT_LIST_HEAD(&obj->vma_list); |
| 4314 | |
| 4315 | obj->ops = ops; |
| 4316 | |
| 4317 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4318 | obj->madv = I915_MADV_WILLNEED; |
| 4319 | |
| 4320 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4321 | } |
| 4322 | |
| 4323 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4324 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4325 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4326 | }; |
| 4327 | |
| 4328 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4329 | size_t size) |
| 4330 | { |
| 4331 | struct drm_i915_gem_object *obj; |
| 4332 | struct address_space *mapping; |
| 4333 | gfp_t mask; |
| 4334 | |
| 4335 | obj = i915_gem_object_alloc(dev); |
| 4336 | if (obj == NULL) |
| 4337 | return NULL; |
| 4338 | |
| 4339 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4340 | i915_gem_object_free(obj); |
| 4341 | return NULL; |
| 4342 | } |
| 4343 | |
| 4344 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4345 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4346 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4347 | mask &= ~__GFP_HIGHMEM; |
| 4348 | mask |= __GFP_DMA32; |
| 4349 | } |
| 4350 | |
| 4351 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 4352 | mapping_set_gfp_mask(mapping, mask); |
| 4353 | |
| 4354 | i915_gem_object_init(obj, &i915_gem_object_ops); |
| 4355 | |
| 4356 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4357 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4358 | |
| 4359 | if (HAS_LLC(dev)) { |
| 4360 | /* On some devices, we can have the GPU use the LLC (the CPU |
| 4361 | * cache) for about a 10% performance improvement |
| 4362 | * compared to uncached. Graphics requests other than |
| 4363 | * display scanout are coherent with the CPU in |
| 4364 | * accessing this cache. This means in this mode we |
| 4365 | * don't need to clflush on the CPU side, and on the |
| 4366 | * GPU side we only need to flush internal caches to |
| 4367 | * get data visible to the CPU. |
| 4368 | * |
| 4369 | * However, we maintain the display planes as UC, and so |
| 4370 | * need to rebind when first used as such. |
| 4371 | */ |
| 4372 | obj->cache_level = I915_CACHE_LLC; |
| 4373 | } else |
| 4374 | obj->cache_level = I915_CACHE_NONE; |
| 4375 | |
| 4376 | trace_i915_gem_object_create(obj); |
| 4377 | |
| 4378 | return obj; |
| 4379 | } |
| 4380 | |
| 4381 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4382 | { |
| 4383 | /* If we are the last user of the backing storage (be it shmemfs |
| 4384 | * pages or stolen etc), we know that the pages are going to be |
| 4385 | * immediately released. In this case, we can then skip copying |
| 4386 | * back the contents from the GPU. |
| 4387 | */ |
| 4388 | |
| 4389 | if (obj->madv != I915_MADV_WILLNEED) |
| 4390 | return false; |
| 4391 | |
| 4392 | if (obj->base.filp == NULL) |
| 4393 | return true; |
| 4394 | |
| 4395 | /* At first glance, this looks racy, but then again so would be |
| 4396 | * userspace racing mmap against close. However, the first external |
| 4397 | * reference to the filp can only be obtained through the |
| 4398 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4399 | * acquiring such a reference whilst we are in the middle of |
| 4400 | * freeing the object. |
| 4401 | */ |
| 4402 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4403 | } |
| 4404 | |
| 4405 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
| 4406 | { |
| 4407 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 4408 | struct drm_device *dev = obj->base.dev; |
| 4409 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4410 | struct i915_vma *vma, *next; |
| 4411 | |
| 4412 | intel_runtime_pm_get(dev_priv); |
| 4413 | |
| 4414 | trace_i915_gem_object_destroy(obj); |
| 4415 | |
| 4416 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
| 4417 | int ret; |
| 4418 | |
| 4419 | vma->pin_count = 0; |
| 4420 | ret = i915_vma_unbind(vma); |
| 4421 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4422 | bool was_interruptible; |
| 4423 | |
| 4424 | was_interruptible = dev_priv->mm.interruptible; |
| 4425 | dev_priv->mm.interruptible = false; |
| 4426 | |
| 4427 | WARN_ON(i915_vma_unbind(vma)); |
| 4428 | |
| 4429 | dev_priv->mm.interruptible = was_interruptible; |
| 4430 | } |
| 4431 | } |
| 4432 | |
| 4433 | i915_gem_object_detach_phys(obj); |
| 4434 | |
| 4435 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4436 | * before progressing. */ |
| 4437 | if (obj->stolen) |
| 4438 | i915_gem_object_unpin_pages(obj); |
| 4439 | |
| 4440 | WARN_ON(obj->frontbuffer_bits); |
| 4441 | |
| 4442 | if (WARN_ON(obj->pages_pin_count)) |
| 4443 | obj->pages_pin_count = 0; |
| 4444 | if (discard_backing_storage(obj)) |
| 4445 | obj->madv = I915_MADV_DONTNEED; |
| 4446 | i915_gem_object_put_pages(obj); |
| 4447 | i915_gem_object_free_mmap_offset(obj); |
| 4448 | |
| 4449 | BUG_ON(obj->pages); |
| 4450 | |
| 4451 | if (obj->base.import_attach) |
| 4452 | drm_prime_gem_destroy(&obj->base, NULL); |
| 4453 | |
| 4454 | if (obj->ops->release) |
| 4455 | obj->ops->release(obj); |
| 4456 | |
| 4457 | drm_gem_object_release(&obj->base); |
| 4458 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
| 4459 | |
| 4460 | kfree(obj->bit_17); |
| 4461 | i915_gem_object_free(obj); |
| 4462 | |
| 4463 | intel_runtime_pm_put(dev_priv); |
| 4464 | } |
| 4465 | |
| 4466 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 4467 | struct i915_address_space *vm) |
| 4468 | { |
| 4469 | struct i915_vma *vma; |
| 4470 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4471 | if (vma->vm == vm) |
| 4472 | return vma; |
| 4473 | |
| 4474 | return NULL; |
| 4475 | } |
| 4476 | |
| 4477 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4478 | { |
| 4479 | WARN_ON(vma->node.allocated); |
| 4480 | |
| 4481 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4482 | if (!list_empty(&vma->exec_list)) |
| 4483 | return; |
| 4484 | |
| 4485 | list_del(&vma->vma_link); |
| 4486 | |
| 4487 | kfree(vma); |
| 4488 | } |
| 4489 | |
| 4490 | static void |
| 4491 | i915_gem_stop_ringbuffers(struct drm_device *dev) |
| 4492 | { |
| 4493 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4494 | struct intel_engine_cs *ring; |
| 4495 | int i; |
| 4496 | |
| 4497 | for_each_ring(ring, dev_priv, i) |
| 4498 | dev_priv->gt.stop_ring(ring); |
| 4499 | } |
| 4500 | |
| 4501 | int |
| 4502 | i915_gem_suspend(struct drm_device *dev) |
| 4503 | { |
| 4504 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4505 | int ret = 0; |
| 4506 | |
| 4507 | mutex_lock(&dev->struct_mutex); |
| 4508 | if (dev_priv->ums.mm_suspended) |
| 4509 | goto err; |
| 4510 | |
| 4511 | ret = i915_gpu_idle(dev); |
| 4512 | if (ret) |
| 4513 | goto err; |
| 4514 | |
| 4515 | i915_gem_retire_requests(dev); |
| 4516 | |
| 4517 | /* Under UMS, be paranoid and evict. */ |
| 4518 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4519 | i915_gem_evict_everything(dev); |
| 4520 | |
| 4521 | i915_kernel_lost_context(dev); |
| 4522 | i915_gem_stop_ringbuffers(dev); |
| 4523 | |
| 4524 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4525 | * We need to replace this with a semaphore, or something. |
| 4526 | * And not confound ums.mm_suspended! |
| 4527 | */ |
| 4528 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, |
| 4529 | DRIVER_MODESET); |
| 4530 | mutex_unlock(&dev->struct_mutex); |
| 4531 | |
| 4532 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
| 4533 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4534 | flush_delayed_work(&dev_priv->mm.idle_work); |
| 4535 | |
| 4536 | return 0; |
| 4537 | |
| 4538 | err: |
| 4539 | mutex_unlock(&dev->struct_mutex); |
| 4540 | return ret; |
| 4541 | } |
| 4542 | |
| 4543 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
| 4544 | { |
| 4545 | struct drm_device *dev = ring->dev; |
| 4546 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4547 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4548 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
| 4549 | int i, ret; |
| 4550 | |
| 4551 | if (!HAS_L3_DPF(dev) || !remap_info) |
| 4552 | return 0; |
| 4553 | |
| 4554 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
| 4555 | if (ret) |
| 4556 | return ret; |
| 4557 | |
| 4558 | /* |
| 4559 | * Note: We do not worry about the concurrent register cacheline hang |
| 4560 | * here because no other code should access these registers other than |
| 4561 | * at initialization time. |
| 4562 | */ |
| 4563 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 4564 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 4565 | intel_ring_emit(ring, reg_base + i); |
| 4566 | intel_ring_emit(ring, remap_info[i/4]); |
| 4567 | } |
| 4568 | |
| 4569 | intel_ring_advance(ring); |
| 4570 | |
| 4571 | return ret; |
| 4572 | } |
| 4573 | |
| 4574 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4575 | { |
| 4576 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4577 | |
| 4578 | if (INTEL_INFO(dev)->gen < 5 || |
| 4579 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4580 | return; |
| 4581 | |
| 4582 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4583 | DISP_TILE_SURFACE_SWIZZLING); |
| 4584 | |
| 4585 | if (IS_GEN5(dev)) |
| 4586 | return; |
| 4587 | |
| 4588 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4589 | if (IS_GEN6(dev)) |
| 4590 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
| 4591 | else if (IS_GEN7(dev)) |
| 4592 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
| 4593 | else if (IS_GEN8(dev)) |
| 4594 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
| 4595 | else |
| 4596 | BUG(); |
| 4597 | } |
| 4598 | |
| 4599 | static bool |
| 4600 | intel_enable_blt(struct drm_device *dev) |
| 4601 | { |
| 4602 | if (!HAS_BLT(dev)) |
| 4603 | return false; |
| 4604 | |
| 4605 | /* The blitter was dysfunctional on early prototypes */ |
| 4606 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4607 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4608 | " graphics performance will be degraded.\n"); |
| 4609 | return false; |
| 4610 | } |
| 4611 | |
| 4612 | return true; |
| 4613 | } |
| 4614 | |
| 4615 | int i915_gem_init_rings(struct drm_device *dev) |
| 4616 | { |
| 4617 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4618 | int ret; |
| 4619 | |
| 4620 | ret = intel_init_render_ring_buffer(dev); |
| 4621 | if (ret) |
| 4622 | return ret; |
| 4623 | |
| 4624 | if (HAS_BSD(dev)) { |
| 4625 | ret = intel_init_bsd_ring_buffer(dev); |
| 4626 | if (ret) |
| 4627 | goto cleanup_render_ring; |
| 4628 | } |
| 4629 | |
| 4630 | if (intel_enable_blt(dev)) { |
| 4631 | ret = intel_init_blt_ring_buffer(dev); |
| 4632 | if (ret) |
| 4633 | goto cleanup_bsd_ring; |
| 4634 | } |
| 4635 | |
| 4636 | if (HAS_VEBOX(dev)) { |
| 4637 | ret = intel_init_vebox_ring_buffer(dev); |
| 4638 | if (ret) |
| 4639 | goto cleanup_blt_ring; |
| 4640 | } |
| 4641 | |
| 4642 | if (HAS_BSD2(dev)) { |
| 4643 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4644 | if (ret) |
| 4645 | goto cleanup_vebox_ring; |
| 4646 | } |
| 4647 | |
| 4648 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4649 | if (ret) |
| 4650 | goto cleanup_bsd2_ring; |
| 4651 | |
| 4652 | return 0; |
| 4653 | |
| 4654 | cleanup_bsd2_ring: |
| 4655 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
| 4656 | cleanup_vebox_ring: |
| 4657 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
| 4658 | cleanup_blt_ring: |
| 4659 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 4660 | cleanup_bsd_ring: |
| 4661 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 4662 | cleanup_render_ring: |
| 4663 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 4664 | |
| 4665 | return ret; |
| 4666 | } |
| 4667 | |
| 4668 | int |
| 4669 | i915_gem_init_hw(struct drm_device *dev) |
| 4670 | { |
| 4671 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4672 | int ret, i; |
| 4673 | |
| 4674 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4675 | return -EIO; |
| 4676 | |
| 4677 | if (dev_priv->ellc_size) |
| 4678 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
| 4679 | |
| 4680 | if (IS_HASWELL(dev)) |
| 4681 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4682 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
| 4683 | |
| 4684 | if (HAS_PCH_NOP(dev)) { |
| 4685 | if (IS_IVYBRIDGE(dev)) { |
| 4686 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4687 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4688 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4689 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4690 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4691 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4692 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4693 | } |
| 4694 | } |
| 4695 | |
| 4696 | i915_gem_init_swizzling(dev); |
| 4697 | |
| 4698 | ret = dev_priv->gt.init_rings(dev); |
| 4699 | if (ret) |
| 4700 | return ret; |
| 4701 | |
| 4702 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
| 4703 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); |
| 4704 | |
| 4705 | /* |
| 4706 | * XXX: Contexts should only be initialized once. Doing a switch to the |
| 4707 | * default context switch however is something we'd like to do after |
| 4708 | * reset or thaw (the latter may not actually be necessary for HW, but |
| 4709 | * goes with our code better). Context switching requires rings (for |
| 4710 | * the do_switch), but before enabling PPGTT. So don't move this. |
| 4711 | */ |
| 4712 | ret = i915_gem_context_enable(dev_priv); |
| 4713 | if (ret && ret != -EIO) { |
| 4714 | DRM_ERROR("Context enable failed %d\n", ret); |
| 4715 | i915_gem_cleanup_ringbuffer(dev); |
| 4716 | } |
| 4717 | |
| 4718 | return ret; |
| 4719 | } |
| 4720 | |
| 4721 | int i915_gem_init(struct drm_device *dev) |
| 4722 | { |
| 4723 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4724 | int ret; |
| 4725 | |
| 4726 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
| 4727 | i915.enable_execlists); |
| 4728 | |
| 4729 | mutex_lock(&dev->struct_mutex); |
| 4730 | |
| 4731 | if (IS_VALLEYVIEW(dev)) { |
| 4732 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
| 4733 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
| 4734 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
| 4735 | VLV_GTLC_ALLOWWAKEACK), 10)) |
| 4736 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4737 | } |
| 4738 | |
| 4739 | if (!i915.enable_execlists) { |
| 4740 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; |
| 4741 | dev_priv->gt.init_rings = i915_gem_init_rings; |
| 4742 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
| 4743 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
| 4744 | } |
| 4745 | |
| 4746 | i915_gem_init_userptr(dev); |
| 4747 | i915_gem_init_global_gtt(dev); |
| 4748 | |
| 4749 | ret = i915_gem_context_init(dev); |
| 4750 | if (ret) { |
| 4751 | mutex_unlock(&dev->struct_mutex); |
| 4752 | return ret; |
| 4753 | } |
| 4754 | |
| 4755 | ret = i915_gem_init_hw(dev); |
| 4756 | if (ret == -EIO) { |
| 4757 | /* Allow ring initialisation to fail by marking the GPU as |
| 4758 | * wedged. But we only want to do this where the GPU is angry, |
| 4759 | * for all other failure, such as an allocation failure, bail. |
| 4760 | */ |
| 4761 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
| 4762 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 4763 | ret = 0; |
| 4764 | } |
| 4765 | mutex_unlock(&dev->struct_mutex); |
| 4766 | |
| 4767 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4768 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4769 | dev_priv->dri1.allow_batchbuffer = 1; |
| 4770 | return ret; |
| 4771 | } |
| 4772 | |
| 4773 | void |
| 4774 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4775 | { |
| 4776 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4777 | struct intel_engine_cs *ring; |
| 4778 | int i; |
| 4779 | |
| 4780 | for_each_ring(ring, dev_priv, i) |
| 4781 | dev_priv->gt.cleanup_ring(ring); |
| 4782 | } |
| 4783 | |
| 4784 | int |
| 4785 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4786 | struct drm_file *file_priv) |
| 4787 | { |
| 4788 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4789 | int ret; |
| 4790 | |
| 4791 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4792 | return 0; |
| 4793 | |
| 4794 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
| 4795 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
| 4796 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
| 4797 | } |
| 4798 | |
| 4799 | mutex_lock(&dev->struct_mutex); |
| 4800 | dev_priv->ums.mm_suspended = 0; |
| 4801 | |
| 4802 | ret = i915_gem_init_hw(dev); |
| 4803 | if (ret != 0) { |
| 4804 | mutex_unlock(&dev->struct_mutex); |
| 4805 | return ret; |
| 4806 | } |
| 4807 | |
| 4808 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
| 4809 | |
| 4810 | ret = drm_irq_install(dev, dev->pdev->irq); |
| 4811 | if (ret) |
| 4812 | goto cleanup_ringbuffer; |
| 4813 | mutex_unlock(&dev->struct_mutex); |
| 4814 | |
| 4815 | return 0; |
| 4816 | |
| 4817 | cleanup_ringbuffer: |
| 4818 | i915_gem_cleanup_ringbuffer(dev); |
| 4819 | dev_priv->ums.mm_suspended = 1; |
| 4820 | mutex_unlock(&dev->struct_mutex); |
| 4821 | |
| 4822 | return ret; |
| 4823 | } |
| 4824 | |
| 4825 | int |
| 4826 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4827 | struct drm_file *file_priv) |
| 4828 | { |
| 4829 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4830 | return 0; |
| 4831 | |
| 4832 | mutex_lock(&dev->struct_mutex); |
| 4833 | drm_irq_uninstall(dev); |
| 4834 | mutex_unlock(&dev->struct_mutex); |
| 4835 | |
| 4836 | return i915_gem_suspend(dev); |
| 4837 | } |
| 4838 | |
| 4839 | void |
| 4840 | i915_gem_lastclose(struct drm_device *dev) |
| 4841 | { |
| 4842 | int ret; |
| 4843 | |
| 4844 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4845 | return; |
| 4846 | |
| 4847 | ret = i915_gem_suspend(dev); |
| 4848 | if (ret) |
| 4849 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
| 4850 | } |
| 4851 | |
| 4852 | static void |
| 4853 | init_ring_lists(struct intel_engine_cs *ring) |
| 4854 | { |
| 4855 | INIT_LIST_HEAD(&ring->active_list); |
| 4856 | INIT_LIST_HEAD(&ring->request_list); |
| 4857 | } |
| 4858 | |
| 4859 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 4860 | struct i915_address_space *vm) |
| 4861 | { |
| 4862 | if (!i915_is_ggtt(vm)) |
| 4863 | drm_mm_init(&vm->mm, vm->start, vm->total); |
| 4864 | vm->dev = dev_priv->dev; |
| 4865 | INIT_LIST_HEAD(&vm->active_list); |
| 4866 | INIT_LIST_HEAD(&vm->inactive_list); |
| 4867 | INIT_LIST_HEAD(&vm->global_link); |
| 4868 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
| 4869 | } |
| 4870 | |
| 4871 | void |
| 4872 | i915_gem_load(struct drm_device *dev) |
| 4873 | { |
| 4874 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4875 | int i; |
| 4876 | |
| 4877 | dev_priv->slab = |
| 4878 | kmem_cache_create("i915_gem_object", |
| 4879 | sizeof(struct drm_i915_gem_object), 0, |
| 4880 | SLAB_HWCACHE_ALIGN, |
| 4881 | NULL); |
| 4882 | |
| 4883 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 4884 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 4885 | |
| 4886 | INIT_LIST_HEAD(&dev_priv->context_list); |
| 4887 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4888 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
| 4889 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 4890 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4891 | init_ring_lists(&dev_priv->ring[i]); |
| 4892 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
| 4893 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
| 4894 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4895 | i915_gem_retire_work_handler); |
| 4896 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 4897 | i915_gem_idle_work_handler); |
| 4898 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
| 4899 | |
| 4900 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4901 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
| 4902 | I915_WRITE(MI_ARB_STATE, |
| 4903 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
| 4904 | } |
| 4905 | |
| 4906 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4907 | |
| 4908 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
| 4909 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4910 | dev_priv->fence_reg_start = 3; |
| 4911 | |
| 4912 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 4913 | dev_priv->num_fence_regs = 32; |
| 4914 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4915 | dev_priv->num_fence_regs = 16; |
| 4916 | else |
| 4917 | dev_priv->num_fence_regs = 8; |
| 4918 | |
| 4919 | /* Initialize fence registers to zero */ |
| 4920 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 4921 | i915_gem_restore_fences(dev); |
| 4922 | |
| 4923 | i915_gem_detect_bit_6_swizzle(dev); |
| 4924 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
| 4925 | |
| 4926 | dev_priv->mm.interruptible = true; |
| 4927 | |
| 4928 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
| 4929 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; |
| 4930 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; |
| 4931 | register_shrinker(&dev_priv->mm.shrinker); |
| 4932 | |
| 4933 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; |
| 4934 | register_oom_notifier(&dev_priv->mm.oom_notifier); |
| 4935 | |
| 4936 | mutex_init(&dev_priv->fb_tracking.lock); |
| 4937 | } |
| 4938 | |
| 4939 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
| 4940 | { |
| 4941 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 4942 | |
| 4943 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
| 4944 | |
| 4945 | /* Clean up our request list when the client is going away, so that |
| 4946 | * later retire_requests won't dereference our soon-to-be-gone |
| 4947 | * file_priv. |
| 4948 | */ |
| 4949 | spin_lock(&file_priv->mm.lock); |
| 4950 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4951 | struct drm_i915_gem_request *request; |
| 4952 | |
| 4953 | request = list_first_entry(&file_priv->mm.request_list, |
| 4954 | struct drm_i915_gem_request, |
| 4955 | client_list); |
| 4956 | list_del(&request->client_list); |
| 4957 | request->file_priv = NULL; |
| 4958 | } |
| 4959 | spin_unlock(&file_priv->mm.lock); |
| 4960 | } |
| 4961 | |
| 4962 | static void |
| 4963 | i915_gem_file_idle_work_handler(struct work_struct *work) |
| 4964 | { |
| 4965 | struct drm_i915_file_private *file_priv = |
| 4966 | container_of(work, typeof(*file_priv), mm.idle_work.work); |
| 4967 | |
| 4968 | atomic_set(&file_priv->rps_wait_boost, false); |
| 4969 | } |
| 4970 | |
| 4971 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 4972 | { |
| 4973 | struct drm_i915_file_private *file_priv; |
| 4974 | int ret; |
| 4975 | |
| 4976 | DRM_DEBUG_DRIVER("\n"); |
| 4977 | |
| 4978 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 4979 | if (!file_priv) |
| 4980 | return -ENOMEM; |
| 4981 | |
| 4982 | file->driver_priv = file_priv; |
| 4983 | file_priv->dev_priv = dev->dev_private; |
| 4984 | file_priv->file = file; |
| 4985 | |
| 4986 | spin_lock_init(&file_priv->mm.lock); |
| 4987 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
| 4988 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, |
| 4989 | i915_gem_file_idle_work_handler); |
| 4990 | |
| 4991 | ret = i915_gem_context_open(dev, file); |
| 4992 | if (ret) |
| 4993 | kfree(file_priv); |
| 4994 | |
| 4995 | return ret; |
| 4996 | } |
| 4997 | |
| 4998 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 4999 | struct drm_i915_gem_object *new, |
| 5000 | unsigned frontbuffer_bits) |
| 5001 | { |
| 5002 | if (old) { |
| 5003 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5004 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5005 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5006 | } |
| 5007 | |
| 5008 | if (new) { |
| 5009 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5010 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5011 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5012 | } |
| 5013 | } |
| 5014 | |
| 5015 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 5016 | { |
| 5017 | if (!mutex_is_locked(mutex)) |
| 5018 | return false; |
| 5019 | |
| 5020 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 5021 | return mutex->owner == task; |
| 5022 | #else |
| 5023 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 5024 | return false; |
| 5025 | #endif |
| 5026 | } |
| 5027 | |
| 5028 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
| 5029 | { |
| 5030 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 5031 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
| 5032 | return false; |
| 5033 | |
| 5034 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) |
| 5035 | return false; |
| 5036 | |
| 5037 | *unlock = false; |
| 5038 | } else |
| 5039 | *unlock = true; |
| 5040 | |
| 5041 | return true; |
| 5042 | } |
| 5043 | |
| 5044 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
| 5045 | { |
| 5046 | struct i915_vma *vma; |
| 5047 | int count = 0; |
| 5048 | |
| 5049 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 5050 | if (drm_mm_node_allocated(&vma->node)) |
| 5051 | count++; |
| 5052 | |
| 5053 | return count; |
| 5054 | } |
| 5055 | |
| 5056 | static unsigned long |
| 5057 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
| 5058 | { |
| 5059 | struct drm_i915_private *dev_priv = |
| 5060 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
| 5061 | struct drm_device *dev = dev_priv->dev; |
| 5062 | struct drm_i915_gem_object *obj; |
| 5063 | unsigned long count; |
| 5064 | bool unlock; |
| 5065 | |
| 5066 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
| 5067 | return 0; |
| 5068 | |
| 5069 | count = 0; |
| 5070 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
| 5071 | if (obj->pages_pin_count == 0) |
| 5072 | count += obj->base.size >> PAGE_SHIFT; |
| 5073 | |
| 5074 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 5075 | if (!i915_gem_obj_is_pinned(obj) && |
| 5076 | obj->pages_pin_count == num_vma_bound(obj)) |
| 5077 | count += obj->base.size >> PAGE_SHIFT; |
| 5078 | } |
| 5079 | |
| 5080 | if (unlock) |
| 5081 | mutex_unlock(&dev->struct_mutex); |
| 5082 | |
| 5083 | return count; |
| 5084 | } |
| 5085 | |
| 5086 | /* All the new VM stuff */ |
| 5087 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5088 | struct i915_address_space *vm) |
| 5089 | { |
| 5090 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5091 | struct i915_vma *vma; |
| 5092 | |
| 5093 | if (!dev_priv->mm.aliasing_ppgtt || |
| 5094 | vm == &dev_priv->mm.aliasing_ppgtt->base) |
| 5095 | vm = &dev_priv->gtt.base; |
| 5096 | |
| 5097 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5098 | if (vma->vm == vm) |
| 5099 | return vma->node.start; |
| 5100 | |
| 5101 | } |
| 5102 | WARN(1, "%s vma for this object not found.\n", |
| 5103 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
| 5104 | return -1; |
| 5105 | } |
| 5106 | |
| 5107 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5108 | struct i915_address_space *vm) |
| 5109 | { |
| 5110 | struct i915_vma *vma; |
| 5111 | |
| 5112 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5113 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
| 5114 | return true; |
| 5115 | |
| 5116 | return false; |
| 5117 | } |
| 5118 | |
| 5119 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5120 | { |
| 5121 | struct i915_vma *vma; |
| 5122 | |
| 5123 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5124 | if (drm_mm_node_allocated(&vma->node)) |
| 5125 | return true; |
| 5126 | |
| 5127 | return false; |
| 5128 | } |
| 5129 | |
| 5130 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 5131 | struct i915_address_space *vm) |
| 5132 | { |
| 5133 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5134 | struct i915_vma *vma; |
| 5135 | |
| 5136 | if (!dev_priv->mm.aliasing_ppgtt || |
| 5137 | vm == &dev_priv->mm.aliasing_ppgtt->base) |
| 5138 | vm = &dev_priv->gtt.base; |
| 5139 | |
| 5140 | BUG_ON(list_empty(&o->vma_list)); |
| 5141 | |
| 5142 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5143 | if (vma->vm == vm) |
| 5144 | return vma->node.size; |
| 5145 | |
| 5146 | return 0; |
| 5147 | } |
| 5148 | |
| 5149 | static unsigned long |
| 5150 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
| 5151 | { |
| 5152 | struct drm_i915_private *dev_priv = |
| 5153 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
| 5154 | struct drm_device *dev = dev_priv->dev; |
| 5155 | unsigned long freed; |
| 5156 | bool unlock; |
| 5157 | |
| 5158 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
| 5159 | return SHRINK_STOP; |
| 5160 | |
| 5161 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
| 5162 | if (freed < sc->nr_to_scan) |
| 5163 | freed += __i915_gem_shrink(dev_priv, |
| 5164 | sc->nr_to_scan - freed, |
| 5165 | false); |
| 5166 | if (unlock) |
| 5167 | mutex_unlock(&dev->struct_mutex); |
| 5168 | |
| 5169 | return freed; |
| 5170 | } |
| 5171 | |
| 5172 | static int |
| 5173 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) |
| 5174 | { |
| 5175 | struct drm_i915_private *dev_priv = |
| 5176 | container_of(nb, struct drm_i915_private, mm.oom_notifier); |
| 5177 | struct drm_device *dev = dev_priv->dev; |
| 5178 | struct drm_i915_gem_object *obj; |
| 5179 | unsigned long timeout = msecs_to_jiffies(5000) + 1; |
| 5180 | unsigned long pinned, bound, unbound, freed; |
| 5181 | bool was_interruptible; |
| 5182 | bool unlock; |
| 5183 | |
| 5184 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
| 5185 | schedule_timeout_killable(1); |
| 5186 | if (fatal_signal_pending(current)) |
| 5187 | return NOTIFY_DONE; |
| 5188 | } |
| 5189 | if (timeout == 0) { |
| 5190 | pr_err("Unable to purge GPU memory due lock contention.\n"); |
| 5191 | return NOTIFY_DONE; |
| 5192 | } |
| 5193 | |
| 5194 | was_interruptible = dev_priv->mm.interruptible; |
| 5195 | dev_priv->mm.interruptible = false; |
| 5196 | |
| 5197 | freed = i915_gem_shrink_all(dev_priv); |
| 5198 | |
| 5199 | dev_priv->mm.interruptible = was_interruptible; |
| 5200 | |
| 5201 | /* Because we may be allocating inside our own driver, we cannot |
| 5202 | * assert that there are no objects with pinned pages that are not |
| 5203 | * being pointed to by hardware. |
| 5204 | */ |
| 5205 | unbound = bound = pinned = 0; |
| 5206 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
| 5207 | if (!obj->base.filp) /* not backed by a freeable object */ |
| 5208 | continue; |
| 5209 | |
| 5210 | if (obj->pages_pin_count) |
| 5211 | pinned += obj->base.size; |
| 5212 | else |
| 5213 | unbound += obj->base.size; |
| 5214 | } |
| 5215 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 5216 | if (!obj->base.filp) |
| 5217 | continue; |
| 5218 | |
| 5219 | if (obj->pages_pin_count) |
| 5220 | pinned += obj->base.size; |
| 5221 | else |
| 5222 | bound += obj->base.size; |
| 5223 | } |
| 5224 | |
| 5225 | if (unlock) |
| 5226 | mutex_unlock(&dev->struct_mutex); |
| 5227 | |
| 5228 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", |
| 5229 | freed, pinned); |
| 5230 | if (unbound || bound) |
| 5231 | pr_err("%lu and %lu bytes still available in the " |
| 5232 | "bound and unbound GPU page lists.\n", |
| 5233 | bound, unbound); |
| 5234 | |
| 5235 | *(unsigned long *)ptr += freed; |
| 5236 | return NOTIFY_DONE; |
| 5237 | } |
| 5238 | |
| 5239 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
| 5240 | { |
| 5241 | struct i915_vma *vma; |
| 5242 | |
| 5243 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
| 5244 | if (vma->vm != obj_to_ggtt(obj)) |
| 5245 | return NULL; |
| 5246 | |
| 5247 | return vma; |
| 5248 | } |