| 1 | /* |
| 2 | * Copyright © 2008-2015 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <drm/drmP.h> |
| 29 | #include <drm/drm_vma_manager.h> |
| 30 | #include <drm/i915_drm.h> |
| 31 | #include "i915_drv.h" |
| 32 | #include "i915_vgpu.h" |
| 33 | #include "i915_trace.h" |
| 34 | #include "intel_drv.h" |
| 35 | #include <linux/shmem_fs.h> |
| 36 | #include <linux/slab.h> |
| 37 | #include <linux/swap.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/dma-buf.h> |
| 40 | |
| 41 | #define RQ_BUG_ON(expr) |
| 42 | |
| 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
| 45 | static void |
| 46 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
| 47 | static void |
| 48 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); |
| 49 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 50 | struct drm_i915_gem_object *obj); |
| 51 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 52 | struct drm_i915_fence_reg *fence, |
| 53 | bool enable); |
| 54 | |
| 55 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 56 | enum i915_cache_level level) |
| 57 | { |
| 58 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 59 | } |
| 60 | |
| 61 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 62 | { |
| 63 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 64 | return true; |
| 65 | |
| 66 | return obj->pin_display; |
| 67 | } |
| 68 | |
| 69 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 70 | { |
| 71 | if (obj->tiling_mode) |
| 72 | i915_gem_release_mmap(obj); |
| 73 | |
| 74 | /* As we do not have an associated fence register, we will force |
| 75 | * a tiling change if we ever need to acquire one. |
| 76 | */ |
| 77 | obj->fence_dirty = false; |
| 78 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 79 | } |
| 80 | |
| 81 | /* some bookkeeping */ |
| 82 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 83 | size_t size) |
| 84 | { |
| 85 | spin_lock(&dev_priv->mm.object_stat_lock); |
| 86 | dev_priv->mm.object_count++; |
| 87 | dev_priv->mm.object_memory += size; |
| 88 | spin_unlock(&dev_priv->mm.object_stat_lock); |
| 89 | } |
| 90 | |
| 91 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 92 | size_t size) |
| 93 | { |
| 94 | spin_lock(&dev_priv->mm.object_stat_lock); |
| 95 | dev_priv->mm.object_count--; |
| 96 | dev_priv->mm.object_memory -= size; |
| 97 | spin_unlock(&dev_priv->mm.object_stat_lock); |
| 98 | } |
| 99 | |
| 100 | static int |
| 101 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
| 102 | { |
| 103 | int ret; |
| 104 | |
| 105 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 106 | i915_terminally_wedged(error)) |
| 107 | if (EXIT_COND) |
| 108 | return 0; |
| 109 | |
| 110 | /* |
| 111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 112 | * userspace. If it takes that long something really bad is going on and |
| 113 | * we should simply try to bail out and fail as gracefully as possible. |
| 114 | */ |
| 115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 116 | EXIT_COND, |
| 117 | 10*HZ); |
| 118 | if (ret == 0) { |
| 119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 120 | return -EIO; |
| 121 | } else if (ret < 0) { |
| 122 | return ret; |
| 123 | } |
| 124 | #undef EXIT_COND |
| 125 | |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 130 | { |
| 131 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 132 | int ret; |
| 133 | |
| 134 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 135 | if (ret) |
| 136 | return ret; |
| 137 | |
| 138 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 139 | if (ret) |
| 140 | return ret; |
| 141 | |
| 142 | WARN_ON(i915_verify_lists(dev)); |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | int |
| 147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 148 | struct drm_file *file) |
| 149 | { |
| 150 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 151 | struct drm_i915_gem_get_aperture *args = data; |
| 152 | struct drm_i915_gem_object *obj; |
| 153 | size_t pinned; |
| 154 | |
| 155 | pinned = 0; |
| 156 | mutex_lock(&dev->struct_mutex); |
| 157 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 158 | if (i915_gem_obj_is_pinned(obj)) |
| 159 | pinned += i915_gem_obj_ggtt_size(obj); |
| 160 | mutex_unlock(&dev->struct_mutex); |
| 161 | |
| 162 | args->aper_size = dev_priv->gtt.base.total; |
| 163 | args->aper_available_size = args->aper_size - pinned; |
| 164 | |
| 165 | return 0; |
| 166 | } |
| 167 | |
| 168 | static int |
| 169 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
| 170 | { |
| 171 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 172 | char *vaddr = obj->phys_handle->vaddr; |
| 173 | struct sg_table *st; |
| 174 | struct scatterlist *sg; |
| 175 | int i; |
| 176 | |
| 177 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
| 178 | return -EINVAL; |
| 179 | |
| 180 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 181 | struct page *page; |
| 182 | char *src; |
| 183 | |
| 184 | page = shmem_read_mapping_page(mapping, i); |
| 185 | if (IS_ERR(page)) |
| 186 | return PTR_ERR(page); |
| 187 | |
| 188 | src = kmap_atomic(page); |
| 189 | memcpy(vaddr, src, PAGE_SIZE); |
| 190 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 191 | kunmap_atomic(src); |
| 192 | |
| 193 | page_cache_release(page); |
| 194 | vaddr += PAGE_SIZE; |
| 195 | } |
| 196 | |
| 197 | i915_gem_chipset_flush(obj->base.dev); |
| 198 | |
| 199 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 200 | if (st == NULL) |
| 201 | return -ENOMEM; |
| 202 | |
| 203 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { |
| 204 | kfree(st); |
| 205 | return -ENOMEM; |
| 206 | } |
| 207 | |
| 208 | sg = st->sgl; |
| 209 | sg->offset = 0; |
| 210 | sg->length = obj->base.size; |
| 211 | |
| 212 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
| 213 | sg_dma_len(sg) = obj->base.size; |
| 214 | |
| 215 | obj->pages = st; |
| 216 | obj->has_dma_mapping = true; |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static void |
| 221 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) |
| 222 | { |
| 223 | int ret; |
| 224 | |
| 225 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 226 | |
| 227 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 228 | if (ret) { |
| 229 | /* In the event of a disaster, abandon all caches and |
| 230 | * hope for the best. |
| 231 | */ |
| 232 | WARN_ON(ret != -EIO); |
| 233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 234 | } |
| 235 | |
| 236 | if (obj->madv == I915_MADV_DONTNEED) |
| 237 | obj->dirty = 0; |
| 238 | |
| 239 | if (obj->dirty) { |
| 240 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 241 | char *vaddr = obj->phys_handle->vaddr; |
| 242 | int i; |
| 243 | |
| 244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 245 | struct page *page; |
| 246 | char *dst; |
| 247 | |
| 248 | page = shmem_read_mapping_page(mapping, i); |
| 249 | if (IS_ERR(page)) |
| 250 | continue; |
| 251 | |
| 252 | dst = kmap_atomic(page); |
| 253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 254 | memcpy(dst, vaddr, PAGE_SIZE); |
| 255 | kunmap_atomic(dst); |
| 256 | |
| 257 | set_page_dirty(page); |
| 258 | if (obj->madv == I915_MADV_WILLNEED) |
| 259 | mark_page_accessed(page); |
| 260 | page_cache_release(page); |
| 261 | vaddr += PAGE_SIZE; |
| 262 | } |
| 263 | obj->dirty = 0; |
| 264 | } |
| 265 | |
| 266 | sg_free_table(obj->pages); |
| 267 | kfree(obj->pages); |
| 268 | |
| 269 | obj->has_dma_mapping = false; |
| 270 | } |
| 271 | |
| 272 | static void |
| 273 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) |
| 274 | { |
| 275 | drm_pci_free(obj->base.dev, obj->phys_handle); |
| 276 | } |
| 277 | |
| 278 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { |
| 279 | .get_pages = i915_gem_object_get_pages_phys, |
| 280 | .put_pages = i915_gem_object_put_pages_phys, |
| 281 | .release = i915_gem_object_release_phys, |
| 282 | }; |
| 283 | |
| 284 | static int |
| 285 | drop_pages(struct drm_i915_gem_object *obj) |
| 286 | { |
| 287 | struct i915_vma *vma, *next; |
| 288 | int ret; |
| 289 | |
| 290 | drm_gem_object_reference(&obj->base); |
| 291 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) |
| 292 | if (i915_vma_unbind(vma)) |
| 293 | break; |
| 294 | |
| 295 | ret = i915_gem_object_put_pages(obj); |
| 296 | drm_gem_object_unreference(&obj->base); |
| 297 | |
| 298 | return ret; |
| 299 | } |
| 300 | |
| 301 | int |
| 302 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 303 | int align) |
| 304 | { |
| 305 | drm_dma_handle_t *phys; |
| 306 | int ret; |
| 307 | |
| 308 | if (obj->phys_handle) { |
| 309 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 310 | return -EBUSY; |
| 311 | |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | if (obj->madv != I915_MADV_WILLNEED) |
| 316 | return -EFAULT; |
| 317 | |
| 318 | if (obj->base.filp == NULL) |
| 319 | return -EINVAL; |
| 320 | |
| 321 | ret = drop_pages(obj); |
| 322 | if (ret) |
| 323 | return ret; |
| 324 | |
| 325 | /* create a new object */ |
| 326 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 327 | if (!phys) |
| 328 | return -ENOMEM; |
| 329 | |
| 330 | obj->phys_handle = phys; |
| 331 | obj->ops = &i915_gem_phys_ops; |
| 332 | |
| 333 | return i915_gem_object_get_pages(obj); |
| 334 | } |
| 335 | |
| 336 | static int |
| 337 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 338 | struct drm_i915_gem_pwrite *args, |
| 339 | struct drm_file *file_priv) |
| 340 | { |
| 341 | struct drm_device *dev = obj->base.dev; |
| 342 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 343 | char __user *user_data = to_user_ptr(args->data_ptr); |
| 344 | int ret = 0; |
| 345 | |
| 346 | /* We manually control the domain here and pretend that it |
| 347 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. |
| 348 | */ |
| 349 | ret = i915_gem_object_wait_rendering(obj, false); |
| 350 | if (ret) |
| 351 | return ret; |
| 352 | |
| 353 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
| 354 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 355 | unsigned long unwritten; |
| 356 | |
| 357 | /* The physical object once assigned is fixed for the lifetime |
| 358 | * of the obj, so we can safely drop the lock and continue |
| 359 | * to access vaddr. |
| 360 | */ |
| 361 | mutex_unlock(&dev->struct_mutex); |
| 362 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 363 | mutex_lock(&dev->struct_mutex); |
| 364 | if (unwritten) { |
| 365 | ret = -EFAULT; |
| 366 | goto out; |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | drm_clflush_virt_range(vaddr, args->size); |
| 371 | i915_gem_chipset_flush(dev); |
| 372 | |
| 373 | out: |
| 374 | intel_fb_obj_flush(obj, false); |
| 375 | return ret; |
| 376 | } |
| 377 | |
| 378 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 379 | { |
| 380 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 381 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
| 382 | } |
| 383 | |
| 384 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 385 | { |
| 386 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 387 | kmem_cache_free(dev_priv->objects, obj); |
| 388 | } |
| 389 | |
| 390 | static int |
| 391 | i915_gem_create(struct drm_file *file, |
| 392 | struct drm_device *dev, |
| 393 | uint64_t size, |
| 394 | uint32_t *handle_p) |
| 395 | { |
| 396 | struct drm_i915_gem_object *obj; |
| 397 | int ret; |
| 398 | u32 handle; |
| 399 | |
| 400 | size = roundup(size, PAGE_SIZE); |
| 401 | if (size == 0) |
| 402 | return -EINVAL; |
| 403 | |
| 404 | /* Allocate the new object */ |
| 405 | obj = i915_gem_alloc_object(dev, size); |
| 406 | if (obj == NULL) |
| 407 | return -ENOMEM; |
| 408 | |
| 409 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
| 410 | /* drop reference from allocate - handle holds it now */ |
| 411 | drm_gem_object_unreference_unlocked(&obj->base); |
| 412 | if (ret) |
| 413 | return ret; |
| 414 | |
| 415 | *handle_p = handle; |
| 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | int |
| 420 | i915_gem_dumb_create(struct drm_file *file, |
| 421 | struct drm_device *dev, |
| 422 | struct drm_mode_create_dumb *args) |
| 423 | { |
| 424 | /* have to work out size/pitch and return them */ |
| 425 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
| 426 | args->size = args->pitch * args->height; |
| 427 | return i915_gem_create(file, dev, |
| 428 | args->size, &args->handle); |
| 429 | } |
| 430 | |
| 431 | /** |
| 432 | * Creates a new mm object and returns a handle to it. |
| 433 | */ |
| 434 | int |
| 435 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 436 | struct drm_file *file) |
| 437 | { |
| 438 | struct drm_i915_gem_create *args = data; |
| 439 | |
| 440 | return i915_gem_create(file, dev, |
| 441 | args->size, &args->handle); |
| 442 | } |
| 443 | |
| 444 | static inline int |
| 445 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 446 | const char *gpu_vaddr, int gpu_offset, |
| 447 | int length) |
| 448 | { |
| 449 | int ret, cpu_offset = 0; |
| 450 | |
| 451 | while (length > 0) { |
| 452 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 453 | int this_length = min(cacheline_end - gpu_offset, length); |
| 454 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 455 | |
| 456 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 457 | gpu_vaddr + swizzled_gpu_offset, |
| 458 | this_length); |
| 459 | if (ret) |
| 460 | return ret + length; |
| 461 | |
| 462 | cpu_offset += this_length; |
| 463 | gpu_offset += this_length; |
| 464 | length -= this_length; |
| 465 | } |
| 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | static inline int |
| 471 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 472 | const char __user *cpu_vaddr, |
| 473 | int length) |
| 474 | { |
| 475 | int ret, cpu_offset = 0; |
| 476 | |
| 477 | while (length > 0) { |
| 478 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 479 | int this_length = min(cacheline_end - gpu_offset, length); |
| 480 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 481 | |
| 482 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 483 | cpu_vaddr + cpu_offset, |
| 484 | this_length); |
| 485 | if (ret) |
| 486 | return ret + length; |
| 487 | |
| 488 | cpu_offset += this_length; |
| 489 | gpu_offset += this_length; |
| 490 | length -= this_length; |
| 491 | } |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | /* |
| 497 | * Pins the specified object's pages and synchronizes the object with |
| 498 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 499 | * flush the object from the CPU cache. |
| 500 | */ |
| 501 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 502 | int *needs_clflush) |
| 503 | { |
| 504 | int ret; |
| 505 | |
| 506 | *needs_clflush = 0; |
| 507 | |
| 508 | if (!obj->base.filp) |
| 509 | return -EINVAL; |
| 510 | |
| 511 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 512 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 513 | * read domain and manually flush cachelines (if required). This |
| 514 | * optimizes for the case when the gpu will dirty the data |
| 515 | * anyway again before the next pread happens. */ |
| 516 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 517 | obj->cache_level); |
| 518 | ret = i915_gem_object_wait_rendering(obj, true); |
| 519 | if (ret) |
| 520 | return ret; |
| 521 | } |
| 522 | |
| 523 | ret = i915_gem_object_get_pages(obj); |
| 524 | if (ret) |
| 525 | return ret; |
| 526 | |
| 527 | i915_gem_object_pin_pages(obj); |
| 528 | |
| 529 | return ret; |
| 530 | } |
| 531 | |
| 532 | /* Per-page copy function for the shmem pread fastpath. |
| 533 | * Flushes invalid cachelines before reading the target if |
| 534 | * needs_clflush is set. */ |
| 535 | static int |
| 536 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 537 | char __user *user_data, |
| 538 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 539 | { |
| 540 | char *vaddr; |
| 541 | int ret; |
| 542 | |
| 543 | if (unlikely(page_do_bit17_swizzling)) |
| 544 | return -EINVAL; |
| 545 | |
| 546 | vaddr = kmap_atomic(page); |
| 547 | if (needs_clflush) |
| 548 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 549 | page_length); |
| 550 | ret = __copy_to_user_inatomic(user_data, |
| 551 | vaddr + shmem_page_offset, |
| 552 | page_length); |
| 553 | kunmap_atomic(vaddr); |
| 554 | |
| 555 | return ret ? -EFAULT : 0; |
| 556 | } |
| 557 | |
| 558 | static void |
| 559 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 560 | bool swizzled) |
| 561 | { |
| 562 | if (unlikely(swizzled)) { |
| 563 | unsigned long start = (unsigned long) addr; |
| 564 | unsigned long end = (unsigned long) addr + length; |
| 565 | |
| 566 | /* For swizzling simply ensure that we always flush both |
| 567 | * channels. Lame, but simple and it works. Swizzled |
| 568 | * pwrite/pread is far from a hotpath - current userspace |
| 569 | * doesn't use it at all. */ |
| 570 | start = round_down(start, 128); |
| 571 | end = round_up(end, 128); |
| 572 | |
| 573 | drm_clflush_virt_range((void *)start, end - start); |
| 574 | } else { |
| 575 | drm_clflush_virt_range(addr, length); |
| 576 | } |
| 577 | |
| 578 | } |
| 579 | |
| 580 | /* Only difference to the fast-path function is that this can handle bit17 |
| 581 | * and uses non-atomic copy and kmap functions. */ |
| 582 | static int |
| 583 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 584 | char __user *user_data, |
| 585 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 586 | { |
| 587 | char *vaddr; |
| 588 | int ret; |
| 589 | |
| 590 | vaddr = kmap(page); |
| 591 | if (needs_clflush) |
| 592 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 593 | page_length, |
| 594 | page_do_bit17_swizzling); |
| 595 | |
| 596 | if (page_do_bit17_swizzling) |
| 597 | ret = __copy_to_user_swizzled(user_data, |
| 598 | vaddr, shmem_page_offset, |
| 599 | page_length); |
| 600 | else |
| 601 | ret = __copy_to_user(user_data, |
| 602 | vaddr + shmem_page_offset, |
| 603 | page_length); |
| 604 | kunmap(page); |
| 605 | |
| 606 | return ret ? - EFAULT : 0; |
| 607 | } |
| 608 | |
| 609 | static int |
| 610 | i915_gem_shmem_pread(struct drm_device *dev, |
| 611 | struct drm_i915_gem_object *obj, |
| 612 | struct drm_i915_gem_pread *args, |
| 613 | struct drm_file *file) |
| 614 | { |
| 615 | char __user *user_data; |
| 616 | ssize_t remain; |
| 617 | loff_t offset; |
| 618 | int shmem_page_offset, page_length, ret = 0; |
| 619 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
| 620 | int prefaulted = 0; |
| 621 | int needs_clflush = 0; |
| 622 | struct sg_page_iter sg_iter; |
| 623 | |
| 624 | user_data = to_user_ptr(args->data_ptr); |
| 625 | remain = args->size; |
| 626 | |
| 627 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 628 | |
| 629 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
| 630 | if (ret) |
| 631 | return ret; |
| 632 | |
| 633 | offset = args->offset; |
| 634 | |
| 635 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 636 | offset >> PAGE_SHIFT) { |
| 637 | struct page *page = sg_page_iter_page(&sg_iter); |
| 638 | |
| 639 | if (remain <= 0) |
| 640 | break; |
| 641 | |
| 642 | /* Operation in this page |
| 643 | * |
| 644 | * shmem_page_offset = offset within page in shmem file |
| 645 | * page_length = bytes to copy for this page |
| 646 | */ |
| 647 | shmem_page_offset = offset_in_page(offset); |
| 648 | page_length = remain; |
| 649 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 650 | page_length = PAGE_SIZE - shmem_page_offset; |
| 651 | |
| 652 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 653 | (page_to_phys(page) & (1 << 17)) != 0; |
| 654 | |
| 655 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 656 | user_data, page_do_bit17_swizzling, |
| 657 | needs_clflush); |
| 658 | if (ret == 0) |
| 659 | goto next_page; |
| 660 | |
| 661 | mutex_unlock(&dev->struct_mutex); |
| 662 | |
| 663 | if (likely(!i915.prefault_disable) && !prefaulted) { |
| 664 | ret = fault_in_multipages_writeable(user_data, remain); |
| 665 | /* Userspace is tricking us, but we've already clobbered |
| 666 | * its pages with the prefault and promised to write the |
| 667 | * data up to the first fault. Hence ignore any errors |
| 668 | * and just continue. */ |
| 669 | (void)ret; |
| 670 | prefaulted = 1; |
| 671 | } |
| 672 | |
| 673 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 674 | user_data, page_do_bit17_swizzling, |
| 675 | needs_clflush); |
| 676 | |
| 677 | mutex_lock(&dev->struct_mutex); |
| 678 | |
| 679 | if (ret) |
| 680 | goto out; |
| 681 | |
| 682 | next_page: |
| 683 | remain -= page_length; |
| 684 | user_data += page_length; |
| 685 | offset += page_length; |
| 686 | } |
| 687 | |
| 688 | out: |
| 689 | i915_gem_object_unpin_pages(obj); |
| 690 | |
| 691 | return ret; |
| 692 | } |
| 693 | |
| 694 | /** |
| 695 | * Reads data from the object referenced by handle. |
| 696 | * |
| 697 | * On error, the contents of *data are undefined. |
| 698 | */ |
| 699 | int |
| 700 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 701 | struct drm_file *file) |
| 702 | { |
| 703 | struct drm_i915_gem_pread *args = data; |
| 704 | struct drm_i915_gem_object *obj; |
| 705 | int ret = 0; |
| 706 | |
| 707 | if (args->size == 0) |
| 708 | return 0; |
| 709 | |
| 710 | if (!access_ok(VERIFY_WRITE, |
| 711 | to_user_ptr(args->data_ptr), |
| 712 | args->size)) |
| 713 | return -EFAULT; |
| 714 | |
| 715 | ret = i915_mutex_lock_interruptible(dev); |
| 716 | if (ret) |
| 717 | return ret; |
| 718 | |
| 719 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 720 | if (&obj->base == NULL) { |
| 721 | ret = -ENOENT; |
| 722 | goto unlock; |
| 723 | } |
| 724 | |
| 725 | /* Bounds check source. */ |
| 726 | if (args->offset > obj->base.size || |
| 727 | args->size > obj->base.size - args->offset) { |
| 728 | ret = -EINVAL; |
| 729 | goto out; |
| 730 | } |
| 731 | |
| 732 | /* prime objects have no backing filp to GEM pread/pwrite |
| 733 | * pages from. |
| 734 | */ |
| 735 | if (!obj->base.filp) { |
| 736 | ret = -EINVAL; |
| 737 | goto out; |
| 738 | } |
| 739 | |
| 740 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 741 | |
| 742 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
| 743 | |
| 744 | out: |
| 745 | drm_gem_object_unreference(&obj->base); |
| 746 | unlock: |
| 747 | mutex_unlock(&dev->struct_mutex); |
| 748 | return ret; |
| 749 | } |
| 750 | |
| 751 | /* This is the fast write path which cannot handle |
| 752 | * page faults in the source data |
| 753 | */ |
| 754 | |
| 755 | static inline int |
| 756 | fast_user_write(struct io_mapping *mapping, |
| 757 | loff_t page_base, int page_offset, |
| 758 | char __user *user_data, |
| 759 | int length) |
| 760 | { |
| 761 | void __iomem *vaddr_atomic; |
| 762 | void *vaddr; |
| 763 | unsigned long unwritten; |
| 764 | |
| 765 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 766 | /* We can use the cpu mem copy function because this is X86. */ |
| 767 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 768 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
| 769 | user_data, length); |
| 770 | io_mapping_unmap_atomic(vaddr_atomic); |
| 771 | return unwritten; |
| 772 | } |
| 773 | |
| 774 | /** |
| 775 | * This is the fast pwrite path, where we copy the data directly from the |
| 776 | * user into the GTT, uncached. |
| 777 | */ |
| 778 | static int |
| 779 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 780 | struct drm_i915_gem_object *obj, |
| 781 | struct drm_i915_gem_pwrite *args, |
| 782 | struct drm_file *file) |
| 783 | { |
| 784 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 785 | ssize_t remain; |
| 786 | loff_t offset, page_base; |
| 787 | char __user *user_data; |
| 788 | int page_offset, page_length, ret; |
| 789 | |
| 790 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
| 791 | if (ret) |
| 792 | goto out; |
| 793 | |
| 794 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 795 | if (ret) |
| 796 | goto out_unpin; |
| 797 | |
| 798 | ret = i915_gem_object_put_fence(obj); |
| 799 | if (ret) |
| 800 | goto out_unpin; |
| 801 | |
| 802 | user_data = to_user_ptr(args->data_ptr); |
| 803 | remain = args->size; |
| 804 | |
| 805 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
| 806 | |
| 807 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
| 808 | |
| 809 | while (remain > 0) { |
| 810 | /* Operation in this page |
| 811 | * |
| 812 | * page_base = page offset within aperture |
| 813 | * page_offset = offset within page |
| 814 | * page_length = bytes to copy for this page |
| 815 | */ |
| 816 | page_base = offset & PAGE_MASK; |
| 817 | page_offset = offset_in_page(offset); |
| 818 | page_length = remain; |
| 819 | if ((page_offset + remain) > PAGE_SIZE) |
| 820 | page_length = PAGE_SIZE - page_offset; |
| 821 | |
| 822 | /* If we get a fault while copying data, then (presumably) our |
| 823 | * source page isn't available. Return the error and we'll |
| 824 | * retry in the slow path. |
| 825 | */ |
| 826 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
| 827 | page_offset, user_data, page_length)) { |
| 828 | ret = -EFAULT; |
| 829 | goto out_flush; |
| 830 | } |
| 831 | |
| 832 | remain -= page_length; |
| 833 | user_data += page_length; |
| 834 | offset += page_length; |
| 835 | } |
| 836 | |
| 837 | out_flush: |
| 838 | intel_fb_obj_flush(obj, false); |
| 839 | out_unpin: |
| 840 | i915_gem_object_ggtt_unpin(obj); |
| 841 | out: |
| 842 | return ret; |
| 843 | } |
| 844 | |
| 845 | /* Per-page copy function for the shmem pwrite fastpath. |
| 846 | * Flushes invalid cachelines before writing to the target if |
| 847 | * needs_clflush_before is set and flushes out any written cachelines after |
| 848 | * writing if needs_clflush is set. */ |
| 849 | static int |
| 850 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 851 | char __user *user_data, |
| 852 | bool page_do_bit17_swizzling, |
| 853 | bool needs_clflush_before, |
| 854 | bool needs_clflush_after) |
| 855 | { |
| 856 | char *vaddr; |
| 857 | int ret; |
| 858 | |
| 859 | if (unlikely(page_do_bit17_swizzling)) |
| 860 | return -EINVAL; |
| 861 | |
| 862 | vaddr = kmap_atomic(page); |
| 863 | if (needs_clflush_before) |
| 864 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 865 | page_length); |
| 866 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 867 | user_data, page_length); |
| 868 | if (needs_clflush_after) |
| 869 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 870 | page_length); |
| 871 | kunmap_atomic(vaddr); |
| 872 | |
| 873 | return ret ? -EFAULT : 0; |
| 874 | } |
| 875 | |
| 876 | /* Only difference to the fast-path function is that this can handle bit17 |
| 877 | * and uses non-atomic copy and kmap functions. */ |
| 878 | static int |
| 879 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 880 | char __user *user_data, |
| 881 | bool page_do_bit17_swizzling, |
| 882 | bool needs_clflush_before, |
| 883 | bool needs_clflush_after) |
| 884 | { |
| 885 | char *vaddr; |
| 886 | int ret; |
| 887 | |
| 888 | vaddr = kmap(page); |
| 889 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
| 890 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 891 | page_length, |
| 892 | page_do_bit17_swizzling); |
| 893 | if (page_do_bit17_swizzling) |
| 894 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
| 895 | user_data, |
| 896 | page_length); |
| 897 | else |
| 898 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 899 | user_data, |
| 900 | page_length); |
| 901 | if (needs_clflush_after) |
| 902 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 903 | page_length, |
| 904 | page_do_bit17_swizzling); |
| 905 | kunmap(page); |
| 906 | |
| 907 | return ret ? -EFAULT : 0; |
| 908 | } |
| 909 | |
| 910 | static int |
| 911 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 912 | struct drm_i915_gem_object *obj, |
| 913 | struct drm_i915_gem_pwrite *args, |
| 914 | struct drm_file *file) |
| 915 | { |
| 916 | ssize_t remain; |
| 917 | loff_t offset; |
| 918 | char __user *user_data; |
| 919 | int shmem_page_offset, page_length, ret = 0; |
| 920 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
| 921 | int hit_slowpath = 0; |
| 922 | int needs_clflush_after = 0; |
| 923 | int needs_clflush_before = 0; |
| 924 | struct sg_page_iter sg_iter; |
| 925 | |
| 926 | user_data = to_user_ptr(args->data_ptr); |
| 927 | remain = args->size; |
| 928 | |
| 929 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 930 | |
| 931 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 932 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 933 | * write domain and manually flush cachelines (if required). This |
| 934 | * optimizes for the case when the gpu will use the data |
| 935 | * right away and we therefore have to clflush anyway. */ |
| 936 | needs_clflush_after = cpu_write_needs_clflush(obj); |
| 937 | ret = i915_gem_object_wait_rendering(obj, false); |
| 938 | if (ret) |
| 939 | return ret; |
| 940 | } |
| 941 | /* Same trick applies to invalidate partially written cachelines read |
| 942 | * before writing. */ |
| 943 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 944 | needs_clflush_before = |
| 945 | !cpu_cache_is_coherent(dev, obj->cache_level); |
| 946 | |
| 947 | ret = i915_gem_object_get_pages(obj); |
| 948 | if (ret) |
| 949 | return ret; |
| 950 | |
| 951 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
| 952 | |
| 953 | i915_gem_object_pin_pages(obj); |
| 954 | |
| 955 | offset = args->offset; |
| 956 | obj->dirty = 1; |
| 957 | |
| 958 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 959 | offset >> PAGE_SHIFT) { |
| 960 | struct page *page = sg_page_iter_page(&sg_iter); |
| 961 | int partial_cacheline_write; |
| 962 | |
| 963 | if (remain <= 0) |
| 964 | break; |
| 965 | |
| 966 | /* Operation in this page |
| 967 | * |
| 968 | * shmem_page_offset = offset within page in shmem file |
| 969 | * page_length = bytes to copy for this page |
| 970 | */ |
| 971 | shmem_page_offset = offset_in_page(offset); |
| 972 | |
| 973 | page_length = remain; |
| 974 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 975 | page_length = PAGE_SIZE - shmem_page_offset; |
| 976 | |
| 977 | /* If we don't overwrite a cacheline completely we need to be |
| 978 | * careful to have up-to-date data by first clflushing. Don't |
| 979 | * overcomplicate things and flush the entire patch. */ |
| 980 | partial_cacheline_write = needs_clflush_before && |
| 981 | ((shmem_page_offset | page_length) |
| 982 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 983 | |
| 984 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 985 | (page_to_phys(page) & (1 << 17)) != 0; |
| 986 | |
| 987 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 988 | user_data, page_do_bit17_swizzling, |
| 989 | partial_cacheline_write, |
| 990 | needs_clflush_after); |
| 991 | if (ret == 0) |
| 992 | goto next_page; |
| 993 | |
| 994 | hit_slowpath = 1; |
| 995 | mutex_unlock(&dev->struct_mutex); |
| 996 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 997 | user_data, page_do_bit17_swizzling, |
| 998 | partial_cacheline_write, |
| 999 | needs_clflush_after); |
| 1000 | |
| 1001 | mutex_lock(&dev->struct_mutex); |
| 1002 | |
| 1003 | if (ret) |
| 1004 | goto out; |
| 1005 | |
| 1006 | next_page: |
| 1007 | remain -= page_length; |
| 1008 | user_data += page_length; |
| 1009 | offset += page_length; |
| 1010 | } |
| 1011 | |
| 1012 | out: |
| 1013 | i915_gem_object_unpin_pages(obj); |
| 1014 | |
| 1015 | if (hit_slowpath) { |
| 1016 | /* |
| 1017 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 1018 | * cachelines in-line while writing and the object moved |
| 1019 | * out of the cpu write domain while we've dropped the lock. |
| 1020 | */ |
| 1021 | if (!needs_clflush_after && |
| 1022 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 1023 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 1024 | i915_gem_chipset_flush(dev); |
| 1025 | } |
| 1026 | } |
| 1027 | |
| 1028 | if (needs_clflush_after) |
| 1029 | i915_gem_chipset_flush(dev); |
| 1030 | |
| 1031 | intel_fb_obj_flush(obj, false); |
| 1032 | return ret; |
| 1033 | } |
| 1034 | |
| 1035 | /** |
| 1036 | * Writes data to the object referenced by handle. |
| 1037 | * |
| 1038 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1039 | */ |
| 1040 | int |
| 1041 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1042 | struct drm_file *file) |
| 1043 | { |
| 1044 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1045 | struct drm_i915_gem_pwrite *args = data; |
| 1046 | struct drm_i915_gem_object *obj; |
| 1047 | int ret; |
| 1048 | |
| 1049 | if (args->size == 0) |
| 1050 | return 0; |
| 1051 | |
| 1052 | if (!access_ok(VERIFY_READ, |
| 1053 | to_user_ptr(args->data_ptr), |
| 1054 | args->size)) |
| 1055 | return -EFAULT; |
| 1056 | |
| 1057 | if (likely(!i915.prefault_disable)) { |
| 1058 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1059 | args->size); |
| 1060 | if (ret) |
| 1061 | return -EFAULT; |
| 1062 | } |
| 1063 | |
| 1064 | intel_runtime_pm_get(dev_priv); |
| 1065 | |
| 1066 | ret = i915_mutex_lock_interruptible(dev); |
| 1067 | if (ret) |
| 1068 | goto put_rpm; |
| 1069 | |
| 1070 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1071 | if (&obj->base == NULL) { |
| 1072 | ret = -ENOENT; |
| 1073 | goto unlock; |
| 1074 | } |
| 1075 | |
| 1076 | /* Bounds check destination. */ |
| 1077 | if (args->offset > obj->base.size || |
| 1078 | args->size > obj->base.size - args->offset) { |
| 1079 | ret = -EINVAL; |
| 1080 | goto out; |
| 1081 | } |
| 1082 | |
| 1083 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1084 | * pages from. |
| 1085 | */ |
| 1086 | if (!obj->base.filp) { |
| 1087 | ret = -EINVAL; |
| 1088 | goto out; |
| 1089 | } |
| 1090 | |
| 1091 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1092 | |
| 1093 | ret = -EFAULT; |
| 1094 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1095 | * it would end up going through the fenced access, and we'll get |
| 1096 | * different detiling behavior between reading and writing. |
| 1097 | * pread/pwrite currently are reading and writing from the CPU |
| 1098 | * perspective, requiring manual detiling by the client. |
| 1099 | */ |
| 1100 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1101 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1102 | cpu_write_needs_clflush(obj)) { |
| 1103 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1104 | /* Note that the gtt paths might fail with non-page-backed user |
| 1105 | * pointers (e.g. gtt mappings when moving data between |
| 1106 | * textures). Fallback to the shmem path in that case. */ |
| 1107 | } |
| 1108 | |
| 1109 | if (ret == -EFAULT || ret == -ENOSPC) { |
| 1110 | if (obj->phys_handle) |
| 1111 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1112 | else |
| 1113 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1114 | } |
| 1115 | |
| 1116 | out: |
| 1117 | drm_gem_object_unreference(&obj->base); |
| 1118 | unlock: |
| 1119 | mutex_unlock(&dev->struct_mutex); |
| 1120 | put_rpm: |
| 1121 | intel_runtime_pm_put(dev_priv); |
| 1122 | |
| 1123 | return ret; |
| 1124 | } |
| 1125 | |
| 1126 | int |
| 1127 | i915_gem_check_wedge(struct i915_gpu_error *error, |
| 1128 | bool interruptible) |
| 1129 | { |
| 1130 | if (i915_reset_in_progress(error)) { |
| 1131 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1132 | * -EIO unconditionally for these. */ |
| 1133 | if (!interruptible) |
| 1134 | return -EIO; |
| 1135 | |
| 1136 | /* Recovery complete, but the reset failed ... */ |
| 1137 | if (i915_terminally_wedged(error)) |
| 1138 | return -EIO; |
| 1139 | |
| 1140 | /* |
| 1141 | * Check if GPU Reset is in progress - we need intel_ring_begin |
| 1142 | * to work properly to reinit the hw state while the gpu is |
| 1143 | * still marked as reset-in-progress. Handle this with a flag. |
| 1144 | */ |
| 1145 | if (!error->reload_in_reset) |
| 1146 | return -EAGAIN; |
| 1147 | } |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | /* |
| 1153 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
| 1154 | */ |
| 1155 | int |
| 1156 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
| 1157 | { |
| 1158 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
| 1159 | |
| 1160 | if (req == req->ring->outstanding_lazy_request) |
| 1161 | i915_add_request(req->ring); |
| 1162 | |
| 1163 | return 0; |
| 1164 | } |
| 1165 | |
| 1166 | static void fake_irq(unsigned long data) |
| 1167 | { |
| 1168 | wake_up_process((struct task_struct *)data); |
| 1169 | } |
| 1170 | |
| 1171 | static bool missed_irq(struct drm_i915_private *dev_priv, |
| 1172 | struct intel_engine_cs *ring) |
| 1173 | { |
| 1174 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
| 1175 | } |
| 1176 | |
| 1177 | static int __i915_spin_request(struct drm_i915_gem_request *req) |
| 1178 | { |
| 1179 | unsigned long timeout; |
| 1180 | |
| 1181 | if (i915_gem_request_get_ring(req)->irq_refcount) |
| 1182 | return -EBUSY; |
| 1183 | |
| 1184 | timeout = jiffies + 1; |
| 1185 | while (!need_resched()) { |
| 1186 | if (i915_gem_request_completed(req, true)) |
| 1187 | return 0; |
| 1188 | |
| 1189 | if (time_after_eq(jiffies, timeout)) |
| 1190 | break; |
| 1191 | |
| 1192 | cpu_relax_lowlatency(); |
| 1193 | } |
| 1194 | if (i915_gem_request_completed(req, false)) |
| 1195 | return 0; |
| 1196 | |
| 1197 | return -EAGAIN; |
| 1198 | } |
| 1199 | |
| 1200 | /** |
| 1201 | * __i915_wait_request - wait until execution of request has finished |
| 1202 | * @req: duh! |
| 1203 | * @reset_counter: reset sequence associated with the given request |
| 1204 | * @interruptible: do an interruptible wait (normally yes) |
| 1205 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1206 | * |
| 1207 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1208 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1209 | * locks are involved, it is sufficient to read the reset_counter before |
| 1210 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1211 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1212 | * inserted. |
| 1213 | * |
| 1214 | * Returns 0 if the request was found within the alloted time. Else returns the |
| 1215 | * errno with remaining time filled in timeout argument. |
| 1216 | */ |
| 1217 | int __i915_wait_request(struct drm_i915_gem_request *req, |
| 1218 | unsigned reset_counter, |
| 1219 | bool interruptible, |
| 1220 | s64 *timeout, |
| 1221 | struct intel_rps_client *rps) |
| 1222 | { |
| 1223 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
| 1224 | struct drm_device *dev = ring->dev; |
| 1225 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1226 | const bool irq_test_in_progress = |
| 1227 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
| 1228 | DEFINE_WAIT(wait); |
| 1229 | unsigned long timeout_expire; |
| 1230 | s64 before, now; |
| 1231 | int ret; |
| 1232 | |
| 1233 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
| 1234 | |
| 1235 | if (list_empty(&req->list)) |
| 1236 | return 0; |
| 1237 | |
| 1238 | if (i915_gem_request_completed(req, true)) |
| 1239 | return 0; |
| 1240 | |
| 1241 | timeout_expire = timeout ? |
| 1242 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; |
| 1243 | |
| 1244 | if (INTEL_INFO(dev_priv)->gen >= 6) |
| 1245 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
| 1246 | |
| 1247 | /* Record current time in case interrupted by signal, or wedged */ |
| 1248 | trace_i915_gem_request_wait_begin(req); |
| 1249 | before = ktime_get_raw_ns(); |
| 1250 | |
| 1251 | /* Optimistic spin for the next jiffie before touching IRQs */ |
| 1252 | ret = __i915_spin_request(req); |
| 1253 | if (ret == 0) |
| 1254 | goto out; |
| 1255 | |
| 1256 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { |
| 1257 | ret = -ENODEV; |
| 1258 | goto out; |
| 1259 | } |
| 1260 | |
| 1261 | for (;;) { |
| 1262 | struct timer_list timer; |
| 1263 | |
| 1264 | prepare_to_wait(&ring->irq_queue, &wait, |
| 1265 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
| 1266 | |
| 1267 | /* We need to check whether any gpu reset happened in between |
| 1268 | * the caller grabbing the seqno and now ... */ |
| 1269 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
| 1270 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
| 1271 | * is truely gone. */ |
| 1272 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1273 | if (ret == 0) |
| 1274 | ret = -EAGAIN; |
| 1275 | break; |
| 1276 | } |
| 1277 | |
| 1278 | if (i915_gem_request_completed(req, false)) { |
| 1279 | ret = 0; |
| 1280 | break; |
| 1281 | } |
| 1282 | |
| 1283 | if (interruptible && signal_pending(current)) { |
| 1284 | ret = -ERESTARTSYS; |
| 1285 | break; |
| 1286 | } |
| 1287 | |
| 1288 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
| 1289 | ret = -ETIME; |
| 1290 | break; |
| 1291 | } |
| 1292 | |
| 1293 | timer.function = NULL; |
| 1294 | if (timeout || missed_irq(dev_priv, ring)) { |
| 1295 | unsigned long expire; |
| 1296 | |
| 1297 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
| 1298 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
| 1299 | mod_timer(&timer, expire); |
| 1300 | } |
| 1301 | |
| 1302 | io_schedule(); |
| 1303 | |
| 1304 | if (timer.function) { |
| 1305 | del_singleshot_timer_sync(&timer); |
| 1306 | destroy_timer_on_stack(&timer); |
| 1307 | } |
| 1308 | } |
| 1309 | if (!irq_test_in_progress) |
| 1310 | ring->irq_put(ring); |
| 1311 | |
| 1312 | finish_wait(&ring->irq_queue, &wait); |
| 1313 | |
| 1314 | out: |
| 1315 | now = ktime_get_raw_ns(); |
| 1316 | trace_i915_gem_request_wait_end(req); |
| 1317 | |
| 1318 | if (timeout) { |
| 1319 | s64 tres = *timeout - (now - before); |
| 1320 | |
| 1321 | *timeout = tres < 0 ? 0 : tres; |
| 1322 | |
| 1323 | /* |
| 1324 | * Apparently ktime isn't accurate enough and occasionally has a |
| 1325 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch |
| 1326 | * things up to make the test happy. We allow up to 1 jiffy. |
| 1327 | * |
| 1328 | * This is a regrssion from the timespec->ktime conversion. |
| 1329 | */ |
| 1330 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) |
| 1331 | *timeout = 0; |
| 1332 | } |
| 1333 | |
| 1334 | return ret; |
| 1335 | } |
| 1336 | |
| 1337 | static inline void |
| 1338 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
| 1339 | { |
| 1340 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1341 | |
| 1342 | if (!file_priv) |
| 1343 | return; |
| 1344 | |
| 1345 | spin_lock(&file_priv->mm.lock); |
| 1346 | list_del(&request->client_list); |
| 1347 | request->file_priv = NULL; |
| 1348 | spin_unlock(&file_priv->mm.lock); |
| 1349 | } |
| 1350 | |
| 1351 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
| 1352 | { |
| 1353 | trace_i915_gem_request_retire(request); |
| 1354 | |
| 1355 | /* We know the GPU must have read the request to have |
| 1356 | * sent us the seqno + interrupt, so use the position |
| 1357 | * of tail of the request to update the last known position |
| 1358 | * of the GPU head. |
| 1359 | * |
| 1360 | * Note this requires that we are always called in request |
| 1361 | * completion order. |
| 1362 | */ |
| 1363 | request->ringbuf->last_retired_head = request->postfix; |
| 1364 | |
| 1365 | list_del_init(&request->list); |
| 1366 | i915_gem_request_remove_from_client(request); |
| 1367 | |
| 1368 | put_pid(request->pid); |
| 1369 | |
| 1370 | i915_gem_request_unreference(request); |
| 1371 | } |
| 1372 | |
| 1373 | static void |
| 1374 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) |
| 1375 | { |
| 1376 | struct intel_engine_cs *engine = req->ring; |
| 1377 | struct drm_i915_gem_request *tmp; |
| 1378 | |
| 1379 | lockdep_assert_held(&engine->dev->struct_mutex); |
| 1380 | |
| 1381 | if (list_empty(&req->list)) |
| 1382 | return; |
| 1383 | |
| 1384 | do { |
| 1385 | tmp = list_first_entry(&engine->request_list, |
| 1386 | typeof(*tmp), list); |
| 1387 | |
| 1388 | i915_gem_request_retire(tmp); |
| 1389 | } while (tmp != req); |
| 1390 | |
| 1391 | WARN_ON(i915_verify_lists(engine->dev)); |
| 1392 | } |
| 1393 | |
| 1394 | /** |
| 1395 | * Waits for a request to be signaled, and cleans up the |
| 1396 | * request and object lists appropriately for that event. |
| 1397 | */ |
| 1398 | int |
| 1399 | i915_wait_request(struct drm_i915_gem_request *req) |
| 1400 | { |
| 1401 | struct drm_device *dev; |
| 1402 | struct drm_i915_private *dev_priv; |
| 1403 | bool interruptible; |
| 1404 | int ret; |
| 1405 | |
| 1406 | BUG_ON(req == NULL); |
| 1407 | |
| 1408 | dev = req->ring->dev; |
| 1409 | dev_priv = dev->dev_private; |
| 1410 | interruptible = dev_priv->mm.interruptible; |
| 1411 | |
| 1412 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1413 | |
| 1414 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1415 | if (ret) |
| 1416 | return ret; |
| 1417 | |
| 1418 | ret = i915_gem_check_olr(req); |
| 1419 | if (ret) |
| 1420 | return ret; |
| 1421 | |
| 1422 | ret = __i915_wait_request(req, |
| 1423 | atomic_read(&dev_priv->gpu_error.reset_counter), |
| 1424 | interruptible, NULL, NULL); |
| 1425 | if (ret) |
| 1426 | return ret; |
| 1427 | |
| 1428 | __i915_gem_request_retire__upto(req); |
| 1429 | return 0; |
| 1430 | } |
| 1431 | |
| 1432 | /** |
| 1433 | * Ensures that all rendering to the object has completed and the object is |
| 1434 | * safe to unbind from the GTT or access from the CPU. |
| 1435 | */ |
| 1436 | int |
| 1437 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1438 | bool readonly) |
| 1439 | { |
| 1440 | int ret, i; |
| 1441 | |
| 1442 | if (!obj->active) |
| 1443 | return 0; |
| 1444 | |
| 1445 | if (readonly) { |
| 1446 | if (obj->last_write_req != NULL) { |
| 1447 | ret = i915_wait_request(obj->last_write_req); |
| 1448 | if (ret) |
| 1449 | return ret; |
| 1450 | |
| 1451 | i = obj->last_write_req->ring->id; |
| 1452 | if (obj->last_read_req[i] == obj->last_write_req) |
| 1453 | i915_gem_object_retire__read(obj, i); |
| 1454 | else |
| 1455 | i915_gem_object_retire__write(obj); |
| 1456 | } |
| 1457 | } else { |
| 1458 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1459 | if (obj->last_read_req[i] == NULL) |
| 1460 | continue; |
| 1461 | |
| 1462 | ret = i915_wait_request(obj->last_read_req[i]); |
| 1463 | if (ret) |
| 1464 | return ret; |
| 1465 | |
| 1466 | i915_gem_object_retire__read(obj, i); |
| 1467 | } |
| 1468 | RQ_BUG_ON(obj->active); |
| 1469 | } |
| 1470 | |
| 1471 | return 0; |
| 1472 | } |
| 1473 | |
| 1474 | static void |
| 1475 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, |
| 1476 | struct drm_i915_gem_request *req) |
| 1477 | { |
| 1478 | int ring = req->ring->id; |
| 1479 | |
| 1480 | if (obj->last_read_req[ring] == req) |
| 1481 | i915_gem_object_retire__read(obj, ring); |
| 1482 | else if (obj->last_write_req == req) |
| 1483 | i915_gem_object_retire__write(obj); |
| 1484 | |
| 1485 | __i915_gem_request_retire__upto(req); |
| 1486 | } |
| 1487 | |
| 1488 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1489 | * as the object state may change during this call. |
| 1490 | */ |
| 1491 | static __must_check int |
| 1492 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1493 | struct intel_rps_client *rps, |
| 1494 | bool readonly) |
| 1495 | { |
| 1496 | struct drm_device *dev = obj->base.dev; |
| 1497 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1498 | struct drm_i915_gem_request *requests[I915_NUM_RINGS]; |
| 1499 | unsigned reset_counter; |
| 1500 | int ret, i, n = 0; |
| 1501 | |
| 1502 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1503 | BUG_ON(!dev_priv->mm.interruptible); |
| 1504 | |
| 1505 | if (!obj->active) |
| 1506 | return 0; |
| 1507 | |
| 1508 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
| 1509 | if (ret) |
| 1510 | return ret; |
| 1511 | |
| 1512 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 1513 | |
| 1514 | if (readonly) { |
| 1515 | struct drm_i915_gem_request *req; |
| 1516 | |
| 1517 | req = obj->last_write_req; |
| 1518 | if (req == NULL) |
| 1519 | return 0; |
| 1520 | |
| 1521 | ret = i915_gem_check_olr(req); |
| 1522 | if (ret) |
| 1523 | goto err; |
| 1524 | |
| 1525 | requests[n++] = i915_gem_request_reference(req); |
| 1526 | } else { |
| 1527 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1528 | struct drm_i915_gem_request *req; |
| 1529 | |
| 1530 | req = obj->last_read_req[i]; |
| 1531 | if (req == NULL) |
| 1532 | continue; |
| 1533 | |
| 1534 | ret = i915_gem_check_olr(req); |
| 1535 | if (ret) |
| 1536 | goto err; |
| 1537 | |
| 1538 | requests[n++] = i915_gem_request_reference(req); |
| 1539 | } |
| 1540 | } |
| 1541 | |
| 1542 | mutex_unlock(&dev->struct_mutex); |
| 1543 | for (i = 0; ret == 0 && i < n; i++) |
| 1544 | ret = __i915_wait_request(requests[i], reset_counter, true, |
| 1545 | NULL, rps); |
| 1546 | mutex_lock(&dev->struct_mutex); |
| 1547 | |
| 1548 | err: |
| 1549 | for (i = 0; i < n; i++) { |
| 1550 | if (ret == 0) |
| 1551 | i915_gem_object_retire_request(obj, requests[i]); |
| 1552 | i915_gem_request_unreference(requests[i]); |
| 1553 | } |
| 1554 | |
| 1555 | return ret; |
| 1556 | } |
| 1557 | |
| 1558 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
| 1559 | { |
| 1560 | struct drm_i915_file_private *fpriv = file->driver_priv; |
| 1561 | return &fpriv->rps; |
| 1562 | } |
| 1563 | |
| 1564 | /** |
| 1565 | * Called when user space prepares to use an object with the CPU, either |
| 1566 | * through the mmap ioctl's mapping or a GTT mapping. |
| 1567 | */ |
| 1568 | int |
| 1569 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1570 | struct drm_file *file) |
| 1571 | { |
| 1572 | struct drm_i915_gem_set_domain *args = data; |
| 1573 | struct drm_i915_gem_object *obj; |
| 1574 | uint32_t read_domains = args->read_domains; |
| 1575 | uint32_t write_domain = args->write_domain; |
| 1576 | int ret; |
| 1577 | |
| 1578 | /* Only handle setting domains to types used by the CPU. */ |
| 1579 | if (write_domain & I915_GEM_GPU_DOMAINS) |
| 1580 | return -EINVAL; |
| 1581 | |
| 1582 | if (read_domains & I915_GEM_GPU_DOMAINS) |
| 1583 | return -EINVAL; |
| 1584 | |
| 1585 | /* Having something in the write domain implies it's in the read |
| 1586 | * domain, and only that read domain. Enforce that in the request. |
| 1587 | */ |
| 1588 | if (write_domain != 0 && read_domains != write_domain) |
| 1589 | return -EINVAL; |
| 1590 | |
| 1591 | ret = i915_mutex_lock_interruptible(dev); |
| 1592 | if (ret) |
| 1593 | return ret; |
| 1594 | |
| 1595 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1596 | if (&obj->base == NULL) { |
| 1597 | ret = -ENOENT; |
| 1598 | goto unlock; |
| 1599 | } |
| 1600 | |
| 1601 | /* Try to flush the object off the GPU without holding the lock. |
| 1602 | * We will repeat the flush holding the lock in the normal manner |
| 1603 | * to catch cases where we are gazumped. |
| 1604 | */ |
| 1605 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
| 1606 | to_rps_client(file), |
| 1607 | !write_domain); |
| 1608 | if (ret) |
| 1609 | goto unref; |
| 1610 | |
| 1611 | if (read_domains & I915_GEM_DOMAIN_GTT) |
| 1612 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
| 1613 | else |
| 1614 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
| 1615 | |
| 1616 | unref: |
| 1617 | drm_gem_object_unreference(&obj->base); |
| 1618 | unlock: |
| 1619 | mutex_unlock(&dev->struct_mutex); |
| 1620 | return ret; |
| 1621 | } |
| 1622 | |
| 1623 | /** |
| 1624 | * Called when user space has done writes to this buffer |
| 1625 | */ |
| 1626 | int |
| 1627 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1628 | struct drm_file *file) |
| 1629 | { |
| 1630 | struct drm_i915_gem_sw_finish *args = data; |
| 1631 | struct drm_i915_gem_object *obj; |
| 1632 | int ret = 0; |
| 1633 | |
| 1634 | ret = i915_mutex_lock_interruptible(dev); |
| 1635 | if (ret) |
| 1636 | return ret; |
| 1637 | |
| 1638 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 1639 | if (&obj->base == NULL) { |
| 1640 | ret = -ENOENT; |
| 1641 | goto unlock; |
| 1642 | } |
| 1643 | |
| 1644 | /* Pinned buffers may be scanout, so flush the cache */ |
| 1645 | if (obj->pin_display) |
| 1646 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1647 | |
| 1648 | drm_gem_object_unreference(&obj->base); |
| 1649 | unlock: |
| 1650 | mutex_unlock(&dev->struct_mutex); |
| 1651 | return ret; |
| 1652 | } |
| 1653 | |
| 1654 | /** |
| 1655 | * Maps the contents of an object, returning the address it is mapped |
| 1656 | * into. |
| 1657 | * |
| 1658 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1659 | * imply a ref on the object itself. |
| 1660 | * |
| 1661 | * IMPORTANT: |
| 1662 | * |
| 1663 | * DRM driver writers who look a this function as an example for how to do GEM |
| 1664 | * mmap support, please don't implement mmap support like here. The modern way |
| 1665 | * to implement DRM mmap support is with an mmap offset ioctl (like |
| 1666 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
| 1667 | * That way debug tooling like valgrind will understand what's going on, hiding |
| 1668 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
| 1669 | * does cpu mmaps this way because we didn't know better. |
| 1670 | */ |
| 1671 | int |
| 1672 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1673 | struct drm_file *file) |
| 1674 | { |
| 1675 | struct drm_i915_gem_mmap *args = data; |
| 1676 | struct drm_gem_object *obj; |
| 1677 | unsigned long addr; |
| 1678 | |
| 1679 | if (args->flags & ~(I915_MMAP_WC)) |
| 1680 | return -EINVAL; |
| 1681 | |
| 1682 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) |
| 1683 | return -ENODEV; |
| 1684 | |
| 1685 | obj = drm_gem_object_lookup(dev, file, args->handle); |
| 1686 | if (obj == NULL) |
| 1687 | return -ENOENT; |
| 1688 | |
| 1689 | /* prime objects have no backing filp to GEM mmap |
| 1690 | * pages from. |
| 1691 | */ |
| 1692 | if (!obj->filp) { |
| 1693 | drm_gem_object_unreference_unlocked(obj); |
| 1694 | return -EINVAL; |
| 1695 | } |
| 1696 | |
| 1697 | addr = vm_mmap(obj->filp, 0, args->size, |
| 1698 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1699 | args->offset); |
| 1700 | if (args->flags & I915_MMAP_WC) { |
| 1701 | struct mm_struct *mm = current->mm; |
| 1702 | struct vm_area_struct *vma; |
| 1703 | |
| 1704 | down_write(&mm->mmap_sem); |
| 1705 | vma = find_vma(mm, addr); |
| 1706 | if (vma) |
| 1707 | vma->vm_page_prot = |
| 1708 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); |
| 1709 | else |
| 1710 | addr = -ENOMEM; |
| 1711 | up_write(&mm->mmap_sem); |
| 1712 | } |
| 1713 | drm_gem_object_unreference_unlocked(obj); |
| 1714 | if (IS_ERR((void *)addr)) |
| 1715 | return addr; |
| 1716 | |
| 1717 | args->addr_ptr = (uint64_t) addr; |
| 1718 | |
| 1719 | return 0; |
| 1720 | } |
| 1721 | |
| 1722 | /** |
| 1723 | * i915_gem_fault - fault a page into the GTT |
| 1724 | * vma: VMA in question |
| 1725 | * vmf: fault info |
| 1726 | * |
| 1727 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1728 | * from userspace. The fault handler takes care of binding the object to |
| 1729 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1730 | * only if needed based on whether the old reg is still valid or the object |
| 1731 | * is tiled) and inserting a new PTE into the faulting process. |
| 1732 | * |
| 1733 | * Note that the faulting process may involve evicting existing objects |
| 1734 | * from the GTT and/or fence registers to make room. So performance may |
| 1735 | * suffer if the GTT working set is large or there are few fence registers |
| 1736 | * left. |
| 1737 | */ |
| 1738 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1739 | { |
| 1740 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1741 | struct drm_device *dev = obj->base.dev; |
| 1742 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1743 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
| 1744 | pgoff_t page_offset; |
| 1745 | unsigned long pfn; |
| 1746 | int ret = 0; |
| 1747 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
| 1748 | |
| 1749 | intel_runtime_pm_get(dev_priv); |
| 1750 | |
| 1751 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1752 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1753 | PAGE_SHIFT; |
| 1754 | |
| 1755 | ret = i915_mutex_lock_interruptible(dev); |
| 1756 | if (ret) |
| 1757 | goto out; |
| 1758 | |
| 1759 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1760 | |
| 1761 | /* Try to flush the object off the GPU first without holding the lock. |
| 1762 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1763 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1764 | * where we are gazumped. |
| 1765 | */ |
| 1766 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1767 | if (ret) |
| 1768 | goto unlock; |
| 1769 | |
| 1770 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1771 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1772 | ret = -EFAULT; |
| 1773 | goto unlock; |
| 1774 | } |
| 1775 | |
| 1776 | /* Use a partial view if the object is bigger than the aperture. */ |
| 1777 | if (obj->base.size >= dev_priv->gtt.mappable_end && |
| 1778 | obj->tiling_mode == I915_TILING_NONE) { |
| 1779 | static const unsigned int chunk_size = 256; // 1 MiB |
| 1780 | |
| 1781 | memset(&view, 0, sizeof(view)); |
| 1782 | view.type = I915_GGTT_VIEW_PARTIAL; |
| 1783 | view.params.partial.offset = rounddown(page_offset, chunk_size); |
| 1784 | view.params.partial.size = |
| 1785 | min_t(unsigned int, |
| 1786 | chunk_size, |
| 1787 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - |
| 1788 | view.params.partial.offset); |
| 1789 | } |
| 1790 | |
| 1791 | /* Now pin it into the GTT if needed */ |
| 1792 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); |
| 1793 | if (ret) |
| 1794 | goto unlock; |
| 1795 | |
| 1796 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1797 | if (ret) |
| 1798 | goto unpin; |
| 1799 | |
| 1800 | ret = i915_gem_object_get_fence(obj); |
| 1801 | if (ret) |
| 1802 | goto unpin; |
| 1803 | |
| 1804 | /* Finally, remap it using the new GTT offset */ |
| 1805 | pfn = dev_priv->gtt.mappable_base + |
| 1806 | i915_gem_obj_ggtt_offset_view(obj, &view); |
| 1807 | pfn >>= PAGE_SHIFT; |
| 1808 | |
| 1809 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
| 1810 | /* Overriding existing pages in partial view does not cause |
| 1811 | * us any trouble as TLBs are still valid because the fault |
| 1812 | * is due to userspace losing part of the mapping or never |
| 1813 | * having accessed it before (at this partials' range). |
| 1814 | */ |
| 1815 | unsigned long base = vma->vm_start + |
| 1816 | (view.params.partial.offset << PAGE_SHIFT); |
| 1817 | unsigned int i; |
| 1818 | |
| 1819 | for (i = 0; i < view.params.partial.size; i++) { |
| 1820 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); |
| 1821 | if (ret) |
| 1822 | break; |
| 1823 | } |
| 1824 | |
| 1825 | obj->fault_mappable = true; |
| 1826 | } else { |
| 1827 | if (!obj->fault_mappable) { |
| 1828 | unsigned long size = min_t(unsigned long, |
| 1829 | vma->vm_end - vma->vm_start, |
| 1830 | obj->base.size); |
| 1831 | int i; |
| 1832 | |
| 1833 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
| 1834 | ret = vm_insert_pfn(vma, |
| 1835 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1836 | pfn + i); |
| 1837 | if (ret) |
| 1838 | break; |
| 1839 | } |
| 1840 | |
| 1841 | obj->fault_mappable = true; |
| 1842 | } else |
| 1843 | ret = vm_insert_pfn(vma, |
| 1844 | (unsigned long)vmf->virtual_address, |
| 1845 | pfn + page_offset); |
| 1846 | } |
| 1847 | unpin: |
| 1848 | i915_gem_object_ggtt_unpin_view(obj, &view); |
| 1849 | unlock: |
| 1850 | mutex_unlock(&dev->struct_mutex); |
| 1851 | out: |
| 1852 | switch (ret) { |
| 1853 | case -EIO: |
| 1854 | /* |
| 1855 | * We eat errors when the gpu is terminally wedged to avoid |
| 1856 | * userspace unduly crashing (gl has no provisions for mmaps to |
| 1857 | * fail). But any other -EIO isn't ours (e.g. swap in failure) |
| 1858 | * and so needs to be reported. |
| 1859 | */ |
| 1860 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
| 1861 | ret = VM_FAULT_SIGBUS; |
| 1862 | break; |
| 1863 | } |
| 1864 | case -EAGAIN: |
| 1865 | /* |
| 1866 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1867 | * handler to reset everything when re-faulting in |
| 1868 | * i915_mutex_lock_interruptible. |
| 1869 | */ |
| 1870 | case 0: |
| 1871 | case -ERESTARTSYS: |
| 1872 | case -EINTR: |
| 1873 | case -EBUSY: |
| 1874 | /* |
| 1875 | * EBUSY is ok: this just means that another thread |
| 1876 | * already did the job. |
| 1877 | */ |
| 1878 | ret = VM_FAULT_NOPAGE; |
| 1879 | break; |
| 1880 | case -ENOMEM: |
| 1881 | ret = VM_FAULT_OOM; |
| 1882 | break; |
| 1883 | case -ENOSPC: |
| 1884 | case -EFAULT: |
| 1885 | ret = VM_FAULT_SIGBUS; |
| 1886 | break; |
| 1887 | default: |
| 1888 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
| 1889 | ret = VM_FAULT_SIGBUS; |
| 1890 | break; |
| 1891 | } |
| 1892 | |
| 1893 | intel_runtime_pm_put(dev_priv); |
| 1894 | return ret; |
| 1895 | } |
| 1896 | |
| 1897 | /** |
| 1898 | * i915_gem_release_mmap - remove physical page mappings |
| 1899 | * @obj: obj in question |
| 1900 | * |
| 1901 | * Preserve the reservation of the mmapping with the DRM core code, but |
| 1902 | * relinquish ownership of the pages back to the system. |
| 1903 | * |
| 1904 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1905 | * object through the GTT and then lose the fence register due to |
| 1906 | * resource pressure. Similarly if the object has been moved out of the |
| 1907 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1908 | * mapping will then trigger a page fault on the next user access, allowing |
| 1909 | * fixup by i915_gem_fault(). |
| 1910 | */ |
| 1911 | void |
| 1912 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
| 1913 | { |
| 1914 | if (!obj->fault_mappable) |
| 1915 | return; |
| 1916 | |
| 1917 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1918 | obj->base.dev->anon_inode->i_mapping); |
| 1919 | obj->fault_mappable = false; |
| 1920 | } |
| 1921 | |
| 1922 | void |
| 1923 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1924 | { |
| 1925 | struct drm_i915_gem_object *obj; |
| 1926 | |
| 1927 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1928 | i915_gem_release_mmap(obj); |
| 1929 | } |
| 1930 | |
| 1931 | uint32_t |
| 1932 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
| 1933 | { |
| 1934 | uint32_t gtt_size; |
| 1935 | |
| 1936 | if (INTEL_INFO(dev)->gen >= 4 || |
| 1937 | tiling_mode == I915_TILING_NONE) |
| 1938 | return size; |
| 1939 | |
| 1940 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1941 | if (INTEL_INFO(dev)->gen == 3) |
| 1942 | gtt_size = 1024*1024; |
| 1943 | else |
| 1944 | gtt_size = 512*1024; |
| 1945 | |
| 1946 | while (gtt_size < size) |
| 1947 | gtt_size <<= 1; |
| 1948 | |
| 1949 | return gtt_size; |
| 1950 | } |
| 1951 | |
| 1952 | /** |
| 1953 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1954 | * @obj: object to check |
| 1955 | * |
| 1956 | * Return the required GTT alignment for an object, taking into account |
| 1957 | * potential fence register mapping. |
| 1958 | */ |
| 1959 | uint32_t |
| 1960 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1961 | int tiling_mode, bool fenced) |
| 1962 | { |
| 1963 | /* |
| 1964 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1965 | * if a fence register is needed for the object. |
| 1966 | */ |
| 1967 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
| 1968 | tiling_mode == I915_TILING_NONE) |
| 1969 | return 4096; |
| 1970 | |
| 1971 | /* |
| 1972 | * Previous chips need to be aligned to the size of the smallest |
| 1973 | * fence register that can contain the object. |
| 1974 | */ |
| 1975 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
| 1976 | } |
| 1977 | |
| 1978 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1979 | { |
| 1980 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1981 | int ret; |
| 1982 | |
| 1983 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
| 1984 | return 0; |
| 1985 | |
| 1986 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1987 | |
| 1988 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1989 | if (ret != -ENOSPC) |
| 1990 | goto out; |
| 1991 | |
| 1992 | /* Badly fragmented mmap space? The only way we can recover |
| 1993 | * space is by destroying unwanted objects. We can't randomly release |
| 1994 | * mmap_offsets as userspace expects them to be persistent for the |
| 1995 | * lifetime of the objects. The closest we can is to release the |
| 1996 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1997 | * which prevents userspace from ever using that object again. |
| 1998 | */ |
| 1999 | i915_gem_shrink(dev_priv, |
| 2000 | obj->base.size >> PAGE_SHIFT, |
| 2001 | I915_SHRINK_BOUND | |
| 2002 | I915_SHRINK_UNBOUND | |
| 2003 | I915_SHRINK_PURGEABLE); |
| 2004 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2005 | if (ret != -ENOSPC) |
| 2006 | goto out; |
| 2007 | |
| 2008 | i915_gem_shrink_all(dev_priv); |
| 2009 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2010 | out: |
| 2011 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 2012 | |
| 2013 | return ret; |
| 2014 | } |
| 2015 | |
| 2016 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 2017 | { |
| 2018 | drm_gem_free_mmap_offset(&obj->base); |
| 2019 | } |
| 2020 | |
| 2021 | int |
| 2022 | i915_gem_mmap_gtt(struct drm_file *file, |
| 2023 | struct drm_device *dev, |
| 2024 | uint32_t handle, |
| 2025 | uint64_t *offset) |
| 2026 | { |
| 2027 | struct drm_i915_gem_object *obj; |
| 2028 | int ret; |
| 2029 | |
| 2030 | ret = i915_mutex_lock_interruptible(dev); |
| 2031 | if (ret) |
| 2032 | return ret; |
| 2033 | |
| 2034 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
| 2035 | if (&obj->base == NULL) { |
| 2036 | ret = -ENOENT; |
| 2037 | goto unlock; |
| 2038 | } |
| 2039 | |
| 2040 | if (obj->madv != I915_MADV_WILLNEED) { |
| 2041 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
| 2042 | ret = -EFAULT; |
| 2043 | goto out; |
| 2044 | } |
| 2045 | |
| 2046 | ret = i915_gem_object_create_mmap_offset(obj); |
| 2047 | if (ret) |
| 2048 | goto out; |
| 2049 | |
| 2050 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
| 2051 | |
| 2052 | out: |
| 2053 | drm_gem_object_unreference(&obj->base); |
| 2054 | unlock: |
| 2055 | mutex_unlock(&dev->struct_mutex); |
| 2056 | return ret; |
| 2057 | } |
| 2058 | |
| 2059 | /** |
| 2060 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 2061 | * @dev: DRM device |
| 2062 | * @data: GTT mapping ioctl data |
| 2063 | * @file: GEM object info |
| 2064 | * |
| 2065 | * Simply returns the fake offset to userspace so it can mmap it. |
| 2066 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 2067 | * up so we can get faults in the handler above. |
| 2068 | * |
| 2069 | * The fault handler will take care of binding the object into the GTT |
| 2070 | * (since it may have been evicted to make room for something), allocating |
| 2071 | * a fence register, and mapping the appropriate aperture address into |
| 2072 | * userspace. |
| 2073 | */ |
| 2074 | int |
| 2075 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2076 | struct drm_file *file) |
| 2077 | { |
| 2078 | struct drm_i915_gem_mmap_gtt *args = data; |
| 2079 | |
| 2080 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 2081 | } |
| 2082 | |
| 2083 | /* Immediately discard the backing storage */ |
| 2084 | static void |
| 2085 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
| 2086 | { |
| 2087 | i915_gem_object_free_mmap_offset(obj); |
| 2088 | |
| 2089 | if (obj->base.filp == NULL) |
| 2090 | return; |
| 2091 | |
| 2092 | /* Our goal here is to return as much of the memory as |
| 2093 | * is possible back to the system as we are called from OOM. |
| 2094 | * To do this we must instruct the shmfs to drop all of its |
| 2095 | * backing pages, *now*. |
| 2096 | */ |
| 2097 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
| 2098 | obj->madv = __I915_MADV_PURGED; |
| 2099 | } |
| 2100 | |
| 2101 | /* Try to discard unwanted pages */ |
| 2102 | static void |
| 2103 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
| 2104 | { |
| 2105 | struct address_space *mapping; |
| 2106 | |
| 2107 | switch (obj->madv) { |
| 2108 | case I915_MADV_DONTNEED: |
| 2109 | i915_gem_object_truncate(obj); |
| 2110 | case __I915_MADV_PURGED: |
| 2111 | return; |
| 2112 | } |
| 2113 | |
| 2114 | if (obj->base.filp == NULL) |
| 2115 | return; |
| 2116 | |
| 2117 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 2118 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
| 2119 | } |
| 2120 | |
| 2121 | static void |
| 2122 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
| 2123 | { |
| 2124 | struct sg_page_iter sg_iter; |
| 2125 | int ret; |
| 2126 | |
| 2127 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 2128 | |
| 2129 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 2130 | if (ret) { |
| 2131 | /* In the event of a disaster, abandon all caches and |
| 2132 | * hope for the best. |
| 2133 | */ |
| 2134 | WARN_ON(ret != -EIO); |
| 2135 | i915_gem_clflush_object(obj, true); |
| 2136 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2137 | } |
| 2138 | |
| 2139 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2140 | i915_gem_object_save_bit_17_swizzle(obj); |
| 2141 | |
| 2142 | if (obj->madv == I915_MADV_DONTNEED) |
| 2143 | obj->dirty = 0; |
| 2144 | |
| 2145 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
| 2146 | struct page *page = sg_page_iter_page(&sg_iter); |
| 2147 | |
| 2148 | if (obj->dirty) |
| 2149 | set_page_dirty(page); |
| 2150 | |
| 2151 | if (obj->madv == I915_MADV_WILLNEED) |
| 2152 | mark_page_accessed(page); |
| 2153 | |
| 2154 | page_cache_release(page); |
| 2155 | } |
| 2156 | obj->dirty = 0; |
| 2157 | |
| 2158 | sg_free_table(obj->pages); |
| 2159 | kfree(obj->pages); |
| 2160 | } |
| 2161 | |
| 2162 | int |
| 2163 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 2164 | { |
| 2165 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2166 | |
| 2167 | if (obj->pages == NULL) |
| 2168 | return 0; |
| 2169 | |
| 2170 | if (obj->pages_pin_count) |
| 2171 | return -EBUSY; |
| 2172 | |
| 2173 | BUG_ON(i915_gem_obj_bound_any(obj)); |
| 2174 | |
| 2175 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 2176 | * array, hence protect them from being reaped by removing them from gtt |
| 2177 | * lists early. */ |
| 2178 | list_del(&obj->global_list); |
| 2179 | |
| 2180 | ops->put_pages(obj); |
| 2181 | obj->pages = NULL; |
| 2182 | |
| 2183 | i915_gem_object_invalidate(obj); |
| 2184 | |
| 2185 | return 0; |
| 2186 | } |
| 2187 | |
| 2188 | static int |
| 2189 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
| 2190 | { |
| 2191 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2192 | int page_count, i; |
| 2193 | struct address_space *mapping; |
| 2194 | struct sg_table *st; |
| 2195 | struct scatterlist *sg; |
| 2196 | struct sg_page_iter sg_iter; |
| 2197 | struct page *page; |
| 2198 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
| 2199 | gfp_t gfp; |
| 2200 | |
| 2201 | /* Assert that the object is not currently in any GPU domain. As it |
| 2202 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2203 | * a GPU cache |
| 2204 | */ |
| 2205 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2206 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2207 | |
| 2208 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2209 | if (st == NULL) |
| 2210 | return -ENOMEM; |
| 2211 | |
| 2212 | page_count = obj->base.size / PAGE_SIZE; |
| 2213 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
| 2214 | kfree(st); |
| 2215 | return -ENOMEM; |
| 2216 | } |
| 2217 | |
| 2218 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2219 | * at this point until we release them. |
| 2220 | * |
| 2221 | * Fail silently without starting the shrinker |
| 2222 | */ |
| 2223 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 2224 | gfp = mapping_gfp_mask(mapping); |
| 2225 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
| 2226 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 2227 | sg = st->sgl; |
| 2228 | st->nents = 0; |
| 2229 | for (i = 0; i < page_count; i++) { |
| 2230 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2231 | if (IS_ERR(page)) { |
| 2232 | i915_gem_shrink(dev_priv, |
| 2233 | page_count, |
| 2234 | I915_SHRINK_BOUND | |
| 2235 | I915_SHRINK_UNBOUND | |
| 2236 | I915_SHRINK_PURGEABLE); |
| 2237 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2238 | } |
| 2239 | if (IS_ERR(page)) { |
| 2240 | /* We've tried hard to allocate the memory by reaping |
| 2241 | * our own buffer, now let the real VM do its job and |
| 2242 | * go down in flames if truly OOM. |
| 2243 | */ |
| 2244 | i915_gem_shrink_all(dev_priv); |
| 2245 | page = shmem_read_mapping_page(mapping, i); |
| 2246 | if (IS_ERR(page)) |
| 2247 | goto err_pages; |
| 2248 | } |
| 2249 | #ifdef CONFIG_SWIOTLB |
| 2250 | if (swiotlb_nr_tbl()) { |
| 2251 | st->nents++; |
| 2252 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2253 | sg = sg_next(sg); |
| 2254 | continue; |
| 2255 | } |
| 2256 | #endif |
| 2257 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2258 | if (i) |
| 2259 | sg = sg_next(sg); |
| 2260 | st->nents++; |
| 2261 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2262 | } else { |
| 2263 | sg->length += PAGE_SIZE; |
| 2264 | } |
| 2265 | last_pfn = page_to_pfn(page); |
| 2266 | |
| 2267 | /* Check that the i965g/gm workaround works. */ |
| 2268 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
| 2269 | } |
| 2270 | #ifdef CONFIG_SWIOTLB |
| 2271 | if (!swiotlb_nr_tbl()) |
| 2272 | #endif |
| 2273 | sg_mark_end(sg); |
| 2274 | obj->pages = st; |
| 2275 | |
| 2276 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2277 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2278 | |
| 2279 | if (obj->tiling_mode != I915_TILING_NONE && |
| 2280 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2281 | i915_gem_object_pin_pages(obj); |
| 2282 | |
| 2283 | return 0; |
| 2284 | |
| 2285 | err_pages: |
| 2286 | sg_mark_end(sg); |
| 2287 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
| 2288 | page_cache_release(sg_page_iter_page(&sg_iter)); |
| 2289 | sg_free_table(st); |
| 2290 | kfree(st); |
| 2291 | |
| 2292 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2293 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2294 | * ENOMEM for a genuine allocation failure. |
| 2295 | * |
| 2296 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2297 | * space and so want to translate the error from shmemfs back to our |
| 2298 | * usual understanding of ENOMEM. |
| 2299 | */ |
| 2300 | if (PTR_ERR(page) == -ENOSPC) |
| 2301 | return -ENOMEM; |
| 2302 | else |
| 2303 | return PTR_ERR(page); |
| 2304 | } |
| 2305 | |
| 2306 | /* Ensure that the associated pages are gathered from the backing storage |
| 2307 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2308 | * multiple times before they are released by a single call to |
| 2309 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2310 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2311 | * or as the object is itself released. |
| 2312 | */ |
| 2313 | int |
| 2314 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2315 | { |
| 2316 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2317 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2318 | int ret; |
| 2319 | |
| 2320 | if (obj->pages) |
| 2321 | return 0; |
| 2322 | |
| 2323 | if (obj->madv != I915_MADV_WILLNEED) { |
| 2324 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
| 2325 | return -EFAULT; |
| 2326 | } |
| 2327 | |
| 2328 | BUG_ON(obj->pages_pin_count); |
| 2329 | |
| 2330 | ret = ops->get_pages(obj); |
| 2331 | if (ret) |
| 2332 | return ret; |
| 2333 | |
| 2334 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
| 2335 | |
| 2336 | obj->get_page.sg = obj->pages->sgl; |
| 2337 | obj->get_page.last = 0; |
| 2338 | |
| 2339 | return 0; |
| 2340 | } |
| 2341 | |
| 2342 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2343 | struct intel_engine_cs *ring) |
| 2344 | { |
| 2345 | struct drm_i915_gem_object *obj = vma->obj; |
| 2346 | |
| 2347 | /* Add a reference if we're newly entering the active list. */ |
| 2348 | if (obj->active == 0) |
| 2349 | drm_gem_object_reference(&obj->base); |
| 2350 | obj->active |= intel_ring_flag(ring); |
| 2351 | |
| 2352 | list_move_tail(&obj->ring_list[ring->id], &ring->active_list); |
| 2353 | i915_gem_request_assign(&obj->last_read_req[ring->id], |
| 2354 | intel_ring_get_request(ring)); |
| 2355 | |
| 2356 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
| 2357 | } |
| 2358 | |
| 2359 | static void |
| 2360 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) |
| 2361 | { |
| 2362 | RQ_BUG_ON(obj->last_write_req == NULL); |
| 2363 | RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); |
| 2364 | |
| 2365 | i915_gem_request_assign(&obj->last_write_req, NULL); |
| 2366 | intel_fb_obj_flush(obj, true); |
| 2367 | } |
| 2368 | |
| 2369 | static void |
| 2370 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
| 2371 | { |
| 2372 | struct i915_vma *vma; |
| 2373 | |
| 2374 | RQ_BUG_ON(obj->last_read_req[ring] == NULL); |
| 2375 | RQ_BUG_ON(!(obj->active & (1 << ring))); |
| 2376 | |
| 2377 | list_del_init(&obj->ring_list[ring]); |
| 2378 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
| 2379 | |
| 2380 | if (obj->last_write_req && obj->last_write_req->ring->id == ring) |
| 2381 | i915_gem_object_retire__write(obj); |
| 2382 | |
| 2383 | obj->active &= ~(1 << ring); |
| 2384 | if (obj->active) |
| 2385 | return; |
| 2386 | |
| 2387 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 2388 | if (!list_empty(&vma->mm_list)) |
| 2389 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); |
| 2390 | } |
| 2391 | |
| 2392 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
| 2393 | drm_gem_object_unreference(&obj->base); |
| 2394 | } |
| 2395 | |
| 2396 | static int |
| 2397 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
| 2398 | { |
| 2399 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2400 | struct intel_engine_cs *ring; |
| 2401 | int ret, i, j; |
| 2402 | |
| 2403 | /* Carefully retire all requests without writing to the rings */ |
| 2404 | for_each_ring(ring, dev_priv, i) { |
| 2405 | ret = intel_ring_idle(ring); |
| 2406 | if (ret) |
| 2407 | return ret; |
| 2408 | } |
| 2409 | i915_gem_retire_requests(dev); |
| 2410 | |
| 2411 | /* Finally reset hw state */ |
| 2412 | for_each_ring(ring, dev_priv, i) { |
| 2413 | intel_ring_init_seqno(ring, seqno); |
| 2414 | |
| 2415 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
| 2416 | ring->semaphore.sync_seqno[j] = 0; |
| 2417 | } |
| 2418 | |
| 2419 | return 0; |
| 2420 | } |
| 2421 | |
| 2422 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2423 | { |
| 2424 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2425 | int ret; |
| 2426 | |
| 2427 | if (seqno == 0) |
| 2428 | return -EINVAL; |
| 2429 | |
| 2430 | /* HWS page needs to be set less than what we |
| 2431 | * will inject to ring |
| 2432 | */ |
| 2433 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2434 | if (ret) |
| 2435 | return ret; |
| 2436 | |
| 2437 | /* Carefully set the last_seqno value so that wrap |
| 2438 | * detection still works |
| 2439 | */ |
| 2440 | dev_priv->next_seqno = seqno; |
| 2441 | dev_priv->last_seqno = seqno - 1; |
| 2442 | if (dev_priv->last_seqno == 0) |
| 2443 | dev_priv->last_seqno--; |
| 2444 | |
| 2445 | return 0; |
| 2446 | } |
| 2447 | |
| 2448 | int |
| 2449 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
| 2450 | { |
| 2451 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2452 | |
| 2453 | /* reserve 0 for non-seqno */ |
| 2454 | if (dev_priv->next_seqno == 0) { |
| 2455 | int ret = i915_gem_init_seqno(dev, 0); |
| 2456 | if (ret) |
| 2457 | return ret; |
| 2458 | |
| 2459 | dev_priv->next_seqno = 1; |
| 2460 | } |
| 2461 | |
| 2462 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
| 2463 | return 0; |
| 2464 | } |
| 2465 | |
| 2466 | /* |
| 2467 | * NB: This function is not allowed to fail. Doing so would mean the the |
| 2468 | * request is not being tracked for completion but the work itself is |
| 2469 | * going to happen on the hardware. This would be a Bad Thing(tm). |
| 2470 | */ |
| 2471 | void __i915_add_request(struct intel_engine_cs *ring, |
| 2472 | struct drm_file *file, |
| 2473 | struct drm_i915_gem_object *obj, |
| 2474 | bool flush_caches) |
| 2475 | { |
| 2476 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 2477 | struct drm_i915_gem_request *request; |
| 2478 | struct intel_ringbuffer *ringbuf; |
| 2479 | u32 request_start; |
| 2480 | int ret; |
| 2481 | |
| 2482 | request = ring->outstanding_lazy_request; |
| 2483 | if (WARN_ON(request == NULL)) |
| 2484 | return; |
| 2485 | |
| 2486 | if (i915.enable_execlists) { |
| 2487 | ringbuf = request->ctx->engine[ring->id].ringbuf; |
| 2488 | } else |
| 2489 | ringbuf = ring->buffer; |
| 2490 | |
| 2491 | /* |
| 2492 | * To ensure that this call will not fail, space for its emissions |
| 2493 | * should already have been reserved in the ring buffer. Let the ring |
| 2494 | * know that it is time to use that space up. |
| 2495 | */ |
| 2496 | intel_ring_reserved_space_use(ringbuf); |
| 2497 | |
| 2498 | request_start = intel_ring_get_tail(ringbuf); |
| 2499 | /* |
| 2500 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2501 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2502 | * things up similar to emitting the lazy request. The difference here |
| 2503 | * is that the flush _must_ happen before the next request, no matter |
| 2504 | * what. |
| 2505 | */ |
| 2506 | if (flush_caches) { |
| 2507 | if (i915.enable_execlists) |
| 2508 | ret = logical_ring_flush_all_caches(ringbuf, request->ctx); |
| 2509 | else |
| 2510 | ret = intel_ring_flush_all_caches(ring); |
| 2511 | /* Not allowed to fail! */ |
| 2512 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); |
| 2513 | } |
| 2514 | |
| 2515 | /* Record the position of the start of the request so that |
| 2516 | * should we detect the updated seqno part-way through the |
| 2517 | * GPU processing the request, we never over-estimate the |
| 2518 | * position of the head. |
| 2519 | */ |
| 2520 | request->postfix = intel_ring_get_tail(ringbuf); |
| 2521 | |
| 2522 | if (i915.enable_execlists) |
| 2523 | ret = ring->emit_request(ringbuf, request); |
| 2524 | else { |
| 2525 | ret = ring->add_request(ring); |
| 2526 | |
| 2527 | request->tail = intel_ring_get_tail(ringbuf); |
| 2528 | } |
| 2529 | /* Not allowed to fail! */ |
| 2530 | WARN(ret, "emit|add_request failed: %d!\n", ret); |
| 2531 | |
| 2532 | request->head = request_start; |
| 2533 | |
| 2534 | /* Whilst this request exists, batch_obj will be on the |
| 2535 | * active_list, and so will hold the active reference. Only when this |
| 2536 | * request is retired will the the batch_obj be moved onto the |
| 2537 | * inactive_list and lose its active reference. Hence we do not need |
| 2538 | * to explicitly hold another reference here. |
| 2539 | */ |
| 2540 | request->batch_obj = obj; |
| 2541 | |
| 2542 | request->emitted_jiffies = jiffies; |
| 2543 | list_add_tail(&request->list, &ring->request_list); |
| 2544 | request->file_priv = NULL; |
| 2545 | |
| 2546 | if (file) { |
| 2547 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2548 | |
| 2549 | spin_lock(&file_priv->mm.lock); |
| 2550 | request->file_priv = file_priv; |
| 2551 | list_add_tail(&request->client_list, |
| 2552 | &file_priv->mm.request_list); |
| 2553 | spin_unlock(&file_priv->mm.lock); |
| 2554 | |
| 2555 | request->pid = get_pid(task_pid(current)); |
| 2556 | } |
| 2557 | |
| 2558 | trace_i915_gem_request_add(request); |
| 2559 | ring->outstanding_lazy_request = NULL; |
| 2560 | |
| 2561 | i915_queue_hangcheck(ring->dev); |
| 2562 | |
| 2563 | queue_delayed_work(dev_priv->wq, |
| 2564 | &dev_priv->mm.retire_work, |
| 2565 | round_jiffies_up_relative(HZ)); |
| 2566 | intel_mark_busy(dev_priv->dev); |
| 2567 | |
| 2568 | /* Sanity check that the reserved size was large enough. */ |
| 2569 | intel_ring_reserved_space_end(ringbuf); |
| 2570 | } |
| 2571 | |
| 2572 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
| 2573 | const struct intel_context *ctx) |
| 2574 | { |
| 2575 | unsigned long elapsed; |
| 2576 | |
| 2577 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2578 | |
| 2579 | if (ctx->hang_stats.banned) |
| 2580 | return true; |
| 2581 | |
| 2582 | if (ctx->hang_stats.ban_period_seconds && |
| 2583 | elapsed <= ctx->hang_stats.ban_period_seconds) { |
| 2584 | if (!i915_gem_context_is_default(ctx)) { |
| 2585 | DRM_DEBUG("context hanging too fast, banning!\n"); |
| 2586 | return true; |
| 2587 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2588 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2589 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
| 2590 | return true; |
| 2591 | } |
| 2592 | } |
| 2593 | |
| 2594 | return false; |
| 2595 | } |
| 2596 | |
| 2597 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
| 2598 | struct intel_context *ctx, |
| 2599 | const bool guilty) |
| 2600 | { |
| 2601 | struct i915_ctx_hang_stats *hs; |
| 2602 | |
| 2603 | if (WARN_ON(!ctx)) |
| 2604 | return; |
| 2605 | |
| 2606 | hs = &ctx->hang_stats; |
| 2607 | |
| 2608 | if (guilty) { |
| 2609 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
| 2610 | hs->batch_active++; |
| 2611 | hs->guilty_ts = get_seconds(); |
| 2612 | } else { |
| 2613 | hs->batch_pending++; |
| 2614 | } |
| 2615 | } |
| 2616 | |
| 2617 | void i915_gem_request_free(struct kref *req_ref) |
| 2618 | { |
| 2619 | struct drm_i915_gem_request *req = container_of(req_ref, |
| 2620 | typeof(*req), ref); |
| 2621 | struct intel_context *ctx = req->ctx; |
| 2622 | |
| 2623 | if (ctx) { |
| 2624 | if (i915.enable_execlists) { |
| 2625 | struct intel_engine_cs *ring = req->ring; |
| 2626 | |
| 2627 | if (ctx != ring->default_context) |
| 2628 | intel_lr_context_unpin(ring, ctx); |
| 2629 | } |
| 2630 | |
| 2631 | i915_gem_context_unreference(ctx); |
| 2632 | } |
| 2633 | |
| 2634 | kmem_cache_free(req->i915->requests, req); |
| 2635 | } |
| 2636 | |
| 2637 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
| 2638 | struct intel_context *ctx, |
| 2639 | struct drm_i915_gem_request **req_out) |
| 2640 | { |
| 2641 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 2642 | struct drm_i915_gem_request *req; |
| 2643 | int ret; |
| 2644 | |
| 2645 | if (!req_out) |
| 2646 | return -EINVAL; |
| 2647 | |
| 2648 | if ((*req_out = ring->outstanding_lazy_request) != NULL) |
| 2649 | return 0; |
| 2650 | |
| 2651 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
| 2652 | if (req == NULL) |
| 2653 | return -ENOMEM; |
| 2654 | |
| 2655 | ret = i915_gem_get_seqno(ring->dev, &req->seqno); |
| 2656 | if (ret) |
| 2657 | goto err; |
| 2658 | |
| 2659 | kref_init(&req->ref); |
| 2660 | req->i915 = dev_priv; |
| 2661 | req->ring = ring; |
| 2662 | req->ctx = ctx; |
| 2663 | i915_gem_context_reference(req->ctx); |
| 2664 | |
| 2665 | if (i915.enable_execlists) |
| 2666 | ret = intel_logical_ring_alloc_request_extras(req); |
| 2667 | else |
| 2668 | ret = intel_ring_alloc_request_extras(req); |
| 2669 | if (ret) { |
| 2670 | i915_gem_context_unreference(req->ctx); |
| 2671 | goto err; |
| 2672 | } |
| 2673 | |
| 2674 | /* |
| 2675 | * Reserve space in the ring buffer for all the commands required to |
| 2676 | * eventually emit this request. This is to guarantee that the |
| 2677 | * i915_add_request() call can't fail. Note that the reserve may need |
| 2678 | * to be redone if the request is not actually submitted straight |
| 2679 | * away, e.g. because a GPU scheduler has deferred it. |
| 2680 | * |
| 2681 | * Note further that this call merely notes the reserve request. A |
| 2682 | * subsequent call to *_ring_begin() is required to actually ensure |
| 2683 | * that the reservation is available. Without the begin, if the |
| 2684 | * request creator immediately submitted the request without adding |
| 2685 | * any commands to it then there might not actually be sufficient |
| 2686 | * room for the submission commands. Unfortunately, the current |
| 2687 | * *_ring_begin() implementations potentially call back here to |
| 2688 | * i915_gem_request_alloc(). Thus calling _begin() here would lead to |
| 2689 | * infinite recursion! Until that back call path is removed, it is |
| 2690 | * necessary to do a manual _begin() outside. |
| 2691 | */ |
| 2692 | intel_ring_reserved_space_reserve(req->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); |
| 2693 | |
| 2694 | *req_out = ring->outstanding_lazy_request = req; |
| 2695 | return 0; |
| 2696 | |
| 2697 | err: |
| 2698 | kmem_cache_free(dev_priv->requests, req); |
| 2699 | return ret; |
| 2700 | } |
| 2701 | |
| 2702 | void i915_gem_request_cancel(struct drm_i915_gem_request *req) |
| 2703 | { |
| 2704 | intel_ring_reserved_space_cancel(req->ringbuf); |
| 2705 | |
| 2706 | i915_gem_request_unreference(req); |
| 2707 | } |
| 2708 | |
| 2709 | struct drm_i915_gem_request * |
| 2710 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
| 2711 | { |
| 2712 | struct drm_i915_gem_request *request; |
| 2713 | |
| 2714 | list_for_each_entry(request, &ring->request_list, list) { |
| 2715 | if (i915_gem_request_completed(request, false)) |
| 2716 | continue; |
| 2717 | |
| 2718 | return request; |
| 2719 | } |
| 2720 | |
| 2721 | return NULL; |
| 2722 | } |
| 2723 | |
| 2724 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
| 2725 | struct intel_engine_cs *ring) |
| 2726 | { |
| 2727 | struct drm_i915_gem_request *request; |
| 2728 | bool ring_hung; |
| 2729 | |
| 2730 | request = i915_gem_find_active_request(ring); |
| 2731 | |
| 2732 | if (request == NULL) |
| 2733 | return; |
| 2734 | |
| 2735 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2736 | |
| 2737 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
| 2738 | |
| 2739 | list_for_each_entry_continue(request, &ring->request_list, list) |
| 2740 | i915_set_reset_status(dev_priv, request->ctx, false); |
| 2741 | } |
| 2742 | |
| 2743 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
| 2744 | struct intel_engine_cs *ring) |
| 2745 | { |
| 2746 | while (!list_empty(&ring->active_list)) { |
| 2747 | struct drm_i915_gem_object *obj; |
| 2748 | |
| 2749 | obj = list_first_entry(&ring->active_list, |
| 2750 | struct drm_i915_gem_object, |
| 2751 | ring_list[ring->id]); |
| 2752 | |
| 2753 | i915_gem_object_retire__read(obj, ring->id); |
| 2754 | } |
| 2755 | |
| 2756 | /* |
| 2757 | * Clear the execlists queue up before freeing the requests, as those |
| 2758 | * are the ones that keep the context and ringbuffer backing objects |
| 2759 | * pinned in place. |
| 2760 | */ |
| 2761 | while (!list_empty(&ring->execlist_queue)) { |
| 2762 | struct drm_i915_gem_request *submit_req; |
| 2763 | |
| 2764 | submit_req = list_first_entry(&ring->execlist_queue, |
| 2765 | struct drm_i915_gem_request, |
| 2766 | execlist_link); |
| 2767 | list_del(&submit_req->execlist_link); |
| 2768 | |
| 2769 | if (submit_req->ctx != ring->default_context) |
| 2770 | intel_lr_context_unpin(ring, submit_req->ctx); |
| 2771 | |
| 2772 | i915_gem_request_unreference(submit_req); |
| 2773 | } |
| 2774 | |
| 2775 | /* |
| 2776 | * We must free the requests after all the corresponding objects have |
| 2777 | * been moved off active lists. Which is the same order as the normal |
| 2778 | * retire_requests function does. This is important if object hold |
| 2779 | * implicit references on things like e.g. ppgtt address spaces through |
| 2780 | * the request. |
| 2781 | */ |
| 2782 | while (!list_empty(&ring->request_list)) { |
| 2783 | struct drm_i915_gem_request *request; |
| 2784 | |
| 2785 | request = list_first_entry(&ring->request_list, |
| 2786 | struct drm_i915_gem_request, |
| 2787 | list); |
| 2788 | |
| 2789 | i915_gem_request_retire(request); |
| 2790 | } |
| 2791 | |
| 2792 | /* This may not have been flushed before the reset, so clean it now */ |
| 2793 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
| 2794 | } |
| 2795 | |
| 2796 | void i915_gem_restore_fences(struct drm_device *dev) |
| 2797 | { |
| 2798 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2799 | int i; |
| 2800 | |
| 2801 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
| 2802 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
| 2803 | |
| 2804 | /* |
| 2805 | * Commit delayed tiling changes if we have an object still |
| 2806 | * attached to the fence, otherwise just clear the fence. |
| 2807 | */ |
| 2808 | if (reg->obj) { |
| 2809 | i915_gem_object_update_fence(reg->obj, reg, |
| 2810 | reg->obj->tiling_mode); |
| 2811 | } else { |
| 2812 | i915_gem_write_fence(dev, i, NULL); |
| 2813 | } |
| 2814 | } |
| 2815 | } |
| 2816 | |
| 2817 | void i915_gem_reset(struct drm_device *dev) |
| 2818 | { |
| 2819 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2820 | struct intel_engine_cs *ring; |
| 2821 | int i; |
| 2822 | |
| 2823 | /* |
| 2824 | * Before we free the objects from the requests, we need to inspect |
| 2825 | * them for finding the guilty party. As the requests only borrow |
| 2826 | * their reference to the objects, the inspection must be done first. |
| 2827 | */ |
| 2828 | for_each_ring(ring, dev_priv, i) |
| 2829 | i915_gem_reset_ring_status(dev_priv, ring); |
| 2830 | |
| 2831 | for_each_ring(ring, dev_priv, i) |
| 2832 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
| 2833 | |
| 2834 | i915_gem_context_reset(dev); |
| 2835 | |
| 2836 | i915_gem_restore_fences(dev); |
| 2837 | |
| 2838 | WARN_ON(i915_verify_lists(dev)); |
| 2839 | } |
| 2840 | |
| 2841 | /** |
| 2842 | * This function clears the request list as sequence numbers are passed. |
| 2843 | */ |
| 2844 | void |
| 2845 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
| 2846 | { |
| 2847 | WARN_ON(i915_verify_lists(ring->dev)); |
| 2848 | |
| 2849 | /* Retire requests first as we use it above for the early return. |
| 2850 | * If we retire requests last, we may use a later seqno and so clear |
| 2851 | * the requests lists without clearing the active list, leading to |
| 2852 | * confusion. |
| 2853 | */ |
| 2854 | while (!list_empty(&ring->request_list)) { |
| 2855 | struct drm_i915_gem_request *request; |
| 2856 | |
| 2857 | request = list_first_entry(&ring->request_list, |
| 2858 | struct drm_i915_gem_request, |
| 2859 | list); |
| 2860 | |
| 2861 | if (!i915_gem_request_completed(request, true)) |
| 2862 | break; |
| 2863 | |
| 2864 | i915_gem_request_retire(request); |
| 2865 | } |
| 2866 | |
| 2867 | /* Move any buffers on the active list that are no longer referenced |
| 2868 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2869 | * before we free the context associated with the requests. |
| 2870 | */ |
| 2871 | while (!list_empty(&ring->active_list)) { |
| 2872 | struct drm_i915_gem_object *obj; |
| 2873 | |
| 2874 | obj = list_first_entry(&ring->active_list, |
| 2875 | struct drm_i915_gem_object, |
| 2876 | ring_list[ring->id]); |
| 2877 | |
| 2878 | if (!list_empty(&obj->last_read_req[ring->id]->list)) |
| 2879 | break; |
| 2880 | |
| 2881 | i915_gem_object_retire__read(obj, ring->id); |
| 2882 | } |
| 2883 | |
| 2884 | if (unlikely(ring->trace_irq_req && |
| 2885 | i915_gem_request_completed(ring->trace_irq_req, true))) { |
| 2886 | ring->irq_put(ring); |
| 2887 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
| 2888 | } |
| 2889 | |
| 2890 | WARN_ON(i915_verify_lists(ring->dev)); |
| 2891 | } |
| 2892 | |
| 2893 | bool |
| 2894 | i915_gem_retire_requests(struct drm_device *dev) |
| 2895 | { |
| 2896 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2897 | struct intel_engine_cs *ring; |
| 2898 | bool idle = true; |
| 2899 | int i; |
| 2900 | |
| 2901 | for_each_ring(ring, dev_priv, i) { |
| 2902 | i915_gem_retire_requests_ring(ring); |
| 2903 | idle &= list_empty(&ring->request_list); |
| 2904 | if (i915.enable_execlists) { |
| 2905 | unsigned long flags; |
| 2906 | |
| 2907 | spin_lock_irqsave(&ring->execlist_lock, flags); |
| 2908 | idle &= list_empty(&ring->execlist_queue); |
| 2909 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
| 2910 | |
| 2911 | intel_execlists_retire_requests(ring); |
| 2912 | } |
| 2913 | } |
| 2914 | |
| 2915 | if (idle) |
| 2916 | mod_delayed_work(dev_priv->wq, |
| 2917 | &dev_priv->mm.idle_work, |
| 2918 | msecs_to_jiffies(100)); |
| 2919 | |
| 2920 | return idle; |
| 2921 | } |
| 2922 | |
| 2923 | static void |
| 2924 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2925 | { |
| 2926 | struct drm_i915_private *dev_priv = |
| 2927 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 2928 | struct drm_device *dev = dev_priv->dev; |
| 2929 | bool idle; |
| 2930 | |
| 2931 | /* Come back later if the device is busy... */ |
| 2932 | idle = false; |
| 2933 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2934 | idle = i915_gem_retire_requests(dev); |
| 2935 | mutex_unlock(&dev->struct_mutex); |
| 2936 | } |
| 2937 | if (!idle) |
| 2938 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2939 | round_jiffies_up_relative(HZ)); |
| 2940 | } |
| 2941 | |
| 2942 | static void |
| 2943 | i915_gem_idle_work_handler(struct work_struct *work) |
| 2944 | { |
| 2945 | struct drm_i915_private *dev_priv = |
| 2946 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
| 2947 | struct drm_device *dev = dev_priv->dev; |
| 2948 | struct intel_engine_cs *ring; |
| 2949 | int i; |
| 2950 | |
| 2951 | for_each_ring(ring, dev_priv, i) |
| 2952 | if (!list_empty(&ring->request_list)) |
| 2953 | return; |
| 2954 | |
| 2955 | intel_mark_idle(dev); |
| 2956 | |
| 2957 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2958 | struct intel_engine_cs *ring; |
| 2959 | int i; |
| 2960 | |
| 2961 | for_each_ring(ring, dev_priv, i) |
| 2962 | i915_gem_batch_pool_fini(&ring->batch_pool); |
| 2963 | |
| 2964 | mutex_unlock(&dev->struct_mutex); |
| 2965 | } |
| 2966 | } |
| 2967 | |
| 2968 | /** |
| 2969 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2970 | * write domains, emitting any outstanding lazy request and retiring and |
| 2971 | * completed requests. |
| 2972 | */ |
| 2973 | static int |
| 2974 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2975 | { |
| 2976 | int ret, i; |
| 2977 | |
| 2978 | if (!obj->active) |
| 2979 | return 0; |
| 2980 | |
| 2981 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 2982 | struct drm_i915_gem_request *req; |
| 2983 | |
| 2984 | req = obj->last_read_req[i]; |
| 2985 | if (req == NULL) |
| 2986 | continue; |
| 2987 | |
| 2988 | if (list_empty(&req->list)) |
| 2989 | goto retire; |
| 2990 | |
| 2991 | ret = i915_gem_check_olr(req); |
| 2992 | if (ret) |
| 2993 | return ret; |
| 2994 | |
| 2995 | if (i915_gem_request_completed(req, true)) { |
| 2996 | __i915_gem_request_retire__upto(req); |
| 2997 | retire: |
| 2998 | i915_gem_object_retire__read(obj, i); |
| 2999 | } |
| 3000 | } |
| 3001 | |
| 3002 | return 0; |
| 3003 | } |
| 3004 | |
| 3005 | /** |
| 3006 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 3007 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 3008 | * |
| 3009 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 3010 | * the timeout parameter. |
| 3011 | * -ETIME: object is still busy after timeout |
| 3012 | * -ERESTARTSYS: signal interrupted the wait |
| 3013 | * -ENONENT: object doesn't exist |
| 3014 | * Also possible, but rare: |
| 3015 | * -EAGAIN: GPU wedged |
| 3016 | * -ENOMEM: damn |
| 3017 | * -ENODEV: Internal IRQ fail |
| 3018 | * -E?: The add request failed |
| 3019 | * |
| 3020 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 3021 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 3022 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 3023 | * without holding struct_mutex the object may become re-busied before this |
| 3024 | * function completes. A similar but shorter * race condition exists in the busy |
| 3025 | * ioctl |
| 3026 | */ |
| 3027 | int |
| 3028 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 3029 | { |
| 3030 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3031 | struct drm_i915_gem_wait *args = data; |
| 3032 | struct drm_i915_gem_object *obj; |
| 3033 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; |
| 3034 | unsigned reset_counter; |
| 3035 | int i, n = 0; |
| 3036 | int ret; |
| 3037 | |
| 3038 | if (args->flags != 0) |
| 3039 | return -EINVAL; |
| 3040 | |
| 3041 | ret = i915_mutex_lock_interruptible(dev); |
| 3042 | if (ret) |
| 3043 | return ret; |
| 3044 | |
| 3045 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 3046 | if (&obj->base == NULL) { |
| 3047 | mutex_unlock(&dev->struct_mutex); |
| 3048 | return -ENOENT; |
| 3049 | } |
| 3050 | |
| 3051 | /* Need to make sure the object gets inactive eventually. */ |
| 3052 | ret = i915_gem_object_flush_active(obj); |
| 3053 | if (ret) |
| 3054 | goto out; |
| 3055 | |
| 3056 | if (!obj->active) |
| 3057 | goto out; |
| 3058 | |
| 3059 | /* Do this after OLR check to make sure we make forward progress polling |
| 3060 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
| 3061 | */ |
| 3062 | if (args->timeout_ns == 0) { |
| 3063 | ret = -ETIME; |
| 3064 | goto out; |
| 3065 | } |
| 3066 | |
| 3067 | drm_gem_object_unreference(&obj->base); |
| 3068 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 3069 | |
| 3070 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3071 | if (obj->last_read_req[i] == NULL) |
| 3072 | continue; |
| 3073 | |
| 3074 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); |
| 3075 | } |
| 3076 | |
| 3077 | mutex_unlock(&dev->struct_mutex); |
| 3078 | |
| 3079 | for (i = 0; i < n; i++) { |
| 3080 | if (ret == 0) |
| 3081 | ret = __i915_wait_request(req[i], reset_counter, true, |
| 3082 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
| 3083 | file->driver_priv); |
| 3084 | i915_gem_request_unreference__unlocked(req[i]); |
| 3085 | } |
| 3086 | return ret; |
| 3087 | |
| 3088 | out: |
| 3089 | drm_gem_object_unreference(&obj->base); |
| 3090 | mutex_unlock(&dev->struct_mutex); |
| 3091 | return ret; |
| 3092 | } |
| 3093 | |
| 3094 | static int |
| 3095 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3096 | struct intel_engine_cs *to, |
| 3097 | struct drm_i915_gem_request *from_req, |
| 3098 | struct drm_i915_gem_request **to_req) |
| 3099 | { |
| 3100 | struct intel_engine_cs *from; |
| 3101 | int ret; |
| 3102 | |
| 3103 | from = i915_gem_request_get_ring(from_req); |
| 3104 | if (to == from) |
| 3105 | return 0; |
| 3106 | |
| 3107 | if (i915_gem_request_completed(from_req, true)) |
| 3108 | return 0; |
| 3109 | |
| 3110 | ret = i915_gem_check_olr(from_req); |
| 3111 | if (ret) |
| 3112 | return ret; |
| 3113 | |
| 3114 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
| 3115 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
| 3116 | ret = __i915_wait_request(from_req, |
| 3117 | atomic_read(&i915->gpu_error.reset_counter), |
| 3118 | i915->mm.interruptible, |
| 3119 | NULL, |
| 3120 | &i915->rps.semaphores); |
| 3121 | if (ret) |
| 3122 | return ret; |
| 3123 | |
| 3124 | i915_gem_object_retire_request(obj, from_req); |
| 3125 | } else { |
| 3126 | int idx = intel_ring_sync_index(from, to); |
| 3127 | u32 seqno = i915_gem_request_get_seqno(from_req); |
| 3128 | |
| 3129 | WARN_ON(!to_req); |
| 3130 | |
| 3131 | if (seqno <= from->semaphore.sync_seqno[idx]) |
| 3132 | return 0; |
| 3133 | |
| 3134 | if (*to_req == NULL) { |
| 3135 | ret = i915_gem_request_alloc(to, to->default_context, to_req); |
| 3136 | if (ret) |
| 3137 | return ret; |
| 3138 | } |
| 3139 | |
| 3140 | trace_i915_gem_ring_sync_to(from, to, from_req); |
| 3141 | ret = to->semaphore.sync_to(to, from, seqno); |
| 3142 | if (ret) |
| 3143 | return ret; |
| 3144 | |
| 3145 | /* We use last_read_req because sync_to() |
| 3146 | * might have just caused seqno wrap under |
| 3147 | * the radar. |
| 3148 | */ |
| 3149 | from->semaphore.sync_seqno[idx] = |
| 3150 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); |
| 3151 | } |
| 3152 | |
| 3153 | return 0; |
| 3154 | } |
| 3155 | |
| 3156 | /** |
| 3157 | * i915_gem_object_sync - sync an object to a ring. |
| 3158 | * |
| 3159 | * @obj: object which may be in use on another ring. |
| 3160 | * @to: ring we wish to use the object on. May be NULL. |
| 3161 | * @to_req: request we wish to use the object for. See below. |
| 3162 | * This will be allocated and returned if a request is |
| 3163 | * required but not passed in. |
| 3164 | * |
| 3165 | * This code is meant to abstract object synchronization with the GPU. |
| 3166 | * Calling with NULL implies synchronizing the object with the CPU |
| 3167 | * rather than a particular GPU ring. Conceptually we serialise writes |
| 3168 | * between engines inside the GPU. We only allow one engine to write |
| 3169 | * into a buffer at any time, but multiple readers. To ensure each has |
| 3170 | * a coherent view of memory, we must: |
| 3171 | * |
| 3172 | * - If there is an outstanding write request to the object, the new |
| 3173 | * request must wait for it to complete (either CPU or in hw, requests |
| 3174 | * on the same ring will be naturally ordered). |
| 3175 | * |
| 3176 | * - If we are a write request (pending_write_domain is set), the new |
| 3177 | * request must wait for outstanding read requests to complete. |
| 3178 | * |
| 3179 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
| 3180 | * rings to_req must be non-NULL. However, a request does not have to be |
| 3181 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a |
| 3182 | * request will be allocated automatically and returned through *to_req. Note |
| 3183 | * that it is not guaranteed that commands will be emitted (because the system |
| 3184 | * might already be idle). Hence there is no need to create a request that |
| 3185 | * might never have any work submitted. Note further that if a request is |
| 3186 | * returned in *to_req, it is the responsibility of the caller to submit |
| 3187 | * that request (after potentially adding more work to it). |
| 3188 | * |
| 3189 | * Returns 0 if successful, else propagates up the lower layer error. |
| 3190 | */ |
| 3191 | int |
| 3192 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3193 | struct intel_engine_cs *to, |
| 3194 | struct drm_i915_gem_request **to_req) |
| 3195 | { |
| 3196 | const bool readonly = obj->base.pending_write_domain == 0; |
| 3197 | struct drm_i915_gem_request *req[I915_NUM_RINGS]; |
| 3198 | int ret, i, n; |
| 3199 | |
| 3200 | if (!obj->active) |
| 3201 | return 0; |
| 3202 | |
| 3203 | if (to == NULL) |
| 3204 | return i915_gem_object_wait_rendering(obj, readonly); |
| 3205 | |
| 3206 | n = 0; |
| 3207 | if (readonly) { |
| 3208 | if (obj->last_write_req) |
| 3209 | req[n++] = obj->last_write_req; |
| 3210 | } else { |
| 3211 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3212 | if (obj->last_read_req[i]) |
| 3213 | req[n++] = obj->last_read_req[i]; |
| 3214 | } |
| 3215 | for (i = 0; i < n; i++) { |
| 3216 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
| 3217 | if (ret) |
| 3218 | return ret; |
| 3219 | } |
| 3220 | |
| 3221 | return 0; |
| 3222 | } |
| 3223 | |
| 3224 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 3225 | { |
| 3226 | u32 old_write_domain, old_read_domains; |
| 3227 | |
| 3228 | /* Force a pagefault for domain tracking on next user access */ |
| 3229 | i915_gem_release_mmap(obj); |
| 3230 | |
| 3231 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3232 | return; |
| 3233 | |
| 3234 | /* Wait for any direct GTT access to complete */ |
| 3235 | mb(); |
| 3236 | |
| 3237 | old_read_domains = obj->base.read_domains; |
| 3238 | old_write_domain = obj->base.write_domain; |
| 3239 | |
| 3240 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 3241 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 3242 | |
| 3243 | trace_i915_gem_object_change_domain(obj, |
| 3244 | old_read_domains, |
| 3245 | old_write_domain); |
| 3246 | } |
| 3247 | |
| 3248 | int i915_vma_unbind(struct i915_vma *vma) |
| 3249 | { |
| 3250 | struct drm_i915_gem_object *obj = vma->obj; |
| 3251 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3252 | int ret; |
| 3253 | |
| 3254 | if (list_empty(&vma->vma_link)) |
| 3255 | return 0; |
| 3256 | |
| 3257 | if (!drm_mm_node_allocated(&vma->node)) { |
| 3258 | i915_gem_vma_destroy(vma); |
| 3259 | return 0; |
| 3260 | } |
| 3261 | |
| 3262 | if (vma->pin_count) |
| 3263 | return -EBUSY; |
| 3264 | |
| 3265 | BUG_ON(obj->pages == NULL); |
| 3266 | |
| 3267 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3268 | if (ret) |
| 3269 | return ret; |
| 3270 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 3271 | * should be safe and we need to cleanup or else we might |
| 3272 | * cause memory corruption through use-after-free. |
| 3273 | */ |
| 3274 | |
| 3275 | if (i915_is_ggtt(vma->vm) && |
| 3276 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3277 | i915_gem_object_finish_gtt(obj); |
| 3278 | |
| 3279 | /* release the fence reg _after_ flushing */ |
| 3280 | ret = i915_gem_object_put_fence(obj); |
| 3281 | if (ret) |
| 3282 | return ret; |
| 3283 | } |
| 3284 | |
| 3285 | trace_i915_vma_unbind(vma); |
| 3286 | |
| 3287 | vma->vm->unbind_vma(vma); |
| 3288 | vma->bound = 0; |
| 3289 | |
| 3290 | list_del_init(&vma->mm_list); |
| 3291 | if (i915_is_ggtt(vma->vm)) { |
| 3292 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3293 | obj->map_and_fenceable = false; |
| 3294 | } else if (vma->ggtt_view.pages) { |
| 3295 | sg_free_table(vma->ggtt_view.pages); |
| 3296 | kfree(vma->ggtt_view.pages); |
| 3297 | vma->ggtt_view.pages = NULL; |
| 3298 | } |
| 3299 | } |
| 3300 | |
| 3301 | drm_mm_remove_node(&vma->node); |
| 3302 | i915_gem_vma_destroy(vma); |
| 3303 | |
| 3304 | /* Since the unbound list is global, only move to that list if |
| 3305 | * no more VMAs exist. */ |
| 3306 | if (list_empty(&obj->vma_list)) { |
| 3307 | i915_gem_gtt_finish_object(obj); |
| 3308 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
| 3309 | } |
| 3310 | |
| 3311 | /* And finally now the object is completely decoupled from this vma, |
| 3312 | * we can drop its hold on the backing storage and allow it to be |
| 3313 | * reaped by the shrinker. |
| 3314 | */ |
| 3315 | i915_gem_object_unpin_pages(obj); |
| 3316 | |
| 3317 | return 0; |
| 3318 | } |
| 3319 | |
| 3320 | int i915_gpu_idle(struct drm_device *dev) |
| 3321 | { |
| 3322 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3323 | struct intel_engine_cs *ring; |
| 3324 | int ret, i; |
| 3325 | |
| 3326 | /* Flush everything onto the inactive list. */ |
| 3327 | for_each_ring(ring, dev_priv, i) { |
| 3328 | if (!i915.enable_execlists) { |
| 3329 | struct drm_i915_gem_request *req; |
| 3330 | |
| 3331 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); |
| 3332 | if (ret) |
| 3333 | return ret; |
| 3334 | |
| 3335 | ret = i915_switch_context(req); |
| 3336 | if (ret) { |
| 3337 | i915_gem_request_cancel(req); |
| 3338 | return ret; |
| 3339 | } |
| 3340 | |
| 3341 | i915_add_request_no_flush(req->ring); |
| 3342 | } |
| 3343 | |
| 3344 | WARN_ON(ring->outstanding_lazy_request); |
| 3345 | |
| 3346 | ret = intel_ring_idle(ring); |
| 3347 | if (ret) |
| 3348 | return ret; |
| 3349 | } |
| 3350 | |
| 3351 | WARN_ON(i915_verify_lists(dev)); |
| 3352 | return 0; |
| 3353 | } |
| 3354 | |
| 3355 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 3356 | struct drm_i915_gem_object *obj) |
| 3357 | { |
| 3358 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3359 | int fence_reg; |
| 3360 | int fence_pitch_shift; |
| 3361 | |
| 3362 | if (INTEL_INFO(dev)->gen >= 6) { |
| 3363 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 3364 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 3365 | } else { |
| 3366 | fence_reg = FENCE_REG_965_0; |
| 3367 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 3368 | } |
| 3369 | |
| 3370 | fence_reg += reg * 8; |
| 3371 | |
| 3372 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 3373 | * we split the 64-bit update into two 32-bit writes. In order |
| 3374 | * for a partial fence not to be evaluated between writes, we |
| 3375 | * precede the update with write to turn off the fence register, |
| 3376 | * and only enable the fence as the last step. |
| 3377 | * |
| 3378 | * For extra levels of paranoia, we make sure each step lands |
| 3379 | * before applying the next step. |
| 3380 | */ |
| 3381 | I915_WRITE(fence_reg, 0); |
| 3382 | POSTING_READ(fence_reg); |
| 3383 | |
| 3384 | if (obj) { |
| 3385 | u32 size = i915_gem_obj_ggtt_size(obj); |
| 3386 | uint64_t val; |
| 3387 | |
| 3388 | /* Adjust fence size to match tiled area */ |
| 3389 | if (obj->tiling_mode != I915_TILING_NONE) { |
| 3390 | uint32_t row_size = obj->stride * |
| 3391 | (obj->tiling_mode == I915_TILING_Y ? 32 : 8); |
| 3392 | size = (size / row_size) * row_size; |
| 3393 | } |
| 3394 | |
| 3395 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
| 3396 | 0xfffff000) << 32; |
| 3397 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
| 3398 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
| 3399 | if (obj->tiling_mode == I915_TILING_Y) |
| 3400 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 3401 | val |= I965_FENCE_REG_VALID; |
| 3402 | |
| 3403 | I915_WRITE(fence_reg + 4, val >> 32); |
| 3404 | POSTING_READ(fence_reg + 4); |
| 3405 | |
| 3406 | I915_WRITE(fence_reg + 0, val); |
| 3407 | POSTING_READ(fence_reg); |
| 3408 | } else { |
| 3409 | I915_WRITE(fence_reg + 4, 0); |
| 3410 | POSTING_READ(fence_reg + 4); |
| 3411 | } |
| 3412 | } |
| 3413 | |
| 3414 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 3415 | struct drm_i915_gem_object *obj) |
| 3416 | { |
| 3417 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3418 | u32 val; |
| 3419 | |
| 3420 | if (obj) { |
| 3421 | u32 size = i915_gem_obj_ggtt_size(obj); |
| 3422 | int pitch_val; |
| 3423 | int tile_width; |
| 3424 | |
| 3425 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
| 3426 | (size & -size) != size || |
| 3427 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3428 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 3429 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
| 3430 | |
| 3431 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 3432 | tile_width = 128; |
| 3433 | else |
| 3434 | tile_width = 512; |
| 3435 | |
| 3436 | /* Note: pitch better be a power of two tile widths */ |
| 3437 | pitch_val = obj->stride / tile_width; |
| 3438 | pitch_val = ffs(pitch_val) - 1; |
| 3439 | |
| 3440 | val = i915_gem_obj_ggtt_offset(obj); |
| 3441 | if (obj->tiling_mode == I915_TILING_Y) |
| 3442 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3443 | val |= I915_FENCE_SIZE_BITS(size); |
| 3444 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3445 | val |= I830_FENCE_REG_VALID; |
| 3446 | } else |
| 3447 | val = 0; |
| 3448 | |
| 3449 | if (reg < 8) |
| 3450 | reg = FENCE_REG_830_0 + reg * 4; |
| 3451 | else |
| 3452 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
| 3453 | |
| 3454 | I915_WRITE(reg, val); |
| 3455 | POSTING_READ(reg); |
| 3456 | } |
| 3457 | |
| 3458 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 3459 | struct drm_i915_gem_object *obj) |
| 3460 | { |
| 3461 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3462 | uint32_t val; |
| 3463 | |
| 3464 | if (obj) { |
| 3465 | u32 size = i915_gem_obj_ggtt_size(obj); |
| 3466 | uint32_t pitch_val; |
| 3467 | |
| 3468 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
| 3469 | (size & -size) != size || |
| 3470 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 3471 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 3472 | i915_gem_obj_ggtt_offset(obj), size); |
| 3473 | |
| 3474 | pitch_val = obj->stride / 128; |
| 3475 | pitch_val = ffs(pitch_val) - 1; |
| 3476 | |
| 3477 | val = i915_gem_obj_ggtt_offset(obj); |
| 3478 | if (obj->tiling_mode == I915_TILING_Y) |
| 3479 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 3480 | val |= I830_FENCE_SIZE_BITS(size); |
| 3481 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 3482 | val |= I830_FENCE_REG_VALID; |
| 3483 | } else |
| 3484 | val = 0; |
| 3485 | |
| 3486 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 3487 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 3488 | } |
| 3489 | |
| 3490 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 3491 | { |
| 3492 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 3493 | } |
| 3494 | |
| 3495 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 3496 | struct drm_i915_gem_object *obj) |
| 3497 | { |
| 3498 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3499 | |
| 3500 | /* Ensure that all CPU reads are completed before installing a fence |
| 3501 | * and all writes before removing the fence. |
| 3502 | */ |
| 3503 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 3504 | mb(); |
| 3505 | |
| 3506 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 3507 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 3508 | obj->stride, obj->tiling_mode); |
| 3509 | |
| 3510 | if (IS_GEN2(dev)) |
| 3511 | i830_write_fence_reg(dev, reg, obj); |
| 3512 | else if (IS_GEN3(dev)) |
| 3513 | i915_write_fence_reg(dev, reg, obj); |
| 3514 | else if (INTEL_INFO(dev)->gen >= 4) |
| 3515 | i965_write_fence_reg(dev, reg, obj); |
| 3516 | |
| 3517 | /* And similarly be paranoid that no direct access to this region |
| 3518 | * is reordered to before the fence is installed. |
| 3519 | */ |
| 3520 | if (i915_gem_object_needs_mb(obj)) |
| 3521 | mb(); |
| 3522 | } |
| 3523 | |
| 3524 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 3525 | struct drm_i915_fence_reg *fence) |
| 3526 | { |
| 3527 | return fence - dev_priv->fence_regs; |
| 3528 | } |
| 3529 | |
| 3530 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 3531 | struct drm_i915_fence_reg *fence, |
| 3532 | bool enable) |
| 3533 | { |
| 3534 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3535 | int reg = fence_number(dev_priv, fence); |
| 3536 | |
| 3537 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 3538 | |
| 3539 | if (enable) { |
| 3540 | obj->fence_reg = reg; |
| 3541 | fence->obj = obj; |
| 3542 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 3543 | } else { |
| 3544 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3545 | fence->obj = NULL; |
| 3546 | list_del_init(&fence->lru_list); |
| 3547 | } |
| 3548 | obj->fence_dirty = false; |
| 3549 | } |
| 3550 | |
| 3551 | static int |
| 3552 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
| 3553 | { |
| 3554 | if (obj->last_fenced_req) { |
| 3555 | int ret = i915_wait_request(obj->last_fenced_req); |
| 3556 | if (ret) |
| 3557 | return ret; |
| 3558 | |
| 3559 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
| 3560 | } |
| 3561 | |
| 3562 | return 0; |
| 3563 | } |
| 3564 | |
| 3565 | int |
| 3566 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 3567 | { |
| 3568 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 3569 | struct drm_i915_fence_reg *fence; |
| 3570 | int ret; |
| 3571 | |
| 3572 | ret = i915_gem_object_wait_fence(obj); |
| 3573 | if (ret) |
| 3574 | return ret; |
| 3575 | |
| 3576 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 3577 | return 0; |
| 3578 | |
| 3579 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 3580 | |
| 3581 | if (WARN_ON(fence->pin_count)) |
| 3582 | return -EBUSY; |
| 3583 | |
| 3584 | i915_gem_object_fence_lost(obj); |
| 3585 | i915_gem_object_update_fence(obj, fence, false); |
| 3586 | |
| 3587 | return 0; |
| 3588 | } |
| 3589 | |
| 3590 | static struct drm_i915_fence_reg * |
| 3591 | i915_find_fence_reg(struct drm_device *dev) |
| 3592 | { |
| 3593 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3594 | struct drm_i915_fence_reg *reg, *avail; |
| 3595 | int i; |
| 3596 | |
| 3597 | /* First try to find a free reg */ |
| 3598 | avail = NULL; |
| 3599 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 3600 | reg = &dev_priv->fence_regs[i]; |
| 3601 | if (!reg->obj) |
| 3602 | return reg; |
| 3603 | |
| 3604 | if (!reg->pin_count) |
| 3605 | avail = reg; |
| 3606 | } |
| 3607 | |
| 3608 | if (avail == NULL) |
| 3609 | goto deadlock; |
| 3610 | |
| 3611 | /* None available, try to steal one or wait for a user to finish */ |
| 3612 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
| 3613 | if (reg->pin_count) |
| 3614 | continue; |
| 3615 | |
| 3616 | return reg; |
| 3617 | } |
| 3618 | |
| 3619 | deadlock: |
| 3620 | /* Wait for completion of pending flips which consume fences */ |
| 3621 | if (intel_has_pending_fb_unpin(dev)) |
| 3622 | return ERR_PTR(-EAGAIN); |
| 3623 | |
| 3624 | return ERR_PTR(-EDEADLK); |
| 3625 | } |
| 3626 | |
| 3627 | /** |
| 3628 | * i915_gem_object_get_fence - set up fencing for an object |
| 3629 | * @obj: object to map through a fence reg |
| 3630 | * |
| 3631 | * When mapping objects through the GTT, userspace wants to be able to write |
| 3632 | * to them without having to worry about swizzling if the object is tiled. |
| 3633 | * This function walks the fence regs looking for a free one for @obj, |
| 3634 | * stealing one if it can't find any. |
| 3635 | * |
| 3636 | * It then sets up the reg based on the object's properties: address, pitch |
| 3637 | * and tiling format. |
| 3638 | * |
| 3639 | * For an untiled surface, this removes any existing fence. |
| 3640 | */ |
| 3641 | int |
| 3642 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
| 3643 | { |
| 3644 | struct drm_device *dev = obj->base.dev; |
| 3645 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3646 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
| 3647 | struct drm_i915_fence_reg *reg; |
| 3648 | int ret; |
| 3649 | |
| 3650 | /* Have we updated the tiling parameters upon the object and so |
| 3651 | * will need to serialise the write to the associated fence register? |
| 3652 | */ |
| 3653 | if (obj->fence_dirty) { |
| 3654 | ret = i915_gem_object_wait_fence(obj); |
| 3655 | if (ret) |
| 3656 | return ret; |
| 3657 | } |
| 3658 | |
| 3659 | /* Just update our place in the LRU if our fence is getting reused. */ |
| 3660 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3661 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 3662 | if (!obj->fence_dirty) { |
| 3663 | list_move_tail(®->lru_list, |
| 3664 | &dev_priv->mm.fence_list); |
| 3665 | return 0; |
| 3666 | } |
| 3667 | } else if (enable) { |
| 3668 | if (WARN_ON(!obj->map_and_fenceable)) |
| 3669 | return -EINVAL; |
| 3670 | |
| 3671 | reg = i915_find_fence_reg(dev); |
| 3672 | if (IS_ERR(reg)) |
| 3673 | return PTR_ERR(reg); |
| 3674 | |
| 3675 | if (reg->obj) { |
| 3676 | struct drm_i915_gem_object *old = reg->obj; |
| 3677 | |
| 3678 | ret = i915_gem_object_wait_fence(old); |
| 3679 | if (ret) |
| 3680 | return ret; |
| 3681 | |
| 3682 | i915_gem_object_fence_lost(old); |
| 3683 | } |
| 3684 | } else |
| 3685 | return 0; |
| 3686 | |
| 3687 | i915_gem_object_update_fence(obj, reg, enable); |
| 3688 | |
| 3689 | return 0; |
| 3690 | } |
| 3691 | |
| 3692 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
| 3693 | unsigned long cache_level) |
| 3694 | { |
| 3695 | struct drm_mm_node *gtt_space = &vma->node; |
| 3696 | struct drm_mm_node *other; |
| 3697 | |
| 3698 | /* |
| 3699 | * On some machines we have to be careful when putting differing types |
| 3700 | * of snoopable memory together to avoid the prefetcher crossing memory |
| 3701 | * domains and dying. During vm initialisation, we decide whether or not |
| 3702 | * these constraints apply and set the drm_mm.color_adjust |
| 3703 | * appropriately. |
| 3704 | */ |
| 3705 | if (vma->vm->mm.color_adjust == NULL) |
| 3706 | return true; |
| 3707 | |
| 3708 | if (!drm_mm_node_allocated(gtt_space)) |
| 3709 | return true; |
| 3710 | |
| 3711 | if (list_empty(>t_space->node_list)) |
| 3712 | return true; |
| 3713 | |
| 3714 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3715 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3716 | return false; |
| 3717 | |
| 3718 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3719 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3720 | return false; |
| 3721 | |
| 3722 | return true; |
| 3723 | } |
| 3724 | |
| 3725 | /** |
| 3726 | * Finds free space in the GTT aperture and binds the object or a view of it |
| 3727 | * there. |
| 3728 | */ |
| 3729 | static struct i915_vma * |
| 3730 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3731 | struct i915_address_space *vm, |
| 3732 | const struct i915_ggtt_view *ggtt_view, |
| 3733 | unsigned alignment, |
| 3734 | uint64_t flags) |
| 3735 | { |
| 3736 | struct drm_device *dev = obj->base.dev; |
| 3737 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3738 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
| 3739 | unsigned long start = |
| 3740 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3741 | unsigned long end = |
| 3742 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
| 3743 | struct i915_vma *vma; |
| 3744 | int ret; |
| 3745 | |
| 3746 | if (i915_is_ggtt(vm)) { |
| 3747 | u32 view_size; |
| 3748 | |
| 3749 | if (WARN_ON(!ggtt_view)) |
| 3750 | return ERR_PTR(-EINVAL); |
| 3751 | |
| 3752 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
| 3753 | |
| 3754 | fence_size = i915_gem_get_gtt_size(dev, |
| 3755 | view_size, |
| 3756 | obj->tiling_mode); |
| 3757 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3758 | view_size, |
| 3759 | obj->tiling_mode, |
| 3760 | true); |
| 3761 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, |
| 3762 | view_size, |
| 3763 | obj->tiling_mode, |
| 3764 | false); |
| 3765 | size = flags & PIN_MAPPABLE ? fence_size : view_size; |
| 3766 | } else { |
| 3767 | fence_size = i915_gem_get_gtt_size(dev, |
| 3768 | obj->base.size, |
| 3769 | obj->tiling_mode); |
| 3770 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3771 | obj->base.size, |
| 3772 | obj->tiling_mode, |
| 3773 | true); |
| 3774 | unfenced_alignment = |
| 3775 | i915_gem_get_gtt_alignment(dev, |
| 3776 | obj->base.size, |
| 3777 | obj->tiling_mode, |
| 3778 | false); |
| 3779 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
| 3780 | } |
| 3781 | |
| 3782 | if (alignment == 0) |
| 3783 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
| 3784 | unfenced_alignment; |
| 3785 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
| 3786 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
| 3787 | ggtt_view ? ggtt_view->type : 0, |
| 3788 | alignment); |
| 3789 | return ERR_PTR(-EINVAL); |
| 3790 | } |
| 3791 | |
| 3792 | /* If binding the object/GGTT view requires more space than the entire |
| 3793 | * aperture has, reject it early before evicting everything in a vain |
| 3794 | * attempt to find space. |
| 3795 | */ |
| 3796 | if (size > end) { |
| 3797 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n", |
| 3798 | ggtt_view ? ggtt_view->type : 0, |
| 3799 | size, |
| 3800 | flags & PIN_MAPPABLE ? "mappable" : "total", |
| 3801 | end); |
| 3802 | return ERR_PTR(-E2BIG); |
| 3803 | } |
| 3804 | |
| 3805 | ret = i915_gem_object_get_pages(obj); |
| 3806 | if (ret) |
| 3807 | return ERR_PTR(ret); |
| 3808 | |
| 3809 | i915_gem_object_pin_pages(obj); |
| 3810 | |
| 3811 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
| 3812 | i915_gem_obj_lookup_or_create_vma(obj, vm); |
| 3813 | |
| 3814 | if (IS_ERR(vma)) |
| 3815 | goto err_unpin; |
| 3816 | |
| 3817 | search_free: |
| 3818 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
| 3819 | size, alignment, |
| 3820 | obj->cache_level, |
| 3821 | start, end, |
| 3822 | DRM_MM_SEARCH_DEFAULT, |
| 3823 | DRM_MM_CREATE_DEFAULT); |
| 3824 | if (ret) { |
| 3825 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
| 3826 | obj->cache_level, |
| 3827 | start, end, |
| 3828 | flags); |
| 3829 | if (ret == 0) |
| 3830 | goto search_free; |
| 3831 | |
| 3832 | goto err_free_vma; |
| 3833 | } |
| 3834 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
| 3835 | ret = -EINVAL; |
| 3836 | goto err_remove_node; |
| 3837 | } |
| 3838 | |
| 3839 | ret = i915_gem_gtt_prepare_object(obj); |
| 3840 | if (ret) |
| 3841 | goto err_remove_node; |
| 3842 | |
| 3843 | trace_i915_vma_bind(vma, flags); |
| 3844 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
| 3845 | if (ret) |
| 3846 | goto err_finish_gtt; |
| 3847 | |
| 3848 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
| 3849 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
| 3850 | |
| 3851 | return vma; |
| 3852 | |
| 3853 | err_finish_gtt: |
| 3854 | i915_gem_gtt_finish_object(obj); |
| 3855 | err_remove_node: |
| 3856 | drm_mm_remove_node(&vma->node); |
| 3857 | err_free_vma: |
| 3858 | i915_gem_vma_destroy(vma); |
| 3859 | vma = ERR_PTR(ret); |
| 3860 | err_unpin: |
| 3861 | i915_gem_object_unpin_pages(obj); |
| 3862 | return vma; |
| 3863 | } |
| 3864 | |
| 3865 | bool |
| 3866 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3867 | bool force) |
| 3868 | { |
| 3869 | /* If we don't have a page list set up, then we're not pinned |
| 3870 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3871 | * again at bind time. |
| 3872 | */ |
| 3873 | if (obj->pages == NULL) |
| 3874 | return false; |
| 3875 | |
| 3876 | /* |
| 3877 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3878 | * marked as wc by the system, or the system is cache-coherent. |
| 3879 | */ |
| 3880 | if (obj->stolen || obj->phys_handle) |
| 3881 | return false; |
| 3882 | |
| 3883 | /* If the GPU is snooping the contents of the CPU cache, |
| 3884 | * we do not need to manually clear the CPU cache lines. However, |
| 3885 | * the caches are only snooped when the render cache is |
| 3886 | * flushed/invalidated. As we always have to emit invalidations |
| 3887 | * and flushes when moving into and out of the RENDER domain, correct |
| 3888 | * snooping behaviour occurs naturally as the result of our domain |
| 3889 | * tracking. |
| 3890 | */ |
| 3891 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
| 3892 | obj->cache_dirty = true; |
| 3893 | return false; |
| 3894 | } |
| 3895 | |
| 3896 | trace_i915_gem_object_clflush(obj); |
| 3897 | drm_clflush_sg(obj->pages); |
| 3898 | obj->cache_dirty = false; |
| 3899 | |
| 3900 | return true; |
| 3901 | } |
| 3902 | |
| 3903 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3904 | static void |
| 3905 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
| 3906 | { |
| 3907 | uint32_t old_write_domain; |
| 3908 | |
| 3909 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
| 3910 | return; |
| 3911 | |
| 3912 | /* No actual flushing is required for the GTT write domain. Writes |
| 3913 | * to it immediately go to main memory as far as we know, so there's |
| 3914 | * no chipset flush. It also doesn't land in render cache. |
| 3915 | * |
| 3916 | * However, we do have to enforce the order so that all writes through |
| 3917 | * the GTT land before any writes to the device, such as updates to |
| 3918 | * the GATT itself. |
| 3919 | */ |
| 3920 | wmb(); |
| 3921 | |
| 3922 | old_write_domain = obj->base.write_domain; |
| 3923 | obj->base.write_domain = 0; |
| 3924 | |
| 3925 | intel_fb_obj_flush(obj, false); |
| 3926 | |
| 3927 | trace_i915_gem_object_change_domain(obj, |
| 3928 | obj->base.read_domains, |
| 3929 | old_write_domain); |
| 3930 | } |
| 3931 | |
| 3932 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3933 | static void |
| 3934 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
| 3935 | { |
| 3936 | uint32_t old_write_domain; |
| 3937 | |
| 3938 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
| 3939 | return; |
| 3940 | |
| 3941 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 3942 | i915_gem_chipset_flush(obj->base.dev); |
| 3943 | |
| 3944 | old_write_domain = obj->base.write_domain; |
| 3945 | obj->base.write_domain = 0; |
| 3946 | |
| 3947 | intel_fb_obj_flush(obj, false); |
| 3948 | |
| 3949 | trace_i915_gem_object_change_domain(obj, |
| 3950 | obj->base.read_domains, |
| 3951 | old_write_domain); |
| 3952 | } |
| 3953 | |
| 3954 | /** |
| 3955 | * Moves a single object to the GTT read, and possibly write domain. |
| 3956 | * |
| 3957 | * This function returns when the move is complete, including waiting on |
| 3958 | * flushes to occur. |
| 3959 | */ |
| 3960 | int |
| 3961 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
| 3962 | { |
| 3963 | uint32_t old_write_domain, old_read_domains; |
| 3964 | struct i915_vma *vma; |
| 3965 | int ret; |
| 3966 | |
| 3967 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3968 | return 0; |
| 3969 | |
| 3970 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 3971 | if (ret) |
| 3972 | return ret; |
| 3973 | |
| 3974 | /* Flush and acquire obj->pages so that we are coherent through |
| 3975 | * direct access in memory with previous cached writes through |
| 3976 | * shmemfs and that our cache domain tracking remains valid. |
| 3977 | * For example, if the obj->filp was moved to swap without us |
| 3978 | * being notified and releasing the pages, we would mistakenly |
| 3979 | * continue to assume that the obj remained out of the CPU cached |
| 3980 | * domain. |
| 3981 | */ |
| 3982 | ret = i915_gem_object_get_pages(obj); |
| 3983 | if (ret) |
| 3984 | return ret; |
| 3985 | |
| 3986 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3987 | |
| 3988 | /* Serialise direct access to this object with the barriers for |
| 3989 | * coherent writes from the GPU, by effectively invalidating the |
| 3990 | * GTT domain upon first access. |
| 3991 | */ |
| 3992 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3993 | mb(); |
| 3994 | |
| 3995 | old_write_domain = obj->base.write_domain; |
| 3996 | old_read_domains = obj->base.read_domains; |
| 3997 | |
| 3998 | /* It should now be out of any other write domains, and we can update |
| 3999 | * the domain values for our changes. |
| 4000 | */ |
| 4001 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 4002 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
| 4003 | if (write) { |
| 4004 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 4005 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 4006 | obj->dirty = 1; |
| 4007 | } |
| 4008 | |
| 4009 | if (write) |
| 4010 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
| 4011 | |
| 4012 | trace_i915_gem_object_change_domain(obj, |
| 4013 | old_read_domains, |
| 4014 | old_write_domain); |
| 4015 | |
| 4016 | /* And bump the LRU for this access */ |
| 4017 | vma = i915_gem_obj_to_ggtt(obj); |
| 4018 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) |
| 4019 | list_move_tail(&vma->mm_list, |
| 4020 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
| 4021 | |
| 4022 | return 0; |
| 4023 | } |
| 4024 | |
| 4025 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 4026 | enum i915_cache_level cache_level) |
| 4027 | { |
| 4028 | struct drm_device *dev = obj->base.dev; |
| 4029 | struct i915_vma *vma, *next; |
| 4030 | int ret; |
| 4031 | |
| 4032 | if (obj->cache_level == cache_level) |
| 4033 | return 0; |
| 4034 | |
| 4035 | if (i915_gem_obj_is_pinned(obj)) { |
| 4036 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 4037 | return -EBUSY; |
| 4038 | } |
| 4039 | |
| 4040 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
| 4041 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
| 4042 | ret = i915_vma_unbind(vma); |
| 4043 | if (ret) |
| 4044 | return ret; |
| 4045 | } |
| 4046 | } |
| 4047 | |
| 4048 | if (i915_gem_obj_bound_any(obj)) { |
| 4049 | ret = i915_gem_object_wait_rendering(obj, false); |
| 4050 | if (ret) |
| 4051 | return ret; |
| 4052 | |
| 4053 | i915_gem_object_finish_gtt(obj); |
| 4054 | |
| 4055 | /* Before SandyBridge, you could not use tiling or fence |
| 4056 | * registers with snooped memory, so relinquish any fences |
| 4057 | * currently pointing to our region in the aperture. |
| 4058 | */ |
| 4059 | if (INTEL_INFO(dev)->gen < 6) { |
| 4060 | ret = i915_gem_object_put_fence(obj); |
| 4061 | if (ret) |
| 4062 | return ret; |
| 4063 | } |
| 4064 | |
| 4065 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4066 | if (drm_mm_node_allocated(&vma->node)) { |
| 4067 | ret = i915_vma_bind(vma, cache_level, |
| 4068 | PIN_UPDATE); |
| 4069 | if (ret) |
| 4070 | return ret; |
| 4071 | } |
| 4072 | } |
| 4073 | |
| 4074 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4075 | vma->node.color = cache_level; |
| 4076 | obj->cache_level = cache_level; |
| 4077 | |
| 4078 | if (obj->cache_dirty && |
| 4079 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 4080 | cpu_write_needs_clflush(obj)) { |
| 4081 | if (i915_gem_clflush_object(obj, true)) |
| 4082 | i915_gem_chipset_flush(obj->base.dev); |
| 4083 | } |
| 4084 | |
| 4085 | return 0; |
| 4086 | } |
| 4087 | |
| 4088 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 4089 | struct drm_file *file) |
| 4090 | { |
| 4091 | struct drm_i915_gem_caching *args = data; |
| 4092 | struct drm_i915_gem_object *obj; |
| 4093 | |
| 4094 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4095 | if (&obj->base == NULL) |
| 4096 | return -ENOENT; |
| 4097 | |
| 4098 | switch (obj->cache_level) { |
| 4099 | case I915_CACHE_LLC: |
| 4100 | case I915_CACHE_L3_LLC: |
| 4101 | args->caching = I915_CACHING_CACHED; |
| 4102 | break; |
| 4103 | |
| 4104 | case I915_CACHE_WT: |
| 4105 | args->caching = I915_CACHING_DISPLAY; |
| 4106 | break; |
| 4107 | |
| 4108 | default: |
| 4109 | args->caching = I915_CACHING_NONE; |
| 4110 | break; |
| 4111 | } |
| 4112 | |
| 4113 | drm_gem_object_unreference_unlocked(&obj->base); |
| 4114 | return 0; |
| 4115 | } |
| 4116 | |
| 4117 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 4118 | struct drm_file *file) |
| 4119 | { |
| 4120 | struct drm_i915_gem_caching *args = data; |
| 4121 | struct drm_i915_gem_object *obj; |
| 4122 | enum i915_cache_level level; |
| 4123 | int ret; |
| 4124 | |
| 4125 | switch (args->caching) { |
| 4126 | case I915_CACHING_NONE: |
| 4127 | level = I915_CACHE_NONE; |
| 4128 | break; |
| 4129 | case I915_CACHING_CACHED: |
| 4130 | level = I915_CACHE_LLC; |
| 4131 | break; |
| 4132 | case I915_CACHING_DISPLAY: |
| 4133 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 4134 | break; |
| 4135 | default: |
| 4136 | return -EINVAL; |
| 4137 | } |
| 4138 | |
| 4139 | ret = i915_mutex_lock_interruptible(dev); |
| 4140 | if (ret) |
| 4141 | return ret; |
| 4142 | |
| 4143 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4144 | if (&obj->base == NULL) { |
| 4145 | ret = -ENOENT; |
| 4146 | goto unlock; |
| 4147 | } |
| 4148 | |
| 4149 | ret = i915_gem_object_set_cache_level(obj, level); |
| 4150 | |
| 4151 | drm_gem_object_unreference(&obj->base); |
| 4152 | unlock: |
| 4153 | mutex_unlock(&dev->struct_mutex); |
| 4154 | return ret; |
| 4155 | } |
| 4156 | |
| 4157 | /* |
| 4158 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 4159 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 4160 | * any flushes to be pipelined (for pageflips). |
| 4161 | */ |
| 4162 | int |
| 4163 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 4164 | u32 alignment, |
| 4165 | struct intel_engine_cs *pipelined, |
| 4166 | struct drm_i915_gem_request **pipelined_request, |
| 4167 | const struct i915_ggtt_view *view) |
| 4168 | { |
| 4169 | u32 old_read_domains, old_write_domain; |
| 4170 | int ret; |
| 4171 | |
| 4172 | ret = i915_gem_object_sync(obj, pipelined, pipelined_request); |
| 4173 | if (ret) |
| 4174 | return ret; |
| 4175 | |
| 4176 | /* Mark the pin_display early so that we account for the |
| 4177 | * display coherency whilst setting up the cache domains. |
| 4178 | */ |
| 4179 | obj->pin_display++; |
| 4180 | |
| 4181 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 4182 | * a result, we make sure that the pinning that is about to occur is |
| 4183 | * done with uncached PTEs. This is lowest common denominator for all |
| 4184 | * chipsets. |
| 4185 | * |
| 4186 | * However for gen6+, we could do better by using the GFDT bit instead |
| 4187 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 4188 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 4189 | */ |
| 4190 | ret = i915_gem_object_set_cache_level(obj, |
| 4191 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
| 4192 | if (ret) |
| 4193 | goto err_unpin_display; |
| 4194 | |
| 4195 | /* As the user may map the buffer once pinned in the display plane |
| 4196 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 4197 | * always use map_and_fenceable for all scanout buffers. |
| 4198 | */ |
| 4199 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
| 4200 | view->type == I915_GGTT_VIEW_NORMAL ? |
| 4201 | PIN_MAPPABLE : 0); |
| 4202 | if (ret) |
| 4203 | goto err_unpin_display; |
| 4204 | |
| 4205 | i915_gem_object_flush_cpu_write_domain(obj); |
| 4206 | |
| 4207 | old_write_domain = obj->base.write_domain; |
| 4208 | old_read_domains = obj->base.read_domains; |
| 4209 | |
| 4210 | /* It should now be out of any other write domains, and we can update |
| 4211 | * the domain values for our changes. |
| 4212 | */ |
| 4213 | obj->base.write_domain = 0; |
| 4214 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
| 4215 | |
| 4216 | trace_i915_gem_object_change_domain(obj, |
| 4217 | old_read_domains, |
| 4218 | old_write_domain); |
| 4219 | |
| 4220 | return 0; |
| 4221 | |
| 4222 | err_unpin_display: |
| 4223 | obj->pin_display--; |
| 4224 | return ret; |
| 4225 | } |
| 4226 | |
| 4227 | void |
| 4228 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
| 4229 | const struct i915_ggtt_view *view) |
| 4230 | { |
| 4231 | if (WARN_ON(obj->pin_display == 0)) |
| 4232 | return; |
| 4233 | |
| 4234 | i915_gem_object_ggtt_unpin_view(obj, view); |
| 4235 | |
| 4236 | obj->pin_display--; |
| 4237 | } |
| 4238 | |
| 4239 | /** |
| 4240 | * Moves a single object to the CPU read, and possibly write domain. |
| 4241 | * |
| 4242 | * This function returns when the move is complete, including waiting on |
| 4243 | * flushes to occur. |
| 4244 | */ |
| 4245 | int |
| 4246 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
| 4247 | { |
| 4248 | uint32_t old_write_domain, old_read_domains; |
| 4249 | int ret; |
| 4250 | |
| 4251 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 4252 | return 0; |
| 4253 | |
| 4254 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 4255 | if (ret) |
| 4256 | return ret; |
| 4257 | |
| 4258 | i915_gem_object_flush_gtt_write_domain(obj); |
| 4259 | |
| 4260 | old_write_domain = obj->base.write_domain; |
| 4261 | old_read_domains = obj->base.read_domains; |
| 4262 | |
| 4263 | /* Flush the CPU cache if it's still invalid. */ |
| 4264 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 4265 | i915_gem_clflush_object(obj, false); |
| 4266 | |
| 4267 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
| 4268 | } |
| 4269 | |
| 4270 | /* It should now be out of any other write domains, and we can update |
| 4271 | * the domain values for our changes. |
| 4272 | */ |
| 4273 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 4274 | |
| 4275 | /* If we're writing through the CPU, then the GPU read domains will |
| 4276 | * need to be invalidated at next use. |
| 4277 | */ |
| 4278 | if (write) { |
| 4279 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4280 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4281 | } |
| 4282 | |
| 4283 | if (write) |
| 4284 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
| 4285 | |
| 4286 | trace_i915_gem_object_change_domain(obj, |
| 4287 | old_read_domains, |
| 4288 | old_write_domain); |
| 4289 | |
| 4290 | return 0; |
| 4291 | } |
| 4292 | |
| 4293 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4294 | * emitted over 20 msec ago. |
| 4295 | * |
| 4296 | * Note that if we were to use the current jiffies each time around the loop, |
| 4297 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4298 | * render a frame was over 20ms. |
| 4299 | * |
| 4300 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4301 | * relatively low latency when blocking on a particular request to finish. |
| 4302 | */ |
| 4303 | static int |
| 4304 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
| 4305 | { |
| 4306 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4307 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 4308 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
| 4309 | struct drm_i915_gem_request *request, *target = NULL; |
| 4310 | unsigned reset_counter; |
| 4311 | int ret; |
| 4312 | |
| 4313 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4314 | if (ret) |
| 4315 | return ret; |
| 4316 | |
| 4317 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 4318 | if (ret) |
| 4319 | return ret; |
| 4320 | |
| 4321 | spin_lock(&file_priv->mm.lock); |
| 4322 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
| 4323 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4324 | break; |
| 4325 | |
| 4326 | target = request; |
| 4327 | } |
| 4328 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
| 4329 | if (target) |
| 4330 | i915_gem_request_reference(target); |
| 4331 | spin_unlock(&file_priv->mm.lock); |
| 4332 | |
| 4333 | if (target == NULL) |
| 4334 | return 0; |
| 4335 | |
| 4336 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
| 4337 | if (ret == 0) |
| 4338 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
| 4339 | |
| 4340 | i915_gem_request_unreference__unlocked(target); |
| 4341 | |
| 4342 | return ret; |
| 4343 | } |
| 4344 | |
| 4345 | static bool |
| 4346 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4347 | { |
| 4348 | struct drm_i915_gem_object *obj = vma->obj; |
| 4349 | |
| 4350 | if (alignment && |
| 4351 | vma->node.start & (alignment - 1)) |
| 4352 | return true; |
| 4353 | |
| 4354 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4355 | return true; |
| 4356 | |
| 4357 | if (flags & PIN_OFFSET_BIAS && |
| 4358 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4359 | return true; |
| 4360 | |
| 4361 | return false; |
| 4362 | } |
| 4363 | |
| 4364 | static int |
| 4365 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, |
| 4366 | struct i915_address_space *vm, |
| 4367 | const struct i915_ggtt_view *ggtt_view, |
| 4368 | uint32_t alignment, |
| 4369 | uint64_t flags) |
| 4370 | { |
| 4371 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4372 | struct i915_vma *vma; |
| 4373 | unsigned bound; |
| 4374 | int ret; |
| 4375 | |
| 4376 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4377 | return -ENODEV; |
| 4378 | |
| 4379 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
| 4380 | return -EINVAL; |
| 4381 | |
| 4382 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
| 4383 | return -EINVAL; |
| 4384 | |
| 4385 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
| 4386 | return -EINVAL; |
| 4387 | |
| 4388 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : |
| 4389 | i915_gem_obj_to_vma(obj, vm); |
| 4390 | |
| 4391 | if (IS_ERR(vma)) |
| 4392 | return PTR_ERR(vma); |
| 4393 | |
| 4394 | if (vma) { |
| 4395 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4396 | return -EBUSY; |
| 4397 | |
| 4398 | if (i915_vma_misplaced(vma, alignment, flags)) { |
| 4399 | unsigned long offset; |
| 4400 | offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : |
| 4401 | i915_gem_obj_offset(obj, vm); |
| 4402 | WARN(vma->pin_count, |
| 4403 | "bo is already pinned in %s with incorrect alignment:" |
| 4404 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
| 4405 | " obj->map_and_fenceable=%d\n", |
| 4406 | ggtt_view ? "ggtt" : "ppgtt", |
| 4407 | offset, |
| 4408 | alignment, |
| 4409 | !!(flags & PIN_MAPPABLE), |
| 4410 | obj->map_and_fenceable); |
| 4411 | ret = i915_vma_unbind(vma); |
| 4412 | if (ret) |
| 4413 | return ret; |
| 4414 | |
| 4415 | vma = NULL; |
| 4416 | } |
| 4417 | } |
| 4418 | |
| 4419 | bound = vma ? vma->bound : 0; |
| 4420 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
| 4421 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
| 4422 | flags); |
| 4423 | if (IS_ERR(vma)) |
| 4424 | return PTR_ERR(vma); |
| 4425 | } else { |
| 4426 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
| 4427 | if (ret) |
| 4428 | return ret; |
| 4429 | } |
| 4430 | |
| 4431 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
| 4432 | (bound ^ vma->bound) & GLOBAL_BIND) { |
| 4433 | bool mappable, fenceable; |
| 4434 | u32 fence_size, fence_alignment; |
| 4435 | |
| 4436 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
| 4437 | obj->base.size, |
| 4438 | obj->tiling_mode); |
| 4439 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
| 4440 | obj->base.size, |
| 4441 | obj->tiling_mode, |
| 4442 | true); |
| 4443 | |
| 4444 | fenceable = (vma->node.size == fence_size && |
| 4445 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 4446 | |
| 4447 | mappable = (vma->node.start + fence_size <= |
| 4448 | dev_priv->gtt.mappable_end); |
| 4449 | |
| 4450 | obj->map_and_fenceable = mappable && fenceable; |
| 4451 | |
| 4452 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 4453 | } |
| 4454 | |
| 4455 | vma->pin_count++; |
| 4456 | return 0; |
| 4457 | } |
| 4458 | |
| 4459 | int |
| 4460 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4461 | struct i915_address_space *vm, |
| 4462 | uint32_t alignment, |
| 4463 | uint64_t flags) |
| 4464 | { |
| 4465 | return i915_gem_object_do_pin(obj, vm, |
| 4466 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, |
| 4467 | alignment, flags); |
| 4468 | } |
| 4469 | |
| 4470 | int |
| 4471 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
| 4472 | const struct i915_ggtt_view *view, |
| 4473 | uint32_t alignment, |
| 4474 | uint64_t flags) |
| 4475 | { |
| 4476 | if (WARN_ONCE(!view, "no view specified")) |
| 4477 | return -EINVAL; |
| 4478 | |
| 4479 | return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, |
| 4480 | alignment, flags | PIN_GLOBAL); |
| 4481 | } |
| 4482 | |
| 4483 | void |
| 4484 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
| 4485 | const struct i915_ggtt_view *view) |
| 4486 | { |
| 4487 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
| 4488 | |
| 4489 | BUG_ON(!vma); |
| 4490 | WARN_ON(vma->pin_count == 0); |
| 4491 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
| 4492 | |
| 4493 | --vma->pin_count; |
| 4494 | } |
| 4495 | |
| 4496 | bool |
| 4497 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 4498 | { |
| 4499 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4500 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4501 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); |
| 4502 | |
| 4503 | WARN_ON(!ggtt_vma || |
| 4504 | dev_priv->fence_regs[obj->fence_reg].pin_count > |
| 4505 | ggtt_vma->pin_count); |
| 4506 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
| 4507 | return true; |
| 4508 | } else |
| 4509 | return false; |
| 4510 | } |
| 4511 | |
| 4512 | void |
| 4513 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 4514 | { |
| 4515 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 4516 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 4517 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
| 4518 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 4519 | } |
| 4520 | } |
| 4521 | |
| 4522 | int |
| 4523 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4524 | struct drm_file *file) |
| 4525 | { |
| 4526 | struct drm_i915_gem_busy *args = data; |
| 4527 | struct drm_i915_gem_object *obj; |
| 4528 | int ret; |
| 4529 | |
| 4530 | ret = i915_mutex_lock_interruptible(dev); |
| 4531 | if (ret) |
| 4532 | return ret; |
| 4533 | |
| 4534 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4535 | if (&obj->base == NULL) { |
| 4536 | ret = -ENOENT; |
| 4537 | goto unlock; |
| 4538 | } |
| 4539 | |
| 4540 | /* Count all active objects as busy, even if they are currently not used |
| 4541 | * by the gpu. Users of this interface expect objects to eventually |
| 4542 | * become non-busy without any further actions, therefore emit any |
| 4543 | * necessary flushes here. |
| 4544 | */ |
| 4545 | ret = i915_gem_object_flush_active(obj); |
| 4546 | if (ret) |
| 4547 | goto unref; |
| 4548 | |
| 4549 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 4550 | args->busy = obj->active << 16; |
| 4551 | if (obj->last_write_req) |
| 4552 | args->busy |= obj->last_write_req->ring->id; |
| 4553 | |
| 4554 | unref: |
| 4555 | drm_gem_object_unreference(&obj->base); |
| 4556 | unlock: |
| 4557 | mutex_unlock(&dev->struct_mutex); |
| 4558 | return ret; |
| 4559 | } |
| 4560 | |
| 4561 | int |
| 4562 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4563 | struct drm_file *file_priv) |
| 4564 | { |
| 4565 | return i915_gem_ring_throttle(dev, file_priv); |
| 4566 | } |
| 4567 | |
| 4568 | int |
| 4569 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4570 | struct drm_file *file_priv) |
| 4571 | { |
| 4572 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4573 | struct drm_i915_gem_madvise *args = data; |
| 4574 | struct drm_i915_gem_object *obj; |
| 4575 | int ret; |
| 4576 | |
| 4577 | switch (args->madv) { |
| 4578 | case I915_MADV_DONTNEED: |
| 4579 | case I915_MADV_WILLNEED: |
| 4580 | break; |
| 4581 | default: |
| 4582 | return -EINVAL; |
| 4583 | } |
| 4584 | |
| 4585 | ret = i915_mutex_lock_interruptible(dev); |
| 4586 | if (ret) |
| 4587 | return ret; |
| 4588 | |
| 4589 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
| 4590 | if (&obj->base == NULL) { |
| 4591 | ret = -ENOENT; |
| 4592 | goto unlock; |
| 4593 | } |
| 4594 | |
| 4595 | if (i915_gem_obj_is_pinned(obj)) { |
| 4596 | ret = -EINVAL; |
| 4597 | goto out; |
| 4598 | } |
| 4599 | |
| 4600 | if (obj->pages && |
| 4601 | obj->tiling_mode != I915_TILING_NONE && |
| 4602 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
| 4603 | if (obj->madv == I915_MADV_WILLNEED) |
| 4604 | i915_gem_object_unpin_pages(obj); |
| 4605 | if (args->madv == I915_MADV_WILLNEED) |
| 4606 | i915_gem_object_pin_pages(obj); |
| 4607 | } |
| 4608 | |
| 4609 | if (obj->madv != __I915_MADV_PURGED) |
| 4610 | obj->madv = args->madv; |
| 4611 | |
| 4612 | /* if the object is no longer attached, discard its backing storage */ |
| 4613 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
| 4614 | i915_gem_object_truncate(obj); |
| 4615 | |
| 4616 | args->retained = obj->madv != __I915_MADV_PURGED; |
| 4617 | |
| 4618 | out: |
| 4619 | drm_gem_object_unreference(&obj->base); |
| 4620 | unlock: |
| 4621 | mutex_unlock(&dev->struct_mutex); |
| 4622 | return ret; |
| 4623 | } |
| 4624 | |
| 4625 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4626 | const struct drm_i915_gem_object_ops *ops) |
| 4627 | { |
| 4628 | int i; |
| 4629 | |
| 4630 | INIT_LIST_HEAD(&obj->global_list); |
| 4631 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4632 | INIT_LIST_HEAD(&obj->ring_list[i]); |
| 4633 | INIT_LIST_HEAD(&obj->obj_exec_link); |
| 4634 | INIT_LIST_HEAD(&obj->vma_list); |
| 4635 | INIT_LIST_HEAD(&obj->batch_pool_link); |
| 4636 | |
| 4637 | obj->ops = ops; |
| 4638 | |
| 4639 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4640 | obj->madv = I915_MADV_WILLNEED; |
| 4641 | |
| 4642 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4643 | } |
| 4644 | |
| 4645 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4646 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4647 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4648 | }; |
| 4649 | |
| 4650 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4651 | size_t size) |
| 4652 | { |
| 4653 | struct drm_i915_gem_object *obj; |
| 4654 | struct address_space *mapping; |
| 4655 | gfp_t mask; |
| 4656 | |
| 4657 | obj = i915_gem_object_alloc(dev); |
| 4658 | if (obj == NULL) |
| 4659 | return NULL; |
| 4660 | |
| 4661 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4662 | i915_gem_object_free(obj); |
| 4663 | return NULL; |
| 4664 | } |
| 4665 | |
| 4666 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4667 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4668 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4669 | mask &= ~__GFP_HIGHMEM; |
| 4670 | mask |= __GFP_DMA32; |
| 4671 | } |
| 4672 | |
| 4673 | mapping = file_inode(obj->base.filp)->i_mapping; |
| 4674 | mapping_set_gfp_mask(mapping, mask); |
| 4675 | |
| 4676 | i915_gem_object_init(obj, &i915_gem_object_ops); |
| 4677 | |
| 4678 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4679 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4680 | |
| 4681 | if (HAS_LLC(dev)) { |
| 4682 | /* On some devices, we can have the GPU use the LLC (the CPU |
| 4683 | * cache) for about a 10% performance improvement |
| 4684 | * compared to uncached. Graphics requests other than |
| 4685 | * display scanout are coherent with the CPU in |
| 4686 | * accessing this cache. This means in this mode we |
| 4687 | * don't need to clflush on the CPU side, and on the |
| 4688 | * GPU side we only need to flush internal caches to |
| 4689 | * get data visible to the CPU. |
| 4690 | * |
| 4691 | * However, we maintain the display planes as UC, and so |
| 4692 | * need to rebind when first used as such. |
| 4693 | */ |
| 4694 | obj->cache_level = I915_CACHE_LLC; |
| 4695 | } else |
| 4696 | obj->cache_level = I915_CACHE_NONE; |
| 4697 | |
| 4698 | trace_i915_gem_object_create(obj); |
| 4699 | |
| 4700 | return obj; |
| 4701 | } |
| 4702 | |
| 4703 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4704 | { |
| 4705 | /* If we are the last user of the backing storage (be it shmemfs |
| 4706 | * pages or stolen etc), we know that the pages are going to be |
| 4707 | * immediately released. In this case, we can then skip copying |
| 4708 | * back the contents from the GPU. |
| 4709 | */ |
| 4710 | |
| 4711 | if (obj->madv != I915_MADV_WILLNEED) |
| 4712 | return false; |
| 4713 | |
| 4714 | if (obj->base.filp == NULL) |
| 4715 | return true; |
| 4716 | |
| 4717 | /* At first glance, this looks racy, but then again so would be |
| 4718 | * userspace racing mmap against close. However, the first external |
| 4719 | * reference to the filp can only be obtained through the |
| 4720 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4721 | * acquiring such a reference whilst we are in the middle of |
| 4722 | * freeing the object. |
| 4723 | */ |
| 4724 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4725 | } |
| 4726 | |
| 4727 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
| 4728 | { |
| 4729 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 4730 | struct drm_device *dev = obj->base.dev; |
| 4731 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4732 | struct i915_vma *vma, *next; |
| 4733 | |
| 4734 | intel_runtime_pm_get(dev_priv); |
| 4735 | |
| 4736 | trace_i915_gem_object_destroy(obj); |
| 4737 | |
| 4738 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
| 4739 | int ret; |
| 4740 | |
| 4741 | vma->pin_count = 0; |
| 4742 | ret = i915_vma_unbind(vma); |
| 4743 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4744 | bool was_interruptible; |
| 4745 | |
| 4746 | was_interruptible = dev_priv->mm.interruptible; |
| 4747 | dev_priv->mm.interruptible = false; |
| 4748 | |
| 4749 | WARN_ON(i915_vma_unbind(vma)); |
| 4750 | |
| 4751 | dev_priv->mm.interruptible = was_interruptible; |
| 4752 | } |
| 4753 | } |
| 4754 | |
| 4755 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4756 | * before progressing. */ |
| 4757 | if (obj->stolen) |
| 4758 | i915_gem_object_unpin_pages(obj); |
| 4759 | |
| 4760 | WARN_ON(obj->frontbuffer_bits); |
| 4761 | |
| 4762 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
| 4763 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
| 4764 | obj->tiling_mode != I915_TILING_NONE) |
| 4765 | i915_gem_object_unpin_pages(obj); |
| 4766 | |
| 4767 | if (WARN_ON(obj->pages_pin_count)) |
| 4768 | obj->pages_pin_count = 0; |
| 4769 | if (discard_backing_storage(obj)) |
| 4770 | obj->madv = I915_MADV_DONTNEED; |
| 4771 | i915_gem_object_put_pages(obj); |
| 4772 | i915_gem_object_free_mmap_offset(obj); |
| 4773 | |
| 4774 | BUG_ON(obj->pages); |
| 4775 | |
| 4776 | if (obj->base.import_attach) |
| 4777 | drm_prime_gem_destroy(&obj->base, NULL); |
| 4778 | |
| 4779 | if (obj->ops->release) |
| 4780 | obj->ops->release(obj); |
| 4781 | |
| 4782 | drm_gem_object_release(&obj->base); |
| 4783 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
| 4784 | |
| 4785 | kfree(obj->bit_17); |
| 4786 | i915_gem_object_free(obj); |
| 4787 | |
| 4788 | intel_runtime_pm_put(dev_priv); |
| 4789 | } |
| 4790 | |
| 4791 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 4792 | struct i915_address_space *vm) |
| 4793 | { |
| 4794 | struct i915_vma *vma; |
| 4795 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 4796 | if (i915_is_ggtt(vma->vm) && |
| 4797 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 4798 | continue; |
| 4799 | if (vma->vm == vm) |
| 4800 | return vma; |
| 4801 | } |
| 4802 | return NULL; |
| 4803 | } |
| 4804 | |
| 4805 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
| 4806 | const struct i915_ggtt_view *view) |
| 4807 | { |
| 4808 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
| 4809 | struct i915_vma *vma; |
| 4810 | |
| 4811 | if (WARN_ONCE(!view, "no view specified")) |
| 4812 | return ERR_PTR(-EINVAL); |
| 4813 | |
| 4814 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4815 | if (vma->vm == ggtt && |
| 4816 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
| 4817 | return vma; |
| 4818 | return NULL; |
| 4819 | } |
| 4820 | |
| 4821 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4822 | { |
| 4823 | struct i915_address_space *vm = NULL; |
| 4824 | WARN_ON(vma->node.allocated); |
| 4825 | |
| 4826 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4827 | if (!list_empty(&vma->exec_list)) |
| 4828 | return; |
| 4829 | |
| 4830 | vm = vma->vm; |
| 4831 | |
| 4832 | if (!i915_is_ggtt(vm)) |
| 4833 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); |
| 4834 | |
| 4835 | list_del(&vma->vma_link); |
| 4836 | |
| 4837 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
| 4838 | } |
| 4839 | |
| 4840 | static void |
| 4841 | i915_gem_stop_ringbuffers(struct drm_device *dev) |
| 4842 | { |
| 4843 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4844 | struct intel_engine_cs *ring; |
| 4845 | int i; |
| 4846 | |
| 4847 | for_each_ring(ring, dev_priv, i) |
| 4848 | dev_priv->gt.stop_ring(ring); |
| 4849 | } |
| 4850 | |
| 4851 | int |
| 4852 | i915_gem_suspend(struct drm_device *dev) |
| 4853 | { |
| 4854 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4855 | int ret = 0; |
| 4856 | |
| 4857 | mutex_lock(&dev->struct_mutex); |
| 4858 | ret = i915_gpu_idle(dev); |
| 4859 | if (ret) |
| 4860 | goto err; |
| 4861 | |
| 4862 | i915_gem_retire_requests(dev); |
| 4863 | |
| 4864 | i915_gem_stop_ringbuffers(dev); |
| 4865 | mutex_unlock(&dev->struct_mutex); |
| 4866 | |
| 4867 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
| 4868 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4869 | flush_delayed_work(&dev_priv->mm.idle_work); |
| 4870 | |
| 4871 | /* Assert that we sucessfully flushed all the work and |
| 4872 | * reset the GPU back to its idle, low power state. |
| 4873 | */ |
| 4874 | WARN_ON(dev_priv->mm.busy); |
| 4875 | |
| 4876 | return 0; |
| 4877 | |
| 4878 | err: |
| 4879 | mutex_unlock(&dev->struct_mutex); |
| 4880 | return ret; |
| 4881 | } |
| 4882 | |
| 4883 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
| 4884 | { |
| 4885 | struct drm_device *dev = ring->dev; |
| 4886 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4887 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4888 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
| 4889 | int i, ret; |
| 4890 | |
| 4891 | if (!HAS_L3_DPF(dev) || !remap_info) |
| 4892 | return 0; |
| 4893 | |
| 4894 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
| 4895 | if (ret) |
| 4896 | return ret; |
| 4897 | |
| 4898 | /* |
| 4899 | * Note: We do not worry about the concurrent register cacheline hang |
| 4900 | * here because no other code should access these registers other than |
| 4901 | * at initialization time. |
| 4902 | */ |
| 4903 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 4904 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 4905 | intel_ring_emit(ring, reg_base + i); |
| 4906 | intel_ring_emit(ring, remap_info[i/4]); |
| 4907 | } |
| 4908 | |
| 4909 | intel_ring_advance(ring); |
| 4910 | |
| 4911 | return ret; |
| 4912 | } |
| 4913 | |
| 4914 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4915 | { |
| 4916 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4917 | |
| 4918 | if (INTEL_INFO(dev)->gen < 5 || |
| 4919 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4920 | return; |
| 4921 | |
| 4922 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4923 | DISP_TILE_SURFACE_SWIZZLING); |
| 4924 | |
| 4925 | if (IS_GEN5(dev)) |
| 4926 | return; |
| 4927 | |
| 4928 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4929 | if (IS_GEN6(dev)) |
| 4930 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
| 4931 | else if (IS_GEN7(dev)) |
| 4932 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
| 4933 | else if (IS_GEN8(dev)) |
| 4934 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
| 4935 | else |
| 4936 | BUG(); |
| 4937 | } |
| 4938 | |
| 4939 | static bool |
| 4940 | intel_enable_blt(struct drm_device *dev) |
| 4941 | { |
| 4942 | if (!HAS_BLT(dev)) |
| 4943 | return false; |
| 4944 | |
| 4945 | /* The blitter was dysfunctional on early prototypes */ |
| 4946 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4947 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4948 | " graphics performance will be degraded.\n"); |
| 4949 | return false; |
| 4950 | } |
| 4951 | |
| 4952 | return true; |
| 4953 | } |
| 4954 | |
| 4955 | static void init_unused_ring(struct drm_device *dev, u32 base) |
| 4956 | { |
| 4957 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4958 | |
| 4959 | I915_WRITE(RING_CTL(base), 0); |
| 4960 | I915_WRITE(RING_HEAD(base), 0); |
| 4961 | I915_WRITE(RING_TAIL(base), 0); |
| 4962 | I915_WRITE(RING_START(base), 0); |
| 4963 | } |
| 4964 | |
| 4965 | static void init_unused_rings(struct drm_device *dev) |
| 4966 | { |
| 4967 | if (IS_I830(dev)) { |
| 4968 | init_unused_ring(dev, PRB1_BASE); |
| 4969 | init_unused_ring(dev, SRB0_BASE); |
| 4970 | init_unused_ring(dev, SRB1_BASE); |
| 4971 | init_unused_ring(dev, SRB2_BASE); |
| 4972 | init_unused_ring(dev, SRB3_BASE); |
| 4973 | } else if (IS_GEN2(dev)) { |
| 4974 | init_unused_ring(dev, SRB0_BASE); |
| 4975 | init_unused_ring(dev, SRB1_BASE); |
| 4976 | } else if (IS_GEN3(dev)) { |
| 4977 | init_unused_ring(dev, PRB1_BASE); |
| 4978 | init_unused_ring(dev, PRB2_BASE); |
| 4979 | } |
| 4980 | } |
| 4981 | |
| 4982 | int i915_gem_init_rings(struct drm_device *dev) |
| 4983 | { |
| 4984 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4985 | int ret; |
| 4986 | |
| 4987 | ret = intel_init_render_ring_buffer(dev); |
| 4988 | if (ret) |
| 4989 | return ret; |
| 4990 | |
| 4991 | if (HAS_BSD(dev)) { |
| 4992 | ret = intel_init_bsd_ring_buffer(dev); |
| 4993 | if (ret) |
| 4994 | goto cleanup_render_ring; |
| 4995 | } |
| 4996 | |
| 4997 | if (intel_enable_blt(dev)) { |
| 4998 | ret = intel_init_blt_ring_buffer(dev); |
| 4999 | if (ret) |
| 5000 | goto cleanup_bsd_ring; |
| 5001 | } |
| 5002 | |
| 5003 | if (HAS_VEBOX(dev)) { |
| 5004 | ret = intel_init_vebox_ring_buffer(dev); |
| 5005 | if (ret) |
| 5006 | goto cleanup_blt_ring; |
| 5007 | } |
| 5008 | |
| 5009 | if (HAS_BSD2(dev)) { |
| 5010 | ret = intel_init_bsd2_ring_buffer(dev); |
| 5011 | if (ret) |
| 5012 | goto cleanup_vebox_ring; |
| 5013 | } |
| 5014 | |
| 5015 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 5016 | if (ret) |
| 5017 | goto cleanup_bsd2_ring; |
| 5018 | |
| 5019 | return 0; |
| 5020 | |
| 5021 | cleanup_bsd2_ring: |
| 5022 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); |
| 5023 | cleanup_vebox_ring: |
| 5024 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
| 5025 | cleanup_blt_ring: |
| 5026 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 5027 | cleanup_bsd_ring: |
| 5028 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 5029 | cleanup_render_ring: |
| 5030 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 5031 | |
| 5032 | return ret; |
| 5033 | } |
| 5034 | |
| 5035 | int |
| 5036 | i915_gem_init_hw(struct drm_device *dev) |
| 5037 | { |
| 5038 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5039 | struct intel_engine_cs *ring; |
| 5040 | int ret, i, j; |
| 5041 | |
| 5042 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 5043 | return -EIO; |
| 5044 | |
| 5045 | /* Double layer security blanket, see i915_gem_init() */ |
| 5046 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 5047 | |
| 5048 | if (dev_priv->ellc_size) |
| 5049 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
| 5050 | |
| 5051 | if (IS_HASWELL(dev)) |
| 5052 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 5053 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
| 5054 | |
| 5055 | if (HAS_PCH_NOP(dev)) { |
| 5056 | if (IS_IVYBRIDGE(dev)) { |
| 5057 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 5058 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 5059 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 5060 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 5061 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 5062 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 5063 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 5064 | } |
| 5065 | } |
| 5066 | |
| 5067 | i915_gem_init_swizzling(dev); |
| 5068 | |
| 5069 | /* |
| 5070 | * At least 830 can leave some of the unused rings |
| 5071 | * "active" (ie. head != tail) after resume which |
| 5072 | * will prevent c3 entry. Makes sure all unused rings |
| 5073 | * are totally idle. |
| 5074 | */ |
| 5075 | init_unused_rings(dev); |
| 5076 | |
| 5077 | BUG_ON(!dev_priv->ring[RCS].default_context); |
| 5078 | |
| 5079 | ret = i915_ppgtt_init_hw(dev); |
| 5080 | if (ret) { |
| 5081 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); |
| 5082 | goto out; |
| 5083 | } |
| 5084 | |
| 5085 | /* Need to do basic initialisation of all rings first: */ |
| 5086 | for_each_ring(ring, dev_priv, i) { |
| 5087 | ret = ring->init_hw(ring); |
| 5088 | if (ret) |
| 5089 | goto out; |
| 5090 | } |
| 5091 | |
| 5092 | /* Now it is safe to go back round and do everything else: */ |
| 5093 | for_each_ring(ring, dev_priv, i) { |
| 5094 | struct drm_i915_gem_request *req; |
| 5095 | |
| 5096 | WARN_ON(!ring->default_context); |
| 5097 | |
| 5098 | ret = i915_gem_request_alloc(ring, ring->default_context, &req); |
| 5099 | if (ret) { |
| 5100 | i915_gem_cleanup_ringbuffer(dev); |
| 5101 | goto out; |
| 5102 | } |
| 5103 | |
| 5104 | if (ring->id == RCS) { |
| 5105 | for (j = 0; j < NUM_L3_SLICES(dev); j++) |
| 5106 | i915_gem_l3_remap(ring, j); |
| 5107 | } |
| 5108 | |
| 5109 | ret = i915_ppgtt_init_ring(req); |
| 5110 | if (ret && ret != -EIO) { |
| 5111 | DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret); |
| 5112 | i915_gem_request_cancel(req); |
| 5113 | i915_gem_cleanup_ringbuffer(dev); |
| 5114 | goto out; |
| 5115 | } |
| 5116 | |
| 5117 | ret = i915_gem_context_enable(req); |
| 5118 | if (ret && ret != -EIO) { |
| 5119 | DRM_ERROR("Context enable ring #%d failed %d\n", i, ret); |
| 5120 | i915_gem_request_cancel(req); |
| 5121 | i915_gem_cleanup_ringbuffer(dev); |
| 5122 | goto out; |
| 5123 | } |
| 5124 | |
| 5125 | i915_add_request_no_flush(ring); |
| 5126 | } |
| 5127 | |
| 5128 | out: |
| 5129 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 5130 | return ret; |
| 5131 | } |
| 5132 | |
| 5133 | int i915_gem_init(struct drm_device *dev) |
| 5134 | { |
| 5135 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5136 | int ret; |
| 5137 | |
| 5138 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
| 5139 | i915.enable_execlists); |
| 5140 | |
| 5141 | mutex_lock(&dev->struct_mutex); |
| 5142 | |
| 5143 | if (IS_VALLEYVIEW(dev)) { |
| 5144 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
| 5145 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
| 5146 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & |
| 5147 | VLV_GTLC_ALLOWWAKEACK), 10)) |
| 5148 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 5149 | } |
| 5150 | |
| 5151 | if (!i915.enable_execlists) { |
| 5152 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
| 5153 | dev_priv->gt.init_rings = i915_gem_init_rings; |
| 5154 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; |
| 5155 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; |
| 5156 | } else { |
| 5157 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
| 5158 | dev_priv->gt.init_rings = intel_logical_rings_init; |
| 5159 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; |
| 5160 | dev_priv->gt.stop_ring = intel_logical_ring_stop; |
| 5161 | } |
| 5162 | |
| 5163 | /* This is just a security blanket to placate dragons. |
| 5164 | * On some systems, we very sporadically observe that the first TLBs |
| 5165 | * used by the CS may be stale, despite us poking the TLB reset. If |
| 5166 | * we hold the forcewake during initialisation these problems |
| 5167 | * just magically go away. |
| 5168 | */ |
| 5169 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 5170 | |
| 5171 | ret = i915_gem_init_userptr(dev); |
| 5172 | if (ret) |
| 5173 | goto out_unlock; |
| 5174 | |
| 5175 | i915_gem_init_global_gtt(dev); |
| 5176 | |
| 5177 | ret = i915_gem_context_init(dev); |
| 5178 | if (ret) |
| 5179 | goto out_unlock; |
| 5180 | |
| 5181 | ret = dev_priv->gt.init_rings(dev); |
| 5182 | if (ret) |
| 5183 | goto out_unlock; |
| 5184 | |
| 5185 | ret = i915_gem_init_hw(dev); |
| 5186 | if (ret == -EIO) { |
| 5187 | /* Allow ring initialisation to fail by marking the GPU as |
| 5188 | * wedged. But we only want to do this where the GPU is angry, |
| 5189 | * for all other failure, such as an allocation failure, bail. |
| 5190 | */ |
| 5191 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
| 5192 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
| 5193 | ret = 0; |
| 5194 | } |
| 5195 | |
| 5196 | out_unlock: |
| 5197 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
| 5198 | mutex_unlock(&dev->struct_mutex); |
| 5199 | |
| 5200 | return ret; |
| 5201 | } |
| 5202 | |
| 5203 | void |
| 5204 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 5205 | { |
| 5206 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5207 | struct intel_engine_cs *ring; |
| 5208 | int i; |
| 5209 | |
| 5210 | for_each_ring(ring, dev_priv, i) |
| 5211 | dev_priv->gt.cleanup_ring(ring); |
| 5212 | } |
| 5213 | |
| 5214 | static void |
| 5215 | init_ring_lists(struct intel_engine_cs *ring) |
| 5216 | { |
| 5217 | INIT_LIST_HEAD(&ring->active_list); |
| 5218 | INIT_LIST_HEAD(&ring->request_list); |
| 5219 | } |
| 5220 | |
| 5221 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 5222 | struct i915_address_space *vm) |
| 5223 | { |
| 5224 | if (!i915_is_ggtt(vm)) |
| 5225 | drm_mm_init(&vm->mm, vm->start, vm->total); |
| 5226 | vm->dev = dev_priv->dev; |
| 5227 | INIT_LIST_HEAD(&vm->active_list); |
| 5228 | INIT_LIST_HEAD(&vm->inactive_list); |
| 5229 | INIT_LIST_HEAD(&vm->global_link); |
| 5230 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
| 5231 | } |
| 5232 | |
| 5233 | void |
| 5234 | i915_gem_load(struct drm_device *dev) |
| 5235 | { |
| 5236 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5237 | int i; |
| 5238 | |
| 5239 | dev_priv->objects = |
| 5240 | kmem_cache_create("i915_gem_object", |
| 5241 | sizeof(struct drm_i915_gem_object), 0, |
| 5242 | SLAB_HWCACHE_ALIGN, |
| 5243 | NULL); |
| 5244 | dev_priv->vmas = |
| 5245 | kmem_cache_create("i915_gem_vma", |
| 5246 | sizeof(struct i915_vma), 0, |
| 5247 | SLAB_HWCACHE_ALIGN, |
| 5248 | NULL); |
| 5249 | dev_priv->requests = |
| 5250 | kmem_cache_create("i915_gem_request", |
| 5251 | sizeof(struct drm_i915_gem_request), 0, |
| 5252 | SLAB_HWCACHE_ALIGN, |
| 5253 | NULL); |
| 5254 | |
| 5255 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 5256 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 5257 | |
| 5258 | INIT_LIST_HEAD(&dev_priv->context_list); |
| 5259 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 5260 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
| 5261 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 5262 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 5263 | init_ring_lists(&dev_priv->ring[i]); |
| 5264 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
| 5265 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
| 5266 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 5267 | i915_gem_retire_work_handler); |
| 5268 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 5269 | i915_gem_idle_work_handler); |
| 5270 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
| 5271 | |
| 5272 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 5273 | |
| 5274 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 5275 | dev_priv->num_fence_regs = 32; |
| 5276 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 5277 | dev_priv->num_fence_regs = 16; |
| 5278 | else |
| 5279 | dev_priv->num_fence_regs = 8; |
| 5280 | |
| 5281 | if (intel_vgpu_active(dev)) |
| 5282 | dev_priv->num_fence_regs = |
| 5283 | I915_READ(vgtif_reg(avail_rs.fence_num)); |
| 5284 | |
| 5285 | /* Initialize fence registers to zero */ |
| 5286 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 5287 | i915_gem_restore_fences(dev); |
| 5288 | |
| 5289 | i915_gem_detect_bit_6_swizzle(dev); |
| 5290 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
| 5291 | |
| 5292 | dev_priv->mm.interruptible = true; |
| 5293 | |
| 5294 | i915_gem_shrinker_init(dev_priv); |
| 5295 | |
| 5296 | mutex_init(&dev_priv->fb_tracking.lock); |
| 5297 | } |
| 5298 | |
| 5299 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
| 5300 | { |
| 5301 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 5302 | |
| 5303 | /* Clean up our request list when the client is going away, so that |
| 5304 | * later retire_requests won't dereference our soon-to-be-gone |
| 5305 | * file_priv. |
| 5306 | */ |
| 5307 | spin_lock(&file_priv->mm.lock); |
| 5308 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5309 | struct drm_i915_gem_request *request; |
| 5310 | |
| 5311 | request = list_first_entry(&file_priv->mm.request_list, |
| 5312 | struct drm_i915_gem_request, |
| 5313 | client_list); |
| 5314 | list_del(&request->client_list); |
| 5315 | request->file_priv = NULL; |
| 5316 | } |
| 5317 | spin_unlock(&file_priv->mm.lock); |
| 5318 | |
| 5319 | if (!list_empty(&file_priv->rps.link)) { |
| 5320 | spin_lock(&to_i915(dev)->rps.client_lock); |
| 5321 | list_del(&file_priv->rps.link); |
| 5322 | spin_unlock(&to_i915(dev)->rps.client_lock); |
| 5323 | } |
| 5324 | } |
| 5325 | |
| 5326 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5327 | { |
| 5328 | struct drm_i915_file_private *file_priv; |
| 5329 | int ret; |
| 5330 | |
| 5331 | DRM_DEBUG_DRIVER("\n"); |
| 5332 | |
| 5333 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5334 | if (!file_priv) |
| 5335 | return -ENOMEM; |
| 5336 | |
| 5337 | file->driver_priv = file_priv; |
| 5338 | file_priv->dev_priv = dev->dev_private; |
| 5339 | file_priv->file = file; |
| 5340 | INIT_LIST_HEAD(&file_priv->rps.link); |
| 5341 | |
| 5342 | spin_lock_init(&file_priv->mm.lock); |
| 5343 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
| 5344 | |
| 5345 | ret = i915_gem_context_open(dev, file); |
| 5346 | if (ret) |
| 5347 | kfree(file_priv); |
| 5348 | |
| 5349 | return ret; |
| 5350 | } |
| 5351 | |
| 5352 | /** |
| 5353 | * i915_gem_track_fb - update frontbuffer tracking |
| 5354 | * old: current GEM buffer for the frontbuffer slots |
| 5355 | * new: new GEM buffer for the frontbuffer slots |
| 5356 | * frontbuffer_bits: bitmask of frontbuffer slots |
| 5357 | * |
| 5358 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
| 5359 | * from @old and setting them in @new. Both @old and @new can be NULL. |
| 5360 | */ |
| 5361 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5362 | struct drm_i915_gem_object *new, |
| 5363 | unsigned frontbuffer_bits) |
| 5364 | { |
| 5365 | if (old) { |
| 5366 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5367 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5368 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5369 | } |
| 5370 | |
| 5371 | if (new) { |
| 5372 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5373 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5374 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5375 | } |
| 5376 | } |
| 5377 | |
| 5378 | /* All the new VM stuff */ |
| 5379 | unsigned long |
| 5380 | i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5381 | struct i915_address_space *vm) |
| 5382 | { |
| 5383 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5384 | struct i915_vma *vma; |
| 5385 | |
| 5386 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
| 5387 | |
| 5388 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5389 | if (i915_is_ggtt(vma->vm) && |
| 5390 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5391 | continue; |
| 5392 | if (vma->vm == vm) |
| 5393 | return vma->node.start; |
| 5394 | } |
| 5395 | |
| 5396 | WARN(1, "%s vma for this object not found.\n", |
| 5397 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
| 5398 | return -1; |
| 5399 | } |
| 5400 | |
| 5401 | unsigned long |
| 5402 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
| 5403 | const struct i915_ggtt_view *view) |
| 5404 | { |
| 5405 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
| 5406 | struct i915_vma *vma; |
| 5407 | |
| 5408 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5409 | if (vma->vm == ggtt && |
| 5410 | i915_ggtt_view_equal(&vma->ggtt_view, view)) |
| 5411 | return vma->node.start; |
| 5412 | |
| 5413 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
| 5414 | return -1; |
| 5415 | } |
| 5416 | |
| 5417 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5418 | struct i915_address_space *vm) |
| 5419 | { |
| 5420 | struct i915_vma *vma; |
| 5421 | |
| 5422 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5423 | if (i915_is_ggtt(vma->vm) && |
| 5424 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5425 | continue; |
| 5426 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
| 5427 | return true; |
| 5428 | } |
| 5429 | |
| 5430 | return false; |
| 5431 | } |
| 5432 | |
| 5433 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
| 5434 | const struct i915_ggtt_view *view) |
| 5435 | { |
| 5436 | struct i915_address_space *ggtt = i915_obj_to_ggtt(o); |
| 5437 | struct i915_vma *vma; |
| 5438 | |
| 5439 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5440 | if (vma->vm == ggtt && |
| 5441 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
| 5442 | drm_mm_node_allocated(&vma->node)) |
| 5443 | return true; |
| 5444 | |
| 5445 | return false; |
| 5446 | } |
| 5447 | |
| 5448 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5449 | { |
| 5450 | struct i915_vma *vma; |
| 5451 | |
| 5452 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5453 | if (drm_mm_node_allocated(&vma->node)) |
| 5454 | return true; |
| 5455 | |
| 5456 | return false; |
| 5457 | } |
| 5458 | |
| 5459 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 5460 | struct i915_address_space *vm) |
| 5461 | { |
| 5462 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5463 | struct i915_vma *vma; |
| 5464 | |
| 5465 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
| 5466 | |
| 5467 | BUG_ON(list_empty(&o->vma_list)); |
| 5468 | |
| 5469 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 5470 | if (i915_is_ggtt(vma->vm) && |
| 5471 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5472 | continue; |
| 5473 | if (vma->vm == vm) |
| 5474 | return vma->node.size; |
| 5475 | } |
| 5476 | return 0; |
| 5477 | } |
| 5478 | |
| 5479 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
| 5480 | { |
| 5481 | struct i915_vma *vma; |
| 5482 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 5483 | if (vma->pin_count > 0) |
| 5484 | return true; |
| 5485 | |
| 5486 | return false; |
| 5487 | } |
| 5488 | |