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agp/intel-gtt: remove dead code
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem.c
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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
35#include <linux/slab.h>
36#include <linux/swap.h>
37#include <linux/pci.h>
38#include <linux/dma-buf.h>
39
40static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 unsigned alignment,
45 bool map_and_fenceable);
46static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
50
51static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
55 bool enable);
56
57static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
60
61static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
62{
63 if (obj->tiling_mode)
64 i915_gem_release_mmap(obj);
65
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
68 */
69 obj->fence_dirty = false;
70 obj->fence_reg = I915_FENCE_REG_NONE;
71}
72
73/* some bookkeeping */
74static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
75 size_t size)
76{
77 dev_priv->mm.object_count++;
78 dev_priv->mm.object_memory += size;
79}
80
81static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
82 size_t size)
83{
84 dev_priv->mm.object_count--;
85 dev_priv->mm.object_memory -= size;
86}
87
88static int
89i915_gem_wait_for_error(struct drm_device *dev)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 struct completion *x = &dev_priv->error_completion;
93 unsigned long flags;
94 int ret;
95
96 if (!atomic_read(&dev_priv->mm.wedged))
97 return 0;
98
99 ret = wait_for_completion_interruptible(x);
100 if (ret)
101 return ret;
102
103 if (atomic_read(&dev_priv->mm.wedged)) {
104 /* GPU is hung, bump the completion count to account for
105 * the token we just consumed so that we never hit zero and
106 * end up waiting upon a subsequent completion event that
107 * will never happen.
108 */
109 spin_lock_irqsave(&x->wait.lock, flags);
110 x->done++;
111 spin_unlock_irqrestore(&x->wait.lock, flags);
112 }
113 return 0;
114}
115
116int i915_mutex_lock_interruptible(struct drm_device *dev)
117{
118 int ret;
119
120 ret = i915_gem_wait_for_error(dev);
121 if (ret)
122 return ret;
123
124 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 if (ret)
126 return ret;
127
128 WARN_ON(i915_verify_lists(dev));
129 return 0;
130}
131
132static inline bool
133i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
134{
135 return !obj->active;
136}
137
138int
139i915_gem_init_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
141{
142 struct drm_i915_gem_init *args = data;
143
144 if (drm_core_check_feature(dev, DRIVER_MODESET))
145 return -ENODEV;
146
147 if (args->gtt_start >= args->gtt_end ||
148 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
149 return -EINVAL;
150
151 /* GEM with user mode setting was never supported on ilk and later. */
152 if (INTEL_INFO(dev)->gen >= 5)
153 return -ENODEV;
154
155 mutex_lock(&dev->struct_mutex);
156 i915_gem_init_global_gtt(dev, args->gtt_start,
157 args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
159
160 return 0;
161}
162
163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
170 size_t pinned;
171
172 pinned = 0;
173 mutex_lock(&dev->struct_mutex);
174 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
175 if (obj->pin_count)
176 pinned += obj->gtt_space->size;
177 mutex_unlock(&dev->struct_mutex);
178
179 args->aper_size = dev_priv->mm.gtt_total;
180 args->aper_available_size = args->aper_size - pinned;
181
182 return 0;
183}
184
185static int
186i915_gem_create(struct drm_file *file,
187 struct drm_device *dev,
188 uint64_t size,
189 uint32_t *handle_p)
190{
191 struct drm_i915_gem_object *obj;
192 int ret;
193 u32 handle;
194
195 size = roundup(size, PAGE_SIZE);
196 if (size == 0)
197 return -EINVAL;
198
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
201 if (obj == NULL)
202 return -ENOMEM;
203
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
205 if (ret) {
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
208 kfree(obj);
209 return ret;
210 }
211
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
215
216 *handle_p = handle;
217 return 0;
218}
219
220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
247
248 return i915_gem_create(file, dev,
249 args->size, &args->handle);
250}
251
252static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
253{
254 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
255
256 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
257 obj->tiling_mode != I915_TILING_NONE;
258}
259
260static inline int
261__copy_to_user_swizzled(char __user *cpu_vaddr,
262 const char *gpu_vaddr, int gpu_offset,
263 int length)
264{
265 int ret, cpu_offset = 0;
266
267 while (length > 0) {
268 int cacheline_end = ALIGN(gpu_offset + 1, 64);
269 int this_length = min(cacheline_end - gpu_offset, length);
270 int swizzled_gpu_offset = gpu_offset ^ 64;
271
272 ret = __copy_to_user(cpu_vaddr + cpu_offset,
273 gpu_vaddr + swizzled_gpu_offset,
274 this_length);
275 if (ret)
276 return ret + length;
277
278 cpu_offset += this_length;
279 gpu_offset += this_length;
280 length -= this_length;
281 }
282
283 return 0;
284}
285
286static inline int
287__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
288 const char __user *cpu_vaddr,
289 int length)
290{
291 int ret, cpu_offset = 0;
292
293 while (length > 0) {
294 int cacheline_end = ALIGN(gpu_offset + 1, 64);
295 int this_length = min(cacheline_end - gpu_offset, length);
296 int swizzled_gpu_offset = gpu_offset ^ 64;
297
298 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
299 cpu_vaddr + cpu_offset,
300 this_length);
301 if (ret)
302 return ret + length;
303
304 cpu_offset += this_length;
305 gpu_offset += this_length;
306 length -= this_length;
307 }
308
309 return 0;
310}
311
312/* Per-page copy function for the shmem pread fastpath.
313 * Flushes invalid cachelines before reading the target if
314 * needs_clflush is set. */
315static int
316shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
317 char __user *user_data,
318 bool page_do_bit17_swizzling, bool needs_clflush)
319{
320 char *vaddr;
321 int ret;
322
323 if (unlikely(page_do_bit17_swizzling))
324 return -EINVAL;
325
326 vaddr = kmap_atomic(page);
327 if (needs_clflush)
328 drm_clflush_virt_range(vaddr + shmem_page_offset,
329 page_length);
330 ret = __copy_to_user_inatomic(user_data,
331 vaddr + shmem_page_offset,
332 page_length);
333 kunmap_atomic(vaddr);
334
335 return ret;
336}
337
338static void
339shmem_clflush_swizzled_range(char *addr, unsigned long length,
340 bool swizzled)
341{
342 if (unlikely(swizzled)) {
343 unsigned long start = (unsigned long) addr;
344 unsigned long end = (unsigned long) addr + length;
345
346 /* For swizzling simply ensure that we always flush both
347 * channels. Lame, but simple and it works. Swizzled
348 * pwrite/pread is far from a hotpath - current userspace
349 * doesn't use it at all. */
350 start = round_down(start, 128);
351 end = round_up(end, 128);
352
353 drm_clflush_virt_range((void *)start, end - start);
354 } else {
355 drm_clflush_virt_range(addr, length);
356 }
357
358}
359
360/* Only difference to the fast-path function is that this can handle bit17
361 * and uses non-atomic copy and kmap functions. */
362static int
363shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
364 char __user *user_data,
365 bool page_do_bit17_swizzling, bool needs_clflush)
366{
367 char *vaddr;
368 int ret;
369
370 vaddr = kmap(page);
371 if (needs_clflush)
372 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
373 page_length,
374 page_do_bit17_swizzling);
375
376 if (page_do_bit17_swizzling)
377 ret = __copy_to_user_swizzled(user_data,
378 vaddr, shmem_page_offset,
379 page_length);
380 else
381 ret = __copy_to_user(user_data,
382 vaddr + shmem_page_offset,
383 page_length);
384 kunmap(page);
385
386 return ret;
387}
388
389static int
390i915_gem_shmem_pread(struct drm_device *dev,
391 struct drm_i915_gem_object *obj,
392 struct drm_i915_gem_pread *args,
393 struct drm_file *file)
394{
395 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
396 char __user *user_data;
397 ssize_t remain;
398 loff_t offset;
399 int shmem_page_offset, page_length, ret = 0;
400 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
401 int hit_slowpath = 0;
402 int prefaulted = 0;
403 int needs_clflush = 0;
404 int release_page;
405
406 user_data = (char __user *) (uintptr_t) args->data_ptr;
407 remain = args->size;
408
409 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
410
411 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
412 /* If we're not in the cpu read domain, set ourself into the gtt
413 * read domain and manually flush cachelines (if required). This
414 * optimizes for the case when the gpu will dirty the data
415 * anyway again before the next pread happens. */
416 if (obj->cache_level == I915_CACHE_NONE)
417 needs_clflush = 1;
418 ret = i915_gem_object_set_to_gtt_domain(obj, false);
419 if (ret)
420 return ret;
421 }
422
423 offset = args->offset;
424
425 while (remain > 0) {
426 struct page *page;
427
428 /* Operation in this page
429 *
430 * shmem_page_offset = offset within page in shmem file
431 * page_length = bytes to copy for this page
432 */
433 shmem_page_offset = offset_in_page(offset);
434 page_length = remain;
435 if ((shmem_page_offset + page_length) > PAGE_SIZE)
436 page_length = PAGE_SIZE - shmem_page_offset;
437
438 if (obj->pages) {
439 page = obj->pages[offset >> PAGE_SHIFT];
440 release_page = 0;
441 } else {
442 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
443 if (IS_ERR(page)) {
444 ret = PTR_ERR(page);
445 goto out;
446 }
447 release_page = 1;
448 }
449
450 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
451 (page_to_phys(page) & (1 << 17)) != 0;
452
453 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
454 user_data, page_do_bit17_swizzling,
455 needs_clflush);
456 if (ret == 0)
457 goto next_page;
458
459 hit_slowpath = 1;
460 page_cache_get(page);
461 mutex_unlock(&dev->struct_mutex);
462
463 if (!prefaulted) {
464 ret = fault_in_multipages_writeable(user_data, remain);
465 /* Userspace is tricking us, but we've already clobbered
466 * its pages with the prefault and promised to write the
467 * data up to the first fault. Hence ignore any errors
468 * and just continue. */
469 (void)ret;
470 prefaulted = 1;
471 }
472
473 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
474 user_data, page_do_bit17_swizzling,
475 needs_clflush);
476
477 mutex_lock(&dev->struct_mutex);
478 page_cache_release(page);
479next_page:
480 mark_page_accessed(page);
481 if (release_page)
482 page_cache_release(page);
483
484 if (ret) {
485 ret = -EFAULT;
486 goto out;
487 }
488
489 remain -= page_length;
490 user_data += page_length;
491 offset += page_length;
492 }
493
494out:
495 if (hit_slowpath) {
496 /* Fixup: Kill any reinstated backing storage pages */
497 if (obj->madv == __I915_MADV_PURGED)
498 i915_gem_object_truncate(obj);
499 }
500
501 return ret;
502}
503
504/**
505 * Reads data from the object referenced by handle.
506 *
507 * On error, the contents of *data are undefined.
508 */
509int
510i915_gem_pread_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file)
512{
513 struct drm_i915_gem_pread *args = data;
514 struct drm_i915_gem_object *obj;
515 int ret = 0;
516
517 if (args->size == 0)
518 return 0;
519
520 if (!access_ok(VERIFY_WRITE,
521 (char __user *)(uintptr_t)args->data_ptr,
522 args->size))
523 return -EFAULT;
524
525 ret = i915_mutex_lock_interruptible(dev);
526 if (ret)
527 return ret;
528
529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
530 if (&obj->base == NULL) {
531 ret = -ENOENT;
532 goto unlock;
533 }
534
535 /* Bounds check source. */
536 if (args->offset > obj->base.size ||
537 args->size > obj->base.size - args->offset) {
538 ret = -EINVAL;
539 goto out;
540 }
541
542 /* prime objects have no backing filp to GEM pread/pwrite
543 * pages from.
544 */
545 if (!obj->base.filp) {
546 ret = -EINVAL;
547 goto out;
548 }
549
550 trace_i915_gem_object_pread(obj, args->offset, args->size);
551
552 ret = i915_gem_shmem_pread(dev, obj, args, file);
553
554out:
555 drm_gem_object_unreference(&obj->base);
556unlock:
557 mutex_unlock(&dev->struct_mutex);
558 return ret;
559}
560
561/* This is the fast write path which cannot handle
562 * page faults in the source data
563 */
564
565static inline int
566fast_user_write(struct io_mapping *mapping,
567 loff_t page_base, int page_offset,
568 char __user *user_data,
569 int length)
570{
571 void __iomem *vaddr_atomic;
572 void *vaddr;
573 unsigned long unwritten;
574
575 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr = (void __force*)vaddr_atomic + page_offset;
578 unwritten = __copy_from_user_inatomic_nocache(vaddr,
579 user_data, length);
580 io_mapping_unmap_atomic(vaddr_atomic);
581 return unwritten;
582}
583
584/**
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
587 */
588static int
589i915_gem_gtt_pwrite_fast(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pwrite *args,
592 struct drm_file *file)
593{
594 drm_i915_private_t *dev_priv = dev->dev_private;
595 ssize_t remain;
596 loff_t offset, page_base;
597 char __user *user_data;
598 int page_offset, page_length, ret;
599
600 ret = i915_gem_object_pin(obj, 0, true);
601 if (ret)
602 goto out;
603
604 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 if (ret)
606 goto out_unpin;
607
608 ret = i915_gem_object_put_fence(obj);
609 if (ret)
610 goto out_unpin;
611
612 user_data = (char __user *) (uintptr_t) args->data_ptr;
613 remain = args->size;
614
615 offset = obj->gtt_offset + args->offset;
616
617 while (remain > 0) {
618 /* Operation in this page
619 *
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
623 */
624 page_base = offset & PAGE_MASK;
625 page_offset = offset_in_page(offset);
626 page_length = remain;
627 if ((page_offset + remain) > PAGE_SIZE)
628 page_length = PAGE_SIZE - page_offset;
629
630 /* If we get a fault while copying data, then (presumably) our
631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
633 */
634 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
635 page_offset, user_data, page_length)) {
636 ret = -EFAULT;
637 goto out_unpin;
638 }
639
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
643 }
644
645out_unpin:
646 i915_gem_object_unpin(obj);
647out:
648 return ret;
649}
650
651/* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
655static int
656shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
657 char __user *user_data,
658 bool page_do_bit17_swizzling,
659 bool needs_clflush_before,
660 bool needs_clflush_after)
661{
662 char *vaddr;
663 int ret;
664
665 if (unlikely(page_do_bit17_swizzling))
666 return -EINVAL;
667
668 vaddr = kmap_atomic(page);
669 if (needs_clflush_before)
670 drm_clflush_virt_range(vaddr + shmem_page_offset,
671 page_length);
672 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
673 user_data,
674 page_length);
675 if (needs_clflush_after)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
677 page_length);
678 kunmap_atomic(vaddr);
679
680 return ret;
681}
682
683/* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
685static int
686shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
687 char __user *user_data,
688 bool page_do_bit17_swizzling,
689 bool needs_clflush_before,
690 bool needs_clflush_after)
691{
692 char *vaddr;
693 int ret;
694
695 vaddr = kmap(page);
696 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
697 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
698 page_length,
699 page_do_bit17_swizzling);
700 if (page_do_bit17_swizzling)
701 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 user_data,
703 page_length);
704 else
705 ret = __copy_from_user(vaddr + shmem_page_offset,
706 user_data,
707 page_length);
708 if (needs_clflush_after)
709 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
710 page_length,
711 page_do_bit17_swizzling);
712 kunmap(page);
713
714 return ret;
715}
716
717static int
718i915_gem_shmem_pwrite(struct drm_device *dev,
719 struct drm_i915_gem_object *obj,
720 struct drm_i915_gem_pwrite *args,
721 struct drm_file *file)
722{
723 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
724 ssize_t remain;
725 loff_t offset;
726 char __user *user_data;
727 int shmem_page_offset, page_length, ret = 0;
728 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
729 int hit_slowpath = 0;
730 int needs_clflush_after = 0;
731 int needs_clflush_before = 0;
732 int release_page;
733
734 user_data = (char __user *) (uintptr_t) args->data_ptr;
735 remain = args->size;
736
737 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
738
739 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
740 /* If we're not in the cpu write domain, set ourself into the gtt
741 * write domain and manually flush cachelines (if required). This
742 * optimizes for the case when the gpu will use the data
743 * right away and we therefore have to clflush anyway. */
744 if (obj->cache_level == I915_CACHE_NONE)
745 needs_clflush_after = 1;
746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
747 if (ret)
748 return ret;
749 }
750 /* Same trick applies for invalidate partially written cachelines before
751 * writing. */
752 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
753 && obj->cache_level == I915_CACHE_NONE)
754 needs_clflush_before = 1;
755
756 offset = args->offset;
757 obj->dirty = 1;
758
759 while (remain > 0) {
760 struct page *page;
761 int partial_cacheline_write;
762
763 /* Operation in this page
764 *
765 * shmem_page_offset = offset within page in shmem file
766 * page_length = bytes to copy for this page
767 */
768 shmem_page_offset = offset_in_page(offset);
769
770 page_length = remain;
771 if ((shmem_page_offset + page_length) > PAGE_SIZE)
772 page_length = PAGE_SIZE - shmem_page_offset;
773
774 /* If we don't overwrite a cacheline completely we need to be
775 * careful to have up-to-date data by first clflushing. Don't
776 * overcomplicate things and flush the entire patch. */
777 partial_cacheline_write = needs_clflush_before &&
778 ((shmem_page_offset | page_length)
779 & (boot_cpu_data.x86_clflush_size - 1));
780
781 if (obj->pages) {
782 page = obj->pages[offset >> PAGE_SHIFT];
783 release_page = 0;
784 } else {
785 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
786 if (IS_ERR(page)) {
787 ret = PTR_ERR(page);
788 goto out;
789 }
790 release_page = 1;
791 }
792
793 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
794 (page_to_phys(page) & (1 << 17)) != 0;
795
796 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
797 user_data, page_do_bit17_swizzling,
798 partial_cacheline_write,
799 needs_clflush_after);
800 if (ret == 0)
801 goto next_page;
802
803 hit_slowpath = 1;
804 page_cache_get(page);
805 mutex_unlock(&dev->struct_mutex);
806
807 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
808 user_data, page_do_bit17_swizzling,
809 partial_cacheline_write,
810 needs_clflush_after);
811
812 mutex_lock(&dev->struct_mutex);
813 page_cache_release(page);
814next_page:
815 set_page_dirty(page);
816 mark_page_accessed(page);
817 if (release_page)
818 page_cache_release(page);
819
820 if (ret) {
821 ret = -EFAULT;
822 goto out;
823 }
824
825 remain -= page_length;
826 user_data += page_length;
827 offset += page_length;
828 }
829
830out:
831 if (hit_slowpath) {
832 /* Fixup: Kill any reinstated backing storage pages */
833 if (obj->madv == __I915_MADV_PURGED)
834 i915_gem_object_truncate(obj);
835 /* and flush dirty cachelines in case the object isn't in the cpu write
836 * domain anymore. */
837 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 i915_gem_clflush_object(obj);
839 intel_gtt_chipset_flush();
840 }
841 }
842
843 if (needs_clflush_after)
844 intel_gtt_chipset_flush();
845
846 return ret;
847}
848
849/**
850 * Writes data to the object referenced by handle.
851 *
852 * On error, the contents of the buffer that were to be modified are undefined.
853 */
854int
855i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
857{
858 struct drm_i915_gem_pwrite *args = data;
859 struct drm_i915_gem_object *obj;
860 int ret;
861
862 if (args->size == 0)
863 return 0;
864
865 if (!access_ok(VERIFY_READ,
866 (char __user *)(uintptr_t)args->data_ptr,
867 args->size))
868 return -EFAULT;
869
870 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
871 args->size);
872 if (ret)
873 return -EFAULT;
874
875 ret = i915_mutex_lock_interruptible(dev);
876 if (ret)
877 return ret;
878
879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
880 if (&obj->base == NULL) {
881 ret = -ENOENT;
882 goto unlock;
883 }
884
885 /* Bounds check destination. */
886 if (args->offset > obj->base.size ||
887 args->size > obj->base.size - args->offset) {
888 ret = -EINVAL;
889 goto out;
890 }
891
892 /* prime objects have no backing filp to GEM pread/pwrite
893 * pages from.
894 */
895 if (!obj->base.filp) {
896 ret = -EINVAL;
897 goto out;
898 }
899
900 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
901
902 ret = -EFAULT;
903 /* We can only do the GTT pwrite on untiled buffers, as otherwise
904 * it would end up going through the fenced access, and we'll get
905 * different detiling behavior between reading and writing.
906 * pread/pwrite currently are reading and writing from the CPU
907 * perspective, requiring manual detiling by the client.
908 */
909 if (obj->phys_obj) {
910 ret = i915_gem_phys_pwrite(dev, obj, args, file);
911 goto out;
912 }
913
914 if (obj->gtt_space &&
915 obj->cache_level == I915_CACHE_NONE &&
916 obj->tiling_mode == I915_TILING_NONE &&
917 obj->map_and_fenceable &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
923 }
924
925 if (ret == -EFAULT)
926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
927
928out:
929 drm_gem_object_unreference(&obj->base);
930unlock:
931 mutex_unlock(&dev->struct_mutex);
932 return ret;
933}
934
935/**
936 * Called when user space prepares to use an object with the CPU, either
937 * through the mmap ioctl's mapping or a GTT mapping.
938 */
939int
940i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
941 struct drm_file *file)
942{
943 struct drm_i915_gem_set_domain *args = data;
944 struct drm_i915_gem_object *obj;
945 uint32_t read_domains = args->read_domains;
946 uint32_t write_domain = args->write_domain;
947 int ret;
948
949 /* Only handle setting domains to types used by the CPU. */
950 if (write_domain & I915_GEM_GPU_DOMAINS)
951 return -EINVAL;
952
953 if (read_domains & I915_GEM_GPU_DOMAINS)
954 return -EINVAL;
955
956 /* Having something in the write domain implies it's in the read
957 * domain, and only that read domain. Enforce that in the request.
958 */
959 if (write_domain != 0 && read_domains != write_domain)
960 return -EINVAL;
961
962 ret = i915_mutex_lock_interruptible(dev);
963 if (ret)
964 return ret;
965
966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
967 if (&obj->base == NULL) {
968 ret = -ENOENT;
969 goto unlock;
970 }
971
972 if (read_domains & I915_GEM_DOMAIN_GTT) {
973 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
974
975 /* Silently promote "you're not bound, there was nothing to do"
976 * to success, since the client was just asking us to
977 * make sure everything was done.
978 */
979 if (ret == -EINVAL)
980 ret = 0;
981 } else {
982 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
983 }
984
985 drm_gem_object_unreference(&obj->base);
986unlock:
987 mutex_unlock(&dev->struct_mutex);
988 return ret;
989}
990
991/**
992 * Called when user space has done writes to this buffer
993 */
994int
995i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file)
997{
998 struct drm_i915_gem_sw_finish *args = data;
999 struct drm_i915_gem_object *obj;
1000 int ret = 0;
1001
1002 ret = i915_mutex_lock_interruptible(dev);
1003 if (ret)
1004 return ret;
1005
1006 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1007 if (&obj->base == NULL) {
1008 ret = -ENOENT;
1009 goto unlock;
1010 }
1011
1012 /* Pinned buffers may be scanout, so flush the cache */
1013 if (obj->pin_count)
1014 i915_gem_object_flush_cpu_write_domain(obj);
1015
1016 drm_gem_object_unreference(&obj->base);
1017unlock:
1018 mutex_unlock(&dev->struct_mutex);
1019 return ret;
1020}
1021
1022/**
1023 * Maps the contents of an object, returning the address it is mapped
1024 * into.
1025 *
1026 * While the mapping holds a reference on the contents of the object, it doesn't
1027 * imply a ref on the object itself.
1028 */
1029int
1030i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1031 struct drm_file *file)
1032{
1033 struct drm_i915_gem_mmap *args = data;
1034 struct drm_gem_object *obj;
1035 unsigned long addr;
1036
1037 obj = drm_gem_object_lookup(dev, file, args->handle);
1038 if (obj == NULL)
1039 return -ENOENT;
1040
1041 /* prime objects have no backing filp to GEM mmap
1042 * pages from.
1043 */
1044 if (!obj->filp) {
1045 drm_gem_object_unreference_unlocked(obj);
1046 return -EINVAL;
1047 }
1048
1049 addr = vm_mmap(obj->filp, 0, args->size,
1050 PROT_READ | PROT_WRITE, MAP_SHARED,
1051 args->offset);
1052 drm_gem_object_unreference_unlocked(obj);
1053 if (IS_ERR((void *)addr))
1054 return addr;
1055
1056 args->addr_ptr = (uint64_t) addr;
1057
1058 return 0;
1059}
1060
1061/**
1062 * i915_gem_fault - fault a page into the GTT
1063 * vma: VMA in question
1064 * vmf: fault info
1065 *
1066 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1067 * from userspace. The fault handler takes care of binding the object to
1068 * the GTT (if needed), allocating and programming a fence register (again,
1069 * only if needed based on whether the old reg is still valid or the object
1070 * is tiled) and inserting a new PTE into the faulting process.
1071 *
1072 * Note that the faulting process may involve evicting existing objects
1073 * from the GTT and/or fence registers to make room. So performance may
1074 * suffer if the GTT working set is large or there are few fence registers
1075 * left.
1076 */
1077int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1078{
1079 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1080 struct drm_device *dev = obj->base.dev;
1081 drm_i915_private_t *dev_priv = dev->dev_private;
1082 pgoff_t page_offset;
1083 unsigned long pfn;
1084 int ret = 0;
1085 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1086
1087 /* We don't use vmf->pgoff since that has the fake offset */
1088 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1089 PAGE_SHIFT;
1090
1091 ret = i915_mutex_lock_interruptible(dev);
1092 if (ret)
1093 goto out;
1094
1095 trace_i915_gem_object_fault(obj, page_offset, true, write);
1096
1097 /* Now bind it into the GTT if needed */
1098 if (!obj->map_and_fenceable) {
1099 ret = i915_gem_object_unbind(obj);
1100 if (ret)
1101 goto unlock;
1102 }
1103 if (!obj->gtt_space) {
1104 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1105 if (ret)
1106 goto unlock;
1107
1108 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1109 if (ret)
1110 goto unlock;
1111 }
1112
1113 if (!obj->has_global_gtt_mapping)
1114 i915_gem_gtt_bind_object(obj, obj->cache_level);
1115
1116 ret = i915_gem_object_get_fence(obj);
1117 if (ret)
1118 goto unlock;
1119
1120 if (i915_gem_object_is_inactive(obj))
1121 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1122
1123 obj->fault_mappable = true;
1124
1125 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1126 page_offset;
1127
1128 /* Finally, remap it using the new GTT offset */
1129 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1130unlock:
1131 mutex_unlock(&dev->struct_mutex);
1132out:
1133 switch (ret) {
1134 case -EIO:
1135 case -EAGAIN:
1136 /* Give the error handler a chance to run and move the
1137 * objects off the GPU active list. Next time we service the
1138 * fault, we should be able to transition the page into the
1139 * GTT without touching the GPU (and so avoid further
1140 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1141 * with coherency, just lost writes.
1142 */
1143 set_need_resched();
1144 case 0:
1145 case -ERESTARTSYS:
1146 case -EINTR:
1147 return VM_FAULT_NOPAGE;
1148 case -ENOMEM:
1149 return VM_FAULT_OOM;
1150 default:
1151 return VM_FAULT_SIGBUS;
1152 }
1153}
1154
1155/**
1156 * i915_gem_release_mmap - remove physical page mappings
1157 * @obj: obj in question
1158 *
1159 * Preserve the reservation of the mmapping with the DRM core code, but
1160 * relinquish ownership of the pages back to the system.
1161 *
1162 * It is vital that we remove the page mapping if we have mapped a tiled
1163 * object through the GTT and then lose the fence register due to
1164 * resource pressure. Similarly if the object has been moved out of the
1165 * aperture, than pages mapped into userspace must be revoked. Removing the
1166 * mapping will then trigger a page fault on the next user access, allowing
1167 * fixup by i915_gem_fault().
1168 */
1169void
1170i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1171{
1172 if (!obj->fault_mappable)
1173 return;
1174
1175 if (obj->base.dev->dev_mapping)
1176 unmap_mapping_range(obj->base.dev->dev_mapping,
1177 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1178 obj->base.size, 1);
1179
1180 obj->fault_mappable = false;
1181}
1182
1183static uint32_t
1184i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1185{
1186 uint32_t gtt_size;
1187
1188 if (INTEL_INFO(dev)->gen >= 4 ||
1189 tiling_mode == I915_TILING_NONE)
1190 return size;
1191
1192 /* Previous chips need a power-of-two fence region when tiling */
1193 if (INTEL_INFO(dev)->gen == 3)
1194 gtt_size = 1024*1024;
1195 else
1196 gtt_size = 512*1024;
1197
1198 while (gtt_size < size)
1199 gtt_size <<= 1;
1200
1201 return gtt_size;
1202}
1203
1204/**
1205 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1206 * @obj: object to check
1207 *
1208 * Return the required GTT alignment for an object, taking into account
1209 * potential fence register mapping.
1210 */
1211static uint32_t
1212i915_gem_get_gtt_alignment(struct drm_device *dev,
1213 uint32_t size,
1214 int tiling_mode)
1215{
1216 /*
1217 * Minimum alignment is 4k (GTT page size), but might be greater
1218 * if a fence register is needed for the object.
1219 */
1220 if (INTEL_INFO(dev)->gen >= 4 ||
1221 tiling_mode == I915_TILING_NONE)
1222 return 4096;
1223
1224 /*
1225 * Previous chips need to be aligned to the size of the smallest
1226 * fence register that can contain the object.
1227 */
1228 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1229}
1230
1231/**
1232 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1233 * unfenced object
1234 * @dev: the device
1235 * @size: size of the object
1236 * @tiling_mode: tiling mode of the object
1237 *
1238 * Return the required GTT alignment for an object, only taking into account
1239 * unfenced tiled surface requirements.
1240 */
1241uint32_t
1242i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1243 uint32_t size,
1244 int tiling_mode)
1245{
1246 /*
1247 * Minimum alignment is 4k (GTT page size) for sane hw.
1248 */
1249 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1250 tiling_mode == I915_TILING_NONE)
1251 return 4096;
1252
1253 /* Previous hardware however needs to be aligned to a power-of-two
1254 * tile height. The simplest method for determining this is to reuse
1255 * the power-of-tile object size.
1256 */
1257 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1258}
1259
1260int
1261i915_gem_mmap_gtt(struct drm_file *file,
1262 struct drm_device *dev,
1263 uint32_t handle,
1264 uint64_t *offset)
1265{
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 struct drm_i915_gem_object *obj;
1268 int ret;
1269
1270 ret = i915_mutex_lock_interruptible(dev);
1271 if (ret)
1272 return ret;
1273
1274 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1275 if (&obj->base == NULL) {
1276 ret = -ENOENT;
1277 goto unlock;
1278 }
1279
1280 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1281 ret = -E2BIG;
1282 goto out;
1283 }
1284
1285 if (obj->madv != I915_MADV_WILLNEED) {
1286 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1287 ret = -EINVAL;
1288 goto out;
1289 }
1290
1291 if (!obj->base.map_list.map) {
1292 ret = drm_gem_create_mmap_offset(&obj->base);
1293 if (ret)
1294 goto out;
1295 }
1296
1297 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1298
1299out:
1300 drm_gem_object_unreference(&obj->base);
1301unlock:
1302 mutex_unlock(&dev->struct_mutex);
1303 return ret;
1304}
1305
1306/**
1307 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1308 * @dev: DRM device
1309 * @data: GTT mapping ioctl data
1310 * @file: GEM object info
1311 *
1312 * Simply returns the fake offset to userspace so it can mmap it.
1313 * The mmap call will end up in drm_gem_mmap(), which will set things
1314 * up so we can get faults in the handler above.
1315 *
1316 * The fault handler will take care of binding the object into the GTT
1317 * (since it may have been evicted to make room for something), allocating
1318 * a fence register, and mapping the appropriate aperture address into
1319 * userspace.
1320 */
1321int
1322i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1323 struct drm_file *file)
1324{
1325 struct drm_i915_gem_mmap_gtt *args = data;
1326
1327 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1328}
1329
1330int
1331i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1332 gfp_t gfpmask)
1333{
1334 int page_count, i;
1335 struct address_space *mapping;
1336 struct inode *inode;
1337 struct page *page;
1338
1339 if (obj->pages || obj->sg_table)
1340 return 0;
1341
1342 /* Get the list of pages out of our struct file. They'll be pinned
1343 * at this point until we release them.
1344 */
1345 page_count = obj->base.size / PAGE_SIZE;
1346 BUG_ON(obj->pages != NULL);
1347 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1348 if (obj->pages == NULL)
1349 return -ENOMEM;
1350
1351 inode = obj->base.filp->f_path.dentry->d_inode;
1352 mapping = inode->i_mapping;
1353 gfpmask |= mapping_gfp_mask(mapping);
1354
1355 for (i = 0; i < page_count; i++) {
1356 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1357 if (IS_ERR(page))
1358 goto err_pages;
1359
1360 obj->pages[i] = page;
1361 }
1362
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 i915_gem_object_do_bit_17_swizzle(obj);
1365
1366 return 0;
1367
1368err_pages:
1369 while (i--)
1370 page_cache_release(obj->pages[i]);
1371
1372 drm_free_large(obj->pages);
1373 obj->pages = NULL;
1374 return PTR_ERR(page);
1375}
1376
1377static void
1378i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1379{
1380 int page_count = obj->base.size / PAGE_SIZE;
1381 int i;
1382
1383 if (!obj->pages)
1384 return;
1385
1386 BUG_ON(obj->madv == __I915_MADV_PURGED);
1387
1388 if (i915_gem_object_needs_bit17_swizzle(obj))
1389 i915_gem_object_save_bit_17_swizzle(obj);
1390
1391 if (obj->madv == I915_MADV_DONTNEED)
1392 obj->dirty = 0;
1393
1394 for (i = 0; i < page_count; i++) {
1395 if (obj->dirty)
1396 set_page_dirty(obj->pages[i]);
1397
1398 if (obj->madv == I915_MADV_WILLNEED)
1399 mark_page_accessed(obj->pages[i]);
1400
1401 page_cache_release(obj->pages[i]);
1402 }
1403 obj->dirty = 0;
1404
1405 drm_free_large(obj->pages);
1406 obj->pages = NULL;
1407}
1408
1409void
1410i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1411 struct intel_ring_buffer *ring,
1412 u32 seqno)
1413{
1414 struct drm_device *dev = obj->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416
1417 BUG_ON(ring == NULL);
1418 obj->ring = ring;
1419
1420 /* Add a reference if we're newly entering the active list. */
1421 if (!obj->active) {
1422 drm_gem_object_reference(&obj->base);
1423 obj->active = 1;
1424 }
1425
1426 /* Move from whatever list we were on to the tail of execution. */
1427 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1428 list_move_tail(&obj->ring_list, &ring->active_list);
1429
1430 obj->last_rendering_seqno = seqno;
1431
1432 if (obj->fenced_gpu_access) {
1433 obj->last_fenced_seqno = seqno;
1434
1435 /* Bump MRU to take account of the delayed flush */
1436 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1437 struct drm_i915_fence_reg *reg;
1438
1439 reg = &dev_priv->fence_regs[obj->fence_reg];
1440 list_move_tail(&reg->lru_list,
1441 &dev_priv->mm.fence_list);
1442 }
1443 }
1444}
1445
1446static void
1447i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1448{
1449 list_del_init(&obj->ring_list);
1450 obj->last_rendering_seqno = 0;
1451 obj->last_fenced_seqno = 0;
1452}
1453
1454static void
1455i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1456{
1457 struct drm_device *dev = obj->base.dev;
1458 drm_i915_private_t *dev_priv = dev->dev_private;
1459
1460 BUG_ON(!obj->active);
1461 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1462
1463 i915_gem_object_move_off_active(obj);
1464}
1465
1466static void
1467i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1468{
1469 struct drm_device *dev = obj->base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471
1472 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1473
1474 BUG_ON(!list_empty(&obj->gpu_write_list));
1475 BUG_ON(!obj->active);
1476 obj->ring = NULL;
1477
1478 i915_gem_object_move_off_active(obj);
1479 obj->fenced_gpu_access = false;
1480
1481 obj->active = 0;
1482 obj->pending_gpu_write = false;
1483 drm_gem_object_unreference(&obj->base);
1484
1485 WARN_ON(i915_verify_lists(dev));
1486}
1487
1488/* Immediately discard the backing storage */
1489static void
1490i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1491{
1492 struct inode *inode;
1493
1494 /* Our goal here is to return as much of the memory as
1495 * is possible back to the system as we are called from OOM.
1496 * To do this we must instruct the shmfs to drop all of its
1497 * backing pages, *now*.
1498 */
1499 inode = obj->base.filp->f_path.dentry->d_inode;
1500 shmem_truncate_range(inode, 0, (loff_t)-1);
1501
1502 if (obj->base.map_list.map)
1503 drm_gem_free_mmap_offset(&obj->base);
1504
1505 obj->madv = __I915_MADV_PURGED;
1506}
1507
1508static inline int
1509i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1510{
1511 return obj->madv == I915_MADV_DONTNEED;
1512}
1513
1514static void
1515i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1516 uint32_t flush_domains)
1517{
1518 struct drm_i915_gem_object *obj, *next;
1519
1520 list_for_each_entry_safe(obj, next,
1521 &ring->gpu_write_list,
1522 gpu_write_list) {
1523 if (obj->base.write_domain & flush_domains) {
1524 uint32_t old_write_domain = obj->base.write_domain;
1525
1526 obj->base.write_domain = 0;
1527 list_del_init(&obj->gpu_write_list);
1528 i915_gem_object_move_to_active(obj, ring,
1529 i915_gem_next_request_seqno(ring));
1530
1531 trace_i915_gem_object_change_domain(obj,
1532 obj->base.read_domains,
1533 old_write_domain);
1534 }
1535 }
1536}
1537
1538static u32
1539i915_gem_get_seqno(struct drm_device *dev)
1540{
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1542 u32 seqno = dev_priv->next_seqno;
1543
1544 /* reserve 0 for non-seqno */
1545 if (++dev_priv->next_seqno == 0)
1546 dev_priv->next_seqno = 1;
1547
1548 return seqno;
1549}
1550
1551u32
1552i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1553{
1554 if (ring->outstanding_lazy_request == 0)
1555 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1556
1557 return ring->outstanding_lazy_request;
1558}
1559
1560int
1561i915_add_request(struct intel_ring_buffer *ring,
1562 struct drm_file *file,
1563 struct drm_i915_gem_request *request)
1564{
1565 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1566 uint32_t seqno;
1567 u32 request_ring_position;
1568 int was_empty;
1569 int ret;
1570
1571 BUG_ON(request == NULL);
1572 seqno = i915_gem_next_request_seqno(ring);
1573
1574 /* Record the position of the start of the request so that
1575 * should we detect the updated seqno part-way through the
1576 * GPU processing the request, we never over-estimate the
1577 * position of the head.
1578 */
1579 request_ring_position = intel_ring_get_tail(ring);
1580
1581 ret = ring->add_request(ring, &seqno);
1582 if (ret)
1583 return ret;
1584
1585 trace_i915_gem_request_add(ring, seqno);
1586
1587 request->seqno = seqno;
1588 request->ring = ring;
1589 request->tail = request_ring_position;
1590 request->emitted_jiffies = jiffies;
1591 was_empty = list_empty(&ring->request_list);
1592 list_add_tail(&request->list, &ring->request_list);
1593
1594 if (file) {
1595 struct drm_i915_file_private *file_priv = file->driver_priv;
1596
1597 spin_lock(&file_priv->mm.lock);
1598 request->file_priv = file_priv;
1599 list_add_tail(&request->client_list,
1600 &file_priv->mm.request_list);
1601 spin_unlock(&file_priv->mm.lock);
1602 }
1603
1604 ring->outstanding_lazy_request = 0;
1605
1606 if (!dev_priv->mm.suspended) {
1607 if (i915_enable_hangcheck) {
1608 mod_timer(&dev_priv->hangcheck_timer,
1609 jiffies +
1610 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1611 }
1612 if (was_empty)
1613 queue_delayed_work(dev_priv->wq,
1614 &dev_priv->mm.retire_work, HZ);
1615 }
1616 return 0;
1617}
1618
1619static inline void
1620i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1621{
1622 struct drm_i915_file_private *file_priv = request->file_priv;
1623
1624 if (!file_priv)
1625 return;
1626
1627 spin_lock(&file_priv->mm.lock);
1628 if (request->file_priv) {
1629 list_del(&request->client_list);
1630 request->file_priv = NULL;
1631 }
1632 spin_unlock(&file_priv->mm.lock);
1633}
1634
1635static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1636 struct intel_ring_buffer *ring)
1637{
1638 while (!list_empty(&ring->request_list)) {
1639 struct drm_i915_gem_request *request;
1640
1641 request = list_first_entry(&ring->request_list,
1642 struct drm_i915_gem_request,
1643 list);
1644
1645 list_del(&request->list);
1646 i915_gem_request_remove_from_client(request);
1647 kfree(request);
1648 }
1649
1650 while (!list_empty(&ring->active_list)) {
1651 struct drm_i915_gem_object *obj;
1652
1653 obj = list_first_entry(&ring->active_list,
1654 struct drm_i915_gem_object,
1655 ring_list);
1656
1657 obj->base.write_domain = 0;
1658 list_del_init(&obj->gpu_write_list);
1659 i915_gem_object_move_to_inactive(obj);
1660 }
1661}
1662
1663static void i915_gem_reset_fences(struct drm_device *dev)
1664{
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 int i;
1667
1668 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1669 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1670
1671 i915_gem_write_fence(dev, i, NULL);
1672
1673 if (reg->obj)
1674 i915_gem_object_fence_lost(reg->obj);
1675
1676 reg->pin_count = 0;
1677 reg->obj = NULL;
1678 INIT_LIST_HEAD(&reg->lru_list);
1679 }
1680
1681 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1682}
1683
1684void i915_gem_reset(struct drm_device *dev)
1685{
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct drm_i915_gem_object *obj;
1688 struct intel_ring_buffer *ring;
1689 int i;
1690
1691 for_each_ring(ring, dev_priv, i)
1692 i915_gem_reset_ring_lists(dev_priv, ring);
1693
1694 /* Remove anything from the flushing lists. The GPU cache is likely
1695 * to be lost on reset along with the data, so simply move the
1696 * lost bo to the inactive list.
1697 */
1698 while (!list_empty(&dev_priv->mm.flushing_list)) {
1699 obj = list_first_entry(&dev_priv->mm.flushing_list,
1700 struct drm_i915_gem_object,
1701 mm_list);
1702
1703 obj->base.write_domain = 0;
1704 list_del_init(&obj->gpu_write_list);
1705 i915_gem_object_move_to_inactive(obj);
1706 }
1707
1708 /* Move everything out of the GPU domains to ensure we do any
1709 * necessary invalidation upon reuse.
1710 */
1711 list_for_each_entry(obj,
1712 &dev_priv->mm.inactive_list,
1713 mm_list)
1714 {
1715 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1716 }
1717
1718 /* The fence registers are invalidated so clear them out */
1719 i915_gem_reset_fences(dev);
1720}
1721
1722/**
1723 * This function clears the request list as sequence numbers are passed.
1724 */
1725void
1726i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1727{
1728 uint32_t seqno;
1729 int i;
1730
1731 if (list_empty(&ring->request_list))
1732 return;
1733
1734 WARN_ON(i915_verify_lists(ring->dev));
1735
1736 seqno = ring->get_seqno(ring);
1737
1738 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1739 if (seqno >= ring->sync_seqno[i])
1740 ring->sync_seqno[i] = 0;
1741
1742 while (!list_empty(&ring->request_list)) {
1743 struct drm_i915_gem_request *request;
1744
1745 request = list_first_entry(&ring->request_list,
1746 struct drm_i915_gem_request,
1747 list);
1748
1749 if (!i915_seqno_passed(seqno, request->seqno))
1750 break;
1751
1752 trace_i915_gem_request_retire(ring, request->seqno);
1753 /* We know the GPU must have read the request to have
1754 * sent us the seqno + interrupt, so use the position
1755 * of tail of the request to update the last known position
1756 * of the GPU head.
1757 */
1758 ring->last_retired_head = request->tail;
1759
1760 list_del(&request->list);
1761 i915_gem_request_remove_from_client(request);
1762 kfree(request);
1763 }
1764
1765 /* Move any buffers on the active list that are no longer referenced
1766 * by the ringbuffer to the flushing/inactive lists as appropriate.
1767 */
1768 while (!list_empty(&ring->active_list)) {
1769 struct drm_i915_gem_object *obj;
1770
1771 obj = list_first_entry(&ring->active_list,
1772 struct drm_i915_gem_object,
1773 ring_list);
1774
1775 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1776 break;
1777
1778 if (obj->base.write_domain != 0)
1779 i915_gem_object_move_to_flushing(obj);
1780 else
1781 i915_gem_object_move_to_inactive(obj);
1782 }
1783
1784 if (unlikely(ring->trace_irq_seqno &&
1785 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1786 ring->irq_put(ring);
1787 ring->trace_irq_seqno = 0;
1788 }
1789
1790 WARN_ON(i915_verify_lists(ring->dev));
1791}
1792
1793void
1794i915_gem_retire_requests(struct drm_device *dev)
1795{
1796 drm_i915_private_t *dev_priv = dev->dev_private;
1797 struct intel_ring_buffer *ring;
1798 int i;
1799
1800 for_each_ring(ring, dev_priv, i)
1801 i915_gem_retire_requests_ring(ring);
1802}
1803
1804static void
1805i915_gem_retire_work_handler(struct work_struct *work)
1806{
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
1809 struct intel_ring_buffer *ring;
1810 bool idle;
1811 int i;
1812
1813 dev_priv = container_of(work, drm_i915_private_t,
1814 mm.retire_work.work);
1815 dev = dev_priv->dev;
1816
1817 /* Come back later if the device is busy... */
1818 if (!mutex_trylock(&dev->struct_mutex)) {
1819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1820 return;
1821 }
1822
1823 i915_gem_retire_requests(dev);
1824
1825 /* Send a periodic flush down the ring so we don't hold onto GEM
1826 * objects indefinitely.
1827 */
1828 idle = true;
1829 for_each_ring(ring, dev_priv, i) {
1830 if (!list_empty(&ring->gpu_write_list)) {
1831 struct drm_i915_gem_request *request;
1832 int ret;
1833
1834 ret = i915_gem_flush_ring(ring,
1835 0, I915_GEM_GPU_DOMAINS);
1836 request = kzalloc(sizeof(*request), GFP_KERNEL);
1837 if (ret || request == NULL ||
1838 i915_add_request(ring, NULL, request))
1839 kfree(request);
1840 }
1841
1842 idle &= list_empty(&ring->request_list);
1843 }
1844
1845 if (!dev_priv->mm.suspended && !idle)
1846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1847
1848 mutex_unlock(&dev->struct_mutex);
1849}
1850
1851static int
1852i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1853{
1854 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1855
1856 if (atomic_read(&dev_priv->mm.wedged)) {
1857 struct completion *x = &dev_priv->error_completion;
1858 bool recovery_complete;
1859 unsigned long flags;
1860
1861 /* Give the error handler a chance to run. */
1862 spin_lock_irqsave(&x->wait.lock, flags);
1863 recovery_complete = x->done > 0;
1864 spin_unlock_irqrestore(&x->wait.lock, flags);
1865
1866 return recovery_complete ? -EIO : -EAGAIN;
1867 }
1868
1869 return 0;
1870}
1871
1872/*
1873 * Compare seqno against outstanding lazy request. Emit a request if they are
1874 * equal.
1875 */
1876static int
1877i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1878{
1879 int ret = 0;
1880
1881 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1882
1883 if (seqno == ring->outstanding_lazy_request) {
1884 struct drm_i915_gem_request *request;
1885
1886 request = kzalloc(sizeof(*request), GFP_KERNEL);
1887 if (request == NULL)
1888 return -ENOMEM;
1889
1890 ret = i915_add_request(ring, NULL, request);
1891 if (ret) {
1892 kfree(request);
1893 return ret;
1894 }
1895
1896 BUG_ON(seqno != request->seqno);
1897 }
1898
1899 return ret;
1900}
1901
1902/**
1903 * __wait_seqno - wait until execution of seqno has finished
1904 * @ring: the ring expected to report seqno
1905 * @seqno: duh!
1906 * @interruptible: do an interruptible wait (normally yes)
1907 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1908 *
1909 * Returns 0 if the seqno was found within the alloted time. Else returns the
1910 * errno with remaining time filled in timeout argument.
1911 */
1912static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1913 bool interruptible, struct timespec *timeout)
1914{
1915 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1916 struct timespec before, now, wait_time={1,0};
1917 unsigned long timeout_jiffies;
1918 long end;
1919 bool wait_forever = true;
1920
1921 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1922 return 0;
1923
1924 trace_i915_gem_request_wait_begin(ring, seqno);
1925
1926 if (timeout != NULL) {
1927 wait_time = *timeout;
1928 wait_forever = false;
1929 }
1930
1931 timeout_jiffies = timespec_to_jiffies(&wait_time);
1932
1933 if (WARN_ON(!ring->irq_get(ring)))
1934 return -ENODEV;
1935
1936 /* Record current time in case interrupted by signal, or wedged * */
1937 getrawmonotonic(&before);
1938
1939#define EXIT_COND \
1940 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1941 atomic_read(&dev_priv->mm.wedged))
1942 do {
1943 if (interruptible)
1944 end = wait_event_interruptible_timeout(ring->irq_queue,
1945 EXIT_COND,
1946 timeout_jiffies);
1947 else
1948 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1949 timeout_jiffies);
1950
1951 if (atomic_read(&dev_priv->mm.wedged))
1952 end = -EAGAIN;
1953 } while (end == 0 && wait_forever);
1954
1955 getrawmonotonic(&now);
1956
1957 ring->irq_put(ring);
1958 trace_i915_gem_request_wait_end(ring, seqno);
1959#undef EXIT_COND
1960
1961 if (timeout) {
1962 struct timespec sleep_time = timespec_sub(now, before);
1963 *timeout = timespec_sub(*timeout, sleep_time);
1964 }
1965
1966 switch (end) {
1967 case -EAGAIN: /* Wedged */
1968 case -ERESTARTSYS: /* Signal */
1969 return (int)end;
1970 case 0: /* Timeout */
1971 if (timeout)
1972 set_normalized_timespec(timeout, 0, 0);
1973 return -ETIME;
1974 default: /* Completed */
1975 WARN_ON(end < 0); /* We're not aware of other errors */
1976 return 0;
1977 }
1978}
1979
1980/**
1981 * Waits for a sequence number to be signaled, and cleans up the
1982 * request and object lists appropriately for that event.
1983 */
1984int
1985i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1986{
1987 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1988 int ret = 0;
1989
1990 BUG_ON(seqno == 0);
1991
1992 ret = i915_gem_check_wedge(dev_priv);
1993 if (ret)
1994 return ret;
1995
1996 ret = i915_gem_check_olr(ring, seqno);
1997 if (ret)
1998 return ret;
1999
2000 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL);
2001
2002 return ret;
2003}
2004
2005/**
2006 * Ensures that all rendering to the object has completed and the object is
2007 * safe to unbind from the GTT or access from the CPU.
2008 */
2009int
2010i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2011{
2012 int ret;
2013
2014 /* This function only exists to support waiting for existing rendering,
2015 * not for emitting required flushes.
2016 */
2017 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2018
2019 /* If there is rendering queued on the buffer being evicted, wait for
2020 * it.
2021 */
2022 if (obj->active) {
2023 ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno);
2024 if (ret)
2025 return ret;
2026 i915_gem_retire_requests_ring(obj->ring);
2027 }
2028
2029 return 0;
2030}
2031
2032/**
2033 * Ensures that an object will eventually get non-busy by flushing any required
2034 * write domains, emitting any outstanding lazy request and retiring and
2035 * completed requests.
2036 */
2037static int
2038i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2039{
2040 int ret;
2041
2042 if (obj->active) {
2043 ret = i915_gem_object_flush_gpu_write_domain(obj);
2044 if (ret)
2045 return ret;
2046
2047 ret = i915_gem_check_olr(obj->ring,
2048 obj->last_rendering_seqno);
2049 if (ret)
2050 return ret;
2051 i915_gem_retire_requests_ring(obj->ring);
2052 }
2053
2054 return 0;
2055}
2056
2057/**
2058 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2059 * @DRM_IOCTL_ARGS: standard ioctl arguments
2060 *
2061 * Returns 0 if successful, else an error is returned with the remaining time in
2062 * the timeout parameter.
2063 * -ETIME: object is still busy after timeout
2064 * -ERESTARTSYS: signal interrupted the wait
2065 * -ENONENT: object doesn't exist
2066 * Also possible, but rare:
2067 * -EAGAIN: GPU wedged
2068 * -ENOMEM: damn
2069 * -ENODEV: Internal IRQ fail
2070 * -E?: The add request failed
2071 *
2072 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2073 * non-zero timeout parameter the wait ioctl will wait for the given number of
2074 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2075 * without holding struct_mutex the object may become re-busied before this
2076 * function completes. A similar but shorter * race condition exists in the busy
2077 * ioctl
2078 */
2079int
2080i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2081{
2082 struct drm_i915_gem_wait *args = data;
2083 struct drm_i915_gem_object *obj;
2084 struct intel_ring_buffer *ring = NULL;
2085 struct timespec timeout_stack, *timeout = NULL;
2086 u32 seqno = 0;
2087 int ret = 0;
2088
2089 if (args->timeout_ns >= 0) {
2090 timeout_stack = ns_to_timespec(args->timeout_ns);
2091 timeout = &timeout_stack;
2092 }
2093
2094 ret = i915_mutex_lock_interruptible(dev);
2095 if (ret)
2096 return ret;
2097
2098 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2099 if (&obj->base == NULL) {
2100 mutex_unlock(&dev->struct_mutex);
2101 return -ENOENT;
2102 }
2103
2104 /* Need to make sure the object gets inactive eventually. */
2105 ret = i915_gem_object_flush_active(obj);
2106 if (ret)
2107 goto out;
2108
2109 if (obj->active) {
2110 seqno = obj->last_rendering_seqno;
2111 ring = obj->ring;
2112 }
2113
2114 if (seqno == 0)
2115 goto out;
2116
2117 /* Do this after OLR check to make sure we make forward progress polling
2118 * on this IOCTL with a 0 timeout (like busy ioctl)
2119 */
2120 if (!args->timeout_ns) {
2121 ret = -ETIME;
2122 goto out;
2123 }
2124
2125 drm_gem_object_unreference(&obj->base);
2126 mutex_unlock(&dev->struct_mutex);
2127
2128 ret = __wait_seqno(ring, seqno, true, timeout);
2129 if (timeout) {
2130 WARN_ON(!timespec_valid(timeout));
2131 args->timeout_ns = timespec_to_ns(timeout);
2132 }
2133 return ret;
2134
2135out:
2136 drm_gem_object_unreference(&obj->base);
2137 mutex_unlock(&dev->struct_mutex);
2138 return ret;
2139}
2140
2141/**
2142 * i915_gem_object_sync - sync an object to a ring.
2143 *
2144 * @obj: object which may be in use on another ring.
2145 * @to: ring we wish to use the object on. May be NULL.
2146 *
2147 * This code is meant to abstract object synchronization with the GPU.
2148 * Calling with NULL implies synchronizing the object with the CPU
2149 * rather than a particular GPU ring.
2150 *
2151 * Returns 0 if successful, else propagates up the lower layer error.
2152 */
2153int
2154i915_gem_object_sync(struct drm_i915_gem_object *obj,
2155 struct intel_ring_buffer *to)
2156{
2157 struct intel_ring_buffer *from = obj->ring;
2158 u32 seqno;
2159 int ret, idx;
2160
2161 if (from == NULL || to == from)
2162 return 0;
2163
2164 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2165 return i915_gem_object_wait_rendering(obj);
2166
2167 idx = intel_ring_sync_index(from, to);
2168
2169 seqno = obj->last_rendering_seqno;
2170 if (seqno <= from->sync_seqno[idx])
2171 return 0;
2172
2173 ret = i915_gem_check_olr(obj->ring, seqno);
2174 if (ret)
2175 return ret;
2176
2177 ret = to->sync_to(to, from, seqno);
2178 if (!ret)
2179 from->sync_seqno[idx] = seqno;
2180
2181 return ret;
2182}
2183
2184static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2185{
2186 u32 old_write_domain, old_read_domains;
2187
2188 /* Act a barrier for all accesses through the GTT */
2189 mb();
2190
2191 /* Force a pagefault for domain tracking on next user access */
2192 i915_gem_release_mmap(obj);
2193
2194 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2195 return;
2196
2197 old_read_domains = obj->base.read_domains;
2198 old_write_domain = obj->base.write_domain;
2199
2200 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2201 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2202
2203 trace_i915_gem_object_change_domain(obj,
2204 old_read_domains,
2205 old_write_domain);
2206}
2207
2208/**
2209 * Unbinds an object from the GTT aperture.
2210 */
2211int
2212i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2213{
2214 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2215 int ret = 0;
2216
2217 if (obj->gtt_space == NULL)
2218 return 0;
2219
2220 if (obj->pin_count)
2221 return -EBUSY;
2222
2223 ret = i915_gem_object_finish_gpu(obj);
2224 if (ret)
2225 return ret;
2226 /* Continue on if we fail due to EIO, the GPU is hung so we
2227 * should be safe and we need to cleanup or else we might
2228 * cause memory corruption through use-after-free.
2229 */
2230
2231 i915_gem_object_finish_gtt(obj);
2232
2233 /* Move the object to the CPU domain to ensure that
2234 * any possible CPU writes while it's not in the GTT
2235 * are flushed when we go to remap it.
2236 */
2237 if (ret == 0)
2238 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2239 if (ret == -ERESTARTSYS)
2240 return ret;
2241 if (ret) {
2242 /* In the event of a disaster, abandon all caches and
2243 * hope for the best.
2244 */
2245 i915_gem_clflush_object(obj);
2246 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2247 }
2248
2249 /* release the fence reg _after_ flushing */
2250 ret = i915_gem_object_put_fence(obj);
2251 if (ret)
2252 return ret;
2253
2254 trace_i915_gem_object_unbind(obj);
2255
2256 if (obj->has_global_gtt_mapping)
2257 i915_gem_gtt_unbind_object(obj);
2258 if (obj->has_aliasing_ppgtt_mapping) {
2259 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2260 obj->has_aliasing_ppgtt_mapping = 0;
2261 }
2262 i915_gem_gtt_finish_object(obj);
2263
2264 i915_gem_object_put_pages_gtt(obj);
2265
2266 list_del_init(&obj->gtt_list);
2267 list_del_init(&obj->mm_list);
2268 /* Avoid an unnecessary call to unbind on rebind. */
2269 obj->map_and_fenceable = true;
2270
2271 drm_mm_put_block(obj->gtt_space);
2272 obj->gtt_space = NULL;
2273 obj->gtt_offset = 0;
2274
2275 if (i915_gem_object_is_purgeable(obj))
2276 i915_gem_object_truncate(obj);
2277
2278 return ret;
2279}
2280
2281int
2282i915_gem_flush_ring(struct intel_ring_buffer *ring,
2283 uint32_t invalidate_domains,
2284 uint32_t flush_domains)
2285{
2286 int ret;
2287
2288 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2289 return 0;
2290
2291 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2292
2293 ret = ring->flush(ring, invalidate_domains, flush_domains);
2294 if (ret)
2295 return ret;
2296
2297 if (flush_domains & I915_GEM_GPU_DOMAINS)
2298 i915_gem_process_flushing_list(ring, flush_domains);
2299
2300 return 0;
2301}
2302
2303static int i915_ring_idle(struct intel_ring_buffer *ring)
2304{
2305 int ret;
2306
2307 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2308 return 0;
2309
2310 if (!list_empty(&ring->gpu_write_list)) {
2311 ret = i915_gem_flush_ring(ring,
2312 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2313 if (ret)
2314 return ret;
2315 }
2316
2317 return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2318}
2319
2320int i915_gpu_idle(struct drm_device *dev)
2321{
2322 drm_i915_private_t *dev_priv = dev->dev_private;
2323 struct intel_ring_buffer *ring;
2324 int ret, i;
2325
2326 /* Flush everything onto the inactive list. */
2327 for_each_ring(ring, dev_priv, i) {
2328 ret = i915_ring_idle(ring);
2329 if (ret)
2330 return ret;
2331
2332 /* Is the device fubar? */
2333 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2334 return -EBUSY;
2335 }
2336
2337 return 0;
2338}
2339
2340static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2341 struct drm_i915_gem_object *obj)
2342{
2343 drm_i915_private_t *dev_priv = dev->dev_private;
2344 uint64_t val;
2345
2346 if (obj) {
2347 u32 size = obj->gtt_space->size;
2348
2349 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2350 0xfffff000) << 32;
2351 val |= obj->gtt_offset & 0xfffff000;
2352 val |= (uint64_t)((obj->stride / 128) - 1) <<
2353 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2354
2355 if (obj->tiling_mode == I915_TILING_Y)
2356 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2357 val |= I965_FENCE_REG_VALID;
2358 } else
2359 val = 0;
2360
2361 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2362 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2363}
2364
2365static void i965_write_fence_reg(struct drm_device *dev, int reg,
2366 struct drm_i915_gem_object *obj)
2367{
2368 drm_i915_private_t *dev_priv = dev->dev_private;
2369 uint64_t val;
2370
2371 if (obj) {
2372 u32 size = obj->gtt_space->size;
2373
2374 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2375 0xfffff000) << 32;
2376 val |= obj->gtt_offset & 0xfffff000;
2377 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2378 if (obj->tiling_mode == I915_TILING_Y)
2379 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2380 val |= I965_FENCE_REG_VALID;
2381 } else
2382 val = 0;
2383
2384 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2385 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2386}
2387
2388static void i915_write_fence_reg(struct drm_device *dev, int reg,
2389 struct drm_i915_gem_object *obj)
2390{
2391 drm_i915_private_t *dev_priv = dev->dev_private;
2392 u32 val;
2393
2394 if (obj) {
2395 u32 size = obj->gtt_space->size;
2396 int pitch_val;
2397 int tile_width;
2398
2399 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2400 (size & -size) != size ||
2401 (obj->gtt_offset & (size - 1)),
2402 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2403 obj->gtt_offset, obj->map_and_fenceable, size);
2404
2405 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2406 tile_width = 128;
2407 else
2408 tile_width = 512;
2409
2410 /* Note: pitch better be a power of two tile widths */
2411 pitch_val = obj->stride / tile_width;
2412 pitch_val = ffs(pitch_val) - 1;
2413
2414 val = obj->gtt_offset;
2415 if (obj->tiling_mode == I915_TILING_Y)
2416 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2417 val |= I915_FENCE_SIZE_BITS(size);
2418 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2419 val |= I830_FENCE_REG_VALID;
2420 } else
2421 val = 0;
2422
2423 if (reg < 8)
2424 reg = FENCE_REG_830_0 + reg * 4;
2425 else
2426 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2427
2428 I915_WRITE(reg, val);
2429 POSTING_READ(reg);
2430}
2431
2432static void i830_write_fence_reg(struct drm_device *dev, int reg,
2433 struct drm_i915_gem_object *obj)
2434{
2435 drm_i915_private_t *dev_priv = dev->dev_private;
2436 uint32_t val;
2437
2438 if (obj) {
2439 u32 size = obj->gtt_space->size;
2440 uint32_t pitch_val;
2441
2442 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2443 (size & -size) != size ||
2444 (obj->gtt_offset & (size - 1)),
2445 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2446 obj->gtt_offset, size);
2447
2448 pitch_val = obj->stride / 128;
2449 pitch_val = ffs(pitch_val) - 1;
2450
2451 val = obj->gtt_offset;
2452 if (obj->tiling_mode == I915_TILING_Y)
2453 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2454 val |= I830_FENCE_SIZE_BITS(size);
2455 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2456 val |= I830_FENCE_REG_VALID;
2457 } else
2458 val = 0;
2459
2460 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2461 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2462}
2463
2464static void i915_gem_write_fence(struct drm_device *dev, int reg,
2465 struct drm_i915_gem_object *obj)
2466{
2467 switch (INTEL_INFO(dev)->gen) {
2468 case 7:
2469 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2470 case 5:
2471 case 4: i965_write_fence_reg(dev, reg, obj); break;
2472 case 3: i915_write_fence_reg(dev, reg, obj); break;
2473 case 2: i830_write_fence_reg(dev, reg, obj); break;
2474 default: break;
2475 }
2476}
2477
2478static inline int fence_number(struct drm_i915_private *dev_priv,
2479 struct drm_i915_fence_reg *fence)
2480{
2481 return fence - dev_priv->fence_regs;
2482}
2483
2484static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2485 struct drm_i915_fence_reg *fence,
2486 bool enable)
2487{
2488 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2489 int reg = fence_number(dev_priv, fence);
2490
2491 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2492
2493 if (enable) {
2494 obj->fence_reg = reg;
2495 fence->obj = obj;
2496 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2497 } else {
2498 obj->fence_reg = I915_FENCE_REG_NONE;
2499 fence->obj = NULL;
2500 list_del_init(&fence->lru_list);
2501 }
2502}
2503
2504static int
2505i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2506{
2507 int ret;
2508
2509 if (obj->fenced_gpu_access) {
2510 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2511 ret = i915_gem_flush_ring(obj->ring,
2512 0, obj->base.write_domain);
2513 if (ret)
2514 return ret;
2515 }
2516
2517 obj->fenced_gpu_access = false;
2518 }
2519
2520 if (obj->last_fenced_seqno) {
2521 ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2522 if (ret)
2523 return ret;
2524
2525 obj->last_fenced_seqno = 0;
2526 }
2527
2528 /* Ensure that all CPU reads are completed before installing a fence
2529 * and all writes before removing the fence.
2530 */
2531 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2532 mb();
2533
2534 return 0;
2535}
2536
2537int
2538i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2539{
2540 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2541 int ret;
2542
2543 ret = i915_gem_object_flush_fence(obj);
2544 if (ret)
2545 return ret;
2546
2547 if (obj->fence_reg == I915_FENCE_REG_NONE)
2548 return 0;
2549
2550 i915_gem_object_update_fence(obj,
2551 &dev_priv->fence_regs[obj->fence_reg],
2552 false);
2553 i915_gem_object_fence_lost(obj);
2554
2555 return 0;
2556}
2557
2558static struct drm_i915_fence_reg *
2559i915_find_fence_reg(struct drm_device *dev)
2560{
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct drm_i915_fence_reg *reg, *avail;
2563 int i;
2564
2565 /* First try to find a free reg */
2566 avail = NULL;
2567 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2568 reg = &dev_priv->fence_regs[i];
2569 if (!reg->obj)
2570 return reg;
2571
2572 if (!reg->pin_count)
2573 avail = reg;
2574 }
2575
2576 if (avail == NULL)
2577 return NULL;
2578
2579 /* None available, try to steal one or wait for a user to finish */
2580 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2581 if (reg->pin_count)
2582 continue;
2583
2584 return reg;
2585 }
2586
2587 return NULL;
2588}
2589
2590/**
2591 * i915_gem_object_get_fence - set up fencing for an object
2592 * @obj: object to map through a fence reg
2593 *
2594 * When mapping objects through the GTT, userspace wants to be able to write
2595 * to them without having to worry about swizzling if the object is tiled.
2596 * This function walks the fence regs looking for a free one for @obj,
2597 * stealing one if it can't find any.
2598 *
2599 * It then sets up the reg based on the object's properties: address, pitch
2600 * and tiling format.
2601 *
2602 * For an untiled surface, this removes any existing fence.
2603 */
2604int
2605i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2606{
2607 struct drm_device *dev = obj->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 bool enable = obj->tiling_mode != I915_TILING_NONE;
2610 struct drm_i915_fence_reg *reg;
2611 int ret;
2612
2613 /* Have we updated the tiling parameters upon the object and so
2614 * will need to serialise the write to the associated fence register?
2615 */
2616 if (obj->fence_dirty) {
2617 ret = i915_gem_object_flush_fence(obj);
2618 if (ret)
2619 return ret;
2620 }
2621
2622 /* Just update our place in the LRU if our fence is getting reused. */
2623 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2624 reg = &dev_priv->fence_regs[obj->fence_reg];
2625 if (!obj->fence_dirty) {
2626 list_move_tail(&reg->lru_list,
2627 &dev_priv->mm.fence_list);
2628 return 0;
2629 }
2630 } else if (enable) {
2631 reg = i915_find_fence_reg(dev);
2632 if (reg == NULL)
2633 return -EDEADLK;
2634
2635 if (reg->obj) {
2636 struct drm_i915_gem_object *old = reg->obj;
2637
2638 ret = i915_gem_object_flush_fence(old);
2639 if (ret)
2640 return ret;
2641
2642 i915_gem_object_fence_lost(old);
2643 }
2644 } else
2645 return 0;
2646
2647 i915_gem_object_update_fence(obj, reg, enable);
2648 obj->fence_dirty = false;
2649
2650 return 0;
2651}
2652
2653/**
2654 * Finds free space in the GTT aperture and binds the object there.
2655 */
2656static int
2657i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2658 unsigned alignment,
2659 bool map_and_fenceable)
2660{
2661 struct drm_device *dev = obj->base.dev;
2662 drm_i915_private_t *dev_priv = dev->dev_private;
2663 struct drm_mm_node *free_space;
2664 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2665 u32 size, fence_size, fence_alignment, unfenced_alignment;
2666 bool mappable, fenceable;
2667 int ret;
2668
2669 if (obj->madv != I915_MADV_WILLNEED) {
2670 DRM_ERROR("Attempting to bind a purgeable object\n");
2671 return -EINVAL;
2672 }
2673
2674 fence_size = i915_gem_get_gtt_size(dev,
2675 obj->base.size,
2676 obj->tiling_mode);
2677 fence_alignment = i915_gem_get_gtt_alignment(dev,
2678 obj->base.size,
2679 obj->tiling_mode);
2680 unfenced_alignment =
2681 i915_gem_get_unfenced_gtt_alignment(dev,
2682 obj->base.size,
2683 obj->tiling_mode);
2684
2685 if (alignment == 0)
2686 alignment = map_and_fenceable ? fence_alignment :
2687 unfenced_alignment;
2688 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2689 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2690 return -EINVAL;
2691 }
2692
2693 size = map_and_fenceable ? fence_size : obj->base.size;
2694
2695 /* If the object is bigger than the entire aperture, reject it early
2696 * before evicting everything in a vain attempt to find space.
2697 */
2698 if (obj->base.size >
2699 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2700 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2701 return -E2BIG;
2702 }
2703
2704 search_free:
2705 if (map_and_fenceable)
2706 free_space =
2707 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2708 size, alignment, 0,
2709 dev_priv->mm.gtt_mappable_end,
2710 0);
2711 else
2712 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2713 size, alignment, 0);
2714
2715 if (free_space != NULL) {
2716 if (map_and_fenceable)
2717 obj->gtt_space =
2718 drm_mm_get_block_range_generic(free_space,
2719 size, alignment, 0,
2720 dev_priv->mm.gtt_mappable_end,
2721 0);
2722 else
2723 obj->gtt_space =
2724 drm_mm_get_block(free_space, size, alignment);
2725 }
2726 if (obj->gtt_space == NULL) {
2727 /* If the gtt is empty and we're still having trouble
2728 * fitting our object in, we're out of memory.
2729 */
2730 ret = i915_gem_evict_something(dev, size, alignment,
2731 map_and_fenceable);
2732 if (ret)
2733 return ret;
2734
2735 goto search_free;
2736 }
2737
2738 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2739 if (ret) {
2740 drm_mm_put_block(obj->gtt_space);
2741 obj->gtt_space = NULL;
2742
2743 if (ret == -ENOMEM) {
2744 /* first try to reclaim some memory by clearing the GTT */
2745 ret = i915_gem_evict_everything(dev, false);
2746 if (ret) {
2747 /* now try to shrink everyone else */
2748 if (gfpmask) {
2749 gfpmask = 0;
2750 goto search_free;
2751 }
2752
2753 return -ENOMEM;
2754 }
2755
2756 goto search_free;
2757 }
2758
2759 return ret;
2760 }
2761
2762 ret = i915_gem_gtt_prepare_object(obj);
2763 if (ret) {
2764 i915_gem_object_put_pages_gtt(obj);
2765 drm_mm_put_block(obj->gtt_space);
2766 obj->gtt_space = NULL;
2767
2768 if (i915_gem_evict_everything(dev, false))
2769 return ret;
2770
2771 goto search_free;
2772 }
2773
2774 if (!dev_priv->mm.aliasing_ppgtt)
2775 i915_gem_gtt_bind_object(obj, obj->cache_level);
2776
2777 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2778 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2779
2780 /* Assert that the object is not currently in any GPU domain. As it
2781 * wasn't in the GTT, there shouldn't be any way it could have been in
2782 * a GPU cache
2783 */
2784 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2785 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2786
2787 obj->gtt_offset = obj->gtt_space->start;
2788
2789 fenceable =
2790 obj->gtt_space->size == fence_size &&
2791 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2792
2793 mappable =
2794 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2795
2796 obj->map_and_fenceable = mappable && fenceable;
2797
2798 trace_i915_gem_object_bind(obj, map_and_fenceable);
2799 return 0;
2800}
2801
2802void
2803i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2804{
2805 /* If we don't have a page list set up, then we're not pinned
2806 * to GPU, and we can ignore the cache flush because it'll happen
2807 * again at bind time.
2808 */
2809 if (obj->pages == NULL)
2810 return;
2811
2812 /* If the GPU is snooping the contents of the CPU cache,
2813 * we do not need to manually clear the CPU cache lines. However,
2814 * the caches are only snooped when the render cache is
2815 * flushed/invalidated. As we always have to emit invalidations
2816 * and flushes when moving into and out of the RENDER domain, correct
2817 * snooping behaviour occurs naturally as the result of our domain
2818 * tracking.
2819 */
2820 if (obj->cache_level != I915_CACHE_NONE)
2821 return;
2822
2823 trace_i915_gem_object_clflush(obj);
2824
2825 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2826}
2827
2828/** Flushes any GPU write domain for the object if it's dirty. */
2829static int
2830i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2831{
2832 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2833 return 0;
2834
2835 /* Queue the GPU write cache flushing we need. */
2836 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2837}
2838
2839/** Flushes the GTT write domain for the object if it's dirty. */
2840static void
2841i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2842{
2843 uint32_t old_write_domain;
2844
2845 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2846 return;
2847
2848 /* No actual flushing is required for the GTT write domain. Writes
2849 * to it immediately go to main memory as far as we know, so there's
2850 * no chipset flush. It also doesn't land in render cache.
2851 *
2852 * However, we do have to enforce the order so that all writes through
2853 * the GTT land before any writes to the device, such as updates to
2854 * the GATT itself.
2855 */
2856 wmb();
2857
2858 old_write_domain = obj->base.write_domain;
2859 obj->base.write_domain = 0;
2860
2861 trace_i915_gem_object_change_domain(obj,
2862 obj->base.read_domains,
2863 old_write_domain);
2864}
2865
2866/** Flushes the CPU write domain for the object if it's dirty. */
2867static void
2868i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2869{
2870 uint32_t old_write_domain;
2871
2872 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2873 return;
2874
2875 i915_gem_clflush_object(obj);
2876 intel_gtt_chipset_flush();
2877 old_write_domain = obj->base.write_domain;
2878 obj->base.write_domain = 0;
2879
2880 trace_i915_gem_object_change_domain(obj,
2881 obj->base.read_domains,
2882 old_write_domain);
2883}
2884
2885/**
2886 * Moves a single object to the GTT read, and possibly write domain.
2887 *
2888 * This function returns when the move is complete, including waiting on
2889 * flushes to occur.
2890 */
2891int
2892i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2893{
2894 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2895 uint32_t old_write_domain, old_read_domains;
2896 int ret;
2897
2898 /* Not valid to be called on unbound objects. */
2899 if (obj->gtt_space == NULL)
2900 return -EINVAL;
2901
2902 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2903 return 0;
2904
2905 ret = i915_gem_object_flush_gpu_write_domain(obj);
2906 if (ret)
2907 return ret;
2908
2909 if (obj->pending_gpu_write || write) {
2910 ret = i915_gem_object_wait_rendering(obj);
2911 if (ret)
2912 return ret;
2913 }
2914
2915 i915_gem_object_flush_cpu_write_domain(obj);
2916
2917 old_write_domain = obj->base.write_domain;
2918 old_read_domains = obj->base.read_domains;
2919
2920 /* It should now be out of any other write domains, and we can update
2921 * the domain values for our changes.
2922 */
2923 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2924 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2925 if (write) {
2926 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2927 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2928 obj->dirty = 1;
2929 }
2930
2931 trace_i915_gem_object_change_domain(obj,
2932 old_read_domains,
2933 old_write_domain);
2934
2935 /* And bump the LRU for this access */
2936 if (i915_gem_object_is_inactive(obj))
2937 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2938
2939 return 0;
2940}
2941
2942int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2943 enum i915_cache_level cache_level)
2944{
2945 struct drm_device *dev = obj->base.dev;
2946 drm_i915_private_t *dev_priv = dev->dev_private;
2947 int ret;
2948
2949 if (obj->cache_level == cache_level)
2950 return 0;
2951
2952 if (obj->pin_count) {
2953 DRM_DEBUG("can not change the cache level of pinned objects\n");
2954 return -EBUSY;
2955 }
2956
2957 if (obj->gtt_space) {
2958 ret = i915_gem_object_finish_gpu(obj);
2959 if (ret)
2960 return ret;
2961
2962 i915_gem_object_finish_gtt(obj);
2963
2964 /* Before SandyBridge, you could not use tiling or fence
2965 * registers with snooped memory, so relinquish any fences
2966 * currently pointing to our region in the aperture.
2967 */
2968 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2969 ret = i915_gem_object_put_fence(obj);
2970 if (ret)
2971 return ret;
2972 }
2973
2974 if (obj->has_global_gtt_mapping)
2975 i915_gem_gtt_bind_object(obj, cache_level);
2976 if (obj->has_aliasing_ppgtt_mapping)
2977 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2978 obj, cache_level);
2979 }
2980
2981 if (cache_level == I915_CACHE_NONE) {
2982 u32 old_read_domains, old_write_domain;
2983
2984 /* If we're coming from LLC cached, then we haven't
2985 * actually been tracking whether the data is in the
2986 * CPU cache or not, since we only allow one bit set
2987 * in obj->write_domain and have been skipping the clflushes.
2988 * Just set it to the CPU cache for now.
2989 */
2990 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2991 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2992
2993 old_read_domains = obj->base.read_domains;
2994 old_write_domain = obj->base.write_domain;
2995
2996 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2997 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2998
2999 trace_i915_gem_object_change_domain(obj,
3000 old_read_domains,
3001 old_write_domain);
3002 }
3003
3004 obj->cache_level = cache_level;
3005 return 0;
3006}
3007
3008/*
3009 * Prepare buffer for display plane (scanout, cursors, etc).
3010 * Can be called from an uninterruptible phase (modesetting) and allows
3011 * any flushes to be pipelined (for pageflips).
3012 */
3013int
3014i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3015 u32 alignment,
3016 struct intel_ring_buffer *pipelined)
3017{
3018 u32 old_read_domains, old_write_domain;
3019 int ret;
3020
3021 ret = i915_gem_object_flush_gpu_write_domain(obj);
3022 if (ret)
3023 return ret;
3024
3025 if (pipelined != obj->ring) {
3026 ret = i915_gem_object_sync(obj, pipelined);
3027 if (ret)
3028 return ret;
3029 }
3030
3031 /* The display engine is not coherent with the LLC cache on gen6. As
3032 * a result, we make sure that the pinning that is about to occur is
3033 * done with uncached PTEs. This is lowest common denominator for all
3034 * chipsets.
3035 *
3036 * However for gen6+, we could do better by using the GFDT bit instead
3037 * of uncaching, which would allow us to flush all the LLC-cached data
3038 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3039 */
3040 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3041 if (ret)
3042 return ret;
3043
3044 /* As the user may map the buffer once pinned in the display plane
3045 * (e.g. libkms for the bootup splash), we have to ensure that we
3046 * always use map_and_fenceable for all scanout buffers.
3047 */
3048 ret = i915_gem_object_pin(obj, alignment, true);
3049 if (ret)
3050 return ret;
3051
3052 i915_gem_object_flush_cpu_write_domain(obj);
3053
3054 old_write_domain = obj->base.write_domain;
3055 old_read_domains = obj->base.read_domains;
3056
3057 /* It should now be out of any other write domains, and we can update
3058 * the domain values for our changes.
3059 */
3060 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3061 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3062
3063 trace_i915_gem_object_change_domain(obj,
3064 old_read_domains,
3065 old_write_domain);
3066
3067 return 0;
3068}
3069
3070int
3071i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3072{
3073 int ret;
3074
3075 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3076 return 0;
3077
3078 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3079 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3080 if (ret)
3081 return ret;
3082 }
3083
3084 ret = i915_gem_object_wait_rendering(obj);
3085 if (ret)
3086 return ret;
3087
3088 /* Ensure that we invalidate the GPU's caches and TLBs. */
3089 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3090 return 0;
3091}
3092
3093/**
3094 * Moves a single object to the CPU read, and possibly write domain.
3095 *
3096 * This function returns when the move is complete, including waiting on
3097 * flushes to occur.
3098 */
3099int
3100i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3101{
3102 uint32_t old_write_domain, old_read_domains;
3103 int ret;
3104
3105 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3106 return 0;
3107
3108 ret = i915_gem_object_flush_gpu_write_domain(obj);
3109 if (ret)
3110 return ret;
3111
3112 if (write || obj->pending_gpu_write) {
3113 ret = i915_gem_object_wait_rendering(obj);
3114 if (ret)
3115 return ret;
3116 }
3117
3118 i915_gem_object_flush_gtt_write_domain(obj);
3119
3120 old_write_domain = obj->base.write_domain;
3121 old_read_domains = obj->base.read_domains;
3122
3123 /* Flush the CPU cache if it's still invalid. */
3124 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3125 i915_gem_clflush_object(obj);
3126
3127 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3128 }
3129
3130 /* It should now be out of any other write domains, and we can update
3131 * the domain values for our changes.
3132 */
3133 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3134
3135 /* If we're writing through the CPU, then the GPU read domains will
3136 * need to be invalidated at next use.
3137 */
3138 if (write) {
3139 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3140 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3141 }
3142
3143 trace_i915_gem_object_change_domain(obj,
3144 old_read_domains,
3145 old_write_domain);
3146
3147 return 0;
3148}
3149
3150/* Throttle our rendering by waiting until the ring has completed our requests
3151 * emitted over 20 msec ago.
3152 *
3153 * Note that if we were to use the current jiffies each time around the loop,
3154 * we wouldn't escape the function with any frames outstanding if the time to
3155 * render a frame was over 20ms.
3156 *
3157 * This should get us reasonable parallelism between CPU and GPU but also
3158 * relatively low latency when blocking on a particular request to finish.
3159 */
3160static int
3161i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3162{
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct drm_i915_file_private *file_priv = file->driver_priv;
3165 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3166 struct drm_i915_gem_request *request;
3167 struct intel_ring_buffer *ring = NULL;
3168 u32 seqno = 0;
3169 int ret;
3170
3171 if (atomic_read(&dev_priv->mm.wedged))
3172 return -EIO;
3173
3174 spin_lock(&file_priv->mm.lock);
3175 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3176 if (time_after_eq(request->emitted_jiffies, recent_enough))
3177 break;
3178
3179 ring = request->ring;
3180 seqno = request->seqno;
3181 }
3182 spin_unlock(&file_priv->mm.lock);
3183
3184 if (seqno == 0)
3185 return 0;
3186
3187 ret = __wait_seqno(ring, seqno, true, NULL);
3188 if (ret == 0)
3189 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3190
3191 return ret;
3192}
3193
3194int
3195i915_gem_object_pin(struct drm_i915_gem_object *obj,
3196 uint32_t alignment,
3197 bool map_and_fenceable)
3198{
3199 int ret;
3200
3201 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3202
3203 if (obj->gtt_space != NULL) {
3204 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3205 (map_and_fenceable && !obj->map_and_fenceable)) {
3206 WARN(obj->pin_count,
3207 "bo is already pinned with incorrect alignment:"
3208 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3209 " obj->map_and_fenceable=%d\n",
3210 obj->gtt_offset, alignment,
3211 map_and_fenceable,
3212 obj->map_and_fenceable);
3213 ret = i915_gem_object_unbind(obj);
3214 if (ret)
3215 return ret;
3216 }
3217 }
3218
3219 if (obj->gtt_space == NULL) {
3220 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3221 map_and_fenceable);
3222 if (ret)
3223 return ret;
3224 }
3225
3226 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3227 i915_gem_gtt_bind_object(obj, obj->cache_level);
3228
3229 obj->pin_count++;
3230 obj->pin_mappable |= map_and_fenceable;
3231
3232 return 0;
3233}
3234
3235void
3236i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3237{
3238 BUG_ON(obj->pin_count == 0);
3239 BUG_ON(obj->gtt_space == NULL);
3240
3241 if (--obj->pin_count == 0)
3242 obj->pin_mappable = false;
3243}
3244
3245int
3246i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3247 struct drm_file *file)
3248{
3249 struct drm_i915_gem_pin *args = data;
3250 struct drm_i915_gem_object *obj;
3251 int ret;
3252
3253 ret = i915_mutex_lock_interruptible(dev);
3254 if (ret)
3255 return ret;
3256
3257 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3258 if (&obj->base == NULL) {
3259 ret = -ENOENT;
3260 goto unlock;
3261 }
3262
3263 if (obj->madv != I915_MADV_WILLNEED) {
3264 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3265 ret = -EINVAL;
3266 goto out;
3267 }
3268
3269 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3270 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3271 args->handle);
3272 ret = -EINVAL;
3273 goto out;
3274 }
3275
3276 obj->user_pin_count++;
3277 obj->pin_filp = file;
3278 if (obj->user_pin_count == 1) {
3279 ret = i915_gem_object_pin(obj, args->alignment, true);
3280 if (ret)
3281 goto out;
3282 }
3283
3284 /* XXX - flush the CPU caches for pinned objects
3285 * as the X server doesn't manage domains yet
3286 */
3287 i915_gem_object_flush_cpu_write_domain(obj);
3288 args->offset = obj->gtt_offset;
3289out:
3290 drm_gem_object_unreference(&obj->base);
3291unlock:
3292 mutex_unlock(&dev->struct_mutex);
3293 return ret;
3294}
3295
3296int
3297i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3298 struct drm_file *file)
3299{
3300 struct drm_i915_gem_pin *args = data;
3301 struct drm_i915_gem_object *obj;
3302 int ret;
3303
3304 ret = i915_mutex_lock_interruptible(dev);
3305 if (ret)
3306 return ret;
3307
3308 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3309 if (&obj->base == NULL) {
3310 ret = -ENOENT;
3311 goto unlock;
3312 }
3313
3314 if (obj->pin_filp != file) {
3315 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3316 args->handle);
3317 ret = -EINVAL;
3318 goto out;
3319 }
3320 obj->user_pin_count--;
3321 if (obj->user_pin_count == 0) {
3322 obj->pin_filp = NULL;
3323 i915_gem_object_unpin(obj);
3324 }
3325
3326out:
3327 drm_gem_object_unreference(&obj->base);
3328unlock:
3329 mutex_unlock(&dev->struct_mutex);
3330 return ret;
3331}
3332
3333int
3334i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3335 struct drm_file *file)
3336{
3337 struct drm_i915_gem_busy *args = data;
3338 struct drm_i915_gem_object *obj;
3339 int ret;
3340
3341 ret = i915_mutex_lock_interruptible(dev);
3342 if (ret)
3343 return ret;
3344
3345 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3346 if (&obj->base == NULL) {
3347 ret = -ENOENT;
3348 goto unlock;
3349 }
3350
3351 /* Count all active objects as busy, even if they are currently not used
3352 * by the gpu. Users of this interface expect objects to eventually
3353 * become non-busy without any further actions, therefore emit any
3354 * necessary flushes here.
3355 */
3356 ret = i915_gem_object_flush_active(obj);
3357
3358 args->busy = obj->active;
3359
3360 drm_gem_object_unreference(&obj->base);
3361unlock:
3362 mutex_unlock(&dev->struct_mutex);
3363 return ret;
3364}
3365
3366int
3367i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3368 struct drm_file *file_priv)
3369{
3370 return i915_gem_ring_throttle(dev, file_priv);
3371}
3372
3373int
3374i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3375 struct drm_file *file_priv)
3376{
3377 struct drm_i915_gem_madvise *args = data;
3378 struct drm_i915_gem_object *obj;
3379 int ret;
3380
3381 switch (args->madv) {
3382 case I915_MADV_DONTNEED:
3383 case I915_MADV_WILLNEED:
3384 break;
3385 default:
3386 return -EINVAL;
3387 }
3388
3389 ret = i915_mutex_lock_interruptible(dev);
3390 if (ret)
3391 return ret;
3392
3393 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3394 if (&obj->base == NULL) {
3395 ret = -ENOENT;
3396 goto unlock;
3397 }
3398
3399 if (obj->pin_count) {
3400 ret = -EINVAL;
3401 goto out;
3402 }
3403
3404 if (obj->madv != __I915_MADV_PURGED)
3405 obj->madv = args->madv;
3406
3407 /* if the object is no longer bound, discard its backing storage */
3408 if (i915_gem_object_is_purgeable(obj) &&
3409 obj->gtt_space == NULL)
3410 i915_gem_object_truncate(obj);
3411
3412 args->retained = obj->madv != __I915_MADV_PURGED;
3413
3414out:
3415 drm_gem_object_unreference(&obj->base);
3416unlock:
3417 mutex_unlock(&dev->struct_mutex);
3418 return ret;
3419}
3420
3421struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3422 size_t size)
3423{
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct drm_i915_gem_object *obj;
3426 struct address_space *mapping;
3427 u32 mask;
3428
3429 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3430 if (obj == NULL)
3431 return NULL;
3432
3433 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3434 kfree(obj);
3435 return NULL;
3436 }
3437
3438 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3439 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3440 /* 965gm cannot relocate objects above 4GiB. */
3441 mask &= ~__GFP_HIGHMEM;
3442 mask |= __GFP_DMA32;
3443 }
3444
3445 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3446 mapping_set_gfp_mask(mapping, mask);
3447
3448 i915_gem_info_add_obj(dev_priv, size);
3449
3450 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3451 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3452
3453 if (HAS_LLC(dev)) {
3454 /* On some devices, we can have the GPU use the LLC (the CPU
3455 * cache) for about a 10% performance improvement
3456 * compared to uncached. Graphics requests other than
3457 * display scanout are coherent with the CPU in
3458 * accessing this cache. This means in this mode we
3459 * don't need to clflush on the CPU side, and on the
3460 * GPU side we only need to flush internal caches to
3461 * get data visible to the CPU.
3462 *
3463 * However, we maintain the display planes as UC, and so
3464 * need to rebind when first used as such.
3465 */
3466 obj->cache_level = I915_CACHE_LLC;
3467 } else
3468 obj->cache_level = I915_CACHE_NONE;
3469
3470 obj->base.driver_private = NULL;
3471 obj->fence_reg = I915_FENCE_REG_NONE;
3472 INIT_LIST_HEAD(&obj->mm_list);
3473 INIT_LIST_HEAD(&obj->gtt_list);
3474 INIT_LIST_HEAD(&obj->ring_list);
3475 INIT_LIST_HEAD(&obj->exec_list);
3476 INIT_LIST_HEAD(&obj->gpu_write_list);
3477 obj->madv = I915_MADV_WILLNEED;
3478 /* Avoid an unnecessary call to unbind on the first bind. */
3479 obj->map_and_fenceable = true;
3480
3481 return obj;
3482}
3483
3484int i915_gem_init_object(struct drm_gem_object *obj)
3485{
3486 BUG();
3487
3488 return 0;
3489}
3490
3491void i915_gem_free_object(struct drm_gem_object *gem_obj)
3492{
3493 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3494 struct drm_device *dev = obj->base.dev;
3495 drm_i915_private_t *dev_priv = dev->dev_private;
3496
3497 trace_i915_gem_object_destroy(obj);
3498
3499 if (gem_obj->import_attach)
3500 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3501
3502 if (obj->phys_obj)
3503 i915_gem_detach_phys_object(dev, obj);
3504
3505 obj->pin_count = 0;
3506 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3507 bool was_interruptible;
3508
3509 was_interruptible = dev_priv->mm.interruptible;
3510 dev_priv->mm.interruptible = false;
3511
3512 WARN_ON(i915_gem_object_unbind(obj));
3513
3514 dev_priv->mm.interruptible = was_interruptible;
3515 }
3516
3517 if (obj->base.map_list.map)
3518 drm_gem_free_mmap_offset(&obj->base);
3519
3520 drm_gem_object_release(&obj->base);
3521 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3522
3523 kfree(obj->bit_17);
3524 kfree(obj);
3525}
3526
3527int
3528i915_gem_idle(struct drm_device *dev)
3529{
3530 drm_i915_private_t *dev_priv = dev->dev_private;
3531 int ret;
3532
3533 mutex_lock(&dev->struct_mutex);
3534
3535 if (dev_priv->mm.suspended) {
3536 mutex_unlock(&dev->struct_mutex);
3537 return 0;
3538 }
3539
3540 ret = i915_gpu_idle(dev);
3541 if (ret) {
3542 mutex_unlock(&dev->struct_mutex);
3543 return ret;
3544 }
3545 i915_gem_retire_requests(dev);
3546
3547 /* Under UMS, be paranoid and evict. */
3548 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3549 i915_gem_evict_everything(dev, false);
3550
3551 i915_gem_reset_fences(dev);
3552
3553 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3554 * We need to replace this with a semaphore, or something.
3555 * And not confound mm.suspended!
3556 */
3557 dev_priv->mm.suspended = 1;
3558 del_timer_sync(&dev_priv->hangcheck_timer);
3559
3560 i915_kernel_lost_context(dev);
3561 i915_gem_cleanup_ringbuffer(dev);
3562
3563 mutex_unlock(&dev->struct_mutex);
3564
3565 /* Cancel the retire work handler, which should be idle now. */
3566 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3567
3568 return 0;
3569}
3570
3571void i915_gem_l3_remap(struct drm_device *dev)
3572{
3573 drm_i915_private_t *dev_priv = dev->dev_private;
3574 u32 misccpctl;
3575 int i;
3576
3577 if (!IS_IVYBRIDGE(dev))
3578 return;
3579
3580 if (!dev_priv->mm.l3_remap_info)
3581 return;
3582
3583 misccpctl = I915_READ(GEN7_MISCCPCTL);
3584 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3585 POSTING_READ(GEN7_MISCCPCTL);
3586
3587 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3588 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3589 if (remap && remap != dev_priv->mm.l3_remap_info[i/4])
3590 DRM_DEBUG("0x%x was already programmed to %x\n",
3591 GEN7_L3LOG_BASE + i, remap);
3592 if (remap && !dev_priv->mm.l3_remap_info[i/4])
3593 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3594 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);
3595 }
3596
3597 /* Make sure all the writes land before disabling dop clock gating */
3598 POSTING_READ(GEN7_L3LOG_BASE);
3599
3600 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3601}
3602
3603void i915_gem_init_swizzling(struct drm_device *dev)
3604{
3605 drm_i915_private_t *dev_priv = dev->dev_private;
3606
3607 if (INTEL_INFO(dev)->gen < 5 ||
3608 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3609 return;
3610
3611 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3612 DISP_TILE_SURFACE_SWIZZLING);
3613
3614 if (IS_GEN5(dev))
3615 return;
3616
3617 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3618 if (IS_GEN6(dev))
3619 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3620 else
3621 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3622}
3623
3624void i915_gem_init_ppgtt(struct drm_device *dev)
3625{
3626 drm_i915_private_t *dev_priv = dev->dev_private;
3627 uint32_t pd_offset;
3628 struct intel_ring_buffer *ring;
3629 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3630 uint32_t __iomem *pd_addr;
3631 uint32_t pd_entry;
3632 int i;
3633
3634 if (!dev_priv->mm.aliasing_ppgtt)
3635 return;
3636
3637
3638 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3639 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3640 dma_addr_t pt_addr;
3641
3642 if (dev_priv->mm.gtt->needs_dmar)
3643 pt_addr = ppgtt->pt_dma_addr[i];
3644 else
3645 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3646
3647 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3648 pd_entry |= GEN6_PDE_VALID;
3649
3650 writel(pd_entry, pd_addr + i);
3651 }
3652 readl(pd_addr);
3653
3654 pd_offset = ppgtt->pd_offset;
3655 pd_offset /= 64; /* in cachelines, */
3656 pd_offset <<= 16;
3657
3658 if (INTEL_INFO(dev)->gen == 6) {
3659 uint32_t ecochk, gab_ctl, ecobits;
3660
3661 ecobits = I915_READ(GAC_ECO_BITS);
3662 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3663
3664 gab_ctl = I915_READ(GAB_CTL);
3665 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3666
3667 ecochk = I915_READ(GAM_ECOCHK);
3668 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3669 ECOCHK_PPGTT_CACHE64B);
3670 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3671 } else if (INTEL_INFO(dev)->gen >= 7) {
3672 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3673 /* GFX_MODE is per-ring on gen7+ */
3674 }
3675
3676 for_each_ring(ring, dev_priv, i) {
3677 if (INTEL_INFO(dev)->gen >= 7)
3678 I915_WRITE(RING_MODE_GEN7(ring),
3679 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3680
3681 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3682 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3683 }
3684}
3685
3686int
3687i915_gem_init_hw(struct drm_device *dev)
3688{
3689 drm_i915_private_t *dev_priv = dev->dev_private;
3690 int ret;
3691
3692 i915_gem_l3_remap(dev);
3693
3694 i915_gem_init_swizzling(dev);
3695
3696 ret = intel_init_render_ring_buffer(dev);
3697 if (ret)
3698 return ret;
3699
3700 if (HAS_BSD(dev)) {
3701 ret = intel_init_bsd_ring_buffer(dev);
3702 if (ret)
3703 goto cleanup_render_ring;
3704 }
3705
3706 if (HAS_BLT(dev)) {
3707 ret = intel_init_blt_ring_buffer(dev);
3708 if (ret)
3709 goto cleanup_bsd_ring;
3710 }
3711
3712 dev_priv->next_seqno = 1;
3713
3714 i915_gem_init_ppgtt(dev);
3715
3716 return 0;
3717
3718cleanup_bsd_ring:
3719 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3720cleanup_render_ring:
3721 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3722 return ret;
3723}
3724
3725static bool
3726intel_enable_ppgtt(struct drm_device *dev)
3727{
3728 if (i915_enable_ppgtt >= 0)
3729 return i915_enable_ppgtt;
3730
3731#ifdef CONFIG_INTEL_IOMMU
3732 /* Disable ppgtt on SNB if VT-d is on. */
3733 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3734 return false;
3735#endif
3736
3737 return true;
3738}
3739
3740int i915_gem_init(struct drm_device *dev)
3741{
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 unsigned long gtt_size, mappable_size;
3744 int ret;
3745
3746 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3747 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3748
3749 mutex_lock(&dev->struct_mutex);
3750 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3751 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3752 * aperture accordingly when using aliasing ppgtt. */
3753 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3754
3755 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3756
3757 ret = i915_gem_init_aliasing_ppgtt(dev);
3758 if (ret) {
3759 mutex_unlock(&dev->struct_mutex);
3760 return ret;
3761 }
3762 } else {
3763 /* Let GEM Manage all of the aperture.
3764 *
3765 * However, leave one page at the end still bound to the scratch
3766 * page. There are a number of places where the hardware
3767 * apparently prefetches past the end of the object, and we've
3768 * seen multiple hangs with the GPU head pointer stuck in a
3769 * batchbuffer bound at the last page of the aperture. One page
3770 * should be enough to keep any prefetching inside of the
3771 * aperture.
3772 */
3773 i915_gem_init_global_gtt(dev, 0, mappable_size,
3774 gtt_size);
3775 }
3776
3777 ret = i915_gem_init_hw(dev);
3778 mutex_unlock(&dev->struct_mutex);
3779 if (ret) {
3780 i915_gem_cleanup_aliasing_ppgtt(dev);
3781 return ret;
3782 }
3783
3784 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3785 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3786 dev_priv->dri1.allow_batchbuffer = 1;
3787 return 0;
3788}
3789
3790void
3791i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3792{
3793 drm_i915_private_t *dev_priv = dev->dev_private;
3794 struct intel_ring_buffer *ring;
3795 int i;
3796
3797 for_each_ring(ring, dev_priv, i)
3798 intel_cleanup_ring_buffer(ring);
3799}
3800
3801int
3802i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3803 struct drm_file *file_priv)
3804{
3805 drm_i915_private_t *dev_priv = dev->dev_private;
3806 int ret;
3807
3808 if (drm_core_check_feature(dev, DRIVER_MODESET))
3809 return 0;
3810
3811 if (atomic_read(&dev_priv->mm.wedged)) {
3812 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3813 atomic_set(&dev_priv->mm.wedged, 0);
3814 }
3815
3816 mutex_lock(&dev->struct_mutex);
3817 dev_priv->mm.suspended = 0;
3818
3819 ret = i915_gem_init_hw(dev);
3820 if (ret != 0) {
3821 mutex_unlock(&dev->struct_mutex);
3822 return ret;
3823 }
3824
3825 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3826 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3827 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3828 mutex_unlock(&dev->struct_mutex);
3829
3830 ret = drm_irq_install(dev);
3831 if (ret)
3832 goto cleanup_ringbuffer;
3833
3834 return 0;
3835
3836cleanup_ringbuffer:
3837 mutex_lock(&dev->struct_mutex);
3838 i915_gem_cleanup_ringbuffer(dev);
3839 dev_priv->mm.suspended = 1;
3840 mutex_unlock(&dev->struct_mutex);
3841
3842 return ret;
3843}
3844
3845int
3846i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3847 struct drm_file *file_priv)
3848{
3849 if (drm_core_check_feature(dev, DRIVER_MODESET))
3850 return 0;
3851
3852 drm_irq_uninstall(dev);
3853 return i915_gem_idle(dev);
3854}
3855
3856void
3857i915_gem_lastclose(struct drm_device *dev)
3858{
3859 int ret;
3860
3861 if (drm_core_check_feature(dev, DRIVER_MODESET))
3862 return;
3863
3864 ret = i915_gem_idle(dev);
3865 if (ret)
3866 DRM_ERROR("failed to idle hardware: %d\n", ret);
3867}
3868
3869static void
3870init_ring_lists(struct intel_ring_buffer *ring)
3871{
3872 INIT_LIST_HEAD(&ring->active_list);
3873 INIT_LIST_HEAD(&ring->request_list);
3874 INIT_LIST_HEAD(&ring->gpu_write_list);
3875}
3876
3877void
3878i915_gem_load(struct drm_device *dev)
3879{
3880 int i;
3881 drm_i915_private_t *dev_priv = dev->dev_private;
3882
3883 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3884 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3885 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3886 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3887 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3888 for (i = 0; i < I915_NUM_RINGS; i++)
3889 init_ring_lists(&dev_priv->ring[i]);
3890 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3891 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3892 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3893 i915_gem_retire_work_handler);
3894 init_completion(&dev_priv->error_completion);
3895
3896 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3897 if (IS_GEN3(dev)) {
3898 I915_WRITE(MI_ARB_STATE,
3899 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3900 }
3901
3902 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3903
3904 /* Old X drivers will take 0-2 for front, back, depth buffers */
3905 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3906 dev_priv->fence_reg_start = 3;
3907
3908 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3909 dev_priv->num_fence_regs = 16;
3910 else
3911 dev_priv->num_fence_regs = 8;
3912
3913 /* Initialize fence registers to zero */
3914 i915_gem_reset_fences(dev);
3915
3916 i915_gem_detect_bit_6_swizzle(dev);
3917 init_waitqueue_head(&dev_priv->pending_flip_queue);
3918
3919 dev_priv->mm.interruptible = true;
3920
3921 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3922 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3923 register_shrinker(&dev_priv->mm.inactive_shrinker);
3924}
3925
3926/*
3927 * Create a physically contiguous memory object for this object
3928 * e.g. for cursor + overlay regs
3929 */
3930static int i915_gem_init_phys_object(struct drm_device *dev,
3931 int id, int size, int align)
3932{
3933 drm_i915_private_t *dev_priv = dev->dev_private;
3934 struct drm_i915_gem_phys_object *phys_obj;
3935 int ret;
3936
3937 if (dev_priv->mm.phys_objs[id - 1] || !size)
3938 return 0;
3939
3940 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3941 if (!phys_obj)
3942 return -ENOMEM;
3943
3944 phys_obj->id = id;
3945
3946 phys_obj->handle = drm_pci_alloc(dev, size, align);
3947 if (!phys_obj->handle) {
3948 ret = -ENOMEM;
3949 goto kfree_obj;
3950 }
3951#ifdef CONFIG_X86
3952 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3953#endif
3954
3955 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3956
3957 return 0;
3958kfree_obj:
3959 kfree(phys_obj);
3960 return ret;
3961}
3962
3963static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3964{
3965 drm_i915_private_t *dev_priv = dev->dev_private;
3966 struct drm_i915_gem_phys_object *phys_obj;
3967
3968 if (!dev_priv->mm.phys_objs[id - 1])
3969 return;
3970
3971 phys_obj = dev_priv->mm.phys_objs[id - 1];
3972 if (phys_obj->cur_obj) {
3973 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3974 }
3975
3976#ifdef CONFIG_X86
3977 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3978#endif
3979 drm_pci_free(dev, phys_obj->handle);
3980 kfree(phys_obj);
3981 dev_priv->mm.phys_objs[id - 1] = NULL;
3982}
3983
3984void i915_gem_free_all_phys_object(struct drm_device *dev)
3985{
3986 int i;
3987
3988 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3989 i915_gem_free_phys_object(dev, i);
3990}
3991
3992void i915_gem_detach_phys_object(struct drm_device *dev,
3993 struct drm_i915_gem_object *obj)
3994{
3995 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3996 char *vaddr;
3997 int i;
3998 int page_count;
3999
4000 if (!obj->phys_obj)
4001 return;
4002 vaddr = obj->phys_obj->handle->vaddr;
4003
4004 page_count = obj->base.size / PAGE_SIZE;
4005 for (i = 0; i < page_count; i++) {
4006 struct page *page = shmem_read_mapping_page(mapping, i);
4007 if (!IS_ERR(page)) {
4008 char *dst = kmap_atomic(page);
4009 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4010 kunmap_atomic(dst);
4011
4012 drm_clflush_pages(&page, 1);
4013
4014 set_page_dirty(page);
4015 mark_page_accessed(page);
4016 page_cache_release(page);
4017 }
4018 }
4019 intel_gtt_chipset_flush();
4020
4021 obj->phys_obj->cur_obj = NULL;
4022 obj->phys_obj = NULL;
4023}
4024
4025int
4026i915_gem_attach_phys_object(struct drm_device *dev,
4027 struct drm_i915_gem_object *obj,
4028 int id,
4029 int align)
4030{
4031 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4032 drm_i915_private_t *dev_priv = dev->dev_private;
4033 int ret = 0;
4034 int page_count;
4035 int i;
4036
4037 if (id > I915_MAX_PHYS_OBJECT)
4038 return -EINVAL;
4039
4040 if (obj->phys_obj) {
4041 if (obj->phys_obj->id == id)
4042 return 0;
4043 i915_gem_detach_phys_object(dev, obj);
4044 }
4045
4046 /* create a new object */
4047 if (!dev_priv->mm.phys_objs[id - 1]) {
4048 ret = i915_gem_init_phys_object(dev, id,
4049 obj->base.size, align);
4050 if (ret) {
4051 DRM_ERROR("failed to init phys object %d size: %zu\n",
4052 id, obj->base.size);
4053 return ret;
4054 }
4055 }
4056
4057 /* bind to the object */
4058 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4059 obj->phys_obj->cur_obj = obj;
4060
4061 page_count = obj->base.size / PAGE_SIZE;
4062
4063 for (i = 0; i < page_count; i++) {
4064 struct page *page;
4065 char *dst, *src;
4066
4067 page = shmem_read_mapping_page(mapping, i);
4068 if (IS_ERR(page))
4069 return PTR_ERR(page);
4070
4071 src = kmap_atomic(page);
4072 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4073 memcpy(dst, src, PAGE_SIZE);
4074 kunmap_atomic(src);
4075
4076 mark_page_accessed(page);
4077 page_cache_release(page);
4078 }
4079
4080 return 0;
4081}
4082
4083static int
4084i915_gem_phys_pwrite(struct drm_device *dev,
4085 struct drm_i915_gem_object *obj,
4086 struct drm_i915_gem_pwrite *args,
4087 struct drm_file *file_priv)
4088{
4089 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4090 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4091
4092 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4093 unsigned long unwritten;
4094
4095 /* The physical object once assigned is fixed for the lifetime
4096 * of the obj, so we can safely drop the lock and continue
4097 * to access vaddr.
4098 */
4099 mutex_unlock(&dev->struct_mutex);
4100 unwritten = copy_from_user(vaddr, user_data, args->size);
4101 mutex_lock(&dev->struct_mutex);
4102 if (unwritten)
4103 return -EFAULT;
4104 }
4105
4106 intel_gtt_chipset_flush();
4107 return 0;
4108}
4109
4110void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4111{
4112 struct drm_i915_file_private *file_priv = file->driver_priv;
4113
4114 /* Clean up our request list when the client is going away, so that
4115 * later retire_requests won't dereference our soon-to-be-gone
4116 * file_priv.
4117 */
4118 spin_lock(&file_priv->mm.lock);
4119 while (!list_empty(&file_priv->mm.request_list)) {
4120 struct drm_i915_gem_request *request;
4121
4122 request = list_first_entry(&file_priv->mm.request_list,
4123 struct drm_i915_gem_request,
4124 client_list);
4125 list_del(&request->client_list);
4126 request->file_priv = NULL;
4127 }
4128 spin_unlock(&file_priv->mm.lock);
4129}
4130
4131static int
4132i915_gpu_is_active(struct drm_device *dev)
4133{
4134 drm_i915_private_t *dev_priv = dev->dev_private;
4135 int lists_empty;
4136
4137 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4138 list_empty(&dev_priv->mm.active_list);
4139
4140 return !lists_empty;
4141}
4142
4143static int
4144i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4145{
4146 struct drm_i915_private *dev_priv =
4147 container_of(shrinker,
4148 struct drm_i915_private,
4149 mm.inactive_shrinker);
4150 struct drm_device *dev = dev_priv->dev;
4151 struct drm_i915_gem_object *obj, *next;
4152 int nr_to_scan = sc->nr_to_scan;
4153 int cnt;
4154
4155 if (!mutex_trylock(&dev->struct_mutex))
4156 return 0;
4157
4158 /* "fast-path" to count number of available objects */
4159 if (nr_to_scan == 0) {
4160 cnt = 0;
4161 list_for_each_entry(obj,
4162 &dev_priv->mm.inactive_list,
4163 mm_list)
4164 cnt++;
4165 mutex_unlock(&dev->struct_mutex);
4166 return cnt / 100 * sysctl_vfs_cache_pressure;
4167 }
4168
4169rescan:
4170 /* first scan for clean buffers */
4171 i915_gem_retire_requests(dev);
4172
4173 list_for_each_entry_safe(obj, next,
4174 &dev_priv->mm.inactive_list,
4175 mm_list) {
4176 if (i915_gem_object_is_purgeable(obj)) {
4177 if (i915_gem_object_unbind(obj) == 0 &&
4178 --nr_to_scan == 0)
4179 break;
4180 }
4181 }
4182
4183 /* second pass, evict/count anything still on the inactive list */
4184 cnt = 0;
4185 list_for_each_entry_safe(obj, next,
4186 &dev_priv->mm.inactive_list,
4187 mm_list) {
4188 if (nr_to_scan &&
4189 i915_gem_object_unbind(obj) == 0)
4190 nr_to_scan--;
4191 else
4192 cnt++;
4193 }
4194
4195 if (nr_to_scan && i915_gpu_is_active(dev)) {
4196 /*
4197 * We are desperate for pages, so as a last resort, wait
4198 * for the GPU to finish and discard whatever we can.
4199 * This has a dramatic impact to reduce the number of
4200 * OOM-killer events whilst running the GPU aggressively.
4201 */
4202 if (i915_gpu_idle(dev) == 0)
4203 goto rescan;
4204 }
4205 mutex_unlock(&dev->struct_mutex);
4206 return cnt / 100 * sysctl_vfs_cache_pressure;
4207}
Linux kernel - Deliverables
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