| 1 | /* |
| 2 | * Copyright © 2011-2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Ben Widawsky <ben@bwidawsk.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | /* |
| 29 | * This file implements HW context support. On gen5+ a HW context consists of an |
| 30 | * opaque GPU object which is referenced at times of context saves and restores. |
| 31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists |
| 32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though |
| 33 | * something like a context does exist for the media ring, the code only |
| 34 | * supports contexts for the render ring. |
| 35 | * |
| 36 | * In software, there is a distinction between contexts created by the user, |
| 37 | * and the default HW context. The default HW context is used by GPU clients |
| 38 | * that do not request setup of their own hardware context. The default |
| 39 | * context's state is never restored to help prevent programming errors. This |
| 40 | * would happen if a client ran and piggy-backed off another clients GPU state. |
| 41 | * The default context only exists to give the GPU some offset to load as the |
| 42 | * current to invoke a save of the context we actually care about. In fact, the |
| 43 | * code could likely be constructed, albeit in a more complicated fashion, to |
| 44 | * never use the default context, though that limits the driver's ability to |
| 45 | * swap out, and/or destroy other contexts. |
| 46 | * |
| 47 | * All other contexts are created as a request by the GPU client. These contexts |
| 48 | * store GPU state, and thus allow GPU clients to not re-emit state (and |
| 49 | * potentially query certain state) at any time. The kernel driver makes |
| 50 | * certain that the appropriate commands are inserted. |
| 51 | * |
| 52 | * The context life cycle is semi-complicated in that context BOs may live |
| 53 | * longer than the context itself because of the way the hardware, and object |
| 54 | * tracking works. Below is a very crude representation of the state machine |
| 55 | * describing the context life. |
| 56 | * refcount pincount active |
| 57 | * S0: initial state 0 0 0 |
| 58 | * S1: context created 1 0 0 |
| 59 | * S2: context is currently running 2 1 X |
| 60 | * S3: GPU referenced, but not current 2 0 1 |
| 61 | * S4: context is current, but destroyed 1 1 0 |
| 62 | * S5: like S3, but destroyed 1 0 1 |
| 63 | * |
| 64 | * The most common (but not all) transitions: |
| 65 | * S0->S1: client creates a context |
| 66 | * S1->S2: client submits execbuf with context |
| 67 | * S2->S3: other clients submits execbuf with context |
| 68 | * S3->S1: context object was retired |
| 69 | * S3->S2: clients submits another execbuf |
| 70 | * S2->S4: context destroy called with current context |
| 71 | * S3->S5->S0: destroy path |
| 72 | * S4->S5->S0: destroy path on current context |
| 73 | * |
| 74 | * There are two confusing terms used above: |
| 75 | * The "current context" means the context which is currently running on the |
| 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
| 77 | * offset of the BO. The GPU is not actively referencing the data at this |
| 78 | * offset, but it will on the next context switch. The only way to avoid this |
| 79 | * is to do a GPU reset. |
| 80 | * |
| 81 | * An "active context' is one which was previously the "current context" and is |
| 82 | * on the active list waiting for the next context switch to occur. Until this |
| 83 | * happens, the object must remain at the same gtt offset. It is therefore |
| 84 | * possible to destroy a context, but it is still active. |
| 85 | * |
| 86 | */ |
| 87 | |
| 88 | #include <drm/drmP.h> |
| 89 | #include <drm/i915_drm.h> |
| 90 | #include "i915_drv.h" |
| 91 | #include "i915_trace.h" |
| 92 | |
| 93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
| 94 | |
| 95 | /* This is a HW constraint. The value below is the largest known requirement |
| 96 | * I've seen in a spec to date, and that was a workaround for a non-shipping |
| 97 | * part. It should be safe to decrease this, but it's more future proof as is. |
| 98 | */ |
| 99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
| 100 | #define GEN7_CONTEXT_ALIGN 4096 |
| 101 | |
| 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
| 103 | { |
| 104 | if (IS_GEN6(dev_priv)) |
| 105 | return GEN6_CONTEXT_ALIGN; |
| 106 | |
| 107 | return GEN7_CONTEXT_ALIGN; |
| 108 | } |
| 109 | |
| 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
| 111 | { |
| 112 | int ret; |
| 113 | u32 reg; |
| 114 | |
| 115 | switch (INTEL_GEN(dev_priv)) { |
| 116 | case 6: |
| 117 | reg = I915_READ(CXT_SIZE); |
| 118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; |
| 119 | break; |
| 120 | case 7: |
| 121 | reg = I915_READ(GEN7_CXT_SIZE); |
| 122 | if (IS_HASWELL(dev_priv)) |
| 123 | ret = HSW_CXT_TOTAL_SIZE; |
| 124 | else |
| 125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; |
| 126 | break; |
| 127 | case 8: |
| 128 | ret = GEN8_CXT_TOTAL_SIZE; |
| 129 | break; |
| 130 | default: |
| 131 | BUG(); |
| 132 | } |
| 133 | |
| 134 | return ret; |
| 135 | } |
| 136 | |
| 137 | static void i915_gem_context_clean(struct intel_context *ctx) |
| 138 | { |
| 139 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
| 140 | struct i915_vma *vma, *next; |
| 141 | |
| 142 | if (!ppgtt) |
| 143 | return; |
| 144 | |
| 145 | list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, |
| 146 | vm_link) { |
| 147 | if (WARN_ON(__i915_vma_unbind_no_wait(vma))) |
| 148 | break; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | void i915_gem_context_free(struct kref *ctx_ref) |
| 153 | { |
| 154 | struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
| 155 | |
| 156 | trace_i915_context_free(ctx); |
| 157 | |
| 158 | if (i915.enable_execlists) |
| 159 | intel_lr_context_free(ctx); |
| 160 | |
| 161 | /* |
| 162 | * This context is going away and we need to remove all VMAs still |
| 163 | * around. This is to handle imported shared objects for which |
| 164 | * destructor did not run when their handles were closed. |
| 165 | */ |
| 166 | i915_gem_context_clean(ctx); |
| 167 | |
| 168 | i915_ppgtt_put(ctx->ppgtt); |
| 169 | |
| 170 | if (ctx->legacy_hw_ctx.rcs_state) |
| 171 | drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base); |
| 172 | list_del(&ctx->link); |
| 173 | |
| 174 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); |
| 175 | kfree(ctx); |
| 176 | } |
| 177 | |
| 178 | struct drm_i915_gem_object * |
| 179 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
| 180 | { |
| 181 | struct drm_i915_gem_object *obj; |
| 182 | int ret; |
| 183 | |
| 184 | obj = i915_gem_object_create(dev, size); |
| 185 | if (IS_ERR(obj)) |
| 186 | return obj; |
| 187 | |
| 188 | /* |
| 189 | * Try to make the context utilize L3 as well as LLC. |
| 190 | * |
| 191 | * On VLV we don't have L3 controls in the PTEs so we |
| 192 | * shouldn't touch the cache level, especially as that |
| 193 | * would make the object snooped which might have a |
| 194 | * negative performance impact. |
| 195 | * |
| 196 | * Snooping is required on non-llc platforms in execlist |
| 197 | * mode, but since all GGTT accesses use PAT entry 0 we |
| 198 | * get snooping anyway regardless of cache_level. |
| 199 | * |
| 200 | * This is only applicable for Ivy Bridge devices since |
| 201 | * later platforms don't have L3 control bits in the PTE. |
| 202 | */ |
| 203 | if (IS_IVYBRIDGE(dev)) { |
| 204 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
| 205 | /* Failure shouldn't ever happen this early */ |
| 206 | if (WARN_ON(ret)) { |
| 207 | drm_gem_object_unreference(&obj->base); |
| 208 | return ERR_PTR(ret); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | return obj; |
| 213 | } |
| 214 | |
| 215 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
| 216 | { |
| 217 | int ret; |
| 218 | |
| 219 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
| 220 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); |
| 221 | if (ret < 0) { |
| 222 | /* Contexts are only released when no longer active. |
| 223 | * Flush any pending retires to hopefully release some |
| 224 | * stale contexts and try again. |
| 225 | */ |
| 226 | i915_gem_retire_requests(dev_priv); |
| 227 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
| 228 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); |
| 229 | if (ret < 0) |
| 230 | return ret; |
| 231 | } |
| 232 | |
| 233 | *out = ret; |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | static struct intel_context * |
| 238 | __create_hw_context(struct drm_device *dev, |
| 239 | struct drm_i915_file_private *file_priv) |
| 240 | { |
| 241 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 242 | struct intel_context *ctx; |
| 243 | int ret; |
| 244 | |
| 245 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
| 246 | if (ctx == NULL) |
| 247 | return ERR_PTR(-ENOMEM); |
| 248 | |
| 249 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
| 250 | if (ret) { |
| 251 | kfree(ctx); |
| 252 | return ERR_PTR(ret); |
| 253 | } |
| 254 | |
| 255 | kref_init(&ctx->ref); |
| 256 | list_add_tail(&ctx->link, &dev_priv->context_list); |
| 257 | ctx->i915 = dev_priv; |
| 258 | |
| 259 | if (dev_priv->hw_context_size) { |
| 260 | struct drm_i915_gem_object *obj = |
| 261 | i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); |
| 262 | if (IS_ERR(obj)) { |
| 263 | ret = PTR_ERR(obj); |
| 264 | goto err_out; |
| 265 | } |
| 266 | ctx->legacy_hw_ctx.rcs_state = obj; |
| 267 | } |
| 268 | |
| 269 | /* Default context will never have a file_priv */ |
| 270 | if (file_priv != NULL) { |
| 271 | ret = idr_alloc(&file_priv->context_idr, ctx, |
| 272 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
| 273 | if (ret < 0) |
| 274 | goto err_out; |
| 275 | } else |
| 276 | ret = DEFAULT_CONTEXT_HANDLE; |
| 277 | |
| 278 | ctx->file_priv = file_priv; |
| 279 | ctx->user_handle = ret; |
| 280 | /* NB: Mark all slices as needing a remap so that when the context first |
| 281 | * loads it will restore whatever remap state already exists. If there |
| 282 | * is no remap info, it will be a NOP. */ |
| 283 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
| 284 | |
| 285 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
| 286 | |
| 287 | return ctx; |
| 288 | |
| 289 | err_out: |
| 290 | i915_gem_context_unreference(ctx); |
| 291 | return ERR_PTR(ret); |
| 292 | } |
| 293 | |
| 294 | /** |
| 295 | * The default context needs to exist per ring that uses contexts. It stores the |
| 296 | * context state of the GPU for applications that don't utilize HW contexts, as |
| 297 | * well as an idle case. |
| 298 | */ |
| 299 | static struct intel_context * |
| 300 | i915_gem_create_context(struct drm_device *dev, |
| 301 | struct drm_i915_file_private *file_priv) |
| 302 | { |
| 303 | const bool is_global_default_ctx = file_priv == NULL; |
| 304 | struct intel_context *ctx; |
| 305 | int ret = 0; |
| 306 | |
| 307 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 308 | |
| 309 | ctx = __create_hw_context(dev, file_priv); |
| 310 | if (IS_ERR(ctx)) |
| 311 | return ctx; |
| 312 | |
| 313 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) { |
| 314 | /* We may need to do things with the shrinker which |
| 315 | * require us to immediately switch back to the default |
| 316 | * context. This can cause a problem as pinning the |
| 317 | * default context also requires GTT space which may not |
| 318 | * be available. To avoid this we always pin the default |
| 319 | * context. |
| 320 | */ |
| 321 | ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, |
| 322 | get_context_alignment(to_i915(dev)), 0); |
| 323 | if (ret) { |
| 324 | DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); |
| 325 | goto err_destroy; |
| 326 | } |
| 327 | } |
| 328 | |
| 329 | if (USES_FULL_PPGTT(dev)) { |
| 330 | struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv); |
| 331 | |
| 332 | if (IS_ERR_OR_NULL(ppgtt)) { |
| 333 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
| 334 | PTR_ERR(ppgtt)); |
| 335 | ret = PTR_ERR(ppgtt); |
| 336 | goto err_unpin; |
| 337 | } |
| 338 | |
| 339 | ctx->ppgtt = ppgtt; |
| 340 | } |
| 341 | |
| 342 | trace_i915_context_create(ctx); |
| 343 | |
| 344 | return ctx; |
| 345 | |
| 346 | err_unpin: |
| 347 | if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) |
| 348 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
| 349 | err_destroy: |
| 350 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
| 351 | i915_gem_context_unreference(ctx); |
| 352 | return ERR_PTR(ret); |
| 353 | } |
| 354 | |
| 355 | static void i915_gem_context_unpin(struct intel_context *ctx, |
| 356 | struct intel_engine_cs *engine) |
| 357 | { |
| 358 | if (i915.enable_execlists) { |
| 359 | intel_lr_context_unpin(ctx, engine); |
| 360 | } else { |
| 361 | if (engine->id == RCS && ctx->legacy_hw_ctx.rcs_state) |
| 362 | i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); |
| 363 | i915_gem_context_unreference(ctx); |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | void i915_gem_context_reset(struct drm_device *dev) |
| 368 | { |
| 369 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 370 | |
| 371 | if (i915.enable_execlists) { |
| 372 | struct intel_context *ctx; |
| 373 | |
| 374 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
| 375 | intel_lr_context_reset(dev_priv, ctx); |
| 376 | } |
| 377 | |
| 378 | i915_gem_context_lost(dev_priv); |
| 379 | } |
| 380 | |
| 381 | int i915_gem_context_init(struct drm_device *dev) |
| 382 | { |
| 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 384 | struct intel_context *ctx; |
| 385 | |
| 386 | /* Init should only be called once per module load. Eventually the |
| 387 | * restriction on the context_disabled check can be loosened. */ |
| 388 | if (WARN_ON(dev_priv->kernel_context)) |
| 389 | return 0; |
| 390 | |
| 391 | if (intel_vgpu_active(dev_priv) && |
| 392 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { |
| 393 | if (!i915.enable_execlists) { |
| 394 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); |
| 395 | return -EINVAL; |
| 396 | } |
| 397 | } |
| 398 | |
| 399 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
| 400 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); |
| 401 | ida_init(&dev_priv->context_hw_ida); |
| 402 | |
| 403 | if (i915.enable_execlists) { |
| 404 | /* NB: intentionally left blank. We will allocate our own |
| 405 | * backing objects as we need them, thank you very much */ |
| 406 | dev_priv->hw_context_size = 0; |
| 407 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
| 408 | dev_priv->hw_context_size = |
| 409 | round_up(get_context_size(dev_priv), 4096); |
| 410 | if (dev_priv->hw_context_size > (1<<20)) { |
| 411 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", |
| 412 | dev_priv->hw_context_size); |
| 413 | dev_priv->hw_context_size = 0; |
| 414 | } |
| 415 | } |
| 416 | |
| 417 | ctx = i915_gem_create_context(dev, NULL); |
| 418 | if (IS_ERR(ctx)) { |
| 419 | DRM_ERROR("Failed to create default global context (error %ld)\n", |
| 420 | PTR_ERR(ctx)); |
| 421 | return PTR_ERR(ctx); |
| 422 | } |
| 423 | |
| 424 | dev_priv->kernel_context = ctx; |
| 425 | |
| 426 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
| 427 | i915.enable_execlists ? "LR" : |
| 428 | dev_priv->hw_context_size ? "HW" : "fake"); |
| 429 | return 0; |
| 430 | } |
| 431 | |
| 432 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
| 433 | { |
| 434 | struct intel_engine_cs *engine; |
| 435 | |
| 436 | for_each_engine(engine, dev_priv) { |
| 437 | if (engine->last_context == NULL) |
| 438 | continue; |
| 439 | |
| 440 | i915_gem_context_unpin(engine->last_context, engine); |
| 441 | engine->last_context = NULL; |
| 442 | } |
| 443 | |
| 444 | /* Force the GPU state to be reinitialised on enabling */ |
| 445 | dev_priv->kernel_context->legacy_hw_ctx.initialized = false; |
| 446 | dev_priv->kernel_context->remap_slice = ALL_L3_SLICES(dev_priv); |
| 447 | } |
| 448 | |
| 449 | void i915_gem_context_fini(struct drm_device *dev) |
| 450 | { |
| 451 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 452 | struct intel_context *dctx = dev_priv->kernel_context; |
| 453 | |
| 454 | if (dctx->legacy_hw_ctx.rcs_state) |
| 455 | i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); |
| 456 | |
| 457 | i915_gem_context_unreference(dctx); |
| 458 | dev_priv->kernel_context = NULL; |
| 459 | |
| 460 | ida_destroy(&dev_priv->context_hw_ida); |
| 461 | } |
| 462 | |
| 463 | static int context_idr_cleanup(int id, void *p, void *data) |
| 464 | { |
| 465 | struct intel_context *ctx = p; |
| 466 | |
| 467 | i915_gem_context_unreference(ctx); |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
| 472 | { |
| 473 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 474 | struct intel_context *ctx; |
| 475 | |
| 476 | idr_init(&file_priv->context_idr); |
| 477 | |
| 478 | mutex_lock(&dev->struct_mutex); |
| 479 | ctx = i915_gem_create_context(dev, file_priv); |
| 480 | mutex_unlock(&dev->struct_mutex); |
| 481 | |
| 482 | if (IS_ERR(ctx)) { |
| 483 | idr_destroy(&file_priv->context_idr); |
| 484 | return PTR_ERR(ctx); |
| 485 | } |
| 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
| 491 | { |
| 492 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 493 | |
| 494 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
| 495 | idr_destroy(&file_priv->context_idr); |
| 496 | } |
| 497 | |
| 498 | struct intel_context * |
| 499 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) |
| 500 | { |
| 501 | struct intel_context *ctx; |
| 502 | |
| 503 | ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id); |
| 504 | if (!ctx) |
| 505 | return ERR_PTR(-ENOENT); |
| 506 | |
| 507 | return ctx; |
| 508 | } |
| 509 | |
| 510 | static inline int |
| 511 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
| 512 | { |
| 513 | struct drm_i915_private *dev_priv = req->i915; |
| 514 | struct intel_engine_cs *engine = req->engine; |
| 515 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
| 516 | const int num_rings = |
| 517 | /* Use an extended w/a on ivb+ if signalling from other rings */ |
| 518 | i915_semaphore_is_enabled(dev_priv) ? |
| 519 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 : |
| 520 | 0; |
| 521 | int len, ret; |
| 522 | |
| 523 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
| 524 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value |
| 525 | * explicitly, so we rely on the value at ring init, stored in |
| 526 | * itlb_before_ctx_switch. |
| 527 | */ |
| 528 | if (IS_GEN6(dev_priv)) { |
| 529 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0); |
| 530 | if (ret) |
| 531 | return ret; |
| 532 | } |
| 533 | |
| 534 | /* These flags are for resource streamer on HSW+ */ |
| 535 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
| 536 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
| 537 | else if (INTEL_GEN(dev_priv) < 8) |
| 538 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
| 539 | |
| 540 | |
| 541 | len = 4; |
| 542 | if (INTEL_GEN(dev_priv) >= 7) |
| 543 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
| 544 | |
| 545 | ret = intel_ring_begin(req, len); |
| 546 | if (ret) |
| 547 | return ret; |
| 548 | |
| 549 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
| 550 | if (INTEL_GEN(dev_priv) >= 7) { |
| 551 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
| 552 | if (num_rings) { |
| 553 | struct intel_engine_cs *signaller; |
| 554 | |
| 555 | intel_ring_emit(engine, |
| 556 | MI_LOAD_REGISTER_IMM(num_rings)); |
| 557 | for_each_engine(signaller, dev_priv) { |
| 558 | if (signaller == engine) |
| 559 | continue; |
| 560 | |
| 561 | intel_ring_emit_reg(engine, |
| 562 | RING_PSMI_CTL(signaller->mmio_base)); |
| 563 | intel_ring_emit(engine, |
| 564 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
| 565 | } |
| 566 | } |
| 567 | } |
| 568 | |
| 569 | intel_ring_emit(engine, MI_NOOP); |
| 570 | intel_ring_emit(engine, MI_SET_CONTEXT); |
| 571 | intel_ring_emit(engine, |
| 572 | i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) | |
| 573 | flags); |
| 574 | /* |
| 575 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP |
| 576 | * WaMiSetContext_Hang:snb,ivb,vlv |
| 577 | */ |
| 578 | intel_ring_emit(engine, MI_NOOP); |
| 579 | |
| 580 | if (INTEL_GEN(dev_priv) >= 7) { |
| 581 | if (num_rings) { |
| 582 | struct intel_engine_cs *signaller; |
| 583 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
| 584 | |
| 585 | intel_ring_emit(engine, |
| 586 | MI_LOAD_REGISTER_IMM(num_rings)); |
| 587 | for_each_engine(signaller, dev_priv) { |
| 588 | if (signaller == engine) |
| 589 | continue; |
| 590 | |
| 591 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
| 592 | intel_ring_emit_reg(engine, last_reg); |
| 593 | intel_ring_emit(engine, |
| 594 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
| 595 | } |
| 596 | |
| 597 | /* Insert a delay before the next switch! */ |
| 598 | intel_ring_emit(engine, |
| 599 | MI_STORE_REGISTER_MEM | |
| 600 | MI_SRM_LRM_GLOBAL_GTT); |
| 601 | intel_ring_emit_reg(engine, last_reg); |
| 602 | intel_ring_emit(engine, engine->scratch.gtt_offset); |
| 603 | intel_ring_emit(engine, MI_NOOP); |
| 604 | } |
| 605 | intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
| 606 | } |
| 607 | |
| 608 | intel_ring_advance(engine); |
| 609 | |
| 610 | return ret; |
| 611 | } |
| 612 | |
| 613 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
| 614 | { |
| 615 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
| 616 | struct intel_engine_cs *engine = req->engine; |
| 617 | int i, ret; |
| 618 | |
| 619 | if (!remap_info) |
| 620 | return 0; |
| 621 | |
| 622 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
| 623 | if (ret) |
| 624 | return ret; |
| 625 | |
| 626 | /* |
| 627 | * Note: We do not worry about the concurrent register cacheline hang |
| 628 | * here because no other code should access these registers other than |
| 629 | * at initialization time. |
| 630 | */ |
| 631 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
| 632 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { |
| 633 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); |
| 634 | intel_ring_emit(engine, remap_info[i]); |
| 635 | } |
| 636 | intel_ring_emit(engine, MI_NOOP); |
| 637 | intel_ring_advance(engine); |
| 638 | |
| 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
| 643 | struct intel_engine_cs *engine, |
| 644 | struct intel_context *to) |
| 645 | { |
| 646 | if (to->remap_slice) |
| 647 | return false; |
| 648 | |
| 649 | if (!to->legacy_hw_ctx.initialized) |
| 650 | return false; |
| 651 | |
| 652 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
| 653 | return false; |
| 654 | |
| 655 | return to == engine->last_context; |
| 656 | } |
| 657 | |
| 658 | static bool |
| 659 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
| 660 | struct intel_engine_cs *engine, |
| 661 | struct intel_context *to) |
| 662 | { |
| 663 | if (!ppgtt) |
| 664 | return false; |
| 665 | |
| 666 | /* Always load the ppgtt on first use */ |
| 667 | if (!engine->last_context) |
| 668 | return true; |
| 669 | |
| 670 | /* Same context without new entries, skip */ |
| 671 | if (engine->last_context == to && |
| 672 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
| 673 | return false; |
| 674 | |
| 675 | if (engine->id != RCS) |
| 676 | return true; |
| 677 | |
| 678 | if (INTEL_GEN(engine->i915) < 8) |
| 679 | return true; |
| 680 | |
| 681 | return false; |
| 682 | } |
| 683 | |
| 684 | static bool |
| 685 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
| 686 | struct intel_context *to, |
| 687 | u32 hw_flags) |
| 688 | { |
| 689 | if (!ppgtt) |
| 690 | return false; |
| 691 | |
| 692 | if (!IS_GEN8(to->i915)) |
| 693 | return false; |
| 694 | |
| 695 | if (hw_flags & MI_RESTORE_INHIBIT) |
| 696 | return true; |
| 697 | |
| 698 | return false; |
| 699 | } |
| 700 | |
| 701 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
| 702 | { |
| 703 | struct intel_context *to = req->ctx; |
| 704 | struct intel_engine_cs *engine = req->engine; |
| 705 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
| 706 | struct intel_context *from; |
| 707 | u32 hw_flags; |
| 708 | int ret, i; |
| 709 | |
| 710 | if (skip_rcs_switch(ppgtt, engine, to)) |
| 711 | return 0; |
| 712 | |
| 713 | /* Trying to pin first makes error handling easier. */ |
| 714 | ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, |
| 715 | get_context_alignment(engine->i915), |
| 716 | 0); |
| 717 | if (ret) |
| 718 | return ret; |
| 719 | |
| 720 | /* |
| 721 | * Pin can switch back to the default context if we end up calling into |
| 722 | * evict_everything - as a last ditch gtt defrag effort that also |
| 723 | * switches to the default context. Hence we need to reload from here. |
| 724 | * |
| 725 | * XXX: Doing so is painfully broken! |
| 726 | */ |
| 727 | from = engine->last_context; |
| 728 | |
| 729 | /* |
| 730 | * Clear this page out of any CPU caches for coherent swap-in/out. Note |
| 731 | * that thanks to write = false in this call and us not setting any gpu |
| 732 | * write domains when putting a context object onto the active list |
| 733 | * (when switching away from it), this won't block. |
| 734 | * |
| 735 | * XXX: We need a real interface to do this instead of trickery. |
| 736 | */ |
| 737 | ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false); |
| 738 | if (ret) |
| 739 | goto unpin_out; |
| 740 | |
| 741 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
| 742 | /* Older GENs and non render rings still want the load first, |
| 743 | * "PP_DCLV followed by PP_DIR_BASE register through Load |
| 744 | * Register Immediate commands in Ring Buffer before submitting |
| 745 | * a context."*/ |
| 746 | trace_switch_mm(engine, to); |
| 747 | ret = ppgtt->switch_mm(ppgtt, req); |
| 748 | if (ret) |
| 749 | goto unpin_out; |
| 750 | } |
| 751 | |
| 752 | if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) |
| 753 | /* NB: If we inhibit the restore, the context is not allowed to |
| 754 | * die because future work may end up depending on valid address |
| 755 | * space. This means we must enforce that a page table load |
| 756 | * occur when this occurs. */ |
| 757 | hw_flags = MI_RESTORE_INHIBIT; |
| 758 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
| 759 | hw_flags = MI_FORCE_RESTORE; |
| 760 | else |
| 761 | hw_flags = 0; |
| 762 | |
| 763 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
| 764 | ret = mi_set_context(req, hw_flags); |
| 765 | if (ret) |
| 766 | goto unpin_out; |
| 767 | } |
| 768 | |
| 769 | /* The backing object for the context is done after switching to the |
| 770 | * *next* context. Therefore we cannot retire the previous context until |
| 771 | * the next context has already started running. In fact, the below code |
| 772 | * is a bit suboptimal because the retiring can occur simply after the |
| 773 | * MI_SET_CONTEXT instead of when the next seqno has completed. |
| 774 | */ |
| 775 | if (from != NULL) { |
| 776 | from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; |
| 777 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req); |
| 778 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
| 779 | * whole damn pipeline, we don't need to explicitly mark the |
| 780 | * object dirty. The only exception is that the context must be |
| 781 | * correct in case the object gets swapped out. Ideally we'd be |
| 782 | * able to defer doing this until we know the object would be |
| 783 | * swapped, but there is no way to do that yet. |
| 784 | */ |
| 785 | from->legacy_hw_ctx.rcs_state->dirty = 1; |
| 786 | |
| 787 | /* obj is kept alive until the next request by its active ref */ |
| 788 | i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); |
| 789 | i915_gem_context_unreference(from); |
| 790 | } |
| 791 | i915_gem_context_reference(to); |
| 792 | engine->last_context = to; |
| 793 | |
| 794 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
| 795 | * setup, and we do not wish to move them. |
| 796 | */ |
| 797 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
| 798 | trace_switch_mm(engine, to); |
| 799 | ret = ppgtt->switch_mm(ppgtt, req); |
| 800 | /* The hardware context switch is emitted, but we haven't |
| 801 | * actually changed the state - so it's probably safe to bail |
| 802 | * here. Still, let the user know something dangerous has |
| 803 | * happened. |
| 804 | */ |
| 805 | if (ret) |
| 806 | return ret; |
| 807 | } |
| 808 | |
| 809 | if (ppgtt) |
| 810 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
| 811 | |
| 812 | for (i = 0; i < MAX_L3_SLICES; i++) { |
| 813 | if (!(to->remap_slice & (1<<i))) |
| 814 | continue; |
| 815 | |
| 816 | ret = remap_l3(req, i); |
| 817 | if (ret) |
| 818 | return ret; |
| 819 | |
| 820 | to->remap_slice &= ~(1<<i); |
| 821 | } |
| 822 | |
| 823 | if (!to->legacy_hw_ctx.initialized) { |
| 824 | if (engine->init_context) { |
| 825 | ret = engine->init_context(req); |
| 826 | if (ret) |
| 827 | return ret; |
| 828 | } |
| 829 | to->legacy_hw_ctx.initialized = true; |
| 830 | } |
| 831 | |
| 832 | return 0; |
| 833 | |
| 834 | unpin_out: |
| 835 | i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); |
| 836 | return ret; |
| 837 | } |
| 838 | |
| 839 | /** |
| 840 | * i915_switch_context() - perform a GPU context switch. |
| 841 | * @req: request for which we'll execute the context switch |
| 842 | * |
| 843 | * The context life cycle is simple. The context refcount is incremented and |
| 844 | * decremented by 1 and create and destroy. If the context is in use by the GPU, |
| 845 | * it will have a refcount > 1. This allows us to destroy the context abstract |
| 846 | * object while letting the normal object tracking destroy the backing BO. |
| 847 | * |
| 848 | * This function should not be used in execlists mode. Instead the context is |
| 849 | * switched by writing to the ELSP and requests keep a reference to their |
| 850 | * context. |
| 851 | */ |
| 852 | int i915_switch_context(struct drm_i915_gem_request *req) |
| 853 | { |
| 854 | struct intel_engine_cs *engine = req->engine; |
| 855 | struct drm_i915_private *dev_priv = req->i915; |
| 856 | |
| 857 | WARN_ON(i915.enable_execlists); |
| 858 | WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
| 859 | |
| 860 | if (engine->id != RCS || |
| 861 | req->ctx->legacy_hw_ctx.rcs_state == NULL) { |
| 862 | struct intel_context *to = req->ctx; |
| 863 | struct i915_hw_ppgtt *ppgtt = |
| 864 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
| 865 | |
| 866 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
| 867 | int ret; |
| 868 | |
| 869 | trace_switch_mm(engine, to); |
| 870 | ret = ppgtt->switch_mm(ppgtt, req); |
| 871 | if (ret) |
| 872 | return ret; |
| 873 | |
| 874 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
| 875 | } |
| 876 | |
| 877 | if (to != engine->last_context) { |
| 878 | i915_gem_context_reference(to); |
| 879 | if (engine->last_context) |
| 880 | i915_gem_context_unreference(engine->last_context); |
| 881 | engine->last_context = to; |
| 882 | } |
| 883 | |
| 884 | return 0; |
| 885 | } |
| 886 | |
| 887 | return do_rcs_switch(req); |
| 888 | } |
| 889 | |
| 890 | static bool contexts_enabled(struct drm_device *dev) |
| 891 | { |
| 892 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
| 893 | } |
| 894 | |
| 895 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 896 | struct drm_file *file) |
| 897 | { |
| 898 | struct drm_i915_gem_context_create *args = data; |
| 899 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 900 | struct intel_context *ctx; |
| 901 | int ret; |
| 902 | |
| 903 | if (!contexts_enabled(dev)) |
| 904 | return -ENODEV; |
| 905 | |
| 906 | if (args->pad != 0) |
| 907 | return -EINVAL; |
| 908 | |
| 909 | ret = i915_mutex_lock_interruptible(dev); |
| 910 | if (ret) |
| 911 | return ret; |
| 912 | |
| 913 | ctx = i915_gem_create_context(dev, file_priv); |
| 914 | mutex_unlock(&dev->struct_mutex); |
| 915 | if (IS_ERR(ctx)) |
| 916 | return PTR_ERR(ctx); |
| 917 | |
| 918 | args->ctx_id = ctx->user_handle; |
| 919 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
| 920 | |
| 921 | return 0; |
| 922 | } |
| 923 | |
| 924 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 925 | struct drm_file *file) |
| 926 | { |
| 927 | struct drm_i915_gem_context_destroy *args = data; |
| 928 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 929 | struct intel_context *ctx; |
| 930 | int ret; |
| 931 | |
| 932 | if (args->pad != 0) |
| 933 | return -EINVAL; |
| 934 | |
| 935 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
| 936 | return -ENOENT; |
| 937 | |
| 938 | ret = i915_mutex_lock_interruptible(dev); |
| 939 | if (ret) |
| 940 | return ret; |
| 941 | |
| 942 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
| 943 | if (IS_ERR(ctx)) { |
| 944 | mutex_unlock(&dev->struct_mutex); |
| 945 | return PTR_ERR(ctx); |
| 946 | } |
| 947 | |
| 948 | idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); |
| 949 | i915_gem_context_unreference(ctx); |
| 950 | mutex_unlock(&dev->struct_mutex); |
| 951 | |
| 952 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); |
| 953 | return 0; |
| 954 | } |
| 955 | |
| 956 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
| 957 | struct drm_file *file) |
| 958 | { |
| 959 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 960 | struct drm_i915_gem_context_param *args = data; |
| 961 | struct intel_context *ctx; |
| 962 | int ret; |
| 963 | |
| 964 | ret = i915_mutex_lock_interruptible(dev); |
| 965 | if (ret) |
| 966 | return ret; |
| 967 | |
| 968 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
| 969 | if (IS_ERR(ctx)) { |
| 970 | mutex_unlock(&dev->struct_mutex); |
| 971 | return PTR_ERR(ctx); |
| 972 | } |
| 973 | |
| 974 | args->size = 0; |
| 975 | switch (args->param) { |
| 976 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
| 977 | args->value = ctx->hang_stats.ban_period_seconds; |
| 978 | break; |
| 979 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
| 980 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
| 981 | break; |
| 982 | case I915_CONTEXT_PARAM_GTT_SIZE: |
| 983 | if (ctx->ppgtt) |
| 984 | args->value = ctx->ppgtt->base.total; |
| 985 | else if (to_i915(dev)->mm.aliasing_ppgtt) |
| 986 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; |
| 987 | else |
| 988 | args->value = to_i915(dev)->ggtt.base.total; |
| 989 | break; |
| 990 | default: |
| 991 | ret = -EINVAL; |
| 992 | break; |
| 993 | } |
| 994 | mutex_unlock(&dev->struct_mutex); |
| 995 | |
| 996 | return ret; |
| 997 | } |
| 998 | |
| 999 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, |
| 1000 | struct drm_file *file) |
| 1001 | { |
| 1002 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1003 | struct drm_i915_gem_context_param *args = data; |
| 1004 | struct intel_context *ctx; |
| 1005 | int ret; |
| 1006 | |
| 1007 | ret = i915_mutex_lock_interruptible(dev); |
| 1008 | if (ret) |
| 1009 | return ret; |
| 1010 | |
| 1011 | ctx = i915_gem_context_get(file_priv, args->ctx_id); |
| 1012 | if (IS_ERR(ctx)) { |
| 1013 | mutex_unlock(&dev->struct_mutex); |
| 1014 | return PTR_ERR(ctx); |
| 1015 | } |
| 1016 | |
| 1017 | switch (args->param) { |
| 1018 | case I915_CONTEXT_PARAM_BAN_PERIOD: |
| 1019 | if (args->size) |
| 1020 | ret = -EINVAL; |
| 1021 | else if (args->value < ctx->hang_stats.ban_period_seconds && |
| 1022 | !capable(CAP_SYS_ADMIN)) |
| 1023 | ret = -EPERM; |
| 1024 | else |
| 1025 | ctx->hang_stats.ban_period_seconds = args->value; |
| 1026 | break; |
| 1027 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
| 1028 | if (args->size) { |
| 1029 | ret = -EINVAL; |
| 1030 | } else { |
| 1031 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; |
| 1032 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; |
| 1033 | } |
| 1034 | break; |
| 1035 | default: |
| 1036 | ret = -EINVAL; |
| 1037 | break; |
| 1038 | } |
| 1039 | mutex_unlock(&dev->struct_mutex); |
| 1040 | |
| 1041 | return ret; |
| 1042 | } |
| 1043 | |
| 1044 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, |
| 1045 | void *data, struct drm_file *file) |
| 1046 | { |
| 1047 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1048 | struct drm_i915_reset_stats *args = data; |
| 1049 | struct i915_ctx_hang_stats *hs; |
| 1050 | struct intel_context *ctx; |
| 1051 | int ret; |
| 1052 | |
| 1053 | if (args->flags || args->pad) |
| 1054 | return -EINVAL; |
| 1055 | |
| 1056 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
| 1057 | return -EPERM; |
| 1058 | |
| 1059 | ret = i915_mutex_lock_interruptible(dev); |
| 1060 | if (ret) |
| 1061 | return ret; |
| 1062 | |
| 1063 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
| 1064 | if (IS_ERR(ctx)) { |
| 1065 | mutex_unlock(&dev->struct_mutex); |
| 1066 | return PTR_ERR(ctx); |
| 1067 | } |
| 1068 | hs = &ctx->hang_stats; |
| 1069 | |
| 1070 | if (capable(CAP_SYS_ADMIN)) |
| 1071 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 1072 | else |
| 1073 | args->reset_count = 0; |
| 1074 | |
| 1075 | args->batch_active = hs->batch_active; |
| 1076 | args->batch_pending = hs->batch_pending; |
| 1077 | |
| 1078 | mutex_unlock(&dev->struct_mutex); |
| 1079 | |
| 1080 | return 0; |
| 1081 | } |