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drm/i915: disable GT power saving early during system suspend
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_execbuffer.c
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1/*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29#include <drm/drmP.h>
30#include <drm/i915_drm.h>
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/dma_remapping.h>
35
36#define __EXEC_OBJECT_HAS_PIN (1<<31)
37#define __EXEC_OBJECT_HAS_FENCE (1<<30)
38
39struct eb_vmas {
40 struct list_head vmas;
41 int and;
42 union {
43 struct i915_vma *lut[0];
44 struct hlist_head buckets[0];
45 };
46};
47
48static struct eb_vmas *
49eb_create(struct drm_i915_gem_execbuffer2 *args)
50{
51 struct eb_vmas *eb = NULL;
52
53 if (args->flags & I915_EXEC_HANDLE_LUT) {
54 unsigned size = args->buffer_count;
55 size *= sizeof(struct i915_vma *);
56 size += sizeof(struct eb_vmas);
57 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
58 }
59
60 if (eb == NULL) {
61 unsigned size = args->buffer_count;
62 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
63 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
64 while (count > 2*size)
65 count >>= 1;
66 eb = kzalloc(count*sizeof(struct hlist_head) +
67 sizeof(struct eb_vmas),
68 GFP_TEMPORARY);
69 if (eb == NULL)
70 return eb;
71
72 eb->and = count - 1;
73 } else
74 eb->and = -args->buffer_count;
75
76 INIT_LIST_HEAD(&eb->vmas);
77 return eb;
78}
79
80static void
81eb_reset(struct eb_vmas *eb)
82{
83 if (eb->and >= 0)
84 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
85}
86
87static int
88eb_lookup_vmas(struct eb_vmas *eb,
89 struct drm_i915_gem_exec_object2 *exec,
90 const struct drm_i915_gem_execbuffer2 *args,
91 struct i915_address_space *vm,
92 struct drm_file *file)
93{
94 struct drm_i915_private *dev_priv = vm->dev->dev_private;
95 struct drm_i915_gem_object *obj;
96 struct list_head objects;
97 int i, ret;
98
99 INIT_LIST_HEAD(&objects);
100 spin_lock(&file->table_lock);
101 /* Grab a reference to the object and release the lock so we can lookup
102 * or create the VMA without using GFP_ATOMIC */
103 for (i = 0; i < args->buffer_count; i++) {
104 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
105 if (obj == NULL) {
106 spin_unlock(&file->table_lock);
107 DRM_DEBUG("Invalid object handle %d at index %d\n",
108 exec[i].handle, i);
109 ret = -ENOENT;
110 goto err;
111 }
112
113 if (!list_empty(&obj->obj_exec_link)) {
114 spin_unlock(&file->table_lock);
115 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
116 obj, exec[i].handle, i);
117 ret = -EINVAL;
118 goto err;
119 }
120
121 drm_gem_object_reference(&obj->base);
122 list_add_tail(&obj->obj_exec_link, &objects);
123 }
124 spin_unlock(&file->table_lock);
125
126 i = 0;
127 while (!list_empty(&objects)) {
128 struct i915_vma *vma;
129 struct i915_address_space *bind_vm = vm;
130
131 if (exec[i].flags & EXEC_OBJECT_NEEDS_GTT &&
132 USES_FULL_PPGTT(vm->dev)) {
133 ret = -EINVAL;
134 goto err;
135 }
136
137 /* If we have secure dispatch, or the userspace assures us that
138 * they know what they're doing, use the GGTT VM.
139 */
140 if (((args->flags & I915_EXEC_SECURE) &&
141 (i == (args->buffer_count - 1))))
142 bind_vm = &dev_priv->gtt.base;
143
144 obj = list_first_entry(&objects,
145 struct drm_i915_gem_object,
146 obj_exec_link);
147
148 /*
149 * NOTE: We can leak any vmas created here when something fails
150 * later on. But that's no issue since vma_unbind can deal with
151 * vmas which are not actually bound. And since only
152 * lookup_or_create exists as an interface to get at the vma
153 * from the (obj, vm) we don't run the risk of creating
154 * duplicated vmas for the same vm.
155 */
156 vma = i915_gem_obj_lookup_or_create_vma(obj, bind_vm);
157 if (IS_ERR(vma)) {
158 DRM_DEBUG("Failed to lookup VMA\n");
159 ret = PTR_ERR(vma);
160 goto err;
161 }
162
163 /* Transfer ownership from the objects list to the vmas list. */
164 list_add_tail(&vma->exec_list, &eb->vmas);
165 list_del_init(&obj->obj_exec_link);
166
167 vma->exec_entry = &exec[i];
168 if (eb->and < 0) {
169 eb->lut[i] = vma;
170 } else {
171 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
172 vma->exec_handle = handle;
173 hlist_add_head(&vma->exec_node,
174 &eb->buckets[handle & eb->and]);
175 }
176 ++i;
177 }
178
179 return 0;
180
181
182err:
183 while (!list_empty(&objects)) {
184 obj = list_first_entry(&objects,
185 struct drm_i915_gem_object,
186 obj_exec_link);
187 list_del_init(&obj->obj_exec_link);
188 drm_gem_object_unreference(&obj->base);
189 }
190 /*
191 * Objects already transfered to the vmas list will be unreferenced by
192 * eb_destroy.
193 */
194
195 return ret;
196}
197
198static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
199{
200 if (eb->and < 0) {
201 if (handle >= -eb->and)
202 return NULL;
203 return eb->lut[handle];
204 } else {
205 struct hlist_head *head;
206 struct hlist_node *node;
207
208 head = &eb->buckets[handle & eb->and];
209 hlist_for_each(node, head) {
210 struct i915_vma *vma;
211
212 vma = hlist_entry(node, struct i915_vma, exec_node);
213 if (vma->exec_handle == handle)
214 return vma;
215 }
216 return NULL;
217 }
218}
219
220static void
221i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
222{
223 struct drm_i915_gem_exec_object2 *entry;
224 struct drm_i915_gem_object *obj = vma->obj;
225
226 if (!drm_mm_node_allocated(&vma->node))
227 return;
228
229 entry = vma->exec_entry;
230
231 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
232 i915_gem_object_unpin_fence(obj);
233
234 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
235 vma->pin_count--;
236
237 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
238}
239
240static void eb_destroy(struct eb_vmas *eb)
241{
242 while (!list_empty(&eb->vmas)) {
243 struct i915_vma *vma;
244
245 vma = list_first_entry(&eb->vmas,
246 struct i915_vma,
247 exec_list);
248 list_del_init(&vma->exec_list);
249 i915_gem_execbuffer_unreserve_vma(vma);
250 drm_gem_object_unreference(&vma->obj->base);
251 }
252 kfree(eb);
253}
254
255static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
256{
257 return (HAS_LLC(obj->base.dev) ||
258 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
259 !obj->map_and_fenceable ||
260 obj->cache_level != I915_CACHE_NONE);
261}
262
263static int
264relocate_entry_cpu(struct drm_i915_gem_object *obj,
265 struct drm_i915_gem_relocation_entry *reloc,
266 uint64_t target_offset)
267{
268 struct drm_device *dev = obj->base.dev;
269 uint32_t page_offset = offset_in_page(reloc->offset);
270 uint64_t delta = reloc->delta + target_offset;
271 char *vaddr;
272 int ret;
273
274 ret = i915_gem_object_set_to_cpu_domain(obj, true);
275 if (ret)
276 return ret;
277
278 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
279 reloc->offset >> PAGE_SHIFT));
280 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
281
282 if (INTEL_INFO(dev)->gen >= 8) {
283 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
284
285 if (page_offset == 0) {
286 kunmap_atomic(vaddr);
287 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
288 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
289 }
290
291 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
292 }
293
294 kunmap_atomic(vaddr);
295
296 return 0;
297}
298
299static int
300relocate_entry_gtt(struct drm_i915_gem_object *obj,
301 struct drm_i915_gem_relocation_entry *reloc,
302 uint64_t target_offset)
303{
304 struct drm_device *dev = obj->base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 uint64_t delta = reloc->delta + target_offset;
307 uint32_t __iomem *reloc_entry;
308 void __iomem *reloc_page;
309 int ret;
310
311 ret = i915_gem_object_set_to_gtt_domain(obj, true);
312 if (ret)
313 return ret;
314
315 ret = i915_gem_object_put_fence(obj);
316 if (ret)
317 return ret;
318
319 /* Map the page containing the relocation we're going to perform. */
320 reloc->offset += i915_gem_obj_ggtt_offset(obj);
321 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
322 reloc->offset & PAGE_MASK);
323 reloc_entry = (uint32_t __iomem *)
324 (reloc_page + offset_in_page(reloc->offset));
325 iowrite32(lower_32_bits(delta), reloc_entry);
326
327 if (INTEL_INFO(dev)->gen >= 8) {
328 reloc_entry += 1;
329
330 if (offset_in_page(reloc->offset + sizeof(uint32_t)) == 0) {
331 io_mapping_unmap_atomic(reloc_page);
332 reloc_page = io_mapping_map_atomic_wc(
333 dev_priv->gtt.mappable,
334 reloc->offset + sizeof(uint32_t));
335 reloc_entry = reloc_page;
336 }
337
338 iowrite32(upper_32_bits(delta), reloc_entry);
339 }
340
341 io_mapping_unmap_atomic(reloc_page);
342
343 return 0;
344}
345
346static int
347i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
348 struct eb_vmas *eb,
349 struct drm_i915_gem_relocation_entry *reloc)
350{
351 struct drm_device *dev = obj->base.dev;
352 struct drm_gem_object *target_obj;
353 struct drm_i915_gem_object *target_i915_obj;
354 struct i915_vma *target_vma;
355 uint64_t target_offset;
356 int ret;
357
358 /* we've already hold a reference to all valid objects */
359 target_vma = eb_get_vma(eb, reloc->target_handle);
360 if (unlikely(target_vma == NULL))
361 return -ENOENT;
362 target_i915_obj = target_vma->obj;
363 target_obj = &target_vma->obj->base;
364
365 target_offset = target_vma->node.start;
366
367 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
368 * pipe_control writes because the gpu doesn't properly redirect them
369 * through the ppgtt for non_secure batchbuffers. */
370 if (unlikely(IS_GEN6(dev) &&
371 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
372 !target_i915_obj->has_global_gtt_mapping)) {
373 struct i915_vma *vma =
374 list_first_entry(&target_i915_obj->vma_list,
375 typeof(*vma), vma_link);
376 vma->bind_vma(vma, target_i915_obj->cache_level, GLOBAL_BIND);
377 }
378
379 /* Validate that the target is in a valid r/w GPU domain */
380 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
381 DRM_DEBUG("reloc with multiple write domains: "
382 "obj %p target %d offset %d "
383 "read %08x write %08x",
384 obj, reloc->target_handle,
385 (int) reloc->offset,
386 reloc->read_domains,
387 reloc->write_domain);
388 return -EINVAL;
389 }
390 if (unlikely((reloc->write_domain | reloc->read_domains)
391 & ~I915_GEM_GPU_DOMAINS)) {
392 DRM_DEBUG("reloc with read/write non-GPU domains: "
393 "obj %p target %d offset %d "
394 "read %08x write %08x",
395 obj, reloc->target_handle,
396 (int) reloc->offset,
397 reloc->read_domains,
398 reloc->write_domain);
399 return -EINVAL;
400 }
401
402 target_obj->pending_read_domains |= reloc->read_domains;
403 target_obj->pending_write_domain |= reloc->write_domain;
404
405 /* If the relocation already has the right value in it, no
406 * more work needs to be done.
407 */
408 if (target_offset == reloc->presumed_offset)
409 return 0;
410
411 /* Check that the relocation address is valid... */
412 if (unlikely(reloc->offset >
413 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
414 DRM_DEBUG("Relocation beyond object bounds: "
415 "obj %p target %d offset %d size %d.\n",
416 obj, reloc->target_handle,
417 (int) reloc->offset,
418 (int) obj->base.size);
419 return -EINVAL;
420 }
421 if (unlikely(reloc->offset & 3)) {
422 DRM_DEBUG("Relocation not 4-byte aligned: "
423 "obj %p target %d offset %d.\n",
424 obj, reloc->target_handle,
425 (int) reloc->offset);
426 return -EINVAL;
427 }
428
429 /* We can't wait for rendering with pagefaults disabled */
430 if (obj->active && in_atomic())
431 return -EFAULT;
432
433 if (use_cpu_reloc(obj))
434 ret = relocate_entry_cpu(obj, reloc, target_offset);
435 else
436 ret = relocate_entry_gtt(obj, reloc, target_offset);
437
438 if (ret)
439 return ret;
440
441 /* and update the user's relocation entry */
442 reloc->presumed_offset = target_offset;
443
444 return 0;
445}
446
447static int
448i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
449 struct eb_vmas *eb)
450{
451#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
452 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
453 struct drm_i915_gem_relocation_entry __user *user_relocs;
454 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
455 int remain, ret;
456
457 user_relocs = to_user_ptr(entry->relocs_ptr);
458
459 remain = entry->relocation_count;
460 while (remain) {
461 struct drm_i915_gem_relocation_entry *r = stack_reloc;
462 int count = remain;
463 if (count > ARRAY_SIZE(stack_reloc))
464 count = ARRAY_SIZE(stack_reloc);
465 remain -= count;
466
467 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
468 return -EFAULT;
469
470 do {
471 u64 offset = r->presumed_offset;
472
473 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
474 if (ret)
475 return ret;
476
477 if (r->presumed_offset != offset &&
478 __copy_to_user_inatomic(&user_relocs->presumed_offset,
479 &r->presumed_offset,
480 sizeof(r->presumed_offset))) {
481 return -EFAULT;
482 }
483
484 user_relocs++;
485 r++;
486 } while (--count);
487 }
488
489 return 0;
490#undef N_RELOC
491}
492
493static int
494i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
495 struct eb_vmas *eb,
496 struct drm_i915_gem_relocation_entry *relocs)
497{
498 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
499 int i, ret;
500
501 for (i = 0; i < entry->relocation_count; i++) {
502 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
503 if (ret)
504 return ret;
505 }
506
507 return 0;
508}
509
510static int
511i915_gem_execbuffer_relocate(struct eb_vmas *eb)
512{
513 struct i915_vma *vma;
514 int ret = 0;
515
516 /* This is the fast path and we cannot handle a pagefault whilst
517 * holding the struct mutex lest the user pass in the relocations
518 * contained within a mmaped bo. For in such a case we, the page
519 * fault handler would call i915_gem_fault() and we would try to
520 * acquire the struct mutex again. Obviously this is bad and so
521 * lockdep complains vehemently.
522 */
523 pagefault_disable();
524 list_for_each_entry(vma, &eb->vmas, exec_list) {
525 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
526 if (ret)
527 break;
528 }
529 pagefault_enable();
530
531 return ret;
532}
533
534static int
535need_reloc_mappable(struct i915_vma *vma)
536{
537 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
538 return entry->relocation_count && !use_cpu_reloc(vma->obj) &&
539 i915_is_ggtt(vma->vm);
540}
541
542static int
543i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
544 struct intel_ring_buffer *ring,
545 bool *need_reloc)
546{
547 struct drm_i915_gem_object *obj = vma->obj;
548 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
549 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
550 bool need_fence;
551 unsigned flags;
552 int ret;
553
554 flags = 0;
555
556 need_fence =
557 has_fenced_gpu_access &&
558 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
559 obj->tiling_mode != I915_TILING_NONE;
560 if (need_fence || need_reloc_mappable(vma))
561 flags |= PIN_MAPPABLE;
562
563 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
564 flags |= PIN_GLOBAL;
565
566 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
567 if (ret)
568 return ret;
569
570 entry->flags |= __EXEC_OBJECT_HAS_PIN;
571
572 if (has_fenced_gpu_access) {
573 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
574 ret = i915_gem_object_get_fence(obj);
575 if (ret)
576 return ret;
577
578 if (i915_gem_object_pin_fence(obj))
579 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
580
581 obj->pending_fenced_gpu_access = true;
582 }
583 }
584
585 if (entry->offset != vma->node.start) {
586 entry->offset = vma->node.start;
587 *need_reloc = true;
588 }
589
590 if (entry->flags & EXEC_OBJECT_WRITE) {
591 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
592 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
593 }
594
595 return 0;
596}
597
598static int
599i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
600 struct list_head *vmas,
601 bool *need_relocs)
602{
603 struct drm_i915_gem_object *obj;
604 struct i915_vma *vma;
605 struct i915_address_space *vm;
606 struct list_head ordered_vmas;
607 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
608 int retry;
609
610 if (list_empty(vmas))
611 return 0;
612
613 i915_gem_retire_requests_ring(ring);
614
615 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
616
617 INIT_LIST_HEAD(&ordered_vmas);
618 while (!list_empty(vmas)) {
619 struct drm_i915_gem_exec_object2 *entry;
620 bool need_fence, need_mappable;
621
622 vma = list_first_entry(vmas, struct i915_vma, exec_list);
623 obj = vma->obj;
624 entry = vma->exec_entry;
625
626 need_fence =
627 has_fenced_gpu_access &&
628 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
629 obj->tiling_mode != I915_TILING_NONE;
630 need_mappable = need_fence || need_reloc_mappable(vma);
631
632 if (need_mappable)
633 list_move(&vma->exec_list, &ordered_vmas);
634 else
635 list_move_tail(&vma->exec_list, &ordered_vmas);
636
637 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
638 obj->base.pending_write_domain = 0;
639 obj->pending_fenced_gpu_access = false;
640 }
641 list_splice(&ordered_vmas, vmas);
642
643 /* Attempt to pin all of the buffers into the GTT.
644 * This is done in 3 phases:
645 *
646 * 1a. Unbind all objects that do not match the GTT constraints for
647 * the execbuffer (fenceable, mappable, alignment etc).
648 * 1b. Increment pin count for already bound objects.
649 * 2. Bind new objects.
650 * 3. Decrement pin count.
651 *
652 * This avoid unnecessary unbinding of later objects in order to make
653 * room for the earlier objects *unless* we need to defragment.
654 */
655 retry = 0;
656 do {
657 int ret = 0;
658
659 /* Unbind any ill-fitting objects or pin. */
660 list_for_each_entry(vma, vmas, exec_list) {
661 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
662 bool need_fence, need_mappable;
663
664 obj = vma->obj;
665
666 if (!drm_mm_node_allocated(&vma->node))
667 continue;
668
669 need_fence =
670 has_fenced_gpu_access &&
671 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
672 obj->tiling_mode != I915_TILING_NONE;
673 need_mappable = need_fence || need_reloc_mappable(vma);
674
675 WARN_ON((need_mappable || need_fence) &&
676 !i915_is_ggtt(vma->vm));
677
678 if ((entry->alignment &&
679 vma->node.start & (entry->alignment - 1)) ||
680 (need_mappable && !obj->map_and_fenceable))
681 ret = i915_vma_unbind(vma);
682 else
683 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
684 if (ret)
685 goto err;
686 }
687
688 /* Bind fresh objects */
689 list_for_each_entry(vma, vmas, exec_list) {
690 if (drm_mm_node_allocated(&vma->node))
691 continue;
692
693 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
694 if (ret)
695 goto err;
696 }
697
698err:
699 if (ret != -ENOSPC || retry++)
700 return ret;
701
702 /* Decrement pin count for bound objects */
703 list_for_each_entry(vma, vmas, exec_list)
704 i915_gem_execbuffer_unreserve_vma(vma);
705
706 ret = i915_gem_evict_vm(vm, true);
707 if (ret)
708 return ret;
709 } while (1);
710}
711
712static int
713i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
714 struct drm_i915_gem_execbuffer2 *args,
715 struct drm_file *file,
716 struct intel_ring_buffer *ring,
717 struct eb_vmas *eb,
718 struct drm_i915_gem_exec_object2 *exec)
719{
720 struct drm_i915_gem_relocation_entry *reloc;
721 struct i915_address_space *vm;
722 struct i915_vma *vma;
723 bool need_relocs;
724 int *reloc_offset;
725 int i, total, ret;
726 unsigned count = args->buffer_count;
727
728 if (WARN_ON(list_empty(&eb->vmas)))
729 return 0;
730
731 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
732
733 /* We may process another execbuffer during the unlock... */
734 while (!list_empty(&eb->vmas)) {
735 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
736 list_del_init(&vma->exec_list);
737 i915_gem_execbuffer_unreserve_vma(vma);
738 drm_gem_object_unreference(&vma->obj->base);
739 }
740
741 mutex_unlock(&dev->struct_mutex);
742
743 total = 0;
744 for (i = 0; i < count; i++)
745 total += exec[i].relocation_count;
746
747 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
748 reloc = drm_malloc_ab(total, sizeof(*reloc));
749 if (reloc == NULL || reloc_offset == NULL) {
750 drm_free_large(reloc);
751 drm_free_large(reloc_offset);
752 mutex_lock(&dev->struct_mutex);
753 return -ENOMEM;
754 }
755
756 total = 0;
757 for (i = 0; i < count; i++) {
758 struct drm_i915_gem_relocation_entry __user *user_relocs;
759 u64 invalid_offset = (u64)-1;
760 int j;
761
762 user_relocs = to_user_ptr(exec[i].relocs_ptr);
763
764 if (copy_from_user(reloc+total, user_relocs,
765 exec[i].relocation_count * sizeof(*reloc))) {
766 ret = -EFAULT;
767 mutex_lock(&dev->struct_mutex);
768 goto err;
769 }
770
771 /* As we do not update the known relocation offsets after
772 * relocating (due to the complexities in lock handling),
773 * we need to mark them as invalid now so that we force the
774 * relocation processing next time. Just in case the target
775 * object is evicted and then rebound into its old
776 * presumed_offset before the next execbuffer - if that
777 * happened we would make the mistake of assuming that the
778 * relocations were valid.
779 */
780 for (j = 0; j < exec[i].relocation_count; j++) {
781 if (copy_to_user(&user_relocs[j].presumed_offset,
782 &invalid_offset,
783 sizeof(invalid_offset))) {
784 ret = -EFAULT;
785 mutex_lock(&dev->struct_mutex);
786 goto err;
787 }
788 }
789
790 reloc_offset[i] = total;
791 total += exec[i].relocation_count;
792 }
793
794 ret = i915_mutex_lock_interruptible(dev);
795 if (ret) {
796 mutex_lock(&dev->struct_mutex);
797 goto err;
798 }
799
800 /* reacquire the objects */
801 eb_reset(eb);
802 ret = eb_lookup_vmas(eb, exec, args, vm, file);
803 if (ret)
804 goto err;
805
806 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
807 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
808 if (ret)
809 goto err;
810
811 list_for_each_entry(vma, &eb->vmas, exec_list) {
812 int offset = vma->exec_entry - exec;
813 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
814 reloc + reloc_offset[offset]);
815 if (ret)
816 goto err;
817 }
818
819 /* Leave the user relocations as are, this is the painfully slow path,
820 * and we want to avoid the complication of dropping the lock whilst
821 * having buffers reserved in the aperture and so causing spurious
822 * ENOSPC for random operations.
823 */
824
825err:
826 drm_free_large(reloc);
827 drm_free_large(reloc_offset);
828 return ret;
829}
830
831static int
832i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
833 struct list_head *vmas)
834{
835 struct i915_vma *vma;
836 uint32_t flush_domains = 0;
837 bool flush_chipset = false;
838 int ret;
839
840 list_for_each_entry(vma, vmas, exec_list) {
841 struct drm_i915_gem_object *obj = vma->obj;
842 ret = i915_gem_object_sync(obj, ring);
843 if (ret)
844 return ret;
845
846 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
847 flush_chipset |= i915_gem_clflush_object(obj, false);
848
849 flush_domains |= obj->base.write_domain;
850 }
851
852 if (flush_chipset)
853 i915_gem_chipset_flush(ring->dev);
854
855 if (flush_domains & I915_GEM_DOMAIN_GTT)
856 wmb();
857
858 /* Unconditionally invalidate gpu caches and ensure that we do flush
859 * any residual writes from the previous batch.
860 */
861 return intel_ring_invalidate_all_caches(ring);
862}
863
864static bool
865i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
866{
867 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
868 return false;
869
870 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
871}
872
873static int
874validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
875 int count)
876{
877 int i;
878 unsigned relocs_total = 0;
879 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
880
881 for (i = 0; i < count; i++) {
882 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
883 int length; /* limited by fault_in_pages_readable() */
884
885 if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
886 return -EINVAL;
887
888 /* First check for malicious input causing overflow in
889 * the worst case where we need to allocate the entire
890 * relocation tree as a single array.
891 */
892 if (exec[i].relocation_count > relocs_max - relocs_total)
893 return -EINVAL;
894 relocs_total += exec[i].relocation_count;
895
896 length = exec[i].relocation_count *
897 sizeof(struct drm_i915_gem_relocation_entry);
898 /*
899 * We must check that the entire relocation array is safe
900 * to read, but since we may need to update the presumed
901 * offsets during execution, check for full write access.
902 */
903 if (!access_ok(VERIFY_WRITE, ptr, length))
904 return -EFAULT;
905
906 if (likely(!i915.prefault_disable)) {
907 if (fault_in_multipages_readable(ptr, length))
908 return -EFAULT;
909 }
910 }
911
912 return 0;
913}
914
915static struct i915_hw_context *
916i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
917 struct intel_ring_buffer *ring, const u32 ctx_id)
918{
919 struct i915_hw_context *ctx = NULL;
920 struct i915_ctx_hang_stats *hs;
921
922 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_ID)
923 return ERR_PTR(-EINVAL);
924
925 ctx = i915_gem_context_get(file->driver_priv, ctx_id);
926 if (IS_ERR(ctx))
927 return ctx;
928
929 hs = &ctx->hang_stats;
930 if (hs->banned) {
931 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
932 return ERR_PTR(-EIO);
933 }
934
935 return ctx;
936}
937
938static void
939i915_gem_execbuffer_move_to_active(struct list_head *vmas,
940 struct intel_ring_buffer *ring)
941{
942 struct i915_vma *vma;
943
944 list_for_each_entry(vma, vmas, exec_list) {
945 struct drm_i915_gem_object *obj = vma->obj;
946 u32 old_read = obj->base.read_domains;
947 u32 old_write = obj->base.write_domain;
948
949 obj->base.write_domain = obj->base.pending_write_domain;
950 if (obj->base.write_domain == 0)
951 obj->base.pending_read_domains |= obj->base.read_domains;
952 obj->base.read_domains = obj->base.pending_read_domains;
953 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
954
955 i915_vma_move_to_active(vma, ring);
956 if (obj->base.write_domain) {
957 obj->dirty = 1;
958 obj->last_write_seqno = intel_ring_get_seqno(ring);
959 /* check for potential scanout */
960 if (i915_gem_obj_ggtt_bound(obj) &&
961 i915_gem_obj_to_ggtt(obj)->pin_count)
962 intel_mark_fb_busy(obj, ring);
963
964 /* update for the implicit flush after a batch */
965 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
966 }
967
968 trace_i915_gem_object_change_domain(obj, old_read, old_write);
969 }
970}
971
972static void
973i915_gem_execbuffer_retire_commands(struct drm_device *dev,
974 struct drm_file *file,
975 struct intel_ring_buffer *ring,
976 struct drm_i915_gem_object *obj)
977{
978 /* Unconditionally force add_request to emit a full flush. */
979 ring->gpu_caches_dirty = true;
980
981 /* Add a breadcrumb for the completion of the batch buffer */
982 (void)__i915_add_request(ring, file, obj, NULL);
983}
984
985static int
986i915_reset_gen7_sol_offsets(struct drm_device *dev,
987 struct intel_ring_buffer *ring)
988{
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 int ret, i;
991
992 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
993 DRM_DEBUG("sol reset is gen7/rcs only\n");
994 return -EINVAL;
995 }
996
997 ret = intel_ring_begin(ring, 4 * 3);
998 if (ret)
999 return ret;
1000
1001 for (i = 0; i < 4; i++) {
1002 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1003 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1004 intel_ring_emit(ring, 0);
1005 }
1006
1007 intel_ring_advance(ring);
1008
1009 return 0;
1010}
1011
1012/**
1013 * Find one BSD ring to dispatch the corresponding BSD command.
1014 * The Ring ID is returned.
1015 */
1016static int gen8_dispatch_bsd_ring(struct drm_device *dev,
1017 struct drm_file *file)
1018{
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020 struct drm_i915_file_private *file_priv = file->driver_priv;
1021
1022 /* Check whether the file_priv is using one ring */
1023 if (file_priv->bsd_ring)
1024 return file_priv->bsd_ring->id;
1025 else {
1026 /* If no, use the ping-pong mechanism to select one ring */
1027 int ring_id;
1028
1029 mutex_lock(&dev->struct_mutex);
1030 if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
1031 ring_id = VCS;
1032 dev_priv->mm.bsd_ring_dispatch_index = 1;
1033 } else {
1034 ring_id = VCS2;
1035 dev_priv->mm.bsd_ring_dispatch_index = 0;
1036 }
1037 file_priv->bsd_ring = &dev_priv->ring[ring_id];
1038 mutex_unlock(&dev->struct_mutex);
1039 return ring_id;
1040 }
1041}
1042
1043static int
1044i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1045 struct drm_file *file,
1046 struct drm_i915_gem_execbuffer2 *args,
1047 struct drm_i915_gem_exec_object2 *exec)
1048{
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 struct eb_vmas *eb;
1051 struct drm_i915_gem_object *batch_obj;
1052 struct drm_clip_rect *cliprects = NULL;
1053 struct intel_ring_buffer *ring;
1054 struct i915_hw_context *ctx;
1055 struct i915_address_space *vm;
1056 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1057 u64 exec_start = args->batch_start_offset, exec_len;
1058 u32 mask, flags;
1059 int ret, mode, i;
1060 bool need_relocs;
1061
1062 if (!i915_gem_check_execbuffer(args))
1063 return -EINVAL;
1064
1065 ret = validate_exec_list(exec, args->buffer_count);
1066 if (ret)
1067 return ret;
1068
1069 flags = 0;
1070 if (args->flags & I915_EXEC_SECURE) {
1071 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1072 return -EPERM;
1073
1074 flags |= I915_DISPATCH_SECURE;
1075 }
1076 if (args->flags & I915_EXEC_IS_PINNED)
1077 flags |= I915_DISPATCH_PINNED;
1078
1079 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
1080 DRM_DEBUG("execbuf with unknown ring: %d\n",
1081 (int)(args->flags & I915_EXEC_RING_MASK));
1082 return -EINVAL;
1083 }
1084
1085 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1086 ring = &dev_priv->ring[RCS];
1087 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1088 if (HAS_BSD2(dev)) {
1089 int ring_id;
1090 ring_id = gen8_dispatch_bsd_ring(dev, file);
1091 ring = &dev_priv->ring[ring_id];
1092 } else
1093 ring = &dev_priv->ring[VCS];
1094 } else
1095 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
1096
1097 if (!intel_ring_initialized(ring)) {
1098 DRM_DEBUG("execbuf with invalid ring: %d\n",
1099 (int)(args->flags & I915_EXEC_RING_MASK));
1100 return -EINVAL;
1101 }
1102
1103 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1104 mask = I915_EXEC_CONSTANTS_MASK;
1105 switch (mode) {
1106 case I915_EXEC_CONSTANTS_REL_GENERAL:
1107 case I915_EXEC_CONSTANTS_ABSOLUTE:
1108 case I915_EXEC_CONSTANTS_REL_SURFACE:
1109 if (mode != 0 && ring != &dev_priv->ring[RCS]) {
1110 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1111 return -EINVAL;
1112 }
1113
1114 if (mode != dev_priv->relative_constants_mode) {
1115 if (INTEL_INFO(dev)->gen < 4) {
1116 DRM_DEBUG("no rel constants on pre-gen4\n");
1117 return -EINVAL;
1118 }
1119
1120 if (INTEL_INFO(dev)->gen > 5 &&
1121 mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1122 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1123 return -EINVAL;
1124 }
1125
1126 /* The HW changed the meaning on this bit on gen6 */
1127 if (INTEL_INFO(dev)->gen >= 6)
1128 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1129 }
1130 break;
1131 default:
1132 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1133 return -EINVAL;
1134 }
1135
1136 if (args->buffer_count < 1) {
1137 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1138 return -EINVAL;
1139 }
1140
1141 if (args->num_cliprects != 0) {
1142 if (ring != &dev_priv->ring[RCS]) {
1143 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1144 return -EINVAL;
1145 }
1146
1147 if (INTEL_INFO(dev)->gen >= 5) {
1148 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1149 return -EINVAL;
1150 }
1151
1152 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1153 DRM_DEBUG("execbuf with %u cliprects\n",
1154 args->num_cliprects);
1155 return -EINVAL;
1156 }
1157
1158 cliprects = kcalloc(args->num_cliprects,
1159 sizeof(*cliprects),
1160 GFP_KERNEL);
1161 if (cliprects == NULL) {
1162 ret = -ENOMEM;
1163 goto pre_mutex_err;
1164 }
1165
1166 if (copy_from_user(cliprects,
1167 to_user_ptr(args->cliprects_ptr),
1168 sizeof(*cliprects)*args->num_cliprects)) {
1169 ret = -EFAULT;
1170 goto pre_mutex_err;
1171 }
1172 } else {
1173 if (args->DR4 == 0xffffffff) {
1174 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1175 args->DR4 = 0;
1176 }
1177
1178 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
1179 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
1180 return -EINVAL;
1181 }
1182 }
1183
1184 intel_runtime_pm_get(dev_priv);
1185
1186 ret = i915_mutex_lock_interruptible(dev);
1187 if (ret)
1188 goto pre_mutex_err;
1189
1190 if (dev_priv->ums.mm_suspended) {
1191 mutex_unlock(&dev->struct_mutex);
1192 ret = -EBUSY;
1193 goto pre_mutex_err;
1194 }
1195
1196 ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
1197 if (IS_ERR(ctx)) {
1198 mutex_unlock(&dev->struct_mutex);
1199 ret = PTR_ERR(ctx);
1200 goto pre_mutex_err;
1201 }
1202
1203 i915_gem_context_reference(ctx);
1204
1205 vm = ctx->vm;
1206 if (!USES_FULL_PPGTT(dev))
1207 vm = &dev_priv->gtt.base;
1208
1209 eb = eb_create(args);
1210 if (eb == NULL) {
1211 i915_gem_context_unreference(ctx);
1212 mutex_unlock(&dev->struct_mutex);
1213 ret = -ENOMEM;
1214 goto pre_mutex_err;
1215 }
1216
1217 /* Look up object handles */
1218 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1219 if (ret)
1220 goto err;
1221
1222 /* take note of the batch buffer before we might reorder the lists */
1223 batch_obj = list_entry(eb->vmas.prev, struct i915_vma, exec_list)->obj;
1224
1225 /* Move the objects en-masse into the GTT, evicting if necessary. */
1226 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1227 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);
1228 if (ret)
1229 goto err;
1230
1231 /* The objects are in their final locations, apply the relocations. */
1232 if (need_relocs)
1233 ret = i915_gem_execbuffer_relocate(eb);
1234 if (ret) {
1235 if (ret == -EFAULT) {
1236 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
1237 eb, exec);
1238 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1239 }
1240 if (ret)
1241 goto err;
1242 }
1243
1244 /* Set the pending read domains for the batch buffer to COMMAND */
1245 if (batch_obj->base.pending_write_domain) {
1246 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1247 ret = -EINVAL;
1248 goto err;
1249 }
1250 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1251
1252 if (i915_needs_cmd_parser(ring)) {
1253 ret = i915_parse_cmds(ring,
1254 batch_obj,
1255 args->batch_start_offset,
1256 file->is_master);
1257 if (ret)
1258 goto err;
1259
1260 /*
1261 * XXX: Actually do this when enabling batch copy...
1262 *
1263 * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit
1264 * from MI_BATCH_BUFFER_START commands issued in the
1265 * dispatch_execbuffer implementations. We specifically don't
1266 * want that set when the command parser is enabled.
1267 */
1268 }
1269
1270 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1271 * batch" bit. Hence we need to pin secure batches into the global gtt.
1272 * hsw should have this fixed, but bdw mucks it up again. */
1273 if (flags & I915_DISPATCH_SECURE &&
1274 !batch_obj->has_global_gtt_mapping) {
1275 /* When we have multiple VMs, we'll need to make sure that we
1276 * allocate space first */
1277 struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj);
1278 BUG_ON(!vma);
1279 vma->bind_vma(vma, batch_obj->cache_level, GLOBAL_BIND);
1280 }
1281
1282 if (flags & I915_DISPATCH_SECURE)
1283 exec_start += i915_gem_obj_ggtt_offset(batch_obj);
1284 else
1285 exec_start += i915_gem_obj_offset(batch_obj, vm);
1286
1287 ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas);
1288 if (ret)
1289 goto err;
1290
1291 ret = i915_switch_context(ring, ctx);
1292 if (ret)
1293 goto err;
1294
1295 if (ring == &dev_priv->ring[RCS] &&
1296 mode != dev_priv->relative_constants_mode) {
1297 ret = intel_ring_begin(ring, 4);
1298 if (ret)
1299 goto err;
1300
1301 intel_ring_emit(ring, MI_NOOP);
1302 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1303 intel_ring_emit(ring, INSTPM);
1304 intel_ring_emit(ring, mask << 16 | mode);
1305 intel_ring_advance(ring);
1306
1307 dev_priv->relative_constants_mode = mode;
1308 }
1309
1310 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1311 ret = i915_reset_gen7_sol_offsets(dev, ring);
1312 if (ret)
1313 goto err;
1314 }
1315
1316
1317 exec_len = args->batch_len;
1318 if (cliprects) {
1319 for (i = 0; i < args->num_cliprects; i++) {
1320 ret = i915_emit_box(dev, &cliprects[i],
1321 args->DR1, args->DR4);
1322 if (ret)
1323 goto err;
1324
1325 ret = ring->dispatch_execbuffer(ring,
1326 exec_start, exec_len,
1327 flags);
1328 if (ret)
1329 goto err;
1330 }
1331 } else {
1332 ret = ring->dispatch_execbuffer(ring,
1333 exec_start, exec_len,
1334 flags);
1335 if (ret)
1336 goto err;
1337 }
1338
1339 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1340
1341 i915_gem_execbuffer_move_to_active(&eb->vmas, ring);
1342 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1343
1344err:
1345 /* the request owns the ref now */
1346 i915_gem_context_unreference(ctx);
1347 eb_destroy(eb);
1348
1349 mutex_unlock(&dev->struct_mutex);
1350
1351pre_mutex_err:
1352 kfree(cliprects);
1353
1354 /* intel_gpu_busy should also get a ref, so it will free when the device
1355 * is really idle. */
1356 intel_runtime_pm_put(dev_priv);
1357 return ret;
1358}
1359
1360/*
1361 * Legacy execbuffer just creates an exec2 list from the original exec object
1362 * list array and passes it to the real function.
1363 */
1364int
1365i915_gem_execbuffer(struct drm_device *dev, void *data,
1366 struct drm_file *file)
1367{
1368 struct drm_i915_gem_execbuffer *args = data;
1369 struct drm_i915_gem_execbuffer2 exec2;
1370 struct drm_i915_gem_exec_object *exec_list = NULL;
1371 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1372 int ret, i;
1373
1374 if (args->buffer_count < 1) {
1375 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1376 return -EINVAL;
1377 }
1378
1379 /* Copy in the exec list from userland */
1380 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1381 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1382 if (exec_list == NULL || exec2_list == NULL) {
1383 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1384 args->buffer_count);
1385 drm_free_large(exec_list);
1386 drm_free_large(exec2_list);
1387 return -ENOMEM;
1388 }
1389 ret = copy_from_user(exec_list,
1390 to_user_ptr(args->buffers_ptr),
1391 sizeof(*exec_list) * args->buffer_count);
1392 if (ret != 0) {
1393 DRM_DEBUG("copy %d exec entries failed %d\n",
1394 args->buffer_count, ret);
1395 drm_free_large(exec_list);
1396 drm_free_large(exec2_list);
1397 return -EFAULT;
1398 }
1399
1400 for (i = 0; i < args->buffer_count; i++) {
1401 exec2_list[i].handle = exec_list[i].handle;
1402 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1403 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1404 exec2_list[i].alignment = exec_list[i].alignment;
1405 exec2_list[i].offset = exec_list[i].offset;
1406 if (INTEL_INFO(dev)->gen < 4)
1407 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1408 else
1409 exec2_list[i].flags = 0;
1410 }
1411
1412 exec2.buffers_ptr = args->buffers_ptr;
1413 exec2.buffer_count = args->buffer_count;
1414 exec2.batch_start_offset = args->batch_start_offset;
1415 exec2.batch_len = args->batch_len;
1416 exec2.DR1 = args->DR1;
1417 exec2.DR4 = args->DR4;
1418 exec2.num_cliprects = args->num_cliprects;
1419 exec2.cliprects_ptr = args->cliprects_ptr;
1420 exec2.flags = I915_EXEC_RENDER;
1421 i915_execbuffer2_set_context_id(exec2, 0);
1422
1423 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1424 if (!ret) {
1425 /* Copy the new buffer offsets back to the user's exec list. */
1426 for (i = 0; i < args->buffer_count; i++)
1427 exec_list[i].offset = exec2_list[i].offset;
1428 /* ... and back out to userspace */
1429 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1430 exec_list,
1431 sizeof(*exec_list) * args->buffer_count);
1432 if (ret) {
1433 ret = -EFAULT;
1434 DRM_DEBUG("failed to copy %d exec entries "
1435 "back to user (%d)\n",
1436 args->buffer_count, ret);
1437 }
1438 }
1439
1440 drm_free_large(exec_list);
1441 drm_free_large(exec2_list);
1442 return ret;
1443}
1444
1445int
1446i915_gem_execbuffer2(struct drm_device *dev, void *data,
1447 struct drm_file *file)
1448{
1449 struct drm_i915_gem_execbuffer2 *args = data;
1450 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1451 int ret;
1452
1453 if (args->buffer_count < 1 ||
1454 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1455 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1456 return -EINVAL;
1457 }
1458
1459 if (args->rsvd2 != 0) {
1460 DRM_DEBUG("dirty rvsd2 field\n");
1461 return -EINVAL;
1462 }
1463
1464 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1465 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1466 if (exec2_list == NULL)
1467 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1468 args->buffer_count);
1469 if (exec2_list == NULL) {
1470 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1471 args->buffer_count);
1472 return -ENOMEM;
1473 }
1474 ret = copy_from_user(exec2_list,
1475 to_user_ptr(args->buffers_ptr),
1476 sizeof(*exec2_list) * args->buffer_count);
1477 if (ret != 0) {
1478 DRM_DEBUG("copy %d exec entries failed %d\n",
1479 args->buffer_count, ret);
1480 drm_free_large(exec2_list);
1481 return -EFAULT;
1482 }
1483
1484 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1485 if (!ret) {
1486 /* Copy the new buffer offsets back to the user's exec list. */
1487 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1488 exec2_list,
1489 sizeof(*exec2_list) * args->buffer_count);
1490 if (ret) {
1491 ret = -EFAULT;
1492 DRM_DEBUG("failed to copy %d exec entries "
1493 "back to user (%d)\n",
1494 args->buffer_count, ret);
1495 }
1496 }
1497
1498 drm_free_large(exec2_list);
1499 return ret;
1500}
Linux kernel - Deliverables
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