| 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Please try to maintain the following order within this file unless it makes |
| 24 | * sense to do otherwise. From top to bottom: |
| 25 | * 1. typedefs |
| 26 | * 2. #defines, and macros |
| 27 | * 3. structure definitions |
| 28 | * 4. function prototypes |
| 29 | * |
| 30 | * Within each section, please try to order by generation in ascending order, |
| 31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). |
| 32 | */ |
| 33 | |
| 34 | #ifndef __I915_GEM_GTT_H__ |
| 35 | #define __I915_GEM_GTT_H__ |
| 36 | |
| 37 | struct drm_i915_file_private; |
| 38 | |
| 39 | typedef uint32_t gen6_pte_t; |
| 40 | typedef uint64_t gen8_pte_t; |
| 41 | typedef uint64_t gen8_pde_t; |
| 42 | |
| 43 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
| 44 | |
| 45 | |
| 46 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ |
| 47 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) |
| 48 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
| 49 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
| 50 | #define GEN6_PTE_CACHE_LLC (2 << 1) |
| 51 | #define GEN6_PTE_UNCACHED (1 << 1) |
| 52 | #define GEN6_PTE_VALID (1 << 0) |
| 53 | |
| 54 | #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) |
| 55 | #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) |
| 56 | #define I915_PDES 512 |
| 57 | #define I915_PDE_MASK (I915_PDES - 1) |
| 58 | #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) |
| 59 | |
| 60 | #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) |
| 61 | #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) |
| 62 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
| 63 | #define GEN6_PDE_SHIFT 22 |
| 64 | #define GEN6_PDE_VALID (1 << 0) |
| 65 | |
| 66 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
| 67 | |
| 68 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) |
| 69 | #define BYT_PTE_WRITEABLE (1 << 1) |
| 70 | |
| 71 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits |
| 72 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. |
| 73 | */ |
| 74 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ |
| 75 | (((bits) & 0x8) << (11 - 3))) |
| 76 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
| 77 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
| 78 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
| 79 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
| 80 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
| 81 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
| 82 | #define HSW_PTE_UNCACHED (0) |
| 83 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
| 84 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
| 85 | |
| 86 | /* GEN8 legacy style address is defined as a 3 level page table: |
| 87 | * 31:30 | 29:21 | 20:12 | 11:0 |
| 88 | * PDPE | PDE | PTE | offset |
| 89 | * The difference as compared to normal x86 3 level page table is the PDPEs are |
| 90 | * programmed via register. |
| 91 | */ |
| 92 | #define GEN8_PDPE_SHIFT 30 |
| 93 | #define GEN8_PDPE_MASK 0x3 |
| 94 | #define GEN8_PDE_SHIFT 21 |
| 95 | #define GEN8_PDE_MASK 0x1ff |
| 96 | #define GEN8_PTE_SHIFT 12 |
| 97 | #define GEN8_PTE_MASK 0x1ff |
| 98 | #define GEN8_LEGACY_PDPES 4 |
| 99 | #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) |
| 100 | |
| 101 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
| 102 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ |
| 103 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ |
| 104 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ |
| 105 | |
| 106 | #define CHV_PPAT_SNOOP (1<<6) |
| 107 | #define GEN8_PPAT_AGE(x) (x<<4) |
| 108 | #define GEN8_PPAT_LLCeLLC (3<<2) |
| 109 | #define GEN8_PPAT_LLCELLC (2<<2) |
| 110 | #define GEN8_PPAT_LLC (1<<2) |
| 111 | #define GEN8_PPAT_WB (3<<0) |
| 112 | #define GEN8_PPAT_WT (2<<0) |
| 113 | #define GEN8_PPAT_WC (1<<0) |
| 114 | #define GEN8_PPAT_UC (0<<0) |
| 115 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) |
| 116 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) |
| 117 | |
| 118 | enum i915_ggtt_view_type { |
| 119 | I915_GGTT_VIEW_NORMAL = 0, |
| 120 | I915_GGTT_VIEW_ROTATED |
| 121 | }; |
| 122 | |
| 123 | struct intel_rotation_info { |
| 124 | unsigned int height; |
| 125 | unsigned int pitch; |
| 126 | uint32_t pixel_format; |
| 127 | uint64_t fb_modifier; |
| 128 | }; |
| 129 | |
| 130 | struct i915_ggtt_view { |
| 131 | enum i915_ggtt_view_type type; |
| 132 | |
| 133 | struct sg_table *pages; |
| 134 | |
| 135 | union { |
| 136 | struct intel_rotation_info rotation_info; |
| 137 | }; |
| 138 | }; |
| 139 | |
| 140 | extern const struct i915_ggtt_view i915_ggtt_view_normal; |
| 141 | |
| 142 | enum i915_cache_level; |
| 143 | |
| 144 | /** |
| 145 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
| 146 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
| 147 | * object into/from the address space. |
| 148 | * |
| 149 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
| 150 | * will always be <= an objects lifetime. So object refcounting should cover us. |
| 151 | */ |
| 152 | struct i915_vma { |
| 153 | struct drm_mm_node node; |
| 154 | struct drm_i915_gem_object *obj; |
| 155 | struct i915_address_space *vm; |
| 156 | |
| 157 | /** Flags and address space this VMA is bound to */ |
| 158 | #define GLOBAL_BIND (1<<0) |
| 159 | #define LOCAL_BIND (1<<1) |
| 160 | #define PTE_READ_ONLY (1<<2) |
| 161 | unsigned int bound : 4; |
| 162 | |
| 163 | /** |
| 164 | * Support different GGTT views into the same object. |
| 165 | * This means there can be multiple VMA mappings per object and per VM. |
| 166 | * i915_ggtt_view_type is used to distinguish between those entries. |
| 167 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also |
| 168 | * assumed in GEM functions which take no ggtt view parameter. |
| 169 | */ |
| 170 | struct i915_ggtt_view ggtt_view; |
| 171 | |
| 172 | /** This object's place on the active/inactive lists */ |
| 173 | struct list_head mm_list; |
| 174 | |
| 175 | struct list_head vma_link; /* Link in the object's VMA list */ |
| 176 | |
| 177 | /** This vma's place in the batchbuffer or on the eviction list */ |
| 178 | struct list_head exec_list; |
| 179 | |
| 180 | /** |
| 181 | * Used for performing relocations during execbuffer insertion. |
| 182 | */ |
| 183 | struct hlist_node exec_node; |
| 184 | unsigned long exec_handle; |
| 185 | struct drm_i915_gem_exec_object2 *exec_entry; |
| 186 | |
| 187 | /** |
| 188 | * How many users have pinned this object in GTT space. The following |
| 189 | * users can each hold at most one reference: pwrite/pread, execbuffer |
| 190 | * (objects are not allowed multiple times for the same batchbuffer), |
| 191 | * and the framebuffer code. When switching/pageflipping, the |
| 192 | * framebuffer code has at most two buffers pinned per crtc. |
| 193 | * |
| 194 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 195 | * bits with absolutely no headroom. So use 4 bits. */ |
| 196 | unsigned int pin_count:4; |
| 197 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
| 198 | |
| 199 | /** Unmap an object from an address space. This usually consists of |
| 200 | * setting the valid PTE entries to a reserved scratch page. */ |
| 201 | void (*unbind_vma)(struct i915_vma *vma); |
| 202 | /* Map an object into an address space with the given cache flags. */ |
| 203 | void (*bind_vma)(struct i915_vma *vma, |
| 204 | enum i915_cache_level cache_level, |
| 205 | u32 flags); |
| 206 | }; |
| 207 | |
| 208 | struct i915_page_table_entry { |
| 209 | struct page *page; |
| 210 | dma_addr_t daddr; |
| 211 | |
| 212 | unsigned long *used_ptes; |
| 213 | }; |
| 214 | |
| 215 | struct i915_page_directory_entry { |
| 216 | struct page *page; /* NULL for GEN6-GEN7 */ |
| 217 | union { |
| 218 | uint32_t pd_offset; |
| 219 | dma_addr_t daddr; |
| 220 | }; |
| 221 | |
| 222 | struct i915_page_table_entry *page_table[I915_PDES]; /* PDEs */ |
| 223 | }; |
| 224 | |
| 225 | struct i915_page_directory_pointer_entry { |
| 226 | /* struct page *page; */ |
| 227 | struct i915_page_directory_entry *page_directory[GEN8_LEGACY_PDPES]; |
| 228 | }; |
| 229 | |
| 230 | struct i915_address_space { |
| 231 | struct drm_mm mm; |
| 232 | struct drm_device *dev; |
| 233 | struct list_head global_link; |
| 234 | unsigned long start; /* Start offset always 0 for dri2 */ |
| 235 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
| 236 | |
| 237 | struct { |
| 238 | dma_addr_t addr; |
| 239 | struct page *page; |
| 240 | } scratch; |
| 241 | |
| 242 | /** |
| 243 | * List of objects currently involved in rendering. |
| 244 | * |
| 245 | * Includes buffers having the contents of their GPU caches |
| 246 | * flushed, not necessarily primitives. last_read_req |
| 247 | * represents when the rendering involved will be completed. |
| 248 | * |
| 249 | * A reference is held on the buffer while on this list. |
| 250 | */ |
| 251 | struct list_head active_list; |
| 252 | |
| 253 | /** |
| 254 | * LRU list of objects which are not in the ringbuffer and |
| 255 | * are ready to unbind, but are still in the GTT. |
| 256 | * |
| 257 | * last_read_req is NULL while an object is in this list. |
| 258 | * |
| 259 | * A reference is not held on the buffer while on this list, |
| 260 | * as merely being GTT-bound shouldn't prevent its being |
| 261 | * freed, and we'll pull it off the list in the free path. |
| 262 | */ |
| 263 | struct list_head inactive_list; |
| 264 | |
| 265 | /* FIXME: Need a more generic return type */ |
| 266 | gen6_pte_t (*pte_encode)(dma_addr_t addr, |
| 267 | enum i915_cache_level level, |
| 268 | bool valid, u32 flags); /* Create a valid PTE */ |
| 269 | int (*allocate_va_range)(struct i915_address_space *vm, |
| 270 | uint64_t start, |
| 271 | uint64_t length); |
| 272 | void (*clear_range)(struct i915_address_space *vm, |
| 273 | uint64_t start, |
| 274 | uint64_t length, |
| 275 | bool use_scratch); |
| 276 | void (*insert_entries)(struct i915_address_space *vm, |
| 277 | struct sg_table *st, |
| 278 | uint64_t start, |
| 279 | enum i915_cache_level cache_level, u32 flags); |
| 280 | void (*cleanup)(struct i915_address_space *vm); |
| 281 | }; |
| 282 | |
| 283 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
| 284 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
| 285 | * collateral associated with any va->pa translations GEN hardware also has a |
| 286 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
| 287 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
| 288 | * the spec. |
| 289 | */ |
| 290 | struct i915_gtt { |
| 291 | struct i915_address_space base; |
| 292 | size_t stolen_size; /* Total size of stolen memory */ |
| 293 | |
| 294 | unsigned long mappable_end; /* End offset that we can CPU map */ |
| 295 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
| 296 | phys_addr_t mappable_base; /* PA of our GMADR */ |
| 297 | |
| 298 | /** "Graphics Stolen Memory" holds the global PTEs */ |
| 299 | void __iomem *gsm; |
| 300 | |
| 301 | bool do_idle_maps; |
| 302 | |
| 303 | int mtrr; |
| 304 | |
| 305 | /* global gtt ops */ |
| 306 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
| 307 | size_t *stolen, phys_addr_t *mappable_base, |
| 308 | unsigned long *mappable_end); |
| 309 | }; |
| 310 | |
| 311 | struct i915_hw_ppgtt { |
| 312 | struct i915_address_space base; |
| 313 | struct kref ref; |
| 314 | struct drm_mm_node node; |
| 315 | unsigned long pd_dirty_rings; |
| 316 | unsigned num_pd_entries; |
| 317 | unsigned num_pd_pages; /* gen8+ */ |
| 318 | union { |
| 319 | struct i915_page_directory_pointer_entry pdp; |
| 320 | struct i915_page_directory_entry pd; |
| 321 | }; |
| 322 | |
| 323 | struct drm_i915_file_private *file_priv; |
| 324 | |
| 325 | gen6_pte_t __iomem *pd_addr; |
| 326 | |
| 327 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
| 328 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, |
| 329 | struct intel_engine_cs *ring); |
| 330 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
| 331 | }; |
| 332 | |
| 333 | /* For each pde iterates over every pde between from start until start + length. |
| 334 | * If start, and start+length are not perfectly divisible, the macro will round |
| 335 | * down, and up as needed. The macro modifies pde, start, and length. Dev is |
| 336 | * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, |
| 337 | * and length = 2G effectively iterates over every PDE in the system. |
| 338 | * |
| 339 | * XXX: temp is not actually needed, but it saves doing the ALIGN operation. |
| 340 | */ |
| 341 | #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ |
| 342 | for (iter = gen6_pde_index(start), pt = (pd)->page_table[iter]; \ |
| 343 | length > 0 && iter < I915_PDES; \ |
| 344 | pt = (pd)->page_table[++iter], \ |
| 345 | temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ |
| 346 | temp = min_t(unsigned, temp, length), \ |
| 347 | start += temp, length -= temp) |
| 348 | |
| 349 | static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) |
| 350 | { |
| 351 | const uint32_t mask = NUM_PTE(pde_shift) - 1; |
| 352 | |
| 353 | return (address >> PAGE_SHIFT) & mask; |
| 354 | } |
| 355 | |
| 356 | /* Helper to counts the number of PTEs within the given length. This count |
| 357 | * does not cross a page table boundary, so the max value would be |
| 358 | * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. |
| 359 | */ |
| 360 | static inline uint32_t i915_pte_count(uint64_t addr, size_t length, |
| 361 | uint32_t pde_shift) |
| 362 | { |
| 363 | const uint64_t mask = ~((1 << pde_shift) - 1); |
| 364 | uint64_t end; |
| 365 | |
| 366 | WARN_ON(length == 0); |
| 367 | WARN_ON(offset_in_page(addr|length)); |
| 368 | |
| 369 | end = addr + length; |
| 370 | |
| 371 | if ((addr & mask) != (end & mask)) |
| 372 | return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); |
| 373 | |
| 374 | return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); |
| 375 | } |
| 376 | |
| 377 | static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) |
| 378 | { |
| 379 | return (addr >> shift) & I915_PDE_MASK; |
| 380 | } |
| 381 | |
| 382 | static inline uint32_t gen6_pte_index(uint32_t addr) |
| 383 | { |
| 384 | return i915_pte_index(addr, GEN6_PDE_SHIFT); |
| 385 | } |
| 386 | |
| 387 | static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) |
| 388 | { |
| 389 | return i915_pte_count(addr, length, GEN6_PDE_SHIFT); |
| 390 | } |
| 391 | |
| 392 | static inline uint32_t gen6_pde_index(uint32_t addr) |
| 393 | { |
| 394 | return i915_pde_index(addr, GEN6_PDE_SHIFT); |
| 395 | } |
| 396 | |
| 397 | int i915_gem_gtt_init(struct drm_device *dev); |
| 398 | void i915_gem_init_global_gtt(struct drm_device *dev); |
| 399 | void i915_global_gtt_cleanup(struct drm_device *dev); |
| 400 | |
| 401 | |
| 402 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); |
| 403 | int i915_ppgtt_init_hw(struct drm_device *dev); |
| 404 | void i915_ppgtt_release(struct kref *kref); |
| 405 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, |
| 406 | struct drm_i915_file_private *fpriv); |
| 407 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
| 408 | { |
| 409 | if (ppgtt) |
| 410 | kref_get(&ppgtt->ref); |
| 411 | } |
| 412 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) |
| 413 | { |
| 414 | if (ppgtt) |
| 415 | kref_put(&ppgtt->ref, i915_ppgtt_release); |
| 416 | } |
| 417 | |
| 418 | void i915_check_and_clear_faults(struct drm_device *dev); |
| 419 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
| 420 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
| 421 | |
| 422 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
| 423 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
| 424 | |
| 425 | #endif |