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Merge tag 'v3.14' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
... / ...
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1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/sysrq.h>
32#include <linux/slab.h>
33#include <linux/circ_buf.h>
34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
36#include "i915_drv.h"
37#include "i915_trace.h"
38#include "intel_drv.h"
39
40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
65static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
83/* For display hotplug interrupt */
84static void
85ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86{
87 assert_spin_locked(&dev_priv->irq_lock);
88
89 if (dev_priv->pm.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pm.regsave.deimr &= ~mask;
92 return;
93 }
94
95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
98 POSTING_READ(DEIMR);
99 }
100}
101
102static void
103ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
104{
105 assert_spin_locked(&dev_priv->irq_lock);
106
107 if (dev_priv->pm.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pm.regsave.deimr |= mask;
110 return;
111 }
112
113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
116 POSTING_READ(DEIMR);
117 }
118}
119
120/**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129{
130 assert_spin_locked(&dev_priv->irq_lock);
131
132 if (dev_priv->pm.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pm.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144}
145
146void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147{
148 ilk_update_gt_irq(dev_priv, mask, mask);
149}
150
151void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152{
153 ilk_update_gt_irq(dev_priv, mask, 0);
154}
155
156/**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165{
166 uint32_t new_val;
167
168 assert_spin_locked(&dev_priv->irq_lock);
169
170 if (dev_priv->pm.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
178 new_val = dev_priv->pm_irq_mask;
179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
185 POSTING_READ(GEN6_PMIMR);
186 }
187}
188
189void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190{
191 snb_update_pm_irq(dev_priv, mask, mask);
192}
193
194void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195{
196 snb_update_pm_irq(dev_priv, mask, 0);
197}
198
199static bool ivb_can_enable_err_int(struct drm_device *dev)
200{
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
205 assert_spin_locked(&dev_priv->irq_lock);
206
207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215}
216
217static bool cpt_can_enable_serr_int(struct drm_device *dev)
218{
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
223 assert_spin_locked(&dev_priv->irq_lock);
224
225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233}
234
235static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
236{
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 reg = PIPESTAT(pipe);
239 u32 pipestat = I915_READ(reg) & 0x7fff0000;
240
241 assert_spin_locked(&dev_priv->irq_lock);
242
243 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
244 POSTING_READ(reg);
245}
246
247static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
252 DE_PIPEB_FIFO_UNDERRUN;
253
254 if (enable)
255 ironlake_enable_display_irq(dev_priv, bit);
256 else
257 ironlake_disable_display_irq(dev_priv, bit);
258}
259
260static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
261 enum pipe pipe, bool enable)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 if (enable) {
265 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
266
267 if (!ivb_can_enable_err_int(dev))
268 return;
269
270 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
271 } else {
272 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
273
274 /* Change the state _after_ we've read out the current one. */
275 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
276
277 if (!was_enabled &&
278 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
279 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
280 pipe_name(pipe));
281 }
282 }
283}
284
285static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
286 enum pipe pipe, bool enable)
287{
288 struct drm_i915_private *dev_priv = dev->dev_private;
289
290 assert_spin_locked(&dev_priv->irq_lock);
291
292 if (enable)
293 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
294 else
295 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
296 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
297 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
298}
299
300/**
301 * ibx_display_interrupt_update - update SDEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
307 uint32_t interrupt_mask,
308 uint32_t enabled_irq_mask)
309{
310 uint32_t sdeimr = I915_READ(SDEIMR);
311 sdeimr &= ~interrupt_mask;
312 sdeimr |= (~enabled_irq_mask & interrupt_mask);
313
314 assert_spin_locked(&dev_priv->irq_lock);
315
316 if (dev_priv->pm.irqs_disabled &&
317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
318 WARN(1, "IRQs disabled\n");
319 dev_priv->pm.regsave.sdeimr &= ~interrupt_mask;
320 dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask &
321 interrupt_mask);
322 return;
323 }
324
325 I915_WRITE(SDEIMR, sdeimr);
326 POSTING_READ(SDEIMR);
327}
328#define ibx_enable_display_interrupt(dev_priv, bits) \
329 ibx_display_interrupt_update((dev_priv), (bits), (bits))
330#define ibx_disable_display_interrupt(dev_priv, bits) \
331 ibx_display_interrupt_update((dev_priv), (bits), 0)
332
333static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
334 enum transcoder pch_transcoder,
335 bool enable)
336{
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
339 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
340
341 if (enable)
342 ibx_enable_display_interrupt(dev_priv, bit);
343 else
344 ibx_disable_display_interrupt(dev_priv, bit);
345}
346
347static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
348 enum transcoder pch_transcoder,
349 bool enable)
350{
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 if (enable) {
354 I915_WRITE(SERR_INT,
355 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
356
357 if (!cpt_can_enable_serr_int(dev))
358 return;
359
360 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
361 } else {
362 uint32_t tmp = I915_READ(SERR_INT);
363 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
364
365 /* Change the state _after_ we've read out the current one. */
366 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
367
368 if (!was_enabled &&
369 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
370 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
371 transcoder_name(pch_transcoder));
372 }
373 }
374}
375
376/**
377 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
378 * @dev: drm device
379 * @pipe: pipe
380 * @enable: true if we want to report FIFO underrun errors, false otherwise
381 *
382 * This function makes us disable or enable CPU fifo underruns for a specific
383 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
384 * reporting for one pipe may also disable all the other CPU error interruts for
385 * the other pipes, due to the fact that there's just one interrupt mask/enable
386 * bit for all the pipes.
387 *
388 * Returns the previous state of underrun reporting.
389 */
390bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
391 enum pipe pipe, bool enable)
392{
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
396 bool ret;
397
398 assert_spin_locked(&dev_priv->irq_lock);
399
400 ret = !intel_crtc->cpu_fifo_underrun_disabled;
401
402 if (enable == ret)
403 goto done;
404
405 intel_crtc->cpu_fifo_underrun_disabled = !enable;
406
407 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
408 i9xx_clear_fifo_underrun(dev, pipe);
409 else if (IS_GEN5(dev) || IS_GEN6(dev))
410 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
411 else if (IS_GEN7(dev))
412 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
413 else if (IS_GEN8(dev))
414 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
415
416done:
417 return ret;
418}
419
420bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
421 enum pipe pipe, bool enable)
422{
423 struct drm_i915_private *dev_priv = dev->dev_private;
424 unsigned long flags;
425 bool ret;
426
427 spin_lock_irqsave(&dev_priv->irq_lock, flags);
428 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
429 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
430
431 return ret;
432}
433
434static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
435 enum pipe pipe)
436{
437 struct drm_i915_private *dev_priv = dev->dev_private;
438 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
440
441 return !intel_crtc->cpu_fifo_underrun_disabled;
442}
443
444/**
445 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
446 * @dev: drm device
447 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
448 * @enable: true if we want to report FIFO underrun errors, false otherwise
449 *
450 * This function makes us disable or enable PCH fifo underruns for a specific
451 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
452 * underrun reporting for one transcoder may also disable all the other PCH
453 * error interruts for the other transcoders, due to the fact that there's just
454 * one interrupt mask/enable bit for all the transcoders.
455 *
456 * Returns the previous state of underrun reporting.
457 */
458bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
459 enum transcoder pch_transcoder,
460 bool enable)
461{
462 struct drm_i915_private *dev_priv = dev->dev_private;
463 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
465 unsigned long flags;
466 bool ret;
467
468 /*
469 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
470 * has only one pch transcoder A that all pipes can use. To avoid racy
471 * pch transcoder -> pipe lookups from interrupt code simply store the
472 * underrun statistics in crtc A. Since we never expose this anywhere
473 * nor use it outside of the fifo underrun code here using the "wrong"
474 * crtc on LPT won't cause issues.
475 */
476
477 spin_lock_irqsave(&dev_priv->irq_lock, flags);
478
479 ret = !intel_crtc->pch_fifo_underrun_disabled;
480
481 if (enable == ret)
482 goto done;
483
484 intel_crtc->pch_fifo_underrun_disabled = !enable;
485
486 if (HAS_PCH_IBX(dev))
487 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
488 else
489 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
490
491done:
492 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
493 return ret;
494}
495
496
497static void
498__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
499 u32 enable_mask, u32 status_mask)
500{
501 u32 reg = PIPESTAT(pipe);
502 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
503
504 assert_spin_locked(&dev_priv->irq_lock);
505
506 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
507 status_mask & ~PIPESTAT_INT_STATUS_MASK))
508 return;
509
510 if ((pipestat & enable_mask) == enable_mask)
511 return;
512
513 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
514
515 /* Enable the interrupt, clear any pending status */
516 pipestat |= enable_mask | status_mask;
517 I915_WRITE(reg, pipestat);
518 POSTING_READ(reg);
519}
520
521static void
522__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
523 u32 enable_mask, u32 status_mask)
524{
525 u32 reg = PIPESTAT(pipe);
526 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
527
528 assert_spin_locked(&dev_priv->irq_lock);
529
530 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
531 status_mask & ~PIPESTAT_INT_STATUS_MASK))
532 return;
533
534 if ((pipestat & enable_mask) == 0)
535 return;
536
537 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
538
539 pipestat &= ~enable_mask;
540 I915_WRITE(reg, pipestat);
541 POSTING_READ(reg);
542}
543
544static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
545{
546 u32 enable_mask = status_mask << 16;
547
548 /*
549 * On pipe A we don't support the PSR interrupt yet, on pipe B the
550 * same bit MBZ.
551 */
552 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
553 return 0;
554
555 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
556 SPRITE0_FLIP_DONE_INT_EN_VLV |
557 SPRITE1_FLIP_DONE_INT_EN_VLV);
558 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
559 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
560 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
561 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
562
563 return enable_mask;
564}
565
566void
567i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
568 u32 status_mask)
569{
570 u32 enable_mask;
571
572 if (IS_VALLEYVIEW(dev_priv->dev))
573 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
574 status_mask);
575 else
576 enable_mask = status_mask << 16;
577 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
578}
579
580void
581i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
582 u32 status_mask)
583{
584 u32 enable_mask;
585
586 if (IS_VALLEYVIEW(dev_priv->dev))
587 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
588 status_mask);
589 else
590 enable_mask = status_mask << 16;
591 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
592}
593
594/**
595 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
596 */
597static void i915_enable_asle_pipestat(struct drm_device *dev)
598{
599 drm_i915_private_t *dev_priv = dev->dev_private;
600 unsigned long irqflags;
601
602 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
603 return;
604
605 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
606
607 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
608 if (INTEL_INFO(dev)->gen >= 4)
609 i915_enable_pipestat(dev_priv, PIPE_A,
610 PIPE_LEGACY_BLC_EVENT_STATUS);
611
612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
613}
614
615/**
616 * i915_pipe_enabled - check if a pipe is enabled
617 * @dev: DRM device
618 * @pipe: pipe to check
619 *
620 * Reading certain registers when the pipe is disabled can hang the chip.
621 * Use this routine to make sure the PLL is running and the pipe is active
622 * before reading such registers if unsure.
623 */
624static int
625i915_pipe_enabled(struct drm_device *dev, int pipe)
626{
627 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
628
629 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
630 /* Locking is horribly broken here, but whatever. */
631 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
633
634 return intel_crtc->active;
635 } else {
636 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
637 }
638}
639
640static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
641{
642 /* Gen2 doesn't have a hardware frame counter */
643 return 0;
644}
645
646/* Called from drm generic code, passed a 'crtc', which
647 * we use as a pipe index
648 */
649static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
650{
651 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
652 unsigned long high_frame;
653 unsigned long low_frame;
654 u32 high1, high2, low, pixel, vbl_start;
655
656 if (!i915_pipe_enabled(dev, pipe)) {
657 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
658 "pipe %c\n", pipe_name(pipe));
659 return 0;
660 }
661
662 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
663 struct intel_crtc *intel_crtc =
664 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
665 const struct drm_display_mode *mode =
666 &intel_crtc->config.adjusted_mode;
667
668 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
669 } else {
670 enum transcoder cpu_transcoder = (enum transcoder) pipe;
671 u32 htotal;
672
673 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
674 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
675
676 vbl_start *= htotal;
677 }
678
679 high_frame = PIPEFRAME(pipe);
680 low_frame = PIPEFRAMEPIXEL(pipe);
681
682 /*
683 * High & low register fields aren't synchronized, so make sure
684 * we get a low value that's stable across two reads of the high
685 * register.
686 */
687 do {
688 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
689 low = I915_READ(low_frame);
690 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
691 } while (high1 != high2);
692
693 high1 >>= PIPE_FRAME_HIGH_SHIFT;
694 pixel = low & PIPE_PIXEL_MASK;
695 low >>= PIPE_FRAME_LOW_SHIFT;
696
697 /*
698 * The frame counter increments at beginning of active.
699 * Cook up a vblank counter by also checking the pixel
700 * counter against vblank start.
701 */
702 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
703}
704
705static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
706{
707 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
708 int reg = PIPE_FRMCOUNT_GM45(pipe);
709
710 if (!i915_pipe_enabled(dev, pipe)) {
711 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
712 "pipe %c\n", pipe_name(pipe));
713 return 0;
714 }
715
716 return I915_READ(reg);
717}
718
719/* raw reads, only for fast reads of display block, no need for forcewake etc. */
720#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
721
722static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
723{
724 struct drm_i915_private *dev_priv = dev->dev_private;
725 uint32_t status;
726 int reg;
727
728 if (INTEL_INFO(dev)->gen >= 8) {
729 status = GEN8_PIPE_VBLANK;
730 reg = GEN8_DE_PIPE_ISR(pipe);
731 } else if (INTEL_INFO(dev)->gen >= 7) {
732 status = DE_PIPE_VBLANK_IVB(pipe);
733 reg = DEISR;
734 } else {
735 status = DE_PIPE_VBLANK(pipe);
736 reg = DEISR;
737 }
738
739 return __raw_i915_read32(dev_priv, reg) & status;
740}
741
742static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
743 unsigned int flags, int *vpos, int *hpos,
744 ktime_t *stime, ktime_t *etime)
745{
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
749 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
750 int position;
751 int vbl_start, vbl_end, htotal, vtotal;
752 bool in_vbl = true;
753 int ret = 0;
754 unsigned long irqflags;
755
756 if (!intel_crtc->active) {
757 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
758 "pipe %c\n", pipe_name(pipe));
759 return 0;
760 }
761
762 htotal = mode->crtc_htotal;
763 vtotal = mode->crtc_vtotal;
764 vbl_start = mode->crtc_vblank_start;
765 vbl_end = mode->crtc_vblank_end;
766
767 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
768 vbl_start = DIV_ROUND_UP(vbl_start, 2);
769 vbl_end /= 2;
770 vtotal /= 2;
771 }
772
773 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
774
775 /*
776 * Lock uncore.lock, as we will do multiple timing critical raw
777 * register reads, potentially with preemption disabled, so the
778 * following code must not block on uncore.lock.
779 */
780 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
781
782 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
783
784 /* Get optional system timestamp before query. */
785 if (stime)
786 *stime = ktime_get();
787
788 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
789 /* No obvious pixelcount register. Only query vertical
790 * scanout position from Display scan line register.
791 */
792 if (IS_GEN2(dev))
793 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
794 else
795 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
796
797 if (HAS_DDI(dev)) {
798 /*
799 * On HSW HDMI outputs there seems to be a 2 line
800 * difference, whereas eDP has the normal 1 line
801 * difference that earlier platforms have. External
802 * DP is unknown. For now just check for the 2 line
803 * difference case on all output types on HSW+.
804 *
805 * This might misinterpret the scanline counter being
806 * one line too far along on eDP, but that's less
807 * dangerous than the alternative since that would lead
808 * the vblank timestamp code astray when it sees a
809 * scanline count before vblank_start during a vblank
810 * interrupt.
811 */
812 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
813 if ((in_vbl && (position == vbl_start - 2 ||
814 position == vbl_start - 1)) ||
815 (!in_vbl && (position == vbl_end - 2 ||
816 position == vbl_end - 1)))
817 position = (position + 2) % vtotal;
818 } else if (HAS_PCH_SPLIT(dev)) {
819 /*
820 * The scanline counter increments at the leading edge
821 * of hsync, ie. it completely misses the active portion
822 * of the line. Fix up the counter at both edges of vblank
823 * to get a more accurate picture whether we're in vblank
824 * or not.
825 */
826 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
827 if ((in_vbl && position == vbl_start - 1) ||
828 (!in_vbl && position == vbl_end - 1))
829 position = (position + 1) % vtotal;
830 } else {
831 /*
832 * ISR vblank status bits don't work the way we'd want
833 * them to work on non-PCH platforms (for
834 * ilk_pipe_in_vblank_locked()), and there doesn't
835 * appear any other way to determine if we're currently
836 * in vblank.
837 *
838 * Instead let's assume that we're already in vblank if
839 * we got called from the vblank interrupt and the
840 * scanline counter value indicates that we're on the
841 * line just prior to vblank start. This should result
842 * in the correct answer, unless the vblank interrupt
843 * delivery really got delayed for almost exactly one
844 * full frame/field.
845 */
846 if (flags & DRM_CALLED_FROM_VBLIRQ &&
847 position == vbl_start - 1) {
848 position = (position + 1) % vtotal;
849
850 /* Signal this correction as "applied". */
851 ret |= 0x8;
852 }
853 }
854 } else {
855 /* Have access to pixelcount since start of frame.
856 * We can split this into vertical and horizontal
857 * scanout position.
858 */
859 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
860
861 /* convert to pixel counts */
862 vbl_start *= htotal;
863 vbl_end *= htotal;
864 vtotal *= htotal;
865 }
866
867 /* Get optional system timestamp after query. */
868 if (etime)
869 *etime = ktime_get();
870
871 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
872
873 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
874
875 in_vbl = position >= vbl_start && position < vbl_end;
876
877 /*
878 * While in vblank, position will be negative
879 * counting up towards 0 at vbl_end. And outside
880 * vblank, position will be positive counting
881 * up since vbl_end.
882 */
883 if (position >= vbl_start)
884 position -= vbl_end;
885 else
886 position += vtotal - vbl_end;
887
888 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
889 *vpos = position;
890 *hpos = 0;
891 } else {
892 *vpos = position / htotal;
893 *hpos = position - (*vpos * htotal);
894 }
895
896 /* In vblank? */
897 if (in_vbl)
898 ret |= DRM_SCANOUTPOS_INVBL;
899
900 return ret;
901}
902
903static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
904 int *max_error,
905 struct timeval *vblank_time,
906 unsigned flags)
907{
908 struct drm_crtc *crtc;
909
910 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
911 DRM_ERROR("Invalid crtc %d\n", pipe);
912 return -EINVAL;
913 }
914
915 /* Get drm_crtc to timestamp: */
916 crtc = intel_get_crtc_for_pipe(dev, pipe);
917 if (crtc == NULL) {
918 DRM_ERROR("Invalid crtc %d\n", pipe);
919 return -EINVAL;
920 }
921
922 if (!crtc->enabled) {
923 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
924 return -EBUSY;
925 }
926
927 /* Helper routine in DRM core does all the work: */
928 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
929 vblank_time, flags,
930 crtc,
931 &to_intel_crtc(crtc)->config.adjusted_mode);
932}
933
934static bool intel_hpd_irq_event(struct drm_device *dev,
935 struct drm_connector *connector)
936{
937 enum drm_connector_status old_status;
938
939 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
940 old_status = connector->status;
941
942 connector->status = connector->funcs->detect(connector, false);
943 if (old_status == connector->status)
944 return false;
945
946 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
947 connector->base.id,
948 drm_get_connector_name(connector),
949 drm_get_connector_status_name(old_status),
950 drm_get_connector_status_name(connector->status));
951
952 return true;
953}
954
955/*
956 * Handle hotplug events outside the interrupt handler proper.
957 */
958#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
959
960static void i915_hotplug_work_func(struct work_struct *work)
961{
962 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
963 hotplug_work);
964 struct drm_device *dev = dev_priv->dev;
965 struct drm_mode_config *mode_config = &dev->mode_config;
966 struct intel_connector *intel_connector;
967 struct intel_encoder *intel_encoder;
968 struct drm_connector *connector;
969 unsigned long irqflags;
970 bool hpd_disabled = false;
971 bool changed = false;
972 u32 hpd_event_bits;
973
974 /* HPD irq before everything is fully set up. */
975 if (!dev_priv->enable_hotplug_processing)
976 return;
977
978 mutex_lock(&mode_config->mutex);
979 DRM_DEBUG_KMS("running encoder hotplug functions\n");
980
981 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
982
983 hpd_event_bits = dev_priv->hpd_event_bits;
984 dev_priv->hpd_event_bits = 0;
985 list_for_each_entry(connector, &mode_config->connector_list, head) {
986 intel_connector = to_intel_connector(connector);
987 intel_encoder = intel_connector->encoder;
988 if (intel_encoder->hpd_pin > HPD_NONE &&
989 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
990 connector->polled == DRM_CONNECTOR_POLL_HPD) {
991 DRM_INFO("HPD interrupt storm detected on connector %s: "
992 "switching from hotplug detection to polling\n",
993 drm_get_connector_name(connector));
994 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
995 connector->polled = DRM_CONNECTOR_POLL_CONNECT
996 | DRM_CONNECTOR_POLL_DISCONNECT;
997 hpd_disabled = true;
998 }
999 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1000 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1001 drm_get_connector_name(connector), intel_encoder->hpd_pin);
1002 }
1003 }
1004 /* if there were no outputs to poll, poll was disabled,
1005 * therefore make sure it's enabled when disabling HPD on
1006 * some connectors */
1007 if (hpd_disabled) {
1008 drm_kms_helper_poll_enable(dev);
1009 mod_timer(&dev_priv->hotplug_reenable_timer,
1010 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1011 }
1012
1013 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1014
1015 list_for_each_entry(connector, &mode_config->connector_list, head) {
1016 intel_connector = to_intel_connector(connector);
1017 intel_encoder = intel_connector->encoder;
1018 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1019 if (intel_encoder->hot_plug)
1020 intel_encoder->hot_plug(intel_encoder);
1021 if (intel_hpd_irq_event(dev, connector))
1022 changed = true;
1023 }
1024 }
1025 mutex_unlock(&mode_config->mutex);
1026
1027 if (changed)
1028 drm_kms_helper_hotplug_event(dev);
1029}
1030
1031static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1032{
1033 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1034}
1035
1036static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1037{
1038 drm_i915_private_t *dev_priv = dev->dev_private;
1039 u32 busy_up, busy_down, max_avg, min_avg;
1040 u8 new_delay;
1041
1042 spin_lock(&mchdev_lock);
1043
1044 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1045
1046 new_delay = dev_priv->ips.cur_delay;
1047
1048 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1049 busy_up = I915_READ(RCPREVBSYTUPAVG);
1050 busy_down = I915_READ(RCPREVBSYTDNAVG);
1051 max_avg = I915_READ(RCBMAXAVG);
1052 min_avg = I915_READ(RCBMINAVG);
1053
1054 /* Handle RCS change request from hw */
1055 if (busy_up > max_avg) {
1056 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1057 new_delay = dev_priv->ips.cur_delay - 1;
1058 if (new_delay < dev_priv->ips.max_delay)
1059 new_delay = dev_priv->ips.max_delay;
1060 } else if (busy_down < min_avg) {
1061 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1062 new_delay = dev_priv->ips.cur_delay + 1;
1063 if (new_delay > dev_priv->ips.min_delay)
1064 new_delay = dev_priv->ips.min_delay;
1065 }
1066
1067 if (ironlake_set_drps(dev, new_delay))
1068 dev_priv->ips.cur_delay = new_delay;
1069
1070 spin_unlock(&mchdev_lock);
1071
1072 return;
1073}
1074
1075static void notify_ring(struct drm_device *dev,
1076 struct intel_ring_buffer *ring)
1077{
1078 if (ring->obj == NULL)
1079 return;
1080
1081 trace_i915_gem_request_complete(ring);
1082
1083 wake_up_all(&ring->irq_queue);
1084 i915_queue_hangcheck(dev);
1085}
1086
1087void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
1088 u32 pm_iir, int new_delay)
1089{
1090 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1091 if (new_delay >= dev_priv->rps.max_freq_softlimit) {
1092 /* Mask UP THRESHOLD Interrupts */
1093 I915_WRITE(GEN6_PMINTRMSK,
1094 I915_READ(GEN6_PMINTRMSK) |
1095 GEN6_PM_RP_UP_THRESHOLD);
1096 dev_priv->rps.rp_up_masked = true;
1097 }
1098 if (dev_priv->rps.rp_down_masked) {
1099 /* UnMask DOWN THRESHOLD Interrupts */
1100 I915_WRITE(GEN6_PMINTRMSK,
1101 I915_READ(GEN6_PMINTRMSK) &
1102 ~GEN6_PM_RP_DOWN_THRESHOLD);
1103 dev_priv->rps.rp_down_masked = false;
1104 }
1105 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1106 if (new_delay <= dev_priv->rps.min_freq_softlimit) {
1107 /* Mask DOWN THRESHOLD Interrupts */
1108 I915_WRITE(GEN6_PMINTRMSK,
1109 I915_READ(GEN6_PMINTRMSK) |
1110 GEN6_PM_RP_DOWN_THRESHOLD);
1111 dev_priv->rps.rp_down_masked = true;
1112 }
1113
1114 if (dev_priv->rps.rp_up_masked) {
1115 /* UnMask UP THRESHOLD Interrupts */
1116 I915_WRITE(GEN6_PMINTRMSK,
1117 I915_READ(GEN6_PMINTRMSK) &
1118 ~GEN6_PM_RP_UP_THRESHOLD);
1119 dev_priv->rps.rp_up_masked = false;
1120 }
1121 }
1122}
1123
1124static void gen6_pm_rps_work(struct work_struct *work)
1125{
1126 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1127 rps.work);
1128 u32 pm_iir;
1129 int new_delay, adj;
1130
1131 spin_lock_irq(&dev_priv->irq_lock);
1132 pm_iir = dev_priv->rps.pm_iir;
1133 dev_priv->rps.pm_iir = 0;
1134 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1135 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1136 spin_unlock_irq(&dev_priv->irq_lock);
1137
1138 /* Make sure we didn't queue anything we're not going to process. */
1139 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1140
1141 if ((pm_iir & dev_priv->pm_rps_events) == 0)
1142 return;
1143
1144 mutex_lock(&dev_priv->rps.hw_lock);
1145
1146 adj = dev_priv->rps.last_adj;
1147 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1148 if (adj > 0)
1149 adj *= 2;
1150 else
1151 adj = 1;
1152 new_delay = dev_priv->rps.cur_freq + adj;
1153
1154 /*
1155 * For better performance, jump directly
1156 * to RPe if we're below it.
1157 */
1158 if (new_delay < dev_priv->rps.efficient_freq)
1159 new_delay = dev_priv->rps.efficient_freq;
1160 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1161 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1162 new_delay = dev_priv->rps.efficient_freq;
1163 else
1164 new_delay = dev_priv->rps.min_freq_softlimit;
1165 adj = 0;
1166 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1167 if (adj < 0)
1168 adj *= 2;
1169 else
1170 adj = -1;
1171 new_delay = dev_priv->rps.cur_freq + adj;
1172 } else { /* unknown event */
1173 new_delay = dev_priv->rps.cur_freq;
1174 }
1175
1176 /* sysfs frequency interfaces may have snuck in while servicing the
1177 * interrupt
1178 */
1179 new_delay = clamp_t(int, new_delay,
1180 dev_priv->rps.min_freq_softlimit,
1181 dev_priv->rps.max_freq_softlimit);
1182
1183 gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1184 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1185
1186 if (IS_VALLEYVIEW(dev_priv->dev))
1187 valleyview_set_rps(dev_priv->dev, new_delay);
1188 else
1189 gen6_set_rps(dev_priv->dev, new_delay);
1190
1191 mutex_unlock(&dev_priv->rps.hw_lock);
1192}
1193
1194
1195/**
1196 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1197 * occurred.
1198 * @work: workqueue struct
1199 *
1200 * Doesn't actually do anything except notify userspace. As a consequence of
1201 * this event, userspace should try to remap the bad rows since statistically
1202 * it is likely the same row is more likely to go bad again.
1203 */
1204static void ivybridge_parity_work(struct work_struct *work)
1205{
1206 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1207 l3_parity.error_work);
1208 u32 error_status, row, bank, subbank;
1209 char *parity_event[6];
1210 uint32_t misccpctl;
1211 unsigned long flags;
1212 uint8_t slice = 0;
1213
1214 /* We must turn off DOP level clock gating to access the L3 registers.
1215 * In order to prevent a get/put style interface, acquire struct mutex
1216 * any time we access those registers.
1217 */
1218 mutex_lock(&dev_priv->dev->struct_mutex);
1219
1220 /* If we've screwed up tracking, just let the interrupt fire again */
1221 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1222 goto out;
1223
1224 misccpctl = I915_READ(GEN7_MISCCPCTL);
1225 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1226 POSTING_READ(GEN7_MISCCPCTL);
1227
1228 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1229 u32 reg;
1230
1231 slice--;
1232 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1233 break;
1234
1235 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1236
1237 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1238
1239 error_status = I915_READ(reg);
1240 row = GEN7_PARITY_ERROR_ROW(error_status);
1241 bank = GEN7_PARITY_ERROR_BANK(error_status);
1242 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1243
1244 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1245 POSTING_READ(reg);
1246
1247 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1248 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1249 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1250 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1251 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1252 parity_event[5] = NULL;
1253
1254 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1255 KOBJ_CHANGE, parity_event);
1256
1257 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1258 slice, row, bank, subbank);
1259
1260 kfree(parity_event[4]);
1261 kfree(parity_event[3]);
1262 kfree(parity_event[2]);
1263 kfree(parity_event[1]);
1264 }
1265
1266 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1267
1268out:
1269 WARN_ON(dev_priv->l3_parity.which_slice);
1270 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1271 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1272 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1273
1274 mutex_unlock(&dev_priv->dev->struct_mutex);
1275}
1276
1277static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1278{
1279 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1280
1281 if (!HAS_L3_DPF(dev))
1282 return;
1283
1284 spin_lock(&dev_priv->irq_lock);
1285 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1286 spin_unlock(&dev_priv->irq_lock);
1287
1288 iir &= GT_PARITY_ERROR(dev);
1289 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1290 dev_priv->l3_parity.which_slice |= 1 << 1;
1291
1292 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1293 dev_priv->l3_parity.which_slice |= 1 << 0;
1294
1295 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1296}
1297
1298static void ilk_gt_irq_handler(struct drm_device *dev,
1299 struct drm_i915_private *dev_priv,
1300 u32 gt_iir)
1301{
1302 if (gt_iir &
1303 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1304 notify_ring(dev, &dev_priv->ring[RCS]);
1305 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1306 notify_ring(dev, &dev_priv->ring[VCS]);
1307}
1308
1309static void snb_gt_irq_handler(struct drm_device *dev,
1310 struct drm_i915_private *dev_priv,
1311 u32 gt_iir)
1312{
1313
1314 if (gt_iir &
1315 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1316 notify_ring(dev, &dev_priv->ring[RCS]);
1317 if (gt_iir & GT_BSD_USER_INTERRUPT)
1318 notify_ring(dev, &dev_priv->ring[VCS]);
1319 if (gt_iir & GT_BLT_USER_INTERRUPT)
1320 notify_ring(dev, &dev_priv->ring[BCS]);
1321
1322 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1323 GT_BSD_CS_ERROR_INTERRUPT |
1324 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1325 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1326 gt_iir);
1327 }
1328
1329 if (gt_iir & GT_PARITY_ERROR(dev))
1330 ivybridge_parity_error_irq_handler(dev, gt_iir);
1331}
1332
1333static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1334 struct drm_i915_private *dev_priv,
1335 u32 master_ctl)
1336{
1337 u32 rcs, bcs, vcs;
1338 uint32_t tmp = 0;
1339 irqreturn_t ret = IRQ_NONE;
1340
1341 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1342 tmp = I915_READ(GEN8_GT_IIR(0));
1343 if (tmp) {
1344 ret = IRQ_HANDLED;
1345 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1346 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1347 if (rcs & GT_RENDER_USER_INTERRUPT)
1348 notify_ring(dev, &dev_priv->ring[RCS]);
1349 if (bcs & GT_RENDER_USER_INTERRUPT)
1350 notify_ring(dev, &dev_priv->ring[BCS]);
1351 I915_WRITE(GEN8_GT_IIR(0), tmp);
1352 } else
1353 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1354 }
1355
1356 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1357 tmp = I915_READ(GEN8_GT_IIR(1));
1358 if (tmp) {
1359 ret = IRQ_HANDLED;
1360 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1361 if (vcs & GT_RENDER_USER_INTERRUPT)
1362 notify_ring(dev, &dev_priv->ring[VCS]);
1363 I915_WRITE(GEN8_GT_IIR(1), tmp);
1364 } else
1365 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1366 }
1367
1368 if (master_ctl & GEN8_GT_VECS_IRQ) {
1369 tmp = I915_READ(GEN8_GT_IIR(3));
1370 if (tmp) {
1371 ret = IRQ_HANDLED;
1372 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1373 if (vcs & GT_RENDER_USER_INTERRUPT)
1374 notify_ring(dev, &dev_priv->ring[VECS]);
1375 I915_WRITE(GEN8_GT_IIR(3), tmp);
1376 } else
1377 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1378 }
1379
1380 return ret;
1381}
1382
1383#define HPD_STORM_DETECT_PERIOD 1000
1384#define HPD_STORM_THRESHOLD 5
1385
1386static inline void intel_hpd_irq_handler(struct drm_device *dev,
1387 u32 hotplug_trigger,
1388 const u32 *hpd)
1389{
1390 drm_i915_private_t *dev_priv = dev->dev_private;
1391 int i;
1392 bool storm_detected = false;
1393
1394 if (!hotplug_trigger)
1395 return;
1396
1397 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1398 hotplug_trigger);
1399
1400 spin_lock(&dev_priv->irq_lock);
1401 for (i = 1; i < HPD_NUM_PINS; i++) {
1402
1403 WARN_ONCE(hpd[i] & hotplug_trigger &&
1404 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1405 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1406 hotplug_trigger, i, hpd[i]);
1407
1408 if (!(hpd[i] & hotplug_trigger) ||
1409 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1410 continue;
1411
1412 dev_priv->hpd_event_bits |= (1 << i);
1413 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1414 dev_priv->hpd_stats[i].hpd_last_jiffies
1415 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1416 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1417 dev_priv->hpd_stats[i].hpd_cnt = 0;
1418 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1419 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1420 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1421 dev_priv->hpd_event_bits &= ~(1 << i);
1422 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1423 storm_detected = true;
1424 } else {
1425 dev_priv->hpd_stats[i].hpd_cnt++;
1426 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1427 dev_priv->hpd_stats[i].hpd_cnt);
1428 }
1429 }
1430
1431 if (storm_detected)
1432 dev_priv->display.hpd_irq_setup(dev);
1433 spin_unlock(&dev_priv->irq_lock);
1434
1435 /*
1436 * Our hotplug handler can grab modeset locks (by calling down into the
1437 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1438 * queue for otherwise the flush_work in the pageflip code will
1439 * deadlock.
1440 */
1441 schedule_work(&dev_priv->hotplug_work);
1442}
1443
1444static void gmbus_irq_handler(struct drm_device *dev)
1445{
1446 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1447
1448 wake_up_all(&dev_priv->gmbus_wait_queue);
1449}
1450
1451static void dp_aux_irq_handler(struct drm_device *dev)
1452{
1453 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1454
1455 wake_up_all(&dev_priv->gmbus_wait_queue);
1456}
1457
1458#if defined(CONFIG_DEBUG_FS)
1459static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1460 uint32_t crc0, uint32_t crc1,
1461 uint32_t crc2, uint32_t crc3,
1462 uint32_t crc4)
1463{
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1466 struct intel_pipe_crc_entry *entry;
1467 int head, tail;
1468
1469 spin_lock(&pipe_crc->lock);
1470
1471 if (!pipe_crc->entries) {
1472 spin_unlock(&pipe_crc->lock);
1473 DRM_ERROR("spurious interrupt\n");
1474 return;
1475 }
1476
1477 head = pipe_crc->head;
1478 tail = pipe_crc->tail;
1479
1480 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1481 spin_unlock(&pipe_crc->lock);
1482 DRM_ERROR("CRC buffer overflowing\n");
1483 return;
1484 }
1485
1486 entry = &pipe_crc->entries[head];
1487
1488 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1489 entry->crc[0] = crc0;
1490 entry->crc[1] = crc1;
1491 entry->crc[2] = crc2;
1492 entry->crc[3] = crc3;
1493 entry->crc[4] = crc4;
1494
1495 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1496 pipe_crc->head = head;
1497
1498 spin_unlock(&pipe_crc->lock);
1499
1500 wake_up_interruptible(&pipe_crc->wq);
1501}
1502#else
1503static inline void
1504display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1505 uint32_t crc0, uint32_t crc1,
1506 uint32_t crc2, uint32_t crc3,
1507 uint32_t crc4) {}
1508#endif
1509
1510
1511static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1512{
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514
1515 display_pipe_crc_irq_handler(dev, pipe,
1516 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1517 0, 0, 0, 0);
1518}
1519
1520static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1521{
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523
1524 display_pipe_crc_irq_handler(dev, pipe,
1525 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1526 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1527 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1528 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1529 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1530}
1531
1532static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1533{
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 uint32_t res1, res2;
1536
1537 if (INTEL_INFO(dev)->gen >= 3)
1538 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1539 else
1540 res1 = 0;
1541
1542 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1543 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1544 else
1545 res2 = 0;
1546
1547 display_pipe_crc_irq_handler(dev, pipe,
1548 I915_READ(PIPE_CRC_RES_RED(pipe)),
1549 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1550 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1551 res1, res2);
1552}
1553
1554/* The RPS events need forcewake, so we add them to a work queue and mask their
1555 * IMR bits until the work is done. Other interrupts can be processed without
1556 * the work queue. */
1557static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1558{
1559 if (pm_iir & dev_priv->pm_rps_events) {
1560 spin_lock(&dev_priv->irq_lock);
1561 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1562 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1563 spin_unlock(&dev_priv->irq_lock);
1564
1565 queue_work(dev_priv->wq, &dev_priv->rps.work);
1566 }
1567
1568 if (HAS_VEBOX(dev_priv->dev)) {
1569 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1570 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1571
1572 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1573 i915_handle_error(dev_priv->dev, false,
1574 "VEBOX CS error interrupt 0x%08x",
1575 pm_iir);
1576 }
1577 }
1578}
1579
1580static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1581{
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 u32 pipe_stats[I915_MAX_PIPES] = { };
1584 int pipe;
1585
1586 spin_lock(&dev_priv->irq_lock);
1587 for_each_pipe(pipe) {
1588 int reg;
1589 u32 mask, iir_bit = 0;
1590
1591 /*
1592 * PIPESTAT bits get signalled even when the interrupt is
1593 * disabled with the mask bits, and some of the status bits do
1594 * not generate interrupts at all (like the underrun bit). Hence
1595 * we need to be careful that we only handle what we want to
1596 * handle.
1597 */
1598 mask = 0;
1599 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1600 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1601
1602 switch (pipe) {
1603 case PIPE_A:
1604 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1605 break;
1606 case PIPE_B:
1607 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1608 break;
1609 }
1610 if (iir & iir_bit)
1611 mask |= dev_priv->pipestat_irq_mask[pipe];
1612
1613 if (!mask)
1614 continue;
1615
1616 reg = PIPESTAT(pipe);
1617 mask |= PIPESTAT_INT_ENABLE_MASK;
1618 pipe_stats[pipe] = I915_READ(reg) & mask;
1619
1620 /*
1621 * Clear the PIPE*STAT regs before the IIR
1622 */
1623 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1624 PIPESTAT_INT_STATUS_MASK))
1625 I915_WRITE(reg, pipe_stats[pipe]);
1626 }
1627 spin_unlock(&dev_priv->irq_lock);
1628
1629 for_each_pipe(pipe) {
1630 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1631 drm_handle_vblank(dev, pipe);
1632
1633 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1634 intel_prepare_page_flip(dev, pipe);
1635 intel_finish_page_flip(dev, pipe);
1636 }
1637
1638 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1639 i9xx_pipe_crc_irq_handler(dev, pipe);
1640
1641 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1642 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1643 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1644 }
1645
1646 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1647 gmbus_irq_handler(dev);
1648}
1649
1650static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1651{
1652 struct drm_device *dev = (struct drm_device *) arg;
1653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1654 u32 iir, gt_iir, pm_iir;
1655 irqreturn_t ret = IRQ_NONE;
1656
1657 while (true) {
1658 iir = I915_READ(VLV_IIR);
1659 gt_iir = I915_READ(GTIIR);
1660 pm_iir = I915_READ(GEN6_PMIIR);
1661
1662 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1663 goto out;
1664
1665 ret = IRQ_HANDLED;
1666
1667 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1668
1669 valleyview_pipestat_irq_handler(dev, iir);
1670
1671 /* Consume port. Then clear IIR or we'll miss events */
1672 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1673 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1674 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1675
1676 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1677
1678 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1679 dp_aux_irq_handler(dev);
1680
1681 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1682 I915_READ(PORT_HOTPLUG_STAT);
1683 }
1684
1685
1686 if (pm_iir)
1687 gen6_rps_irq_handler(dev_priv, pm_iir);
1688
1689 I915_WRITE(GTIIR, gt_iir);
1690 I915_WRITE(GEN6_PMIIR, pm_iir);
1691 I915_WRITE(VLV_IIR, iir);
1692 }
1693
1694out:
1695 return ret;
1696}
1697
1698static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1699{
1700 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1701 int pipe;
1702 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1703
1704 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1705
1706 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1707 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1708 SDE_AUDIO_POWER_SHIFT);
1709 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1710 port_name(port));
1711 }
1712
1713 if (pch_iir & SDE_AUX_MASK)
1714 dp_aux_irq_handler(dev);
1715
1716 if (pch_iir & SDE_GMBUS)
1717 gmbus_irq_handler(dev);
1718
1719 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1720 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1721
1722 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1723 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1724
1725 if (pch_iir & SDE_POISON)
1726 DRM_ERROR("PCH poison interrupt\n");
1727
1728 if (pch_iir & SDE_FDI_MASK)
1729 for_each_pipe(pipe)
1730 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1731 pipe_name(pipe),
1732 I915_READ(FDI_RX_IIR(pipe)));
1733
1734 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1735 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1736
1737 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1738 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1739
1740 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1741 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1742 false))
1743 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1744
1745 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1746 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1747 false))
1748 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1749}
1750
1751static void ivb_err_int_handler(struct drm_device *dev)
1752{
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 u32 err_int = I915_READ(GEN7_ERR_INT);
1755 enum pipe pipe;
1756
1757 if (err_int & ERR_INT_POISON)
1758 DRM_ERROR("Poison interrupt\n");
1759
1760 for_each_pipe(pipe) {
1761 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1762 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1763 false))
1764 DRM_ERROR("Pipe %c FIFO underrun\n",
1765 pipe_name(pipe));
1766 }
1767
1768 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1769 if (IS_IVYBRIDGE(dev))
1770 ivb_pipe_crc_irq_handler(dev, pipe);
1771 else
1772 hsw_pipe_crc_irq_handler(dev, pipe);
1773 }
1774 }
1775
1776 I915_WRITE(GEN7_ERR_INT, err_int);
1777}
1778
1779static void cpt_serr_int_handler(struct drm_device *dev)
1780{
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 u32 serr_int = I915_READ(SERR_INT);
1783
1784 if (serr_int & SERR_INT_POISON)
1785 DRM_ERROR("PCH poison interrupt\n");
1786
1787 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1788 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1789 false))
1790 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1791
1792 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1793 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1794 false))
1795 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1796
1797 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1798 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1799 false))
1800 DRM_ERROR("PCH transcoder C FIFO underrun\n");
1801
1802 I915_WRITE(SERR_INT, serr_int);
1803}
1804
1805static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1806{
1807 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1808 int pipe;
1809 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1810
1811 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1812
1813 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1814 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1815 SDE_AUDIO_POWER_SHIFT_CPT);
1816 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1817 port_name(port));
1818 }
1819
1820 if (pch_iir & SDE_AUX_MASK_CPT)
1821 dp_aux_irq_handler(dev);
1822
1823 if (pch_iir & SDE_GMBUS_CPT)
1824 gmbus_irq_handler(dev);
1825
1826 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1827 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1828
1829 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1830 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1831
1832 if (pch_iir & SDE_FDI_MASK_CPT)
1833 for_each_pipe(pipe)
1834 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1835 pipe_name(pipe),
1836 I915_READ(FDI_RX_IIR(pipe)));
1837
1838 if (pch_iir & SDE_ERROR_CPT)
1839 cpt_serr_int_handler(dev);
1840}
1841
1842static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1843{
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 enum pipe pipe;
1846
1847 if (de_iir & DE_AUX_CHANNEL_A)
1848 dp_aux_irq_handler(dev);
1849
1850 if (de_iir & DE_GSE)
1851 intel_opregion_asle_intr(dev);
1852
1853 if (de_iir & DE_POISON)
1854 DRM_ERROR("Poison interrupt\n");
1855
1856 for_each_pipe(pipe) {
1857 if (de_iir & DE_PIPE_VBLANK(pipe))
1858 drm_handle_vblank(dev, pipe);
1859
1860 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1861 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1862 DRM_ERROR("Pipe %c FIFO underrun\n",
1863 pipe_name(pipe));
1864
1865 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1866 i9xx_pipe_crc_irq_handler(dev, pipe);
1867
1868 /* plane/pipes map 1:1 on ilk+ */
1869 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1870 intel_prepare_page_flip(dev, pipe);
1871 intel_finish_page_flip_plane(dev, pipe);
1872 }
1873 }
1874
1875 /* check event from PCH */
1876 if (de_iir & DE_PCH_EVENT) {
1877 u32 pch_iir = I915_READ(SDEIIR);
1878
1879 if (HAS_PCH_CPT(dev))
1880 cpt_irq_handler(dev, pch_iir);
1881 else
1882 ibx_irq_handler(dev, pch_iir);
1883
1884 /* should clear PCH hotplug event before clear CPU irq */
1885 I915_WRITE(SDEIIR, pch_iir);
1886 }
1887
1888 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1889 ironlake_rps_change_irq_handler(dev);
1890}
1891
1892static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1893{
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 enum pipe pipe;
1896
1897 if (de_iir & DE_ERR_INT_IVB)
1898 ivb_err_int_handler(dev);
1899
1900 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1901 dp_aux_irq_handler(dev);
1902
1903 if (de_iir & DE_GSE_IVB)
1904 intel_opregion_asle_intr(dev);
1905
1906 for_each_pipe(pipe) {
1907 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1908 drm_handle_vblank(dev, pipe);
1909
1910 /* plane/pipes map 1:1 on ilk+ */
1911 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1912 intel_prepare_page_flip(dev, pipe);
1913 intel_finish_page_flip_plane(dev, pipe);
1914 }
1915 }
1916
1917 /* check event from PCH */
1918 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1919 u32 pch_iir = I915_READ(SDEIIR);
1920
1921 cpt_irq_handler(dev, pch_iir);
1922
1923 /* clear PCH hotplug event before clear CPU irq */
1924 I915_WRITE(SDEIIR, pch_iir);
1925 }
1926}
1927
1928static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1929{
1930 struct drm_device *dev = (struct drm_device *) arg;
1931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1932 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1933 irqreturn_t ret = IRQ_NONE;
1934
1935 /* We get interrupts on unclaimed registers, so check for this before we
1936 * do any I915_{READ,WRITE}. */
1937 intel_uncore_check_errors(dev);
1938
1939 /* disable master interrupt before clearing iir */
1940 de_ier = I915_READ(DEIER);
1941 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1942 POSTING_READ(DEIER);
1943
1944 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1945 * interrupts will will be stored on its back queue, and then we'll be
1946 * able to process them after we restore SDEIER (as soon as we restore
1947 * it, we'll get an interrupt if SDEIIR still has something to process
1948 * due to its back queue). */
1949 if (!HAS_PCH_NOP(dev)) {
1950 sde_ier = I915_READ(SDEIER);
1951 I915_WRITE(SDEIER, 0);
1952 POSTING_READ(SDEIER);
1953 }
1954
1955 gt_iir = I915_READ(GTIIR);
1956 if (gt_iir) {
1957 if (INTEL_INFO(dev)->gen >= 6)
1958 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1959 else
1960 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1961 I915_WRITE(GTIIR, gt_iir);
1962 ret = IRQ_HANDLED;
1963 }
1964
1965 de_iir = I915_READ(DEIIR);
1966 if (de_iir) {
1967 if (INTEL_INFO(dev)->gen >= 7)
1968 ivb_display_irq_handler(dev, de_iir);
1969 else
1970 ilk_display_irq_handler(dev, de_iir);
1971 I915_WRITE(DEIIR, de_iir);
1972 ret = IRQ_HANDLED;
1973 }
1974
1975 if (INTEL_INFO(dev)->gen >= 6) {
1976 u32 pm_iir = I915_READ(GEN6_PMIIR);
1977 if (pm_iir) {
1978 gen6_rps_irq_handler(dev_priv, pm_iir);
1979 I915_WRITE(GEN6_PMIIR, pm_iir);
1980 ret = IRQ_HANDLED;
1981 }
1982 }
1983
1984 I915_WRITE(DEIER, de_ier);
1985 POSTING_READ(DEIER);
1986 if (!HAS_PCH_NOP(dev)) {
1987 I915_WRITE(SDEIER, sde_ier);
1988 POSTING_READ(SDEIER);
1989 }
1990
1991 return ret;
1992}
1993
1994static irqreturn_t gen8_irq_handler(int irq, void *arg)
1995{
1996 struct drm_device *dev = arg;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 u32 master_ctl;
1999 irqreturn_t ret = IRQ_NONE;
2000 uint32_t tmp = 0;
2001 enum pipe pipe;
2002
2003 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2004 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2005 if (!master_ctl)
2006 return IRQ_NONE;
2007
2008 I915_WRITE(GEN8_MASTER_IRQ, 0);
2009 POSTING_READ(GEN8_MASTER_IRQ);
2010
2011 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2012
2013 if (master_ctl & GEN8_DE_MISC_IRQ) {
2014 tmp = I915_READ(GEN8_DE_MISC_IIR);
2015 if (tmp & GEN8_DE_MISC_GSE)
2016 intel_opregion_asle_intr(dev);
2017 else if (tmp)
2018 DRM_ERROR("Unexpected DE Misc interrupt\n");
2019 else
2020 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2021
2022 if (tmp) {
2023 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2024 ret = IRQ_HANDLED;
2025 }
2026 }
2027
2028 if (master_ctl & GEN8_DE_PORT_IRQ) {
2029 tmp = I915_READ(GEN8_DE_PORT_IIR);
2030 if (tmp & GEN8_AUX_CHANNEL_A)
2031 dp_aux_irq_handler(dev);
2032 else if (tmp)
2033 DRM_ERROR("Unexpected DE Port interrupt\n");
2034 else
2035 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2036
2037 if (tmp) {
2038 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2039 ret = IRQ_HANDLED;
2040 }
2041 }
2042
2043 for_each_pipe(pipe) {
2044 uint32_t pipe_iir;
2045
2046 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2047 continue;
2048
2049 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2050 if (pipe_iir & GEN8_PIPE_VBLANK)
2051 drm_handle_vblank(dev, pipe);
2052
2053 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2054 intel_prepare_page_flip(dev, pipe);
2055 intel_finish_page_flip_plane(dev, pipe);
2056 }
2057
2058 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2059 hsw_pipe_crc_irq_handler(dev, pipe);
2060
2061 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2062 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2063 false))
2064 DRM_ERROR("Pipe %c FIFO underrun\n",
2065 pipe_name(pipe));
2066 }
2067
2068 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2069 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2070 pipe_name(pipe),
2071 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2072 }
2073
2074 if (pipe_iir) {
2075 ret = IRQ_HANDLED;
2076 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2077 } else
2078 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2079 }
2080
2081 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2082 /*
2083 * FIXME(BDW): Assume for now that the new interrupt handling
2084 * scheme also closed the SDE interrupt handling race we've seen
2085 * on older pch-split platforms. But this needs testing.
2086 */
2087 u32 pch_iir = I915_READ(SDEIIR);
2088
2089 cpt_irq_handler(dev, pch_iir);
2090
2091 if (pch_iir) {
2092 I915_WRITE(SDEIIR, pch_iir);
2093 ret = IRQ_HANDLED;
2094 }
2095 }
2096
2097 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2098 POSTING_READ(GEN8_MASTER_IRQ);
2099
2100 return ret;
2101}
2102
2103static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2104 bool reset_completed)
2105{
2106 struct intel_ring_buffer *ring;
2107 int i;
2108
2109 /*
2110 * Notify all waiters for GPU completion events that reset state has
2111 * been changed, and that they need to restart their wait after
2112 * checking for potential errors (and bail out to drop locks if there is
2113 * a gpu reset pending so that i915_error_work_func can acquire them).
2114 */
2115
2116 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2117 for_each_ring(ring, dev_priv, i)
2118 wake_up_all(&ring->irq_queue);
2119
2120 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2121 wake_up_all(&dev_priv->pending_flip_queue);
2122
2123 /*
2124 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2125 * reset state is cleared.
2126 */
2127 if (reset_completed)
2128 wake_up_all(&dev_priv->gpu_error.reset_queue);
2129}
2130
2131/**
2132 * i915_error_work_func - do process context error handling work
2133 * @work: work struct
2134 *
2135 * Fire an error uevent so userspace can see that a hang or error
2136 * was detected.
2137 */
2138static void i915_error_work_func(struct work_struct *work)
2139{
2140 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2141 work);
2142 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
2143 gpu_error);
2144 struct drm_device *dev = dev_priv->dev;
2145 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2146 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2147 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2148 int ret;
2149
2150 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2151
2152 /*
2153 * Note that there's only one work item which does gpu resets, so we
2154 * need not worry about concurrent gpu resets potentially incrementing
2155 * error->reset_counter twice. We only need to take care of another
2156 * racing irq/hangcheck declaring the gpu dead for a second time. A
2157 * quick check for that is good enough: schedule_work ensures the
2158 * correct ordering between hang detection and this work item, and since
2159 * the reset in-progress bit is only ever set by code outside of this
2160 * work we don't need to worry about any other races.
2161 */
2162 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2163 DRM_DEBUG_DRIVER("resetting chip\n");
2164 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2165 reset_event);
2166
2167 /*
2168 * All state reset _must_ be completed before we update the
2169 * reset counter, for otherwise waiters might miss the reset
2170 * pending state and not properly drop locks, resulting in
2171 * deadlocks with the reset work.
2172 */
2173 ret = i915_reset(dev);
2174
2175 intel_display_handle_reset(dev);
2176
2177 if (ret == 0) {
2178 /*
2179 * After all the gem state is reset, increment the reset
2180 * counter and wake up everyone waiting for the reset to
2181 * complete.
2182 *
2183 * Since unlock operations are a one-sided barrier only,
2184 * we need to insert a barrier here to order any seqno
2185 * updates before
2186 * the counter increment.
2187 */
2188 smp_mb__before_atomic_inc();
2189 atomic_inc(&dev_priv->gpu_error.reset_counter);
2190
2191 kobject_uevent_env(&dev->primary->kdev->kobj,
2192 KOBJ_CHANGE, reset_done_event);
2193 } else {
2194 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2195 }
2196
2197 /*
2198 * Note: The wake_up also serves as a memory barrier so that
2199 * waiters see the update value of the reset counter atomic_t.
2200 */
2201 i915_error_wake_up(dev_priv, true);
2202 }
2203}
2204
2205static void i915_report_and_clear_eir(struct drm_device *dev)
2206{
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 uint32_t instdone[I915_NUM_INSTDONE_REG];
2209 u32 eir = I915_READ(EIR);
2210 int pipe, i;
2211
2212 if (!eir)
2213 return;
2214
2215 pr_err("render error detected, EIR: 0x%08x\n", eir);
2216
2217 i915_get_extra_instdone(dev, instdone);
2218
2219 if (IS_G4X(dev)) {
2220 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2221 u32 ipeir = I915_READ(IPEIR_I965);
2222
2223 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2224 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2225 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2226 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2227 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2228 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2229 I915_WRITE(IPEIR_I965, ipeir);
2230 POSTING_READ(IPEIR_I965);
2231 }
2232 if (eir & GM45_ERROR_PAGE_TABLE) {
2233 u32 pgtbl_err = I915_READ(PGTBL_ER);
2234 pr_err("page table error\n");
2235 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2236 I915_WRITE(PGTBL_ER, pgtbl_err);
2237 POSTING_READ(PGTBL_ER);
2238 }
2239 }
2240
2241 if (!IS_GEN2(dev)) {
2242 if (eir & I915_ERROR_PAGE_TABLE) {
2243 u32 pgtbl_err = I915_READ(PGTBL_ER);
2244 pr_err("page table error\n");
2245 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2246 I915_WRITE(PGTBL_ER, pgtbl_err);
2247 POSTING_READ(PGTBL_ER);
2248 }
2249 }
2250
2251 if (eir & I915_ERROR_MEMORY_REFRESH) {
2252 pr_err("memory refresh error:\n");
2253 for_each_pipe(pipe)
2254 pr_err("pipe %c stat: 0x%08x\n",
2255 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2256 /* pipestat has already been acked */
2257 }
2258 if (eir & I915_ERROR_INSTRUCTION) {
2259 pr_err("instruction error\n");
2260 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2261 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2262 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2263 if (INTEL_INFO(dev)->gen < 4) {
2264 u32 ipeir = I915_READ(IPEIR);
2265
2266 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2267 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2268 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2269 I915_WRITE(IPEIR, ipeir);
2270 POSTING_READ(IPEIR);
2271 } else {
2272 u32 ipeir = I915_READ(IPEIR_I965);
2273
2274 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2275 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2276 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2277 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2278 I915_WRITE(IPEIR_I965, ipeir);
2279 POSTING_READ(IPEIR_I965);
2280 }
2281 }
2282
2283 I915_WRITE(EIR, eir);
2284 POSTING_READ(EIR);
2285 eir = I915_READ(EIR);
2286 if (eir) {
2287 /*
2288 * some errors might have become stuck,
2289 * mask them.
2290 */
2291 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2292 I915_WRITE(EMR, I915_READ(EMR) | eir);
2293 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2294 }
2295}
2296
2297/**
2298 * i915_handle_error - handle an error interrupt
2299 * @dev: drm device
2300 *
2301 * Do some basic checking of regsiter state at error interrupt time and
2302 * dump it to the syslog. Also call i915_capture_error_state() to make
2303 * sure we get a record and make it available in debugfs. Fire a uevent
2304 * so userspace knows something bad happened (should trigger collection
2305 * of a ring dump etc.).
2306 */
2307void i915_handle_error(struct drm_device *dev, bool wedged,
2308 const char *fmt, ...)
2309{
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 va_list args;
2312 char error_msg[80];
2313
2314 va_start(args, fmt);
2315 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2316 va_end(args);
2317
2318 i915_capture_error_state(dev, wedged, error_msg);
2319 i915_report_and_clear_eir(dev);
2320
2321 if (wedged) {
2322 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2323 &dev_priv->gpu_error.reset_counter);
2324
2325 /*
2326 * Wakeup waiting processes so that the reset work function
2327 * i915_error_work_func doesn't deadlock trying to grab various
2328 * locks. By bumping the reset counter first, the woken
2329 * processes will see a reset in progress and back off,
2330 * releasing their locks and then wait for the reset completion.
2331 * We must do this for _all_ gpu waiters that might hold locks
2332 * that the reset work needs to acquire.
2333 *
2334 * Note: The wake_up serves as the required memory barrier to
2335 * ensure that the waiters see the updated value of the reset
2336 * counter atomic_t.
2337 */
2338 i915_error_wake_up(dev_priv, false);
2339 }
2340
2341 /*
2342 * Our reset work can grab modeset locks (since it needs to reset the
2343 * state of outstanding pagelips). Hence it must not be run on our own
2344 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2345 * code will deadlock.
2346 */
2347 schedule_work(&dev_priv->gpu_error.work);
2348}
2349
2350static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2351{
2352 drm_i915_private_t *dev_priv = dev->dev_private;
2353 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355 struct drm_i915_gem_object *obj;
2356 struct intel_unpin_work *work;
2357 unsigned long flags;
2358 bool stall_detected;
2359
2360 /* Ignore early vblank irqs */
2361 if (intel_crtc == NULL)
2362 return;
2363
2364 spin_lock_irqsave(&dev->event_lock, flags);
2365 work = intel_crtc->unpin_work;
2366
2367 if (work == NULL ||
2368 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2369 !work->enable_stall_check) {
2370 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2371 spin_unlock_irqrestore(&dev->event_lock, flags);
2372 return;
2373 }
2374
2375 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2376 obj = work->pending_flip_obj;
2377 if (INTEL_INFO(dev)->gen >= 4) {
2378 int dspsurf = DSPSURF(intel_crtc->plane);
2379 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2380 i915_gem_obj_ggtt_offset(obj);
2381 } else {
2382 int dspaddr = DSPADDR(intel_crtc->plane);
2383 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2384 crtc->y * crtc->fb->pitches[0] +
2385 crtc->x * crtc->fb->bits_per_pixel/8);
2386 }
2387
2388 spin_unlock_irqrestore(&dev->event_lock, flags);
2389
2390 if (stall_detected) {
2391 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2392 intel_prepare_page_flip(dev, intel_crtc->plane);
2393 }
2394}
2395
2396/* Called from drm generic code, passed 'crtc' which
2397 * we use as a pipe index
2398 */
2399static int i915_enable_vblank(struct drm_device *dev, int pipe)
2400{
2401 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2402 unsigned long irqflags;
2403
2404 if (!i915_pipe_enabled(dev, pipe))
2405 return -EINVAL;
2406
2407 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2408 if (INTEL_INFO(dev)->gen >= 4)
2409 i915_enable_pipestat(dev_priv, pipe,
2410 PIPE_START_VBLANK_INTERRUPT_STATUS);
2411 else
2412 i915_enable_pipestat(dev_priv, pipe,
2413 PIPE_VBLANK_INTERRUPT_STATUS);
2414
2415 /* maintain vblank delivery even in deep C-states */
2416 if (INTEL_INFO(dev)->gen == 3)
2417 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2418 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2419
2420 return 0;
2421}
2422
2423static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2424{
2425 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2426 unsigned long irqflags;
2427 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2428 DE_PIPE_VBLANK(pipe);
2429
2430 if (!i915_pipe_enabled(dev, pipe))
2431 return -EINVAL;
2432
2433 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2434 ironlake_enable_display_irq(dev_priv, bit);
2435 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2436
2437 return 0;
2438}
2439
2440static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2441{
2442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2443 unsigned long irqflags;
2444
2445 if (!i915_pipe_enabled(dev, pipe))
2446 return -EINVAL;
2447
2448 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2449 i915_enable_pipestat(dev_priv, pipe,
2450 PIPE_START_VBLANK_INTERRUPT_STATUS);
2451 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2452
2453 return 0;
2454}
2455
2456static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2457{
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 unsigned long irqflags;
2460
2461 if (!i915_pipe_enabled(dev, pipe))
2462 return -EINVAL;
2463
2464 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2465 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2466 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2467 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2468 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2469 return 0;
2470}
2471
2472/* Called from drm generic code, passed 'crtc' which
2473 * we use as a pipe index
2474 */
2475static void i915_disable_vblank(struct drm_device *dev, int pipe)
2476{
2477 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2478 unsigned long irqflags;
2479
2480 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2481 if (INTEL_INFO(dev)->gen == 3)
2482 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2483
2484 i915_disable_pipestat(dev_priv, pipe,
2485 PIPE_VBLANK_INTERRUPT_STATUS |
2486 PIPE_START_VBLANK_INTERRUPT_STATUS);
2487 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2488}
2489
2490static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2491{
2492 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2493 unsigned long irqflags;
2494 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2495 DE_PIPE_VBLANK(pipe);
2496
2497 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2498 ironlake_disable_display_irq(dev_priv, bit);
2499 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2500}
2501
2502static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2503{
2504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2505 unsigned long irqflags;
2506
2507 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2508 i915_disable_pipestat(dev_priv, pipe,
2509 PIPE_START_VBLANK_INTERRUPT_STATUS);
2510 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2511}
2512
2513static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2514{
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 unsigned long irqflags;
2517
2518 if (!i915_pipe_enabled(dev, pipe))
2519 return;
2520
2521 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2522 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2523 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2524 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2525 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2526}
2527
2528static u32
2529ring_last_seqno(struct intel_ring_buffer *ring)
2530{
2531 return list_entry(ring->request_list.prev,
2532 struct drm_i915_gem_request, list)->seqno;
2533}
2534
2535static bool
2536ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2537{
2538 return (list_empty(&ring->request_list) ||
2539 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2540}
2541
2542static struct intel_ring_buffer *
2543semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2544{
2545 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2546 u32 cmd, ipehr, head;
2547 int i;
2548
2549 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2550 if ((ipehr & ~(0x3 << 16)) !=
2551 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2552 return NULL;
2553
2554 /*
2555 * HEAD is likely pointing to the dword after the actual command,
2556 * so scan backwards until we find the MBOX. But limit it to just 3
2557 * dwords. Note that we don't care about ACTHD here since that might
2558 * point at at batch, and semaphores are always emitted into the
2559 * ringbuffer itself.
2560 */
2561 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2562
2563 for (i = 4; i; --i) {
2564 /*
2565 * Be paranoid and presume the hw has gone off into the wild -
2566 * our ring is smaller than what the hardware (and hence
2567 * HEAD_ADDR) allows. Also handles wrap-around.
2568 */
2569 head &= ring->size - 1;
2570
2571 /* This here seems to blow up */
2572 cmd = ioread32(ring->virtual_start + head);
2573 if (cmd == ipehr)
2574 break;
2575
2576 head -= 4;
2577 }
2578
2579 if (!i)
2580 return NULL;
2581
2582 *seqno = ioread32(ring->virtual_start + head + 4) + 1;
2583 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2584}
2585
2586static int semaphore_passed(struct intel_ring_buffer *ring)
2587{
2588 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2589 struct intel_ring_buffer *signaller;
2590 u32 seqno, ctl;
2591
2592 ring->hangcheck.deadlock = true;
2593
2594 signaller = semaphore_waits_for(ring, &seqno);
2595 if (signaller == NULL || signaller->hangcheck.deadlock)
2596 return -1;
2597
2598 /* cursory check for an unkickable deadlock */
2599 ctl = I915_READ_CTL(signaller);
2600 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2601 return -1;
2602
2603 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2604}
2605
2606static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2607{
2608 struct intel_ring_buffer *ring;
2609 int i;
2610
2611 for_each_ring(ring, dev_priv, i)
2612 ring->hangcheck.deadlock = false;
2613}
2614
2615static enum intel_ring_hangcheck_action
2616ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
2617{
2618 struct drm_device *dev = ring->dev;
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 u32 tmp;
2621
2622 if (ring->hangcheck.acthd != acthd)
2623 return HANGCHECK_ACTIVE;
2624
2625 if (IS_GEN2(dev))
2626 return HANGCHECK_HUNG;
2627
2628 /* Is the chip hanging on a WAIT_FOR_EVENT?
2629 * If so we can simply poke the RB_WAIT bit
2630 * and break the hang. This should work on
2631 * all but the second generation chipsets.
2632 */
2633 tmp = I915_READ_CTL(ring);
2634 if (tmp & RING_WAIT) {
2635 i915_handle_error(dev, false,
2636 "Kicking stuck wait on %s",
2637 ring->name);
2638 I915_WRITE_CTL(ring, tmp);
2639 return HANGCHECK_KICK;
2640 }
2641
2642 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2643 switch (semaphore_passed(ring)) {
2644 default:
2645 return HANGCHECK_HUNG;
2646 case 1:
2647 i915_handle_error(dev, false,
2648 "Kicking stuck semaphore on %s",
2649 ring->name);
2650 I915_WRITE_CTL(ring, tmp);
2651 return HANGCHECK_KICK;
2652 case 0:
2653 return HANGCHECK_WAIT;
2654 }
2655 }
2656
2657 return HANGCHECK_HUNG;
2658}
2659
2660/**
2661 * This is called when the chip hasn't reported back with completed
2662 * batchbuffers in a long time. We keep track per ring seqno progress and
2663 * if there are no progress, hangcheck score for that ring is increased.
2664 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2665 * we kick the ring. If we see no progress on three subsequent calls
2666 * we assume chip is wedged and try to fix it by resetting the chip.
2667 */
2668static void i915_hangcheck_elapsed(unsigned long data)
2669{
2670 struct drm_device *dev = (struct drm_device *)data;
2671 drm_i915_private_t *dev_priv = dev->dev_private;
2672 struct intel_ring_buffer *ring;
2673 int i;
2674 int busy_count = 0, rings_hung = 0;
2675 bool stuck[I915_NUM_RINGS] = { 0 };
2676#define BUSY 1
2677#define KICK 5
2678#define HUNG 20
2679
2680 if (!i915.enable_hangcheck)
2681 return;
2682
2683 for_each_ring(ring, dev_priv, i) {
2684 u64 acthd;
2685 u32 seqno;
2686 bool busy = true;
2687
2688 semaphore_clear_deadlocks(dev_priv);
2689
2690 seqno = ring->get_seqno(ring, false);
2691 acthd = intel_ring_get_active_head(ring);
2692
2693 if (ring->hangcheck.seqno == seqno) {
2694 if (ring_idle(ring, seqno)) {
2695 ring->hangcheck.action = HANGCHECK_IDLE;
2696
2697 if (waitqueue_active(&ring->irq_queue)) {
2698 /* Issue a wake-up to catch stuck h/w. */
2699 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2700 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2701 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2702 ring->name);
2703 else
2704 DRM_INFO("Fake missed irq on %s\n",
2705 ring->name);
2706 wake_up_all(&ring->irq_queue);
2707 }
2708 /* Safeguard against driver failure */
2709 ring->hangcheck.score += BUSY;
2710 } else
2711 busy = false;
2712 } else {
2713 /* We always increment the hangcheck score
2714 * if the ring is busy and still processing
2715 * the same request, so that no single request
2716 * can run indefinitely (such as a chain of
2717 * batches). The only time we do not increment
2718 * the hangcheck score on this ring, if this
2719 * ring is in a legitimate wait for another
2720 * ring. In that case the waiting ring is a
2721 * victim and we want to be sure we catch the
2722 * right culprit. Then every time we do kick
2723 * the ring, add a small increment to the
2724 * score so that we can catch a batch that is
2725 * being repeatedly kicked and so responsible
2726 * for stalling the machine.
2727 */
2728 ring->hangcheck.action = ring_stuck(ring,
2729 acthd);
2730
2731 switch (ring->hangcheck.action) {
2732 case HANGCHECK_IDLE:
2733 case HANGCHECK_WAIT:
2734 break;
2735 case HANGCHECK_ACTIVE:
2736 ring->hangcheck.score += BUSY;
2737 break;
2738 case HANGCHECK_KICK:
2739 ring->hangcheck.score += KICK;
2740 break;
2741 case HANGCHECK_HUNG:
2742 ring->hangcheck.score += HUNG;
2743 stuck[i] = true;
2744 break;
2745 }
2746 }
2747 } else {
2748 ring->hangcheck.action = HANGCHECK_ACTIVE;
2749
2750 /* Gradually reduce the count so that we catch DoS
2751 * attempts across multiple batches.
2752 */
2753 if (ring->hangcheck.score > 0)
2754 ring->hangcheck.score--;
2755 }
2756
2757 ring->hangcheck.seqno = seqno;
2758 ring->hangcheck.acthd = acthd;
2759 busy_count += busy;
2760 }
2761
2762 for_each_ring(ring, dev_priv, i) {
2763 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2764 DRM_INFO("%s on %s\n",
2765 stuck[i] ? "stuck" : "no progress",
2766 ring->name);
2767 rings_hung++;
2768 }
2769 }
2770
2771 if (rings_hung)
2772 return i915_handle_error(dev, true, "Ring hung");
2773
2774 if (busy_count)
2775 /* Reset timer case chip hangs without another request
2776 * being added */
2777 i915_queue_hangcheck(dev);
2778}
2779
2780void i915_queue_hangcheck(struct drm_device *dev)
2781{
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783 if (!i915.enable_hangcheck)
2784 return;
2785
2786 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2787 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2788}
2789
2790static void ibx_irq_preinstall(struct drm_device *dev)
2791{
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793
2794 if (HAS_PCH_NOP(dev))
2795 return;
2796
2797 /* south display irq */
2798 I915_WRITE(SDEIMR, 0xffffffff);
2799 /*
2800 * SDEIER is also touched by the interrupt handler to work around missed
2801 * PCH interrupts. Hence we can't update it after the interrupt handler
2802 * is enabled - instead we unconditionally enable all PCH interrupt
2803 * sources here, but then only unmask them as needed with SDEIMR.
2804 */
2805 I915_WRITE(SDEIER, 0xffffffff);
2806 POSTING_READ(SDEIER);
2807}
2808
2809static void gen5_gt_irq_preinstall(struct drm_device *dev)
2810{
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812
2813 /* and GT */
2814 I915_WRITE(GTIMR, 0xffffffff);
2815 I915_WRITE(GTIER, 0x0);
2816 POSTING_READ(GTIER);
2817
2818 if (INTEL_INFO(dev)->gen >= 6) {
2819 /* and PM */
2820 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2821 I915_WRITE(GEN6_PMIER, 0x0);
2822 POSTING_READ(GEN6_PMIER);
2823 }
2824}
2825
2826/* drm_dma.h hooks
2827*/
2828static void ironlake_irq_preinstall(struct drm_device *dev)
2829{
2830 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2831
2832 I915_WRITE(HWSTAM, 0xeffe);
2833
2834 I915_WRITE(DEIMR, 0xffffffff);
2835 I915_WRITE(DEIER, 0x0);
2836 POSTING_READ(DEIER);
2837
2838 gen5_gt_irq_preinstall(dev);
2839
2840 ibx_irq_preinstall(dev);
2841}
2842
2843static void valleyview_irq_preinstall(struct drm_device *dev)
2844{
2845 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2846 int pipe;
2847
2848 /* VLV magic */
2849 I915_WRITE(VLV_IMR, 0);
2850 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2851 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2852 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2853
2854 /* and GT */
2855 I915_WRITE(GTIIR, I915_READ(GTIIR));
2856 I915_WRITE(GTIIR, I915_READ(GTIIR));
2857
2858 gen5_gt_irq_preinstall(dev);
2859
2860 I915_WRITE(DPINVGTT, 0xff);
2861
2862 I915_WRITE(PORT_HOTPLUG_EN, 0);
2863 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2864 for_each_pipe(pipe)
2865 I915_WRITE(PIPESTAT(pipe), 0xffff);
2866 I915_WRITE(VLV_IIR, 0xffffffff);
2867 I915_WRITE(VLV_IMR, 0xffffffff);
2868 I915_WRITE(VLV_IER, 0x0);
2869 POSTING_READ(VLV_IER);
2870}
2871
2872static void gen8_irq_preinstall(struct drm_device *dev)
2873{
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 int pipe;
2876
2877 I915_WRITE(GEN8_MASTER_IRQ, 0);
2878 POSTING_READ(GEN8_MASTER_IRQ);
2879
2880 /* IIR can theoretically queue up two events. Be paranoid */
2881#define GEN8_IRQ_INIT_NDX(type, which) do { \
2882 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2883 POSTING_READ(GEN8_##type##_IMR(which)); \
2884 I915_WRITE(GEN8_##type##_IER(which), 0); \
2885 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2886 POSTING_READ(GEN8_##type##_IIR(which)); \
2887 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2888 } while (0)
2889
2890#define GEN8_IRQ_INIT(type) do { \
2891 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2892 POSTING_READ(GEN8_##type##_IMR); \
2893 I915_WRITE(GEN8_##type##_IER, 0); \
2894 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2895 POSTING_READ(GEN8_##type##_IIR); \
2896 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2897 } while (0)
2898
2899 GEN8_IRQ_INIT_NDX(GT, 0);
2900 GEN8_IRQ_INIT_NDX(GT, 1);
2901 GEN8_IRQ_INIT_NDX(GT, 2);
2902 GEN8_IRQ_INIT_NDX(GT, 3);
2903
2904 for_each_pipe(pipe) {
2905 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2906 }
2907
2908 GEN8_IRQ_INIT(DE_PORT);
2909 GEN8_IRQ_INIT(DE_MISC);
2910 GEN8_IRQ_INIT(PCU);
2911#undef GEN8_IRQ_INIT
2912#undef GEN8_IRQ_INIT_NDX
2913
2914 POSTING_READ(GEN8_PCU_IIR);
2915
2916 ibx_irq_preinstall(dev);
2917}
2918
2919static void ibx_hpd_irq_setup(struct drm_device *dev)
2920{
2921 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2922 struct drm_mode_config *mode_config = &dev->mode_config;
2923 struct intel_encoder *intel_encoder;
2924 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2925
2926 if (HAS_PCH_IBX(dev)) {
2927 hotplug_irqs = SDE_HOTPLUG_MASK;
2928 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2929 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2930 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2931 } else {
2932 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2933 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2934 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2935 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2936 }
2937
2938 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2939
2940 /*
2941 * Enable digital hotplug on the PCH, and configure the DP short pulse
2942 * duration to 2ms (which is the minimum in the Display Port spec)
2943 *
2944 * This register is the same on all known PCH chips.
2945 */
2946 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2947 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2948 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2949 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2950 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2951 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2952}
2953
2954static void ibx_irq_postinstall(struct drm_device *dev)
2955{
2956 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2957 u32 mask;
2958
2959 if (HAS_PCH_NOP(dev))
2960 return;
2961
2962 if (HAS_PCH_IBX(dev)) {
2963 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
2964 } else {
2965 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2966
2967 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2968 }
2969
2970 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2971 I915_WRITE(SDEIMR, ~mask);
2972}
2973
2974static void gen5_gt_irq_postinstall(struct drm_device *dev)
2975{
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 u32 pm_irqs, gt_irqs;
2978
2979 pm_irqs = gt_irqs = 0;
2980
2981 dev_priv->gt_irq_mask = ~0;
2982 if (HAS_L3_DPF(dev)) {
2983 /* L3 parity interrupt is always unmasked. */
2984 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2985 gt_irqs |= GT_PARITY_ERROR(dev);
2986 }
2987
2988 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2989 if (IS_GEN5(dev)) {
2990 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2991 ILK_BSD_USER_INTERRUPT;
2992 } else {
2993 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2994 }
2995
2996 I915_WRITE(GTIIR, I915_READ(GTIIR));
2997 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2998 I915_WRITE(GTIER, gt_irqs);
2999 POSTING_READ(GTIER);
3000
3001 if (INTEL_INFO(dev)->gen >= 6) {
3002 pm_irqs |= dev_priv->pm_rps_events;
3003
3004 if (HAS_VEBOX(dev))
3005 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3006
3007 dev_priv->pm_irq_mask = 0xffffffff;
3008 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3009 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
3010 I915_WRITE(GEN6_PMIER, pm_irqs);
3011 POSTING_READ(GEN6_PMIER);
3012 }
3013}
3014
3015static int ironlake_irq_postinstall(struct drm_device *dev)
3016{
3017 unsigned long irqflags;
3018 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3019 u32 display_mask, extra_mask;
3020
3021 if (INTEL_INFO(dev)->gen >= 7) {
3022 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3023 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3024 DE_PLANEB_FLIP_DONE_IVB |
3025 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3026 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3027 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3028
3029 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3030 } else {
3031 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3032 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3033 DE_AUX_CHANNEL_A |
3034 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3035 DE_POISON);
3036 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3037 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3038 }
3039
3040 dev_priv->irq_mask = ~display_mask;
3041
3042 /* should always can generate irq */
3043 I915_WRITE(DEIIR, I915_READ(DEIIR));
3044 I915_WRITE(DEIMR, dev_priv->irq_mask);
3045 I915_WRITE(DEIER, display_mask | extra_mask);
3046 POSTING_READ(DEIER);
3047
3048 gen5_gt_irq_postinstall(dev);
3049
3050 ibx_irq_postinstall(dev);
3051
3052 if (IS_IRONLAKE_M(dev)) {
3053 /* Enable PCU event interrupts
3054 *
3055 * spinlocking not required here for correctness since interrupt
3056 * setup is guaranteed to run in single-threaded context. But we
3057 * need it to make the assert_spin_locked happy. */
3058 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3059 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3060 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3061 }
3062
3063 return 0;
3064}
3065
3066static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3067{
3068 u32 pipestat_mask;
3069 u32 iir_mask;
3070
3071 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3072 PIPE_FIFO_UNDERRUN_STATUS;
3073
3074 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3075 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3076 POSTING_READ(PIPESTAT(PIPE_A));
3077
3078 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3079 PIPE_CRC_DONE_INTERRUPT_STATUS;
3080
3081 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3082 PIPE_GMBUS_INTERRUPT_STATUS);
3083 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3084
3085 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3086 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3087 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3088 dev_priv->irq_mask &= ~iir_mask;
3089
3090 I915_WRITE(VLV_IIR, iir_mask);
3091 I915_WRITE(VLV_IIR, iir_mask);
3092 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3093 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3094 POSTING_READ(VLV_IER);
3095}
3096
3097static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3098{
3099 u32 pipestat_mask;
3100 u32 iir_mask;
3101
3102 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3103 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3104 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3105
3106 dev_priv->irq_mask |= iir_mask;
3107 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3108 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3109 I915_WRITE(VLV_IIR, iir_mask);
3110 I915_WRITE(VLV_IIR, iir_mask);
3111 POSTING_READ(VLV_IIR);
3112
3113 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3114 PIPE_CRC_DONE_INTERRUPT_STATUS;
3115
3116 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3117 PIPE_GMBUS_INTERRUPT_STATUS);
3118 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3119
3120 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3121 PIPE_FIFO_UNDERRUN_STATUS;
3122 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3123 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3124 POSTING_READ(PIPESTAT(PIPE_A));
3125}
3126
3127void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3128{
3129 assert_spin_locked(&dev_priv->irq_lock);
3130
3131 if (dev_priv->display_irqs_enabled)
3132 return;
3133
3134 dev_priv->display_irqs_enabled = true;
3135
3136 if (dev_priv->dev->irq_enabled)
3137 valleyview_display_irqs_install(dev_priv);
3138}
3139
3140void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3141{
3142 assert_spin_locked(&dev_priv->irq_lock);
3143
3144 if (!dev_priv->display_irqs_enabled)
3145 return;
3146
3147 dev_priv->display_irqs_enabled = false;
3148
3149 if (dev_priv->dev->irq_enabled)
3150 valleyview_display_irqs_uninstall(dev_priv);
3151}
3152
3153static int valleyview_irq_postinstall(struct drm_device *dev)
3154{
3155 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3156 unsigned long irqflags;
3157
3158 dev_priv->irq_mask = ~0;
3159
3160 I915_WRITE(PORT_HOTPLUG_EN, 0);
3161 POSTING_READ(PORT_HOTPLUG_EN);
3162
3163 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3164 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3165 I915_WRITE(VLV_IIR, 0xffffffff);
3166 POSTING_READ(VLV_IER);
3167
3168 /* Interrupt setup is already guaranteed to be single-threaded, this is
3169 * just to make the assert_spin_locked check happy. */
3170 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3171 if (dev_priv->display_irqs_enabled)
3172 valleyview_display_irqs_install(dev_priv);
3173 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3174
3175 I915_WRITE(VLV_IIR, 0xffffffff);
3176 I915_WRITE(VLV_IIR, 0xffffffff);
3177
3178 gen5_gt_irq_postinstall(dev);
3179
3180 /* ack & enable invalid PTE error interrupts */
3181#if 0 /* FIXME: add support to irq handler for checking these bits */
3182 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3183 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3184#endif
3185
3186 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3187
3188 return 0;
3189}
3190
3191static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3192{
3193 int i;
3194
3195 /* These are interrupts we'll toggle with the ring mask register */
3196 uint32_t gt_interrupts[] = {
3197 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3198 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3199 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3200 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3201 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3202 0,
3203 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3204 };
3205
3206 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
3207 u32 tmp = I915_READ(GEN8_GT_IIR(i));
3208 if (tmp)
3209 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3210 i, tmp);
3211 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
3212 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
3213 }
3214 POSTING_READ(GEN8_GT_IER(0));
3215}
3216
3217static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3218{
3219 struct drm_device *dev = dev_priv->dev;
3220 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3221 GEN8_PIPE_CDCLK_CRC_DONE |
3222 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3223 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3224 GEN8_PIPE_FIFO_UNDERRUN;
3225 int pipe;
3226 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3227 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3228 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3229
3230 for_each_pipe(pipe) {
3231 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3232 if (tmp)
3233 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3234 pipe, tmp);
3235 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3236 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3237 }
3238 POSTING_READ(GEN8_DE_PIPE_ISR(0));
3239
3240 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3241 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3242 POSTING_READ(GEN8_DE_PORT_IER);
3243}
3244
3245static int gen8_irq_postinstall(struct drm_device *dev)
3246{
3247 struct drm_i915_private *dev_priv = dev->dev_private;
3248
3249 gen8_gt_irq_postinstall(dev_priv);
3250 gen8_de_irq_postinstall(dev_priv);
3251
3252 ibx_irq_postinstall(dev);
3253
3254 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3255 POSTING_READ(GEN8_MASTER_IRQ);
3256
3257 return 0;
3258}
3259
3260static void gen8_irq_uninstall(struct drm_device *dev)
3261{
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3263 int pipe;
3264
3265 if (!dev_priv)
3266 return;
3267
3268 I915_WRITE(GEN8_MASTER_IRQ, 0);
3269
3270#define GEN8_IRQ_FINI_NDX(type, which) do { \
3271 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3272 I915_WRITE(GEN8_##type##_IER(which), 0); \
3273 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3274 } while (0)
3275
3276#define GEN8_IRQ_FINI(type) do { \
3277 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3278 I915_WRITE(GEN8_##type##_IER, 0); \
3279 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3280 } while (0)
3281
3282 GEN8_IRQ_FINI_NDX(GT, 0);
3283 GEN8_IRQ_FINI_NDX(GT, 1);
3284 GEN8_IRQ_FINI_NDX(GT, 2);
3285 GEN8_IRQ_FINI_NDX(GT, 3);
3286
3287 for_each_pipe(pipe) {
3288 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3289 }
3290
3291 GEN8_IRQ_FINI(DE_PORT);
3292 GEN8_IRQ_FINI(DE_MISC);
3293 GEN8_IRQ_FINI(PCU);
3294#undef GEN8_IRQ_FINI
3295#undef GEN8_IRQ_FINI_NDX
3296
3297 POSTING_READ(GEN8_PCU_IIR);
3298}
3299
3300static void valleyview_irq_uninstall(struct drm_device *dev)
3301{
3302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3303 unsigned long irqflags;
3304 int pipe;
3305
3306 if (!dev_priv)
3307 return;
3308
3309 intel_hpd_irq_uninstall(dev_priv);
3310
3311 for_each_pipe(pipe)
3312 I915_WRITE(PIPESTAT(pipe), 0xffff);
3313
3314 I915_WRITE(HWSTAM, 0xffffffff);
3315 I915_WRITE(PORT_HOTPLUG_EN, 0);
3316 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3317
3318 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3319 if (dev_priv->display_irqs_enabled)
3320 valleyview_display_irqs_uninstall(dev_priv);
3321 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3322
3323 dev_priv->irq_mask = 0;
3324
3325 I915_WRITE(VLV_IIR, 0xffffffff);
3326 I915_WRITE(VLV_IMR, 0xffffffff);
3327 I915_WRITE(VLV_IER, 0x0);
3328 POSTING_READ(VLV_IER);
3329}
3330
3331static void ironlake_irq_uninstall(struct drm_device *dev)
3332{
3333 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3334
3335 if (!dev_priv)
3336 return;
3337
3338 intel_hpd_irq_uninstall(dev_priv);
3339
3340 I915_WRITE(HWSTAM, 0xffffffff);
3341
3342 I915_WRITE(DEIMR, 0xffffffff);
3343 I915_WRITE(DEIER, 0x0);
3344 I915_WRITE(DEIIR, I915_READ(DEIIR));
3345 if (IS_GEN7(dev))
3346 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3347
3348 I915_WRITE(GTIMR, 0xffffffff);
3349 I915_WRITE(GTIER, 0x0);
3350 I915_WRITE(GTIIR, I915_READ(GTIIR));
3351
3352 if (HAS_PCH_NOP(dev))
3353 return;
3354
3355 I915_WRITE(SDEIMR, 0xffffffff);
3356 I915_WRITE(SDEIER, 0x0);
3357 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3358 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3359 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3360}
3361
3362static void i8xx_irq_preinstall(struct drm_device * dev)
3363{
3364 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3365 int pipe;
3366
3367 for_each_pipe(pipe)
3368 I915_WRITE(PIPESTAT(pipe), 0);
3369 I915_WRITE16(IMR, 0xffff);
3370 I915_WRITE16(IER, 0x0);
3371 POSTING_READ16(IER);
3372}
3373
3374static int i8xx_irq_postinstall(struct drm_device *dev)
3375{
3376 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3377 unsigned long irqflags;
3378
3379 I915_WRITE16(EMR,
3380 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3381
3382 /* Unmask the interrupts that we always want on. */
3383 dev_priv->irq_mask =
3384 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3385 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3386 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3387 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3388 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3389 I915_WRITE16(IMR, dev_priv->irq_mask);
3390
3391 I915_WRITE16(IER,
3392 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3393 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3394 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3395 I915_USER_INTERRUPT);
3396 POSTING_READ16(IER);
3397
3398 /* Interrupt setup is already guaranteed to be single-threaded, this is
3399 * just to make the assert_spin_locked check happy. */
3400 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3401 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3402 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3403 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3404
3405 return 0;
3406}
3407
3408/*
3409 * Returns true when a page flip has completed.
3410 */
3411static bool i8xx_handle_vblank(struct drm_device *dev,
3412 int plane, int pipe, u32 iir)
3413{
3414 drm_i915_private_t *dev_priv = dev->dev_private;
3415 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3416
3417 if (!drm_handle_vblank(dev, pipe))
3418 return false;
3419
3420 if ((iir & flip_pending) == 0)
3421 return false;
3422
3423 intel_prepare_page_flip(dev, plane);
3424
3425 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3426 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3427 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3428 * the flip is completed (no longer pending). Since this doesn't raise
3429 * an interrupt per se, we watch for the change at vblank.
3430 */
3431 if (I915_READ16(ISR) & flip_pending)
3432 return false;
3433
3434 intel_finish_page_flip(dev, pipe);
3435
3436 return true;
3437}
3438
3439static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3440{
3441 struct drm_device *dev = (struct drm_device *) arg;
3442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3443 u16 iir, new_iir;
3444 u32 pipe_stats[2];
3445 unsigned long irqflags;
3446 int pipe;
3447 u16 flip_mask =
3448 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3449 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3450
3451 iir = I915_READ16(IIR);
3452 if (iir == 0)
3453 return IRQ_NONE;
3454
3455 while (iir & ~flip_mask) {
3456 /* Can't rely on pipestat interrupt bit in iir as it might
3457 * have been cleared after the pipestat interrupt was received.
3458 * It doesn't set the bit in iir again, but it still produces
3459 * interrupts (for non-MSI).
3460 */
3461 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3462 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3463 i915_handle_error(dev, false,
3464 "Command parser error, iir 0x%08x",
3465 iir);
3466
3467 for_each_pipe(pipe) {
3468 int reg = PIPESTAT(pipe);
3469 pipe_stats[pipe] = I915_READ(reg);
3470
3471 /*
3472 * Clear the PIPE*STAT regs before the IIR
3473 */
3474 if (pipe_stats[pipe] & 0x8000ffff)
3475 I915_WRITE(reg, pipe_stats[pipe]);
3476 }
3477 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3478
3479 I915_WRITE16(IIR, iir & ~flip_mask);
3480 new_iir = I915_READ16(IIR); /* Flush posted writes */
3481
3482 i915_update_dri1_breadcrumb(dev);
3483
3484 if (iir & I915_USER_INTERRUPT)
3485 notify_ring(dev, &dev_priv->ring[RCS]);
3486
3487 for_each_pipe(pipe) {
3488 int plane = pipe;
3489 if (HAS_FBC(dev))
3490 plane = !plane;
3491
3492 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3493 i8xx_handle_vblank(dev, plane, pipe, iir))
3494 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3495
3496 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3497 i9xx_pipe_crc_irq_handler(dev, pipe);
3498
3499 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3500 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3501 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3502 }
3503
3504 iir = new_iir;
3505 }
3506
3507 return IRQ_HANDLED;
3508}
3509
3510static void i8xx_irq_uninstall(struct drm_device * dev)
3511{
3512 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3513 int pipe;
3514
3515 for_each_pipe(pipe) {
3516 /* Clear enable bits; then clear status bits */
3517 I915_WRITE(PIPESTAT(pipe), 0);
3518 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3519 }
3520 I915_WRITE16(IMR, 0xffff);
3521 I915_WRITE16(IER, 0x0);
3522 I915_WRITE16(IIR, I915_READ16(IIR));
3523}
3524
3525static void i915_irq_preinstall(struct drm_device * dev)
3526{
3527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3528 int pipe;
3529
3530 if (I915_HAS_HOTPLUG(dev)) {
3531 I915_WRITE(PORT_HOTPLUG_EN, 0);
3532 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3533 }
3534
3535 I915_WRITE16(HWSTAM, 0xeffe);
3536 for_each_pipe(pipe)
3537 I915_WRITE(PIPESTAT(pipe), 0);
3538 I915_WRITE(IMR, 0xffffffff);
3539 I915_WRITE(IER, 0x0);
3540 POSTING_READ(IER);
3541}
3542
3543static int i915_irq_postinstall(struct drm_device *dev)
3544{
3545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3546 u32 enable_mask;
3547 unsigned long irqflags;
3548
3549 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3550
3551 /* Unmask the interrupts that we always want on. */
3552 dev_priv->irq_mask =
3553 ~(I915_ASLE_INTERRUPT |
3554 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3555 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3556 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3557 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3558 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3559
3560 enable_mask =
3561 I915_ASLE_INTERRUPT |
3562 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3563 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3564 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3565 I915_USER_INTERRUPT;
3566
3567 if (I915_HAS_HOTPLUG(dev)) {
3568 I915_WRITE(PORT_HOTPLUG_EN, 0);
3569 POSTING_READ(PORT_HOTPLUG_EN);
3570
3571 /* Enable in IER... */
3572 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3573 /* and unmask in IMR */
3574 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3575 }
3576
3577 I915_WRITE(IMR, dev_priv->irq_mask);
3578 I915_WRITE(IER, enable_mask);
3579 POSTING_READ(IER);
3580
3581 i915_enable_asle_pipestat(dev);
3582
3583 /* Interrupt setup is already guaranteed to be single-threaded, this is
3584 * just to make the assert_spin_locked check happy. */
3585 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3586 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3587 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3588 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3589
3590 return 0;
3591}
3592
3593/*
3594 * Returns true when a page flip has completed.
3595 */
3596static bool i915_handle_vblank(struct drm_device *dev,
3597 int plane, int pipe, u32 iir)
3598{
3599 drm_i915_private_t *dev_priv = dev->dev_private;
3600 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3601
3602 if (!drm_handle_vblank(dev, pipe))
3603 return false;
3604
3605 if ((iir & flip_pending) == 0)
3606 return false;
3607
3608 intel_prepare_page_flip(dev, plane);
3609
3610 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3611 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3612 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3613 * the flip is completed (no longer pending). Since this doesn't raise
3614 * an interrupt per se, we watch for the change at vblank.
3615 */
3616 if (I915_READ(ISR) & flip_pending)
3617 return false;
3618
3619 intel_finish_page_flip(dev, pipe);
3620
3621 return true;
3622}
3623
3624static irqreturn_t i915_irq_handler(int irq, void *arg)
3625{
3626 struct drm_device *dev = (struct drm_device *) arg;
3627 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3628 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3629 unsigned long irqflags;
3630 u32 flip_mask =
3631 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3632 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3633 int pipe, ret = IRQ_NONE;
3634
3635 iir = I915_READ(IIR);
3636 do {
3637 bool irq_received = (iir & ~flip_mask) != 0;
3638 bool blc_event = false;
3639
3640 /* Can't rely on pipestat interrupt bit in iir as it might
3641 * have been cleared after the pipestat interrupt was received.
3642 * It doesn't set the bit in iir again, but it still produces
3643 * interrupts (for non-MSI).
3644 */
3645 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3646 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3647 i915_handle_error(dev, false,
3648 "Command parser error, iir 0x%08x",
3649 iir);
3650
3651 for_each_pipe(pipe) {
3652 int reg = PIPESTAT(pipe);
3653 pipe_stats[pipe] = I915_READ(reg);
3654
3655 /* Clear the PIPE*STAT regs before the IIR */
3656 if (pipe_stats[pipe] & 0x8000ffff) {
3657 I915_WRITE(reg, pipe_stats[pipe]);
3658 irq_received = true;
3659 }
3660 }
3661 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3662
3663 if (!irq_received)
3664 break;
3665
3666 /* Consume port. Then clear IIR or we'll miss events */
3667 if ((I915_HAS_HOTPLUG(dev)) &&
3668 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3669 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3670 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3671
3672 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3673
3674 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3675 POSTING_READ(PORT_HOTPLUG_STAT);
3676 }
3677
3678 I915_WRITE(IIR, iir & ~flip_mask);
3679 new_iir = I915_READ(IIR); /* Flush posted writes */
3680
3681 if (iir & I915_USER_INTERRUPT)
3682 notify_ring(dev, &dev_priv->ring[RCS]);
3683
3684 for_each_pipe(pipe) {
3685 int plane = pipe;
3686 if (HAS_FBC(dev))
3687 plane = !plane;
3688
3689 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3690 i915_handle_vblank(dev, plane, pipe, iir))
3691 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3692
3693 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3694 blc_event = true;
3695
3696 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3697 i9xx_pipe_crc_irq_handler(dev, pipe);
3698
3699 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3700 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3701 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3702 }
3703
3704 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3705 intel_opregion_asle_intr(dev);
3706
3707 /* With MSI, interrupts are only generated when iir
3708 * transitions from zero to nonzero. If another bit got
3709 * set while we were handling the existing iir bits, then
3710 * we would never get another interrupt.
3711 *
3712 * This is fine on non-MSI as well, as if we hit this path
3713 * we avoid exiting the interrupt handler only to generate
3714 * another one.
3715 *
3716 * Note that for MSI this could cause a stray interrupt report
3717 * if an interrupt landed in the time between writing IIR and
3718 * the posting read. This should be rare enough to never
3719 * trigger the 99% of 100,000 interrupts test for disabling
3720 * stray interrupts.
3721 */
3722 ret = IRQ_HANDLED;
3723 iir = new_iir;
3724 } while (iir & ~flip_mask);
3725
3726 i915_update_dri1_breadcrumb(dev);
3727
3728 return ret;
3729}
3730
3731static void i915_irq_uninstall(struct drm_device * dev)
3732{
3733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3734 int pipe;
3735
3736 intel_hpd_irq_uninstall(dev_priv);
3737
3738 if (I915_HAS_HOTPLUG(dev)) {
3739 I915_WRITE(PORT_HOTPLUG_EN, 0);
3740 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3741 }
3742
3743 I915_WRITE16(HWSTAM, 0xffff);
3744 for_each_pipe(pipe) {
3745 /* Clear enable bits; then clear status bits */
3746 I915_WRITE(PIPESTAT(pipe), 0);
3747 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3748 }
3749 I915_WRITE(IMR, 0xffffffff);
3750 I915_WRITE(IER, 0x0);
3751
3752 I915_WRITE(IIR, I915_READ(IIR));
3753}
3754
3755static void i965_irq_preinstall(struct drm_device * dev)
3756{
3757 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3758 int pipe;
3759
3760 I915_WRITE(PORT_HOTPLUG_EN, 0);
3761 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3762
3763 I915_WRITE(HWSTAM, 0xeffe);
3764 for_each_pipe(pipe)
3765 I915_WRITE(PIPESTAT(pipe), 0);
3766 I915_WRITE(IMR, 0xffffffff);
3767 I915_WRITE(IER, 0x0);
3768 POSTING_READ(IER);
3769}
3770
3771static int i965_irq_postinstall(struct drm_device *dev)
3772{
3773 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3774 u32 enable_mask;
3775 u32 error_mask;
3776 unsigned long irqflags;
3777
3778 /* Unmask the interrupts that we always want on. */
3779 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3780 I915_DISPLAY_PORT_INTERRUPT |
3781 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3782 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3783 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3784 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3785 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3786
3787 enable_mask = ~dev_priv->irq_mask;
3788 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3789 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3790 enable_mask |= I915_USER_INTERRUPT;
3791
3792 if (IS_G4X(dev))
3793 enable_mask |= I915_BSD_USER_INTERRUPT;
3794
3795 /* Interrupt setup is already guaranteed to be single-threaded, this is
3796 * just to make the assert_spin_locked check happy. */
3797 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3798 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3799 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3800 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3801 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3802
3803 /*
3804 * Enable some error detection, note the instruction error mask
3805 * bit is reserved, so we leave it masked.
3806 */
3807 if (IS_G4X(dev)) {
3808 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3809 GM45_ERROR_MEM_PRIV |
3810 GM45_ERROR_CP_PRIV |
3811 I915_ERROR_MEMORY_REFRESH);
3812 } else {
3813 error_mask = ~(I915_ERROR_PAGE_TABLE |
3814 I915_ERROR_MEMORY_REFRESH);
3815 }
3816 I915_WRITE(EMR, error_mask);
3817
3818 I915_WRITE(IMR, dev_priv->irq_mask);
3819 I915_WRITE(IER, enable_mask);
3820 POSTING_READ(IER);
3821
3822 I915_WRITE(PORT_HOTPLUG_EN, 0);
3823 POSTING_READ(PORT_HOTPLUG_EN);
3824
3825 i915_enable_asle_pipestat(dev);
3826
3827 return 0;
3828}
3829
3830static void i915_hpd_irq_setup(struct drm_device *dev)
3831{
3832 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3833 struct drm_mode_config *mode_config = &dev->mode_config;
3834 struct intel_encoder *intel_encoder;
3835 u32 hotplug_en;
3836
3837 assert_spin_locked(&dev_priv->irq_lock);
3838
3839 if (I915_HAS_HOTPLUG(dev)) {
3840 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3841 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3842 /* Note HDMI and DP share hotplug bits */
3843 /* enable bits are the same for all generations */
3844 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3845 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3846 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3847 /* Programming the CRT detection parameters tends
3848 to generate a spurious hotplug event about three
3849 seconds later. So just do it once.
3850 */
3851 if (IS_G4X(dev))
3852 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3853 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3854 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3855
3856 /* Ignore TV since it's buggy */
3857 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3858 }
3859}
3860
3861static irqreturn_t i965_irq_handler(int irq, void *arg)
3862{
3863 struct drm_device *dev = (struct drm_device *) arg;
3864 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3865 u32 iir, new_iir;
3866 u32 pipe_stats[I915_MAX_PIPES];
3867 unsigned long irqflags;
3868 int ret = IRQ_NONE, pipe;
3869 u32 flip_mask =
3870 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3871 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3872
3873 iir = I915_READ(IIR);
3874
3875 for (;;) {
3876 bool irq_received = (iir & ~flip_mask) != 0;
3877 bool blc_event = false;
3878
3879 /* Can't rely on pipestat interrupt bit in iir as it might
3880 * have been cleared after the pipestat interrupt was received.
3881 * It doesn't set the bit in iir again, but it still produces
3882 * interrupts (for non-MSI).
3883 */
3884 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3885 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3886 i915_handle_error(dev, false,
3887 "Command parser error, iir 0x%08x",
3888 iir);
3889
3890 for_each_pipe(pipe) {
3891 int reg = PIPESTAT(pipe);
3892 pipe_stats[pipe] = I915_READ(reg);
3893
3894 /*
3895 * Clear the PIPE*STAT regs before the IIR
3896 */
3897 if (pipe_stats[pipe] & 0x8000ffff) {
3898 I915_WRITE(reg, pipe_stats[pipe]);
3899 irq_received = true;
3900 }
3901 }
3902 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3903
3904 if (!irq_received)
3905 break;
3906
3907 ret = IRQ_HANDLED;
3908
3909 /* Consume port. Then clear IIR or we'll miss events */
3910 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3911 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3912 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3913 HOTPLUG_INT_STATUS_G4X :
3914 HOTPLUG_INT_STATUS_I915);
3915
3916 intel_hpd_irq_handler(dev, hotplug_trigger,
3917 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3918
3919 if (IS_G4X(dev) &&
3920 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3921 dp_aux_irq_handler(dev);
3922
3923 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3924 I915_READ(PORT_HOTPLUG_STAT);
3925 }
3926
3927 I915_WRITE(IIR, iir & ~flip_mask);
3928 new_iir = I915_READ(IIR); /* Flush posted writes */
3929
3930 if (iir & I915_USER_INTERRUPT)
3931 notify_ring(dev, &dev_priv->ring[RCS]);
3932 if (iir & I915_BSD_USER_INTERRUPT)
3933 notify_ring(dev, &dev_priv->ring[VCS]);
3934
3935 for_each_pipe(pipe) {
3936 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3937 i915_handle_vblank(dev, pipe, pipe, iir))
3938 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3939
3940 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3941 blc_event = true;
3942
3943 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3944 i9xx_pipe_crc_irq_handler(dev, pipe);
3945
3946 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3947 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3948 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3949 }
3950
3951 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3952 intel_opregion_asle_intr(dev);
3953
3954 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3955 gmbus_irq_handler(dev);
3956
3957 /* With MSI, interrupts are only generated when iir
3958 * transitions from zero to nonzero. If another bit got
3959 * set while we were handling the existing iir bits, then
3960 * we would never get another interrupt.
3961 *
3962 * This is fine on non-MSI as well, as if we hit this path
3963 * we avoid exiting the interrupt handler only to generate
3964 * another one.
3965 *
3966 * Note that for MSI this could cause a stray interrupt report
3967 * if an interrupt landed in the time between writing IIR and
3968 * the posting read. This should be rare enough to never
3969 * trigger the 99% of 100,000 interrupts test for disabling
3970 * stray interrupts.
3971 */
3972 iir = new_iir;
3973 }
3974
3975 i915_update_dri1_breadcrumb(dev);
3976
3977 return ret;
3978}
3979
3980static void i965_irq_uninstall(struct drm_device * dev)
3981{
3982 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3983 int pipe;
3984
3985 if (!dev_priv)
3986 return;
3987
3988 intel_hpd_irq_uninstall(dev_priv);
3989
3990 I915_WRITE(PORT_HOTPLUG_EN, 0);
3991 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3992
3993 I915_WRITE(HWSTAM, 0xffffffff);
3994 for_each_pipe(pipe)
3995 I915_WRITE(PIPESTAT(pipe), 0);
3996 I915_WRITE(IMR, 0xffffffff);
3997 I915_WRITE(IER, 0x0);
3998
3999 for_each_pipe(pipe)
4000 I915_WRITE(PIPESTAT(pipe),
4001 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4002 I915_WRITE(IIR, I915_READ(IIR));
4003}
4004
4005static void intel_hpd_irq_reenable(unsigned long data)
4006{
4007 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
4008 struct drm_device *dev = dev_priv->dev;
4009 struct drm_mode_config *mode_config = &dev->mode_config;
4010 unsigned long irqflags;
4011 int i;
4012
4013 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4014 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4015 struct drm_connector *connector;
4016
4017 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4018 continue;
4019
4020 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4021
4022 list_for_each_entry(connector, &mode_config->connector_list, head) {
4023 struct intel_connector *intel_connector = to_intel_connector(connector);
4024
4025 if (intel_connector->encoder->hpd_pin == i) {
4026 if (connector->polled != intel_connector->polled)
4027 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4028 drm_get_connector_name(connector));
4029 connector->polled = intel_connector->polled;
4030 if (!connector->polled)
4031 connector->polled = DRM_CONNECTOR_POLL_HPD;
4032 }
4033 }
4034 }
4035 if (dev_priv->display.hpd_irq_setup)
4036 dev_priv->display.hpd_irq_setup(dev);
4037 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4038}
4039
4040void intel_irq_init(struct drm_device *dev)
4041{
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043
4044 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4045 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4046 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4047 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4048
4049 /* Let's track the enabled rps events */
4050 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4051
4052 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4053 i915_hangcheck_elapsed,
4054 (unsigned long) dev);
4055 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4056 (unsigned long) dev_priv);
4057
4058 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4059
4060 if (IS_GEN2(dev)) {
4061 dev->max_vblank_count = 0;
4062 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4063 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4064 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4065 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4066 } else {
4067 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4068 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4069 }
4070
4071 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4072 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4073 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4074 }
4075
4076 if (IS_VALLEYVIEW(dev)) {
4077 dev->driver->irq_handler = valleyview_irq_handler;
4078 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4079 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4080 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4081 dev->driver->enable_vblank = valleyview_enable_vblank;
4082 dev->driver->disable_vblank = valleyview_disable_vblank;
4083 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4084 } else if (IS_GEN8(dev)) {
4085 dev->driver->irq_handler = gen8_irq_handler;
4086 dev->driver->irq_preinstall = gen8_irq_preinstall;
4087 dev->driver->irq_postinstall = gen8_irq_postinstall;
4088 dev->driver->irq_uninstall = gen8_irq_uninstall;
4089 dev->driver->enable_vblank = gen8_enable_vblank;
4090 dev->driver->disable_vblank = gen8_disable_vblank;
4091 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4092 } else if (HAS_PCH_SPLIT(dev)) {
4093 dev->driver->irq_handler = ironlake_irq_handler;
4094 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4095 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4096 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4097 dev->driver->enable_vblank = ironlake_enable_vblank;
4098 dev->driver->disable_vblank = ironlake_disable_vblank;
4099 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4100 } else {
4101 if (INTEL_INFO(dev)->gen == 2) {
4102 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4103 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4104 dev->driver->irq_handler = i8xx_irq_handler;
4105 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4106 } else if (INTEL_INFO(dev)->gen == 3) {
4107 dev->driver->irq_preinstall = i915_irq_preinstall;
4108 dev->driver->irq_postinstall = i915_irq_postinstall;
4109 dev->driver->irq_uninstall = i915_irq_uninstall;
4110 dev->driver->irq_handler = i915_irq_handler;
4111 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4112 } else {
4113 dev->driver->irq_preinstall = i965_irq_preinstall;
4114 dev->driver->irq_postinstall = i965_irq_postinstall;
4115 dev->driver->irq_uninstall = i965_irq_uninstall;
4116 dev->driver->irq_handler = i965_irq_handler;
4117 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4118 }
4119 dev->driver->enable_vblank = i915_enable_vblank;
4120 dev->driver->disable_vblank = i915_disable_vblank;
4121 }
4122}
4123
4124void intel_hpd_init(struct drm_device *dev)
4125{
4126 struct drm_i915_private *dev_priv = dev->dev_private;
4127 struct drm_mode_config *mode_config = &dev->mode_config;
4128 struct drm_connector *connector;
4129 unsigned long irqflags;
4130 int i;
4131
4132 for (i = 1; i < HPD_NUM_PINS; i++) {
4133 dev_priv->hpd_stats[i].hpd_cnt = 0;
4134 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4135 }
4136 list_for_each_entry(connector, &mode_config->connector_list, head) {
4137 struct intel_connector *intel_connector = to_intel_connector(connector);
4138 connector->polled = intel_connector->polled;
4139 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4140 connector->polled = DRM_CONNECTOR_POLL_HPD;
4141 }
4142
4143 /* Interrupt setup is already guaranteed to be single-threaded, this is
4144 * just to make the assert_spin_locked checks happy. */
4145 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4146 if (dev_priv->display.hpd_irq_setup)
4147 dev_priv->display.hpd_irq_setup(dev);
4148 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4149}
4150
4151/* Disable interrupts so we can allow runtime PM. */
4152void hsw_runtime_pm_disable_interrupts(struct drm_device *dev)
4153{
4154 struct drm_i915_private *dev_priv = dev->dev_private;
4155 unsigned long irqflags;
4156
4157 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4158
4159 dev_priv->pm.regsave.deimr = I915_READ(DEIMR);
4160 dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR);
4161 dev_priv->pm.regsave.gtimr = I915_READ(GTIMR);
4162 dev_priv->pm.regsave.gtier = I915_READ(GTIER);
4163 dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
4164
4165 ironlake_disable_display_irq(dev_priv, 0xffffffff);
4166 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4167 ilk_disable_gt_irq(dev_priv, 0xffffffff);
4168 snb_disable_pm_irq(dev_priv, 0xffffffff);
4169
4170 dev_priv->pm.irqs_disabled = true;
4171
4172 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4173}
4174
4175/* Restore interrupts so we can recover from runtime PM. */
4176void hsw_runtime_pm_restore_interrupts(struct drm_device *dev)
4177{
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 unsigned long irqflags;
4180 uint32_t val;
4181
4182 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4183
4184 val = I915_READ(DEIMR);
4185 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
4186
4187 val = I915_READ(SDEIMR);
4188 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
4189
4190 val = I915_READ(GTIMR);
4191 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
4192
4193 val = I915_READ(GEN6_PMIMR);
4194 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4195
4196 dev_priv->pm.irqs_disabled = false;
4197
4198 ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr);
4199 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr);
4200 ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr);
4201 snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr);
4202 I915_WRITE(GTIER, dev_priv->pm.regsave.gtier);
4203
4204 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4205}
Linux kernel - Deliverables
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