| 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
| 2 | */ |
| 3 | /* |
| 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "i915_drm.h" |
| 32 | #include "i915_drv.h" |
| 33 | |
| 34 | #define MAX_NOPID ((u32)~0) |
| 35 | |
| 36 | /** These are the interrupts used by the driver */ |
| 37 | #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \ |
| 38 | I915_ASLE_INTERRUPT | \ |
| 39 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 40 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) |
| 41 | |
| 42 | void |
| 43 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 44 | { |
| 45 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 46 | dev_priv->irq_mask_reg &= ~mask; |
| 47 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 48 | (void) I915_READ(IMR); |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | static inline void |
| 53 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 54 | { |
| 55 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 56 | dev_priv->irq_mask_reg |= mask; |
| 57 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 58 | (void) I915_READ(IMR); |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | /** |
| 63 | * i915_get_pipe - return the the pipe associated with a given plane |
| 64 | * @dev: DRM device |
| 65 | * @plane: plane to look for |
| 66 | * |
| 67 | * The Intel Mesa & 2D drivers call the vblank routines with a plane number |
| 68 | * rather than a pipe number, since they may not always be equal. This routine |
| 69 | * maps the given @plane back to a pipe number. |
| 70 | */ |
| 71 | static int |
| 72 | i915_get_pipe(struct drm_device *dev, int plane) |
| 73 | { |
| 74 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 75 | u32 dspcntr; |
| 76 | |
| 77 | dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR); |
| 78 | |
| 79 | return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0; |
| 80 | } |
| 81 | |
| 82 | /** |
| 83 | * i915_get_plane - return the the plane associated with a given pipe |
| 84 | * @dev: DRM device |
| 85 | * @pipe: pipe to look for |
| 86 | * |
| 87 | * The Intel Mesa & 2D drivers call the vblank routines with a plane number |
| 88 | * rather than a plane number, since they may not always be equal. This routine |
| 89 | * maps the given @pipe back to a plane number. |
| 90 | */ |
| 91 | static int |
| 92 | i915_get_plane(struct drm_device *dev, int pipe) |
| 93 | { |
| 94 | if (i915_get_pipe(dev, 0) == pipe) |
| 95 | return 0; |
| 96 | return 1; |
| 97 | } |
| 98 | |
| 99 | /** |
| 100 | * i915_pipe_enabled - check if a pipe is enabled |
| 101 | * @dev: DRM device |
| 102 | * @pipe: pipe to check |
| 103 | * |
| 104 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 105 | * Use this routine to make sure the PLL is running and the pipe is active |
| 106 | * before reading such registers if unsure. |
| 107 | */ |
| 108 | static int |
| 109 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 110 | { |
| 111 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 112 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; |
| 113 | |
| 114 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) |
| 115 | return 1; |
| 116 | |
| 117 | return 0; |
| 118 | } |
| 119 | |
| 120 | /** |
| 121 | * Emit blits for scheduled buffer swaps. |
| 122 | * |
| 123 | * This function will be called with the HW lock held. |
| 124 | */ |
| 125 | static void i915_vblank_tasklet(struct drm_device *dev) |
| 126 | { |
| 127 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 128 | unsigned long irqflags; |
| 129 | struct list_head *list, *tmp, hits, *hit; |
| 130 | int nhits, nrects, slice[2], upper[2], lower[2], i; |
| 131 | unsigned counter[2]; |
| 132 | struct drm_drawable_info *drw; |
| 133 | drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; |
| 134 | u32 cpp = dev_priv->cpp; |
| 135 | u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD | |
| 136 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 137 | XY_SRC_COPY_BLT_WRITE_RGB) |
| 138 | : XY_SRC_COPY_BLT_CMD; |
| 139 | u32 src_pitch = sarea_priv->pitch * cpp; |
| 140 | u32 dst_pitch = sarea_priv->pitch * cpp; |
| 141 | u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); |
| 142 | RING_LOCALS; |
| 143 | |
| 144 | if (IS_I965G(dev) && sarea_priv->front_tiled) { |
| 145 | cmd |= XY_SRC_COPY_BLT_DST_TILED; |
| 146 | dst_pitch >>= 2; |
| 147 | } |
| 148 | if (IS_I965G(dev) && sarea_priv->back_tiled) { |
| 149 | cmd |= XY_SRC_COPY_BLT_SRC_TILED; |
| 150 | src_pitch >>= 2; |
| 151 | } |
| 152 | |
| 153 | counter[0] = drm_vblank_count(dev, 0); |
| 154 | counter[1] = drm_vblank_count(dev, 1); |
| 155 | |
| 156 | DRM_DEBUG("\n"); |
| 157 | |
| 158 | INIT_LIST_HEAD(&hits); |
| 159 | |
| 160 | nhits = nrects = 0; |
| 161 | |
| 162 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
| 163 | |
| 164 | /* Find buffer swaps scheduled for this vertical blank */ |
| 165 | list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) { |
| 166 | drm_i915_vbl_swap_t *vbl_swap = |
| 167 | list_entry(list, drm_i915_vbl_swap_t, head); |
| 168 | int pipe = i915_get_pipe(dev, vbl_swap->plane); |
| 169 | |
| 170 | if ((counter[pipe] - vbl_swap->sequence) > (1<<23)) |
| 171 | continue; |
| 172 | |
| 173 | list_del(list); |
| 174 | dev_priv->swaps_pending--; |
| 175 | drm_vblank_put(dev, pipe); |
| 176 | |
| 177 | spin_unlock(&dev_priv->swaps_lock); |
| 178 | spin_lock(&dev->drw_lock); |
| 179 | |
| 180 | drw = drm_get_drawable_info(dev, vbl_swap->drw_id); |
| 181 | |
| 182 | if (!drw) { |
| 183 | spin_unlock(&dev->drw_lock); |
| 184 | drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER); |
| 185 | spin_lock(&dev_priv->swaps_lock); |
| 186 | continue; |
| 187 | } |
| 188 | |
| 189 | list_for_each(hit, &hits) { |
| 190 | drm_i915_vbl_swap_t *swap_cmp = |
| 191 | list_entry(hit, drm_i915_vbl_swap_t, head); |
| 192 | struct drm_drawable_info *drw_cmp = |
| 193 | drm_get_drawable_info(dev, swap_cmp->drw_id); |
| 194 | |
| 195 | if (drw_cmp && |
| 196 | drw_cmp->rects[0].y1 > drw->rects[0].y1) { |
| 197 | list_add_tail(list, hit); |
| 198 | break; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | spin_unlock(&dev->drw_lock); |
| 203 | |
| 204 | /* List of hits was empty, or we reached the end of it */ |
| 205 | if (hit == &hits) |
| 206 | list_add_tail(list, hits.prev); |
| 207 | |
| 208 | nhits++; |
| 209 | |
| 210 | spin_lock(&dev_priv->swaps_lock); |
| 211 | } |
| 212 | |
| 213 | if (nhits == 0) { |
| 214 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); |
| 215 | return; |
| 216 | } |
| 217 | |
| 218 | spin_unlock(&dev_priv->swaps_lock); |
| 219 | |
| 220 | i915_kernel_lost_context(dev); |
| 221 | |
| 222 | if (IS_I965G(dev)) { |
| 223 | BEGIN_LP_RING(4); |
| 224 | |
| 225 | OUT_RING(GFX_OP_DRAWRECT_INFO_I965); |
| 226 | OUT_RING(0); |
| 227 | OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16)); |
| 228 | OUT_RING(0); |
| 229 | ADVANCE_LP_RING(); |
| 230 | } else { |
| 231 | BEGIN_LP_RING(6); |
| 232 | |
| 233 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
| 234 | OUT_RING(0); |
| 235 | OUT_RING(0); |
| 236 | OUT_RING(sarea_priv->width | sarea_priv->height << 16); |
| 237 | OUT_RING(sarea_priv->width | sarea_priv->height << 16); |
| 238 | OUT_RING(0); |
| 239 | |
| 240 | ADVANCE_LP_RING(); |
| 241 | } |
| 242 | |
| 243 | sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT; |
| 244 | |
| 245 | upper[0] = upper[1] = 0; |
| 246 | slice[0] = max(sarea_priv->pipeA_h / nhits, 1); |
| 247 | slice[1] = max(sarea_priv->pipeB_h / nhits, 1); |
| 248 | lower[0] = sarea_priv->pipeA_y + slice[0]; |
| 249 | lower[1] = sarea_priv->pipeB_y + slice[0]; |
| 250 | |
| 251 | spin_lock(&dev->drw_lock); |
| 252 | |
| 253 | /* Emit blits for buffer swaps, partitioning both outputs into as many |
| 254 | * slices as there are buffer swaps scheduled in order to avoid tearing |
| 255 | * (based on the assumption that a single buffer swap would always |
| 256 | * complete before scanout starts). |
| 257 | */ |
| 258 | for (i = 0; i++ < nhits; |
| 259 | upper[0] = lower[0], lower[0] += slice[0], |
| 260 | upper[1] = lower[1], lower[1] += slice[1]) { |
| 261 | if (i == nhits) |
| 262 | lower[0] = lower[1] = sarea_priv->height; |
| 263 | |
| 264 | list_for_each(hit, &hits) { |
| 265 | drm_i915_vbl_swap_t *swap_hit = |
| 266 | list_entry(hit, drm_i915_vbl_swap_t, head); |
| 267 | struct drm_clip_rect *rect; |
| 268 | int num_rects, plane; |
| 269 | unsigned short top, bottom; |
| 270 | |
| 271 | drw = drm_get_drawable_info(dev, swap_hit->drw_id); |
| 272 | |
| 273 | if (!drw) |
| 274 | continue; |
| 275 | |
| 276 | rect = drw->rects; |
| 277 | plane = swap_hit->plane; |
| 278 | top = upper[plane]; |
| 279 | bottom = lower[plane]; |
| 280 | |
| 281 | for (num_rects = drw->num_rects; num_rects--; rect++) { |
| 282 | int y1 = max(rect->y1, top); |
| 283 | int y2 = min(rect->y2, bottom); |
| 284 | |
| 285 | if (y1 >= y2) |
| 286 | continue; |
| 287 | |
| 288 | BEGIN_LP_RING(8); |
| 289 | |
| 290 | OUT_RING(cmd); |
| 291 | OUT_RING(ropcpp | dst_pitch); |
| 292 | OUT_RING((y1 << 16) | rect->x1); |
| 293 | OUT_RING((y2 << 16) | rect->x2); |
| 294 | OUT_RING(sarea_priv->front_offset); |
| 295 | OUT_RING((y1 << 16) | rect->x1); |
| 296 | OUT_RING(src_pitch); |
| 297 | OUT_RING(sarea_priv->back_offset); |
| 298 | |
| 299 | ADVANCE_LP_RING(); |
| 300 | } |
| 301 | } |
| 302 | } |
| 303 | |
| 304 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
| 305 | |
| 306 | list_for_each_safe(hit, tmp, &hits) { |
| 307 | drm_i915_vbl_swap_t *swap_hit = |
| 308 | list_entry(hit, drm_i915_vbl_swap_t, head); |
| 309 | |
| 310 | list_del(hit); |
| 311 | |
| 312 | drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER); |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | u32 i915_get_vblank_counter(struct drm_device *dev, int plane) |
| 317 | { |
| 318 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 319 | unsigned long high_frame; |
| 320 | unsigned long low_frame; |
| 321 | u32 high1, high2, low, count; |
| 322 | int pipe; |
| 323 | |
| 324 | pipe = i915_get_pipe(dev, plane); |
| 325 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 326 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 327 | |
| 328 | if (!i915_pipe_enabled(dev, pipe)) { |
| 329 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | /* |
| 334 | * High & low register fields aren't synchronized, so make sure |
| 335 | * we get a low value that's stable across two reads of the high |
| 336 | * register. |
| 337 | */ |
| 338 | do { |
| 339 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 340 | PIPE_FRAME_HIGH_SHIFT); |
| 341 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> |
| 342 | PIPE_FRAME_LOW_SHIFT); |
| 343 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 344 | PIPE_FRAME_HIGH_SHIFT); |
| 345 | } while (high1 != high2); |
| 346 | |
| 347 | count = (high1 << 8) | low; |
| 348 | |
| 349 | return count; |
| 350 | } |
| 351 | |
| 352 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 353 | { |
| 354 | struct drm_device *dev = (struct drm_device *) arg; |
| 355 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 356 | u32 iir; |
| 357 | u32 pipea_stats, pipeb_stats; |
| 358 | int vblank = 0; |
| 359 | |
| 360 | if (dev->pdev->msi_enabled) |
| 361 | I915_WRITE(IMR, ~0); |
| 362 | iir = I915_READ(IIR); |
| 363 | |
| 364 | if (iir == 0) { |
| 365 | if (dev->pdev->msi_enabled) { |
| 366 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 367 | (void) I915_READ(IMR); |
| 368 | } |
| 369 | return IRQ_NONE; |
| 370 | } |
| 371 | |
| 372 | /* |
| 373 | * Clear the PIPE(A|B)STAT regs before the IIR otherwise |
| 374 | * we may get extra interrupts. |
| 375 | */ |
| 376 | if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) { |
| 377 | pipea_stats = I915_READ(PIPEASTAT); |
| 378 | if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)) |
| 379 | pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | |
| 380 | PIPE_VBLANK_INTERRUPT_ENABLE); |
| 381 | else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| |
| 382 | PIPE_VBLANK_INTERRUPT_STATUS)) { |
| 383 | vblank++; |
| 384 | drm_handle_vblank(dev, i915_get_plane(dev, 0)); |
| 385 | } |
| 386 | |
| 387 | I915_WRITE(PIPEASTAT, pipea_stats); |
| 388 | } |
| 389 | if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) { |
| 390 | pipeb_stats = I915_READ(PIPEBSTAT); |
| 391 | /* Ack the event */ |
| 392 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
| 393 | |
| 394 | /* The vblank interrupt gets enabled even if we didn't ask for |
| 395 | it, so make sure it's shut down again */ |
| 396 | if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)) |
| 397 | pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | |
| 398 | PIPE_VBLANK_INTERRUPT_ENABLE); |
| 399 | else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS| |
| 400 | PIPE_VBLANK_INTERRUPT_STATUS)) { |
| 401 | vblank++; |
| 402 | drm_handle_vblank(dev, i915_get_plane(dev, 1)); |
| 403 | } |
| 404 | |
| 405 | if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) |
| 406 | opregion_asle_intr(dev); |
| 407 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
| 408 | } |
| 409 | |
| 410 | if (iir & I915_ASLE_INTERRUPT) |
| 411 | opregion_asle_intr(dev); |
| 412 | |
| 413 | dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
| 414 | |
| 415 | if (dev->pdev->msi_enabled) |
| 416 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 417 | I915_WRITE(IIR, iir); |
| 418 | (void) I915_READ(IIR); |
| 419 | |
| 420 | if (vblank && dev_priv->swaps_pending > 0) |
| 421 | drm_locked_tasklet(dev, i915_vblank_tasklet); |
| 422 | |
| 423 | return IRQ_HANDLED; |
| 424 | } |
| 425 | |
| 426 | static int i915_emit_irq(struct drm_device * dev) |
| 427 | { |
| 428 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 429 | RING_LOCALS; |
| 430 | |
| 431 | i915_kernel_lost_context(dev); |
| 432 | |
| 433 | DRM_DEBUG("\n"); |
| 434 | |
| 435 | dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; |
| 436 | |
| 437 | if (dev_priv->counter > 0x7FFFFFFFUL) |
| 438 | dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; |
| 439 | |
| 440 | BEGIN_LP_RING(6); |
| 441 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 442 | OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); |
| 443 | OUT_RING(dev_priv->counter); |
| 444 | OUT_RING(0); |
| 445 | OUT_RING(0); |
| 446 | OUT_RING(MI_USER_INTERRUPT); |
| 447 | ADVANCE_LP_RING(); |
| 448 | |
| 449 | return dev_priv->counter; |
| 450 | } |
| 451 | |
| 452 | static void i915_user_irq_get(struct drm_device *dev) |
| 453 | { |
| 454 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 455 | |
| 456 | spin_lock(&dev_priv->user_irq_lock); |
| 457 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) |
| 458 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 459 | spin_unlock(&dev_priv->user_irq_lock); |
| 460 | } |
| 461 | |
| 462 | void i915_user_irq_put(struct drm_device *dev) |
| 463 | { |
| 464 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 465 | |
| 466 | spin_lock(&dev_priv->user_irq_lock); |
| 467 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
| 468 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) |
| 469 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 470 | spin_unlock(&dev_priv->user_irq_lock); |
| 471 | } |
| 472 | |
| 473 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
| 474 | { |
| 475 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 476 | int ret = 0; |
| 477 | |
| 478 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
| 479 | READ_BREADCRUMB(dev_priv)); |
| 480 | |
| 481 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
| 482 | dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
| 483 | return 0; |
| 484 | } |
| 485 | |
| 486 | dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 487 | |
| 488 | i915_user_irq_get(dev); |
| 489 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
| 490 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
| 491 | i915_user_irq_put(dev); |
| 492 | |
| 493 | if (ret == -EBUSY) { |
| 494 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
| 495 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 496 | } |
| 497 | |
| 498 | dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
| 499 | |
| 500 | return ret; |
| 501 | } |
| 502 | |
| 503 | /* Needs the lock as it touches the ring. |
| 504 | */ |
| 505 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 506 | struct drm_file *file_priv) |
| 507 | { |
| 508 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 509 | drm_i915_irq_emit_t *emit = data; |
| 510 | int result; |
| 511 | |
| 512 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 513 | |
| 514 | if (!dev_priv) { |
| 515 | DRM_ERROR("called with no initialization\n"); |
| 516 | return -EINVAL; |
| 517 | } |
| 518 | |
| 519 | result = i915_emit_irq(dev); |
| 520 | |
| 521 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
| 522 | DRM_ERROR("copy_to_user\n"); |
| 523 | return -EFAULT; |
| 524 | } |
| 525 | |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | /* Doesn't need the hardware lock. |
| 530 | */ |
| 531 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 532 | struct drm_file *file_priv) |
| 533 | { |
| 534 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 535 | drm_i915_irq_wait_t *irqwait = data; |
| 536 | |
| 537 | if (!dev_priv) { |
| 538 | DRM_ERROR("called with no initialization\n"); |
| 539 | return -EINVAL; |
| 540 | } |
| 541 | |
| 542 | return i915_wait_irq(dev, irqwait->irq_seq); |
| 543 | } |
| 544 | |
| 545 | int i915_enable_vblank(struct drm_device *dev, int plane) |
| 546 | { |
| 547 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 548 | int pipe = i915_get_pipe(dev, plane); |
| 549 | u32 pipestat_reg = 0; |
| 550 | u32 pipestat; |
| 551 | |
| 552 | switch (pipe) { |
| 553 | case 0: |
| 554 | pipestat_reg = PIPEASTAT; |
| 555 | i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT); |
| 556 | break; |
| 557 | case 1: |
| 558 | pipestat_reg = PIPEBSTAT; |
| 559 | i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); |
| 560 | break; |
| 561 | default: |
| 562 | DRM_ERROR("tried to enable vblank on non-existent pipe %d\n", |
| 563 | pipe); |
| 564 | break; |
| 565 | } |
| 566 | |
| 567 | if (pipestat_reg) { |
| 568 | pipestat = I915_READ(pipestat_reg); |
| 569 | if (IS_I965G(dev)) |
| 570 | pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE; |
| 571 | else |
| 572 | pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE; |
| 573 | /* Clear any stale interrupt status */ |
| 574 | pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | |
| 575 | PIPE_VBLANK_INTERRUPT_STATUS); |
| 576 | I915_WRITE(pipestat_reg, pipestat); |
| 577 | } |
| 578 | |
| 579 | return 0; |
| 580 | } |
| 581 | |
| 582 | void i915_disable_vblank(struct drm_device *dev, int plane) |
| 583 | { |
| 584 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 585 | int pipe = i915_get_pipe(dev, plane); |
| 586 | u32 pipestat_reg = 0; |
| 587 | u32 pipestat; |
| 588 | |
| 589 | switch (pipe) { |
| 590 | case 0: |
| 591 | pipestat_reg = PIPEASTAT; |
| 592 | i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT); |
| 593 | break; |
| 594 | case 1: |
| 595 | pipestat_reg = PIPEBSTAT; |
| 596 | i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); |
| 597 | break; |
| 598 | default: |
| 599 | DRM_ERROR("tried to disable vblank on non-existent pipe %d\n", |
| 600 | pipe); |
| 601 | break; |
| 602 | } |
| 603 | |
| 604 | if (pipestat_reg) { |
| 605 | pipestat = I915_READ(pipestat_reg); |
| 606 | pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE | |
| 607 | PIPE_VBLANK_INTERRUPT_ENABLE); |
| 608 | /* Clear any stale interrupt status */ |
| 609 | pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS | |
| 610 | PIPE_VBLANK_INTERRUPT_STATUS); |
| 611 | I915_WRITE(pipestat_reg, pipestat); |
| 612 | } |
| 613 | } |
| 614 | |
| 615 | /* Set the vblank monitor pipe |
| 616 | */ |
| 617 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 618 | struct drm_file *file_priv) |
| 619 | { |
| 620 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 621 | |
| 622 | if (!dev_priv) { |
| 623 | DRM_ERROR("called with no initialization\n"); |
| 624 | return -EINVAL; |
| 625 | } |
| 626 | |
| 627 | return 0; |
| 628 | } |
| 629 | |
| 630 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 631 | struct drm_file *file_priv) |
| 632 | { |
| 633 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 634 | drm_i915_vblank_pipe_t *pipe = data; |
| 635 | |
| 636 | if (!dev_priv) { |
| 637 | DRM_ERROR("called with no initialization\n"); |
| 638 | return -EINVAL; |
| 639 | } |
| 640 | |
| 641 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 642 | |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | /** |
| 647 | * Schedule buffer swap at given vertical blank. |
| 648 | */ |
| 649 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 650 | struct drm_file *file_priv) |
| 651 | { |
| 652 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 653 | drm_i915_vblank_swap_t *swap = data; |
| 654 | drm_i915_vbl_swap_t *vbl_swap; |
| 655 | unsigned int pipe, seqtype, curseq, plane; |
| 656 | unsigned long irqflags; |
| 657 | struct list_head *list; |
| 658 | int ret; |
| 659 | |
| 660 | if (!dev_priv) { |
| 661 | DRM_ERROR("%s called with no initialization\n", __func__); |
| 662 | return -EINVAL; |
| 663 | } |
| 664 | |
| 665 | if (dev_priv->sarea_priv->rotation) { |
| 666 | DRM_DEBUG("Rotation not supported\n"); |
| 667 | return -EINVAL; |
| 668 | } |
| 669 | |
| 670 | if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE | |
| 671 | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) { |
| 672 | DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype); |
| 673 | return -EINVAL; |
| 674 | } |
| 675 | |
| 676 | plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0; |
| 677 | pipe = i915_get_pipe(dev, plane); |
| 678 | |
| 679 | seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE); |
| 680 | |
| 681 | if (!(dev_priv->vblank_pipe & (1 << pipe))) { |
| 682 | DRM_ERROR("Invalid pipe %d\n", pipe); |
| 683 | return -EINVAL; |
| 684 | } |
| 685 | |
| 686 | spin_lock_irqsave(&dev->drw_lock, irqflags); |
| 687 | |
| 688 | if (!drm_get_drawable_info(dev, swap->drawable)) { |
| 689 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
| 690 | DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable); |
| 691 | return -EINVAL; |
| 692 | } |
| 693 | |
| 694 | spin_unlock_irqrestore(&dev->drw_lock, irqflags); |
| 695 | |
| 696 | /* |
| 697 | * We take the ref here and put it when the swap actually completes |
| 698 | * in the tasklet. |
| 699 | */ |
| 700 | ret = drm_vblank_get(dev, pipe); |
| 701 | if (ret) |
| 702 | return ret; |
| 703 | curseq = drm_vblank_count(dev, pipe); |
| 704 | |
| 705 | if (seqtype == _DRM_VBLANK_RELATIVE) |
| 706 | swap->sequence += curseq; |
| 707 | |
| 708 | if ((curseq - swap->sequence) <= (1<<23)) { |
| 709 | if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) { |
| 710 | swap->sequence = curseq + 1; |
| 711 | } else { |
| 712 | DRM_DEBUG("Missed target sequence\n"); |
| 713 | drm_vblank_put(dev, pipe); |
| 714 | return -EINVAL; |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
| 719 | |
| 720 | list_for_each(list, &dev_priv->vbl_swaps.head) { |
| 721 | vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head); |
| 722 | |
| 723 | if (vbl_swap->drw_id == swap->drawable && |
| 724 | vbl_swap->plane == plane && |
| 725 | vbl_swap->sequence == swap->sequence) { |
| 726 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); |
| 727 | DRM_DEBUG("Already scheduled\n"); |
| 728 | return 0; |
| 729 | } |
| 730 | } |
| 731 | |
| 732 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); |
| 733 | |
| 734 | if (dev_priv->swaps_pending >= 100) { |
| 735 | DRM_DEBUG("Too many swaps queued\n"); |
| 736 | drm_vblank_put(dev, pipe); |
| 737 | return -EBUSY; |
| 738 | } |
| 739 | |
| 740 | vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER); |
| 741 | |
| 742 | if (!vbl_swap) { |
| 743 | DRM_ERROR("Failed to allocate memory to queue swap\n"); |
| 744 | drm_vblank_put(dev, pipe); |
| 745 | return -ENOMEM; |
| 746 | } |
| 747 | |
| 748 | DRM_DEBUG("\n"); |
| 749 | |
| 750 | vbl_swap->drw_id = swap->drawable; |
| 751 | vbl_swap->plane = plane; |
| 752 | vbl_swap->sequence = swap->sequence; |
| 753 | |
| 754 | spin_lock_irqsave(&dev_priv->swaps_lock, irqflags); |
| 755 | |
| 756 | list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head); |
| 757 | dev_priv->swaps_pending++; |
| 758 | |
| 759 | spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags); |
| 760 | |
| 761 | return 0; |
| 762 | } |
| 763 | |
| 764 | /* drm_dma.h hooks |
| 765 | */ |
| 766 | void i915_driver_irq_preinstall(struct drm_device * dev) |
| 767 | { |
| 768 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 769 | |
| 770 | I915_WRITE(HWSTAM, 0xeffe); |
| 771 | I915_WRITE(IMR, 0xffffffff); |
| 772 | I915_WRITE(IER, 0x0); |
| 773 | } |
| 774 | |
| 775 | int i915_driver_irq_postinstall(struct drm_device *dev) |
| 776 | { |
| 777 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 778 | int ret, num_pipes = 2; |
| 779 | |
| 780 | spin_lock_init(&dev_priv->swaps_lock); |
| 781 | INIT_LIST_HEAD(&dev_priv->vbl_swaps.head); |
| 782 | dev_priv->swaps_pending = 0; |
| 783 | |
| 784 | /* Set initial unmasked IRQs to just the selected vblank pipes. */ |
| 785 | dev_priv->irq_mask_reg = ~0; |
| 786 | |
| 787 | ret = drm_vblank_init(dev, num_pipes); |
| 788 | if (ret) |
| 789 | return ret; |
| 790 | |
| 791 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
| 792 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
| 793 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 794 | |
| 795 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
| 796 | |
| 797 | dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK; |
| 798 | |
| 799 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 800 | I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK); |
| 801 | (void) I915_READ(IER); |
| 802 | |
| 803 | opregion_enable_asle(dev); |
| 804 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
| 805 | |
| 806 | return 0; |
| 807 | } |
| 808 | |
| 809 | void i915_driver_irq_uninstall(struct drm_device * dev) |
| 810 | { |
| 811 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 812 | u32 temp; |
| 813 | |
| 814 | if (!dev_priv) |
| 815 | return; |
| 816 | |
| 817 | dev_priv->vblank_pipe = 0; |
| 818 | |
| 819 | I915_WRITE(HWSTAM, 0xffffffff); |
| 820 | I915_WRITE(IMR, 0xffffffff); |
| 821 | I915_WRITE(IER, 0x0); |
| 822 | |
| 823 | temp = I915_READ(PIPEASTAT); |
| 824 | I915_WRITE(PIPEASTAT, temp); |
| 825 | temp = I915_READ(PIPEBSTAT); |
| 826 | I915_WRITE(PIPEBSTAT, temp); |
| 827 | temp = I915_READ(IIR); |
| 828 | I915_WRITE(IIR, temp); |
| 829 | } |