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Revert "drm/i915/ringbuffer: Ignore failure to setup the ring on Sandybridge"
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
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1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#include <linux/sysrq.h>
30#include <linux/slab.h>
31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35#include "i915_trace.h"
36#include "intel_drv.h"
37
38#define MAX_NOPID ((u32)~0)
39
40/**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
47#define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
54
55/** Interrupts that we mask and unmask at runtime. */
56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
57
58#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
67void
68ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
69{
70 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
71 dev_priv->gt_irq_mask_reg &= ~mask;
72 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
73 (void) I915_READ(GTIMR);
74 }
75}
76
77void
78ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
79{
80 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
81 dev_priv->gt_irq_mask_reg |= mask;
82 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
83 (void) I915_READ(GTIMR);
84 }
85}
86
87/* For display hotplug interrupt */
88static void
89ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
90{
91 if ((dev_priv->irq_mask_reg & mask) != 0) {
92 dev_priv->irq_mask_reg &= ~mask;
93 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
94 (void) I915_READ(DEIMR);
95 }
96}
97
98static inline void
99ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
100{
101 if ((dev_priv->irq_mask_reg & mask) != mask) {
102 dev_priv->irq_mask_reg |= mask;
103 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
104 (void) I915_READ(DEIMR);
105 }
106}
107
108void
109i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
110{
111 if ((dev_priv->irq_mask_reg & mask) != 0) {
112 dev_priv->irq_mask_reg &= ~mask;
113 I915_WRITE(IMR, dev_priv->irq_mask_reg);
114 (void) I915_READ(IMR);
115 }
116}
117
118void
119i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
120{
121 if ((dev_priv->irq_mask_reg & mask) != mask) {
122 dev_priv->irq_mask_reg |= mask;
123 I915_WRITE(IMR, dev_priv->irq_mask_reg);
124 (void) I915_READ(IMR);
125 }
126}
127
128static inline u32
129i915_pipestat(int pipe)
130{
131 if (pipe == 0)
132 return PIPEASTAT;
133 if (pipe == 1)
134 return PIPEBSTAT;
135 BUG();
136}
137
138void
139i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
140{
141 if ((dev_priv->pipestat[pipe] & mask) != mask) {
142 u32 reg = i915_pipestat(pipe);
143
144 dev_priv->pipestat[pipe] |= mask;
145 /* Enable the interrupt, clear any pending status */
146 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
147 (void) I915_READ(reg);
148 }
149}
150
151void
152i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
153{
154 if ((dev_priv->pipestat[pipe] & mask) != 0) {
155 u32 reg = i915_pipestat(pipe);
156
157 dev_priv->pipestat[pipe] &= ~mask;
158 I915_WRITE(reg, dev_priv->pipestat[pipe]);
159 (void) I915_READ(reg);
160 }
161}
162
163/**
164 * intel_enable_asle - enable ASLE interrupt for OpRegion
165 */
166void intel_enable_asle (struct drm_device *dev)
167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
169
170 if (HAS_PCH_SPLIT(dev))
171 ironlake_enable_display_irq(dev_priv, DE_GSE);
172 else {
173 i915_enable_pipestat(dev_priv, 1,
174 PIPE_LEGACY_BLC_EVENT_ENABLE);
175 if (INTEL_INFO(dev)->gen >= 4)
176 i915_enable_pipestat(dev_priv, 0,
177 PIPE_LEGACY_BLC_EVENT_ENABLE);
178 }
179}
180
181/**
182 * i915_pipe_enabled - check if a pipe is enabled
183 * @dev: DRM device
184 * @pipe: pipe to check
185 *
186 * Reading certain registers when the pipe is disabled can hang the chip.
187 * Use this routine to make sure the PLL is running and the pipe is active
188 * before reading such registers if unsure.
189 */
190static int
191i915_pipe_enabled(struct drm_device *dev, int pipe)
192{
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
195}
196
197/* Called from drm generic code, passed a 'crtc', which
198 * we use as a pipe index
199 */
200u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
201{
202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
203 unsigned long high_frame;
204 unsigned long low_frame;
205 u32 high1, high2, low;
206
207 if (!i915_pipe_enabled(dev, pipe)) {
208 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
209 "pipe %d\n", pipe);
210 return 0;
211 }
212
213 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
214 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
215
216 /*
217 * High & low register fields aren't synchronized, so make sure
218 * we get a low value that's stable across two reads of the high
219 * register.
220 */
221 do {
222 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
223 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
224 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
225 } while (high1 != high2);
226
227 high1 >>= PIPE_FRAME_HIGH_SHIFT;
228 low >>= PIPE_FRAME_LOW_SHIFT;
229 return (high1 << 8) | low;
230}
231
232u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
233{
234 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
235 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
236
237 if (!i915_pipe_enabled(dev, pipe)) {
238 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
239 "pipe %d\n", pipe);
240 return 0;
241 }
242
243 return I915_READ(reg);
244}
245
246/*
247 * Handle hotplug events outside the interrupt handler proper.
248 */
249static void i915_hotplug_work_func(struct work_struct *work)
250{
251 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
252 hotplug_work);
253 struct drm_device *dev = dev_priv->dev;
254 struct drm_mode_config *mode_config = &dev->mode_config;
255 struct intel_encoder *encoder;
256
257 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
258 if (encoder->hot_plug)
259 encoder->hot_plug(encoder);
260
261 /* Just fire off a uevent and let userspace tell us what to do */
262 drm_helper_hpd_irq_event(dev);
263}
264
265static void i915_handle_rps_change(struct drm_device *dev)
266{
267 drm_i915_private_t *dev_priv = dev->dev_private;
268 u32 busy_up, busy_down, max_avg, min_avg;
269 u8 new_delay = dev_priv->cur_delay;
270
271 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
272 busy_up = I915_READ(RCPREVBSYTUPAVG);
273 busy_down = I915_READ(RCPREVBSYTDNAVG);
274 max_avg = I915_READ(RCBMAXAVG);
275 min_avg = I915_READ(RCBMINAVG);
276
277 /* Handle RCS change request from hw */
278 if (busy_up > max_avg) {
279 if (dev_priv->cur_delay != dev_priv->max_delay)
280 new_delay = dev_priv->cur_delay - 1;
281 if (new_delay < dev_priv->max_delay)
282 new_delay = dev_priv->max_delay;
283 } else if (busy_down < min_avg) {
284 if (dev_priv->cur_delay != dev_priv->min_delay)
285 new_delay = dev_priv->cur_delay + 1;
286 if (new_delay > dev_priv->min_delay)
287 new_delay = dev_priv->min_delay;
288 }
289
290 if (ironlake_set_drps(dev, new_delay))
291 dev_priv->cur_delay = new_delay;
292
293 return;
294}
295
296static void notify_ring(struct drm_device *dev,
297 struct intel_ring_buffer *ring)
298{
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 u32 seqno = ring->get_seqno(ring);
301 ring->irq_seqno = seqno;
302 trace_i915_gem_request_complete(dev, seqno);
303 wake_up_all(&ring->irq_queue);
304 dev_priv->hangcheck_count = 0;
305 mod_timer(&dev_priv->hangcheck_timer,
306 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
307}
308
309static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
310{
311 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
312 int ret = IRQ_NONE;
313 u32 de_iir, gt_iir, de_ier, pch_iir;
314 u32 hotplug_mask;
315 struct drm_i915_master_private *master_priv;
316 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
317
318 if (IS_GEN6(dev))
319 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
320
321 /* disable master interrupt before clearing iir */
322 de_ier = I915_READ(DEIER);
323 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
324 (void)I915_READ(DEIER);
325
326 de_iir = I915_READ(DEIIR);
327 gt_iir = I915_READ(GTIIR);
328 pch_iir = I915_READ(SDEIIR);
329
330 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
331 goto done;
332
333 if (HAS_PCH_CPT(dev))
334 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
335 else
336 hotplug_mask = SDE_HOTPLUG_MASK;
337
338 ret = IRQ_HANDLED;
339
340 if (dev->primary->master) {
341 master_priv = dev->primary->master->driver_priv;
342 if (master_priv->sarea_priv)
343 master_priv->sarea_priv->last_dispatch =
344 READ_BREADCRUMB(dev_priv);
345 }
346
347 if (gt_iir & GT_PIPE_NOTIFY)
348 notify_ring(dev, &dev_priv->render_ring);
349 if (gt_iir & bsd_usr_interrupt)
350 notify_ring(dev, &dev_priv->bsd_ring);
351 if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
352 notify_ring(dev, &dev_priv->blt_ring);
353
354 if (de_iir & DE_GSE)
355 intel_opregion_gse_intr(dev);
356
357 if (de_iir & DE_PLANEA_FLIP_DONE) {
358 intel_prepare_page_flip(dev, 0);
359 intel_finish_page_flip_plane(dev, 0);
360 }
361
362 if (de_iir & DE_PLANEB_FLIP_DONE) {
363 intel_prepare_page_flip(dev, 1);
364 intel_finish_page_flip_plane(dev, 1);
365 }
366
367 if (de_iir & DE_PIPEA_VBLANK)
368 drm_handle_vblank(dev, 0);
369
370 if (de_iir & DE_PIPEB_VBLANK)
371 drm_handle_vblank(dev, 1);
372
373 /* check event from PCH */
374 if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
375 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
376
377 if (de_iir & DE_PCU_EVENT) {
378 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
379 i915_handle_rps_change(dev);
380 }
381
382 /* should clear PCH hotplug event before clear CPU irq */
383 I915_WRITE(SDEIIR, pch_iir);
384 I915_WRITE(GTIIR, gt_iir);
385 I915_WRITE(DEIIR, de_iir);
386
387done:
388 I915_WRITE(DEIER, de_ier);
389 (void)I915_READ(DEIER);
390
391 return ret;
392}
393
394/**
395 * i915_error_work_func - do process context error handling work
396 * @work: work struct
397 *
398 * Fire an error uevent so userspace can see that a hang or error
399 * was detected.
400 */
401static void i915_error_work_func(struct work_struct *work)
402{
403 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
404 error_work);
405 struct drm_device *dev = dev_priv->dev;
406 char *error_event[] = { "ERROR=1", NULL };
407 char *reset_event[] = { "RESET=1", NULL };
408 char *reset_done_event[] = { "ERROR=0", NULL };
409
410 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
411
412 if (atomic_read(&dev_priv->mm.wedged)) {
413 DRM_DEBUG_DRIVER("resetting chip\n");
414 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
415 if (!i915_reset(dev, GRDOM_RENDER)) {
416 atomic_set(&dev_priv->mm.wedged, 0);
417 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
418 }
419 complete_all(&dev_priv->error_completion);
420 }
421}
422
423#ifdef CONFIG_DEBUG_FS
424static struct drm_i915_error_object *
425i915_error_object_create(struct drm_device *dev,
426 struct drm_gem_object *src)
427{
428 drm_i915_private_t *dev_priv = dev->dev_private;
429 struct drm_i915_error_object *dst;
430 struct drm_i915_gem_object *src_priv;
431 int page, page_count;
432 u32 reloc_offset;
433
434 if (src == NULL)
435 return NULL;
436
437 src_priv = to_intel_bo(src);
438 if (src_priv->pages == NULL)
439 return NULL;
440
441 page_count = src->size / PAGE_SIZE;
442
443 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
444 if (dst == NULL)
445 return NULL;
446
447 reloc_offset = src_priv->gtt_offset;
448 for (page = 0; page < page_count; page++) {
449 unsigned long flags;
450 void __iomem *s;
451 void *d;
452
453 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
454 if (d == NULL)
455 goto unwind;
456
457 local_irq_save(flags);
458 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
459 reloc_offset);
460 memcpy_fromio(d, s, PAGE_SIZE);
461 io_mapping_unmap_atomic(s);
462 local_irq_restore(flags);
463
464 dst->pages[page] = d;
465
466 reloc_offset += PAGE_SIZE;
467 }
468 dst->page_count = page_count;
469 dst->gtt_offset = src_priv->gtt_offset;
470
471 return dst;
472
473unwind:
474 while (page--)
475 kfree(dst->pages[page]);
476 kfree(dst);
477 return NULL;
478}
479
480static void
481i915_error_object_free(struct drm_i915_error_object *obj)
482{
483 int page;
484
485 if (obj == NULL)
486 return;
487
488 for (page = 0; page < obj->page_count; page++)
489 kfree(obj->pages[page]);
490
491 kfree(obj);
492}
493
494static void
495i915_error_state_free(struct drm_device *dev,
496 struct drm_i915_error_state *error)
497{
498 i915_error_object_free(error->batchbuffer[0]);
499 i915_error_object_free(error->batchbuffer[1]);
500 i915_error_object_free(error->ringbuffer);
501 kfree(error->active_bo);
502 kfree(error->overlay);
503 kfree(error);
504}
505
506static u32
507i915_get_bbaddr(struct drm_device *dev, u32 *ring)
508{
509 u32 cmd;
510
511 if (IS_I830(dev) || IS_845G(dev))
512 cmd = MI_BATCH_BUFFER;
513 else if (INTEL_INFO(dev)->gen >= 4)
514 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
515 MI_BATCH_NON_SECURE_I965);
516 else
517 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
518
519 return ring[0] == cmd ? ring[1] : 0;
520}
521
522static u32
523i915_ringbuffer_last_batch(struct drm_device *dev)
524{
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 u32 head, bbaddr;
527 u32 *ring;
528
529 /* Locate the current position in the ringbuffer and walk back
530 * to find the most recently dispatched batch buffer.
531 */
532 bbaddr = 0;
533 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
534 ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
535
536 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
537 bbaddr = i915_get_bbaddr(dev, ring);
538 if (bbaddr)
539 break;
540 }
541
542 if (bbaddr == 0) {
543 ring = (u32 *)(dev_priv->render_ring.virtual_start
544 + dev_priv->render_ring.size);
545 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
546 bbaddr = i915_get_bbaddr(dev, ring);
547 if (bbaddr)
548 break;
549 }
550 }
551
552 return bbaddr;
553}
554
555/**
556 * i915_capture_error_state - capture an error record for later analysis
557 * @dev: drm device
558 *
559 * Should be called when an error is detected (either a hang or an error
560 * interrupt) to capture error state from the time of the error. Fills
561 * out a structure which becomes available in debugfs for user level tools
562 * to pick up.
563 */
564static void i915_capture_error_state(struct drm_device *dev)
565{
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct drm_i915_gem_object *obj_priv;
568 struct drm_i915_error_state *error;
569 struct drm_gem_object *batchbuffer[2];
570 unsigned long flags;
571 u32 bbaddr;
572 int count;
573
574 spin_lock_irqsave(&dev_priv->error_lock, flags);
575 error = dev_priv->first_error;
576 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
577 if (error)
578 return;
579
580 error = kmalloc(sizeof(*error), GFP_ATOMIC);
581 if (!error) {
582 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
583 return;
584 }
585
586 DRM_DEBUG_DRIVER("generating error event\n");
587
588 error->seqno =
589 dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
590 error->eir = I915_READ(EIR);
591 error->pgtbl_er = I915_READ(PGTBL_ER);
592 error->pipeastat = I915_READ(PIPEASTAT);
593 error->pipebstat = I915_READ(PIPEBSTAT);
594 error->instpm = I915_READ(INSTPM);
595 error->error = 0;
596 if (INTEL_INFO(dev)->gen >= 6) {
597 error->error = I915_READ(ERROR_GEN6);
598
599 error->bcs_acthd = I915_READ(BCS_ACTHD);
600 error->bcs_ipehr = I915_READ(BCS_IPEHR);
601 error->bcs_ipeir = I915_READ(BCS_IPEIR);
602 error->bcs_instdone = I915_READ(BCS_INSTDONE);
603 error->bcs_seqno = 0;
604 if (dev_priv->blt_ring.get_seqno)
605 error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring);
606
607 error->vcs_acthd = I915_READ(VCS_ACTHD);
608 error->vcs_ipehr = I915_READ(VCS_IPEHR);
609 error->vcs_ipeir = I915_READ(VCS_IPEIR);
610 error->vcs_instdone = I915_READ(VCS_INSTDONE);
611 error->vcs_seqno = 0;
612 if (dev_priv->bsd_ring.get_seqno)
613 error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring);
614 }
615 if (INTEL_INFO(dev)->gen >= 4) {
616 error->ipeir = I915_READ(IPEIR_I965);
617 error->ipehr = I915_READ(IPEHR_I965);
618 error->instdone = I915_READ(INSTDONE_I965);
619 error->instps = I915_READ(INSTPS);
620 error->instdone1 = I915_READ(INSTDONE1);
621 error->acthd = I915_READ(ACTHD_I965);
622 error->bbaddr = I915_READ64(BB_ADDR);
623 } else {
624 error->ipeir = I915_READ(IPEIR);
625 error->ipehr = I915_READ(IPEHR);
626 error->instdone = I915_READ(INSTDONE);
627 error->acthd = I915_READ(ACTHD);
628 error->bbaddr = 0;
629 }
630
631 bbaddr = i915_ringbuffer_last_batch(dev);
632
633 /* Grab the current batchbuffer, most likely to have crashed. */
634 batchbuffer[0] = NULL;
635 batchbuffer[1] = NULL;
636 count = 0;
637 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
638 struct drm_gem_object *obj = &obj_priv->base;
639
640 if (batchbuffer[0] == NULL &&
641 bbaddr >= obj_priv->gtt_offset &&
642 bbaddr < obj_priv->gtt_offset + obj->size)
643 batchbuffer[0] = obj;
644
645 if (batchbuffer[1] == NULL &&
646 error->acthd >= obj_priv->gtt_offset &&
647 error->acthd < obj_priv->gtt_offset + obj->size)
648 batchbuffer[1] = obj;
649
650 count++;
651 }
652 /* Scan the other lists for completeness for those bizarre errors. */
653 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
654 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) {
655 struct drm_gem_object *obj = &obj_priv->base;
656
657 if (batchbuffer[0] == NULL &&
658 bbaddr >= obj_priv->gtt_offset &&
659 bbaddr < obj_priv->gtt_offset + obj->size)
660 batchbuffer[0] = obj;
661
662 if (batchbuffer[1] == NULL &&
663 error->acthd >= obj_priv->gtt_offset &&
664 error->acthd < obj_priv->gtt_offset + obj->size)
665 batchbuffer[1] = obj;
666
667 if (batchbuffer[0] && batchbuffer[1])
668 break;
669 }
670 }
671 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
672 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) {
673 struct drm_gem_object *obj = &obj_priv->base;
674
675 if (batchbuffer[0] == NULL &&
676 bbaddr >= obj_priv->gtt_offset &&
677 bbaddr < obj_priv->gtt_offset + obj->size)
678 batchbuffer[0] = obj;
679
680 if (batchbuffer[1] == NULL &&
681 error->acthd >= obj_priv->gtt_offset &&
682 error->acthd < obj_priv->gtt_offset + obj->size)
683 batchbuffer[1] = obj;
684
685 if (batchbuffer[0] && batchbuffer[1])
686 break;
687 }
688 }
689
690 /* We need to copy these to an anonymous buffer as the simplest
691 * method to avoid being overwritten by userspace.
692 */
693 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
694 if (batchbuffer[1] != batchbuffer[0])
695 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
696 else
697 error->batchbuffer[1] = NULL;
698
699 /* Record the ringbuffer */
700 error->ringbuffer = i915_error_object_create(dev,
701 dev_priv->render_ring.gem_object);
702
703 /* Record buffers on the active list. */
704 error->active_bo = NULL;
705 error->active_bo_count = 0;
706
707 if (count)
708 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
709 GFP_ATOMIC);
710
711 if (error->active_bo) {
712 int i = 0;
713 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
714 struct drm_gem_object *obj = &obj_priv->base;
715
716 error->active_bo[i].size = obj->size;
717 error->active_bo[i].name = obj->name;
718 error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
719 error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
720 error->active_bo[i].read_domains = obj->read_domains;
721 error->active_bo[i].write_domain = obj->write_domain;
722 error->active_bo[i].fence_reg = obj_priv->fence_reg;
723 error->active_bo[i].pinned = 0;
724 if (obj_priv->pin_count > 0)
725 error->active_bo[i].pinned = 1;
726 if (obj_priv->user_pin_count > 0)
727 error->active_bo[i].pinned = -1;
728 error->active_bo[i].tiling = obj_priv->tiling_mode;
729 error->active_bo[i].dirty = obj_priv->dirty;
730 error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
731 error->active_bo[i].ring = obj_priv->ring->id;
732
733 if (++i == count)
734 break;
735 }
736 error->active_bo_count = i;
737 }
738
739 do_gettimeofday(&error->time);
740
741 error->overlay = intel_overlay_capture_error_state(dev);
742
743 spin_lock_irqsave(&dev_priv->error_lock, flags);
744 if (dev_priv->first_error == NULL) {
745 dev_priv->first_error = error;
746 error = NULL;
747 }
748 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
749
750 if (error)
751 i915_error_state_free(dev, error);
752}
753
754void i915_destroy_error_state(struct drm_device *dev)
755{
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 struct drm_i915_error_state *error;
758
759 spin_lock(&dev_priv->error_lock);
760 error = dev_priv->first_error;
761 dev_priv->first_error = NULL;
762 spin_unlock(&dev_priv->error_lock);
763
764 if (error)
765 i915_error_state_free(dev, error);
766}
767#else
768#define i915_capture_error_state(x)
769#endif
770
771static void i915_report_and_clear_eir(struct drm_device *dev)
772{
773 struct drm_i915_private *dev_priv = dev->dev_private;
774 u32 eir = I915_READ(EIR);
775
776 if (!eir)
777 return;
778
779 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
780 eir);
781
782 if (IS_G4X(dev)) {
783 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
784 u32 ipeir = I915_READ(IPEIR_I965);
785
786 printk(KERN_ERR " IPEIR: 0x%08x\n",
787 I915_READ(IPEIR_I965));
788 printk(KERN_ERR " IPEHR: 0x%08x\n",
789 I915_READ(IPEHR_I965));
790 printk(KERN_ERR " INSTDONE: 0x%08x\n",
791 I915_READ(INSTDONE_I965));
792 printk(KERN_ERR " INSTPS: 0x%08x\n",
793 I915_READ(INSTPS));
794 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
795 I915_READ(INSTDONE1));
796 printk(KERN_ERR " ACTHD: 0x%08x\n",
797 I915_READ(ACTHD_I965));
798 I915_WRITE(IPEIR_I965, ipeir);
799 (void)I915_READ(IPEIR_I965);
800 }
801 if (eir & GM45_ERROR_PAGE_TABLE) {
802 u32 pgtbl_err = I915_READ(PGTBL_ER);
803 printk(KERN_ERR "page table error\n");
804 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
805 pgtbl_err);
806 I915_WRITE(PGTBL_ER, pgtbl_err);
807 (void)I915_READ(PGTBL_ER);
808 }
809 }
810
811 if (!IS_GEN2(dev)) {
812 if (eir & I915_ERROR_PAGE_TABLE) {
813 u32 pgtbl_err = I915_READ(PGTBL_ER);
814 printk(KERN_ERR "page table error\n");
815 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
816 pgtbl_err);
817 I915_WRITE(PGTBL_ER, pgtbl_err);
818 (void)I915_READ(PGTBL_ER);
819 }
820 }
821
822 if (eir & I915_ERROR_MEMORY_REFRESH) {
823 u32 pipea_stats = I915_READ(PIPEASTAT);
824 u32 pipeb_stats = I915_READ(PIPEBSTAT);
825
826 printk(KERN_ERR "memory refresh error\n");
827 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
828 pipea_stats);
829 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
830 pipeb_stats);
831 /* pipestat has already been acked */
832 }
833 if (eir & I915_ERROR_INSTRUCTION) {
834 printk(KERN_ERR "instruction error\n");
835 printk(KERN_ERR " INSTPM: 0x%08x\n",
836 I915_READ(INSTPM));
837 if (INTEL_INFO(dev)->gen < 4) {
838 u32 ipeir = I915_READ(IPEIR);
839
840 printk(KERN_ERR " IPEIR: 0x%08x\n",
841 I915_READ(IPEIR));
842 printk(KERN_ERR " IPEHR: 0x%08x\n",
843 I915_READ(IPEHR));
844 printk(KERN_ERR " INSTDONE: 0x%08x\n",
845 I915_READ(INSTDONE));
846 printk(KERN_ERR " ACTHD: 0x%08x\n",
847 I915_READ(ACTHD));
848 I915_WRITE(IPEIR, ipeir);
849 (void)I915_READ(IPEIR);
850 } else {
851 u32 ipeir = I915_READ(IPEIR_I965);
852
853 printk(KERN_ERR " IPEIR: 0x%08x\n",
854 I915_READ(IPEIR_I965));
855 printk(KERN_ERR " IPEHR: 0x%08x\n",
856 I915_READ(IPEHR_I965));
857 printk(KERN_ERR " INSTDONE: 0x%08x\n",
858 I915_READ(INSTDONE_I965));
859 printk(KERN_ERR " INSTPS: 0x%08x\n",
860 I915_READ(INSTPS));
861 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
862 I915_READ(INSTDONE1));
863 printk(KERN_ERR " ACTHD: 0x%08x\n",
864 I915_READ(ACTHD_I965));
865 I915_WRITE(IPEIR_I965, ipeir);
866 (void)I915_READ(IPEIR_I965);
867 }
868 }
869
870 I915_WRITE(EIR, eir);
871 (void)I915_READ(EIR);
872 eir = I915_READ(EIR);
873 if (eir) {
874 /*
875 * some errors might have become stuck,
876 * mask them.
877 */
878 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
879 I915_WRITE(EMR, I915_READ(EMR) | eir);
880 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
881 }
882}
883
884/**
885 * i915_handle_error - handle an error interrupt
886 * @dev: drm device
887 *
888 * Do some basic checking of regsiter state at error interrupt time and
889 * dump it to the syslog. Also call i915_capture_error_state() to make
890 * sure we get a record and make it available in debugfs. Fire a uevent
891 * so userspace knows something bad happened (should trigger collection
892 * of a ring dump etc.).
893 */
894void i915_handle_error(struct drm_device *dev, bool wedged)
895{
896 struct drm_i915_private *dev_priv = dev->dev_private;
897
898 i915_capture_error_state(dev);
899 i915_report_and_clear_eir(dev);
900
901 if (wedged) {
902 INIT_COMPLETION(dev_priv->error_completion);
903 atomic_set(&dev_priv->mm.wedged, 1);
904
905 /*
906 * Wakeup waiting processes so they don't hang
907 */
908 wake_up_all(&dev_priv->render_ring.irq_queue);
909 if (HAS_BSD(dev))
910 wake_up_all(&dev_priv->bsd_ring.irq_queue);
911 if (HAS_BLT(dev))
912 wake_up_all(&dev_priv->blt_ring.irq_queue);
913 }
914
915 queue_work(dev_priv->wq, &dev_priv->error_work);
916}
917
918static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
919{
920 drm_i915_private_t *dev_priv = dev->dev_private;
921 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
923 struct drm_i915_gem_object *obj_priv;
924 struct intel_unpin_work *work;
925 unsigned long flags;
926 bool stall_detected;
927
928 /* Ignore early vblank irqs */
929 if (intel_crtc == NULL)
930 return;
931
932 spin_lock_irqsave(&dev->event_lock, flags);
933 work = intel_crtc->unpin_work;
934
935 if (work == NULL || work->pending || !work->enable_stall_check) {
936 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
937 spin_unlock_irqrestore(&dev->event_lock, flags);
938 return;
939 }
940
941 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
942 obj_priv = to_intel_bo(work->pending_flip_obj);
943 if (INTEL_INFO(dev)->gen >= 4) {
944 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
945 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
946 } else {
947 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
948 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
949 crtc->y * crtc->fb->pitch +
950 crtc->x * crtc->fb->bits_per_pixel/8);
951 }
952
953 spin_unlock_irqrestore(&dev->event_lock, flags);
954
955 if (stall_detected) {
956 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
957 intel_prepare_page_flip(dev, intel_crtc->plane);
958 }
959}
960
961irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
962{
963 struct drm_device *dev = (struct drm_device *) arg;
964 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
965 struct drm_i915_master_private *master_priv;
966 u32 iir, new_iir;
967 u32 pipea_stats, pipeb_stats;
968 u32 vblank_status;
969 int vblank = 0;
970 unsigned long irqflags;
971 int irq_received;
972 int ret = IRQ_NONE;
973
974 atomic_inc(&dev_priv->irq_received);
975
976 if (HAS_PCH_SPLIT(dev))
977 return ironlake_irq_handler(dev);
978
979 iir = I915_READ(IIR);
980
981 if (INTEL_INFO(dev)->gen >= 4)
982 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
983 else
984 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
985
986 for (;;) {
987 irq_received = iir != 0;
988
989 /* Can't rely on pipestat interrupt bit in iir as it might
990 * have been cleared after the pipestat interrupt was received.
991 * It doesn't set the bit in iir again, but it still produces
992 * interrupts (for non-MSI).
993 */
994 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
995 pipea_stats = I915_READ(PIPEASTAT);
996 pipeb_stats = I915_READ(PIPEBSTAT);
997
998 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
999 i915_handle_error(dev, false);
1000
1001 /*
1002 * Clear the PIPE(A|B)STAT regs before the IIR
1003 */
1004 if (pipea_stats & 0x8000ffff) {
1005 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
1006 DRM_DEBUG_DRIVER("pipe a underrun\n");
1007 I915_WRITE(PIPEASTAT, pipea_stats);
1008 irq_received = 1;
1009 }
1010
1011 if (pipeb_stats & 0x8000ffff) {
1012 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
1013 DRM_DEBUG_DRIVER("pipe b underrun\n");
1014 I915_WRITE(PIPEBSTAT, pipeb_stats);
1015 irq_received = 1;
1016 }
1017 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1018
1019 if (!irq_received)
1020 break;
1021
1022 ret = IRQ_HANDLED;
1023
1024 /* Consume port. Then clear IIR or we'll miss events */
1025 if ((I915_HAS_HOTPLUG(dev)) &&
1026 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1027 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1028
1029 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1030 hotplug_status);
1031 if (hotplug_status & dev_priv->hotplug_supported_mask)
1032 queue_work(dev_priv->wq,
1033 &dev_priv->hotplug_work);
1034
1035 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1036 I915_READ(PORT_HOTPLUG_STAT);
1037 }
1038
1039 I915_WRITE(IIR, iir);
1040 new_iir = I915_READ(IIR); /* Flush posted writes */
1041
1042 if (dev->primary->master) {
1043 master_priv = dev->primary->master->driver_priv;
1044 if (master_priv->sarea_priv)
1045 master_priv->sarea_priv->last_dispatch =
1046 READ_BREADCRUMB(dev_priv);
1047 }
1048
1049 if (iir & I915_USER_INTERRUPT)
1050 notify_ring(dev, &dev_priv->render_ring);
1051 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1052 notify_ring(dev, &dev_priv->bsd_ring);
1053
1054 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1055 intel_prepare_page_flip(dev, 0);
1056 if (dev_priv->flip_pending_is_done)
1057 intel_finish_page_flip_plane(dev, 0);
1058 }
1059
1060 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1061 intel_prepare_page_flip(dev, 1);
1062 if (dev_priv->flip_pending_is_done)
1063 intel_finish_page_flip_plane(dev, 1);
1064 }
1065
1066 if (pipea_stats & vblank_status) {
1067 vblank++;
1068 drm_handle_vblank(dev, 0);
1069 if (!dev_priv->flip_pending_is_done) {
1070 i915_pageflip_stall_check(dev, 0);
1071 intel_finish_page_flip(dev, 0);
1072 }
1073 }
1074
1075 if (pipeb_stats & vblank_status) {
1076 vblank++;
1077 drm_handle_vblank(dev, 1);
1078 if (!dev_priv->flip_pending_is_done) {
1079 i915_pageflip_stall_check(dev, 1);
1080 intel_finish_page_flip(dev, 1);
1081 }
1082 }
1083
1084 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1085 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1086 (iir & I915_ASLE_INTERRUPT))
1087 intel_opregion_asle_intr(dev);
1088
1089 /* With MSI, interrupts are only generated when iir
1090 * transitions from zero to nonzero. If another bit got
1091 * set while we were handling the existing iir bits, then
1092 * we would never get another interrupt.
1093 *
1094 * This is fine on non-MSI as well, as if we hit this path
1095 * we avoid exiting the interrupt handler only to generate
1096 * another one.
1097 *
1098 * Note that for MSI this could cause a stray interrupt report
1099 * if an interrupt landed in the time between writing IIR and
1100 * the posting read. This should be rare enough to never
1101 * trigger the 99% of 100,000 interrupts test for disabling
1102 * stray interrupts.
1103 */
1104 iir = new_iir;
1105 }
1106
1107 return ret;
1108}
1109
1110static int i915_emit_irq(struct drm_device * dev)
1111{
1112 drm_i915_private_t *dev_priv = dev->dev_private;
1113 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1114
1115 i915_kernel_lost_context(dev);
1116
1117 DRM_DEBUG_DRIVER("\n");
1118
1119 dev_priv->counter++;
1120 if (dev_priv->counter > 0x7FFFFFFFUL)
1121 dev_priv->counter = 1;
1122 if (master_priv->sarea_priv)
1123 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1124
1125 if (BEGIN_LP_RING(4) == 0) {
1126 OUT_RING(MI_STORE_DWORD_INDEX);
1127 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1128 OUT_RING(dev_priv->counter);
1129 OUT_RING(MI_USER_INTERRUPT);
1130 ADVANCE_LP_RING();
1131 }
1132
1133 return dev_priv->counter;
1134}
1135
1136void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1137{
1138 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1139 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1140
1141 if (dev_priv->trace_irq_seqno == 0)
1142 render_ring->user_irq_get(render_ring);
1143
1144 dev_priv->trace_irq_seqno = seqno;
1145}
1146
1147static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1148{
1149 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1150 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1151 int ret = 0;
1152 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1153
1154 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1155 READ_BREADCRUMB(dev_priv));
1156
1157 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1158 if (master_priv->sarea_priv)
1159 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1160 return 0;
1161 }
1162
1163 if (master_priv->sarea_priv)
1164 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1165
1166 render_ring->user_irq_get(render_ring);
1167 DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1168 READ_BREADCRUMB(dev_priv) >= irq_nr);
1169 render_ring->user_irq_put(render_ring);
1170
1171 if (ret == -EBUSY) {
1172 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1173 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1174 }
1175
1176 return ret;
1177}
1178
1179/* Needs the lock as it touches the ring.
1180 */
1181int i915_irq_emit(struct drm_device *dev, void *data,
1182 struct drm_file *file_priv)
1183{
1184 drm_i915_private_t *dev_priv = dev->dev_private;
1185 drm_i915_irq_emit_t *emit = data;
1186 int result;
1187
1188 if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1189 DRM_ERROR("called with no initialization\n");
1190 return -EINVAL;
1191 }
1192
1193 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1194
1195 mutex_lock(&dev->struct_mutex);
1196 result = i915_emit_irq(dev);
1197 mutex_unlock(&dev->struct_mutex);
1198
1199 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1200 DRM_ERROR("copy_to_user\n");
1201 return -EFAULT;
1202 }
1203
1204 return 0;
1205}
1206
1207/* Doesn't need the hardware lock.
1208 */
1209int i915_irq_wait(struct drm_device *dev, void *data,
1210 struct drm_file *file_priv)
1211{
1212 drm_i915_private_t *dev_priv = dev->dev_private;
1213 drm_i915_irq_wait_t *irqwait = data;
1214
1215 if (!dev_priv) {
1216 DRM_ERROR("called with no initialization\n");
1217 return -EINVAL;
1218 }
1219
1220 return i915_wait_irq(dev, irqwait->irq_seq);
1221}
1222
1223/* Called from drm generic code, passed 'crtc' which
1224 * we use as a pipe index
1225 */
1226int i915_enable_vblank(struct drm_device *dev, int pipe)
1227{
1228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1229 unsigned long irqflags;
1230
1231 if (!i915_pipe_enabled(dev, pipe))
1232 return -EINVAL;
1233
1234 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1235 if (HAS_PCH_SPLIT(dev))
1236 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1237 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1238 else if (INTEL_INFO(dev)->gen >= 4)
1239 i915_enable_pipestat(dev_priv, pipe,
1240 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1241 else
1242 i915_enable_pipestat(dev_priv, pipe,
1243 PIPE_VBLANK_INTERRUPT_ENABLE);
1244 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1245 return 0;
1246}
1247
1248/* Called from drm generic code, passed 'crtc' which
1249 * we use as a pipe index
1250 */
1251void i915_disable_vblank(struct drm_device *dev, int pipe)
1252{
1253 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1254 unsigned long irqflags;
1255
1256 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1257 if (HAS_PCH_SPLIT(dev))
1258 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1259 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1260 else
1261 i915_disable_pipestat(dev_priv, pipe,
1262 PIPE_VBLANK_INTERRUPT_ENABLE |
1263 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1264 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1265}
1266
1267void i915_enable_interrupt (struct drm_device *dev)
1268{
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270
1271 if (!HAS_PCH_SPLIT(dev))
1272 intel_opregion_enable_asle(dev);
1273 dev_priv->irq_enabled = 1;
1274}
1275
1276
1277/* Set the vblank monitor pipe
1278 */
1279int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1280 struct drm_file *file_priv)
1281{
1282 drm_i915_private_t *dev_priv = dev->dev_private;
1283
1284 if (!dev_priv) {
1285 DRM_ERROR("called with no initialization\n");
1286 return -EINVAL;
1287 }
1288
1289 return 0;
1290}
1291
1292int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1293 struct drm_file *file_priv)
1294{
1295 drm_i915_private_t *dev_priv = dev->dev_private;
1296 drm_i915_vblank_pipe_t *pipe = data;
1297
1298 if (!dev_priv) {
1299 DRM_ERROR("called with no initialization\n");
1300 return -EINVAL;
1301 }
1302
1303 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1304
1305 return 0;
1306}
1307
1308/**
1309 * Schedule buffer swap at given vertical blank.
1310 */
1311int i915_vblank_swap(struct drm_device *dev, void *data,
1312 struct drm_file *file_priv)
1313{
1314 /* The delayed swap mechanism was fundamentally racy, and has been
1315 * removed. The model was that the client requested a delayed flip/swap
1316 * from the kernel, then waited for vblank before continuing to perform
1317 * rendering. The problem was that the kernel might wake the client
1318 * up before it dispatched the vblank swap (since the lock has to be
1319 * held while touching the ringbuffer), in which case the client would
1320 * clear and start the next frame before the swap occurred, and
1321 * flicker would occur in addition to likely missing the vblank.
1322 *
1323 * In the absence of this ioctl, userland falls back to a correct path
1324 * of waiting for a vblank, then dispatching the swap on its own.
1325 * Context switching to userland and back is plenty fast enough for
1326 * meeting the requirements of vblank swapping.
1327 */
1328 return -EINVAL;
1329}
1330
1331static u32
1332ring_last_seqno(struct intel_ring_buffer *ring)
1333{
1334 return list_entry(ring->request_list.prev,
1335 struct drm_i915_gem_request, list)->seqno;
1336}
1337
1338static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1339{
1340 if (list_empty(&ring->request_list) ||
1341 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1342 /* Issue a wake-up to catch stuck h/w. */
1343 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1344 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1345 ring->name,
1346 ring->waiting_seqno,
1347 ring->get_seqno(ring));
1348 wake_up_all(&ring->irq_queue);
1349 *err = true;
1350 }
1351 return true;
1352 }
1353 return false;
1354}
1355
1356/**
1357 * This is called when the chip hasn't reported back with completed
1358 * batchbuffers in a long time. The first time this is called we simply record
1359 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1360 * again, we assume the chip is wedged and try to fix it.
1361 */
1362void i915_hangcheck_elapsed(unsigned long data)
1363{
1364 struct drm_device *dev = (struct drm_device *)data;
1365 drm_i915_private_t *dev_priv = dev->dev_private;
1366 uint32_t acthd, instdone, instdone1;
1367 bool err = false;
1368
1369 /* If all work is done then ACTHD clearly hasn't advanced. */
1370 if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) &&
1371 i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) &&
1372 i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) {
1373 dev_priv->hangcheck_count = 0;
1374 if (err)
1375 goto repeat;
1376 return;
1377 }
1378
1379 if (INTEL_INFO(dev)->gen < 4) {
1380 acthd = I915_READ(ACTHD);
1381 instdone = I915_READ(INSTDONE);
1382 instdone1 = 0;
1383 } else {
1384 acthd = I915_READ(ACTHD_I965);
1385 instdone = I915_READ(INSTDONE_I965);
1386 instdone1 = I915_READ(INSTDONE1);
1387 }
1388
1389 if (dev_priv->last_acthd == acthd &&
1390 dev_priv->last_instdone == instdone &&
1391 dev_priv->last_instdone1 == instdone1) {
1392 if (dev_priv->hangcheck_count++ > 1) {
1393 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1394
1395 if (!IS_GEN2(dev)) {
1396 /* Is the chip hanging on a WAIT_FOR_EVENT?
1397 * If so we can simply poke the RB_WAIT bit
1398 * and break the hang. This should work on
1399 * all but the second generation chipsets.
1400 */
1401 u32 tmp = I915_READ(PRB0_CTL);
1402 if (tmp & RING_WAIT) {
1403 I915_WRITE(PRB0_CTL, tmp);
1404 POSTING_READ(PRB0_CTL);
1405 goto repeat;
1406 }
1407 }
1408
1409 i915_handle_error(dev, true);
1410 return;
1411 }
1412 } else {
1413 dev_priv->hangcheck_count = 0;
1414
1415 dev_priv->last_acthd = acthd;
1416 dev_priv->last_instdone = instdone;
1417 dev_priv->last_instdone1 = instdone1;
1418 }
1419
1420repeat:
1421 /* Reset timer case chip hangs without another request being added */
1422 mod_timer(&dev_priv->hangcheck_timer,
1423 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1424}
1425
1426/* drm_dma.h hooks
1427*/
1428static void ironlake_irq_preinstall(struct drm_device *dev)
1429{
1430 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1431
1432 I915_WRITE(HWSTAM, 0xeffe);
1433
1434 /* XXX hotplug from PCH */
1435
1436 I915_WRITE(DEIMR, 0xffffffff);
1437 I915_WRITE(DEIER, 0x0);
1438 (void) I915_READ(DEIER);
1439
1440 /* and GT */
1441 I915_WRITE(GTIMR, 0xffffffff);
1442 I915_WRITE(GTIER, 0x0);
1443 (void) I915_READ(GTIER);
1444
1445 /* south display irq */
1446 I915_WRITE(SDEIMR, 0xffffffff);
1447 I915_WRITE(SDEIER, 0x0);
1448 (void) I915_READ(SDEIER);
1449}
1450
1451static int ironlake_irq_postinstall(struct drm_device *dev)
1452{
1453 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1454 /* enable kind of interrupts always enabled */
1455 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1456 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1457 u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1458 u32 hotplug_mask;
1459
1460 dev_priv->irq_mask_reg = ~display_mask;
1461 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1462
1463 /* should always can generate irq */
1464 I915_WRITE(DEIIR, I915_READ(DEIIR));
1465 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1466 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1467 (void) I915_READ(DEIER);
1468
1469 if (IS_GEN6(dev)) {
1470 render_mask =
1471 GT_PIPE_NOTIFY |
1472 GT_GEN6_BSD_USER_INTERRUPT |
1473 GT_BLT_USER_INTERRUPT;
1474 }
1475
1476 dev_priv->gt_irq_mask_reg = ~render_mask;
1477 dev_priv->gt_irq_enable_reg = render_mask;
1478
1479 I915_WRITE(GTIIR, I915_READ(GTIIR));
1480 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1481 if (IS_GEN6(dev)) {
1482 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1483 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1484 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1485 }
1486
1487 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1488 (void) I915_READ(GTIER);
1489
1490 if (HAS_PCH_CPT(dev)) {
1491 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT |
1492 SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1493 } else {
1494 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1495 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1496 }
1497
1498 dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1499 dev_priv->pch_irq_enable_reg = hotplug_mask;
1500
1501 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1502 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1503 I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1504 (void) I915_READ(SDEIER);
1505
1506 if (IS_IRONLAKE_M(dev)) {
1507 /* Clear & enable PCU event interrupts */
1508 I915_WRITE(DEIIR, DE_PCU_EVENT);
1509 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1510 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1511 }
1512
1513 return 0;
1514}
1515
1516void i915_driver_irq_preinstall(struct drm_device * dev)
1517{
1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1519
1520 atomic_set(&dev_priv->irq_received, 0);
1521
1522 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1523 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1524
1525 if (HAS_PCH_SPLIT(dev)) {
1526 ironlake_irq_preinstall(dev);
1527 return;
1528 }
1529
1530 if (I915_HAS_HOTPLUG(dev)) {
1531 I915_WRITE(PORT_HOTPLUG_EN, 0);
1532 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1533 }
1534
1535 I915_WRITE(HWSTAM, 0xeffe);
1536 I915_WRITE(PIPEASTAT, 0);
1537 I915_WRITE(PIPEBSTAT, 0);
1538 I915_WRITE(IMR, 0xffffffff);
1539 I915_WRITE(IER, 0x0);
1540 (void) I915_READ(IER);
1541}
1542
1543/*
1544 * Must be called after intel_modeset_init or hotplug interrupts won't be
1545 * enabled correctly.
1546 */
1547int i915_driver_irq_postinstall(struct drm_device *dev)
1548{
1549 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1550 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1551 u32 error_mask;
1552
1553 DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1554 if (HAS_BSD(dev))
1555 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1556 if (HAS_BLT(dev))
1557 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1558
1559 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1560
1561 if (HAS_PCH_SPLIT(dev))
1562 return ironlake_irq_postinstall(dev);
1563
1564 /* Unmask the interrupts that we always want on. */
1565 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1566
1567 dev_priv->pipestat[0] = 0;
1568 dev_priv->pipestat[1] = 0;
1569
1570 if (I915_HAS_HOTPLUG(dev)) {
1571 /* Enable in IER... */
1572 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1573 /* and unmask in IMR */
1574 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1575 }
1576
1577 /*
1578 * Enable some error detection, note the instruction error mask
1579 * bit is reserved, so we leave it masked.
1580 */
1581 if (IS_G4X(dev)) {
1582 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1583 GM45_ERROR_MEM_PRIV |
1584 GM45_ERROR_CP_PRIV |
1585 I915_ERROR_MEMORY_REFRESH);
1586 } else {
1587 error_mask = ~(I915_ERROR_PAGE_TABLE |
1588 I915_ERROR_MEMORY_REFRESH);
1589 }
1590 I915_WRITE(EMR, error_mask);
1591
1592 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1593 I915_WRITE(IER, enable_mask);
1594 (void) I915_READ(IER);
1595
1596 if (I915_HAS_HOTPLUG(dev)) {
1597 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1598
1599 /* Note HDMI and DP share bits */
1600 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1601 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1602 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1603 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1604 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1605 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1606 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1607 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1608 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1609 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1610 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1611 hotplug_en |= CRT_HOTPLUG_INT_EN;
1612
1613 /* Programming the CRT detection parameters tends
1614 to generate a spurious hotplug event about three
1615 seconds later. So just do it once.
1616 */
1617 if (IS_G4X(dev))
1618 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1619 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1620 }
1621
1622 /* Ignore TV since it's buggy */
1623
1624 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1625 }
1626
1627 intel_opregion_enable_asle(dev);
1628
1629 return 0;
1630}
1631
1632static void ironlake_irq_uninstall(struct drm_device *dev)
1633{
1634 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1635 I915_WRITE(HWSTAM, 0xffffffff);
1636
1637 I915_WRITE(DEIMR, 0xffffffff);
1638 I915_WRITE(DEIER, 0x0);
1639 I915_WRITE(DEIIR, I915_READ(DEIIR));
1640
1641 I915_WRITE(GTIMR, 0xffffffff);
1642 I915_WRITE(GTIER, 0x0);
1643 I915_WRITE(GTIIR, I915_READ(GTIIR));
1644}
1645
1646void i915_driver_irq_uninstall(struct drm_device * dev)
1647{
1648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1649
1650 if (!dev_priv)
1651 return;
1652
1653 dev_priv->vblank_pipe = 0;
1654
1655 if (HAS_PCH_SPLIT(dev)) {
1656 ironlake_irq_uninstall(dev);
1657 return;
1658 }
1659
1660 if (I915_HAS_HOTPLUG(dev)) {
1661 I915_WRITE(PORT_HOTPLUG_EN, 0);
1662 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1663 }
1664
1665 I915_WRITE(HWSTAM, 0xffffffff);
1666 I915_WRITE(PIPEASTAT, 0);
1667 I915_WRITE(PIPEBSTAT, 0);
1668 I915_WRITE(IMR, 0xffffffff);
1669 I915_WRITE(IER, 0x0);
1670
1671 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1672 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1673 I915_WRITE(IIR, I915_READ(IIR));
1674}
Linux kernel - Deliverables
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