| 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_edid.h> |
| 28 | #include "intel_drv.h" |
| 29 | #include "i915_drv.h" |
| 30 | |
| 31 | /** |
| 32 | * DOC: High Definition Audio over HDMI and Display Port |
| 33 | * |
| 34 | * The graphics and audio drivers together support High Definition Audio over |
| 35 | * HDMI and Display Port. The audio programming sequences are divided into audio |
| 36 | * codec and controller enable and disable sequences. The graphics driver |
| 37 | * handles the audio codec sequences, while the audio driver handles the audio |
| 38 | * controller sequences. |
| 39 | * |
| 40 | * The disable sequences must be performed before disabling the transcoder or |
| 41 | * port. The enable sequences may only be performed after enabling the |
| 42 | * transcoder and port, and after completed link training. |
| 43 | * |
| 44 | * The codec and controller sequences could be done either parallel or serial, |
| 45 | * but generally the ELDV/PD change in the codec sequence indicates to the audio |
| 46 | * driver that the controller sequence should start. Indeed, most of the |
| 47 | * co-operation between the graphics and audio drivers is handled via audio |
| 48 | * related registers. (The notable exception is the power management, not |
| 49 | * covered here.) |
| 50 | */ |
| 51 | |
| 52 | static const struct { |
| 53 | int clock; |
| 54 | u32 config; |
| 55 | } hdmi_audio_clock[] = { |
| 56 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
| 57 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
| 58 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
| 59 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
| 60 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
| 61 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
| 62 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
| 63 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
| 64 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
| 65 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
| 66 | }; |
| 67 | |
| 68 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
| 69 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
| 70 | { |
| 71 | int i; |
| 72 | |
| 73 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
| 74 | if (mode->clock == hdmi_audio_clock[i].clock) |
| 75 | break; |
| 76 | } |
| 77 | |
| 78 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
| 79 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
| 80 | i = 1; |
| 81 | } |
| 82 | |
| 83 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
| 84 | hdmi_audio_clock[i].clock, |
| 85 | hdmi_audio_clock[i].config); |
| 86 | |
| 87 | return hdmi_audio_clock[i].config; |
| 88 | } |
| 89 | |
| 90 | static bool intel_eld_uptodate(struct drm_connector *connector, |
| 91 | int reg_eldv, uint32_t bits_eldv, |
| 92 | int reg_elda, uint32_t bits_elda, |
| 93 | int reg_edid) |
| 94 | { |
| 95 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 96 | uint8_t *eld = connector->eld; |
| 97 | uint32_t tmp; |
| 98 | int i; |
| 99 | |
| 100 | tmp = I915_READ(reg_eldv); |
| 101 | tmp &= bits_eldv; |
| 102 | |
| 103 | if (!tmp) |
| 104 | return false; |
| 105 | |
| 106 | tmp = I915_READ(reg_elda); |
| 107 | tmp &= ~bits_elda; |
| 108 | I915_WRITE(reg_elda, tmp); |
| 109 | |
| 110 | for (i = 0; i < drm_eld_size(eld) / 4; i++) |
| 111 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
| 112 | return false; |
| 113 | |
| 114 | return true; |
| 115 | } |
| 116 | |
| 117 | static void g4x_audio_codec_disable(struct intel_encoder *encoder) |
| 118 | { |
| 119 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 120 | uint32_t eldv, tmp; |
| 121 | |
| 122 | DRM_DEBUG_KMS("Disable audio codec\n"); |
| 123 | |
| 124 | tmp = I915_READ(G4X_AUD_VID_DID); |
| 125 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) |
| 126 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 127 | else |
| 128 | eldv = G4X_ELDV_DEVCTG; |
| 129 | |
| 130 | /* Invalidate ELD */ |
| 131 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
| 132 | tmp &= ~eldv; |
| 133 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
| 134 | } |
| 135 | |
| 136 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
| 137 | struct intel_encoder *encoder, |
| 138 | struct drm_display_mode *mode) |
| 139 | { |
| 140 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 141 | uint8_t *eld = connector->eld; |
| 142 | uint32_t eldv; |
| 143 | uint32_t tmp; |
| 144 | int len, i; |
| 145 | |
| 146 | DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); |
| 147 | |
| 148 | tmp = I915_READ(G4X_AUD_VID_DID); |
| 149 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) |
| 150 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 151 | else |
| 152 | eldv = G4X_ELDV_DEVCTG; |
| 153 | |
| 154 | if (intel_eld_uptodate(connector, |
| 155 | G4X_AUD_CNTL_ST, eldv, |
| 156 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
| 157 | G4X_HDMIW_HDMIEDID)) |
| 158 | return; |
| 159 | |
| 160 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
| 161 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
| 162 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
| 163 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
| 164 | |
| 165 | len = min(drm_eld_size(eld) / 4, len); |
| 166 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 167 | for (i = 0; i < len; i++) |
| 168 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
| 169 | |
| 170 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
| 171 | tmp |= eldv; |
| 172 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
| 173 | } |
| 174 | |
| 175 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
| 176 | { |
| 177 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 178 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 179 | enum pipe pipe = intel_crtc->pipe; |
| 180 | uint32_t tmp; |
| 181 | |
| 182 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
| 183 | |
| 184 | /* Disable timestamps */ |
| 185 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
| 186 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 187 | tmp |= AUD_CONFIG_N_PROG_ENABLE; |
| 188 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; |
| 189 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; |
| 190 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 191 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 192 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
| 193 | |
| 194 | /* Invalidate ELD */ |
| 195 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
| 196 | tmp &= ~AUDIO_ELD_VALID(pipe); |
| 197 | tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); |
| 198 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
| 199 | } |
| 200 | |
| 201 | static void hsw_audio_codec_enable(struct drm_connector *connector, |
| 202 | struct intel_encoder *encoder, |
| 203 | struct drm_display_mode *mode) |
| 204 | { |
| 205 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 206 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 207 | enum pipe pipe = intel_crtc->pipe; |
| 208 | const uint8_t *eld = connector->eld; |
| 209 | uint32_t tmp; |
| 210 | int len, i; |
| 211 | |
| 212 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
| 213 | pipe_name(pipe), drm_eld_size(eld)); |
| 214 | |
| 215 | /* Enable audio presence detect, invalidate ELD */ |
| 216 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
| 217 | tmp |= AUDIO_OUTPUT_ENABLE(pipe); |
| 218 | tmp &= ~AUDIO_ELD_VALID(pipe); |
| 219 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
| 220 | |
| 221 | /* |
| 222 | * FIXME: We're supposed to wait for vblank here, but we have vblanks |
| 223 | * disabled during the mode set. The proper fix would be to push the |
| 224 | * rest of the setup into a vblank work item, queued here, but the |
| 225 | * infrastructure is not there yet. |
| 226 | */ |
| 227 | |
| 228 | /* Reset ELD write address */ |
| 229 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); |
| 230 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
| 231 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
| 232 | |
| 233 | /* Up to 84 bytes of hw ELD buffer */ |
| 234 | len = min(drm_eld_size(eld), 84); |
| 235 | for (i = 0; i < len / 4; i++) |
| 236 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
| 237 | |
| 238 | /* ELD valid */ |
| 239 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
| 240 | tmp |= AUDIO_ELD_VALID(pipe); |
| 241 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
| 242 | |
| 243 | /* Enable timestamps */ |
| 244 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
| 245 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 246 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
| 247 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
| 248 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 249 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 250 | else |
| 251 | tmp |= audio_config_hdmi_pixel_clock(mode); |
| 252 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
| 253 | } |
| 254 | |
| 255 | static void ilk_audio_codec_disable(struct intel_encoder *encoder) |
| 256 | { |
| 257 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 258 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 259 | struct intel_digital_port *intel_dig_port = |
| 260 | enc_to_dig_port(&encoder->base); |
| 261 | enum port port = intel_dig_port->port; |
| 262 | enum pipe pipe = intel_crtc->pipe; |
| 263 | uint32_t tmp, eldv; |
| 264 | int aud_config; |
| 265 | int aud_cntrl_st2; |
| 266 | |
| 267 | DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", |
| 268 | port_name(port), pipe_name(pipe)); |
| 269 | |
| 270 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 271 | aud_config = IBX_AUD_CFG(pipe); |
| 272 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
| 273 | } else if (IS_VALLEYVIEW(dev_priv)) { |
| 274 | aud_config = VLV_AUD_CFG(pipe); |
| 275 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
| 276 | } else { |
| 277 | aud_config = CPT_AUD_CFG(pipe); |
| 278 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
| 279 | } |
| 280 | |
| 281 | /* Disable timestamps */ |
| 282 | tmp = I915_READ(aud_config); |
| 283 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 284 | tmp |= AUD_CONFIG_N_PROG_ENABLE; |
| 285 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; |
| 286 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; |
| 287 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 288 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 289 | I915_WRITE(aud_config, tmp); |
| 290 | |
| 291 | if (WARN_ON(!port)) { |
| 292 | eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | |
| 293 | IBX_ELD_VALID(PORT_D); |
| 294 | } else { |
| 295 | eldv = IBX_ELD_VALID(port); |
| 296 | } |
| 297 | |
| 298 | /* Invalidate ELD */ |
| 299 | tmp = I915_READ(aud_cntrl_st2); |
| 300 | tmp &= ~eldv; |
| 301 | I915_WRITE(aud_cntrl_st2, tmp); |
| 302 | } |
| 303 | |
| 304 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
| 305 | struct intel_encoder *encoder, |
| 306 | struct drm_display_mode *mode) |
| 307 | { |
| 308 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 309 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 310 | struct intel_digital_port *intel_dig_port = |
| 311 | enc_to_dig_port(&encoder->base); |
| 312 | enum port port = intel_dig_port->port; |
| 313 | enum pipe pipe = intel_crtc->pipe; |
| 314 | uint8_t *eld = connector->eld; |
| 315 | uint32_t eldv; |
| 316 | uint32_t tmp; |
| 317 | int len, i; |
| 318 | int hdmiw_hdmiedid; |
| 319 | int aud_config; |
| 320 | int aud_cntl_st; |
| 321 | int aud_cntrl_st2; |
| 322 | |
| 323 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", |
| 324 | port_name(port), pipe_name(pipe), drm_eld_size(eld)); |
| 325 | |
| 326 | /* |
| 327 | * FIXME: We're supposed to wait for vblank here, but we have vblanks |
| 328 | * disabled during the mode set. The proper fix would be to push the |
| 329 | * rest of the setup into a vblank work item, queued here, but the |
| 330 | * infrastructure is not there yet. |
| 331 | */ |
| 332 | |
| 333 | if (HAS_PCH_IBX(connector->dev)) { |
| 334 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
| 335 | aud_config = IBX_AUD_CFG(pipe); |
| 336 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
| 337 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
| 338 | } else if (IS_VALLEYVIEW(connector->dev)) { |
| 339 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
| 340 | aud_config = VLV_AUD_CFG(pipe); |
| 341 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
| 342 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
| 343 | } else { |
| 344 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
| 345 | aud_config = CPT_AUD_CFG(pipe); |
| 346 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
| 347 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
| 348 | } |
| 349 | |
| 350 | if (WARN_ON(!port)) { |
| 351 | eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | |
| 352 | IBX_ELD_VALID(PORT_D); |
| 353 | } else { |
| 354 | eldv = IBX_ELD_VALID(port); |
| 355 | } |
| 356 | |
| 357 | /* Invalidate ELD */ |
| 358 | tmp = I915_READ(aud_cntrl_st2); |
| 359 | tmp &= ~eldv; |
| 360 | I915_WRITE(aud_cntrl_st2, tmp); |
| 361 | |
| 362 | /* Reset ELD write address */ |
| 363 | tmp = I915_READ(aud_cntl_st); |
| 364 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
| 365 | I915_WRITE(aud_cntl_st, tmp); |
| 366 | |
| 367 | /* Up to 84 bytes of hw ELD buffer */ |
| 368 | len = min(drm_eld_size(eld), 84); |
| 369 | for (i = 0; i < len / 4; i++) |
| 370 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 371 | |
| 372 | /* ELD valid */ |
| 373 | tmp = I915_READ(aud_cntrl_st2); |
| 374 | tmp |= eldv; |
| 375 | I915_WRITE(aud_cntrl_st2, tmp); |
| 376 | |
| 377 | /* Enable timestamps */ |
| 378 | tmp = I915_READ(aud_config); |
| 379 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 380 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
| 381 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
| 382 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 383 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 384 | else |
| 385 | tmp |= audio_config_hdmi_pixel_clock(mode); |
| 386 | I915_WRITE(aud_config, tmp); |
| 387 | } |
| 388 | |
| 389 | /** |
| 390 | * intel_audio_codec_enable - Enable the audio codec for HD audio |
| 391 | * @intel_encoder: encoder on which to enable audio |
| 392 | * |
| 393 | * The enable sequences may only be performed after enabling the transcoder and |
| 394 | * port, and after completed link training. |
| 395 | */ |
| 396 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) |
| 397 | { |
| 398 | struct drm_encoder *encoder = &intel_encoder->base; |
| 399 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
| 400 | struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
| 401 | struct drm_connector *connector; |
| 402 | struct drm_device *dev = encoder->dev; |
| 403 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 404 | |
| 405 | connector = drm_select_eld(encoder, mode); |
| 406 | if (!connector) |
| 407 | return; |
| 408 | |
| 409 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 410 | connector->base.id, |
| 411 | connector->name, |
| 412 | connector->encoder->base.id, |
| 413 | connector->encoder->name); |
| 414 | |
| 415 | /* ELD Conn_Type */ |
| 416 | connector->eld[5] &= ~(3 << 2); |
| 417 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 418 | connector->eld[5] |= (1 << 2); |
| 419 | |
| 420 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
| 421 | |
| 422 | if (dev_priv->display.audio_codec_enable) |
| 423 | dev_priv->display.audio_codec_enable(connector, intel_encoder, mode); |
| 424 | } |
| 425 | |
| 426 | /** |
| 427 | * intel_audio_codec_disable - Disable the audio codec for HD audio |
| 428 | * @encoder: encoder on which to disable audio |
| 429 | * |
| 430 | * The disable sequences must be performed before disabling the transcoder or |
| 431 | * port. |
| 432 | */ |
| 433 | void intel_audio_codec_disable(struct intel_encoder *encoder) |
| 434 | { |
| 435 | struct drm_device *dev = encoder->base.dev; |
| 436 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 437 | |
| 438 | if (dev_priv->display.audio_codec_disable) |
| 439 | dev_priv->display.audio_codec_disable(encoder); |
| 440 | } |
| 441 | |
| 442 | /** |
| 443 | * intel_init_audio - Set up chip specific audio functions |
| 444 | * @dev: drm device |
| 445 | */ |
| 446 | void intel_init_audio(struct drm_device *dev) |
| 447 | { |
| 448 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 449 | |
| 450 | if (IS_G4X(dev)) { |
| 451 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
| 452 | dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; |
| 453 | } else if (IS_VALLEYVIEW(dev)) { |
| 454 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
| 455 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
| 456 | } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { |
| 457 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
| 458 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; |
| 459 | } else if (HAS_PCH_SPLIT(dev)) { |
| 460 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
| 461 | dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; |
| 462 | } |
| 463 | } |