| 1 | /* |
| 2 | * Copyright © 2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define CTM_COEFF_SIGN (1ULL << 63) |
| 28 | |
| 29 | #define CTM_COEFF_1_0 (1ULL << 32) |
| 30 | #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) |
| 31 | #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) |
| 32 | #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) |
| 33 | #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) |
| 34 | #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) |
| 35 | #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) |
| 36 | |
| 37 | #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) |
| 38 | |
| 39 | #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) |
| 40 | #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) |
| 41 | |
| 42 | #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) |
| 43 | |
| 44 | /* |
| 45 | * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point |
| 46 | * format). This macro takes the coefficient we want transformed and the |
| 47 | * number of fractional bits. |
| 48 | * |
| 49 | * We only have a 9 bits precision window which slides depending on the value |
| 50 | * of the CTM coefficient and we write the value from bit 3. We also round the |
| 51 | * value. |
| 52 | */ |
| 53 | #define I9XX_CSC_COEFF_FP(coeff, fbits) \ |
| 54 | (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) |
| 55 | |
| 56 | #define I9XX_CSC_COEFF_LIMITED_RANGE \ |
| 57 | I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9) |
| 58 | #define I9XX_CSC_COEFF_1_0 \ |
| 59 | ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8)) |
| 60 | |
| 61 | static bool crtc_state_is_legacy(struct drm_crtc_state *state) |
| 62 | { |
| 63 | return !state->degamma_lut && |
| 64 | !state->ctm && |
| 65 | state->gamma_lut && |
| 66 | state->gamma_lut->length == LEGACY_LUT_LENGTH; |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * When using limited range, multiply the matrix given by userspace by |
| 71 | * the matrix that we would use for the limited range. We do the |
| 72 | * multiplication in U2.30 format. |
| 73 | */ |
| 74 | static void ctm_mult_by_limited(uint64_t *result, int64_t *input) |
| 75 | { |
| 76 | int i; |
| 77 | |
| 78 | for (i = 0; i < 9; i++) |
| 79 | result[i] = 0; |
| 80 | |
| 81 | for (i = 0; i < 3; i++) { |
| 82 | int64_t user_coeff = input[i * 3 + i]; |
| 83 | uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2; |
| 84 | uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), |
| 85 | 0, |
| 86 | CTM_COEFF_4_0 - 1) >> 2; |
| 87 | |
| 88 | result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27; |
| 89 | if (CTM_COEFF_NEGATIVE(user_coeff)) |
| 90 | result[i * 3 + i] |= CTM_COEFF_SIGN; |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | /* Set up the pipe CSC unit. */ |
| 95 | static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) |
| 96 | { |
| 97 | struct drm_crtc *crtc = crtc_state->crtc; |
| 98 | struct drm_device *dev = crtc->dev; |
| 99 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 101 | int i, pipe = intel_crtc->pipe; |
| 102 | uint16_t coeffs[9] = { 0, }; |
| 103 | |
| 104 | if (crtc_state->ctm) { |
| 105 | struct drm_color_ctm *ctm = |
| 106 | (struct drm_color_ctm *)crtc_state->ctm->data; |
| 107 | uint64_t input[9] = { 0, }; |
| 108 | |
| 109 | if (intel_crtc->config->limited_color_range) { |
| 110 | ctm_mult_by_limited(input, ctm->matrix); |
| 111 | } else { |
| 112 | for (i = 0; i < ARRAY_SIZE(input); i++) |
| 113 | input[i] = ctm->matrix[i]; |
| 114 | } |
| 115 | |
| 116 | /* |
| 117 | * Convert fixed point S31.32 input to format supported by the |
| 118 | * hardware. |
| 119 | */ |
| 120 | for (i = 0; i < ARRAY_SIZE(coeffs); i++) { |
| 121 | uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i]; |
| 122 | |
| 123 | /* |
| 124 | * Clamp input value to min/max supported by |
| 125 | * hardware. |
| 126 | */ |
| 127 | abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); |
| 128 | |
| 129 | /* sign bit */ |
| 130 | if (CTM_COEFF_NEGATIVE(input[i])) |
| 131 | coeffs[i] |= 1 << 15; |
| 132 | |
| 133 | if (abs_coeff < CTM_COEFF_0_125) |
| 134 | coeffs[i] |= (3 << 12) | |
| 135 | I9XX_CSC_COEFF_FP(abs_coeff, 12); |
| 136 | else if (abs_coeff < CTM_COEFF_0_25) |
| 137 | coeffs[i] |= (2 << 12) | |
| 138 | I9XX_CSC_COEFF_FP(abs_coeff, 11); |
| 139 | else if (abs_coeff < CTM_COEFF_0_5) |
| 140 | coeffs[i] |= (1 << 12) | |
| 141 | I9XX_CSC_COEFF_FP(abs_coeff, 10); |
| 142 | else if (abs_coeff < CTM_COEFF_1_0) |
| 143 | coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9); |
| 144 | else if (abs_coeff < CTM_COEFF_2_0) |
| 145 | coeffs[i] |= (7 << 12) | |
| 146 | I9XX_CSC_COEFF_FP(abs_coeff, 8); |
| 147 | else |
| 148 | coeffs[i] |= (6 << 12) | |
| 149 | I9XX_CSC_COEFF_FP(abs_coeff, 7); |
| 150 | } |
| 151 | } else { |
| 152 | /* |
| 153 | * Load an identity matrix if no coefficients are provided. |
| 154 | * |
| 155 | * TODO: Check what kind of values actually come out of the |
| 156 | * pipe with these coeff/postoff values and adjust to get the |
| 157 | * best accuracy. Perhaps we even need to take the bpc value |
| 158 | * into consideration. |
| 159 | */ |
| 160 | for (i = 0; i < 3; i++) { |
| 161 | if (intel_crtc->config->limited_color_range) |
| 162 | coeffs[i * 3 + i] = |
| 163 | I9XX_CSC_COEFF_LIMITED_RANGE; |
| 164 | else |
| 165 | coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0; |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]); |
| 170 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16); |
| 171 | |
| 172 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]); |
| 173 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16); |
| 174 | |
| 175 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]); |
| 176 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16); |
| 177 | |
| 178 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
| 179 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
| 180 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
| 181 | |
| 182 | if (INTEL_INFO(dev)->gen > 6) { |
| 183 | uint16_t postoff = 0; |
| 184 | |
| 185 | if (intel_crtc->config->limited_color_range) |
| 186 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
| 187 | |
| 188 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
| 189 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
| 190 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
| 191 | |
| 192 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
| 193 | } else { |
| 194 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
| 195 | |
| 196 | if (intel_crtc->config->limited_color_range) |
| 197 | mode |= CSC_BLACK_SCREEN_OFFSET; |
| 198 | |
| 199 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | /* |
| 204 | * Set up the pipe CSC unit on CherryView. |
| 205 | */ |
| 206 | static void cherryview_load_csc_matrix(struct drm_crtc_state *state) |
| 207 | { |
| 208 | struct drm_crtc *crtc = state->crtc; |
| 209 | struct drm_device *dev = crtc->dev; |
| 210 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 211 | int pipe = to_intel_crtc(crtc)->pipe; |
| 212 | uint32_t mode; |
| 213 | |
| 214 | if (state->ctm) { |
| 215 | struct drm_color_ctm *ctm = |
| 216 | (struct drm_color_ctm *) state->ctm->data; |
| 217 | uint16_t coeffs[9] = { 0, }; |
| 218 | int i; |
| 219 | |
| 220 | for (i = 0; i < ARRAY_SIZE(coeffs); i++) { |
| 221 | uint64_t abs_coeff = |
| 222 | ((1ULL << 63) - 1) & ctm->matrix[i]; |
| 223 | |
| 224 | /* Round coefficient. */ |
| 225 | abs_coeff += 1 << (32 - 13); |
| 226 | /* Clamp to hardware limits. */ |
| 227 | abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); |
| 228 | |
| 229 | /* Write coefficients in S3.12 format. */ |
| 230 | if (ctm->matrix[i] & (1ULL << 63)) |
| 231 | coeffs[i] = 1 << 15; |
| 232 | coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; |
| 233 | coeffs[i] |= (abs_coeff >> 20) & 0xfff; |
| 234 | } |
| 235 | |
| 236 | I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), |
| 237 | coeffs[1] << 16 | coeffs[0]); |
| 238 | I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), |
| 239 | coeffs[3] << 16 | coeffs[2]); |
| 240 | I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), |
| 241 | coeffs[5] << 16 | coeffs[4]); |
| 242 | I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), |
| 243 | coeffs[7] << 16 | coeffs[6]); |
| 244 | I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]); |
| 245 | } |
| 246 | |
| 247 | mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0); |
| 248 | if (!crtc_state_is_legacy(state)) { |
| 249 | mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | |
| 250 | (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0); |
| 251 | } |
| 252 | I915_WRITE(CGM_PIPE_MODE(pipe), mode); |
| 253 | } |
| 254 | |
| 255 | void intel_color_set_csc(struct drm_crtc_state *crtc_state) |
| 256 | { |
| 257 | struct drm_device *dev = crtc_state->crtc->dev; |
| 258 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 259 | |
| 260 | if (dev_priv->display.load_csc_matrix) |
| 261 | dev_priv->display.load_csc_matrix(crtc_state); |
| 262 | } |
| 263 | |
| 264 | /* Loads the legacy palette/gamma unit for the CRTC. */ |
| 265 | static void i9xx_load_luts_internal(struct drm_crtc *crtc, |
| 266 | struct drm_property_blob *blob) |
| 267 | { |
| 268 | struct drm_device *dev = crtc->dev; |
| 269 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 271 | enum pipe pipe = intel_crtc->pipe; |
| 272 | int i; |
| 273 | |
| 274 | if (HAS_GMCH_DISPLAY(dev)) { |
| 275 | if (intel_crtc->config->has_dsi_encoder) |
| 276 | assert_dsi_pll_enabled(dev_priv); |
| 277 | else |
| 278 | assert_pll_enabled(dev_priv, pipe); |
| 279 | } |
| 280 | |
| 281 | if (blob) { |
| 282 | struct drm_color_lut *lut = (struct drm_color_lut *) blob->data; |
| 283 | for (i = 0; i < 256; i++) { |
| 284 | uint32_t word = |
| 285 | (drm_color_lut_extract(lut[i].red, 8) << 16) | |
| 286 | (drm_color_lut_extract(lut[i].green, 8) << 8) | |
| 287 | drm_color_lut_extract(lut[i].blue, 8); |
| 288 | |
| 289 | if (HAS_GMCH_DISPLAY(dev)) |
| 290 | I915_WRITE(PALETTE(pipe, i), word); |
| 291 | else |
| 292 | I915_WRITE(LGC_PALETTE(pipe, i), word); |
| 293 | } |
| 294 | } else { |
| 295 | for (i = 0; i < 256; i++) { |
| 296 | uint32_t word = (i << 16) | (i << 8) | i; |
| 297 | |
| 298 | if (HAS_GMCH_DISPLAY(dev)) |
| 299 | I915_WRITE(PALETTE(pipe, i), word); |
| 300 | else |
| 301 | I915_WRITE(LGC_PALETTE(pipe, i), word); |
| 302 | } |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | static void i9xx_load_luts(struct drm_crtc_state *crtc_state) |
| 307 | { |
| 308 | i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut); |
| 309 | } |
| 310 | |
| 311 | /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */ |
| 312 | static void haswell_load_luts(struct drm_crtc_state *crtc_state) |
| 313 | { |
| 314 | struct drm_crtc *crtc = crtc_state->crtc; |
| 315 | struct drm_device *dev = crtc->dev; |
| 316 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 318 | struct intel_crtc_state *intel_crtc_state = |
| 319 | to_intel_crtc_state(crtc_state); |
| 320 | bool reenable_ips = false; |
| 321 | |
| 322 | /* |
| 323 | * Workaround : Do not read or write the pipe palette/gamma data while |
| 324 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 325 | */ |
| 326 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
| 327 | (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) { |
| 328 | hsw_disable_ips(intel_crtc); |
| 329 | reenable_ips = true; |
| 330 | } |
| 331 | |
| 332 | intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; |
| 333 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
| 334 | |
| 335 | i9xx_load_luts(crtc_state); |
| 336 | |
| 337 | if (reenable_ips) |
| 338 | hsw_enable_ips(intel_crtc); |
| 339 | } |
| 340 | |
| 341 | /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ |
| 342 | static void broadwell_load_luts(struct drm_crtc_state *state) |
| 343 | { |
| 344 | struct drm_crtc *crtc = state->crtc; |
| 345 | struct drm_device *dev = crtc->dev; |
| 346 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 347 | struct intel_crtc_state *intel_state = to_intel_crtc_state(state); |
| 348 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
| 349 | uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size; |
| 350 | |
| 351 | if (crtc_state_is_legacy(state)) { |
| 352 | haswell_load_luts(state); |
| 353 | return; |
| 354 | } |
| 355 | |
| 356 | I915_WRITE(PREC_PAL_INDEX(pipe), |
| 357 | PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT); |
| 358 | |
| 359 | if (state->degamma_lut) { |
| 360 | struct drm_color_lut *lut = |
| 361 | (struct drm_color_lut *) state->degamma_lut->data; |
| 362 | |
| 363 | for (i = 0; i < lut_size; i++) { |
| 364 | uint32_t word = |
| 365 | drm_color_lut_extract(lut[i].red, 10) << 20 | |
| 366 | drm_color_lut_extract(lut[i].green, 10) << 10 | |
| 367 | drm_color_lut_extract(lut[i].blue, 10); |
| 368 | |
| 369 | I915_WRITE(PREC_PAL_DATA(pipe), word); |
| 370 | } |
| 371 | } else { |
| 372 | for (i = 0; i < lut_size; i++) { |
| 373 | uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); |
| 374 | |
| 375 | I915_WRITE(PREC_PAL_DATA(pipe), |
| 376 | (v << 20) | (v << 10) | v); |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | if (state->gamma_lut) { |
| 381 | struct drm_color_lut *lut = |
| 382 | (struct drm_color_lut *) state->gamma_lut->data; |
| 383 | |
| 384 | for (i = 0; i < lut_size; i++) { |
| 385 | uint32_t word = |
| 386 | (drm_color_lut_extract(lut[i].red, 10) << 20) | |
| 387 | (drm_color_lut_extract(lut[i].green, 10) << 10) | |
| 388 | drm_color_lut_extract(lut[i].blue, 10); |
| 389 | |
| 390 | I915_WRITE(PREC_PAL_DATA(pipe), word); |
| 391 | } |
| 392 | |
| 393 | /* Program the max register to clamp values > 1.0. */ |
| 394 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), |
| 395 | drm_color_lut_extract(lut[i].red, 16)); |
| 396 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), |
| 397 | drm_color_lut_extract(lut[i].green, 16)); |
| 398 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), |
| 399 | drm_color_lut_extract(lut[i].blue, 16)); |
| 400 | } else { |
| 401 | for (i = 0; i < lut_size; i++) { |
| 402 | uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); |
| 403 | |
| 404 | I915_WRITE(PREC_PAL_DATA(pipe), |
| 405 | (v << 20) | (v << 10) | v); |
| 406 | } |
| 407 | |
| 408 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1); |
| 409 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1); |
| 410 | I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1); |
| 411 | } |
| 412 | |
| 413 | intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; |
| 414 | I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT); |
| 415 | POSTING_READ(GAMMA_MODE(pipe)); |
| 416 | |
| 417 | /* |
| 418 | * Reset the index, otherwise it prevents the legacy palette to be |
| 419 | * written properly. |
| 420 | */ |
| 421 | I915_WRITE(PREC_PAL_INDEX(pipe), 0); |
| 422 | } |
| 423 | |
| 424 | /* Loads the palette/gamma unit for the CRTC on CherryView. */ |
| 425 | static void cherryview_load_luts(struct drm_crtc_state *state) |
| 426 | { |
| 427 | struct drm_crtc *crtc = state->crtc; |
| 428 | struct drm_device *dev = crtc->dev; |
| 429 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 430 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
| 431 | struct drm_color_lut *lut; |
| 432 | uint32_t i, lut_size; |
| 433 | uint32_t word0, word1; |
| 434 | |
| 435 | if (crtc_state_is_legacy(state)) { |
| 436 | /* Turn off degamma/gamma on CGM block. */ |
| 437 | I915_WRITE(CGM_PIPE_MODE(pipe), |
| 438 | (state->ctm ? CGM_PIPE_MODE_CSC : 0)); |
| 439 | i9xx_load_luts_internal(crtc, state->gamma_lut); |
| 440 | return; |
| 441 | } |
| 442 | |
| 443 | if (state->degamma_lut) { |
| 444 | lut = (struct drm_color_lut *) state->degamma_lut->data; |
| 445 | lut_size = INTEL_INFO(dev)->color.degamma_lut_size; |
| 446 | for (i = 0; i < lut_size; i++) { |
| 447 | /* Write LUT in U0.14 format. */ |
| 448 | word0 = |
| 449 | (drm_color_lut_extract(lut[i].green, 14) << 16) | |
| 450 | drm_color_lut_extract(lut[i].blue, 14); |
| 451 | word1 = drm_color_lut_extract(lut[i].red, 14); |
| 452 | |
| 453 | I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0); |
| 454 | I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1); |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | if (state->gamma_lut) { |
| 459 | lut = (struct drm_color_lut *) state->gamma_lut->data; |
| 460 | lut_size = INTEL_INFO(dev)->color.gamma_lut_size; |
| 461 | for (i = 0; i < lut_size; i++) { |
| 462 | /* Write LUT in U0.10 format. */ |
| 463 | word0 = |
| 464 | (drm_color_lut_extract(lut[i].green, 10) << 16) | |
| 465 | drm_color_lut_extract(lut[i].blue, 10); |
| 466 | word1 = drm_color_lut_extract(lut[i].red, 10); |
| 467 | |
| 468 | I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0); |
| 469 | I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1); |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | I915_WRITE(CGM_PIPE_MODE(pipe), |
| 474 | (state->ctm ? CGM_PIPE_MODE_CSC : 0) | |
| 475 | (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | |
| 476 | (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0)); |
| 477 | |
| 478 | /* |
| 479 | * Also program a linear LUT in the legacy block (behind the |
| 480 | * CGM block). |
| 481 | */ |
| 482 | i9xx_load_luts_internal(crtc, NULL); |
| 483 | } |
| 484 | |
| 485 | void intel_color_load_luts(struct drm_crtc_state *crtc_state) |
| 486 | { |
| 487 | struct drm_device *dev = crtc_state->crtc->dev; |
| 488 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 489 | |
| 490 | dev_priv->display.load_luts(crtc_state); |
| 491 | } |
| 492 | |
| 493 | int intel_color_check(struct drm_crtc *crtc, |
| 494 | struct drm_crtc_state *crtc_state) |
| 495 | { |
| 496 | struct drm_device *dev = crtc->dev; |
| 497 | size_t gamma_length, degamma_length; |
| 498 | |
| 499 | degamma_length = INTEL_INFO(dev)->color.degamma_lut_size * |
| 500 | sizeof(struct drm_color_lut); |
| 501 | gamma_length = INTEL_INFO(dev)->color.gamma_lut_size * |
| 502 | sizeof(struct drm_color_lut); |
| 503 | |
| 504 | /* |
| 505 | * We allow both degamma & gamma luts at the right size or |
| 506 | * NULL. |
| 507 | */ |
| 508 | if ((!crtc_state->degamma_lut || |
| 509 | crtc_state->degamma_lut->length == degamma_length) && |
| 510 | (!crtc_state->gamma_lut || |
| 511 | crtc_state->gamma_lut->length == gamma_length)) |
| 512 | return 0; |
| 513 | |
| 514 | /* |
| 515 | * We also allow no degamma lut and a gamma lut at the legacy |
| 516 | * size (256 entries). |
| 517 | */ |
| 518 | if (!crtc_state->degamma_lut && |
| 519 | crtc_state->gamma_lut && |
| 520 | crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH) |
| 521 | return 0; |
| 522 | |
| 523 | return -EINVAL; |
| 524 | } |
| 525 | |
| 526 | void intel_color_init(struct drm_crtc *crtc) |
| 527 | { |
| 528 | struct drm_device *dev = crtc->dev; |
| 529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 530 | |
| 531 | drm_mode_crtc_set_gamma_size(crtc, 256); |
| 532 | |
| 533 | if (IS_CHERRYVIEW(dev)) { |
| 534 | dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix; |
| 535 | dev_priv->display.load_luts = cherryview_load_luts; |
| 536 | } else if (IS_HASWELL(dev)) { |
| 537 | dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; |
| 538 | dev_priv->display.load_luts = haswell_load_luts; |
| 539 | } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) || |
| 540 | IS_BROXTON(dev) || IS_KABYLAKE(dev)) { |
| 541 | dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; |
| 542 | dev_priv->display.load_luts = broadwell_load_luts; |
| 543 | } else { |
| 544 | dev_priv->display.load_luts = i9xx_load_luts; |
| 545 | } |
| 546 | |
| 547 | /* Enable color management support when we have degamma & gamma LUTs. */ |
| 548 | if (INTEL_INFO(dev)->color.degamma_lut_size != 0 && |
| 549 | INTEL_INFO(dev)->color.gamma_lut_size != 0) |
| 550 | drm_helper_crtc_enable_color_mgmt(crtc, |
| 551 | INTEL_INFO(dev)->color.degamma_lut_size, |
| 552 | INTEL_INFO(dev)->color.gamma_lut_size); |
| 553 | } |