| 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "i915_drv.h" |
| 29 | #include "intel_drv.h" |
| 30 | |
| 31 | struct ddi_buf_trans { |
| 32 | u32 trans1; /* balance leg enable, de-emph level */ |
| 33 | u32 trans2; /* vref sel, vswing */ |
| 34 | }; |
| 35 | |
| 36 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
| 37 | * them for both DP and FDI transports, allowing those ports to |
| 38 | * automatically adapt to HDMI connections as well |
| 39 | */ |
| 40 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
| 41 | { 0x00FFFFFF, 0x0006000E }, |
| 42 | { 0x00D75FFF, 0x0005000A }, |
| 43 | { 0x00C30FFF, 0x00040006 }, |
| 44 | { 0x80AAAFFF, 0x000B0000 }, |
| 45 | { 0x00FFFFFF, 0x0005000A }, |
| 46 | { 0x00D75FFF, 0x000C0004 }, |
| 47 | { 0x80C30FFF, 0x000B0000 }, |
| 48 | { 0x00FFFFFF, 0x00040006 }, |
| 49 | { 0x80D75FFF, 0x000B0000 }, |
| 50 | }; |
| 51 | |
| 52 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
| 53 | { 0x00FFFFFF, 0x0007000E }, |
| 54 | { 0x00D75FFF, 0x000F000A }, |
| 55 | { 0x00C30FFF, 0x00060006 }, |
| 56 | { 0x00AAAFFF, 0x001E0000 }, |
| 57 | { 0x00FFFFFF, 0x000F000A }, |
| 58 | { 0x00D75FFF, 0x00160004 }, |
| 59 | { 0x00C30FFF, 0x001E0000 }, |
| 60 | { 0x00FFFFFF, 0x00060006 }, |
| 61 | { 0x00D75FFF, 0x001E0000 }, |
| 62 | }; |
| 63 | |
| 64 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
| 65 | /* Idx NT mV d T mV d db */ |
| 66 | { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ |
| 67 | { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ |
| 68 | { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ |
| 69 | { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ |
| 70 | { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ |
| 71 | { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ |
| 72 | { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ |
| 73 | { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ |
| 74 | { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ |
| 75 | { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ |
| 76 | { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ |
| 77 | { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ |
| 78 | }; |
| 79 | |
| 80 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
| 81 | { 0x00FFFFFF, 0x00000012 }, |
| 82 | { 0x00EBAFFF, 0x00020011 }, |
| 83 | { 0x00C71FFF, 0x0006000F }, |
| 84 | { 0x00AAAFFF, 0x000E000A }, |
| 85 | { 0x00FFFFFF, 0x00020011 }, |
| 86 | { 0x00DB6FFF, 0x0005000F }, |
| 87 | { 0x00BEEFFF, 0x000A000C }, |
| 88 | { 0x00FFFFFF, 0x0005000F }, |
| 89 | { 0x00DB6FFF, 0x000A000C }, |
| 90 | }; |
| 91 | |
| 92 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
| 93 | { 0x00FFFFFF, 0x0007000E }, |
| 94 | { 0x00D75FFF, 0x000E000A }, |
| 95 | { 0x00BEFFFF, 0x00140006 }, |
| 96 | { 0x80B2CFFF, 0x001B0002 }, |
| 97 | { 0x00FFFFFF, 0x000E000A }, |
| 98 | { 0x00DB6FFF, 0x00160005 }, |
| 99 | { 0x80C71FFF, 0x001A0002 }, |
| 100 | { 0x00F7DFFF, 0x00180004 }, |
| 101 | { 0x80D75FFF, 0x001B0002 }, |
| 102 | }; |
| 103 | |
| 104 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
| 105 | { 0x00FFFFFF, 0x0001000E }, |
| 106 | { 0x00D75FFF, 0x0004000A }, |
| 107 | { 0x00C30FFF, 0x00070006 }, |
| 108 | { 0x00AAAFFF, 0x000C0000 }, |
| 109 | { 0x00FFFFFF, 0x0004000A }, |
| 110 | { 0x00D75FFF, 0x00090004 }, |
| 111 | { 0x00C30FFF, 0x000C0000 }, |
| 112 | { 0x00FFFFFF, 0x00070006 }, |
| 113 | { 0x00D75FFF, 0x000C0000 }, |
| 114 | }; |
| 115 | |
| 116 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
| 117 | /* Idx NT mV d T mV df db */ |
| 118 | { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ |
| 119 | { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ |
| 120 | { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ |
| 121 | { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ |
| 122 | { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ |
| 123 | { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ |
| 124 | { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ |
| 125 | { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ |
| 126 | { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ |
| 127 | { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ |
| 128 | }; |
| 129 | |
| 130 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
| 131 | { 0x00000018, 0x000000a2 }, |
| 132 | { 0x00004014, 0x0000009B }, |
| 133 | { 0x00006012, 0x00000088 }, |
| 134 | { 0x00008010, 0x00000087 }, |
| 135 | { 0x00000018, 0x0000009B }, |
| 136 | { 0x00004014, 0x00000088 }, |
| 137 | { 0x00006012, 0x00000087 }, |
| 138 | { 0x00000018, 0x00000088 }, |
| 139 | { 0x00004014, 0x00000087 }, |
| 140 | }; |
| 141 | |
| 142 | /* eDP 1.4 low vswing translation parameters */ |
| 143 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
| 144 | { 0x00000018, 0x000000a8 }, |
| 145 | { 0x00002016, 0x000000ab }, |
| 146 | { 0x00006012, 0x000000a2 }, |
| 147 | { 0x00008010, 0x00000088 }, |
| 148 | { 0x00000018, 0x000000ab }, |
| 149 | { 0x00004014, 0x000000a2 }, |
| 150 | { 0x00006012, 0x000000a6 }, |
| 151 | { 0x00000018, 0x000000a2 }, |
| 152 | { 0x00005013, 0x0000009c }, |
| 153 | { 0x00000018, 0x00000088 }, |
| 154 | }; |
| 155 | |
| 156 | |
| 157 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
| 158 | /* Idx NT mV T mV db */ |
| 159 | { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */ |
| 160 | { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */ |
| 161 | { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */ |
| 162 | { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */ |
| 163 | { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */ |
| 164 | { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */ |
| 165 | { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */ |
| 166 | { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */ |
| 167 | { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */ |
| 168 | { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */ |
| 169 | }; |
| 170 | |
| 171 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
| 172 | { |
| 173 | struct drm_encoder *encoder = &intel_encoder->base; |
| 174 | int type = intel_encoder->type; |
| 175 | |
| 176 | if (type == INTEL_OUTPUT_DP_MST) { |
| 177 | struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary; |
| 178 | return intel_dig_port->port; |
| 179 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
| 180 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
| 181 | struct intel_digital_port *intel_dig_port = |
| 182 | enc_to_dig_port(encoder); |
| 183 | return intel_dig_port->port; |
| 184 | |
| 185 | } else if (type == INTEL_OUTPUT_ANALOG) { |
| 186 | return PORT_E; |
| 187 | |
| 188 | } else { |
| 189 | DRM_ERROR("Invalid DDI encoder type %d\n", type); |
| 190 | BUG(); |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | /* |
| 195 | * Starting with Haswell, DDI port buffers must be programmed with correct |
| 196 | * values in advance. The buffer values are different for FDI and DP modes, |
| 197 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
| 198 | * in either FDI or DP modes only, as HDMI connections will work with both |
| 199 | * of those |
| 200 | */ |
| 201 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
| 202 | { |
| 203 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 204 | u32 reg; |
| 205 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_800mV_0dB, |
| 206 | size; |
| 207 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
| 208 | const struct ddi_buf_trans *ddi_translations_fdi; |
| 209 | const struct ddi_buf_trans *ddi_translations_dp; |
| 210 | const struct ddi_buf_trans *ddi_translations_edp; |
| 211 | const struct ddi_buf_trans *ddi_translations_hdmi; |
| 212 | const struct ddi_buf_trans *ddi_translations; |
| 213 | |
| 214 | if (IS_SKYLAKE(dev)) { |
| 215 | ddi_translations_fdi = NULL; |
| 216 | ddi_translations_dp = skl_ddi_translations_dp; |
| 217 | n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
| 218 | if (dev_priv->vbt.edp_low_vswing) { |
| 219 | ddi_translations_edp = skl_ddi_translations_edp; |
| 220 | n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
| 221 | } else { |
| 222 | ddi_translations_edp = skl_ddi_translations_dp; |
| 223 | n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
| 224 | } |
| 225 | |
| 226 | ddi_translations_hdmi = skl_ddi_translations_hdmi; |
| 227 | n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
| 228 | hdmi_800mV_0dB = 7; |
| 229 | } else if (IS_BROADWELL(dev)) { |
| 230 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
| 231 | ddi_translations_dp = bdw_ddi_translations_dp; |
| 232 | ddi_translations_edp = bdw_ddi_translations_edp; |
| 233 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
| 234 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
| 235 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
| 236 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
| 237 | hdmi_800mV_0dB = 7; |
| 238 | } else if (IS_HASWELL(dev)) { |
| 239 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
| 240 | ddi_translations_dp = hsw_ddi_translations_dp; |
| 241 | ddi_translations_edp = hsw_ddi_translations_dp; |
| 242 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
| 243 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
| 244 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
| 245 | hdmi_800mV_0dB = 6; |
| 246 | } else { |
| 247 | WARN(1, "ddi translation table missing\n"); |
| 248 | ddi_translations_edp = bdw_ddi_translations_dp; |
| 249 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
| 250 | ddi_translations_dp = bdw_ddi_translations_dp; |
| 251 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
| 252 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
| 253 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
| 254 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
| 255 | hdmi_800mV_0dB = 7; |
| 256 | } |
| 257 | |
| 258 | switch (port) { |
| 259 | case PORT_A: |
| 260 | ddi_translations = ddi_translations_edp; |
| 261 | size = n_edp_entries; |
| 262 | break; |
| 263 | case PORT_B: |
| 264 | case PORT_C: |
| 265 | ddi_translations = ddi_translations_dp; |
| 266 | size = n_dp_entries; |
| 267 | break; |
| 268 | case PORT_D: |
| 269 | if (intel_dp_is_edp(dev, PORT_D)) { |
| 270 | ddi_translations = ddi_translations_edp; |
| 271 | size = n_edp_entries; |
| 272 | } else { |
| 273 | ddi_translations = ddi_translations_dp; |
| 274 | size = n_dp_entries; |
| 275 | } |
| 276 | break; |
| 277 | case PORT_E: |
| 278 | if (ddi_translations_fdi) |
| 279 | ddi_translations = ddi_translations_fdi; |
| 280 | else |
| 281 | ddi_translations = ddi_translations_dp; |
| 282 | size = n_dp_entries; |
| 283 | break; |
| 284 | default: |
| 285 | BUG(); |
| 286 | } |
| 287 | |
| 288 | for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) { |
| 289 | I915_WRITE(reg, ddi_translations[i].trans1); |
| 290 | reg += 4; |
| 291 | I915_WRITE(reg, ddi_translations[i].trans2); |
| 292 | reg += 4; |
| 293 | } |
| 294 | |
| 295 | /* Choose a good default if VBT is badly populated */ |
| 296 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || |
| 297 | hdmi_level >= n_hdmi_entries) |
| 298 | hdmi_level = hdmi_800mV_0dB; |
| 299 | |
| 300 | /* Entry 9 is for HDMI: */ |
| 301 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); |
| 302 | reg += 4; |
| 303 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); |
| 304 | reg += 4; |
| 305 | } |
| 306 | |
| 307 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP |
| 308 | * mode and port E for FDI. |
| 309 | */ |
| 310 | void intel_prepare_ddi(struct drm_device *dev) |
| 311 | { |
| 312 | int port; |
| 313 | |
| 314 | if (!HAS_DDI(dev)) |
| 315 | return; |
| 316 | |
| 317 | for (port = PORT_A; port <= PORT_E; port++) |
| 318 | intel_prepare_ddi_buffers(dev, port); |
| 319 | } |
| 320 | |
| 321 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
| 322 | enum port port) |
| 323 | { |
| 324 | uint32_t reg = DDI_BUF_CTL(port); |
| 325 | int i; |
| 326 | |
| 327 | for (i = 0; i < 8; i++) { |
| 328 | udelay(1); |
| 329 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) |
| 330 | return; |
| 331 | } |
| 332 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); |
| 333 | } |
| 334 | |
| 335 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
| 336 | * connection to the PCH-located connectors. For this, it is necessary to train |
| 337 | * both the DDI port and PCH receiver for the desired DDI buffer settings. |
| 338 | * |
| 339 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, |
| 340 | * please note that when FDI mode is active on DDI E, it shares 2 lines with |
| 341 | * DDI A (which is used for eDP) |
| 342 | */ |
| 343 | |
| 344 | void hsw_fdi_link_train(struct drm_crtc *crtc) |
| 345 | { |
| 346 | struct drm_device *dev = crtc->dev; |
| 347 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 349 | u32 temp, i, rx_ctl_val; |
| 350 | |
| 351 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
| 352 | * mode set "sequence for CRT port" document: |
| 353 | * - TP1 to TP2 time with the default value |
| 354 | * - FDI delay to 90h |
| 355 | * |
| 356 | * WaFDIAutoLinkSetTimingOverrride:hsw |
| 357 | */ |
| 358 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | |
| 359 | FDI_RX_PWRDN_LANE0_VAL(2) | |
| 360 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 361 | |
| 362 | /* Enable the PCH Receiver FDI PLL */ |
| 363 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
| 364 | FDI_RX_PLL_ENABLE | |
| 365 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
| 366 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
| 367 | POSTING_READ(_FDI_RXA_CTL); |
| 368 | udelay(220); |
| 369 | |
| 370 | /* Switch from Rawclk to PCDclk */ |
| 371 | rx_ctl_val |= FDI_PCDCLK; |
| 372 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
| 373 | |
| 374 | /* Configure Port Clock Select */ |
| 375 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
| 376 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); |
| 377 | |
| 378 | /* Start the training iterating through available voltages and emphasis, |
| 379 | * testing each value twice. */ |
| 380 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
| 381 | /* Configure DP_TP_CTL with auto-training */ |
| 382 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 383 | DP_TP_CTL_FDI_AUTOTRAIN | |
| 384 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
| 385 | DP_TP_CTL_LINK_TRAIN_PAT1 | |
| 386 | DP_TP_CTL_ENABLE); |
| 387 | |
| 388 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
| 389 | * DDI E does not support port reversal, the functionality is |
| 390 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the |
| 391 | * port reversal bit */ |
| 392 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
| 393 | DDI_BUF_CTL_ENABLE | |
| 394 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
| 395 | DDI_BUF_TRANS_SELECT(i / 2)); |
| 396 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
| 397 | |
| 398 | udelay(600); |
| 399 | |
| 400 | /* Program PCH FDI Receiver TU */ |
| 401 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); |
| 402 | |
| 403 | /* Enable PCH FDI Receiver with auto-training */ |
| 404 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; |
| 405 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
| 406 | POSTING_READ(_FDI_RXA_CTL); |
| 407 | |
| 408 | /* Wait for FDI receiver lane calibration */ |
| 409 | udelay(30); |
| 410 | |
| 411 | /* Unset FDI_RX_MISC pwrdn lanes */ |
| 412 | temp = I915_READ(_FDI_RXA_MISC); |
| 413 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
| 414 | I915_WRITE(_FDI_RXA_MISC, temp); |
| 415 | POSTING_READ(_FDI_RXA_MISC); |
| 416 | |
| 417 | /* Wait for FDI auto training time */ |
| 418 | udelay(5); |
| 419 | |
| 420 | temp = I915_READ(DP_TP_STATUS(PORT_E)); |
| 421 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { |
| 422 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
| 423 | |
| 424 | /* Enable normal pixel sending for FDI */ |
| 425 | I915_WRITE(DP_TP_CTL(PORT_E), |
| 426 | DP_TP_CTL_FDI_AUTOTRAIN | |
| 427 | DP_TP_CTL_LINK_TRAIN_NORMAL | |
| 428 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | |
| 429 | DP_TP_CTL_ENABLE); |
| 430 | |
| 431 | return; |
| 432 | } |
| 433 | |
| 434 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
| 435 | temp &= ~DDI_BUF_CTL_ENABLE; |
| 436 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); |
| 437 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
| 438 | |
| 439 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
| 440 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
| 441 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 442 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 443 | I915_WRITE(DP_TP_CTL(PORT_E), temp); |
| 444 | POSTING_READ(DP_TP_CTL(PORT_E)); |
| 445 | |
| 446 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); |
| 447 | |
| 448 | rx_ctl_val &= ~FDI_RX_ENABLE; |
| 449 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
| 450 | POSTING_READ(_FDI_RXA_CTL); |
| 451 | |
| 452 | /* Reset FDI_RX_MISC pwrdn lanes */ |
| 453 | temp = I915_READ(_FDI_RXA_MISC); |
| 454 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
| 455 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
| 456 | I915_WRITE(_FDI_RXA_MISC, temp); |
| 457 | POSTING_READ(_FDI_RXA_MISC); |
| 458 | } |
| 459 | |
| 460 | DRM_ERROR("FDI link training failed!\n"); |
| 461 | } |
| 462 | |
| 463 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
| 464 | { |
| 465 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 466 | struct intel_digital_port *intel_dig_port = |
| 467 | enc_to_dig_port(&encoder->base); |
| 468 | |
| 469 | intel_dp->DP = intel_dig_port->saved_port_bits | |
| 470 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
| 471 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
| 472 | |
| 473 | } |
| 474 | |
| 475 | static struct intel_encoder * |
| 476 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) |
| 477 | { |
| 478 | struct drm_device *dev = crtc->dev; |
| 479 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 480 | struct intel_encoder *intel_encoder, *ret = NULL; |
| 481 | int num_encoders = 0; |
| 482 | |
| 483 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 484 | ret = intel_encoder; |
| 485 | num_encoders++; |
| 486 | } |
| 487 | |
| 488 | if (num_encoders != 1) |
| 489 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
| 490 | pipe_name(intel_crtc->pipe)); |
| 491 | |
| 492 | BUG_ON(ret == NULL); |
| 493 | return ret; |
| 494 | } |
| 495 | |
| 496 | static struct intel_encoder * |
| 497 | intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc) |
| 498 | { |
| 499 | struct drm_device *dev = crtc->base.dev; |
| 500 | struct intel_encoder *intel_encoder, *ret = NULL; |
| 501 | int num_encoders = 0; |
| 502 | |
| 503 | for_each_intel_encoder(dev, intel_encoder) { |
| 504 | if (intel_encoder->new_crtc == crtc) { |
| 505 | ret = intel_encoder; |
| 506 | num_encoders++; |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, |
| 511 | pipe_name(crtc->pipe)); |
| 512 | |
| 513 | BUG_ON(ret == NULL); |
| 514 | return ret; |
| 515 | } |
| 516 | |
| 517 | #define LC_FREQ 2700 |
| 518 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
| 519 | |
| 520 | #define P_MIN 2 |
| 521 | #define P_MAX 64 |
| 522 | #define P_INC 2 |
| 523 | |
| 524 | /* Constraints for PLL good behavior */ |
| 525 | #define REF_MIN 48 |
| 526 | #define REF_MAX 400 |
| 527 | #define VCO_MIN 2400 |
| 528 | #define VCO_MAX 4800 |
| 529 | |
| 530 | #define abs_diff(a, b) ({ \ |
| 531 | typeof(a) __a = (a); \ |
| 532 | typeof(b) __b = (b); \ |
| 533 | (void) (&__a == &__b); \ |
| 534 | __a > __b ? (__a - __b) : (__b - __a); }) |
| 535 | |
| 536 | struct wrpll_rnp { |
| 537 | unsigned p, n2, r2; |
| 538 | }; |
| 539 | |
| 540 | static unsigned wrpll_get_budget_for_freq(int clock) |
| 541 | { |
| 542 | unsigned budget; |
| 543 | |
| 544 | switch (clock) { |
| 545 | case 25175000: |
| 546 | case 25200000: |
| 547 | case 27000000: |
| 548 | case 27027000: |
| 549 | case 37762500: |
| 550 | case 37800000: |
| 551 | case 40500000: |
| 552 | case 40541000: |
| 553 | case 54000000: |
| 554 | case 54054000: |
| 555 | case 59341000: |
| 556 | case 59400000: |
| 557 | case 72000000: |
| 558 | case 74176000: |
| 559 | case 74250000: |
| 560 | case 81000000: |
| 561 | case 81081000: |
| 562 | case 89012000: |
| 563 | case 89100000: |
| 564 | case 108000000: |
| 565 | case 108108000: |
| 566 | case 111264000: |
| 567 | case 111375000: |
| 568 | case 148352000: |
| 569 | case 148500000: |
| 570 | case 162000000: |
| 571 | case 162162000: |
| 572 | case 222525000: |
| 573 | case 222750000: |
| 574 | case 296703000: |
| 575 | case 297000000: |
| 576 | budget = 0; |
| 577 | break; |
| 578 | case 233500000: |
| 579 | case 245250000: |
| 580 | case 247750000: |
| 581 | case 253250000: |
| 582 | case 298000000: |
| 583 | budget = 1500; |
| 584 | break; |
| 585 | case 169128000: |
| 586 | case 169500000: |
| 587 | case 179500000: |
| 588 | case 202000000: |
| 589 | budget = 2000; |
| 590 | break; |
| 591 | case 256250000: |
| 592 | case 262500000: |
| 593 | case 270000000: |
| 594 | case 272500000: |
| 595 | case 273750000: |
| 596 | case 280750000: |
| 597 | case 281250000: |
| 598 | case 286000000: |
| 599 | case 291750000: |
| 600 | budget = 4000; |
| 601 | break; |
| 602 | case 267250000: |
| 603 | case 268500000: |
| 604 | budget = 5000; |
| 605 | break; |
| 606 | default: |
| 607 | budget = 1000; |
| 608 | break; |
| 609 | } |
| 610 | |
| 611 | return budget; |
| 612 | } |
| 613 | |
| 614 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, |
| 615 | unsigned r2, unsigned n2, unsigned p, |
| 616 | struct wrpll_rnp *best) |
| 617 | { |
| 618 | uint64_t a, b, c, d, diff, diff_best; |
| 619 | |
| 620 | /* No best (r,n,p) yet */ |
| 621 | if (best->p == 0) { |
| 622 | best->p = p; |
| 623 | best->n2 = n2; |
| 624 | best->r2 = r2; |
| 625 | return; |
| 626 | } |
| 627 | |
| 628 | /* |
| 629 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to |
| 630 | * freq2k. |
| 631 | * |
| 632 | * delta = 1e6 * |
| 633 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / |
| 634 | * freq2k; |
| 635 | * |
| 636 | * and we would like delta <= budget. |
| 637 | * |
| 638 | * If the discrepancy is above the PPM-based budget, always prefer to |
| 639 | * improve upon the previous solution. However, if you're within the |
| 640 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). |
| 641 | */ |
| 642 | a = freq2k * budget * p * r2; |
| 643 | b = freq2k * budget * best->p * best->r2; |
| 644 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
| 645 | diff_best = abs_diff(freq2k * best->p * best->r2, |
| 646 | LC_FREQ_2K * best->n2); |
| 647 | c = 1000000 * diff; |
| 648 | d = 1000000 * diff_best; |
| 649 | |
| 650 | if (a < c && b < d) { |
| 651 | /* If both are above the budget, pick the closer */ |
| 652 | if (best->p * best->r2 * diff < p * r2 * diff_best) { |
| 653 | best->p = p; |
| 654 | best->n2 = n2; |
| 655 | best->r2 = r2; |
| 656 | } |
| 657 | } else if (a >= c && b < d) { |
| 658 | /* If A is below the threshold but B is above it? Update. */ |
| 659 | best->p = p; |
| 660 | best->n2 = n2; |
| 661 | best->r2 = r2; |
| 662 | } else if (a >= c && b >= d) { |
| 663 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ |
| 664 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { |
| 665 | best->p = p; |
| 666 | best->n2 = n2; |
| 667 | best->r2 = r2; |
| 668 | } |
| 669 | } |
| 670 | /* Otherwise a < c && b >= d, do nothing */ |
| 671 | } |
| 672 | |
| 673 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
| 674 | int reg) |
| 675 | { |
| 676 | int refclk = LC_FREQ; |
| 677 | int n, p, r; |
| 678 | u32 wrpll; |
| 679 | |
| 680 | wrpll = I915_READ(reg); |
| 681 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
| 682 | case WRPLL_PLL_SSC: |
| 683 | case WRPLL_PLL_NON_SSC: |
| 684 | /* |
| 685 | * We could calculate spread here, but our checking |
| 686 | * code only cares about 5% accuracy, and spread is a max of |
| 687 | * 0.5% downspread. |
| 688 | */ |
| 689 | refclk = 135; |
| 690 | break; |
| 691 | case WRPLL_PLL_LCPLL: |
| 692 | refclk = LC_FREQ; |
| 693 | break; |
| 694 | default: |
| 695 | WARN(1, "bad wrpll refclk\n"); |
| 696 | return 0; |
| 697 | } |
| 698 | |
| 699 | r = wrpll & WRPLL_DIVIDER_REF_MASK; |
| 700 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; |
| 701 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; |
| 702 | |
| 703 | /* Convert to KHz, p & r have a fixed point portion */ |
| 704 | return (refclk * n * 100) / (p * r); |
| 705 | } |
| 706 | |
| 707 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
| 708 | uint32_t dpll) |
| 709 | { |
| 710 | uint32_t cfgcr1_reg, cfgcr2_reg; |
| 711 | uint32_t cfgcr1_val, cfgcr2_val; |
| 712 | uint32_t p0, p1, p2, dco_freq; |
| 713 | |
| 714 | cfgcr1_reg = GET_CFG_CR1_REG(dpll); |
| 715 | cfgcr2_reg = GET_CFG_CR2_REG(dpll); |
| 716 | |
| 717 | cfgcr1_val = I915_READ(cfgcr1_reg); |
| 718 | cfgcr2_val = I915_READ(cfgcr2_reg); |
| 719 | |
| 720 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; |
| 721 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; |
| 722 | |
| 723 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) |
| 724 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; |
| 725 | else |
| 726 | p1 = 1; |
| 727 | |
| 728 | |
| 729 | switch (p0) { |
| 730 | case DPLL_CFGCR2_PDIV_1: |
| 731 | p0 = 1; |
| 732 | break; |
| 733 | case DPLL_CFGCR2_PDIV_2: |
| 734 | p0 = 2; |
| 735 | break; |
| 736 | case DPLL_CFGCR2_PDIV_3: |
| 737 | p0 = 3; |
| 738 | break; |
| 739 | case DPLL_CFGCR2_PDIV_7: |
| 740 | p0 = 7; |
| 741 | break; |
| 742 | } |
| 743 | |
| 744 | switch (p2) { |
| 745 | case DPLL_CFGCR2_KDIV_5: |
| 746 | p2 = 5; |
| 747 | break; |
| 748 | case DPLL_CFGCR2_KDIV_2: |
| 749 | p2 = 2; |
| 750 | break; |
| 751 | case DPLL_CFGCR2_KDIV_3: |
| 752 | p2 = 3; |
| 753 | break; |
| 754 | case DPLL_CFGCR2_KDIV_1: |
| 755 | p2 = 1; |
| 756 | break; |
| 757 | } |
| 758 | |
| 759 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; |
| 760 | |
| 761 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * |
| 762 | 1000) / 0x8000; |
| 763 | |
| 764 | return dco_freq / (p0 * p1 * p2 * 5); |
| 765 | } |
| 766 | |
| 767 | |
| 768 | static void skl_ddi_clock_get(struct intel_encoder *encoder, |
| 769 | struct intel_crtc_state *pipe_config) |
| 770 | { |
| 771 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 772 | int link_clock = 0; |
| 773 | uint32_t dpll_ctl1, dpll; |
| 774 | |
| 775 | dpll = pipe_config->ddi_pll_sel; |
| 776 | |
| 777 | dpll_ctl1 = I915_READ(DPLL_CTRL1); |
| 778 | |
| 779 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { |
| 780 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); |
| 781 | } else { |
| 782 | link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll); |
| 783 | link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll); |
| 784 | |
| 785 | switch (link_clock) { |
| 786 | case DPLL_CRTL1_LINK_RATE_810: |
| 787 | link_clock = 81000; |
| 788 | break; |
| 789 | case DPLL_CRTL1_LINK_RATE_1350: |
| 790 | link_clock = 135000; |
| 791 | break; |
| 792 | case DPLL_CRTL1_LINK_RATE_2700: |
| 793 | link_clock = 270000; |
| 794 | break; |
| 795 | default: |
| 796 | WARN(1, "Unsupported link rate\n"); |
| 797 | break; |
| 798 | } |
| 799 | link_clock *= 2; |
| 800 | } |
| 801 | |
| 802 | pipe_config->port_clock = link_clock; |
| 803 | |
| 804 | if (pipe_config->has_dp_encoder) |
| 805 | pipe_config->base.adjusted_mode.crtc_clock = |
| 806 | intel_dotclock_calculate(pipe_config->port_clock, |
| 807 | &pipe_config->dp_m_n); |
| 808 | else |
| 809 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
| 810 | } |
| 811 | |
| 812 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
| 813 | struct intel_crtc_state *pipe_config) |
| 814 | { |
| 815 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 816 | int link_clock = 0; |
| 817 | u32 val, pll; |
| 818 | |
| 819 | val = pipe_config->ddi_pll_sel; |
| 820 | switch (val & PORT_CLK_SEL_MASK) { |
| 821 | case PORT_CLK_SEL_LCPLL_810: |
| 822 | link_clock = 81000; |
| 823 | break; |
| 824 | case PORT_CLK_SEL_LCPLL_1350: |
| 825 | link_clock = 135000; |
| 826 | break; |
| 827 | case PORT_CLK_SEL_LCPLL_2700: |
| 828 | link_clock = 270000; |
| 829 | break; |
| 830 | case PORT_CLK_SEL_WRPLL1: |
| 831 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); |
| 832 | break; |
| 833 | case PORT_CLK_SEL_WRPLL2: |
| 834 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); |
| 835 | break; |
| 836 | case PORT_CLK_SEL_SPLL: |
| 837 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; |
| 838 | if (pll == SPLL_PLL_FREQ_810MHz) |
| 839 | link_clock = 81000; |
| 840 | else if (pll == SPLL_PLL_FREQ_1350MHz) |
| 841 | link_clock = 135000; |
| 842 | else if (pll == SPLL_PLL_FREQ_2700MHz) |
| 843 | link_clock = 270000; |
| 844 | else { |
| 845 | WARN(1, "bad spll freq\n"); |
| 846 | return; |
| 847 | } |
| 848 | break; |
| 849 | default: |
| 850 | WARN(1, "bad port clock sel\n"); |
| 851 | return; |
| 852 | } |
| 853 | |
| 854 | pipe_config->port_clock = link_clock * 2; |
| 855 | |
| 856 | if (pipe_config->has_pch_encoder) |
| 857 | pipe_config->base.adjusted_mode.crtc_clock = |
| 858 | intel_dotclock_calculate(pipe_config->port_clock, |
| 859 | &pipe_config->fdi_m_n); |
| 860 | else if (pipe_config->has_dp_encoder) |
| 861 | pipe_config->base.adjusted_mode.crtc_clock = |
| 862 | intel_dotclock_calculate(pipe_config->port_clock, |
| 863 | &pipe_config->dp_m_n); |
| 864 | else |
| 865 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
| 866 | } |
| 867 | |
| 868 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
| 869 | struct intel_crtc_state *pipe_config) |
| 870 | { |
| 871 | struct drm_device *dev = encoder->base.dev; |
| 872 | |
| 873 | if (INTEL_INFO(dev)->gen <= 8) |
| 874 | hsw_ddi_clock_get(encoder, pipe_config); |
| 875 | else |
| 876 | skl_ddi_clock_get(encoder, pipe_config); |
| 877 | } |
| 878 | |
| 879 | static void |
| 880 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
| 881 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) |
| 882 | { |
| 883 | uint64_t freq2k; |
| 884 | unsigned p, n2, r2; |
| 885 | struct wrpll_rnp best = { 0, 0, 0 }; |
| 886 | unsigned budget; |
| 887 | |
| 888 | freq2k = clock / 100; |
| 889 | |
| 890 | budget = wrpll_get_budget_for_freq(clock); |
| 891 | |
| 892 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely |
| 893 | * and directly pass the LC PLL to it. */ |
| 894 | if (freq2k == 5400000) { |
| 895 | *n2_out = 2; |
| 896 | *p_out = 1; |
| 897 | *r2_out = 2; |
| 898 | return; |
| 899 | } |
| 900 | |
| 901 | /* |
| 902 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by |
| 903 | * the WR PLL. |
| 904 | * |
| 905 | * We want R so that REF_MIN <= Ref <= REF_MAX. |
| 906 | * Injecting R2 = 2 * R gives: |
| 907 | * REF_MAX * r2 > LC_FREQ * 2 and |
| 908 | * REF_MIN * r2 < LC_FREQ * 2 |
| 909 | * |
| 910 | * Which means the desired boundaries for r2 are: |
| 911 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN |
| 912 | * |
| 913 | */ |
| 914 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; |
| 915 | r2 <= LC_FREQ * 2 / REF_MIN; |
| 916 | r2++) { |
| 917 | |
| 918 | /* |
| 919 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R |
| 920 | * |
| 921 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. |
| 922 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: |
| 923 | * VCO_MAX * r2 > n2 * LC_FREQ and |
| 924 | * VCO_MIN * r2 < n2 * LC_FREQ) |
| 925 | * |
| 926 | * Which means the desired boundaries for n2 are: |
| 927 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ |
| 928 | */ |
| 929 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; |
| 930 | n2 <= VCO_MAX * r2 / LC_FREQ; |
| 931 | n2++) { |
| 932 | |
| 933 | for (p = P_MIN; p <= P_MAX; p += P_INC) |
| 934 | wrpll_update_rnp(freq2k, budget, |
| 935 | r2, n2, p, &best); |
| 936 | } |
| 937 | } |
| 938 | |
| 939 | *n2_out = best.n2; |
| 940 | *p_out = best.p; |
| 941 | *r2_out = best.r2; |
| 942 | } |
| 943 | |
| 944 | static bool |
| 945 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
| 946 | struct intel_crtc_state *crtc_state, |
| 947 | struct intel_encoder *intel_encoder, |
| 948 | int clock) |
| 949 | { |
| 950 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
| 951 | struct intel_shared_dpll *pll; |
| 952 | uint32_t val; |
| 953 | unsigned p, n2, r2; |
| 954 | |
| 955 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
| 956 | |
| 957 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
| 958 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
| 959 | WRPLL_DIVIDER_POST(p); |
| 960 | |
| 961 | crtc_state->dpll_hw_state.wrpll = val; |
| 962 | |
| 963 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
| 964 | if (pll == NULL) { |
| 965 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
| 966 | pipe_name(intel_crtc->pipe)); |
| 967 | return false; |
| 968 | } |
| 969 | |
| 970 | crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
| 971 | } |
| 972 | |
| 973 | return true; |
| 974 | } |
| 975 | |
| 976 | struct skl_wrpll_params { |
| 977 | uint32_t dco_fraction; |
| 978 | uint32_t dco_integer; |
| 979 | uint32_t qdiv_ratio; |
| 980 | uint32_t qdiv_mode; |
| 981 | uint32_t kdiv; |
| 982 | uint32_t pdiv; |
| 983 | uint32_t central_freq; |
| 984 | }; |
| 985 | |
| 986 | static void |
| 987 | skl_ddi_calculate_wrpll(int clock /* in Hz */, |
| 988 | struct skl_wrpll_params *wrpll_params) |
| 989 | { |
| 990 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ |
| 991 | uint64_t dco_central_freq[3] = {8400000000ULL, |
| 992 | 9000000000ULL, |
| 993 | 9600000000ULL}; |
| 994 | uint32_t min_dco_deviation = 400; |
| 995 | uint32_t min_dco_index = 3; |
| 996 | uint32_t P0[4] = {1, 2, 3, 7}; |
| 997 | uint32_t P2[4] = {1, 2, 3, 5}; |
| 998 | bool found = false; |
| 999 | uint32_t candidate_p = 0; |
| 1000 | uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0}; |
| 1001 | uint32_t candidate_p2[3] = {0}; |
| 1002 | uint32_t dco_central_freq_deviation[3]; |
| 1003 | uint32_t i, P1, k, dco_count; |
| 1004 | bool retry_with_odd = false; |
| 1005 | uint64_t dco_freq; |
| 1006 | |
| 1007 | /* Determine P0, P1 or P2 */ |
| 1008 | for (dco_count = 0; dco_count < 3; dco_count++) { |
| 1009 | found = false; |
| 1010 | candidate_p = |
| 1011 | div64_u64(dco_central_freq[dco_count], afe_clock); |
| 1012 | if (retry_with_odd == false) |
| 1013 | candidate_p = (candidate_p % 2 == 0 ? |
| 1014 | candidate_p : candidate_p + 1); |
| 1015 | |
| 1016 | for (P1 = 1; P1 < candidate_p; P1++) { |
| 1017 | for (i = 0; i < 4; i++) { |
| 1018 | if (!(P0[i] != 1 || P1 == 1)) |
| 1019 | continue; |
| 1020 | |
| 1021 | for (k = 0; k < 4; k++) { |
| 1022 | if (P1 != 1 && P2[k] != 2) |
| 1023 | continue; |
| 1024 | |
| 1025 | if (candidate_p == P0[i] * P1 * P2[k]) { |
| 1026 | /* Found possible P0, P1, P2 */ |
| 1027 | found = true; |
| 1028 | candidate_p0[dco_count] = P0[i]; |
| 1029 | candidate_p1[dco_count] = P1; |
| 1030 | candidate_p2[dco_count] = P2[k]; |
| 1031 | goto found; |
| 1032 | } |
| 1033 | |
| 1034 | } |
| 1035 | } |
| 1036 | } |
| 1037 | |
| 1038 | found: |
| 1039 | if (found) { |
| 1040 | dco_central_freq_deviation[dco_count] = |
| 1041 | div64_u64(10000 * |
| 1042 | abs_diff((candidate_p * afe_clock), |
| 1043 | dco_central_freq[dco_count]), |
| 1044 | dco_central_freq[dco_count]); |
| 1045 | |
| 1046 | if (dco_central_freq_deviation[dco_count] < |
| 1047 | min_dco_deviation) { |
| 1048 | min_dco_deviation = |
| 1049 | dco_central_freq_deviation[dco_count]; |
| 1050 | min_dco_index = dco_count; |
| 1051 | } |
| 1052 | } |
| 1053 | |
| 1054 | if (min_dco_index > 2 && dco_count == 2) { |
| 1055 | retry_with_odd = true; |
| 1056 | dco_count = 0; |
| 1057 | } |
| 1058 | } |
| 1059 | |
| 1060 | if (min_dco_index > 2) { |
| 1061 | WARN(1, "No valid values found for the given pixel clock\n"); |
| 1062 | } else { |
| 1063 | wrpll_params->central_freq = dco_central_freq[min_dco_index]; |
| 1064 | |
| 1065 | switch (dco_central_freq[min_dco_index]) { |
| 1066 | case 9600000000ULL: |
| 1067 | wrpll_params->central_freq = 0; |
| 1068 | break; |
| 1069 | case 9000000000ULL: |
| 1070 | wrpll_params->central_freq = 1; |
| 1071 | break; |
| 1072 | case 8400000000ULL: |
| 1073 | wrpll_params->central_freq = 3; |
| 1074 | } |
| 1075 | |
| 1076 | switch (candidate_p0[min_dco_index]) { |
| 1077 | case 1: |
| 1078 | wrpll_params->pdiv = 0; |
| 1079 | break; |
| 1080 | case 2: |
| 1081 | wrpll_params->pdiv = 1; |
| 1082 | break; |
| 1083 | case 3: |
| 1084 | wrpll_params->pdiv = 2; |
| 1085 | break; |
| 1086 | case 7: |
| 1087 | wrpll_params->pdiv = 4; |
| 1088 | break; |
| 1089 | default: |
| 1090 | WARN(1, "Incorrect PDiv\n"); |
| 1091 | } |
| 1092 | |
| 1093 | switch (candidate_p2[min_dco_index]) { |
| 1094 | case 5: |
| 1095 | wrpll_params->kdiv = 0; |
| 1096 | break; |
| 1097 | case 2: |
| 1098 | wrpll_params->kdiv = 1; |
| 1099 | break; |
| 1100 | case 3: |
| 1101 | wrpll_params->kdiv = 2; |
| 1102 | break; |
| 1103 | case 1: |
| 1104 | wrpll_params->kdiv = 3; |
| 1105 | break; |
| 1106 | default: |
| 1107 | WARN(1, "Incorrect KDiv\n"); |
| 1108 | } |
| 1109 | |
| 1110 | wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; |
| 1111 | wrpll_params->qdiv_mode = |
| 1112 | (wrpll_params->qdiv_ratio == 1) ? 0 : 1; |
| 1113 | |
| 1114 | dco_freq = candidate_p0[min_dco_index] * |
| 1115 | candidate_p1[min_dco_index] * |
| 1116 | candidate_p2[min_dco_index] * afe_clock; |
| 1117 | |
| 1118 | /* |
| 1119 | * Intermediate values are in Hz. |
| 1120 | * Divide by MHz to match bsepc |
| 1121 | */ |
| 1122 | wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); |
| 1123 | wrpll_params->dco_fraction = |
| 1124 | div_u64(((div_u64(dco_freq, 24) - |
| 1125 | wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); |
| 1126 | |
| 1127 | } |
| 1128 | } |
| 1129 | |
| 1130 | |
| 1131 | static bool |
| 1132 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, |
| 1133 | struct intel_crtc_state *crtc_state, |
| 1134 | struct intel_encoder *intel_encoder, |
| 1135 | int clock) |
| 1136 | { |
| 1137 | struct intel_shared_dpll *pll; |
| 1138 | uint32_t ctrl1, cfgcr1, cfgcr2; |
| 1139 | |
| 1140 | /* |
| 1141 | * See comment in intel_dpll_hw_state to understand why we always use 0 |
| 1142 | * as the DPLL id in this function. |
| 1143 | */ |
| 1144 | |
| 1145 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); |
| 1146 | |
| 1147 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
| 1148 | struct skl_wrpll_params wrpll_params = { 0, }; |
| 1149 | |
| 1150 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); |
| 1151 | |
| 1152 | skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params); |
| 1153 | |
| 1154 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | |
| 1155 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | |
| 1156 | wrpll_params.dco_integer; |
| 1157 | |
| 1158 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | |
| 1159 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | |
| 1160 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | |
| 1161 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | |
| 1162 | wrpll_params.central_freq; |
| 1163 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { |
| 1164 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1165 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1166 | |
| 1167 | switch (intel_dp->link_bw) { |
| 1168 | case DP_LINK_BW_1_62: |
| 1169 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0); |
| 1170 | break; |
| 1171 | case DP_LINK_BW_2_7: |
| 1172 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0); |
| 1173 | break; |
| 1174 | case DP_LINK_BW_5_4: |
| 1175 | ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0); |
| 1176 | break; |
| 1177 | } |
| 1178 | |
| 1179 | cfgcr1 = cfgcr2 = 0; |
| 1180 | } else /* eDP */ |
| 1181 | return true; |
| 1182 | |
| 1183 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
| 1184 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; |
| 1185 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; |
| 1186 | |
| 1187 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
| 1188 | if (pll == NULL) { |
| 1189 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
| 1190 | pipe_name(intel_crtc->pipe)); |
| 1191 | return false; |
| 1192 | } |
| 1193 | |
| 1194 | /* shared DPLL id 0 is DPLL 1 */ |
| 1195 | crtc_state->ddi_pll_sel = pll->id + 1; |
| 1196 | |
| 1197 | return true; |
| 1198 | } |
| 1199 | |
| 1200 | /* |
| 1201 | * Tries to find a *shared* PLL for the CRTC and store it in |
| 1202 | * intel_crtc->ddi_pll_sel. |
| 1203 | * |
| 1204 | * For private DPLLs, compute_config() should do the selection for us. This |
| 1205 | * function should be folded into compute_config() eventually. |
| 1206 | */ |
| 1207 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
| 1208 | struct intel_crtc_state *crtc_state) |
| 1209 | { |
| 1210 | struct drm_device *dev = intel_crtc->base.dev; |
| 1211 | struct intel_encoder *intel_encoder = |
| 1212 | intel_ddi_get_crtc_new_encoder(intel_crtc); |
| 1213 | int clock = crtc_state->port_clock; |
| 1214 | |
| 1215 | if (IS_SKYLAKE(dev)) |
| 1216 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
| 1217 | intel_encoder, clock); |
| 1218 | else |
| 1219 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
| 1220 | intel_encoder, clock); |
| 1221 | } |
| 1222 | |
| 1223 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
| 1224 | { |
| 1225 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 1226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1227 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
| 1228 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 1229 | int type = intel_encoder->type; |
| 1230 | uint32_t temp; |
| 1231 | |
| 1232 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
| 1233 | temp = TRANS_MSA_SYNC_CLK; |
| 1234 | switch (intel_crtc->config->pipe_bpp) { |
| 1235 | case 18: |
| 1236 | temp |= TRANS_MSA_6_BPC; |
| 1237 | break; |
| 1238 | case 24: |
| 1239 | temp |= TRANS_MSA_8_BPC; |
| 1240 | break; |
| 1241 | case 30: |
| 1242 | temp |= TRANS_MSA_10_BPC; |
| 1243 | break; |
| 1244 | case 36: |
| 1245 | temp |= TRANS_MSA_12_BPC; |
| 1246 | break; |
| 1247 | default: |
| 1248 | BUG(); |
| 1249 | } |
| 1250 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
| 1251 | } |
| 1252 | } |
| 1253 | |
| 1254 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
| 1255 | { |
| 1256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1257 | struct drm_device *dev = crtc->dev; |
| 1258 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1259 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 1260 | uint32_t temp; |
| 1261 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 1262 | if (state == true) |
| 1263 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
| 1264 | else |
| 1265 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; |
| 1266 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
| 1267 | } |
| 1268 | |
| 1269 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
| 1270 | { |
| 1271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1272 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
| 1273 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1274 | struct drm_device *dev = crtc->dev; |
| 1275 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1276 | enum pipe pipe = intel_crtc->pipe; |
| 1277 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 1278 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1279 | int type = intel_encoder->type; |
| 1280 | uint32_t temp; |
| 1281 | |
| 1282 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
| 1283 | temp = TRANS_DDI_FUNC_ENABLE; |
| 1284 | temp |= TRANS_DDI_SELECT_PORT(port); |
| 1285 | |
| 1286 | switch (intel_crtc->config->pipe_bpp) { |
| 1287 | case 18: |
| 1288 | temp |= TRANS_DDI_BPC_6; |
| 1289 | break; |
| 1290 | case 24: |
| 1291 | temp |= TRANS_DDI_BPC_8; |
| 1292 | break; |
| 1293 | case 30: |
| 1294 | temp |= TRANS_DDI_BPC_10; |
| 1295 | break; |
| 1296 | case 36: |
| 1297 | temp |= TRANS_DDI_BPC_12; |
| 1298 | break; |
| 1299 | default: |
| 1300 | BUG(); |
| 1301 | } |
| 1302 | |
| 1303 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
| 1304 | temp |= TRANS_DDI_PVSYNC; |
| 1305 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
| 1306 | temp |= TRANS_DDI_PHSYNC; |
| 1307 | |
| 1308 | if (cpu_transcoder == TRANSCODER_EDP) { |
| 1309 | switch (pipe) { |
| 1310 | case PIPE_A: |
| 1311 | /* On Haswell, can only use the always-on power well for |
| 1312 | * eDP when not using the panel fitter, and when not |
| 1313 | * using motion blur mitigation (which we don't |
| 1314 | * support). */ |
| 1315 | if (IS_HASWELL(dev) && |
| 1316 | (intel_crtc->config->pch_pfit.enabled || |
| 1317 | intel_crtc->config->pch_pfit.force_thru)) |
| 1318 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
| 1319 | else |
| 1320 | temp |= TRANS_DDI_EDP_INPUT_A_ON; |
| 1321 | break; |
| 1322 | case PIPE_B: |
| 1323 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; |
| 1324 | break; |
| 1325 | case PIPE_C: |
| 1326 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; |
| 1327 | break; |
| 1328 | default: |
| 1329 | BUG(); |
| 1330 | break; |
| 1331 | } |
| 1332 | } |
| 1333 | |
| 1334 | if (type == INTEL_OUTPUT_HDMI) { |
| 1335 | if (intel_crtc->config->has_hdmi_sink) |
| 1336 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
| 1337 | else |
| 1338 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
| 1339 | |
| 1340 | } else if (type == INTEL_OUTPUT_ANALOG) { |
| 1341 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
| 1342 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
| 1343 | |
| 1344 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || |
| 1345 | type == INTEL_OUTPUT_EDP) { |
| 1346 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1347 | |
| 1348 | if (intel_dp->is_mst) { |
| 1349 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
| 1350 | } else |
| 1351 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
| 1352 | |
| 1353 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
| 1354 | } else if (type == INTEL_OUTPUT_DP_MST) { |
| 1355 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; |
| 1356 | |
| 1357 | if (intel_dp->is_mst) { |
| 1358 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
| 1359 | } else |
| 1360 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
| 1361 | |
| 1362 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
| 1363 | } else { |
| 1364 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
| 1365 | intel_encoder->type, pipe_name(pipe)); |
| 1366 | } |
| 1367 | |
| 1368 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
| 1369 | } |
| 1370 | |
| 1371 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| 1372 | enum transcoder cpu_transcoder) |
| 1373 | { |
| 1374 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
| 1375 | uint32_t val = I915_READ(reg); |
| 1376 | |
| 1377 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
| 1378 | val |= TRANS_DDI_PORT_NONE; |
| 1379 | I915_WRITE(reg, val); |
| 1380 | } |
| 1381 | |
| 1382 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
| 1383 | { |
| 1384 | struct drm_device *dev = intel_connector->base.dev; |
| 1385 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1386 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
| 1387 | int type = intel_connector->base.connector_type; |
| 1388 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1389 | enum pipe pipe = 0; |
| 1390 | enum transcoder cpu_transcoder; |
| 1391 | enum intel_display_power_domain power_domain; |
| 1392 | uint32_t tmp; |
| 1393 | |
| 1394 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1395 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
| 1396 | return false; |
| 1397 | |
| 1398 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
| 1399 | return false; |
| 1400 | |
| 1401 | if (port == PORT_A) |
| 1402 | cpu_transcoder = TRANSCODER_EDP; |
| 1403 | else |
| 1404 | cpu_transcoder = (enum transcoder) pipe; |
| 1405 | |
| 1406 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 1407 | |
| 1408 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { |
| 1409 | case TRANS_DDI_MODE_SELECT_HDMI: |
| 1410 | case TRANS_DDI_MODE_SELECT_DVI: |
| 1411 | return (type == DRM_MODE_CONNECTOR_HDMIA); |
| 1412 | |
| 1413 | case TRANS_DDI_MODE_SELECT_DP_SST: |
| 1414 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 1415 | return true; |
| 1416 | return (type == DRM_MODE_CONNECTOR_DisplayPort); |
| 1417 | case TRANS_DDI_MODE_SELECT_DP_MST: |
| 1418 | /* if the transcoder is in MST state then |
| 1419 | * connector isn't connected */ |
| 1420 | return false; |
| 1421 | |
| 1422 | case TRANS_DDI_MODE_SELECT_FDI: |
| 1423 | return (type == DRM_MODE_CONNECTOR_VGA); |
| 1424 | |
| 1425 | default: |
| 1426 | return false; |
| 1427 | } |
| 1428 | } |
| 1429 | |
| 1430 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
| 1431 | enum pipe *pipe) |
| 1432 | { |
| 1433 | struct drm_device *dev = encoder->base.dev; |
| 1434 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1435 | enum port port = intel_ddi_get_encoder_port(encoder); |
| 1436 | enum intel_display_power_domain power_domain; |
| 1437 | u32 tmp; |
| 1438 | int i; |
| 1439 | |
| 1440 | power_domain = intel_display_port_power_domain(encoder); |
| 1441 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
| 1442 | return false; |
| 1443 | |
| 1444 | tmp = I915_READ(DDI_BUF_CTL(port)); |
| 1445 | |
| 1446 | if (!(tmp & DDI_BUF_CTL_ENABLE)) |
| 1447 | return false; |
| 1448 | |
| 1449 | if (port == PORT_A) { |
| 1450 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
| 1451 | |
| 1452 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 1453 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 1454 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 1455 | *pipe = PIPE_A; |
| 1456 | break; |
| 1457 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 1458 | *pipe = PIPE_B; |
| 1459 | break; |
| 1460 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 1461 | *pipe = PIPE_C; |
| 1462 | break; |
| 1463 | } |
| 1464 | |
| 1465 | return true; |
| 1466 | } else { |
| 1467 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
| 1468 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); |
| 1469 | |
| 1470 | if ((tmp & TRANS_DDI_PORT_MASK) |
| 1471 | == TRANS_DDI_SELECT_PORT(port)) { |
| 1472 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) |
| 1473 | return false; |
| 1474 | |
| 1475 | *pipe = i; |
| 1476 | return true; |
| 1477 | } |
| 1478 | } |
| 1479 | } |
| 1480 | |
| 1481 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
| 1482 | |
| 1483 | return false; |
| 1484 | } |
| 1485 | |
| 1486 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
| 1487 | { |
| 1488 | struct drm_crtc *crtc = &intel_crtc->base; |
| 1489 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 1490 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
| 1491 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1492 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 1493 | |
| 1494 | if (cpu_transcoder != TRANSCODER_EDP) |
| 1495 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
| 1496 | TRANS_CLK_SEL_PORT(port)); |
| 1497 | } |
| 1498 | |
| 1499 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
| 1500 | { |
| 1501 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
| 1502 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
| 1503 | |
| 1504 | if (cpu_transcoder != TRANSCODER_EDP) |
| 1505 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
| 1506 | TRANS_CLK_SEL_DISABLED); |
| 1507 | } |
| 1508 | |
| 1509 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
| 1510 | { |
| 1511 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1512 | struct drm_device *dev = encoder->dev; |
| 1513 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1514 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
| 1515 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1516 | int type = intel_encoder->type; |
| 1517 | |
| 1518 | if (type == INTEL_OUTPUT_EDP) { |
| 1519 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1520 | intel_edp_panel_on(intel_dp); |
| 1521 | } |
| 1522 | |
| 1523 | if (IS_SKYLAKE(dev)) { |
| 1524 | uint32_t dpll = crtc->config->ddi_pll_sel; |
| 1525 | uint32_t val; |
| 1526 | |
| 1527 | /* |
| 1528 | * DPLL0 is used for eDP and is the only "private" DPLL (as |
| 1529 | * opposed to shared) on SKL |
| 1530 | */ |
| 1531 | if (type == INTEL_OUTPUT_EDP) { |
| 1532 | WARN_ON(dpll != SKL_DPLL0); |
| 1533 | |
| 1534 | val = I915_READ(DPLL_CTRL1); |
| 1535 | |
| 1536 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | |
| 1537 | DPLL_CTRL1_SSC(dpll) | |
| 1538 | DPLL_CRTL1_LINK_RATE_MASK(dpll)); |
| 1539 | val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); |
| 1540 | |
| 1541 | I915_WRITE(DPLL_CTRL1, val); |
| 1542 | POSTING_READ(DPLL_CTRL1); |
| 1543 | } |
| 1544 | |
| 1545 | /* DDI -> PLL mapping */ |
| 1546 | val = I915_READ(DPLL_CTRL2); |
| 1547 | |
| 1548 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | |
| 1549 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); |
| 1550 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | |
| 1551 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
| 1552 | |
| 1553 | I915_WRITE(DPLL_CTRL2, val); |
| 1554 | |
| 1555 | } else { |
| 1556 | WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
| 1557 | I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); |
| 1558 | } |
| 1559 | |
| 1560 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
| 1561 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1562 | |
| 1563 | intel_ddi_init_dp_buf_reg(intel_encoder); |
| 1564 | |
| 1565 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 1566 | intel_dp_start_link_train(intel_dp); |
| 1567 | intel_dp_complete_link_train(intel_dp); |
| 1568 | if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) |
| 1569 | intel_dp_stop_link_train(intel_dp); |
| 1570 | } else if (type == INTEL_OUTPUT_HDMI) { |
| 1571 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 1572 | |
| 1573 | intel_hdmi->set_infoframes(encoder, |
| 1574 | crtc->config->has_hdmi_sink, |
| 1575 | &crtc->config->base.adjusted_mode); |
| 1576 | } |
| 1577 | } |
| 1578 | |
| 1579 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
| 1580 | { |
| 1581 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1582 | struct drm_device *dev = encoder->dev; |
| 1583 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1584 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1585 | int type = intel_encoder->type; |
| 1586 | uint32_t val; |
| 1587 | bool wait = false; |
| 1588 | |
| 1589 | val = I915_READ(DDI_BUF_CTL(port)); |
| 1590 | if (val & DDI_BUF_CTL_ENABLE) { |
| 1591 | val &= ~DDI_BUF_CTL_ENABLE; |
| 1592 | I915_WRITE(DDI_BUF_CTL(port), val); |
| 1593 | wait = true; |
| 1594 | } |
| 1595 | |
| 1596 | val = I915_READ(DP_TP_CTL(port)); |
| 1597 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 1598 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 1599 | I915_WRITE(DP_TP_CTL(port), val); |
| 1600 | |
| 1601 | if (wait) |
| 1602 | intel_wait_ddi_buf_idle(dev_priv, port); |
| 1603 | |
| 1604 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
| 1605 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1606 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
| 1607 | intel_edp_panel_vdd_on(intel_dp); |
| 1608 | intel_edp_panel_off(intel_dp); |
| 1609 | } |
| 1610 | |
| 1611 | if (IS_SKYLAKE(dev)) |
| 1612 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
| 1613 | DPLL_CTRL2_DDI_CLK_OFF(port))); |
| 1614 | else |
| 1615 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
| 1616 | } |
| 1617 | |
| 1618 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
| 1619 | { |
| 1620 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1621 | struct drm_crtc *crtc = encoder->crtc; |
| 1622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1623 | struct drm_device *dev = encoder->dev; |
| 1624 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1625 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
| 1626 | int type = intel_encoder->type; |
| 1627 | |
| 1628 | if (type == INTEL_OUTPUT_HDMI) { |
| 1629 | struct intel_digital_port *intel_dig_port = |
| 1630 | enc_to_dig_port(encoder); |
| 1631 | |
| 1632 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
| 1633 | * are ignored so nothing special needs to be done besides |
| 1634 | * enabling the port. |
| 1635 | */ |
| 1636 | I915_WRITE(DDI_BUF_CTL(port), |
| 1637 | intel_dig_port->saved_port_bits | |
| 1638 | DDI_BUF_CTL_ENABLE); |
| 1639 | } else if (type == INTEL_OUTPUT_EDP) { |
| 1640 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1641 | |
| 1642 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
| 1643 | intel_dp_stop_link_train(intel_dp); |
| 1644 | |
| 1645 | intel_edp_backlight_on(intel_dp); |
| 1646 | intel_psr_enable(intel_dp); |
| 1647 | intel_edp_drrs_enable(intel_dp); |
| 1648 | } |
| 1649 | |
| 1650 | if (intel_crtc->config->has_audio) { |
| 1651 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
| 1652 | intel_audio_codec_enable(intel_encoder); |
| 1653 | } |
| 1654 | } |
| 1655 | |
| 1656 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
| 1657 | { |
| 1658 | struct drm_encoder *encoder = &intel_encoder->base; |
| 1659 | struct drm_crtc *crtc = encoder->crtc; |
| 1660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1661 | int type = intel_encoder->type; |
| 1662 | struct drm_device *dev = encoder->dev; |
| 1663 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1664 | |
| 1665 | if (intel_crtc->config->has_audio) { |
| 1666 | intel_audio_codec_disable(intel_encoder); |
| 1667 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
| 1668 | } |
| 1669 | |
| 1670 | if (type == INTEL_OUTPUT_EDP) { |
| 1671 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1672 | |
| 1673 | intel_edp_drrs_disable(intel_dp); |
| 1674 | intel_psr_disable(intel_dp); |
| 1675 | intel_edp_backlight_off(intel_dp); |
| 1676 | } |
| 1677 | } |
| 1678 | |
| 1679 | static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv) |
| 1680 | { |
| 1681 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); |
| 1682 | uint32_t cdctl = I915_READ(CDCLK_CTL); |
| 1683 | uint32_t linkrate; |
| 1684 | |
| 1685 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { |
| 1686 | WARN(1, "LCPLL1 not enabled\n"); |
| 1687 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
| 1688 | } |
| 1689 | |
| 1690 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) |
| 1691 | return 540000; |
| 1692 | |
| 1693 | linkrate = (I915_READ(DPLL_CTRL1) & |
| 1694 | DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
| 1695 | |
| 1696 | if (linkrate == DPLL_CRTL1_LINK_RATE_2160 || |
| 1697 | linkrate == DPLL_CRTL1_LINK_RATE_1080) { |
| 1698 | /* vco 8640 */ |
| 1699 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 1700 | case CDCLK_FREQ_450_432: |
| 1701 | return 432000; |
| 1702 | case CDCLK_FREQ_337_308: |
| 1703 | return 308570; |
| 1704 | case CDCLK_FREQ_675_617: |
| 1705 | return 617140; |
| 1706 | default: |
| 1707 | WARN(1, "Unknown cd freq selection\n"); |
| 1708 | } |
| 1709 | } else { |
| 1710 | /* vco 8100 */ |
| 1711 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
| 1712 | case CDCLK_FREQ_450_432: |
| 1713 | return 450000; |
| 1714 | case CDCLK_FREQ_337_308: |
| 1715 | return 337500; |
| 1716 | case CDCLK_FREQ_675_617: |
| 1717 | return 675000; |
| 1718 | default: |
| 1719 | WARN(1, "Unknown cd freq selection\n"); |
| 1720 | } |
| 1721 | } |
| 1722 | |
| 1723 | /* error case, do as if DPLL0 isn't enabled */ |
| 1724 | return 24000; |
| 1725 | } |
| 1726 | |
| 1727 | static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv) |
| 1728 | { |
| 1729 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 1730 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 1731 | |
| 1732 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 1733 | return 800000; |
| 1734 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 1735 | return 450000; |
| 1736 | else if (freq == LCPLL_CLK_FREQ_450) |
| 1737 | return 450000; |
| 1738 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
| 1739 | return 540000; |
| 1740 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
| 1741 | return 337500; |
| 1742 | else |
| 1743 | return 675000; |
| 1744 | } |
| 1745 | |
| 1746 | static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv) |
| 1747 | { |
| 1748 | struct drm_device *dev = dev_priv->dev; |
| 1749 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
| 1750 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
| 1751 | |
| 1752 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
| 1753 | return 800000; |
| 1754 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
| 1755 | return 450000; |
| 1756 | else if (freq == LCPLL_CLK_FREQ_450) |
| 1757 | return 450000; |
| 1758 | else if (IS_HSW_ULT(dev)) |
| 1759 | return 337500; |
| 1760 | else |
| 1761 | return 540000; |
| 1762 | } |
| 1763 | |
| 1764 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
| 1765 | { |
| 1766 | struct drm_device *dev = dev_priv->dev; |
| 1767 | |
| 1768 | if (IS_SKYLAKE(dev)) |
| 1769 | return skl_get_cdclk_freq(dev_priv); |
| 1770 | |
| 1771 | if (IS_BROADWELL(dev)) |
| 1772 | return bdw_get_cdclk_freq(dev_priv); |
| 1773 | |
| 1774 | /* Haswell */ |
| 1775 | return hsw_get_cdclk_freq(dev_priv); |
| 1776 | } |
| 1777 | |
| 1778 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
| 1779 | struct intel_shared_dpll *pll) |
| 1780 | { |
| 1781 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
| 1782 | POSTING_READ(WRPLL_CTL(pll->id)); |
| 1783 | udelay(20); |
| 1784 | } |
| 1785 | |
| 1786 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, |
| 1787 | struct intel_shared_dpll *pll) |
| 1788 | { |
| 1789 | uint32_t val; |
| 1790 | |
| 1791 | val = I915_READ(WRPLL_CTL(pll->id)); |
| 1792 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
| 1793 | POSTING_READ(WRPLL_CTL(pll->id)); |
| 1794 | } |
| 1795 | |
| 1796 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
| 1797 | struct intel_shared_dpll *pll, |
| 1798 | struct intel_dpll_hw_state *hw_state) |
| 1799 | { |
| 1800 | uint32_t val; |
| 1801 | |
| 1802 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 1803 | return false; |
| 1804 | |
| 1805 | val = I915_READ(WRPLL_CTL(pll->id)); |
| 1806 | hw_state->wrpll = val; |
| 1807 | |
| 1808 | return val & WRPLL_PLL_ENABLE; |
| 1809 | } |
| 1810 | |
| 1811 | static const char * const hsw_ddi_pll_names[] = { |
| 1812 | "WRPLL 1", |
| 1813 | "WRPLL 2", |
| 1814 | }; |
| 1815 | |
| 1816 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
| 1817 | { |
| 1818 | int i; |
| 1819 | |
| 1820 | dev_priv->num_shared_dpll = 2; |
| 1821 | |
| 1822 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 1823 | dev_priv->shared_dplls[i].id = i; |
| 1824 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; |
| 1825 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; |
| 1826 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; |
| 1827 | dev_priv->shared_dplls[i].get_hw_state = |
| 1828 | hsw_ddi_pll_get_hw_state; |
| 1829 | } |
| 1830 | } |
| 1831 | |
| 1832 | static const char * const skl_ddi_pll_names[] = { |
| 1833 | "DPLL 1", |
| 1834 | "DPLL 2", |
| 1835 | "DPLL 3", |
| 1836 | }; |
| 1837 | |
| 1838 | struct skl_dpll_regs { |
| 1839 | u32 ctl, cfgcr1, cfgcr2; |
| 1840 | }; |
| 1841 | |
| 1842 | /* this array is indexed by the *shared* pll id */ |
| 1843 | static const struct skl_dpll_regs skl_dpll_regs[3] = { |
| 1844 | { |
| 1845 | /* DPLL 1 */ |
| 1846 | .ctl = LCPLL2_CTL, |
| 1847 | .cfgcr1 = DPLL1_CFGCR1, |
| 1848 | .cfgcr2 = DPLL1_CFGCR2, |
| 1849 | }, |
| 1850 | { |
| 1851 | /* DPLL 2 */ |
| 1852 | .ctl = WRPLL_CTL1, |
| 1853 | .cfgcr1 = DPLL2_CFGCR1, |
| 1854 | .cfgcr2 = DPLL2_CFGCR2, |
| 1855 | }, |
| 1856 | { |
| 1857 | /* DPLL 3 */ |
| 1858 | .ctl = WRPLL_CTL2, |
| 1859 | .cfgcr1 = DPLL3_CFGCR1, |
| 1860 | .cfgcr2 = DPLL3_CFGCR2, |
| 1861 | }, |
| 1862 | }; |
| 1863 | |
| 1864 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, |
| 1865 | struct intel_shared_dpll *pll) |
| 1866 | { |
| 1867 | uint32_t val; |
| 1868 | unsigned int dpll; |
| 1869 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 1870 | |
| 1871 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
| 1872 | dpll = pll->id + 1; |
| 1873 | |
| 1874 | val = I915_READ(DPLL_CTRL1); |
| 1875 | |
| 1876 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | |
| 1877 | DPLL_CRTL1_LINK_RATE_MASK(dpll)); |
| 1878 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); |
| 1879 | |
| 1880 | I915_WRITE(DPLL_CTRL1, val); |
| 1881 | POSTING_READ(DPLL_CTRL1); |
| 1882 | |
| 1883 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); |
| 1884 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); |
| 1885 | POSTING_READ(regs[pll->id].cfgcr1); |
| 1886 | POSTING_READ(regs[pll->id].cfgcr2); |
| 1887 | |
| 1888 | /* the enable bit is always bit 31 */ |
| 1889 | I915_WRITE(regs[pll->id].ctl, |
| 1890 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); |
| 1891 | |
| 1892 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) |
| 1893 | DRM_ERROR("DPLL %d not locked\n", dpll); |
| 1894 | } |
| 1895 | |
| 1896 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, |
| 1897 | struct intel_shared_dpll *pll) |
| 1898 | { |
| 1899 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 1900 | |
| 1901 | /* the enable bit is always bit 31 */ |
| 1902 | I915_WRITE(regs[pll->id].ctl, |
| 1903 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); |
| 1904 | POSTING_READ(regs[pll->id].ctl); |
| 1905 | } |
| 1906 | |
| 1907 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
| 1908 | struct intel_shared_dpll *pll, |
| 1909 | struct intel_dpll_hw_state *hw_state) |
| 1910 | { |
| 1911 | uint32_t val; |
| 1912 | unsigned int dpll; |
| 1913 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 1914 | |
| 1915 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 1916 | return false; |
| 1917 | |
| 1918 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ |
| 1919 | dpll = pll->id + 1; |
| 1920 | |
| 1921 | val = I915_READ(regs[pll->id].ctl); |
| 1922 | if (!(val & LCPLL_PLL_ENABLE)) |
| 1923 | return false; |
| 1924 | |
| 1925 | val = I915_READ(DPLL_CTRL1); |
| 1926 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; |
| 1927 | |
| 1928 | /* avoid reading back stale values if HDMI mode is not enabled */ |
| 1929 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { |
| 1930 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); |
| 1931 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); |
| 1932 | } |
| 1933 | |
| 1934 | return true; |
| 1935 | } |
| 1936 | |
| 1937 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) |
| 1938 | { |
| 1939 | int i; |
| 1940 | |
| 1941 | dev_priv->num_shared_dpll = 3; |
| 1942 | |
| 1943 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 1944 | dev_priv->shared_dplls[i].id = i; |
| 1945 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; |
| 1946 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; |
| 1947 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; |
| 1948 | dev_priv->shared_dplls[i].get_hw_state = |
| 1949 | skl_ddi_pll_get_hw_state; |
| 1950 | } |
| 1951 | } |
| 1952 | |
| 1953 | void intel_ddi_pll_init(struct drm_device *dev) |
| 1954 | { |
| 1955 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1956 | uint32_t val = I915_READ(LCPLL_CTL); |
| 1957 | |
| 1958 | if (IS_SKYLAKE(dev)) |
| 1959 | skl_shared_dplls_init(dev_priv); |
| 1960 | else |
| 1961 | hsw_shared_dplls_init(dev_priv); |
| 1962 | |
| 1963 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
| 1964 | intel_ddi_get_cdclk_freq(dev_priv)); |
| 1965 | |
| 1966 | if (IS_SKYLAKE(dev)) { |
| 1967 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) |
| 1968 | DRM_ERROR("LCPLL1 is disabled\n"); |
| 1969 | } else { |
| 1970 | /* |
| 1971 | * The LCPLL register should be turned on by the BIOS. For now |
| 1972 | * let's just check its state and print errors in case |
| 1973 | * something is wrong. Don't even try to turn it on. |
| 1974 | */ |
| 1975 | |
| 1976 | if (val & LCPLL_CD_SOURCE_FCLK) |
| 1977 | DRM_ERROR("CDCLK source is not LCPLL\n"); |
| 1978 | |
| 1979 | if (val & LCPLL_PLL_DISABLE) |
| 1980 | DRM_ERROR("LCPLL is disabled\n"); |
| 1981 | } |
| 1982 | } |
| 1983 | |
| 1984 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) |
| 1985 | { |
| 1986 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 1987 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 1988 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
| 1989 | enum port port = intel_dig_port->port; |
| 1990 | uint32_t val; |
| 1991 | bool wait = false; |
| 1992 | |
| 1993 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { |
| 1994 | val = I915_READ(DDI_BUF_CTL(port)); |
| 1995 | if (val & DDI_BUF_CTL_ENABLE) { |
| 1996 | val &= ~DDI_BUF_CTL_ENABLE; |
| 1997 | I915_WRITE(DDI_BUF_CTL(port), val); |
| 1998 | wait = true; |
| 1999 | } |
| 2000 | |
| 2001 | val = I915_READ(DP_TP_CTL(port)); |
| 2002 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); |
| 2003 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2004 | I915_WRITE(DP_TP_CTL(port), val); |
| 2005 | POSTING_READ(DP_TP_CTL(port)); |
| 2006 | |
| 2007 | if (wait) |
| 2008 | intel_wait_ddi_buf_idle(dev_priv, port); |
| 2009 | } |
| 2010 | |
| 2011 | val = DP_TP_CTL_ENABLE | |
| 2012 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2013 | if (intel_dp->is_mst) |
| 2014 | val |= DP_TP_CTL_MODE_MST; |
| 2015 | else { |
| 2016 | val |= DP_TP_CTL_MODE_SST; |
| 2017 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2018 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
| 2019 | } |
| 2020 | I915_WRITE(DP_TP_CTL(port), val); |
| 2021 | POSTING_READ(DP_TP_CTL(port)); |
| 2022 | |
| 2023 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; |
| 2024 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); |
| 2025 | POSTING_READ(DDI_BUF_CTL(port)); |
| 2026 | |
| 2027 | udelay(600); |
| 2028 | } |
| 2029 | |
| 2030 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
| 2031 | { |
| 2032 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 2033 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
| 2034 | uint32_t val; |
| 2035 | |
| 2036 | intel_ddi_post_disable(intel_encoder); |
| 2037 | |
| 2038 | val = I915_READ(_FDI_RXA_CTL); |
| 2039 | val &= ~FDI_RX_ENABLE; |
| 2040 | I915_WRITE(_FDI_RXA_CTL, val); |
| 2041 | |
| 2042 | val = I915_READ(_FDI_RXA_MISC); |
| 2043 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
| 2044 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); |
| 2045 | I915_WRITE(_FDI_RXA_MISC, val); |
| 2046 | |
| 2047 | val = I915_READ(_FDI_RXA_CTL); |
| 2048 | val &= ~FDI_PCDCLK; |
| 2049 | I915_WRITE(_FDI_RXA_CTL, val); |
| 2050 | |
| 2051 | val = I915_READ(_FDI_RXA_CTL); |
| 2052 | val &= ~FDI_RX_PLL_ENABLE; |
| 2053 | I915_WRITE(_FDI_RXA_CTL, val); |
| 2054 | } |
| 2055 | |
| 2056 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
| 2057 | { |
| 2058 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 2059 | int type = intel_dig_port->base.type; |
| 2060 | |
| 2061 | if (type != INTEL_OUTPUT_DISPLAYPORT && |
| 2062 | type != INTEL_OUTPUT_EDP && |
| 2063 | type != INTEL_OUTPUT_UNKNOWN) { |
| 2064 | return; |
| 2065 | } |
| 2066 | |
| 2067 | intel_dp_hot_plug(intel_encoder); |
| 2068 | } |
| 2069 | |
| 2070 | void intel_ddi_get_config(struct intel_encoder *encoder, |
| 2071 | struct intel_crtc_state *pipe_config) |
| 2072 | { |
| 2073 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 2074 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 2075 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 2076 | struct intel_hdmi *intel_hdmi; |
| 2077 | u32 temp, flags = 0; |
| 2078 | |
| 2079 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
| 2080 | if (temp & TRANS_DDI_PHSYNC) |
| 2081 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2082 | else |
| 2083 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2084 | if (temp & TRANS_DDI_PVSYNC) |
| 2085 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2086 | else |
| 2087 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 2088 | |
| 2089 | pipe_config->base.adjusted_mode.flags |= flags; |
| 2090 | |
| 2091 | switch (temp & TRANS_DDI_BPC_MASK) { |
| 2092 | case TRANS_DDI_BPC_6: |
| 2093 | pipe_config->pipe_bpp = 18; |
| 2094 | break; |
| 2095 | case TRANS_DDI_BPC_8: |
| 2096 | pipe_config->pipe_bpp = 24; |
| 2097 | break; |
| 2098 | case TRANS_DDI_BPC_10: |
| 2099 | pipe_config->pipe_bpp = 30; |
| 2100 | break; |
| 2101 | case TRANS_DDI_BPC_12: |
| 2102 | pipe_config->pipe_bpp = 36; |
| 2103 | break; |
| 2104 | default: |
| 2105 | break; |
| 2106 | } |
| 2107 | |
| 2108 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { |
| 2109 | case TRANS_DDI_MODE_SELECT_HDMI: |
| 2110 | pipe_config->has_hdmi_sink = true; |
| 2111 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
| 2112 | |
| 2113 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
| 2114 | pipe_config->has_infoframe = true; |
| 2115 | break; |
| 2116 | case TRANS_DDI_MODE_SELECT_DVI: |
| 2117 | case TRANS_DDI_MODE_SELECT_FDI: |
| 2118 | break; |
| 2119 | case TRANS_DDI_MODE_SELECT_DP_SST: |
| 2120 | case TRANS_DDI_MODE_SELECT_DP_MST: |
| 2121 | pipe_config->has_dp_encoder = true; |
| 2122 | intel_dp_get_m_n(intel_crtc, pipe_config); |
| 2123 | break; |
| 2124 | default: |
| 2125 | break; |
| 2126 | } |
| 2127 | |
| 2128 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
| 2129 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
| 2130 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) |
| 2131 | pipe_config->has_audio = true; |
| 2132 | } |
| 2133 | |
| 2134 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
| 2135 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
| 2136 | /* |
| 2137 | * This is a big fat ugly hack. |
| 2138 | * |
| 2139 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2140 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2141 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2142 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2143 | * max, not what it tells us to use. |
| 2144 | * |
| 2145 | * Note: This will still be broken if the eDP panel is not lit |
| 2146 | * up by the BIOS, and thus we can't get the mode at module |
| 2147 | * load. |
| 2148 | */ |
| 2149 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
| 2150 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
| 2151 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
| 2152 | } |
| 2153 | |
| 2154 | intel_ddi_clock_get(encoder, pipe_config); |
| 2155 | } |
| 2156 | |
| 2157 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
| 2158 | { |
| 2159 | /* HDMI has nothing special to destroy, so we can go with this. */ |
| 2160 | intel_dp_encoder_destroy(encoder); |
| 2161 | } |
| 2162 | |
| 2163 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
| 2164 | struct intel_crtc_state *pipe_config) |
| 2165 | { |
| 2166 | int type = encoder->type; |
| 2167 | int port = intel_ddi_get_encoder_port(encoder); |
| 2168 | |
| 2169 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
| 2170 | |
| 2171 | if (port == PORT_A) |
| 2172 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 2173 | |
| 2174 | if (type == INTEL_OUTPUT_HDMI) |
| 2175 | return intel_hdmi_compute_config(encoder, pipe_config); |
| 2176 | else |
| 2177 | return intel_dp_compute_config(encoder, pipe_config); |
| 2178 | } |
| 2179 | |
| 2180 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
| 2181 | .destroy = intel_ddi_destroy, |
| 2182 | }; |
| 2183 | |
| 2184 | static struct intel_connector * |
| 2185 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) |
| 2186 | { |
| 2187 | struct intel_connector *connector; |
| 2188 | enum port port = intel_dig_port->port; |
| 2189 | |
| 2190 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); |
| 2191 | if (!connector) |
| 2192 | return NULL; |
| 2193 | |
| 2194 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
| 2195 | if (!intel_dp_init_connector(intel_dig_port, connector)) { |
| 2196 | kfree(connector); |
| 2197 | return NULL; |
| 2198 | } |
| 2199 | |
| 2200 | return connector; |
| 2201 | } |
| 2202 | |
| 2203 | static struct intel_connector * |
| 2204 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) |
| 2205 | { |
| 2206 | struct intel_connector *connector; |
| 2207 | enum port port = intel_dig_port->port; |
| 2208 | |
| 2209 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); |
| 2210 | if (!connector) |
| 2211 | return NULL; |
| 2212 | |
| 2213 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); |
| 2214 | intel_hdmi_init_connector(intel_dig_port, connector); |
| 2215 | |
| 2216 | return connector; |
| 2217 | } |
| 2218 | |
| 2219 | void intel_ddi_init(struct drm_device *dev, enum port port) |
| 2220 | { |
| 2221 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2222 | struct intel_digital_port *intel_dig_port; |
| 2223 | struct intel_encoder *intel_encoder; |
| 2224 | struct drm_encoder *encoder; |
| 2225 | bool init_hdmi, init_dp; |
| 2226 | |
| 2227 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || |
| 2228 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); |
| 2229 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; |
| 2230 | if (!init_dp && !init_hdmi) { |
| 2231 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", |
| 2232 | port_name(port)); |
| 2233 | init_hdmi = true; |
| 2234 | init_dp = true; |
| 2235 | } |
| 2236 | |
| 2237 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
| 2238 | if (!intel_dig_port) |
| 2239 | return; |
| 2240 | |
| 2241 | intel_encoder = &intel_dig_port->base; |
| 2242 | encoder = &intel_encoder->base; |
| 2243 | |
| 2244 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, |
| 2245 | DRM_MODE_ENCODER_TMDS); |
| 2246 | |
| 2247 | intel_encoder->compute_config = intel_ddi_compute_config; |
| 2248 | intel_encoder->enable = intel_enable_ddi; |
| 2249 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
| 2250 | intel_encoder->disable = intel_disable_ddi; |
| 2251 | intel_encoder->post_disable = intel_ddi_post_disable; |
| 2252 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
| 2253 | intel_encoder->get_config = intel_ddi_get_config; |
| 2254 | |
| 2255 | intel_dig_port->port = port; |
| 2256 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
| 2257 | (DDI_BUF_PORT_REVERSAL | |
| 2258 | DDI_A_4_LANES); |
| 2259 | |
| 2260 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
| 2261 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 2262 | intel_encoder->cloneable = 0; |
| 2263 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
| 2264 | |
| 2265 | if (init_dp) { |
| 2266 | if (!intel_ddi_init_dp_connector(intel_dig_port)) |
| 2267 | goto err; |
| 2268 | |
| 2269 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
| 2270 | dev_priv->hpd_irq_port[port] = intel_dig_port; |
| 2271 | } |
| 2272 | |
| 2273 | /* In theory we don't need the encoder->type check, but leave it just in |
| 2274 | * case we have some really bad VBTs... */ |
| 2275 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
| 2276 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) |
| 2277 | goto err; |
| 2278 | } |
| 2279 | |
| 2280 | return; |
| 2281 | |
| 2282 | err: |
| 2283 | drm_encoder_cleanup(encoder); |
| 2284 | kfree(intel_dig_port); |
| 2285 | } |