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drm/i915/skl: Adjust the port PLL selection code
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
50};
51
52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
62};
63
64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
78};
79
80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
90};
91
92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
98 { 0x00DB6FFF, 0x00160005 },
99 { 0x80C71FFF, 0x001A0002 },
100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
102};
103
104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
114};
115
116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
128};
129
130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
131 { 0x00000018, 0x000000a0 },
132 { 0x00004014, 0x00000098 },
133 { 0x00006012, 0x00000088 },
134 { 0x00008010, 0x00000080 },
135 { 0x00000018, 0x00000098 },
136 { 0x00004014, 0x00000088 },
137 { 0x00006012, 0x00000080 },
138 { 0x00000018, 0x00000088 },
139 { 0x00004014, 0x00000080 },
140};
141
142static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
154};
155
156enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
157{
158 struct drm_encoder *encoder = &intel_encoder->base;
159 int type = intel_encoder->type;
160
161 if (type == INTEL_OUTPUT_DP_MST) {
162 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
163 return intel_dig_port->port;
164 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
165 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
166 struct intel_digital_port *intel_dig_port =
167 enc_to_dig_port(encoder);
168 return intel_dig_port->port;
169
170 } else if (type == INTEL_OUTPUT_ANALOG) {
171 return PORT_E;
172
173 } else {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type);
175 BUG();
176 }
177}
178
179/*
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
184 * of those
185 */
186static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 u32 reg;
190 int i, n_hdmi_entries, hdmi_800mV_0dB;
191 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
192 const struct ddi_buf_trans *ddi_translations_fdi;
193 const struct ddi_buf_trans *ddi_translations_dp;
194 const struct ddi_buf_trans *ddi_translations_edp;
195 const struct ddi_buf_trans *ddi_translations_hdmi;
196 const struct ddi_buf_trans *ddi_translations;
197
198 if (IS_SKYLAKE(dev)) {
199 ddi_translations_fdi = NULL;
200 ddi_translations_dp = skl_ddi_translations_dp;
201 ddi_translations_edp = skl_ddi_translations_dp;
202 ddi_translations_hdmi = skl_ddi_translations_hdmi;
203 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
204 hdmi_800mV_0dB = 7;
205 } else if (IS_BROADWELL(dev)) {
206 ddi_translations_fdi = bdw_ddi_translations_fdi;
207 ddi_translations_dp = bdw_ddi_translations_dp;
208 ddi_translations_edp = bdw_ddi_translations_edp;
209 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
210 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
211 hdmi_800mV_0dB = 7;
212 } else if (IS_HASWELL(dev)) {
213 ddi_translations_fdi = hsw_ddi_translations_fdi;
214 ddi_translations_dp = hsw_ddi_translations_dp;
215 ddi_translations_edp = hsw_ddi_translations_dp;
216 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
217 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
218 hdmi_800mV_0dB = 6;
219 } else {
220 WARN(1, "ddi translation table missing\n");
221 ddi_translations_edp = bdw_ddi_translations_dp;
222 ddi_translations_fdi = bdw_ddi_translations_fdi;
223 ddi_translations_dp = bdw_ddi_translations_dp;
224 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
225 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
226 hdmi_800mV_0dB = 7;
227 }
228
229 switch (port) {
230 case PORT_A:
231 ddi_translations = ddi_translations_edp;
232 break;
233 case PORT_B:
234 case PORT_C:
235 ddi_translations = ddi_translations_dp;
236 break;
237 case PORT_D:
238 if (intel_dp_is_edp(dev, PORT_D))
239 ddi_translations = ddi_translations_edp;
240 else
241 ddi_translations = ddi_translations_dp;
242 break;
243 case PORT_E:
244 if (ddi_translations_fdi)
245 ddi_translations = ddi_translations_fdi;
246 else
247 ddi_translations = ddi_translations_dp;
248 break;
249 default:
250 BUG();
251 }
252
253 for (i = 0, reg = DDI_BUF_TRANS(port);
254 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
255 I915_WRITE(reg, ddi_translations[i].trans1);
256 reg += 4;
257 I915_WRITE(reg, ddi_translations[i].trans2);
258 reg += 4;
259 }
260
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
263 hdmi_level >= n_hdmi_entries)
264 hdmi_level = hdmi_800mV_0dB;
265
266 /* Entry 9 is for HDMI: */
267 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
268 reg += 4;
269 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
270 reg += 4;
271}
272
273/* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
275 */
276void intel_prepare_ddi(struct drm_device *dev)
277{
278 int port;
279
280 if (!HAS_DDI(dev))
281 return;
282
283 for (port = PORT_A; port <= PORT_E; port++)
284 intel_prepare_ddi_buffers(dev, port);
285}
286
287static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
288 enum port port)
289{
290 uint32_t reg = DDI_BUF_CTL(port);
291 int i;
292
293 for (i = 0; i < 8; i++) {
294 udelay(1);
295 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
296 return;
297 }
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
299}
300
301/* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
304 *
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
308 */
309
310void hsw_fdi_link_train(struct drm_crtc *crtc)
311{
312 struct drm_device *dev = crtc->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
315 u32 temp, i, rx_ctl_val;
316
317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
320 * - FDI delay to 90h
321 *
322 * WaFDIAutoLinkSetTimingOverrride:hsw
323 */
324 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
327
328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
330 FDI_RX_PLL_ENABLE |
331 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL);
334 udelay(220);
335
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val |= FDI_PCDCLK;
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
339
340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
342 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
343
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
346 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E),
349 DP_TP_CTL_FDI_AUTOTRAIN |
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
351 DP_TP_CTL_LINK_TRAIN_PAT1 |
352 DP_TP_CTL_ENABLE);
353
354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E),
359 DDI_BUF_CTL_ENABLE |
360 ((intel_crtc->config.fdi_lanes - 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i / 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E));
363
364 udelay(600);
365
366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
368
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
372 POSTING_READ(_FDI_RXA_CTL);
373
374 /* Wait for FDI receiver lane calibration */
375 udelay(30);
376
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp = I915_READ(_FDI_RXA_MISC);
379 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
380 I915_WRITE(_FDI_RXA_MISC, temp);
381 POSTING_READ(_FDI_RXA_MISC);
382
383 /* Wait for FDI auto training time */
384 udelay(5);
385
386 temp = I915_READ(DP_TP_STATUS(PORT_E));
387 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
389
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E),
392 DP_TP_CTL_FDI_AUTOTRAIN |
393 DP_TP_CTL_LINK_TRAIN_NORMAL |
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
395 DP_TP_CTL_ENABLE);
396
397 return;
398 }
399
400 temp = I915_READ(DDI_BUF_CTL(PORT_E));
401 temp &= ~DDI_BUF_CTL_ENABLE;
402 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
403 POSTING_READ(DDI_BUF_CTL(PORT_E));
404
405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
406 temp = I915_READ(DP_TP_CTL(PORT_E));
407 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
408 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
409 I915_WRITE(DP_TP_CTL(PORT_E), temp);
410 POSTING_READ(DP_TP_CTL(PORT_E));
411
412 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
413
414 rx_ctl_val &= ~FDI_RX_ENABLE;
415 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
416 POSTING_READ(_FDI_RXA_CTL);
417
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp = I915_READ(_FDI_RXA_MISC);
420 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC, temp);
423 POSTING_READ(_FDI_RXA_MISC);
424 }
425
426 DRM_ERROR("FDI link training failed!\n");
427}
428
429void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
430{
431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
432 struct intel_digital_port *intel_dig_port =
433 enc_to_dig_port(&encoder->base);
434
435 intel_dp->DP = intel_dig_port->saved_port_bits |
436 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
437 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
438
439}
440
441static struct intel_encoder *
442intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
443{
444 struct drm_device *dev = crtc->dev;
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
446 struct intel_encoder *intel_encoder, *ret = NULL;
447 int num_encoders = 0;
448
449 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
450 ret = intel_encoder;
451 num_encoders++;
452 }
453
454 if (num_encoders != 1)
455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
456 pipe_name(intel_crtc->pipe));
457
458 BUG_ON(ret == NULL);
459 return ret;
460}
461
462static struct intel_encoder *
463intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
464{
465 struct drm_device *dev = crtc->base.dev;
466 struct intel_encoder *intel_encoder, *ret = NULL;
467 int num_encoders = 0;
468
469 for_each_intel_encoder(dev, intel_encoder) {
470 if (intel_encoder->new_crtc == crtc) {
471 ret = intel_encoder;
472 num_encoders++;
473 }
474 }
475
476 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
477 pipe_name(crtc->pipe));
478
479 BUG_ON(ret == NULL);
480 return ret;
481}
482
483#define LC_FREQ 2700
484#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
485
486#define P_MIN 2
487#define P_MAX 64
488#define P_INC 2
489
490/* Constraints for PLL good behavior */
491#define REF_MIN 48
492#define REF_MAX 400
493#define VCO_MIN 2400
494#define VCO_MAX 4800
495
496#define abs_diff(a, b) ({ \
497 typeof(a) __a = (a); \
498 typeof(b) __b = (b); \
499 (void) (&__a == &__b); \
500 __a > __b ? (__a - __b) : (__b - __a); })
501
502struct wrpll_rnp {
503 unsigned p, n2, r2;
504};
505
506static unsigned wrpll_get_budget_for_freq(int clock)
507{
508 unsigned budget;
509
510 switch (clock) {
511 case 25175000:
512 case 25200000:
513 case 27000000:
514 case 27027000:
515 case 37762500:
516 case 37800000:
517 case 40500000:
518 case 40541000:
519 case 54000000:
520 case 54054000:
521 case 59341000:
522 case 59400000:
523 case 72000000:
524 case 74176000:
525 case 74250000:
526 case 81000000:
527 case 81081000:
528 case 89012000:
529 case 89100000:
530 case 108000000:
531 case 108108000:
532 case 111264000:
533 case 111375000:
534 case 148352000:
535 case 148500000:
536 case 162000000:
537 case 162162000:
538 case 222525000:
539 case 222750000:
540 case 296703000:
541 case 297000000:
542 budget = 0;
543 break;
544 case 233500000:
545 case 245250000:
546 case 247750000:
547 case 253250000:
548 case 298000000:
549 budget = 1500;
550 break;
551 case 169128000:
552 case 169500000:
553 case 179500000:
554 case 202000000:
555 budget = 2000;
556 break;
557 case 256250000:
558 case 262500000:
559 case 270000000:
560 case 272500000:
561 case 273750000:
562 case 280750000:
563 case 281250000:
564 case 286000000:
565 case 291750000:
566 budget = 4000;
567 break;
568 case 267250000:
569 case 268500000:
570 budget = 5000;
571 break;
572 default:
573 budget = 1000;
574 break;
575 }
576
577 return budget;
578}
579
580static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
581 unsigned r2, unsigned n2, unsigned p,
582 struct wrpll_rnp *best)
583{
584 uint64_t a, b, c, d, diff, diff_best;
585
586 /* No best (r,n,p) yet */
587 if (best->p == 0) {
588 best->p = p;
589 best->n2 = n2;
590 best->r2 = r2;
591 return;
592 }
593
594 /*
595 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
596 * freq2k.
597 *
598 * delta = 1e6 *
599 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
600 * freq2k;
601 *
602 * and we would like delta <= budget.
603 *
604 * If the discrepancy is above the PPM-based budget, always prefer to
605 * improve upon the previous solution. However, if you're within the
606 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
607 */
608 a = freq2k * budget * p * r2;
609 b = freq2k * budget * best->p * best->r2;
610 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
611 diff_best = abs_diff(freq2k * best->p * best->r2,
612 LC_FREQ_2K * best->n2);
613 c = 1000000 * diff;
614 d = 1000000 * diff_best;
615
616 if (a < c && b < d) {
617 /* If both are above the budget, pick the closer */
618 if (best->p * best->r2 * diff < p * r2 * diff_best) {
619 best->p = p;
620 best->n2 = n2;
621 best->r2 = r2;
622 }
623 } else if (a >= c && b < d) {
624 /* If A is below the threshold but B is above it? Update. */
625 best->p = p;
626 best->n2 = n2;
627 best->r2 = r2;
628 } else if (a >= c && b >= d) {
629 /* Both are below the limit, so pick the higher n2/(r2*r2) */
630 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
631 best->p = p;
632 best->n2 = n2;
633 best->r2 = r2;
634 }
635 }
636 /* Otherwise a < c && b >= d, do nothing */
637}
638
639static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
640 int reg)
641{
642 int refclk = LC_FREQ;
643 int n, p, r;
644 u32 wrpll;
645
646 wrpll = I915_READ(reg);
647 switch (wrpll & WRPLL_PLL_REF_MASK) {
648 case WRPLL_PLL_SSC:
649 case WRPLL_PLL_NON_SSC:
650 /*
651 * We could calculate spread here, but our checking
652 * code only cares about 5% accuracy, and spread is a max of
653 * 0.5% downspread.
654 */
655 refclk = 135;
656 break;
657 case WRPLL_PLL_LCPLL:
658 refclk = LC_FREQ;
659 break;
660 default:
661 WARN(1, "bad wrpll refclk\n");
662 return 0;
663 }
664
665 r = wrpll & WRPLL_DIVIDER_REF_MASK;
666 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
667 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
668
669 /* Convert to KHz, p & r have a fixed point portion */
670 return (refclk * n * 100) / (p * r);
671}
672
673static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
674 uint32_t dpll)
675{
676 uint32_t cfgcr1_reg, cfgcr2_reg;
677 uint32_t cfgcr1_val, cfgcr2_val;
678 uint32_t p0, p1, p2, dco_freq;
679
680 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
681 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
682
683 cfgcr1_val = I915_READ(cfgcr1_reg);
684 cfgcr2_val = I915_READ(cfgcr2_reg);
685
686 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
687 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
688
689 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
690 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
691 else
692 p1 = 1;
693
694
695 switch (p0) {
696 case DPLL_CFGCR2_PDIV_1:
697 p0 = 1;
698 break;
699 case DPLL_CFGCR2_PDIV_2:
700 p0 = 2;
701 break;
702 case DPLL_CFGCR2_PDIV_3:
703 p0 = 3;
704 break;
705 case DPLL_CFGCR2_PDIV_7:
706 p0 = 7;
707 break;
708 }
709
710 switch (p2) {
711 case DPLL_CFGCR2_KDIV_5:
712 p2 = 5;
713 break;
714 case DPLL_CFGCR2_KDIV_2:
715 p2 = 2;
716 break;
717 case DPLL_CFGCR2_KDIV_3:
718 p2 = 3;
719 break;
720 case DPLL_CFGCR2_KDIV_1:
721 p2 = 1;
722 break;
723 }
724
725 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
726
727 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
728 1000) / 0x8000;
729
730 return dco_freq / (p0 * p1 * p2 * 5);
731}
732
733
734static void skl_ddi_clock_get(struct intel_encoder *encoder,
735 struct intel_crtc_config *pipe_config)
736{
737 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
738 enum port port = intel_ddi_get_encoder_port(encoder);
739 int link_clock = 0;
740 uint32_t dpll_ctl1, dpll;
741
742 /* FIXME: This should be tracked in the pipe config. */
743 dpll = I915_READ(DPLL_CTRL2);
744 dpll &= DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
745 dpll >>= DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
746
747 dpll_ctl1 = I915_READ(DPLL_CTRL1);
748
749 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
750 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
751 } else {
752 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
753 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
754
755 switch (link_clock) {
756 case DPLL_CRTL1_LINK_RATE_810:
757 link_clock = 81000;
758 break;
759 case DPLL_CRTL1_LINK_RATE_1350:
760 link_clock = 135000;
761 break;
762 case DPLL_CRTL1_LINK_RATE_2700:
763 link_clock = 270000;
764 break;
765 default:
766 WARN(1, "Unsupported link rate\n");
767 break;
768 }
769 link_clock *= 2;
770 }
771
772 pipe_config->port_clock = link_clock;
773
774 if (pipe_config->has_dp_encoder)
775 pipe_config->adjusted_mode.crtc_clock =
776 intel_dotclock_calculate(pipe_config->port_clock,
777 &pipe_config->dp_m_n);
778 else
779 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
780}
781
782static void hsw_ddi_clock_get(struct intel_encoder *encoder,
783 struct intel_crtc_config *pipe_config)
784{
785 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
786 int link_clock = 0;
787 u32 val, pll;
788
789 val = pipe_config->ddi_pll_sel;
790 switch (val & PORT_CLK_SEL_MASK) {
791 case PORT_CLK_SEL_LCPLL_810:
792 link_clock = 81000;
793 break;
794 case PORT_CLK_SEL_LCPLL_1350:
795 link_clock = 135000;
796 break;
797 case PORT_CLK_SEL_LCPLL_2700:
798 link_clock = 270000;
799 break;
800 case PORT_CLK_SEL_WRPLL1:
801 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
802 break;
803 case PORT_CLK_SEL_WRPLL2:
804 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
805 break;
806 case PORT_CLK_SEL_SPLL:
807 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
808 if (pll == SPLL_PLL_FREQ_810MHz)
809 link_clock = 81000;
810 else if (pll == SPLL_PLL_FREQ_1350MHz)
811 link_clock = 135000;
812 else if (pll == SPLL_PLL_FREQ_2700MHz)
813 link_clock = 270000;
814 else {
815 WARN(1, "bad spll freq\n");
816 return;
817 }
818 break;
819 default:
820 WARN(1, "bad port clock sel\n");
821 return;
822 }
823
824 pipe_config->port_clock = link_clock * 2;
825
826 if (pipe_config->has_pch_encoder)
827 pipe_config->adjusted_mode.crtc_clock =
828 intel_dotclock_calculate(pipe_config->port_clock,
829 &pipe_config->fdi_m_n);
830 else if (pipe_config->has_dp_encoder)
831 pipe_config->adjusted_mode.crtc_clock =
832 intel_dotclock_calculate(pipe_config->port_clock,
833 &pipe_config->dp_m_n);
834 else
835 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
836}
837
838void intel_ddi_clock_get(struct intel_encoder *encoder,
839 struct intel_crtc_config *pipe_config)
840{
841 hsw_ddi_clock_get(encoder, pipe_config);
842}
843
844static void
845hsw_ddi_calculate_wrpll(int clock /* in Hz */,
846 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
847{
848 uint64_t freq2k;
849 unsigned p, n2, r2;
850 struct wrpll_rnp best = { 0, 0, 0 };
851 unsigned budget;
852
853 freq2k = clock / 100;
854
855 budget = wrpll_get_budget_for_freq(clock);
856
857 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
858 * and directly pass the LC PLL to it. */
859 if (freq2k == 5400000) {
860 *n2_out = 2;
861 *p_out = 1;
862 *r2_out = 2;
863 return;
864 }
865
866 /*
867 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
868 * the WR PLL.
869 *
870 * We want R so that REF_MIN <= Ref <= REF_MAX.
871 * Injecting R2 = 2 * R gives:
872 * REF_MAX * r2 > LC_FREQ * 2 and
873 * REF_MIN * r2 < LC_FREQ * 2
874 *
875 * Which means the desired boundaries for r2 are:
876 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
877 *
878 */
879 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
880 r2 <= LC_FREQ * 2 / REF_MIN;
881 r2++) {
882
883 /*
884 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
885 *
886 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
887 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
888 * VCO_MAX * r2 > n2 * LC_FREQ and
889 * VCO_MIN * r2 < n2 * LC_FREQ)
890 *
891 * Which means the desired boundaries for n2 are:
892 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
893 */
894 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
895 n2 <= VCO_MAX * r2 / LC_FREQ;
896 n2++) {
897
898 for (p = P_MIN; p <= P_MAX; p += P_INC)
899 wrpll_update_rnp(freq2k, budget,
900 r2, n2, p, &best);
901 }
902 }
903
904 *n2_out = best.n2;
905 *p_out = best.p;
906 *r2_out = best.r2;
907}
908
909static bool
910hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
911 struct intel_encoder *intel_encoder,
912 int clock)
913{
914 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
915 struct intel_shared_dpll *pll;
916 uint32_t val;
917 unsigned p, n2, r2;
918
919 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
920
921 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
922 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
923 WRPLL_DIVIDER_POST(p);
924
925 intel_crtc->new_config->dpll_hw_state.wrpll = val;
926
927 pll = intel_get_shared_dpll(intel_crtc);
928 if (pll == NULL) {
929 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
930 pipe_name(intel_crtc->pipe));
931 return false;
932 }
933
934 intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
935 }
936
937 return true;
938}
939
940
941/*
942 * Tries to find a *shared* PLL for the CRTC and store it in
943 * intel_crtc->ddi_pll_sel.
944 *
945 * For private DPLLs, compute_config() should do the selection for us. This
946 * function should be folded into compute_config() eventually.
947 */
948bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
949{
950 struct intel_encoder *intel_encoder =
951 intel_ddi_get_crtc_new_encoder(intel_crtc);
952 int clock = intel_crtc->new_config->port_clock;
953
954 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
955}
956
957void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
958{
959 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
961 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
962 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
963 int type = intel_encoder->type;
964 uint32_t temp;
965
966 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
967 temp = TRANS_MSA_SYNC_CLK;
968 switch (intel_crtc->config.pipe_bpp) {
969 case 18:
970 temp |= TRANS_MSA_6_BPC;
971 break;
972 case 24:
973 temp |= TRANS_MSA_8_BPC;
974 break;
975 case 30:
976 temp |= TRANS_MSA_10_BPC;
977 break;
978 case 36:
979 temp |= TRANS_MSA_12_BPC;
980 break;
981 default:
982 BUG();
983 }
984 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
985 }
986}
987
988void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
989{
990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
991 struct drm_device *dev = crtc->dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
994 uint32_t temp;
995 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
996 if (state == true)
997 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
998 else
999 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1000 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1001}
1002
1003void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1004{
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1007 struct drm_encoder *encoder = &intel_encoder->base;
1008 struct drm_device *dev = crtc->dev;
1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 enum pipe pipe = intel_crtc->pipe;
1011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1012 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1013 int type = intel_encoder->type;
1014 uint32_t temp;
1015
1016 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1017 temp = TRANS_DDI_FUNC_ENABLE;
1018 temp |= TRANS_DDI_SELECT_PORT(port);
1019
1020 switch (intel_crtc->config.pipe_bpp) {
1021 case 18:
1022 temp |= TRANS_DDI_BPC_6;
1023 break;
1024 case 24:
1025 temp |= TRANS_DDI_BPC_8;
1026 break;
1027 case 30:
1028 temp |= TRANS_DDI_BPC_10;
1029 break;
1030 case 36:
1031 temp |= TRANS_DDI_BPC_12;
1032 break;
1033 default:
1034 BUG();
1035 }
1036
1037 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1038 temp |= TRANS_DDI_PVSYNC;
1039 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1040 temp |= TRANS_DDI_PHSYNC;
1041
1042 if (cpu_transcoder == TRANSCODER_EDP) {
1043 switch (pipe) {
1044 case PIPE_A:
1045 /* On Haswell, can only use the always-on power well for
1046 * eDP when not using the panel fitter, and when not
1047 * using motion blur mitigation (which we don't
1048 * support). */
1049 if (IS_HASWELL(dev) &&
1050 (intel_crtc->config.pch_pfit.enabled ||
1051 intel_crtc->config.pch_pfit.force_thru))
1052 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1053 else
1054 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1055 break;
1056 case PIPE_B:
1057 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1058 break;
1059 case PIPE_C:
1060 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1061 break;
1062 default:
1063 BUG();
1064 break;
1065 }
1066 }
1067
1068 if (type == INTEL_OUTPUT_HDMI) {
1069 if (intel_crtc->config.has_hdmi_sink)
1070 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1071 else
1072 temp |= TRANS_DDI_MODE_SELECT_DVI;
1073
1074 } else if (type == INTEL_OUTPUT_ANALOG) {
1075 temp |= TRANS_DDI_MODE_SELECT_FDI;
1076 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
1077
1078 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1079 type == INTEL_OUTPUT_EDP) {
1080 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1081
1082 if (intel_dp->is_mst) {
1083 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1084 } else
1085 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1086
1087 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1088 } else if (type == INTEL_OUTPUT_DP_MST) {
1089 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1090
1091 if (intel_dp->is_mst) {
1092 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1093 } else
1094 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1095
1096 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1097 } else {
1098 WARN(1, "Invalid encoder type %d for pipe %c\n",
1099 intel_encoder->type, pipe_name(pipe));
1100 }
1101
1102 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1103}
1104
1105void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1106 enum transcoder cpu_transcoder)
1107{
1108 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1109 uint32_t val = I915_READ(reg);
1110
1111 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1112 val |= TRANS_DDI_PORT_NONE;
1113 I915_WRITE(reg, val);
1114}
1115
1116bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1117{
1118 struct drm_device *dev = intel_connector->base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 struct intel_encoder *intel_encoder = intel_connector->encoder;
1121 int type = intel_connector->base.connector_type;
1122 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1123 enum pipe pipe = 0;
1124 enum transcoder cpu_transcoder;
1125 enum intel_display_power_domain power_domain;
1126 uint32_t tmp;
1127
1128 power_domain = intel_display_port_power_domain(intel_encoder);
1129 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1130 return false;
1131
1132 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1133 return false;
1134
1135 if (port == PORT_A)
1136 cpu_transcoder = TRANSCODER_EDP;
1137 else
1138 cpu_transcoder = (enum transcoder) pipe;
1139
1140 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1141
1142 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1143 case TRANS_DDI_MODE_SELECT_HDMI:
1144 case TRANS_DDI_MODE_SELECT_DVI:
1145 return (type == DRM_MODE_CONNECTOR_HDMIA);
1146
1147 case TRANS_DDI_MODE_SELECT_DP_SST:
1148 if (type == DRM_MODE_CONNECTOR_eDP)
1149 return true;
1150 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1151 case TRANS_DDI_MODE_SELECT_DP_MST:
1152 /* if the transcoder is in MST state then
1153 * connector isn't connected */
1154 return false;
1155
1156 case TRANS_DDI_MODE_SELECT_FDI:
1157 return (type == DRM_MODE_CONNECTOR_VGA);
1158
1159 default:
1160 return false;
1161 }
1162}
1163
1164bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1165 enum pipe *pipe)
1166{
1167 struct drm_device *dev = encoder->base.dev;
1168 struct drm_i915_private *dev_priv = dev->dev_private;
1169 enum port port = intel_ddi_get_encoder_port(encoder);
1170 enum intel_display_power_domain power_domain;
1171 u32 tmp;
1172 int i;
1173
1174 power_domain = intel_display_port_power_domain(encoder);
1175 if (!intel_display_power_is_enabled(dev_priv, power_domain))
1176 return false;
1177
1178 tmp = I915_READ(DDI_BUF_CTL(port));
1179
1180 if (!(tmp & DDI_BUF_CTL_ENABLE))
1181 return false;
1182
1183 if (port == PORT_A) {
1184 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1185
1186 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1187 case TRANS_DDI_EDP_INPUT_A_ON:
1188 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1189 *pipe = PIPE_A;
1190 break;
1191 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1192 *pipe = PIPE_B;
1193 break;
1194 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1195 *pipe = PIPE_C;
1196 break;
1197 }
1198
1199 return true;
1200 } else {
1201 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1202 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1203
1204 if ((tmp & TRANS_DDI_PORT_MASK)
1205 == TRANS_DDI_SELECT_PORT(port)) {
1206 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1207 return false;
1208
1209 *pipe = i;
1210 return true;
1211 }
1212 }
1213 }
1214
1215 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1216
1217 return false;
1218}
1219
1220void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1221{
1222 struct drm_crtc *crtc = &intel_crtc->base;
1223 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1224 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1225 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1226 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1227
1228 if (cpu_transcoder != TRANSCODER_EDP)
1229 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1230 TRANS_CLK_SEL_PORT(port));
1231}
1232
1233void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1234{
1235 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1236 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1237
1238 if (cpu_transcoder != TRANSCODER_EDP)
1239 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1240 TRANS_CLK_SEL_DISABLED);
1241}
1242
1243static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1244{
1245 struct drm_encoder *encoder = &intel_encoder->base;
1246 struct drm_device *dev = encoder->dev;
1247 struct drm_i915_private *dev_priv = dev->dev_private;
1248 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1249 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1250 int type = intel_encoder->type;
1251
1252 if (type == INTEL_OUTPUT_EDP) {
1253 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1254 intel_edp_panel_on(intel_dp);
1255 }
1256
1257 if (IS_SKYLAKE(dev)) {
1258 uint32_t dpll = crtc->config.ddi_pll_sel;
1259 uint32_t val;
1260
1261 val = I915_READ(DPLL_CTRL2);
1262
1263 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1264 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1265 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1266 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1267
1268 I915_WRITE(DPLL_CTRL2, val);
1269 } else {
1270 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1271 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1272 }
1273
1274 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1275 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1276
1277 intel_ddi_init_dp_buf_reg(intel_encoder);
1278
1279 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1280 intel_dp_start_link_train(intel_dp);
1281 intel_dp_complete_link_train(intel_dp);
1282 if (port != PORT_A)
1283 intel_dp_stop_link_train(intel_dp);
1284 } else if (type == INTEL_OUTPUT_HDMI) {
1285 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1286
1287 intel_hdmi->set_infoframes(encoder,
1288 crtc->config.has_hdmi_sink,
1289 &crtc->config.adjusted_mode);
1290 }
1291}
1292
1293static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1294{
1295 struct drm_encoder *encoder = &intel_encoder->base;
1296 struct drm_device *dev = encoder->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1299 int type = intel_encoder->type;
1300 uint32_t val;
1301 bool wait = false;
1302
1303 val = I915_READ(DDI_BUF_CTL(port));
1304 if (val & DDI_BUF_CTL_ENABLE) {
1305 val &= ~DDI_BUF_CTL_ENABLE;
1306 I915_WRITE(DDI_BUF_CTL(port), val);
1307 wait = true;
1308 }
1309
1310 val = I915_READ(DP_TP_CTL(port));
1311 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1312 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1313 I915_WRITE(DP_TP_CTL(port), val);
1314
1315 if (wait)
1316 intel_wait_ddi_buf_idle(dev_priv, port);
1317
1318 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1319 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1320 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1321 intel_edp_panel_vdd_on(intel_dp);
1322 intel_edp_panel_off(intel_dp);
1323 }
1324
1325 if (IS_SKYLAKE(dev))
1326 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1327 DPLL_CTRL2_DDI_CLK_OFF(port)));
1328 else
1329 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1330}
1331
1332static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1333{
1334 struct drm_encoder *encoder = &intel_encoder->base;
1335 struct drm_crtc *crtc = encoder->crtc;
1336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1337 struct drm_device *dev = encoder->dev;
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1340 int type = intel_encoder->type;
1341
1342 if (type == INTEL_OUTPUT_HDMI) {
1343 struct intel_digital_port *intel_dig_port =
1344 enc_to_dig_port(encoder);
1345
1346 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1347 * are ignored so nothing special needs to be done besides
1348 * enabling the port.
1349 */
1350 I915_WRITE(DDI_BUF_CTL(port),
1351 intel_dig_port->saved_port_bits |
1352 DDI_BUF_CTL_ENABLE);
1353 } else if (type == INTEL_OUTPUT_EDP) {
1354 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1355
1356 if (port == PORT_A)
1357 intel_dp_stop_link_train(intel_dp);
1358
1359 intel_edp_backlight_on(intel_dp);
1360 intel_edp_psr_enable(intel_dp);
1361 }
1362
1363 if (intel_crtc->config.has_audio) {
1364 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1365 intel_audio_codec_enable(intel_encoder);
1366 }
1367}
1368
1369static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1370{
1371 struct drm_encoder *encoder = &intel_encoder->base;
1372 struct drm_crtc *crtc = encoder->crtc;
1373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1374 int type = intel_encoder->type;
1375 struct drm_device *dev = encoder->dev;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377
1378 if (intel_crtc->config.has_audio) {
1379 intel_audio_codec_disable(intel_encoder);
1380 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1381 }
1382
1383 if (type == INTEL_OUTPUT_EDP) {
1384 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1385
1386 intel_edp_psr_disable(intel_dp);
1387 intel_edp_backlight_off(intel_dp);
1388 }
1389}
1390
1391static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1392{
1393 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1394 uint32_t cdctl = I915_READ(CDCLK_CTL);
1395 uint32_t linkrate;
1396
1397 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1398 WARN(1, "LCPLL1 not enabled\n");
1399 return 24000; /* 24MHz is the cd freq with NSSC ref */
1400 }
1401
1402 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1403 return 540000;
1404
1405 linkrate = (I915_READ(DPLL_CTRL1) &
1406 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1407
1408 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1409 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1410 /* vco 8640 */
1411 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1412 case CDCLK_FREQ_450_432:
1413 return 432000;
1414 case CDCLK_FREQ_337_308:
1415 return 308570;
1416 case CDCLK_FREQ_675_617:
1417 return 617140;
1418 default:
1419 WARN(1, "Unknown cd freq selection\n");
1420 }
1421 } else {
1422 /* vco 8100 */
1423 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1424 case CDCLK_FREQ_450_432:
1425 return 450000;
1426 case CDCLK_FREQ_337_308:
1427 return 337500;
1428 case CDCLK_FREQ_675_617:
1429 return 675000;
1430 default:
1431 WARN(1, "Unknown cd freq selection\n");
1432 }
1433 }
1434
1435 /* error case, do as if DPLL0 isn't enabled */
1436 return 24000;
1437}
1438
1439static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1440{
1441 uint32_t lcpll = I915_READ(LCPLL_CTL);
1442 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1443
1444 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1445 return 800000;
1446 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1447 return 450000;
1448 else if (freq == LCPLL_CLK_FREQ_450)
1449 return 450000;
1450 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1451 return 540000;
1452 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1453 return 337500;
1454 else
1455 return 675000;
1456}
1457
1458static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1459{
1460 struct drm_device *dev = dev_priv->dev;
1461 uint32_t lcpll = I915_READ(LCPLL_CTL);
1462 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1463
1464 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1465 return 800000;
1466 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1467 return 450000;
1468 else if (freq == LCPLL_CLK_FREQ_450)
1469 return 450000;
1470 else if (IS_HSW_ULT(dev))
1471 return 337500;
1472 else
1473 return 540000;
1474}
1475
1476int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1477{
1478 struct drm_device *dev = dev_priv->dev;
1479
1480 if (IS_SKYLAKE(dev))
1481 return skl_get_cdclk_freq(dev_priv);
1482
1483 if (IS_BROADWELL(dev))
1484 return bdw_get_cdclk_freq(dev_priv);
1485
1486 /* Haswell */
1487 return hsw_get_cdclk_freq(dev_priv);
1488}
1489
1490static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1491 struct intel_shared_dpll *pll)
1492{
1493 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1494 POSTING_READ(WRPLL_CTL(pll->id));
1495 udelay(20);
1496}
1497
1498static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1499 struct intel_shared_dpll *pll)
1500{
1501 uint32_t val;
1502
1503 val = I915_READ(WRPLL_CTL(pll->id));
1504 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1505 POSTING_READ(WRPLL_CTL(pll->id));
1506}
1507
1508static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1509 struct intel_shared_dpll *pll,
1510 struct intel_dpll_hw_state *hw_state)
1511{
1512 uint32_t val;
1513
1514 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1515 return false;
1516
1517 val = I915_READ(WRPLL_CTL(pll->id));
1518 hw_state->wrpll = val;
1519
1520 return val & WRPLL_PLL_ENABLE;
1521}
1522
1523static const char * const hsw_ddi_pll_names[] = {
1524 "WRPLL 1",
1525 "WRPLL 2",
1526};
1527
1528static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1529{
1530 int i;
1531
1532 dev_priv->num_shared_dpll = 2;
1533
1534 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1535 dev_priv->shared_dplls[i].id = i;
1536 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1537 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1538 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1539 dev_priv->shared_dplls[i].get_hw_state =
1540 hsw_ddi_pll_get_hw_state;
1541 }
1542}
1543
1544static const char * const skl_ddi_pll_names[] = {
1545 "DPLL 1",
1546 "DPLL 2",
1547 "DPLL 3",
1548};
1549
1550struct skl_dpll_regs {
1551 u32 ctl, cfgcr1, cfgcr2;
1552};
1553
1554/* this array is indexed by the *shared* pll id */
1555static const struct skl_dpll_regs skl_dpll_regs[3] = {
1556 {
1557 /* DPLL 1 */
1558 .ctl = LCPLL2_CTL,
1559 .cfgcr1 = DPLL1_CFGCR1,
1560 .cfgcr2 = DPLL1_CFGCR2,
1561 },
1562 {
1563 /* DPLL 2 */
1564 .ctl = WRPLL_CTL1,
1565 .cfgcr1 = DPLL2_CFGCR1,
1566 .cfgcr2 = DPLL2_CFGCR2,
1567 },
1568 {
1569 /* DPLL 3 */
1570 .ctl = WRPLL_CTL2,
1571 .cfgcr1 = DPLL3_CFGCR1,
1572 .cfgcr2 = DPLL3_CFGCR2,
1573 },
1574};
1575
1576static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1577 struct intel_shared_dpll *pll)
1578{
1579 uint32_t val;
1580 unsigned int dpll;
1581 const struct skl_dpll_regs *regs = skl_dpll_regs;
1582
1583 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1584 dpll = pll->id + 1;
1585
1586 val = I915_READ(DPLL_CTRL1);
1587
1588 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1589 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1590 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1591
1592 I915_WRITE(DPLL_CTRL1, val);
1593 POSTING_READ(DPLL_CTRL1);
1594
1595 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1596 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1597 POSTING_READ(regs[pll->id].cfgcr1);
1598 POSTING_READ(regs[pll->id].cfgcr2);
1599
1600 /* the enable bit is always bit 31 */
1601 I915_WRITE(regs[pll->id].ctl,
1602 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1603
1604 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1605 DRM_ERROR("DPLL %d not locked\n", dpll);
1606}
1607
1608static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1609 struct intel_shared_dpll *pll)
1610{
1611 const struct skl_dpll_regs *regs = skl_dpll_regs;
1612
1613 /* the enable bit is always bit 31 */
1614 I915_WRITE(regs[pll->id].ctl,
1615 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1616 POSTING_READ(regs[pll->id].ctl);
1617}
1618
1619static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1620 struct intel_shared_dpll *pll,
1621 struct intel_dpll_hw_state *hw_state)
1622{
1623 uint32_t val;
1624 unsigned int dpll;
1625 const struct skl_dpll_regs *regs = skl_dpll_regs;
1626
1627 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1628 return false;
1629
1630 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1631 dpll = pll->id + 1;
1632
1633 val = I915_READ(regs[pll->id].ctl);
1634 if (!(val & LCPLL_PLL_ENABLE))
1635 return false;
1636
1637 val = I915_READ(DPLL_CTRL1);
1638 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1639
1640 /* avoid reading back stale values if HDMI mode is not enabled */
1641 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1642 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1643 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1644 }
1645
1646 return true;
1647}
1648
1649static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1650{
1651 int i;
1652
1653 dev_priv->num_shared_dpll = 3;
1654
1655 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1656 dev_priv->shared_dplls[i].id = i;
1657 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1658 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1659 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1660 dev_priv->shared_dplls[i].get_hw_state =
1661 skl_ddi_pll_get_hw_state;
1662 }
1663}
1664
1665void intel_ddi_pll_init(struct drm_device *dev)
1666{
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1668 uint32_t val = I915_READ(LCPLL_CTL);
1669
1670 if (IS_SKYLAKE(dev))
1671 skl_shared_dplls_init(dev_priv);
1672 else
1673 hsw_shared_dplls_init(dev_priv);
1674
1675 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1676 intel_ddi_get_cdclk_freq(dev_priv));
1677
1678 if (IS_SKYLAKE(dev)) {
1679 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1680 DRM_ERROR("LCPLL1 is disabled\n");
1681 } else {
1682 /*
1683 * The LCPLL register should be turned on by the BIOS. For now
1684 * let's just check its state and print errors in case
1685 * something is wrong. Don't even try to turn it on.
1686 */
1687
1688 if (val & LCPLL_CD_SOURCE_FCLK)
1689 DRM_ERROR("CDCLK source is not LCPLL\n");
1690
1691 if (val & LCPLL_PLL_DISABLE)
1692 DRM_ERROR("LCPLL is disabled\n");
1693 }
1694}
1695
1696void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1697{
1698 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1699 struct intel_dp *intel_dp = &intel_dig_port->dp;
1700 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1701 enum port port = intel_dig_port->port;
1702 uint32_t val;
1703 bool wait = false;
1704
1705 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1706 val = I915_READ(DDI_BUF_CTL(port));
1707 if (val & DDI_BUF_CTL_ENABLE) {
1708 val &= ~DDI_BUF_CTL_ENABLE;
1709 I915_WRITE(DDI_BUF_CTL(port), val);
1710 wait = true;
1711 }
1712
1713 val = I915_READ(DP_TP_CTL(port));
1714 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1715 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1716 I915_WRITE(DP_TP_CTL(port), val);
1717 POSTING_READ(DP_TP_CTL(port));
1718
1719 if (wait)
1720 intel_wait_ddi_buf_idle(dev_priv, port);
1721 }
1722
1723 val = DP_TP_CTL_ENABLE |
1724 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1725 if (intel_dp->is_mst)
1726 val |= DP_TP_CTL_MODE_MST;
1727 else {
1728 val |= DP_TP_CTL_MODE_SST;
1729 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1730 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1731 }
1732 I915_WRITE(DP_TP_CTL(port), val);
1733 POSTING_READ(DP_TP_CTL(port));
1734
1735 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1736 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1737 POSTING_READ(DDI_BUF_CTL(port));
1738
1739 udelay(600);
1740}
1741
1742void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1743{
1744 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1745 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1746 uint32_t val;
1747
1748 intel_ddi_post_disable(intel_encoder);
1749
1750 val = I915_READ(_FDI_RXA_CTL);
1751 val &= ~FDI_RX_ENABLE;
1752 I915_WRITE(_FDI_RXA_CTL, val);
1753
1754 val = I915_READ(_FDI_RXA_MISC);
1755 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1756 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1757 I915_WRITE(_FDI_RXA_MISC, val);
1758
1759 val = I915_READ(_FDI_RXA_CTL);
1760 val &= ~FDI_PCDCLK;
1761 I915_WRITE(_FDI_RXA_CTL, val);
1762
1763 val = I915_READ(_FDI_RXA_CTL);
1764 val &= ~FDI_RX_PLL_ENABLE;
1765 I915_WRITE(_FDI_RXA_CTL, val);
1766}
1767
1768static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1769{
1770 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1771 int type = intel_dig_port->base.type;
1772
1773 if (type != INTEL_OUTPUT_DISPLAYPORT &&
1774 type != INTEL_OUTPUT_EDP &&
1775 type != INTEL_OUTPUT_UNKNOWN) {
1776 return;
1777 }
1778
1779 intel_dp_hot_plug(intel_encoder);
1780}
1781
1782void intel_ddi_get_config(struct intel_encoder *encoder,
1783 struct intel_crtc_config *pipe_config)
1784{
1785 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1786 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1787 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1788 u32 temp, flags = 0;
1789 struct drm_device *dev = dev_priv->dev;
1790
1791 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1792 if (temp & TRANS_DDI_PHSYNC)
1793 flags |= DRM_MODE_FLAG_PHSYNC;
1794 else
1795 flags |= DRM_MODE_FLAG_NHSYNC;
1796 if (temp & TRANS_DDI_PVSYNC)
1797 flags |= DRM_MODE_FLAG_PVSYNC;
1798 else
1799 flags |= DRM_MODE_FLAG_NVSYNC;
1800
1801 pipe_config->adjusted_mode.flags |= flags;
1802
1803 switch (temp & TRANS_DDI_BPC_MASK) {
1804 case TRANS_DDI_BPC_6:
1805 pipe_config->pipe_bpp = 18;
1806 break;
1807 case TRANS_DDI_BPC_8:
1808 pipe_config->pipe_bpp = 24;
1809 break;
1810 case TRANS_DDI_BPC_10:
1811 pipe_config->pipe_bpp = 30;
1812 break;
1813 case TRANS_DDI_BPC_12:
1814 pipe_config->pipe_bpp = 36;
1815 break;
1816 default:
1817 break;
1818 }
1819
1820 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1821 case TRANS_DDI_MODE_SELECT_HDMI:
1822 pipe_config->has_hdmi_sink = true;
1823 case TRANS_DDI_MODE_SELECT_DVI:
1824 case TRANS_DDI_MODE_SELECT_FDI:
1825 break;
1826 case TRANS_DDI_MODE_SELECT_DP_SST:
1827 case TRANS_DDI_MODE_SELECT_DP_MST:
1828 pipe_config->has_dp_encoder = true;
1829 intel_dp_get_m_n(intel_crtc, pipe_config);
1830 break;
1831 default:
1832 break;
1833 }
1834
1835 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1836 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1837 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
1838 pipe_config->has_audio = true;
1839 }
1840
1841 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1842 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1843 /*
1844 * This is a big fat ugly hack.
1845 *
1846 * Some machines in UEFI boot mode provide us a VBT that has 18
1847 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1848 * unknown we fail to light up. Yet the same BIOS boots up with
1849 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1850 * max, not what it tells us to use.
1851 *
1852 * Note: This will still be broken if the eDP panel is not lit
1853 * up by the BIOS, and thus we can't get the mode at module
1854 * load.
1855 */
1856 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1857 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1858 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1859 }
1860
1861 if (INTEL_INFO(dev)->gen <= 8)
1862 hsw_ddi_clock_get(encoder, pipe_config);
1863 else
1864 skl_ddi_clock_get(encoder, pipe_config);
1865}
1866
1867static void intel_ddi_destroy(struct drm_encoder *encoder)
1868{
1869 /* HDMI has nothing special to destroy, so we can go with this. */
1870 intel_dp_encoder_destroy(encoder);
1871}
1872
1873static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1874 struct intel_crtc_config *pipe_config)
1875{
1876 int type = encoder->type;
1877 int port = intel_ddi_get_encoder_port(encoder);
1878
1879 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1880
1881 if (port == PORT_A)
1882 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1883
1884 if (type == INTEL_OUTPUT_HDMI)
1885 return intel_hdmi_compute_config(encoder, pipe_config);
1886 else
1887 return intel_dp_compute_config(encoder, pipe_config);
1888}
1889
1890static const struct drm_encoder_funcs intel_ddi_funcs = {
1891 .destroy = intel_ddi_destroy,
1892};
1893
1894static struct intel_connector *
1895intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1896{
1897 struct intel_connector *connector;
1898 enum port port = intel_dig_port->port;
1899
1900 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1901 if (!connector)
1902 return NULL;
1903
1904 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1905 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1906 kfree(connector);
1907 return NULL;
1908 }
1909
1910 return connector;
1911}
1912
1913static struct intel_connector *
1914intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1915{
1916 struct intel_connector *connector;
1917 enum port port = intel_dig_port->port;
1918
1919 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1920 if (!connector)
1921 return NULL;
1922
1923 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1924 intel_hdmi_init_connector(intel_dig_port, connector);
1925
1926 return connector;
1927}
1928
1929void intel_ddi_init(struct drm_device *dev, enum port port)
1930{
1931 struct drm_i915_private *dev_priv = dev->dev_private;
1932 struct intel_digital_port *intel_dig_port;
1933 struct intel_encoder *intel_encoder;
1934 struct drm_encoder *encoder;
1935 bool init_hdmi, init_dp;
1936
1937 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1938 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1939 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1940 if (!init_dp && !init_hdmi) {
1941 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1942 port_name(port));
1943 init_hdmi = true;
1944 init_dp = true;
1945 }
1946
1947 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1948 if (!intel_dig_port)
1949 return;
1950
1951 intel_encoder = &intel_dig_port->base;
1952 encoder = &intel_encoder->base;
1953
1954 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1955 DRM_MODE_ENCODER_TMDS);
1956
1957 intel_encoder->compute_config = intel_ddi_compute_config;
1958 intel_encoder->enable = intel_enable_ddi;
1959 intel_encoder->pre_enable = intel_ddi_pre_enable;
1960 intel_encoder->disable = intel_disable_ddi;
1961 intel_encoder->post_disable = intel_ddi_post_disable;
1962 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1963 intel_encoder->get_config = intel_ddi_get_config;
1964
1965 intel_dig_port->port = port;
1966 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1967 (DDI_BUF_PORT_REVERSAL |
1968 DDI_A_4_LANES);
1969
1970 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1971 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1972 intel_encoder->cloneable = 0;
1973 intel_encoder->hot_plug = intel_ddi_hot_plug;
1974
1975 if (init_dp) {
1976 if (!intel_ddi_init_dp_connector(intel_dig_port))
1977 goto err;
1978
1979 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1980 dev_priv->hpd_irq_port[port] = intel_dig_port;
1981 }
1982
1983 /* In theory we don't need the encoder->type check, but leave it just in
1984 * case we have some really bad VBTs... */
1985 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1986 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1987 goto err;
1988 }
1989
1990 return;
1991
1992err:
1993 drm_encoder_cleanup(encoder);
1994 kfree(intel_dig_port);
1995}
Linux kernel - Deliverables
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