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drm/i915: move wedged to the other gpu error handling stuff
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
42#include <linux/dma_remapping.h>
43
44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45static void intel_increase_pllclock(struct drm_crtc *crtc);
46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58} intel_clock_t;
59
60typedef struct {
61 int min, max;
62} intel_range_t;
63
64typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76};
77
78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99
100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
104static bool
105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
122}
123
124static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
150};
151
152static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
178};
179
180
181static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
193 },
194 .find_pll = intel_g4x_find_best_PLL,
195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
237 },
238 .find_pll = intel_g4x_find_best_PLL,
239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
253};
254
255static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
269};
270
271static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
283};
284
285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
290static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
302};
303
304static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
330};
331
332/* LVDS 100mhz refclk limits. */
333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
373};
374
375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
420
421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
423 return 0;
424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
431 return 0;
432 }
433
434 return I915_READ(DPIO_DATA);
435}
436
437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
441
442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
444 return;
445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
453}
454
455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
468{
469 struct drm_device *dev = crtc->dev;
470 const intel_limit_t *limit;
471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
473 if (intel_is_dual_link_lvds(dev)) {
474 /* LVDS dual channel */
475 if (refclk == 100000)
476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
480 if (refclk == 100000)
481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
487 limit = &intel_limits_ironlake_display_port;
488 else
489 limit = &intel_limits_ironlake_dac;
490
491 return limit;
492}
493
494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
500 if (intel_is_dual_link_lvds(dev))
501 /* LVDS with dual channel */
502 limit = &intel_limits_g4x_dual_channel_lvds;
503 else
504 /* LVDS with dual channel */
505 limit = &intel_limits_g4x_single_channel_lvds;
506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
508 limit = &intel_limits_g4x_hdmi;
509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
510 limit = &intel_limits_g4x_sdvo;
511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
512 limit = &intel_limits_g4x_display_port;
513 } else /* The option is for other outputs */
514 limit = &intel_limits_i9xx_sdvo;
515
516 return limit;
517}
518
519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
524 if (HAS_PCH_SPLIT(dev))
525 limit = intel_ironlake_limit(crtc, refclk);
526 else if (IS_G4X(dev)) {
527 limit = intel_g4x_limit(crtc);
528 } else if (IS_PINEVIEW(dev)) {
529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
530 limit = &intel_limits_pineview_lvds;
531 else
532 limit = &intel_limits_pineview_sdvo;
533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
547 limit = &intel_limits_i8xx_lvds;
548 else
549 limit = &intel_limits_i8xx_dvo;
550 }
551 return limit;
552}
553
554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
556{
557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
567 return;
568 }
569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
579{
580 struct drm_device *dev = crtc->dev;
581 struct intel_encoder *encoder;
582
583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
585 return true;
586
587 return false;
588}
589
590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
599{
600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
601 INTELPllInvalid("p1 out of range\n");
602 if (clock->p < limit->p.min || limit->p.max < clock->p)
603 INTELPllInvalid("p out of range\n");
604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
605 INTELPllInvalid("m2 out of range\n");
606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
607 INTELPllInvalid("m1 out of range\n");
608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
609 INTELPllInvalid("m1 <= m2\n");
610 if (clock->m < limit->m.min || limit->m.max < clock->m)
611 INTELPllInvalid("m out of range\n");
612 if (clock->n < limit->n.min || limit->n.max < clock->n)
613 INTELPllInvalid("n out of range\n");
614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
615 INTELPllInvalid("vco out of range\n");
616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
620 INTELPllInvalid("dot out of range\n");
621
622 return true;
623}
624
625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
629
630{
631 struct drm_device *dev = crtc->dev;
632 intel_clock_t clock;
633 int err = target;
634
635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
636 /*
637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
640 */
641 if (intel_is_dual_link_lvds(dev))
642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
652 memset(best_clock, 0, sizeof(*best_clock));
653
654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
665 int this_err;
666
667 intel_clock(dev, refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
670 continue;
671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
692{
693 struct drm_device *dev = crtc->dev;
694 intel_clock_t clock;
695 int max_n;
696 bool found;
697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
702 int lvds_reg;
703
704 if (HAS_PCH_SPLIT(dev))
705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 intel_clock(dev, refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
739
740 this_err = abs(clock.dot - target);
741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
751 return found;
752}
753
754static bool
755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
761
762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
785{
786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
806}
807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
818 flag = 0;
819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
875
876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
905{
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 int pipestat_reg = PIPESTAT(pipe);
908
909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
930 /* Wait for vblank interrupt bit to set */
931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
952 *
953 */
954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
959
960 if (INTEL_INFO(dev)->gen >= 4) {
961 int reg = PIPECONF(cpu_transcoder);
962
963 /* Wait for the Pipe State to go off */
964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
966 WARN(1, "pipe_off wait timed out\n");
967 } else {
968 u32 last_line, line_mask;
969 int reg = PIPEDSL(pipe);
970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
977 /* Wait for the display line to settle */
978 do {
979 last_line = I915_READ(reg) & line_mask;
980 mdelay(5);
981 } while (((I915_READ(reg) & line_mask) != last_line) &&
982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
984 WARN(1, "pipe_off wait timed out\n");
985 }
986}
987
988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
1061{
1062 u32 val;
1063 bool cur_state;
1064
1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072 return;
1073
1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
1097 }
1098}
1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
1110
1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156 if (HAS_DDI(dev_priv->dev))
1157 return;
1158
1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
1181 bool locked = true;
1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
1201 pipe_name(pipe));
1202}
1203
1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
1206{
1207 int reg;
1208 u32 val;
1209 bool cur_state;
1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
1212
1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
1217 reg = PIPECONF(cpu_transcoder);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & PIPECONF_ENABLE);
1220 WARN(cur_state != state,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
1222 pipe_name(pipe), state_string(state), state_string(cur_state));
1223}
1224
1225static void assert_plane(struct drm_i915_private *dev_priv,
1226 enum plane plane, bool state)
1227{
1228 int reg;
1229 u32 val;
1230 bool cur_state;
1231
1232 reg = DSPCNTR(plane);
1233 val = I915_READ(reg);
1234 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1235 WARN(cur_state != state,
1236 "plane %c assertion failure (expected %s, current %s)\n",
1237 plane_name(plane), state_string(state), state_string(cur_state));
1238}
1239
1240#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1241#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1242
1243static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 enum pipe pipe)
1245{
1246 int reg, i;
1247 u32 val;
1248 int cur_pipe;
1249
1250 /* Planes are fixed to pipes on ILK+ */
1251 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1252 reg = DSPCNTR(pipe);
1253 val = I915_READ(reg);
1254 WARN((val & DISPLAY_PLANE_ENABLE),
1255 "plane %c assertion failure, should be disabled but not\n",
1256 plane_name(pipe));
1257 return;
1258 }
1259
1260 /* Need to check both planes against the pipe */
1261 for (i = 0; i < 2; i++) {
1262 reg = DSPCNTR(i);
1263 val = I915_READ(reg);
1264 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265 DISPPLANE_SEL_PIPE_SHIFT;
1266 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i), pipe_name(pipe));
1269 }
1270}
1271
1272static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1273{
1274 u32 val;
1275 bool enabled;
1276
1277 if (HAS_PCH_LPT(dev_priv->dev)) {
1278 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1279 return;
1280 }
1281
1282 val = I915_READ(PCH_DREF_CONTROL);
1283 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1284 DREF_SUPERSPREAD_SOURCE_MASK));
1285 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1286}
1287
1288static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290{
1291 int reg;
1292 u32 val;
1293 bool enabled;
1294
1295 reg = TRANSCONF(pipe);
1296 val = I915_READ(reg);
1297 enabled = !!(val & TRANS_ENABLE);
1298 WARN(enabled,
1299 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1300 pipe_name(pipe));
1301}
1302
1303static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, u32 port_sel, u32 val)
1305{
1306 if ((val & DP_PORT_EN) == 0)
1307 return false;
1308
1309 if (HAS_PCH_CPT(dev_priv->dev)) {
1310 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1311 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1312 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1313 return false;
1314 } else {
1315 if ((val & DP_PIPE_MASK) != (pipe << 30))
1316 return false;
1317 }
1318 return true;
1319}
1320
1321static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, u32 val)
1323{
1324 if ((val & PORT_ENABLE) == 0)
1325 return false;
1326
1327 if (HAS_PCH_CPT(dev_priv->dev)) {
1328 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1329 return false;
1330 } else {
1331 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1332 return false;
1333 }
1334 return true;
1335}
1336
1337static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, u32 val)
1339{
1340 if ((val & LVDS_PORT_EN) == 0)
1341 return false;
1342
1343 if (HAS_PCH_CPT(dev_priv->dev)) {
1344 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1345 return false;
1346 } else {
1347 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1348 return false;
1349 }
1350 return true;
1351}
1352
1353static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe, u32 val)
1355{
1356 if ((val & ADPA_DAC_ENABLE) == 0)
1357 return false;
1358 if (HAS_PCH_CPT(dev_priv->dev)) {
1359 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1360 return false;
1361 } else {
1362 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1363 return false;
1364 }
1365 return true;
1366}
1367
1368static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe, int reg, u32 port_sel)
1370{
1371 u32 val = I915_READ(reg);
1372 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1373 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1374 reg, pipe_name(pipe));
1375
1376 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1377 && (val & DP_PIPEB_SELECT),
1378 "IBX PCH dp port still using transcoder B\n");
1379}
1380
1381static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, int reg)
1383{
1384 u32 val = I915_READ(reg);
1385 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1386 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1387 reg, pipe_name(pipe));
1388
1389 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1390 && (val & SDVO_PIPE_B_SELECT),
1391 "IBX PCH hdmi port still using transcoder B\n");
1392}
1393
1394static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
1399
1400 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1403
1404 reg = PCH_ADPA;
1405 val = I915_READ(reg);
1406 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
1408 pipe_name(pipe));
1409
1410 reg = PCH_LVDS;
1411 val = I915_READ(reg);
1412 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1414 pipe_name(pipe));
1415
1416 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1419}
1420
1421/**
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1425 *
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1429 *
1430 * Note! This is for pre-ILK only.
1431 *
1432 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1433 */
1434static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* No really, not for ILK+ */
1440 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1441
1442 /* PLL is protected by panel, make sure we can write it */
1443 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1444 assert_panel_unlocked(dev_priv, pipe);
1445
1446 reg = DPLL(pipe);
1447 val = I915_READ(reg);
1448 val |= DPLL_VCO_ENABLE;
1449
1450 /* We do this three times for luck */
1451 I915_WRITE(reg, val);
1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460}
1461
1462/**
1463 * intel_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1466 *
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 *
1469 * Note! This is for pre-ILK only.
1470 */
1471static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
1475
1476 /* Don't disable pipe A or pipe A PLLs if needed */
1477 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1478 return;
1479
1480 /* Make sure the pipe isn't still relying on us */
1481 assert_pipe_disabled(dev_priv, pipe);
1482
1483 reg = DPLL(pipe);
1484 val = I915_READ(reg);
1485 val &= ~DPLL_VCO_ENABLE;
1486 I915_WRITE(reg, val);
1487 POSTING_READ(reg);
1488}
1489
1490/* SBI access */
1491static void
1492intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1493 enum intel_sbi_destination destination)
1494{
1495 u32 tmp;
1496
1497 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1498
1499 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1500 100)) {
1501 DRM_ERROR("timeout waiting for SBI to become ready\n");
1502 return;
1503 }
1504
1505 I915_WRITE(SBI_ADDR, (reg << 16));
1506 I915_WRITE(SBI_DATA, value);
1507
1508 if (destination == SBI_ICLK)
1509 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1510 else
1511 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1512 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1513
1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 return;
1518 }
1519}
1520
1521static u32
1522intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1523 enum intel_sbi_destination destination)
1524{
1525 u32 value = 0;
1526 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1527
1528 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to become ready\n");
1531 return 0;
1532 }
1533
1534 I915_WRITE(SBI_ADDR, (reg << 16));
1535
1536 if (destination == SBI_ICLK)
1537 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1538 else
1539 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1540 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1541
1542 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1543 100)) {
1544 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1545 return 0;
1546 }
1547
1548 return I915_READ(SBI_DATA);
1549}
1550
1551/**
1552 * ironlake_enable_pch_pll - enable PCH PLL
1553 * @dev_priv: i915 private structure
1554 * @pipe: pipe PLL to enable
1555 *
1556 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1557 * drives the transcoder clock.
1558 */
1559static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1560{
1561 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1562 struct intel_pch_pll *pll;
1563 int reg;
1564 u32 val;
1565
1566 /* PCH PLLs only available on ILK, SNB and IVB */
1567 BUG_ON(dev_priv->info->gen < 5);
1568 pll = intel_crtc->pch_pll;
1569 if (pll == NULL)
1570 return;
1571
1572 if (WARN_ON(pll->refcount == 0))
1573 return;
1574
1575 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1576 pll->pll_reg, pll->active, pll->on,
1577 intel_crtc->base.base.id);
1578
1579 /* PCH refclock must be enabled first */
1580 assert_pch_refclk_enabled(dev_priv);
1581
1582 if (pll->active++ && pll->on) {
1583 assert_pch_pll_enabled(dev_priv, pll, NULL);
1584 return;
1585 }
1586
1587 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1588
1589 reg = pll->pll_reg;
1590 val = I915_READ(reg);
1591 val |= DPLL_VCO_ENABLE;
1592 I915_WRITE(reg, val);
1593 POSTING_READ(reg);
1594 udelay(200);
1595
1596 pll->on = true;
1597}
1598
1599static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1600{
1601 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1602 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1603 int reg;
1604 u32 val;
1605
1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv->info->gen < 5);
1608 if (pll == NULL)
1609 return;
1610
1611 if (WARN_ON(pll->refcount == 0))
1612 return;
1613
1614 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1615 pll->pll_reg, pll->active, pll->on,
1616 intel_crtc->base.base.id);
1617
1618 if (WARN_ON(pll->active == 0)) {
1619 assert_pch_pll_disabled(dev_priv, pll, NULL);
1620 return;
1621 }
1622
1623 if (--pll->active) {
1624 assert_pch_pll_enabled(dev_priv, pll, NULL);
1625 return;
1626 }
1627
1628 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1629
1630 /* Make sure transcoder isn't still depending on us */
1631 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1632
1633 reg = pll->pll_reg;
1634 val = I915_READ(reg);
1635 val &= ~DPLL_VCO_ENABLE;
1636 I915_WRITE(reg, val);
1637 POSTING_READ(reg);
1638 udelay(200);
1639
1640 pll->on = false;
1641}
1642
1643static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1644 enum pipe pipe)
1645{
1646 struct drm_device *dev = dev_priv->dev;
1647 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1648 uint32_t reg, val, pipeconf_val;
1649
1650 /* PCH only available on ILK+ */
1651 BUG_ON(dev_priv->info->gen < 5);
1652
1653 /* Make sure PCH DPLL is enabled */
1654 assert_pch_pll_enabled(dev_priv,
1655 to_intel_crtc(crtc)->pch_pll,
1656 to_intel_crtc(crtc));
1657
1658 /* FDI must be feeding us bits for PCH ports */
1659 assert_fdi_tx_enabled(dev_priv, pipe);
1660 assert_fdi_rx_enabled(dev_priv, pipe);
1661
1662 if (HAS_PCH_CPT(dev)) {
1663 /* Workaround: Set the timing override bit before enabling the
1664 * pch transcoder. */
1665 reg = TRANS_CHICKEN2(pipe);
1666 val = I915_READ(reg);
1667 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1668 I915_WRITE(reg, val);
1669 }
1670
1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
1673 pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
1680 val &= ~PIPECONF_BPC_MASK;
1681 val |= pipeconf_val & PIPECONF_BPC_MASK;
1682 }
1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
1699static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1700 enum transcoder cpu_transcoder)
1701{
1702 u32 val, pipeconf_val;
1703
1704 /* PCH only available on ILK+ */
1705 BUG_ON(dev_priv->info->gen < 5);
1706
1707 /* FDI must be feeding us bits for PCH ports */
1708 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1709 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1710
1711 /* Workaround: set timing override bit. */
1712 val = I915_READ(_TRANSA_CHICKEN2);
1713 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1714 I915_WRITE(_TRANSA_CHICKEN2, val);
1715
1716 val = TRANS_ENABLE;
1717 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1718
1719 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1720 PIPECONF_INTERLACED_ILK)
1721 val |= TRANS_INTERLACED;
1722 else
1723 val |= TRANS_PROGRESSIVE;
1724
1725 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1726 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1727 DRM_ERROR("Failed to enable PCH transcoder\n");
1728}
1729
1730static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1731 enum pipe pipe)
1732{
1733 struct drm_device *dev = dev_priv->dev;
1734 uint32_t reg, val;
1735
1736 /* FDI relies on the transcoder */
1737 assert_fdi_tx_disabled(dev_priv, pipe);
1738 assert_fdi_rx_disabled(dev_priv, pipe);
1739
1740 /* Ports must be off as well */
1741 assert_pch_ports_disabled(dev_priv, pipe);
1742
1743 reg = TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 val &= ~TRANS_ENABLE;
1746 I915_WRITE(reg, val);
1747 /* wait for PCH transcoder off, transcoder state */
1748 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1749 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1750
1751 if (!HAS_PCH_IBX(dev)) {
1752 /* Workaround: Clear the timing override chicken bit again. */
1753 reg = TRANS_CHICKEN2(pipe);
1754 val = I915_READ(reg);
1755 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1756 I915_WRITE(reg, val);
1757 }
1758}
1759
1760static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1761{
1762 u32 val;
1763
1764 val = I915_READ(_TRANSACONF);
1765 val &= ~TRANS_ENABLE;
1766 I915_WRITE(_TRANSACONF, val);
1767 /* wait for PCH transcoder off, transcoder state */
1768 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1769 DRM_ERROR("Failed to disable PCH transcoder\n");
1770
1771 /* Workaround: clear timing override bit. */
1772 val = I915_READ(_TRANSA_CHICKEN2);
1773 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1774 I915_WRITE(_TRANSA_CHICKEN2, val);
1775}
1776
1777/**
1778 * intel_enable_pipe - enable a pipe, asserting requirements
1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe to enable
1781 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1782 *
1783 * Enable @pipe, making sure that various hardware specific requirements
1784 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1785 *
1786 * @pipe should be %PIPE_A or %PIPE_B.
1787 *
1788 * Will wait until the pipe is actually running (i.e. first vblank) before
1789 * returning.
1790 */
1791static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1792 bool pch_port)
1793{
1794 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1795 pipe);
1796 enum pipe pch_transcoder;
1797 int reg;
1798 u32 val;
1799
1800 if (HAS_PCH_LPT(dev_priv->dev))
1801 pch_transcoder = TRANSCODER_A;
1802 else
1803 pch_transcoder = pipe;
1804
1805 /*
1806 * A pipe without a PLL won't actually be able to drive bits from
1807 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1808 * need the check.
1809 */
1810 if (!HAS_PCH_SPLIT(dev_priv->dev))
1811 assert_pll_enabled(dev_priv, pipe);
1812 else {
1813 if (pch_port) {
1814 /* if driving the PCH, we need FDI enabled */
1815 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1816 assert_fdi_tx_pll_enabled(dev_priv,
1817 (enum pipe) cpu_transcoder);
1818 }
1819 /* FIXME: assert CPU port conditions for SNB+ */
1820 }
1821
1822 reg = PIPECONF(cpu_transcoder);
1823 val = I915_READ(reg);
1824 if (val & PIPECONF_ENABLE)
1825 return;
1826
1827 I915_WRITE(reg, val | PIPECONF_ENABLE);
1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
1831/**
1832 * intel_disable_pipe - disable a pipe, asserting requirements
1833 * @dev_priv: i915 private structure
1834 * @pipe: pipe to disable
1835 *
1836 * Disable @pipe, making sure that various hardware specific requirements
1837 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1838 *
1839 * @pipe should be %PIPE_A or %PIPE_B.
1840 *
1841 * Will wait until the pipe has shut down before returning.
1842 */
1843static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1844 enum pipe pipe)
1845{
1846 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1847 pipe);
1848 int reg;
1849 u32 val;
1850
1851 /*
1852 * Make sure planes won't keep trying to pump pixels to us,
1853 * or we might hang the display.
1854 */
1855 assert_planes_disabled(dev_priv, pipe);
1856
1857 /* Don't disable pipe A or pipe A PLLs if needed */
1858 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1859 return;
1860
1861 reg = PIPECONF(cpu_transcoder);
1862 val = I915_READ(reg);
1863 if ((val & PIPECONF_ENABLE) == 0)
1864 return;
1865
1866 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1867 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1868}
1869
1870/*
1871 * Plane regs are double buffered, going from enabled->disabled needs a
1872 * trigger in order to latch. The display address reg provides this.
1873 */
1874void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1875 enum plane plane)
1876{
1877 if (dev_priv->info->gen >= 4)
1878 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1879 else
1880 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1881}
1882
1883/**
1884 * intel_enable_plane - enable a display plane on a given pipe
1885 * @dev_priv: i915 private structure
1886 * @plane: plane to enable
1887 * @pipe: pipe being fed
1888 *
1889 * Enable @plane on @pipe, making sure that @pipe is running first.
1890 */
1891static void intel_enable_plane(struct drm_i915_private *dev_priv,
1892 enum plane plane, enum pipe pipe)
1893{
1894 int reg;
1895 u32 val;
1896
1897 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1898 assert_pipe_enabled(dev_priv, pipe);
1899
1900 reg = DSPCNTR(plane);
1901 val = I915_READ(reg);
1902 if (val & DISPLAY_PLANE_ENABLE)
1903 return;
1904
1905 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1906 intel_flush_display_plane(dev_priv, plane);
1907 intel_wait_for_vblank(dev_priv->dev, pipe);
1908}
1909
1910/**
1911 * intel_disable_plane - disable a display plane
1912 * @dev_priv: i915 private structure
1913 * @plane: plane to disable
1914 * @pipe: pipe consuming the data
1915 *
1916 * Disable @plane; should be an independent operation.
1917 */
1918static void intel_disable_plane(struct drm_i915_private *dev_priv,
1919 enum plane plane, enum pipe pipe)
1920{
1921 int reg;
1922 u32 val;
1923
1924 reg = DSPCNTR(plane);
1925 val = I915_READ(reg);
1926 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1927 return;
1928
1929 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1930 intel_flush_display_plane(dev_priv, plane);
1931 intel_wait_for_vblank(dev_priv->dev, pipe);
1932}
1933
1934int
1935intel_pin_and_fence_fb_obj(struct drm_device *dev,
1936 struct drm_i915_gem_object *obj,
1937 struct intel_ring_buffer *pipelined)
1938{
1939 struct drm_i915_private *dev_priv = dev->dev_private;
1940 u32 alignment;
1941 int ret;
1942
1943 switch (obj->tiling_mode) {
1944 case I915_TILING_NONE:
1945 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1946 alignment = 128 * 1024;
1947 else if (INTEL_INFO(dev)->gen >= 4)
1948 alignment = 4 * 1024;
1949 else
1950 alignment = 64 * 1024;
1951 break;
1952 case I915_TILING_X:
1953 /* pin() will align the object as required by fence */
1954 alignment = 0;
1955 break;
1956 case I915_TILING_Y:
1957 /* FIXME: Is this true? */
1958 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1959 return -EINVAL;
1960 default:
1961 BUG();
1962 }
1963
1964 dev_priv->mm.interruptible = false;
1965 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1966 if (ret)
1967 goto err_interruptible;
1968
1969 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1970 * fence, whereas 965+ only requires a fence if using
1971 * framebuffer compression. For simplicity, we always install
1972 * a fence as the cost is not that onerous.
1973 */
1974 ret = i915_gem_object_get_fence(obj);
1975 if (ret)
1976 goto err_unpin;
1977
1978 i915_gem_object_pin_fence(obj);
1979
1980 dev_priv->mm.interruptible = true;
1981 return 0;
1982
1983err_unpin:
1984 i915_gem_object_unpin(obj);
1985err_interruptible:
1986 dev_priv->mm.interruptible = true;
1987 return ret;
1988}
1989
1990void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1991{
1992 i915_gem_object_unpin_fence(obj);
1993 i915_gem_object_unpin(obj);
1994}
1995
1996/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1997 * is assumed to be a power-of-two. */
1998unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1999 unsigned int bpp,
2000 unsigned int pitch)
2001{
2002 int tile_rows, tiles;
2003
2004 tile_rows = *y / 8;
2005 *y %= 8;
2006 tiles = *x / (512/bpp);
2007 *x %= 512/bpp;
2008
2009 return tile_rows * pitch * 8 + tiles * 4096;
2010}
2011
2012static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2013 int x, int y)
2014{
2015 struct drm_device *dev = crtc->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2018 struct intel_framebuffer *intel_fb;
2019 struct drm_i915_gem_object *obj;
2020 int plane = intel_crtc->plane;
2021 unsigned long linear_offset;
2022 u32 dspcntr;
2023 u32 reg;
2024
2025 switch (plane) {
2026 case 0:
2027 case 1:
2028 break;
2029 default:
2030 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2031 return -EINVAL;
2032 }
2033
2034 intel_fb = to_intel_framebuffer(fb);
2035 obj = intel_fb->obj;
2036
2037 reg = DSPCNTR(plane);
2038 dspcntr = I915_READ(reg);
2039 /* Mask out pixel format bits in case we change it */
2040 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2041 switch (fb->pixel_format) {
2042 case DRM_FORMAT_C8:
2043 dspcntr |= DISPPLANE_8BPP;
2044 break;
2045 case DRM_FORMAT_XRGB1555:
2046 case DRM_FORMAT_ARGB1555:
2047 dspcntr |= DISPPLANE_BGRX555;
2048 break;
2049 case DRM_FORMAT_RGB565:
2050 dspcntr |= DISPPLANE_BGRX565;
2051 break;
2052 case DRM_FORMAT_XRGB8888:
2053 case DRM_FORMAT_ARGB8888:
2054 dspcntr |= DISPPLANE_BGRX888;
2055 break;
2056 case DRM_FORMAT_XBGR8888:
2057 case DRM_FORMAT_ABGR8888:
2058 dspcntr |= DISPPLANE_RGBX888;
2059 break;
2060 case DRM_FORMAT_XRGB2101010:
2061 case DRM_FORMAT_ARGB2101010:
2062 dspcntr |= DISPPLANE_BGRX101010;
2063 break;
2064 case DRM_FORMAT_XBGR2101010:
2065 case DRM_FORMAT_ABGR2101010:
2066 dspcntr |= DISPPLANE_RGBX101010;
2067 break;
2068 default:
2069 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2070 return -EINVAL;
2071 }
2072
2073 if (INTEL_INFO(dev)->gen >= 4) {
2074 if (obj->tiling_mode != I915_TILING_NONE)
2075 dspcntr |= DISPPLANE_TILED;
2076 else
2077 dspcntr &= ~DISPPLANE_TILED;
2078 }
2079
2080 I915_WRITE(reg, dspcntr);
2081
2082 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2083
2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 intel_crtc->dspaddr_offset =
2086 intel_gen4_compute_offset_xtiled(&x, &y,
2087 fb->bits_per_pixel / 8,
2088 fb->pitches[0]);
2089 linear_offset -= intel_crtc->dspaddr_offset;
2090 } else {
2091 intel_crtc->dspaddr_offset = linear_offset;
2092 }
2093
2094 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2095 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2096 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2097 if (INTEL_INFO(dev)->gen >= 4) {
2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
2099 obj->gtt_offset + intel_crtc->dspaddr_offset);
2100 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2101 I915_WRITE(DSPLINOFF(plane), linear_offset);
2102 } else
2103 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2104 POSTING_READ(reg);
2105
2106 return 0;
2107}
2108
2109static int ironlake_update_plane(struct drm_crtc *crtc,
2110 struct drm_framebuffer *fb, int x, int y)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2115 struct intel_framebuffer *intel_fb;
2116 struct drm_i915_gem_object *obj;
2117 int plane = intel_crtc->plane;
2118 unsigned long linear_offset;
2119 u32 dspcntr;
2120 u32 reg;
2121
2122 switch (plane) {
2123 case 0:
2124 case 1:
2125 case 2:
2126 break;
2127 default:
2128 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2129 return -EINVAL;
2130 }
2131
2132 intel_fb = to_intel_framebuffer(fb);
2133 obj = intel_fb->obj;
2134
2135 reg = DSPCNTR(plane);
2136 dspcntr = I915_READ(reg);
2137 /* Mask out pixel format bits in case we change it */
2138 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2139 switch (fb->pixel_format) {
2140 case DRM_FORMAT_C8:
2141 dspcntr |= DISPPLANE_8BPP;
2142 break;
2143 case DRM_FORMAT_RGB565:
2144 dspcntr |= DISPPLANE_BGRX565;
2145 break;
2146 case DRM_FORMAT_XRGB8888:
2147 case DRM_FORMAT_ARGB8888:
2148 dspcntr |= DISPPLANE_BGRX888;
2149 break;
2150 case DRM_FORMAT_XBGR8888:
2151 case DRM_FORMAT_ABGR8888:
2152 dspcntr |= DISPPLANE_RGBX888;
2153 break;
2154 case DRM_FORMAT_XRGB2101010:
2155 case DRM_FORMAT_ARGB2101010:
2156 dspcntr |= DISPPLANE_BGRX101010;
2157 break;
2158 case DRM_FORMAT_XBGR2101010:
2159 case DRM_FORMAT_ABGR2101010:
2160 dspcntr |= DISPPLANE_RGBX101010;
2161 break;
2162 default:
2163 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2164 return -EINVAL;
2165 }
2166
2167 if (obj->tiling_mode != I915_TILING_NONE)
2168 dspcntr |= DISPPLANE_TILED;
2169 else
2170 dspcntr &= ~DISPPLANE_TILED;
2171
2172 /* must disable */
2173 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2174
2175 I915_WRITE(reg, dspcntr);
2176
2177 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2178 intel_crtc->dspaddr_offset =
2179 intel_gen4_compute_offset_xtiled(&x, &y,
2180 fb->bits_per_pixel / 8,
2181 fb->pitches[0]);
2182 linear_offset -= intel_crtc->dspaddr_offset;
2183
2184 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2185 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2186 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2187 I915_MODIFY_DISPBASE(DSPSURF(plane),
2188 obj->gtt_offset + intel_crtc->dspaddr_offset);
2189 if (IS_HASWELL(dev)) {
2190 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2191 } else {
2192 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2193 I915_WRITE(DSPLINOFF(plane), linear_offset);
2194 }
2195 POSTING_READ(reg);
2196
2197 return 0;
2198}
2199
2200/* Assume fb object is pinned & idle & fenced and just update base pointers */
2201static int
2202intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2203 int x, int y, enum mode_set_atomic state)
2204{
2205 struct drm_device *dev = crtc->dev;
2206 struct drm_i915_private *dev_priv = dev->dev_private;
2207
2208 if (dev_priv->display.disable_fbc)
2209 dev_priv->display.disable_fbc(dev);
2210 intel_increase_pllclock(crtc);
2211
2212 return dev_priv->display.update_plane(crtc, fb, x, y);
2213}
2214
2215static int
2216intel_finish_fb(struct drm_framebuffer *old_fb)
2217{
2218 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2219 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2220 bool was_interruptible = dev_priv->mm.interruptible;
2221 int ret;
2222
2223 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2224
2225 wait_event(dev_priv->pending_flip_queue,
2226 atomic_read(&dev_priv->gpu_error.wedged) ||
2227 atomic_read(&obj->pending_flip) == 0);
2228
2229 /* Big Hammer, we also need to ensure that any pending
2230 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231 * current scanout is retired before unpinning the old
2232 * framebuffer.
2233 *
2234 * This should only fail upon a hung GPU, in which case we
2235 * can safely continue.
2236 */
2237 dev_priv->mm.interruptible = false;
2238 ret = i915_gem_object_finish_gpu(obj);
2239 dev_priv->mm.interruptible = was_interruptible;
2240
2241 return ret;
2242}
2243
2244static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2245{
2246 struct drm_device *dev = crtc->dev;
2247 struct drm_i915_master_private *master_priv;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
2250 if (!dev->primary->master)
2251 return;
2252
2253 master_priv = dev->primary->master->driver_priv;
2254 if (!master_priv->sarea_priv)
2255 return;
2256
2257 switch (intel_crtc->pipe) {
2258 case 0:
2259 master_priv->sarea_priv->pipeA_x = x;
2260 master_priv->sarea_priv->pipeA_y = y;
2261 break;
2262 case 1:
2263 master_priv->sarea_priv->pipeB_x = x;
2264 master_priv->sarea_priv->pipeB_y = y;
2265 break;
2266 default:
2267 break;
2268 }
2269}
2270
2271static int
2272intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2273 struct drm_framebuffer *fb)
2274{
2275 struct drm_device *dev = crtc->dev;
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2278 struct drm_framebuffer *old_fb;
2279 int ret;
2280
2281 /* no fb bound */
2282 if (!fb) {
2283 DRM_ERROR("No FB bound\n");
2284 return 0;
2285 }
2286
2287 if(intel_crtc->plane > dev_priv->num_pipe) {
2288 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2289 intel_crtc->plane,
2290 dev_priv->num_pipe);
2291 return -EINVAL;
2292 }
2293
2294 mutex_lock(&dev->struct_mutex);
2295 ret = intel_pin_and_fence_fb_obj(dev,
2296 to_intel_framebuffer(fb)->obj,
2297 NULL);
2298 if (ret != 0) {
2299 mutex_unlock(&dev->struct_mutex);
2300 DRM_ERROR("pin & fence failed\n");
2301 return ret;
2302 }
2303
2304 if (crtc->fb)
2305 intel_finish_fb(crtc->fb);
2306
2307 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2308 if (ret) {
2309 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2310 mutex_unlock(&dev->struct_mutex);
2311 DRM_ERROR("failed to update base address\n");
2312 return ret;
2313 }
2314
2315 old_fb = crtc->fb;
2316 crtc->fb = fb;
2317 crtc->x = x;
2318 crtc->y = y;
2319
2320 if (old_fb) {
2321 intel_wait_for_vblank(dev, intel_crtc->pipe);
2322 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2323 }
2324
2325 intel_update_fbc(dev);
2326 mutex_unlock(&dev->struct_mutex);
2327
2328 intel_crtc_update_sarea_pos(crtc, x, y);
2329
2330 return 0;
2331}
2332
2333static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334{
2335 struct drm_device *dev = crtc->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 int pipe = intel_crtc->pipe;
2339 u32 reg, temp;
2340
2341 /* enable normal train */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
2344 if (IS_IVYBRIDGE(dev)) {
2345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2347 } else {
2348 temp &= ~FDI_LINK_TRAIN_NONE;
2349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2350 }
2351 I915_WRITE(reg, temp);
2352
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 if (HAS_PCH_CPT(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358 } else {
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_NONE;
2361 }
2362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364 /* wait one idle pattern time */
2365 POSTING_READ(reg);
2366 udelay(1000);
2367
2368 /* IVB wants error correction enabled */
2369 if (IS_IVYBRIDGE(dev))
2370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371 FDI_FE_ERRC_ENABLE);
2372}
2373
2374static void ivb_modeset_global_resources(struct drm_device *dev)
2375{
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct intel_crtc *pipe_B_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2379 struct intel_crtc *pipe_C_crtc =
2380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2381 uint32_t temp;
2382
2383 /* When everything is off disable fdi C so that we could enable fdi B
2384 * with all lanes. XXX: This misses the case where a pipe is not using
2385 * any pch resources and so doesn't need any fdi lanes. */
2386 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395}
2396
2397/* The FDI link training functions for ILK/Ibexpeak. */
2398static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 int plane = intel_crtc->plane;
2405 u32 reg, temp, tries;
2406
2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
2419 udelay(150);
2420
2421 /* enable CPU FDI TX and PCH FDI RX */
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~(7 << 19);
2425 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2429
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
2437 udelay(150);
2438
2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
2443
2444 reg = FDI_RX_IIR(pipe);
2445 for (tries = 0; tries < 5; tries++) {
2446 temp = I915_READ(reg);
2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 break;
2453 }
2454 }
2455 if (tries == 5)
2456 DRM_ERROR("FDI train 1 fail!\n");
2457
2458 /* Train 2 */
2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
2463 I915_WRITE(reg, temp);
2464
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2470
2471 POSTING_READ(reg);
2472 udelay(150);
2473
2474 reg = FDI_RX_IIR(pipe);
2475 for (tries = 0; tries < 5; tries++) {
2476 temp = I915_READ(reg);
2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
2484 }
2485 if (tries == 5)
2486 DRM_ERROR("FDI train 2 fail!\n");
2487
2488 DRM_DEBUG_KMS("FDI train done\n");
2489
2490}
2491
2492static const int snb_b_fdi_train_param[] = {
2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497};
2498
2499/* The FDI link training functions for SNB/Cougarpoint. */
2500static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501{
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
2506 u32 reg, temp, i, retry;
2507
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(150);
2518
2519 /* enable CPU FDI TX and PCH FDI RX */
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~(7 << 19);
2523 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2530
2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
2546 udelay(150);
2547
2548 for (i = 0; i < 4; i++) {
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
2556 udelay(500);
2557
2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
2568 }
2569 if (retry < 5)
2570 break;
2571 }
2572 if (i == 4)
2573 DRM_ERROR("FDI train 1 fail!\n");
2574
2575 /* Train 2 */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
2585 I915_WRITE(reg, temp);
2586
2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
2601 for (i = 0; i < 4; i++) {
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
2621 }
2622 if (retry < 5)
2623 break;
2624 }
2625 if (i == 4)
2626 DRM_ERROR("FDI train 2 fail!\n");
2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629}
2630
2631/* Manual link training for Ivy Bridge A0 parts */
2632static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~(7 << 19);
2658 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674 temp |= FDI_COMPOSITE_SYNC;
2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
2680 for (i = 0; i < 4; i++) {
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
2722 for (i = 0; i < 4; i++) {
2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746}
2747
2748static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2749{
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 int pipe = intel_crtc->pipe;
2753 u32 reg, temp;
2754
2755
2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~((0x7 << 19) | (0x7 << 16));
2760 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
2772 udelay(200);
2773
2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2779
2780 POSTING_READ(reg);
2781 udelay(100);
2782 }
2783}
2784
2785static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786{
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812}
2813
2814static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840 }
2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865}
2866
2867static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 unsigned long flags;
2872 bool pending;
2873
2874 if (atomic_read(&dev_priv->gpu_error.wedged))
2875 return false;
2876
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881 return pending;
2882}
2883
2884static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885{
2886 struct drm_device *dev = crtc->dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888
2889 if (crtc->fb == NULL)
2890 return;
2891
2892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2893
2894 wait_event(dev_priv->pending_flip_queue,
2895 !intel_crtc_has_pending_flip(crtc));
2896
2897 mutex_lock(&dev->struct_mutex);
2898 intel_finish_fb(crtc->fb);
2899 mutex_unlock(&dev->struct_mutex);
2900}
2901
2902static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2903{
2904 struct drm_device *dev = crtc->dev;
2905 struct intel_encoder *intel_encoder;
2906
2907 /*
2908 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2909 * must be driven by its own crtc; no sharing is possible.
2910 */
2911 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2912 switch (intel_encoder->type) {
2913 case INTEL_OUTPUT_EDP:
2914 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2915 return false;
2916 continue;
2917 }
2918 }
2919
2920 return true;
2921}
2922
2923static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2924{
2925 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2926}
2927
2928/* Program iCLKIP clock to the desired frequency */
2929static void lpt_program_iclkip(struct drm_crtc *crtc)
2930{
2931 struct drm_device *dev = crtc->dev;
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2933 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2934 u32 temp;
2935
2936 mutex_lock(&dev_priv->dpio_lock);
2937
2938 /* It is necessary to ungate the pixclk gate prior to programming
2939 * the divisors, and gate it back when it is done.
2940 */
2941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2942
2943 /* Disable SSCCTL */
2944 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2945 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2946 SBI_SSCCTL_DISABLE,
2947 SBI_ICLK);
2948
2949 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2950 if (crtc->mode.clock == 20000) {
2951 auxdiv = 1;
2952 divsel = 0x41;
2953 phaseinc = 0x20;
2954 } else {
2955 /* The iCLK virtual clock root frequency is in MHz,
2956 * but the crtc->mode.clock in in KHz. To get the divisors,
2957 * it is necessary to divide one by another, so we
2958 * convert the virtual clock precision to KHz here for higher
2959 * precision.
2960 */
2961 u32 iclk_virtual_root_freq = 172800 * 1000;
2962 u32 iclk_pi_range = 64;
2963 u32 desired_divisor, msb_divisor_value, pi_value;
2964
2965 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2966 msb_divisor_value = desired_divisor / iclk_pi_range;
2967 pi_value = desired_divisor % iclk_pi_range;
2968
2969 auxdiv = 0;
2970 divsel = msb_divisor_value - 2;
2971 phaseinc = pi_value;
2972 }
2973
2974 /* This should not happen with any sane values */
2975 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2976 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2977 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2978 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2979
2980 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2981 crtc->mode.clock,
2982 auxdiv,
2983 divsel,
2984 phasedir,
2985 phaseinc);
2986
2987 /* Program SSCDIVINTPHASE6 */
2988 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2989 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2990 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2991 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2992 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2993 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2994 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2995 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2996
2997 /* Program SSCAUXDIV */
2998 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2999 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3000 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3001 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3002
3003 /* Enable modulator and associated divider */
3004 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3005 temp &= ~SBI_SSCCTL_DISABLE;
3006 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3007
3008 /* Wait for initialization time */
3009 udelay(24);
3010
3011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3012
3013 mutex_unlock(&dev_priv->dpio_lock);
3014}
3015
3016/*
3017 * Enable PCH resources required for PCH ports:
3018 * - PCH PLLs
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3022 * - transcoder
3023 */
3024static void ironlake_pch_enable(struct drm_crtc *crtc)
3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
3030 u32 reg, temp;
3031
3032 assert_transcoder_disabled(dev_priv, pipe);
3033
3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
3039 /* For PCH output, training FDI link */
3040 dev_priv->display.fdi_link_train(crtc);
3041
3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3045 *
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
3049 ironlake_enable_pch_pll(intel_crtc);
3050
3051 if (HAS_PCH_CPT(dev)) {
3052 u32 sel;
3053
3054 temp = I915_READ(PCH_DPLL_SEL);
3055 switch (pipe) {
3056 default:
3057 case 0:
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3060 break;
3061 case 1:
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3064 break;
3065 case 2:
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3068 break;
3069 }
3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071 temp |= sel;
3072 else
3073 temp &= ~sel;
3074 I915_WRITE(PCH_DPLL_SEL, temp);
3075 }
3076
3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
3079 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3080 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3081 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3082
3083 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3084 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3085 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3086 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3087
3088 intel_fdi_normal_train(crtc);
3089
3090 /* For PCH DP, enable TRANS_DP_CTL */
3091 if (HAS_PCH_CPT(dev) &&
3092 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3093 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3094 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3095 reg = TRANS_DP_CTL(pipe);
3096 temp = I915_READ(reg);
3097 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3098 TRANS_DP_SYNC_MASK |
3099 TRANS_DP_BPC_MASK);
3100 temp |= (TRANS_DP_OUTPUT_ENABLE |
3101 TRANS_DP_ENH_FRAMING);
3102 temp |= bpc << 9; /* same format but at 11:9 */
3103
3104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3105 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3106 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3107 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3108
3109 switch (intel_trans_dp_port_sel(crtc)) {
3110 case PCH_DP_B:
3111 temp |= TRANS_DP_PORT_SEL_B;
3112 break;
3113 case PCH_DP_C:
3114 temp |= TRANS_DP_PORT_SEL_C;
3115 break;
3116 case PCH_DP_D:
3117 temp |= TRANS_DP_PORT_SEL_D;
3118 break;
3119 default:
3120 BUG();
3121 }
3122
3123 I915_WRITE(reg, temp);
3124 }
3125
3126 ironlake_enable_pch_transcoder(dev_priv, pipe);
3127}
3128
3129static void lpt_pch_enable(struct drm_crtc *crtc)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3134 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3135
3136 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3137
3138 lpt_program_iclkip(crtc);
3139
3140 /* Set transcoder timing. */
3141 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3142 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3143 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3144
3145 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3146 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3147 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3148 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3149
3150 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3151}
3152
3153static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3154{
3155 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3156
3157 if (pll == NULL)
3158 return;
3159
3160 if (pll->refcount == 0) {
3161 WARN(1, "bad PCH PLL refcount\n");
3162 return;
3163 }
3164
3165 --pll->refcount;
3166 intel_crtc->pch_pll = NULL;
3167}
3168
3169static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3170{
3171 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3172 struct intel_pch_pll *pll;
3173 int i;
3174
3175 pll = intel_crtc->pch_pll;
3176 if (pll) {
3177 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3178 intel_crtc->base.base.id, pll->pll_reg);
3179 goto prepare;
3180 }
3181
3182 if (HAS_PCH_IBX(dev_priv->dev)) {
3183 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3184 i = intel_crtc->pipe;
3185 pll = &dev_priv->pch_plls[i];
3186
3187 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3188 intel_crtc->base.base.id, pll->pll_reg);
3189
3190 goto found;
3191 }
3192
3193 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3194 pll = &dev_priv->pch_plls[i];
3195
3196 /* Only want to check enabled timings first */
3197 if (pll->refcount == 0)
3198 continue;
3199
3200 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3201 fp == I915_READ(pll->fp0_reg)) {
3202 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3203 intel_crtc->base.base.id,
3204 pll->pll_reg, pll->refcount, pll->active);
3205
3206 goto found;
3207 }
3208 }
3209
3210 /* Ok no matching timings, maybe there's a free one? */
3211 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3212 pll = &dev_priv->pch_plls[i];
3213 if (pll->refcount == 0) {
3214 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3215 intel_crtc->base.base.id, pll->pll_reg);
3216 goto found;
3217 }
3218 }
3219
3220 return NULL;
3221
3222found:
3223 intel_crtc->pch_pll = pll;
3224 pll->refcount++;
3225 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3226prepare: /* separate function? */
3227 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3228
3229 /* Wait for the clocks to stabilize before rewriting the regs */
3230 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3231 POSTING_READ(pll->pll_reg);
3232 udelay(150);
3233
3234 I915_WRITE(pll->fp0_reg, fp);
3235 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3236 pll->on = false;
3237 return pll;
3238}
3239
3240void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3241{
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 int dslreg = PIPEDSL(pipe);
3244 u32 temp;
3245
3246 temp = I915_READ(dslreg);
3247 udelay(500);
3248 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3249 if (wait_for(I915_READ(dslreg) != temp, 5))
3250 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3251 }
3252}
3253
3254static void ironlake_crtc_enable(struct drm_crtc *crtc)
3255{
3256 struct drm_device *dev = crtc->dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3259 struct intel_encoder *encoder;
3260 int pipe = intel_crtc->pipe;
3261 int plane = intel_crtc->plane;
3262 u32 temp;
3263 bool is_pch_port;
3264
3265 WARN_ON(!crtc->enabled);
3266
3267 if (intel_crtc->active)
3268 return;
3269
3270 intel_crtc->active = true;
3271 intel_update_watermarks(dev);
3272
3273 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3274 temp = I915_READ(PCH_LVDS);
3275 if ((temp & LVDS_PORT_EN) == 0)
3276 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3277 }
3278
3279 is_pch_port = ironlake_crtc_driving_pch(crtc);
3280
3281 if (is_pch_port) {
3282 /* Note: FDI PLL enabling _must_ be done before we enable the
3283 * cpu pipes, hence this is separate from all the other fdi/pch
3284 * enabling. */
3285 ironlake_fdi_pll_enable(intel_crtc);
3286 } else {
3287 assert_fdi_tx_disabled(dev_priv, pipe);
3288 assert_fdi_rx_disabled(dev_priv, pipe);
3289 }
3290
3291 for_each_encoder_on_crtc(dev, crtc, encoder)
3292 if (encoder->pre_enable)
3293 encoder->pre_enable(encoder);
3294
3295 /* Enable panel fitting for LVDS */
3296 if (dev_priv->pch_pf_size &&
3297 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3298 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3299 /* Force use of hard-coded filter coefficients
3300 * as some pre-programmed values are broken,
3301 * e.g. x201.
3302 */
3303 if (IS_IVYBRIDGE(dev))
3304 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3305 PF_PIPE_SEL_IVB(pipe));
3306 else
3307 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3308 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3309 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3310 }
3311
3312 /*
3313 * On ILK+ LUT must be loaded before the pipe is running but with
3314 * clocks enabled
3315 */
3316 intel_crtc_load_lut(crtc);
3317
3318 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3319 intel_enable_plane(dev_priv, plane, pipe);
3320
3321 if (is_pch_port)
3322 ironlake_pch_enable(crtc);
3323
3324 mutex_lock(&dev->struct_mutex);
3325 intel_update_fbc(dev);
3326 mutex_unlock(&dev->struct_mutex);
3327
3328 intel_crtc_update_cursor(crtc, true);
3329
3330 for_each_encoder_on_crtc(dev, crtc, encoder)
3331 encoder->enable(encoder);
3332
3333 if (HAS_PCH_CPT(dev))
3334 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3335
3336 /*
3337 * There seems to be a race in PCH platform hw (at least on some
3338 * outputs) where an enabled pipe still completes any pageflip right
3339 * away (as if the pipe is off) instead of waiting for vblank. As soon
3340 * as the first vblank happend, everything works as expected. Hence just
3341 * wait for one vblank before returning to avoid strange things
3342 * happening.
3343 */
3344 intel_wait_for_vblank(dev, intel_crtc->pipe);
3345}
3346
3347static void haswell_crtc_enable(struct drm_crtc *crtc)
3348{
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352 struct intel_encoder *encoder;
3353 int pipe = intel_crtc->pipe;
3354 int plane = intel_crtc->plane;
3355 bool is_pch_port;
3356
3357 WARN_ON(!crtc->enabled);
3358
3359 if (intel_crtc->active)
3360 return;
3361
3362 intel_crtc->active = true;
3363 intel_update_watermarks(dev);
3364
3365 is_pch_port = haswell_crtc_driving_pch(crtc);
3366
3367 if (is_pch_port)
3368 dev_priv->display.fdi_link_train(crtc);
3369
3370 for_each_encoder_on_crtc(dev, crtc, encoder)
3371 if (encoder->pre_enable)
3372 encoder->pre_enable(encoder);
3373
3374 intel_ddi_enable_pipe_clock(intel_crtc);
3375
3376 /* Enable panel fitting for eDP */
3377 if (dev_priv->pch_pf_size &&
3378 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3379 /* Force use of hard-coded filter coefficients
3380 * as some pre-programmed values are broken,
3381 * e.g. x201.
3382 */
3383 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3384 PF_PIPE_SEL_IVB(pipe));
3385 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3386 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3387 }
3388
3389 /*
3390 * On ILK+ LUT must be loaded before the pipe is running but with
3391 * clocks enabled
3392 */
3393 intel_crtc_load_lut(crtc);
3394
3395 intel_ddi_set_pipe_settings(crtc);
3396 intel_ddi_enable_pipe_func(crtc);
3397
3398 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3399 intel_enable_plane(dev_priv, plane, pipe);
3400
3401 if (is_pch_port)
3402 lpt_pch_enable(crtc);
3403
3404 mutex_lock(&dev->struct_mutex);
3405 intel_update_fbc(dev);
3406 mutex_unlock(&dev->struct_mutex);
3407
3408 intel_crtc_update_cursor(crtc, true);
3409
3410 for_each_encoder_on_crtc(dev, crtc, encoder)
3411 encoder->enable(encoder);
3412
3413 /*
3414 * There seems to be a race in PCH platform hw (at least on some
3415 * outputs) where an enabled pipe still completes any pageflip right
3416 * away (as if the pipe is off) instead of waiting for vblank. As soon
3417 * as the first vblank happend, everything works as expected. Hence just
3418 * wait for one vblank before returning to avoid strange things
3419 * happening.
3420 */
3421 intel_wait_for_vblank(dev, intel_crtc->pipe);
3422}
3423
3424static void ironlake_crtc_disable(struct drm_crtc *crtc)
3425{
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 struct intel_encoder *encoder;
3430 int pipe = intel_crtc->pipe;
3431 int plane = intel_crtc->plane;
3432 u32 reg, temp;
3433
3434
3435 if (!intel_crtc->active)
3436 return;
3437
3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 encoder->disable(encoder);
3440
3441 intel_crtc_wait_for_pending_flips(crtc);
3442 drm_vblank_off(dev, pipe);
3443 intel_crtc_update_cursor(crtc, false);
3444
3445 intel_disable_plane(dev_priv, plane, pipe);
3446
3447 if (dev_priv->cfb_plane == plane)
3448 intel_disable_fbc(dev);
3449
3450 intel_disable_pipe(dev_priv, pipe);
3451
3452 /* Disable PF */
3453 I915_WRITE(PF_CTL(pipe), 0);
3454 I915_WRITE(PF_WIN_SZ(pipe), 0);
3455
3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 if (encoder->post_disable)
3458 encoder->post_disable(encoder);
3459
3460 ironlake_fdi_disable(crtc);
3461
3462 ironlake_disable_pch_transcoder(dev_priv, pipe);
3463
3464 if (HAS_PCH_CPT(dev)) {
3465 /* disable TRANS_DP_CTL */
3466 reg = TRANS_DP_CTL(pipe);
3467 temp = I915_READ(reg);
3468 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3469 temp |= TRANS_DP_PORT_SEL_NONE;
3470 I915_WRITE(reg, temp);
3471
3472 /* disable DPLL_SEL */
3473 temp = I915_READ(PCH_DPLL_SEL);
3474 switch (pipe) {
3475 case 0:
3476 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3477 break;
3478 case 1:
3479 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3480 break;
3481 case 2:
3482 /* C shares PLL A or B */
3483 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3484 break;
3485 default:
3486 BUG(); /* wtf */
3487 }
3488 I915_WRITE(PCH_DPLL_SEL, temp);
3489 }
3490
3491 /* disable PCH DPLL */
3492 intel_disable_pch_pll(intel_crtc);
3493
3494 ironlake_fdi_pll_disable(intel_crtc);
3495
3496 intel_crtc->active = false;
3497 intel_update_watermarks(dev);
3498
3499 mutex_lock(&dev->struct_mutex);
3500 intel_update_fbc(dev);
3501 mutex_unlock(&dev->struct_mutex);
3502}
3503
3504static void haswell_crtc_disable(struct drm_crtc *crtc)
3505{
3506 struct drm_device *dev = crtc->dev;
3507 struct drm_i915_private *dev_priv = dev->dev_private;
3508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509 struct intel_encoder *encoder;
3510 int pipe = intel_crtc->pipe;
3511 int plane = intel_crtc->plane;
3512 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3513 bool is_pch_port;
3514
3515 if (!intel_crtc->active)
3516 return;
3517
3518 is_pch_port = haswell_crtc_driving_pch(crtc);
3519
3520 for_each_encoder_on_crtc(dev, crtc, encoder)
3521 encoder->disable(encoder);
3522
3523 intel_crtc_wait_for_pending_flips(crtc);
3524 drm_vblank_off(dev, pipe);
3525 intel_crtc_update_cursor(crtc, false);
3526
3527 intel_disable_plane(dev_priv, plane, pipe);
3528
3529 if (dev_priv->cfb_plane == plane)
3530 intel_disable_fbc(dev);
3531
3532 intel_disable_pipe(dev_priv, pipe);
3533
3534 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3535
3536 /* Disable PF */
3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_SZ(pipe), 0);
3539
3540 intel_ddi_disable_pipe_clock(intel_crtc);
3541
3542 for_each_encoder_on_crtc(dev, crtc, encoder)
3543 if (encoder->post_disable)
3544 encoder->post_disable(encoder);
3545
3546 if (is_pch_port) {
3547 lpt_disable_pch_transcoder(dev_priv);
3548 intel_ddi_fdi_disable(crtc);
3549 }
3550
3551 intel_crtc->active = false;
3552 intel_update_watermarks(dev);
3553
3554 mutex_lock(&dev->struct_mutex);
3555 intel_update_fbc(dev);
3556 mutex_unlock(&dev->struct_mutex);
3557}
3558
3559static void ironlake_crtc_off(struct drm_crtc *crtc)
3560{
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 intel_put_pch_pll(intel_crtc);
3563}
3564
3565static void haswell_crtc_off(struct drm_crtc *crtc)
3566{
3567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568
3569 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3570 * start using it. */
3571 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3572
3573 intel_ddi_put_crtc_pll(crtc);
3574}
3575
3576static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3577{
3578 if (!enable && intel_crtc->overlay) {
3579 struct drm_device *dev = intel_crtc->base.dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582 mutex_lock(&dev->struct_mutex);
3583 dev_priv->mm.interruptible = false;
3584 (void) intel_overlay_switch_off(intel_crtc->overlay);
3585 dev_priv->mm.interruptible = true;
3586 mutex_unlock(&dev->struct_mutex);
3587 }
3588
3589 /* Let userspace switch the overlay on again. In most cases userspace
3590 * has to recompute where to put it anyway.
3591 */
3592}
3593
3594static void i9xx_crtc_enable(struct drm_crtc *crtc)
3595{
3596 struct drm_device *dev = crtc->dev;
3597 struct drm_i915_private *dev_priv = dev->dev_private;
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3599 struct intel_encoder *encoder;
3600 int pipe = intel_crtc->pipe;
3601 int plane = intel_crtc->plane;
3602
3603 WARN_ON(!crtc->enabled);
3604
3605 if (intel_crtc->active)
3606 return;
3607
3608 intel_crtc->active = true;
3609 intel_update_watermarks(dev);
3610
3611 intel_enable_pll(dev_priv, pipe);
3612 intel_enable_pipe(dev_priv, pipe, false);
3613 intel_enable_plane(dev_priv, plane, pipe);
3614
3615 intel_crtc_load_lut(crtc);
3616 intel_update_fbc(dev);
3617
3618 /* Give the overlay scaler a chance to enable if it's on this pipe */
3619 intel_crtc_dpms_overlay(intel_crtc, true);
3620 intel_crtc_update_cursor(crtc, true);
3621
3622 for_each_encoder_on_crtc(dev, crtc, encoder)
3623 encoder->enable(encoder);
3624}
3625
3626static void i9xx_crtc_disable(struct drm_crtc *crtc)
3627{
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 struct intel_encoder *encoder;
3632 int pipe = intel_crtc->pipe;
3633 int plane = intel_crtc->plane;
3634
3635
3636 if (!intel_crtc->active)
3637 return;
3638
3639 for_each_encoder_on_crtc(dev, crtc, encoder)
3640 encoder->disable(encoder);
3641
3642 /* Give the overlay scaler a chance to disable if it's on this pipe */
3643 intel_crtc_wait_for_pending_flips(crtc);
3644 drm_vblank_off(dev, pipe);
3645 intel_crtc_dpms_overlay(intel_crtc, false);
3646 intel_crtc_update_cursor(crtc, false);
3647
3648 if (dev_priv->cfb_plane == plane)
3649 intel_disable_fbc(dev);
3650
3651 intel_disable_plane(dev_priv, plane, pipe);
3652 intel_disable_pipe(dev_priv, pipe);
3653 intel_disable_pll(dev_priv, pipe);
3654
3655 intel_crtc->active = false;
3656 intel_update_fbc(dev);
3657 intel_update_watermarks(dev);
3658}
3659
3660static void i9xx_crtc_off(struct drm_crtc *crtc)
3661{
3662}
3663
3664static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3665 bool enabled)
3666{
3667 struct drm_device *dev = crtc->dev;
3668 struct drm_i915_master_private *master_priv;
3669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670 int pipe = intel_crtc->pipe;
3671
3672 if (!dev->primary->master)
3673 return;
3674
3675 master_priv = dev->primary->master->driver_priv;
3676 if (!master_priv->sarea_priv)
3677 return;
3678
3679 switch (pipe) {
3680 case 0:
3681 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3682 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3683 break;
3684 case 1:
3685 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3686 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3687 break;
3688 default:
3689 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3690 break;
3691 }
3692}
3693
3694/**
3695 * Sets the power management mode of the pipe and plane.
3696 */
3697void intel_crtc_update_dpms(struct drm_crtc *crtc)
3698{
3699 struct drm_device *dev = crtc->dev;
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3701 struct intel_encoder *intel_encoder;
3702 bool enable = false;
3703
3704 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3705 enable |= intel_encoder->connectors_active;
3706
3707 if (enable)
3708 dev_priv->display.crtc_enable(crtc);
3709 else
3710 dev_priv->display.crtc_disable(crtc);
3711
3712 intel_crtc_update_sarea(crtc, enable);
3713}
3714
3715static void intel_crtc_noop(struct drm_crtc *crtc)
3716{
3717}
3718
3719static void intel_crtc_disable(struct drm_crtc *crtc)
3720{
3721 struct drm_device *dev = crtc->dev;
3722 struct drm_connector *connector;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724
3725 /* crtc should still be enabled when we disable it. */
3726 WARN_ON(!crtc->enabled);
3727
3728 dev_priv->display.crtc_disable(crtc);
3729 intel_crtc_update_sarea(crtc, false);
3730 dev_priv->display.off(crtc);
3731
3732 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3733 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3734
3735 if (crtc->fb) {
3736 mutex_lock(&dev->struct_mutex);
3737 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3738 mutex_unlock(&dev->struct_mutex);
3739 crtc->fb = NULL;
3740 }
3741
3742 /* Update computed state. */
3743 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3744 if (!connector->encoder || !connector->encoder->crtc)
3745 continue;
3746
3747 if (connector->encoder->crtc != crtc)
3748 continue;
3749
3750 connector->dpms = DRM_MODE_DPMS_OFF;
3751 to_intel_encoder(connector->encoder)->connectors_active = false;
3752 }
3753}
3754
3755void intel_modeset_disable(struct drm_device *dev)
3756{
3757 struct drm_crtc *crtc;
3758
3759 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3760 if (crtc->enabled)
3761 intel_crtc_disable(crtc);
3762 }
3763}
3764
3765void intel_encoder_noop(struct drm_encoder *encoder)
3766{
3767}
3768
3769void intel_encoder_destroy(struct drm_encoder *encoder)
3770{
3771 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3772
3773 drm_encoder_cleanup(encoder);
3774 kfree(intel_encoder);
3775}
3776
3777/* Simple dpms helper for encodres with just one connector, no cloning and only
3778 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3779 * state of the entire output pipe. */
3780void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3781{
3782 if (mode == DRM_MODE_DPMS_ON) {
3783 encoder->connectors_active = true;
3784
3785 intel_crtc_update_dpms(encoder->base.crtc);
3786 } else {
3787 encoder->connectors_active = false;
3788
3789 intel_crtc_update_dpms(encoder->base.crtc);
3790 }
3791}
3792
3793/* Cross check the actual hw state with our own modeset state tracking (and it's
3794 * internal consistency). */
3795static void intel_connector_check_state(struct intel_connector *connector)
3796{
3797 if (connector->get_hw_state(connector)) {
3798 struct intel_encoder *encoder = connector->encoder;
3799 struct drm_crtc *crtc;
3800 bool encoder_enabled;
3801 enum pipe pipe;
3802
3803 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3804 connector->base.base.id,
3805 drm_get_connector_name(&connector->base));
3806
3807 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3808 "wrong connector dpms state\n");
3809 WARN(connector->base.encoder != &encoder->base,
3810 "active connector not linked to encoder\n");
3811 WARN(!encoder->connectors_active,
3812 "encoder->connectors_active not set\n");
3813
3814 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3815 WARN(!encoder_enabled, "encoder not enabled\n");
3816 if (WARN_ON(!encoder->base.crtc))
3817 return;
3818
3819 crtc = encoder->base.crtc;
3820
3821 WARN(!crtc->enabled, "crtc not enabled\n");
3822 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3823 WARN(pipe != to_intel_crtc(crtc)->pipe,
3824 "encoder active on the wrong pipe\n");
3825 }
3826}
3827
3828/* Even simpler default implementation, if there's really no special case to
3829 * consider. */
3830void intel_connector_dpms(struct drm_connector *connector, int mode)
3831{
3832 struct intel_encoder *encoder = intel_attached_encoder(connector);
3833
3834 /* All the simple cases only support two dpms states. */
3835 if (mode != DRM_MODE_DPMS_ON)
3836 mode = DRM_MODE_DPMS_OFF;
3837
3838 if (mode == connector->dpms)
3839 return;
3840
3841 connector->dpms = mode;
3842
3843 /* Only need to change hw state when actually enabled */
3844 if (encoder->base.crtc)
3845 intel_encoder_dpms(encoder, mode);
3846 else
3847 WARN_ON(encoder->connectors_active != false);
3848
3849 intel_modeset_check_state(connector->dev);
3850}
3851
3852/* Simple connector->get_hw_state implementation for encoders that support only
3853 * one connector and no cloning and hence the encoder state determines the state
3854 * of the connector. */
3855bool intel_connector_get_hw_state(struct intel_connector *connector)
3856{
3857 enum pipe pipe = 0;
3858 struct intel_encoder *encoder = connector->encoder;
3859
3860 return encoder->get_hw_state(encoder, &pipe);
3861}
3862
3863static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3864 const struct drm_display_mode *mode,
3865 struct drm_display_mode *adjusted_mode)
3866{
3867 struct drm_device *dev = crtc->dev;
3868
3869 if (HAS_PCH_SPLIT(dev)) {
3870 /* FDI link clock is fixed at 2.7G */
3871 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3872 return false;
3873 }
3874
3875 /* All interlaced capable intel hw wants timings in frames. Note though
3876 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3877 * timings, so we need to be careful not to clobber these.*/
3878 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3879 drm_mode_set_crtcinfo(adjusted_mode, 0);
3880
3881 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3882 * with a hsync front porch of 0.
3883 */
3884 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3885 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3886 return false;
3887
3888 return true;
3889}
3890
3891static int valleyview_get_display_clock_speed(struct drm_device *dev)
3892{
3893 return 400000; /* FIXME */
3894}
3895
3896static int i945_get_display_clock_speed(struct drm_device *dev)
3897{
3898 return 400000;
3899}
3900
3901static int i915_get_display_clock_speed(struct drm_device *dev)
3902{
3903 return 333000;
3904}
3905
3906static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3907{
3908 return 200000;
3909}
3910
3911static int i915gm_get_display_clock_speed(struct drm_device *dev)
3912{
3913 u16 gcfgc = 0;
3914
3915 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3916
3917 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3918 return 133000;
3919 else {
3920 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3921 case GC_DISPLAY_CLOCK_333_MHZ:
3922 return 333000;
3923 default:
3924 case GC_DISPLAY_CLOCK_190_200_MHZ:
3925 return 190000;
3926 }
3927 }
3928}
3929
3930static int i865_get_display_clock_speed(struct drm_device *dev)
3931{
3932 return 266000;
3933}
3934
3935static int i855_get_display_clock_speed(struct drm_device *dev)
3936{
3937 u16 hpllcc = 0;
3938 /* Assume that the hardware is in the high speed state. This
3939 * should be the default.
3940 */
3941 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3942 case GC_CLOCK_133_200:
3943 case GC_CLOCK_100_200:
3944 return 200000;
3945 case GC_CLOCK_166_250:
3946 return 250000;
3947 case GC_CLOCK_100_133:
3948 return 133000;
3949 }
3950
3951 /* Shouldn't happen */
3952 return 0;
3953}
3954
3955static int i830_get_display_clock_speed(struct drm_device *dev)
3956{
3957 return 133000;
3958}
3959
3960static void
3961intel_reduce_ratio(uint32_t *num, uint32_t *den)
3962{
3963 while (*num > 0xffffff || *den > 0xffffff) {
3964 *num >>= 1;
3965 *den >>= 1;
3966 }
3967}
3968
3969void
3970intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3971 int pixel_clock, int link_clock,
3972 struct intel_link_m_n *m_n)
3973{
3974 m_n->tu = 64;
3975 m_n->gmch_m = bits_per_pixel * pixel_clock;
3976 m_n->gmch_n = link_clock * nlanes * 8;
3977 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3978 m_n->link_m = pixel_clock;
3979 m_n->link_n = link_clock;
3980 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
3981}
3982
3983static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3984{
3985 if (i915_panel_use_ssc >= 0)
3986 return i915_panel_use_ssc != 0;
3987 return dev_priv->lvds_use_ssc
3988 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3989}
3990
3991/**
3992 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3993 * @crtc: CRTC structure
3994 * @mode: requested mode
3995 *
3996 * A pipe may be connected to one or more outputs. Based on the depth of the
3997 * attached framebuffer, choose a good color depth to use on the pipe.
3998 *
3999 * If possible, match the pipe depth to the fb depth. In some cases, this
4000 * isn't ideal, because the connected output supports a lesser or restricted
4001 * set of depths. Resolve that here:
4002 * LVDS typically supports only 6bpc, so clamp down in that case
4003 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4004 * Displays may support a restricted set as well, check EDID and clamp as
4005 * appropriate.
4006 * DP may want to dither down to 6bpc to fit larger modes
4007 *
4008 * RETURNS:
4009 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4010 * true if they don't match).
4011 */
4012static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4013 struct drm_framebuffer *fb,
4014 unsigned int *pipe_bpp,
4015 struct drm_display_mode *mode)
4016{
4017 struct drm_device *dev = crtc->dev;
4018 struct drm_i915_private *dev_priv = dev->dev_private;
4019 struct drm_connector *connector;
4020 struct intel_encoder *intel_encoder;
4021 unsigned int display_bpc = UINT_MAX, bpc;
4022
4023 /* Walk the encoders & connectors on this crtc, get min bpc */
4024 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4025
4026 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4027 unsigned int lvds_bpc;
4028
4029 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4030 LVDS_A3_POWER_UP)
4031 lvds_bpc = 8;
4032 else
4033 lvds_bpc = 6;
4034
4035 if (lvds_bpc < display_bpc) {
4036 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4037 display_bpc = lvds_bpc;
4038 }
4039 continue;
4040 }
4041
4042 /* Not one of the known troublemakers, check the EDID */
4043 list_for_each_entry(connector, &dev->mode_config.connector_list,
4044 head) {
4045 if (connector->encoder != &intel_encoder->base)
4046 continue;
4047
4048 /* Don't use an invalid EDID bpc value */
4049 if (connector->display_info.bpc &&
4050 connector->display_info.bpc < display_bpc) {
4051 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4052 display_bpc = connector->display_info.bpc;
4053 }
4054 }
4055
4056 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4057 /* Use VBT settings if we have an eDP panel */
4058 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4059
4060 if (edp_bpc && edp_bpc < display_bpc) {
4061 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4062 display_bpc = edp_bpc;
4063 }
4064 continue;
4065 }
4066
4067 /*
4068 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4069 * through, clamp it down. (Note: >12bpc will be caught below.)
4070 */
4071 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4072 if (display_bpc > 8 && display_bpc < 12) {
4073 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4074 display_bpc = 12;
4075 } else {
4076 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4077 display_bpc = 8;
4078 }
4079 }
4080 }
4081
4082 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4083 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4084 display_bpc = 6;
4085 }
4086
4087 /*
4088 * We could just drive the pipe at the highest bpc all the time and
4089 * enable dithering as needed, but that costs bandwidth. So choose
4090 * the minimum value that expresses the full color range of the fb but
4091 * also stays within the max display bpc discovered above.
4092 */
4093
4094 switch (fb->depth) {
4095 case 8:
4096 bpc = 8; /* since we go through a colormap */
4097 break;
4098 case 15:
4099 case 16:
4100 bpc = 6; /* min is 18bpp */
4101 break;
4102 case 24:
4103 bpc = 8;
4104 break;
4105 case 30:
4106 bpc = 10;
4107 break;
4108 case 48:
4109 bpc = 12;
4110 break;
4111 default:
4112 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4113 bpc = min((unsigned int)8, display_bpc);
4114 break;
4115 }
4116
4117 display_bpc = min(display_bpc, bpc);
4118
4119 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4120 bpc, display_bpc);
4121
4122 *pipe_bpp = display_bpc * 3;
4123
4124 return display_bpc != bpc;
4125}
4126
4127static int vlv_get_refclk(struct drm_crtc *crtc)
4128{
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 int refclk = 27000; /* for DP & HDMI */
4132
4133 return 100000; /* only one validated so far */
4134
4135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4136 refclk = 96000;
4137 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4138 if (intel_panel_use_ssc(dev_priv))
4139 refclk = 100000;
4140 else
4141 refclk = 96000;
4142 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4143 refclk = 100000;
4144 }
4145
4146 return refclk;
4147}
4148
4149static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4150{
4151 struct drm_device *dev = crtc->dev;
4152 struct drm_i915_private *dev_priv = dev->dev_private;
4153 int refclk;
4154
4155 if (IS_VALLEYVIEW(dev)) {
4156 refclk = vlv_get_refclk(crtc);
4157 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4158 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4159 refclk = dev_priv->lvds_ssc_freq * 1000;
4160 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4161 refclk / 1000);
4162 } else if (!IS_GEN2(dev)) {
4163 refclk = 96000;
4164 } else {
4165 refclk = 48000;
4166 }
4167
4168 return refclk;
4169}
4170
4171static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4172 intel_clock_t *clock)
4173{
4174 /* SDVO TV has fixed PLL values depend on its clock range,
4175 this mirrors vbios setting. */
4176 if (adjusted_mode->clock >= 100000
4177 && adjusted_mode->clock < 140500) {
4178 clock->p1 = 2;
4179 clock->p2 = 10;
4180 clock->n = 3;
4181 clock->m1 = 16;
4182 clock->m2 = 8;
4183 } else if (adjusted_mode->clock >= 140500
4184 && adjusted_mode->clock <= 200000) {
4185 clock->p1 = 1;
4186 clock->p2 = 10;
4187 clock->n = 6;
4188 clock->m1 = 12;
4189 clock->m2 = 8;
4190 }
4191}
4192
4193static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4194 intel_clock_t *clock,
4195 intel_clock_t *reduced_clock)
4196{
4197 struct drm_device *dev = crtc->dev;
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4200 int pipe = intel_crtc->pipe;
4201 u32 fp, fp2 = 0;
4202
4203 if (IS_PINEVIEW(dev)) {
4204 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4205 if (reduced_clock)
4206 fp2 = (1 << reduced_clock->n) << 16 |
4207 reduced_clock->m1 << 8 | reduced_clock->m2;
4208 } else {
4209 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4210 if (reduced_clock)
4211 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4212 reduced_clock->m2;
4213 }
4214
4215 I915_WRITE(FP0(pipe), fp);
4216
4217 intel_crtc->lowfreq_avail = false;
4218 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4219 reduced_clock && i915_powersave) {
4220 I915_WRITE(FP1(pipe), fp2);
4221 intel_crtc->lowfreq_avail = true;
4222 } else {
4223 I915_WRITE(FP1(pipe), fp);
4224 }
4225}
4226
4227static void vlv_update_pll(struct drm_crtc *crtc,
4228 struct drm_display_mode *mode,
4229 struct drm_display_mode *adjusted_mode,
4230 intel_clock_t *clock, intel_clock_t *reduced_clock,
4231 int num_connectors)
4232{
4233 struct drm_device *dev = crtc->dev;
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236 int pipe = intel_crtc->pipe;
4237 u32 dpll, mdiv, pdiv;
4238 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4239 bool is_sdvo;
4240 u32 temp;
4241
4242 mutex_lock(&dev_priv->dpio_lock);
4243
4244 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4245 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4246
4247 dpll = DPLL_VGA_MODE_DIS;
4248 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4249 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4250 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4251
4252 I915_WRITE(DPLL(pipe), dpll);
4253 POSTING_READ(DPLL(pipe));
4254
4255 bestn = clock->n;
4256 bestm1 = clock->m1;
4257 bestm2 = clock->m2;
4258 bestp1 = clock->p1;
4259 bestp2 = clock->p2;
4260
4261 /*
4262 * In Valleyview PLL and program lane counter registers are exposed
4263 * through DPIO interface
4264 */
4265 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4266 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4267 mdiv |= ((bestn << DPIO_N_SHIFT));
4268 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4269 mdiv |= (1 << DPIO_K_SHIFT);
4270 mdiv |= DPIO_ENABLE_CALIBRATION;
4271 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4272
4273 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4274
4275 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4276 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4277 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4278 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4279 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4280
4281 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4282
4283 dpll |= DPLL_VCO_ENABLE;
4284 I915_WRITE(DPLL(pipe), dpll);
4285 POSTING_READ(DPLL(pipe));
4286 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4287 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4288
4289 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4290
4291 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4292 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4293
4294 I915_WRITE(DPLL(pipe), dpll);
4295
4296 /* Wait for the clocks to stabilize. */
4297 POSTING_READ(DPLL(pipe));
4298 udelay(150);
4299
4300 temp = 0;
4301 if (is_sdvo) {
4302 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4303 if (temp > 1)
4304 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4305 else
4306 temp = 0;
4307 }
4308 I915_WRITE(DPLL_MD(pipe), temp);
4309 POSTING_READ(DPLL_MD(pipe));
4310
4311 /* Now program lane control registers */
4312 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4313 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4314 {
4315 temp = 0x1000C4;
4316 if(pipe == 1)
4317 temp |= (1 << 21);
4318 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4319 }
4320 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4321 {
4322 temp = 0x1000C4;
4323 if(pipe == 1)
4324 temp |= (1 << 21);
4325 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4326 }
4327
4328 mutex_unlock(&dev_priv->dpio_lock);
4329}
4330
4331static void i9xx_update_pll(struct drm_crtc *crtc,
4332 struct drm_display_mode *mode,
4333 struct drm_display_mode *adjusted_mode,
4334 intel_clock_t *clock, intel_clock_t *reduced_clock,
4335 int num_connectors)
4336{
4337 struct drm_device *dev = crtc->dev;
4338 struct drm_i915_private *dev_priv = dev->dev_private;
4339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4340 struct intel_encoder *encoder;
4341 int pipe = intel_crtc->pipe;
4342 u32 dpll;
4343 bool is_sdvo;
4344
4345 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4346
4347 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4348 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4349
4350 dpll = DPLL_VGA_MODE_DIS;
4351
4352 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4353 dpll |= DPLLB_MODE_LVDS;
4354 else
4355 dpll |= DPLLB_MODE_DAC_SERIAL;
4356 if (is_sdvo) {
4357 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4358 if (pixel_multiplier > 1) {
4359 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4360 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4361 }
4362 dpll |= DPLL_DVO_HIGH_SPEED;
4363 }
4364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4365 dpll |= DPLL_DVO_HIGH_SPEED;
4366
4367 /* compute bitmask from p1 value */
4368 if (IS_PINEVIEW(dev))
4369 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4370 else {
4371 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4372 if (IS_G4X(dev) && reduced_clock)
4373 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4374 }
4375 switch (clock->p2) {
4376 case 5:
4377 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4378 break;
4379 case 7:
4380 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4381 break;
4382 case 10:
4383 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4384 break;
4385 case 14:
4386 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4387 break;
4388 }
4389 if (INTEL_INFO(dev)->gen >= 4)
4390 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4391
4392 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4393 dpll |= PLL_REF_INPUT_TVCLKINBC;
4394 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4395 /* XXX: just matching BIOS for now */
4396 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4397 dpll |= 3;
4398 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4399 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4400 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4401 else
4402 dpll |= PLL_REF_INPUT_DREFCLK;
4403
4404 dpll |= DPLL_VCO_ENABLE;
4405 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4406 POSTING_READ(DPLL(pipe));
4407 udelay(150);
4408
4409 for_each_encoder_on_crtc(dev, crtc, encoder)
4410 if (encoder->pre_pll_enable)
4411 encoder->pre_pll_enable(encoder);
4412
4413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4414 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4415
4416 I915_WRITE(DPLL(pipe), dpll);
4417
4418 /* Wait for the clocks to stabilize. */
4419 POSTING_READ(DPLL(pipe));
4420 udelay(150);
4421
4422 if (INTEL_INFO(dev)->gen >= 4) {
4423 u32 temp = 0;
4424 if (is_sdvo) {
4425 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4426 if (temp > 1)
4427 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4428 else
4429 temp = 0;
4430 }
4431 I915_WRITE(DPLL_MD(pipe), temp);
4432 } else {
4433 /* The pixel multiplier can only be updated once the
4434 * DPLL is enabled and the clocks are stable.
4435 *
4436 * So write it again.
4437 */
4438 I915_WRITE(DPLL(pipe), dpll);
4439 }
4440}
4441
4442static void i8xx_update_pll(struct drm_crtc *crtc,
4443 struct drm_display_mode *adjusted_mode,
4444 intel_clock_t *clock, intel_clock_t *reduced_clock,
4445 int num_connectors)
4446{
4447 struct drm_device *dev = crtc->dev;
4448 struct drm_i915_private *dev_priv = dev->dev_private;
4449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4450 struct intel_encoder *encoder;
4451 int pipe = intel_crtc->pipe;
4452 u32 dpll;
4453
4454 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4455
4456 dpll = DPLL_VGA_MODE_DIS;
4457
4458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4459 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4460 } else {
4461 if (clock->p1 == 2)
4462 dpll |= PLL_P1_DIVIDE_BY_TWO;
4463 else
4464 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4465 if (clock->p2 == 4)
4466 dpll |= PLL_P2_DIVIDE_BY_4;
4467 }
4468
4469 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4470 /* XXX: just matching BIOS for now */
4471 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4472 dpll |= 3;
4473 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4474 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4475 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4476 else
4477 dpll |= PLL_REF_INPUT_DREFCLK;
4478
4479 dpll |= DPLL_VCO_ENABLE;
4480 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4481 POSTING_READ(DPLL(pipe));
4482 udelay(150);
4483
4484 for_each_encoder_on_crtc(dev, crtc, encoder)
4485 if (encoder->pre_pll_enable)
4486 encoder->pre_pll_enable(encoder);
4487
4488 I915_WRITE(DPLL(pipe), dpll);
4489
4490 /* Wait for the clocks to stabilize. */
4491 POSTING_READ(DPLL(pipe));
4492 udelay(150);
4493
4494 /* The pixel multiplier can only be updated once the
4495 * DPLL is enabled and the clocks are stable.
4496 *
4497 * So write it again.
4498 */
4499 I915_WRITE(DPLL(pipe), dpll);
4500}
4501
4502static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4503 struct drm_display_mode *mode,
4504 struct drm_display_mode *adjusted_mode)
4505{
4506 struct drm_device *dev = intel_crtc->base.dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 enum pipe pipe = intel_crtc->pipe;
4509 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4510 uint32_t vsyncshift;
4511
4512 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4513 /* the chip adds 2 halflines automatically */
4514 adjusted_mode->crtc_vtotal -= 1;
4515 adjusted_mode->crtc_vblank_end -= 1;
4516 vsyncshift = adjusted_mode->crtc_hsync_start
4517 - adjusted_mode->crtc_htotal / 2;
4518 } else {
4519 vsyncshift = 0;
4520 }
4521
4522 if (INTEL_INFO(dev)->gen > 3)
4523 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4524
4525 I915_WRITE(HTOTAL(cpu_transcoder),
4526 (adjusted_mode->crtc_hdisplay - 1) |
4527 ((adjusted_mode->crtc_htotal - 1) << 16));
4528 I915_WRITE(HBLANK(cpu_transcoder),
4529 (adjusted_mode->crtc_hblank_start - 1) |
4530 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4531 I915_WRITE(HSYNC(cpu_transcoder),
4532 (adjusted_mode->crtc_hsync_start - 1) |
4533 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4534
4535 I915_WRITE(VTOTAL(cpu_transcoder),
4536 (adjusted_mode->crtc_vdisplay - 1) |
4537 ((adjusted_mode->crtc_vtotal - 1) << 16));
4538 I915_WRITE(VBLANK(cpu_transcoder),
4539 (adjusted_mode->crtc_vblank_start - 1) |
4540 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4541 I915_WRITE(VSYNC(cpu_transcoder),
4542 (adjusted_mode->crtc_vsync_start - 1) |
4543 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4544
4545 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4546 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4547 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4548 * bits. */
4549 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4550 (pipe == PIPE_B || pipe == PIPE_C))
4551 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4552
4553 /* pipesrc controls the size that is scaled from, which should
4554 * always be the user's requested size.
4555 */
4556 I915_WRITE(PIPESRC(pipe),
4557 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4558}
4559
4560static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4561 struct drm_display_mode *mode,
4562 struct drm_display_mode *adjusted_mode,
4563 int x, int y,
4564 struct drm_framebuffer *fb)
4565{
4566 struct drm_device *dev = crtc->dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4569 int pipe = intel_crtc->pipe;
4570 int plane = intel_crtc->plane;
4571 int refclk, num_connectors = 0;
4572 intel_clock_t clock, reduced_clock;
4573 u32 dspcntr, pipeconf;
4574 bool ok, has_reduced_clock = false, is_sdvo = false;
4575 bool is_lvds = false, is_tv = false, is_dp = false;
4576 struct intel_encoder *encoder;
4577 const intel_limit_t *limit;
4578 int ret;
4579
4580 for_each_encoder_on_crtc(dev, crtc, encoder) {
4581 switch (encoder->type) {
4582 case INTEL_OUTPUT_LVDS:
4583 is_lvds = true;
4584 break;
4585 case INTEL_OUTPUT_SDVO:
4586 case INTEL_OUTPUT_HDMI:
4587 is_sdvo = true;
4588 if (encoder->needs_tv_clock)
4589 is_tv = true;
4590 break;
4591 case INTEL_OUTPUT_TVOUT:
4592 is_tv = true;
4593 break;
4594 case INTEL_OUTPUT_DISPLAYPORT:
4595 is_dp = true;
4596 break;
4597 }
4598
4599 num_connectors++;
4600 }
4601
4602 refclk = i9xx_get_refclk(crtc, num_connectors);
4603
4604 /*
4605 * Returns a set of divisors for the desired target clock with the given
4606 * refclk, or FALSE. The returned values represent the clock equation:
4607 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4608 */
4609 limit = intel_limit(crtc, refclk);
4610 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4611 &clock);
4612 if (!ok) {
4613 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4614 return -EINVAL;
4615 }
4616
4617 /* Ensure that the cursor is valid for the new mode before changing... */
4618 intel_crtc_update_cursor(crtc, true);
4619
4620 if (is_lvds && dev_priv->lvds_downclock_avail) {
4621 /*
4622 * Ensure we match the reduced clock's P to the target clock.
4623 * If the clocks don't match, we can't switch the display clock
4624 * by using the FP0/FP1. In such case we will disable the LVDS
4625 * downclock feature.
4626 */
4627 has_reduced_clock = limit->find_pll(limit, crtc,
4628 dev_priv->lvds_downclock,
4629 refclk,
4630 &clock,
4631 &reduced_clock);
4632 }
4633
4634 if (is_sdvo && is_tv)
4635 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4636
4637 if (IS_GEN2(dev))
4638 i8xx_update_pll(crtc, adjusted_mode, &clock,
4639 has_reduced_clock ? &reduced_clock : NULL,
4640 num_connectors);
4641 else if (IS_VALLEYVIEW(dev))
4642 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4643 has_reduced_clock ? &reduced_clock : NULL,
4644 num_connectors);
4645 else
4646 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4647 has_reduced_clock ? &reduced_clock : NULL,
4648 num_connectors);
4649
4650 /* setup pipeconf */
4651 pipeconf = I915_READ(PIPECONF(pipe));
4652
4653 /* Set up the display plane register */
4654 dspcntr = DISPPLANE_GAMMA_ENABLE;
4655
4656 if (pipe == 0)
4657 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4658 else
4659 dspcntr |= DISPPLANE_SEL_PIPE_B;
4660
4661 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4662 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4663 * core speed.
4664 *
4665 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4666 * pipe == 0 check?
4667 */
4668 if (mode->clock >
4669 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4670 pipeconf |= PIPECONF_DOUBLE_WIDE;
4671 else
4672 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4673 }
4674
4675 /* default to 8bpc */
4676 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4677 if (is_dp) {
4678 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4679 pipeconf |= PIPECONF_6BPC |
4680 PIPECONF_DITHER_EN |
4681 PIPECONF_DITHER_TYPE_SP;
4682 }
4683 }
4684
4685 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4686 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4687 pipeconf |= PIPECONF_6BPC |
4688 PIPECONF_ENABLE |
4689 I965_PIPECONF_ACTIVE;
4690 }
4691 }
4692
4693 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4694 drm_mode_debug_printmodeline(mode);
4695
4696 if (HAS_PIPE_CXSR(dev)) {
4697 if (intel_crtc->lowfreq_avail) {
4698 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4699 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4700 } else {
4701 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4702 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4703 }
4704 }
4705
4706 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4707 if (!IS_GEN2(dev) &&
4708 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4709 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4710 else
4711 pipeconf |= PIPECONF_PROGRESSIVE;
4712
4713 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4714
4715 /* pipesrc and dspsize control the size that is scaled from,
4716 * which should always be the user's requested size.
4717 */
4718 I915_WRITE(DSPSIZE(plane),
4719 ((mode->vdisplay - 1) << 16) |
4720 (mode->hdisplay - 1));
4721 I915_WRITE(DSPPOS(plane), 0);
4722
4723 I915_WRITE(PIPECONF(pipe), pipeconf);
4724 POSTING_READ(PIPECONF(pipe));
4725 intel_enable_pipe(dev_priv, pipe, false);
4726
4727 intel_wait_for_vblank(dev, pipe);
4728
4729 I915_WRITE(DSPCNTR(plane), dspcntr);
4730 POSTING_READ(DSPCNTR(plane));
4731
4732 ret = intel_pipe_set_base(crtc, x, y, fb);
4733
4734 intel_update_watermarks(dev);
4735
4736 return ret;
4737}
4738
4739static void ironlake_init_pch_refclk(struct drm_device *dev)
4740{
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742 struct drm_mode_config *mode_config = &dev->mode_config;
4743 struct intel_encoder *encoder;
4744 u32 temp;
4745 bool has_lvds = false;
4746 bool has_cpu_edp = false;
4747 bool has_pch_edp = false;
4748 bool has_panel = false;
4749 bool has_ck505 = false;
4750 bool can_ssc = false;
4751
4752 /* We need to take the global config into account */
4753 list_for_each_entry(encoder, &mode_config->encoder_list,
4754 base.head) {
4755 switch (encoder->type) {
4756 case INTEL_OUTPUT_LVDS:
4757 has_panel = true;
4758 has_lvds = true;
4759 break;
4760 case INTEL_OUTPUT_EDP:
4761 has_panel = true;
4762 if (intel_encoder_is_pch_edp(&encoder->base))
4763 has_pch_edp = true;
4764 else
4765 has_cpu_edp = true;
4766 break;
4767 }
4768 }
4769
4770 if (HAS_PCH_IBX(dev)) {
4771 has_ck505 = dev_priv->display_clock_mode;
4772 can_ssc = has_ck505;
4773 } else {
4774 has_ck505 = false;
4775 can_ssc = true;
4776 }
4777
4778 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4779 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4780 has_ck505);
4781
4782 /* Ironlake: try to setup display ref clock before DPLL
4783 * enabling. This is only under driver's control after
4784 * PCH B stepping, previous chipset stepping should be
4785 * ignoring this setting.
4786 */
4787 temp = I915_READ(PCH_DREF_CONTROL);
4788 /* Always enable nonspread source */
4789 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4790
4791 if (has_ck505)
4792 temp |= DREF_NONSPREAD_CK505_ENABLE;
4793 else
4794 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4795
4796 if (has_panel) {
4797 temp &= ~DREF_SSC_SOURCE_MASK;
4798 temp |= DREF_SSC_SOURCE_ENABLE;
4799
4800 /* SSC must be turned on before enabling the CPU output */
4801 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4802 DRM_DEBUG_KMS("Using SSC on panel\n");
4803 temp |= DREF_SSC1_ENABLE;
4804 } else
4805 temp &= ~DREF_SSC1_ENABLE;
4806
4807 /* Get SSC going before enabling the outputs */
4808 I915_WRITE(PCH_DREF_CONTROL, temp);
4809 POSTING_READ(PCH_DREF_CONTROL);
4810 udelay(200);
4811
4812 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4813
4814 /* Enable CPU source on CPU attached eDP */
4815 if (has_cpu_edp) {
4816 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4817 DRM_DEBUG_KMS("Using SSC on eDP\n");
4818 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4819 }
4820 else
4821 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4822 } else
4823 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4824
4825 I915_WRITE(PCH_DREF_CONTROL, temp);
4826 POSTING_READ(PCH_DREF_CONTROL);
4827 udelay(200);
4828 } else {
4829 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4830
4831 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4832
4833 /* Turn off CPU output */
4834 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4835
4836 I915_WRITE(PCH_DREF_CONTROL, temp);
4837 POSTING_READ(PCH_DREF_CONTROL);
4838 udelay(200);
4839
4840 /* Turn off the SSC source */
4841 temp &= ~DREF_SSC_SOURCE_MASK;
4842 temp |= DREF_SSC_SOURCE_DISABLE;
4843
4844 /* Turn off SSC1 */
4845 temp &= ~ DREF_SSC1_ENABLE;
4846
4847 I915_WRITE(PCH_DREF_CONTROL, temp);
4848 POSTING_READ(PCH_DREF_CONTROL);
4849 udelay(200);
4850 }
4851}
4852
4853/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4854static void lpt_init_pch_refclk(struct drm_device *dev)
4855{
4856 struct drm_i915_private *dev_priv = dev->dev_private;
4857 struct drm_mode_config *mode_config = &dev->mode_config;
4858 struct intel_encoder *encoder;
4859 bool has_vga = false;
4860 bool is_sdv = false;
4861 u32 tmp;
4862
4863 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4864 switch (encoder->type) {
4865 case INTEL_OUTPUT_ANALOG:
4866 has_vga = true;
4867 break;
4868 }
4869 }
4870
4871 if (!has_vga)
4872 return;
4873
4874 /* XXX: Rip out SDV support once Haswell ships for real. */
4875 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4876 is_sdv = true;
4877
4878 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4879 tmp &= ~SBI_SSCCTL_DISABLE;
4880 tmp |= SBI_SSCCTL_PATHALT;
4881 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4882
4883 udelay(24);
4884
4885 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4886 tmp &= ~SBI_SSCCTL_PATHALT;
4887 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4888
4889 if (!is_sdv) {
4890 tmp = I915_READ(SOUTH_CHICKEN2);
4891 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4892 I915_WRITE(SOUTH_CHICKEN2, tmp);
4893
4894 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4895 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4896 DRM_ERROR("FDI mPHY reset assert timeout\n");
4897
4898 tmp = I915_READ(SOUTH_CHICKEN2);
4899 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4900 I915_WRITE(SOUTH_CHICKEN2, tmp);
4901
4902 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4903 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4904 100))
4905 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4906 }
4907
4908 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4909 tmp &= ~(0xFF << 24);
4910 tmp |= (0x12 << 24);
4911 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4912
4913 if (!is_sdv) {
4914 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4915 tmp &= ~(0x3 << 6);
4916 tmp |= (1 << 6) | (1 << 0);
4917 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4918 }
4919
4920 if (is_sdv) {
4921 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4922 tmp |= 0x7FFF;
4923 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4924 }
4925
4926 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4927 tmp |= (1 << 11);
4928 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4929
4930 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4931 tmp |= (1 << 11);
4932 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4933
4934 if (is_sdv) {
4935 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4936 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4937 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4938
4939 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4940 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4941 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4942
4943 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4944 tmp |= (0x3F << 8);
4945 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4946
4947 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4948 tmp |= (0x3F << 8);
4949 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4950 }
4951
4952 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4953 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4954 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4955
4956 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4957 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4958 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4959
4960 if (!is_sdv) {
4961 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4962 tmp &= ~(7 << 13);
4963 tmp |= (5 << 13);
4964 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4965
4966 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4967 tmp &= ~(7 << 13);
4968 tmp |= (5 << 13);
4969 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4970 }
4971
4972 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4973 tmp &= ~0xFF;
4974 tmp |= 0x1C;
4975 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4976
4977 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4978 tmp &= ~0xFF;
4979 tmp |= 0x1C;
4980 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4981
4982 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4983 tmp &= ~(0xFF << 16);
4984 tmp |= (0x1C << 16);
4985 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4986
4987 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4988 tmp &= ~(0xFF << 16);
4989 tmp |= (0x1C << 16);
4990 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4991
4992 if (!is_sdv) {
4993 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4994 tmp |= (1 << 27);
4995 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4996
4997 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4998 tmp |= (1 << 27);
4999 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5000
5001 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5002 tmp &= ~(0xF << 28);
5003 tmp |= (4 << 28);
5004 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5005
5006 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5007 tmp &= ~(0xF << 28);
5008 tmp |= (4 << 28);
5009 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5010 }
5011
5012 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5013 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5014 tmp |= SBI_DBUFF0_ENABLE;
5015 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5016}
5017
5018/*
5019 * Initialize reference clocks when the driver loads
5020 */
5021void intel_init_pch_refclk(struct drm_device *dev)
5022{
5023 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5024 ironlake_init_pch_refclk(dev);
5025 else if (HAS_PCH_LPT(dev))
5026 lpt_init_pch_refclk(dev);
5027}
5028
5029static int ironlake_get_refclk(struct drm_crtc *crtc)
5030{
5031 struct drm_device *dev = crtc->dev;
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 struct intel_encoder *encoder;
5034 struct intel_encoder *edp_encoder = NULL;
5035 int num_connectors = 0;
5036 bool is_lvds = false;
5037
5038 for_each_encoder_on_crtc(dev, crtc, encoder) {
5039 switch (encoder->type) {
5040 case INTEL_OUTPUT_LVDS:
5041 is_lvds = true;
5042 break;
5043 case INTEL_OUTPUT_EDP:
5044 edp_encoder = encoder;
5045 break;
5046 }
5047 num_connectors++;
5048 }
5049
5050 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5051 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5052 dev_priv->lvds_ssc_freq);
5053 return dev_priv->lvds_ssc_freq * 1000;
5054 }
5055
5056 return 120000;
5057}
5058
5059static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5060 struct drm_display_mode *adjusted_mode,
5061 bool dither)
5062{
5063 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065 int pipe = intel_crtc->pipe;
5066 uint32_t val;
5067
5068 val = I915_READ(PIPECONF(pipe));
5069
5070 val &= ~PIPECONF_BPC_MASK;
5071 switch (intel_crtc->bpp) {
5072 case 18:
5073 val |= PIPECONF_6BPC;
5074 break;
5075 case 24:
5076 val |= PIPECONF_8BPC;
5077 break;
5078 case 30:
5079 val |= PIPECONF_10BPC;
5080 break;
5081 case 36:
5082 val |= PIPECONF_12BPC;
5083 break;
5084 default:
5085 /* Case prevented by intel_choose_pipe_bpp_dither. */
5086 BUG();
5087 }
5088
5089 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5090 if (dither)
5091 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5092
5093 val &= ~PIPECONF_INTERLACE_MASK;
5094 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5095 val |= PIPECONF_INTERLACED_ILK;
5096 else
5097 val |= PIPECONF_PROGRESSIVE;
5098
5099 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5100 val |= PIPECONF_COLOR_RANGE_SELECT;
5101 else
5102 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5103
5104 I915_WRITE(PIPECONF(pipe), val);
5105 POSTING_READ(PIPECONF(pipe));
5106}
5107
5108static void haswell_set_pipeconf(struct drm_crtc *crtc,
5109 struct drm_display_mode *adjusted_mode,
5110 bool dither)
5111{
5112 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5114 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5115 uint32_t val;
5116
5117 val = I915_READ(PIPECONF(cpu_transcoder));
5118
5119 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5120 if (dither)
5121 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5122
5123 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5124 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5125 val |= PIPECONF_INTERLACED_ILK;
5126 else
5127 val |= PIPECONF_PROGRESSIVE;
5128
5129 I915_WRITE(PIPECONF(cpu_transcoder), val);
5130 POSTING_READ(PIPECONF(cpu_transcoder));
5131}
5132
5133static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5134 struct drm_display_mode *adjusted_mode,
5135 intel_clock_t *clock,
5136 bool *has_reduced_clock,
5137 intel_clock_t *reduced_clock)
5138{
5139 struct drm_device *dev = crtc->dev;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct intel_encoder *intel_encoder;
5142 int refclk;
5143 const intel_limit_t *limit;
5144 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5145
5146 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5147 switch (intel_encoder->type) {
5148 case INTEL_OUTPUT_LVDS:
5149 is_lvds = true;
5150 break;
5151 case INTEL_OUTPUT_SDVO:
5152 case INTEL_OUTPUT_HDMI:
5153 is_sdvo = true;
5154 if (intel_encoder->needs_tv_clock)
5155 is_tv = true;
5156 break;
5157 case INTEL_OUTPUT_TVOUT:
5158 is_tv = true;
5159 break;
5160 }
5161 }
5162
5163 refclk = ironlake_get_refclk(crtc);
5164
5165 /*
5166 * Returns a set of divisors for the desired target clock with the given
5167 * refclk, or FALSE. The returned values represent the clock equation:
5168 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5169 */
5170 limit = intel_limit(crtc, refclk);
5171 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5172 clock);
5173 if (!ret)
5174 return false;
5175
5176 if (is_lvds && dev_priv->lvds_downclock_avail) {
5177 /*
5178 * Ensure we match the reduced clock's P to the target clock.
5179 * If the clocks don't match, we can't switch the display clock
5180 * by using the FP0/FP1. In such case we will disable the LVDS
5181 * downclock feature.
5182 */
5183 *has_reduced_clock = limit->find_pll(limit, crtc,
5184 dev_priv->lvds_downclock,
5185 refclk,
5186 clock,
5187 reduced_clock);
5188 }
5189
5190 if (is_sdvo && is_tv)
5191 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5192
5193 return true;
5194}
5195
5196static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5197{
5198 struct drm_i915_private *dev_priv = dev->dev_private;
5199 uint32_t temp;
5200
5201 temp = I915_READ(SOUTH_CHICKEN1);
5202 if (temp & FDI_BC_BIFURCATION_SELECT)
5203 return;
5204
5205 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5206 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5207
5208 temp |= FDI_BC_BIFURCATION_SELECT;
5209 DRM_DEBUG_KMS("enabling fdi C rx\n");
5210 I915_WRITE(SOUTH_CHICKEN1, temp);
5211 POSTING_READ(SOUTH_CHICKEN1);
5212}
5213
5214static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5215{
5216 struct drm_device *dev = intel_crtc->base.dev;
5217 struct drm_i915_private *dev_priv = dev->dev_private;
5218 struct intel_crtc *pipe_B_crtc =
5219 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5220
5221 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5222 intel_crtc->pipe, intel_crtc->fdi_lanes);
5223 if (intel_crtc->fdi_lanes > 4) {
5224 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5225 intel_crtc->pipe, intel_crtc->fdi_lanes);
5226 /* Clamp lanes to avoid programming the hw with bogus values. */
5227 intel_crtc->fdi_lanes = 4;
5228
5229 return false;
5230 }
5231
5232 if (dev_priv->num_pipe == 2)
5233 return true;
5234
5235 switch (intel_crtc->pipe) {
5236 case PIPE_A:
5237 return true;
5238 case PIPE_B:
5239 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5240 intel_crtc->fdi_lanes > 2) {
5241 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5242 intel_crtc->pipe, intel_crtc->fdi_lanes);
5243 /* Clamp lanes to avoid programming the hw with bogus values. */
5244 intel_crtc->fdi_lanes = 2;
5245
5246 return false;
5247 }
5248
5249 if (intel_crtc->fdi_lanes > 2)
5250 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5251 else
5252 cpt_enable_fdi_bc_bifurcation(dev);
5253
5254 return true;
5255 case PIPE_C:
5256 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5257 if (intel_crtc->fdi_lanes > 2) {
5258 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5259 intel_crtc->pipe, intel_crtc->fdi_lanes);
5260 /* Clamp lanes to avoid programming the hw with bogus values. */
5261 intel_crtc->fdi_lanes = 2;
5262
5263 return false;
5264 }
5265 } else {
5266 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5267 return false;
5268 }
5269
5270 cpt_enable_fdi_bc_bifurcation(dev);
5271
5272 return true;
5273 default:
5274 BUG();
5275 }
5276}
5277
5278int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5279{
5280 /*
5281 * Account for spread spectrum to avoid
5282 * oversubscribing the link. Max center spread
5283 * is 2.5%; use 5% for safety's sake.
5284 */
5285 u32 bps = target_clock * bpp * 21 / 20;
5286 return bps / (link_bw * 8) + 1;
5287}
5288
5289static void ironlake_set_m_n(struct drm_crtc *crtc,
5290 struct drm_display_mode *mode,
5291 struct drm_display_mode *adjusted_mode)
5292{
5293 struct drm_device *dev = crtc->dev;
5294 struct drm_i915_private *dev_priv = dev->dev_private;
5295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5296 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5297 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5298 struct intel_link_m_n m_n = {0};
5299 int target_clock, pixel_multiplier, lane, link_bw;
5300 bool is_dp = false, is_cpu_edp = false;
5301
5302 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5303 switch (intel_encoder->type) {
5304 case INTEL_OUTPUT_DISPLAYPORT:
5305 is_dp = true;
5306 break;
5307 case INTEL_OUTPUT_EDP:
5308 is_dp = true;
5309 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5310 is_cpu_edp = true;
5311 edp_encoder = intel_encoder;
5312 break;
5313 }
5314 }
5315
5316 /* FDI link */
5317 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5318 lane = 0;
5319 /* CPU eDP doesn't require FDI link, so just set DP M/N
5320 according to current link config */
5321 if (is_cpu_edp) {
5322 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5323 } else {
5324 /* FDI is a binary signal running at ~2.7GHz, encoding
5325 * each output octet as 10 bits. The actual frequency
5326 * is stored as a divider into a 100MHz clock, and the
5327 * mode pixel clock is stored in units of 1KHz.
5328 * Hence the bw of each lane in terms of the mode signal
5329 * is:
5330 */
5331 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5332 }
5333
5334 /* [e]DP over FDI requires target mode clock instead of link clock. */
5335 if (edp_encoder)
5336 target_clock = intel_edp_target_clock(edp_encoder, mode);
5337 else if (is_dp)
5338 target_clock = mode->clock;
5339 else
5340 target_clock = adjusted_mode->clock;
5341
5342 if (!lane)
5343 lane = ironlake_get_lanes_required(target_clock, link_bw,
5344 intel_crtc->bpp);
5345
5346 intel_crtc->fdi_lanes = lane;
5347
5348 if (pixel_multiplier > 1)
5349 link_bw *= pixel_multiplier;
5350 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5351
5352 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5353 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5354 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5355 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5356}
5357
5358static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5359 struct drm_display_mode *adjusted_mode,
5360 intel_clock_t *clock, u32 fp)
5361{
5362 struct drm_crtc *crtc = &intel_crtc->base;
5363 struct drm_device *dev = crtc->dev;
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365 struct intel_encoder *intel_encoder;
5366 uint32_t dpll;
5367 int factor, pixel_multiplier, num_connectors = 0;
5368 bool is_lvds = false, is_sdvo = false, is_tv = false;
5369 bool is_dp = false, is_cpu_edp = false;
5370
5371 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5372 switch (intel_encoder->type) {
5373 case INTEL_OUTPUT_LVDS:
5374 is_lvds = true;
5375 break;
5376 case INTEL_OUTPUT_SDVO:
5377 case INTEL_OUTPUT_HDMI:
5378 is_sdvo = true;
5379 if (intel_encoder->needs_tv_clock)
5380 is_tv = true;
5381 break;
5382 case INTEL_OUTPUT_TVOUT:
5383 is_tv = true;
5384 break;
5385 case INTEL_OUTPUT_DISPLAYPORT:
5386 is_dp = true;
5387 break;
5388 case INTEL_OUTPUT_EDP:
5389 is_dp = true;
5390 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5391 is_cpu_edp = true;
5392 break;
5393 }
5394
5395 num_connectors++;
5396 }
5397
5398 /* Enable autotuning of the PLL clock (if permissible) */
5399 factor = 21;
5400 if (is_lvds) {
5401 if ((intel_panel_use_ssc(dev_priv) &&
5402 dev_priv->lvds_ssc_freq == 100) ||
5403 intel_is_dual_link_lvds(dev))
5404 factor = 25;
5405 } else if (is_sdvo && is_tv)
5406 factor = 20;
5407
5408 if (clock->m < factor * clock->n)
5409 fp |= FP_CB_TUNE;
5410
5411 dpll = 0;
5412
5413 if (is_lvds)
5414 dpll |= DPLLB_MODE_LVDS;
5415 else
5416 dpll |= DPLLB_MODE_DAC_SERIAL;
5417 if (is_sdvo) {
5418 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5419 if (pixel_multiplier > 1) {
5420 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5421 }
5422 dpll |= DPLL_DVO_HIGH_SPEED;
5423 }
5424 if (is_dp && !is_cpu_edp)
5425 dpll |= DPLL_DVO_HIGH_SPEED;
5426
5427 /* compute bitmask from p1 value */
5428 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5429 /* also FPA1 */
5430 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5431
5432 switch (clock->p2) {
5433 case 5:
5434 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5435 break;
5436 case 7:
5437 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5438 break;
5439 case 10:
5440 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5441 break;
5442 case 14:
5443 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5444 break;
5445 }
5446
5447 if (is_sdvo && is_tv)
5448 dpll |= PLL_REF_INPUT_TVCLKINBC;
5449 else if (is_tv)
5450 /* XXX: just matching BIOS for now */
5451 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5452 dpll |= 3;
5453 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5455 else
5456 dpll |= PLL_REF_INPUT_DREFCLK;
5457
5458 return dpll;
5459}
5460
5461static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5462 struct drm_display_mode *mode,
5463 struct drm_display_mode *adjusted_mode,
5464 int x, int y,
5465 struct drm_framebuffer *fb)
5466{
5467 struct drm_device *dev = crtc->dev;
5468 struct drm_i915_private *dev_priv = dev->dev_private;
5469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5470 int pipe = intel_crtc->pipe;
5471 int plane = intel_crtc->plane;
5472 int num_connectors = 0;
5473 intel_clock_t clock, reduced_clock;
5474 u32 dpll, fp = 0, fp2 = 0;
5475 bool ok, has_reduced_clock = false;
5476 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5477 struct intel_encoder *encoder;
5478 int ret;
5479 bool dither, fdi_config_ok;
5480
5481 for_each_encoder_on_crtc(dev, crtc, encoder) {
5482 switch (encoder->type) {
5483 case INTEL_OUTPUT_LVDS:
5484 is_lvds = true;
5485 break;
5486 case INTEL_OUTPUT_DISPLAYPORT:
5487 is_dp = true;
5488 break;
5489 case INTEL_OUTPUT_EDP:
5490 is_dp = true;
5491 if (!intel_encoder_is_pch_edp(&encoder->base))
5492 is_cpu_edp = true;
5493 break;
5494 }
5495
5496 num_connectors++;
5497 }
5498
5499 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5500 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5501
5502 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5503 &has_reduced_clock, &reduced_clock);
5504 if (!ok) {
5505 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5506 return -EINVAL;
5507 }
5508
5509 /* Ensure that the cursor is valid for the new mode before changing... */
5510 intel_crtc_update_cursor(crtc, true);
5511
5512 /* determine panel color depth */
5513 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5514 adjusted_mode);
5515 if (is_lvds && dev_priv->lvds_dither)
5516 dither = true;
5517
5518 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5519 if (has_reduced_clock)
5520 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5521 reduced_clock.m2;
5522
5523 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5524
5525 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5526 drm_mode_debug_printmodeline(mode);
5527
5528 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5529 if (!is_cpu_edp) {
5530 struct intel_pch_pll *pll;
5531
5532 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5533 if (pll == NULL) {
5534 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5535 pipe);
5536 return -EINVAL;
5537 }
5538 } else
5539 intel_put_pch_pll(intel_crtc);
5540
5541 if (is_dp && !is_cpu_edp)
5542 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5543
5544 for_each_encoder_on_crtc(dev, crtc, encoder)
5545 if (encoder->pre_pll_enable)
5546 encoder->pre_pll_enable(encoder);
5547
5548 if (intel_crtc->pch_pll) {
5549 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5550
5551 /* Wait for the clocks to stabilize. */
5552 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5553 udelay(150);
5554
5555 /* The pixel multiplier can only be updated once the
5556 * DPLL is enabled and the clocks are stable.
5557 *
5558 * So write it again.
5559 */
5560 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5561 }
5562
5563 intel_crtc->lowfreq_avail = false;
5564 if (intel_crtc->pch_pll) {
5565 if (is_lvds && has_reduced_clock && i915_powersave) {
5566 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5567 intel_crtc->lowfreq_avail = true;
5568 } else {
5569 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5570 }
5571 }
5572
5573 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5574
5575 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5576 * ironlake_check_fdi_lanes. */
5577 ironlake_set_m_n(crtc, mode, adjusted_mode);
5578
5579 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5580
5581 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5582
5583 intel_wait_for_vblank(dev, pipe);
5584
5585 /* Set up the display plane register */
5586 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5587 POSTING_READ(DSPCNTR(plane));
5588
5589 ret = intel_pipe_set_base(crtc, x, y, fb);
5590
5591 intel_update_watermarks(dev);
5592
5593 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5594
5595 return fdi_config_ok ? ret : -EINVAL;
5596}
5597
5598static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5599 struct drm_display_mode *mode,
5600 struct drm_display_mode *adjusted_mode,
5601 int x, int y,
5602 struct drm_framebuffer *fb)
5603{
5604 struct drm_device *dev = crtc->dev;
5605 struct drm_i915_private *dev_priv = dev->dev_private;
5606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5607 int pipe = intel_crtc->pipe;
5608 int plane = intel_crtc->plane;
5609 int num_connectors = 0;
5610 bool is_dp = false, is_cpu_edp = false;
5611 struct intel_encoder *encoder;
5612 int ret;
5613 bool dither;
5614
5615 for_each_encoder_on_crtc(dev, crtc, encoder) {
5616 switch (encoder->type) {
5617 case INTEL_OUTPUT_DISPLAYPORT:
5618 is_dp = true;
5619 break;
5620 case INTEL_OUTPUT_EDP:
5621 is_dp = true;
5622 if (!intel_encoder_is_pch_edp(&encoder->base))
5623 is_cpu_edp = true;
5624 break;
5625 }
5626
5627 num_connectors++;
5628 }
5629
5630 if (is_cpu_edp)
5631 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5632 else
5633 intel_crtc->cpu_transcoder = pipe;
5634
5635 /* We are not sure yet this won't happen. */
5636 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5637 INTEL_PCH_TYPE(dev));
5638
5639 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5640 num_connectors, pipe_name(pipe));
5641
5642 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5643 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5644
5645 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5646
5647 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5648 return -EINVAL;
5649
5650 /* Ensure that the cursor is valid for the new mode before changing... */
5651 intel_crtc_update_cursor(crtc, true);
5652
5653 /* determine panel color depth */
5654 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5655 adjusted_mode);
5656
5657 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5658 drm_mode_debug_printmodeline(mode);
5659
5660 if (is_dp && !is_cpu_edp)
5661 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5662
5663 intel_crtc->lowfreq_avail = false;
5664
5665 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5666
5667 if (!is_dp || is_cpu_edp)
5668 ironlake_set_m_n(crtc, mode, adjusted_mode);
5669
5670 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5671
5672 /* Set up the display plane register */
5673 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5674 POSTING_READ(DSPCNTR(plane));
5675
5676 ret = intel_pipe_set_base(crtc, x, y, fb);
5677
5678 intel_update_watermarks(dev);
5679
5680 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5681
5682 return ret;
5683}
5684
5685static int intel_crtc_mode_set(struct drm_crtc *crtc,
5686 struct drm_display_mode *mode,
5687 struct drm_display_mode *adjusted_mode,
5688 int x, int y,
5689 struct drm_framebuffer *fb)
5690{
5691 struct drm_device *dev = crtc->dev;
5692 struct drm_i915_private *dev_priv = dev->dev_private;
5693 struct drm_encoder_helper_funcs *encoder_funcs;
5694 struct intel_encoder *encoder;
5695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5696 int pipe = intel_crtc->pipe;
5697 int ret;
5698
5699 drm_vblank_pre_modeset(dev, pipe);
5700
5701 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5702 x, y, fb);
5703 drm_vblank_post_modeset(dev, pipe);
5704
5705 if (ret != 0)
5706 return ret;
5707
5708 for_each_encoder_on_crtc(dev, crtc, encoder) {
5709 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5710 encoder->base.base.id,
5711 drm_get_encoder_name(&encoder->base),
5712 mode->base.id, mode->name);
5713 encoder_funcs = encoder->base.helper_private;
5714 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5715 }
5716
5717 return 0;
5718}
5719
5720static bool intel_eld_uptodate(struct drm_connector *connector,
5721 int reg_eldv, uint32_t bits_eldv,
5722 int reg_elda, uint32_t bits_elda,
5723 int reg_edid)
5724{
5725 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5726 uint8_t *eld = connector->eld;
5727 uint32_t i;
5728
5729 i = I915_READ(reg_eldv);
5730 i &= bits_eldv;
5731
5732 if (!eld[0])
5733 return !i;
5734
5735 if (!i)
5736 return false;
5737
5738 i = I915_READ(reg_elda);
5739 i &= ~bits_elda;
5740 I915_WRITE(reg_elda, i);
5741
5742 for (i = 0; i < eld[2]; i++)
5743 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5744 return false;
5745
5746 return true;
5747}
5748
5749static void g4x_write_eld(struct drm_connector *connector,
5750 struct drm_crtc *crtc)
5751{
5752 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5753 uint8_t *eld = connector->eld;
5754 uint32_t eldv;
5755 uint32_t len;
5756 uint32_t i;
5757
5758 i = I915_READ(G4X_AUD_VID_DID);
5759
5760 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5761 eldv = G4X_ELDV_DEVCL_DEVBLC;
5762 else
5763 eldv = G4X_ELDV_DEVCTG;
5764
5765 if (intel_eld_uptodate(connector,
5766 G4X_AUD_CNTL_ST, eldv,
5767 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5768 G4X_HDMIW_HDMIEDID))
5769 return;
5770
5771 i = I915_READ(G4X_AUD_CNTL_ST);
5772 i &= ~(eldv | G4X_ELD_ADDR);
5773 len = (i >> 9) & 0x1f; /* ELD buffer size */
5774 I915_WRITE(G4X_AUD_CNTL_ST, i);
5775
5776 if (!eld[0])
5777 return;
5778
5779 len = min_t(uint8_t, eld[2], len);
5780 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5781 for (i = 0; i < len; i++)
5782 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5783
5784 i = I915_READ(G4X_AUD_CNTL_ST);
5785 i |= eldv;
5786 I915_WRITE(G4X_AUD_CNTL_ST, i);
5787}
5788
5789static void haswell_write_eld(struct drm_connector *connector,
5790 struct drm_crtc *crtc)
5791{
5792 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5793 uint8_t *eld = connector->eld;
5794 struct drm_device *dev = crtc->dev;
5795 uint32_t eldv;
5796 uint32_t i;
5797 int len;
5798 int pipe = to_intel_crtc(crtc)->pipe;
5799 int tmp;
5800
5801 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5802 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5803 int aud_config = HSW_AUD_CFG(pipe);
5804 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5805
5806
5807 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5808
5809 /* Audio output enable */
5810 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5811 tmp = I915_READ(aud_cntrl_st2);
5812 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5813 I915_WRITE(aud_cntrl_st2, tmp);
5814
5815 /* Wait for 1 vertical blank */
5816 intel_wait_for_vblank(dev, pipe);
5817
5818 /* Set ELD valid state */
5819 tmp = I915_READ(aud_cntrl_st2);
5820 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5821 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5822 I915_WRITE(aud_cntrl_st2, tmp);
5823 tmp = I915_READ(aud_cntrl_st2);
5824 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5825
5826 /* Enable HDMI mode */
5827 tmp = I915_READ(aud_config);
5828 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5829 /* clear N_programing_enable and N_value_index */
5830 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5831 I915_WRITE(aud_config, tmp);
5832
5833 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5834
5835 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5836
5837 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5838 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5839 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5840 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5841 } else
5842 I915_WRITE(aud_config, 0);
5843
5844 if (intel_eld_uptodate(connector,
5845 aud_cntrl_st2, eldv,
5846 aud_cntl_st, IBX_ELD_ADDRESS,
5847 hdmiw_hdmiedid))
5848 return;
5849
5850 i = I915_READ(aud_cntrl_st2);
5851 i &= ~eldv;
5852 I915_WRITE(aud_cntrl_st2, i);
5853
5854 if (!eld[0])
5855 return;
5856
5857 i = I915_READ(aud_cntl_st);
5858 i &= ~IBX_ELD_ADDRESS;
5859 I915_WRITE(aud_cntl_st, i);
5860 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5861 DRM_DEBUG_DRIVER("port num:%d\n", i);
5862
5863 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5864 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5865 for (i = 0; i < len; i++)
5866 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5867
5868 i = I915_READ(aud_cntrl_st2);
5869 i |= eldv;
5870 I915_WRITE(aud_cntrl_st2, i);
5871
5872}
5873
5874static void ironlake_write_eld(struct drm_connector *connector,
5875 struct drm_crtc *crtc)
5876{
5877 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5878 uint8_t *eld = connector->eld;
5879 uint32_t eldv;
5880 uint32_t i;
5881 int len;
5882 int hdmiw_hdmiedid;
5883 int aud_config;
5884 int aud_cntl_st;
5885 int aud_cntrl_st2;
5886 int pipe = to_intel_crtc(crtc)->pipe;
5887
5888 if (HAS_PCH_IBX(connector->dev)) {
5889 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5890 aud_config = IBX_AUD_CFG(pipe);
5891 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5892 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5893 } else {
5894 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5895 aud_config = CPT_AUD_CFG(pipe);
5896 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5897 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5898 }
5899
5900 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5901
5902 i = I915_READ(aud_cntl_st);
5903 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5904 if (!i) {
5905 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5906 /* operate blindly on all ports */
5907 eldv = IBX_ELD_VALIDB;
5908 eldv |= IBX_ELD_VALIDB << 4;
5909 eldv |= IBX_ELD_VALIDB << 8;
5910 } else {
5911 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5912 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5913 }
5914
5915 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5916 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5917 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5918 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5919 } else
5920 I915_WRITE(aud_config, 0);
5921
5922 if (intel_eld_uptodate(connector,
5923 aud_cntrl_st2, eldv,
5924 aud_cntl_st, IBX_ELD_ADDRESS,
5925 hdmiw_hdmiedid))
5926 return;
5927
5928 i = I915_READ(aud_cntrl_st2);
5929 i &= ~eldv;
5930 I915_WRITE(aud_cntrl_st2, i);
5931
5932 if (!eld[0])
5933 return;
5934
5935 i = I915_READ(aud_cntl_st);
5936 i &= ~IBX_ELD_ADDRESS;
5937 I915_WRITE(aud_cntl_st, i);
5938
5939 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5940 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5941 for (i = 0; i < len; i++)
5942 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5943
5944 i = I915_READ(aud_cntrl_st2);
5945 i |= eldv;
5946 I915_WRITE(aud_cntrl_st2, i);
5947}
5948
5949void intel_write_eld(struct drm_encoder *encoder,
5950 struct drm_display_mode *mode)
5951{
5952 struct drm_crtc *crtc = encoder->crtc;
5953 struct drm_connector *connector;
5954 struct drm_device *dev = encoder->dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956
5957 connector = drm_select_eld(encoder, mode);
5958 if (!connector)
5959 return;
5960
5961 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5962 connector->base.id,
5963 drm_get_connector_name(connector),
5964 connector->encoder->base.id,
5965 drm_get_encoder_name(connector->encoder));
5966
5967 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5968
5969 if (dev_priv->display.write_eld)
5970 dev_priv->display.write_eld(connector, crtc);
5971}
5972
5973/** Loads the palette/gamma unit for the CRTC with the prepared values */
5974void intel_crtc_load_lut(struct drm_crtc *crtc)
5975{
5976 struct drm_device *dev = crtc->dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5979 int palreg = PALETTE(intel_crtc->pipe);
5980 int i;
5981
5982 /* The clocks have to be on to load the palette. */
5983 if (!crtc->enabled || !intel_crtc->active)
5984 return;
5985
5986 /* use legacy palette for Ironlake */
5987 if (HAS_PCH_SPLIT(dev))
5988 palreg = LGC_PALETTE(intel_crtc->pipe);
5989
5990 for (i = 0; i < 256; i++) {
5991 I915_WRITE(palreg + 4 * i,
5992 (intel_crtc->lut_r[i] << 16) |
5993 (intel_crtc->lut_g[i] << 8) |
5994 intel_crtc->lut_b[i]);
5995 }
5996}
5997
5998static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5999{
6000 struct drm_device *dev = crtc->dev;
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003 bool visible = base != 0;
6004 u32 cntl;
6005
6006 if (intel_crtc->cursor_visible == visible)
6007 return;
6008
6009 cntl = I915_READ(_CURACNTR);
6010 if (visible) {
6011 /* On these chipsets we can only modify the base whilst
6012 * the cursor is disabled.
6013 */
6014 I915_WRITE(_CURABASE, base);
6015
6016 cntl &= ~(CURSOR_FORMAT_MASK);
6017 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6018 cntl |= CURSOR_ENABLE |
6019 CURSOR_GAMMA_ENABLE |
6020 CURSOR_FORMAT_ARGB;
6021 } else
6022 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6023 I915_WRITE(_CURACNTR, cntl);
6024
6025 intel_crtc->cursor_visible = visible;
6026}
6027
6028static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6029{
6030 struct drm_device *dev = crtc->dev;
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6033 int pipe = intel_crtc->pipe;
6034 bool visible = base != 0;
6035
6036 if (intel_crtc->cursor_visible != visible) {
6037 uint32_t cntl = I915_READ(CURCNTR(pipe));
6038 if (base) {
6039 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6040 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6041 cntl |= pipe << 28; /* Connect to correct pipe */
6042 } else {
6043 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6044 cntl |= CURSOR_MODE_DISABLE;
6045 }
6046 I915_WRITE(CURCNTR(pipe), cntl);
6047
6048 intel_crtc->cursor_visible = visible;
6049 }
6050 /* and commit changes on next vblank */
6051 I915_WRITE(CURBASE(pipe), base);
6052}
6053
6054static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6055{
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059 int pipe = intel_crtc->pipe;
6060 bool visible = base != 0;
6061
6062 if (intel_crtc->cursor_visible != visible) {
6063 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6064 if (base) {
6065 cntl &= ~CURSOR_MODE;
6066 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6067 } else {
6068 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6069 cntl |= CURSOR_MODE_DISABLE;
6070 }
6071 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6072
6073 intel_crtc->cursor_visible = visible;
6074 }
6075 /* and commit changes on next vblank */
6076 I915_WRITE(CURBASE_IVB(pipe), base);
6077}
6078
6079/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6080static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6081 bool on)
6082{
6083 struct drm_device *dev = crtc->dev;
6084 struct drm_i915_private *dev_priv = dev->dev_private;
6085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6086 int pipe = intel_crtc->pipe;
6087 int x = intel_crtc->cursor_x;
6088 int y = intel_crtc->cursor_y;
6089 u32 base, pos;
6090 bool visible;
6091
6092 pos = 0;
6093
6094 if (on && crtc->enabled && crtc->fb) {
6095 base = intel_crtc->cursor_addr;
6096 if (x > (int) crtc->fb->width)
6097 base = 0;
6098
6099 if (y > (int) crtc->fb->height)
6100 base = 0;
6101 } else
6102 base = 0;
6103
6104 if (x < 0) {
6105 if (x + intel_crtc->cursor_width < 0)
6106 base = 0;
6107
6108 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6109 x = -x;
6110 }
6111 pos |= x << CURSOR_X_SHIFT;
6112
6113 if (y < 0) {
6114 if (y + intel_crtc->cursor_height < 0)
6115 base = 0;
6116
6117 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6118 y = -y;
6119 }
6120 pos |= y << CURSOR_Y_SHIFT;
6121
6122 visible = base != 0;
6123 if (!visible && !intel_crtc->cursor_visible)
6124 return;
6125
6126 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6127 I915_WRITE(CURPOS_IVB(pipe), pos);
6128 ivb_update_cursor(crtc, base);
6129 } else {
6130 I915_WRITE(CURPOS(pipe), pos);
6131 if (IS_845G(dev) || IS_I865G(dev))
6132 i845_update_cursor(crtc, base);
6133 else
6134 i9xx_update_cursor(crtc, base);
6135 }
6136}
6137
6138static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6139 struct drm_file *file,
6140 uint32_t handle,
6141 uint32_t width, uint32_t height)
6142{
6143 struct drm_device *dev = crtc->dev;
6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146 struct drm_i915_gem_object *obj;
6147 uint32_t addr;
6148 int ret;
6149
6150 /* if we want to turn off the cursor ignore width and height */
6151 if (!handle) {
6152 DRM_DEBUG_KMS("cursor off\n");
6153 addr = 0;
6154 obj = NULL;
6155 mutex_lock(&dev->struct_mutex);
6156 goto finish;
6157 }
6158
6159 /* Currently we only support 64x64 cursors */
6160 if (width != 64 || height != 64) {
6161 DRM_ERROR("we currently only support 64x64 cursors\n");
6162 return -EINVAL;
6163 }
6164
6165 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6166 if (&obj->base == NULL)
6167 return -ENOENT;
6168
6169 if (obj->base.size < width * height * 4) {
6170 DRM_ERROR("buffer is to small\n");
6171 ret = -ENOMEM;
6172 goto fail;
6173 }
6174
6175 /* we only need to pin inside GTT if cursor is non-phy */
6176 mutex_lock(&dev->struct_mutex);
6177 if (!dev_priv->info->cursor_needs_physical) {
6178 if (obj->tiling_mode) {
6179 DRM_ERROR("cursor cannot be tiled\n");
6180 ret = -EINVAL;
6181 goto fail_locked;
6182 }
6183
6184 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6185 if (ret) {
6186 DRM_ERROR("failed to move cursor bo into the GTT\n");
6187 goto fail_locked;
6188 }
6189
6190 ret = i915_gem_object_put_fence(obj);
6191 if (ret) {
6192 DRM_ERROR("failed to release fence for cursor");
6193 goto fail_unpin;
6194 }
6195
6196 addr = obj->gtt_offset;
6197 } else {
6198 int align = IS_I830(dev) ? 16 * 1024 : 256;
6199 ret = i915_gem_attach_phys_object(dev, obj,
6200 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6201 align);
6202 if (ret) {
6203 DRM_ERROR("failed to attach phys object\n");
6204 goto fail_locked;
6205 }
6206 addr = obj->phys_obj->handle->busaddr;
6207 }
6208
6209 if (IS_GEN2(dev))
6210 I915_WRITE(CURSIZE, (height << 12) | width);
6211
6212 finish:
6213 if (intel_crtc->cursor_bo) {
6214 if (dev_priv->info->cursor_needs_physical) {
6215 if (intel_crtc->cursor_bo != obj)
6216 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6217 } else
6218 i915_gem_object_unpin(intel_crtc->cursor_bo);
6219 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6220 }
6221
6222 mutex_unlock(&dev->struct_mutex);
6223
6224 intel_crtc->cursor_addr = addr;
6225 intel_crtc->cursor_bo = obj;
6226 intel_crtc->cursor_width = width;
6227 intel_crtc->cursor_height = height;
6228
6229 intel_crtc_update_cursor(crtc, true);
6230
6231 return 0;
6232fail_unpin:
6233 i915_gem_object_unpin(obj);
6234fail_locked:
6235 mutex_unlock(&dev->struct_mutex);
6236fail:
6237 drm_gem_object_unreference_unlocked(&obj->base);
6238 return ret;
6239}
6240
6241static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6242{
6243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6244
6245 intel_crtc->cursor_x = x;
6246 intel_crtc->cursor_y = y;
6247
6248 intel_crtc_update_cursor(crtc, true);
6249
6250 return 0;
6251}
6252
6253/** Sets the color ramps on behalf of RandR */
6254void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6255 u16 blue, int regno)
6256{
6257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6258
6259 intel_crtc->lut_r[regno] = red >> 8;
6260 intel_crtc->lut_g[regno] = green >> 8;
6261 intel_crtc->lut_b[regno] = blue >> 8;
6262}
6263
6264void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6265 u16 *blue, int regno)
6266{
6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268
6269 *red = intel_crtc->lut_r[regno] << 8;
6270 *green = intel_crtc->lut_g[regno] << 8;
6271 *blue = intel_crtc->lut_b[regno] << 8;
6272}
6273
6274static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6275 u16 *blue, uint32_t start, uint32_t size)
6276{
6277 int end = (start + size > 256) ? 256 : start + size, i;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279
6280 for (i = start; i < end; i++) {
6281 intel_crtc->lut_r[i] = red[i] >> 8;
6282 intel_crtc->lut_g[i] = green[i] >> 8;
6283 intel_crtc->lut_b[i] = blue[i] >> 8;
6284 }
6285
6286 intel_crtc_load_lut(crtc);
6287}
6288
6289/**
6290 * Get a pipe with a simple mode set on it for doing load-based monitor
6291 * detection.
6292 *
6293 * It will be up to the load-detect code to adjust the pipe as appropriate for
6294 * its requirements. The pipe will be connected to no other encoders.
6295 *
6296 * Currently this code will only succeed if there is a pipe with no encoders
6297 * configured for it. In the future, it could choose to temporarily disable
6298 * some outputs to free up a pipe for its use.
6299 *
6300 * \return crtc, or NULL if no pipes are available.
6301 */
6302
6303/* VESA 640x480x72Hz mode to set on the pipe */
6304static struct drm_display_mode load_detect_mode = {
6305 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6306 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6307};
6308
6309static struct drm_framebuffer *
6310intel_framebuffer_create(struct drm_device *dev,
6311 struct drm_mode_fb_cmd2 *mode_cmd,
6312 struct drm_i915_gem_object *obj)
6313{
6314 struct intel_framebuffer *intel_fb;
6315 int ret;
6316
6317 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6318 if (!intel_fb) {
6319 drm_gem_object_unreference_unlocked(&obj->base);
6320 return ERR_PTR(-ENOMEM);
6321 }
6322
6323 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6324 if (ret) {
6325 drm_gem_object_unreference_unlocked(&obj->base);
6326 kfree(intel_fb);
6327 return ERR_PTR(ret);
6328 }
6329
6330 return &intel_fb->base;
6331}
6332
6333static u32
6334intel_framebuffer_pitch_for_width(int width, int bpp)
6335{
6336 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6337 return ALIGN(pitch, 64);
6338}
6339
6340static u32
6341intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6342{
6343 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6344 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6345}
6346
6347static struct drm_framebuffer *
6348intel_framebuffer_create_for_mode(struct drm_device *dev,
6349 struct drm_display_mode *mode,
6350 int depth, int bpp)
6351{
6352 struct drm_i915_gem_object *obj;
6353 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6354
6355 obj = i915_gem_alloc_object(dev,
6356 intel_framebuffer_size_for_mode(mode, bpp));
6357 if (obj == NULL)
6358 return ERR_PTR(-ENOMEM);
6359
6360 mode_cmd.width = mode->hdisplay;
6361 mode_cmd.height = mode->vdisplay;
6362 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6363 bpp);
6364 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6365
6366 return intel_framebuffer_create(dev, &mode_cmd, obj);
6367}
6368
6369static struct drm_framebuffer *
6370mode_fits_in_fbdev(struct drm_device *dev,
6371 struct drm_display_mode *mode)
6372{
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct drm_i915_gem_object *obj;
6375 struct drm_framebuffer *fb;
6376
6377 if (dev_priv->fbdev == NULL)
6378 return NULL;
6379
6380 obj = dev_priv->fbdev->ifb.obj;
6381 if (obj == NULL)
6382 return NULL;
6383
6384 fb = &dev_priv->fbdev->ifb.base;
6385 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6386 fb->bits_per_pixel))
6387 return NULL;
6388
6389 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6390 return NULL;
6391
6392 return fb;
6393}
6394
6395bool intel_get_load_detect_pipe(struct drm_connector *connector,
6396 struct drm_display_mode *mode,
6397 struct intel_load_detect_pipe *old)
6398{
6399 struct intel_crtc *intel_crtc;
6400 struct intel_encoder *intel_encoder =
6401 intel_attached_encoder(connector);
6402 struct drm_crtc *possible_crtc;
6403 struct drm_encoder *encoder = &intel_encoder->base;
6404 struct drm_crtc *crtc = NULL;
6405 struct drm_device *dev = encoder->dev;
6406 struct drm_framebuffer *fb;
6407 int i = -1;
6408
6409 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6410 connector->base.id, drm_get_connector_name(connector),
6411 encoder->base.id, drm_get_encoder_name(encoder));
6412
6413 /*
6414 * Algorithm gets a little messy:
6415 *
6416 * - if the connector already has an assigned crtc, use it (but make
6417 * sure it's on first)
6418 *
6419 * - try to find the first unused crtc that can drive this connector,
6420 * and use that if we find one
6421 */
6422
6423 /* See if we already have a CRTC for this connector */
6424 if (encoder->crtc) {
6425 crtc = encoder->crtc;
6426
6427 old->dpms_mode = connector->dpms;
6428 old->load_detect_temp = false;
6429
6430 /* Make sure the crtc and connector are running */
6431 if (connector->dpms != DRM_MODE_DPMS_ON)
6432 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6433
6434 return true;
6435 }
6436
6437 /* Find an unused one (if possible) */
6438 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6439 i++;
6440 if (!(encoder->possible_crtcs & (1 << i)))
6441 continue;
6442 if (!possible_crtc->enabled) {
6443 crtc = possible_crtc;
6444 break;
6445 }
6446 }
6447
6448 /*
6449 * If we didn't find an unused CRTC, don't use any.
6450 */
6451 if (!crtc) {
6452 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6453 return false;
6454 }
6455
6456 intel_encoder->new_crtc = to_intel_crtc(crtc);
6457 to_intel_connector(connector)->new_encoder = intel_encoder;
6458
6459 intel_crtc = to_intel_crtc(crtc);
6460 old->dpms_mode = connector->dpms;
6461 old->load_detect_temp = true;
6462 old->release_fb = NULL;
6463
6464 if (!mode)
6465 mode = &load_detect_mode;
6466
6467 /* We need a framebuffer large enough to accommodate all accesses
6468 * that the plane may generate whilst we perform load detection.
6469 * We can not rely on the fbcon either being present (we get called
6470 * during its initialisation to detect all boot displays, or it may
6471 * not even exist) or that it is large enough to satisfy the
6472 * requested mode.
6473 */
6474 fb = mode_fits_in_fbdev(dev, mode);
6475 if (fb == NULL) {
6476 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6477 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6478 old->release_fb = fb;
6479 } else
6480 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6481 if (IS_ERR(fb)) {
6482 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6483 return false;
6484 }
6485
6486 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6487 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6488 if (old->release_fb)
6489 old->release_fb->funcs->destroy(old->release_fb);
6490 return false;
6491 }
6492
6493 /* let the connector get through one full cycle before testing */
6494 intel_wait_for_vblank(dev, intel_crtc->pipe);
6495 return true;
6496}
6497
6498void intel_release_load_detect_pipe(struct drm_connector *connector,
6499 struct intel_load_detect_pipe *old)
6500{
6501 struct intel_encoder *intel_encoder =
6502 intel_attached_encoder(connector);
6503 struct drm_encoder *encoder = &intel_encoder->base;
6504
6505 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6506 connector->base.id, drm_get_connector_name(connector),
6507 encoder->base.id, drm_get_encoder_name(encoder));
6508
6509 if (old->load_detect_temp) {
6510 struct drm_crtc *crtc = encoder->crtc;
6511
6512 to_intel_connector(connector)->new_encoder = NULL;
6513 intel_encoder->new_crtc = NULL;
6514 intel_set_mode(crtc, NULL, 0, 0, NULL);
6515
6516 if (old->release_fb)
6517 old->release_fb->funcs->destroy(old->release_fb);
6518
6519 return;
6520 }
6521
6522 /* Switch crtc and encoder back off if necessary */
6523 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6524 connector->funcs->dpms(connector, old->dpms_mode);
6525}
6526
6527/* Returns the clock of the currently programmed mode of the given pipe. */
6528static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6529{
6530 struct drm_i915_private *dev_priv = dev->dev_private;
6531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6532 int pipe = intel_crtc->pipe;
6533 u32 dpll = I915_READ(DPLL(pipe));
6534 u32 fp;
6535 intel_clock_t clock;
6536
6537 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6538 fp = I915_READ(FP0(pipe));
6539 else
6540 fp = I915_READ(FP1(pipe));
6541
6542 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6543 if (IS_PINEVIEW(dev)) {
6544 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6545 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6546 } else {
6547 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6548 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6549 }
6550
6551 if (!IS_GEN2(dev)) {
6552 if (IS_PINEVIEW(dev))
6553 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6554 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6555 else
6556 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6557 DPLL_FPA01_P1_POST_DIV_SHIFT);
6558
6559 switch (dpll & DPLL_MODE_MASK) {
6560 case DPLLB_MODE_DAC_SERIAL:
6561 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6562 5 : 10;
6563 break;
6564 case DPLLB_MODE_LVDS:
6565 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6566 7 : 14;
6567 break;
6568 default:
6569 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6570 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6571 return 0;
6572 }
6573
6574 /* XXX: Handle the 100Mhz refclk */
6575 intel_clock(dev, 96000, &clock);
6576 } else {
6577 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6578
6579 if (is_lvds) {
6580 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6581 DPLL_FPA01_P1_POST_DIV_SHIFT);
6582 clock.p2 = 14;
6583
6584 if ((dpll & PLL_REF_INPUT_MASK) ==
6585 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6586 /* XXX: might not be 66MHz */
6587 intel_clock(dev, 66000, &clock);
6588 } else
6589 intel_clock(dev, 48000, &clock);
6590 } else {
6591 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6592 clock.p1 = 2;
6593 else {
6594 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6595 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6596 }
6597 if (dpll & PLL_P2_DIVIDE_BY_4)
6598 clock.p2 = 4;
6599 else
6600 clock.p2 = 2;
6601
6602 intel_clock(dev, 48000, &clock);
6603 }
6604 }
6605
6606 /* XXX: It would be nice to validate the clocks, but we can't reuse
6607 * i830PllIsValid() because it relies on the xf86_config connector
6608 * configuration being accurate, which it isn't necessarily.
6609 */
6610
6611 return clock.dot;
6612}
6613
6614/** Returns the currently programmed mode of the given pipe. */
6615struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6616 struct drm_crtc *crtc)
6617{
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6620 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6621 struct drm_display_mode *mode;
6622 int htot = I915_READ(HTOTAL(cpu_transcoder));
6623 int hsync = I915_READ(HSYNC(cpu_transcoder));
6624 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6625 int vsync = I915_READ(VSYNC(cpu_transcoder));
6626
6627 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6628 if (!mode)
6629 return NULL;
6630
6631 mode->clock = intel_crtc_clock_get(dev, crtc);
6632 mode->hdisplay = (htot & 0xffff) + 1;
6633 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6634 mode->hsync_start = (hsync & 0xffff) + 1;
6635 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6636 mode->vdisplay = (vtot & 0xffff) + 1;
6637 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6638 mode->vsync_start = (vsync & 0xffff) + 1;
6639 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6640
6641 drm_mode_set_name(mode);
6642
6643 return mode;
6644}
6645
6646static void intel_increase_pllclock(struct drm_crtc *crtc)
6647{
6648 struct drm_device *dev = crtc->dev;
6649 drm_i915_private_t *dev_priv = dev->dev_private;
6650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6651 int pipe = intel_crtc->pipe;
6652 int dpll_reg = DPLL(pipe);
6653 int dpll;
6654
6655 if (HAS_PCH_SPLIT(dev))
6656 return;
6657
6658 if (!dev_priv->lvds_downclock_avail)
6659 return;
6660
6661 dpll = I915_READ(dpll_reg);
6662 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6663 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6664
6665 assert_panel_unlocked(dev_priv, pipe);
6666
6667 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6668 I915_WRITE(dpll_reg, dpll);
6669 intel_wait_for_vblank(dev, pipe);
6670
6671 dpll = I915_READ(dpll_reg);
6672 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6673 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6674 }
6675}
6676
6677static void intel_decrease_pllclock(struct drm_crtc *crtc)
6678{
6679 struct drm_device *dev = crtc->dev;
6680 drm_i915_private_t *dev_priv = dev->dev_private;
6681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6682
6683 if (HAS_PCH_SPLIT(dev))
6684 return;
6685
6686 if (!dev_priv->lvds_downclock_avail)
6687 return;
6688
6689 /*
6690 * Since this is called by a timer, we should never get here in
6691 * the manual case.
6692 */
6693 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6694 int pipe = intel_crtc->pipe;
6695 int dpll_reg = DPLL(pipe);
6696 int dpll;
6697
6698 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6699
6700 assert_panel_unlocked(dev_priv, pipe);
6701
6702 dpll = I915_READ(dpll_reg);
6703 dpll |= DISPLAY_RATE_SELECT_FPA1;
6704 I915_WRITE(dpll_reg, dpll);
6705 intel_wait_for_vblank(dev, pipe);
6706 dpll = I915_READ(dpll_reg);
6707 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6708 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6709 }
6710
6711}
6712
6713void intel_mark_busy(struct drm_device *dev)
6714{
6715 i915_update_gfx_val(dev->dev_private);
6716}
6717
6718void intel_mark_idle(struct drm_device *dev)
6719{
6720}
6721
6722void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6723{
6724 struct drm_device *dev = obj->base.dev;
6725 struct drm_crtc *crtc;
6726
6727 if (!i915_powersave)
6728 return;
6729
6730 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6731 if (!crtc->fb)
6732 continue;
6733
6734 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6735 intel_increase_pllclock(crtc);
6736 }
6737}
6738
6739void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6740{
6741 struct drm_device *dev = obj->base.dev;
6742 struct drm_crtc *crtc;
6743
6744 if (!i915_powersave)
6745 return;
6746
6747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6748 if (!crtc->fb)
6749 continue;
6750
6751 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6752 intel_decrease_pllclock(crtc);
6753 }
6754}
6755
6756static void intel_crtc_destroy(struct drm_crtc *crtc)
6757{
6758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759 struct drm_device *dev = crtc->dev;
6760 struct intel_unpin_work *work;
6761 unsigned long flags;
6762
6763 spin_lock_irqsave(&dev->event_lock, flags);
6764 work = intel_crtc->unpin_work;
6765 intel_crtc->unpin_work = NULL;
6766 spin_unlock_irqrestore(&dev->event_lock, flags);
6767
6768 if (work) {
6769 cancel_work_sync(&work->work);
6770 kfree(work);
6771 }
6772
6773 drm_crtc_cleanup(crtc);
6774
6775 kfree(intel_crtc);
6776}
6777
6778static void intel_unpin_work_fn(struct work_struct *__work)
6779{
6780 struct intel_unpin_work *work =
6781 container_of(__work, struct intel_unpin_work, work);
6782 struct drm_device *dev = work->crtc->dev;
6783
6784 mutex_lock(&dev->struct_mutex);
6785 intel_unpin_fb_obj(work->old_fb_obj);
6786 drm_gem_object_unreference(&work->pending_flip_obj->base);
6787 drm_gem_object_unreference(&work->old_fb_obj->base);
6788
6789 intel_update_fbc(dev);
6790 mutex_unlock(&dev->struct_mutex);
6791
6792 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6793 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6794
6795 kfree(work);
6796}
6797
6798static void do_intel_finish_page_flip(struct drm_device *dev,
6799 struct drm_crtc *crtc)
6800{
6801 drm_i915_private_t *dev_priv = dev->dev_private;
6802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6803 struct intel_unpin_work *work;
6804 struct drm_i915_gem_object *obj;
6805 unsigned long flags;
6806
6807 /* Ignore early vblank irqs */
6808 if (intel_crtc == NULL)
6809 return;
6810
6811 spin_lock_irqsave(&dev->event_lock, flags);
6812 work = intel_crtc->unpin_work;
6813
6814 /* Ensure we don't miss a work->pending update ... */
6815 smp_rmb();
6816
6817 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6818 spin_unlock_irqrestore(&dev->event_lock, flags);
6819 return;
6820 }
6821
6822 /* and that the unpin work is consistent wrt ->pending. */
6823 smp_rmb();
6824
6825 intel_crtc->unpin_work = NULL;
6826
6827 if (work->event)
6828 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6829
6830 drm_vblank_put(dev, intel_crtc->pipe);
6831
6832 spin_unlock_irqrestore(&dev->event_lock, flags);
6833
6834 obj = work->old_fb_obj;
6835
6836 wake_up_all(&dev_priv->pending_flip_queue);
6837
6838 queue_work(dev_priv->wq, &work->work);
6839
6840 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6841}
6842
6843void intel_finish_page_flip(struct drm_device *dev, int pipe)
6844{
6845 drm_i915_private_t *dev_priv = dev->dev_private;
6846 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6847
6848 do_intel_finish_page_flip(dev, crtc);
6849}
6850
6851void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6852{
6853 drm_i915_private_t *dev_priv = dev->dev_private;
6854 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6855
6856 do_intel_finish_page_flip(dev, crtc);
6857}
6858
6859void intel_prepare_page_flip(struct drm_device *dev, int plane)
6860{
6861 drm_i915_private_t *dev_priv = dev->dev_private;
6862 struct intel_crtc *intel_crtc =
6863 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6864 unsigned long flags;
6865
6866 /* NB: An MMIO update of the plane base pointer will also
6867 * generate a page-flip completion irq, i.e. every modeset
6868 * is also accompanied by a spurious intel_prepare_page_flip().
6869 */
6870 spin_lock_irqsave(&dev->event_lock, flags);
6871 if (intel_crtc->unpin_work)
6872 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6873 spin_unlock_irqrestore(&dev->event_lock, flags);
6874}
6875
6876inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6877{
6878 /* Ensure that the work item is consistent when activating it ... */
6879 smp_wmb();
6880 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6881 /* and that it is marked active as soon as the irq could fire. */
6882 smp_wmb();
6883}
6884
6885static int intel_gen2_queue_flip(struct drm_device *dev,
6886 struct drm_crtc *crtc,
6887 struct drm_framebuffer *fb,
6888 struct drm_i915_gem_object *obj)
6889{
6890 struct drm_i915_private *dev_priv = dev->dev_private;
6891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6892 u32 flip_mask;
6893 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6894 int ret;
6895
6896 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6897 if (ret)
6898 goto err;
6899
6900 ret = intel_ring_begin(ring, 6);
6901 if (ret)
6902 goto err_unpin;
6903
6904 /* Can't queue multiple flips, so wait for the previous
6905 * one to finish before executing the next.
6906 */
6907 if (intel_crtc->plane)
6908 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6909 else
6910 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6911 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6912 intel_ring_emit(ring, MI_NOOP);
6913 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6914 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6915 intel_ring_emit(ring, fb->pitches[0]);
6916 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6917 intel_ring_emit(ring, 0); /* aux display base address, unused */
6918
6919 intel_mark_page_flip_active(intel_crtc);
6920 intel_ring_advance(ring);
6921 return 0;
6922
6923err_unpin:
6924 intel_unpin_fb_obj(obj);
6925err:
6926 return ret;
6927}
6928
6929static int intel_gen3_queue_flip(struct drm_device *dev,
6930 struct drm_crtc *crtc,
6931 struct drm_framebuffer *fb,
6932 struct drm_i915_gem_object *obj)
6933{
6934 struct drm_i915_private *dev_priv = dev->dev_private;
6935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6936 u32 flip_mask;
6937 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6938 int ret;
6939
6940 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6941 if (ret)
6942 goto err;
6943
6944 ret = intel_ring_begin(ring, 6);
6945 if (ret)
6946 goto err_unpin;
6947
6948 if (intel_crtc->plane)
6949 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6950 else
6951 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6952 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6953 intel_ring_emit(ring, MI_NOOP);
6954 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6955 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6956 intel_ring_emit(ring, fb->pitches[0]);
6957 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6958 intel_ring_emit(ring, MI_NOOP);
6959
6960 intel_mark_page_flip_active(intel_crtc);
6961 intel_ring_advance(ring);
6962 return 0;
6963
6964err_unpin:
6965 intel_unpin_fb_obj(obj);
6966err:
6967 return ret;
6968}
6969
6970static int intel_gen4_queue_flip(struct drm_device *dev,
6971 struct drm_crtc *crtc,
6972 struct drm_framebuffer *fb,
6973 struct drm_i915_gem_object *obj)
6974{
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6977 uint32_t pf, pipesrc;
6978 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6979 int ret;
6980
6981 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6982 if (ret)
6983 goto err;
6984
6985 ret = intel_ring_begin(ring, 4);
6986 if (ret)
6987 goto err_unpin;
6988
6989 /* i965+ uses the linear or tiled offsets from the
6990 * Display Registers (which do not change across a page-flip)
6991 * so we need only reprogram the base address.
6992 */
6993 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6994 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6995 intel_ring_emit(ring, fb->pitches[0]);
6996 intel_ring_emit(ring,
6997 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6998 obj->tiling_mode);
6999
7000 /* XXX Enabling the panel-fitter across page-flip is so far
7001 * untested on non-native modes, so ignore it for now.
7002 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7003 */
7004 pf = 0;
7005 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7006 intel_ring_emit(ring, pf | pipesrc);
7007
7008 intel_mark_page_flip_active(intel_crtc);
7009 intel_ring_advance(ring);
7010 return 0;
7011
7012err_unpin:
7013 intel_unpin_fb_obj(obj);
7014err:
7015 return ret;
7016}
7017
7018static int intel_gen6_queue_flip(struct drm_device *dev,
7019 struct drm_crtc *crtc,
7020 struct drm_framebuffer *fb,
7021 struct drm_i915_gem_object *obj)
7022{
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7025 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7026 uint32_t pf, pipesrc;
7027 int ret;
7028
7029 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7030 if (ret)
7031 goto err;
7032
7033 ret = intel_ring_begin(ring, 4);
7034 if (ret)
7035 goto err_unpin;
7036
7037 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7039 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7040 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7041
7042 /* Contrary to the suggestions in the documentation,
7043 * "Enable Panel Fitter" does not seem to be required when page
7044 * flipping with a non-native mode, and worse causes a normal
7045 * modeset to fail.
7046 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7047 */
7048 pf = 0;
7049 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7050 intel_ring_emit(ring, pf | pipesrc);
7051
7052 intel_mark_page_flip_active(intel_crtc);
7053 intel_ring_advance(ring);
7054 return 0;
7055
7056err_unpin:
7057 intel_unpin_fb_obj(obj);
7058err:
7059 return ret;
7060}
7061
7062/*
7063 * On gen7 we currently use the blit ring because (in early silicon at least)
7064 * the render ring doesn't give us interrpts for page flip completion, which
7065 * means clients will hang after the first flip is queued. Fortunately the
7066 * blit ring generates interrupts properly, so use it instead.
7067 */
7068static int intel_gen7_queue_flip(struct drm_device *dev,
7069 struct drm_crtc *crtc,
7070 struct drm_framebuffer *fb,
7071 struct drm_i915_gem_object *obj)
7072{
7073 struct drm_i915_private *dev_priv = dev->dev_private;
7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7075 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7076 uint32_t plane_bit = 0;
7077 int ret;
7078
7079 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7080 if (ret)
7081 goto err;
7082
7083 switch(intel_crtc->plane) {
7084 case PLANE_A:
7085 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7086 break;
7087 case PLANE_B:
7088 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7089 break;
7090 case PLANE_C:
7091 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7092 break;
7093 default:
7094 WARN_ONCE(1, "unknown plane in flip command\n");
7095 ret = -ENODEV;
7096 goto err_unpin;
7097 }
7098
7099 ret = intel_ring_begin(ring, 4);
7100 if (ret)
7101 goto err_unpin;
7102
7103 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7104 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7105 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7106 intel_ring_emit(ring, (MI_NOOP));
7107
7108 intel_mark_page_flip_active(intel_crtc);
7109 intel_ring_advance(ring);
7110 return 0;
7111
7112err_unpin:
7113 intel_unpin_fb_obj(obj);
7114err:
7115 return ret;
7116}
7117
7118static int intel_default_queue_flip(struct drm_device *dev,
7119 struct drm_crtc *crtc,
7120 struct drm_framebuffer *fb,
7121 struct drm_i915_gem_object *obj)
7122{
7123 return -ENODEV;
7124}
7125
7126static int intel_crtc_page_flip(struct drm_crtc *crtc,
7127 struct drm_framebuffer *fb,
7128 struct drm_pending_vblank_event *event)
7129{
7130 struct drm_device *dev = crtc->dev;
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 struct intel_framebuffer *intel_fb;
7133 struct drm_i915_gem_object *obj;
7134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7135 struct intel_unpin_work *work;
7136 unsigned long flags;
7137 int ret;
7138
7139 /* Can't change pixel format via MI display flips. */
7140 if (fb->pixel_format != crtc->fb->pixel_format)
7141 return -EINVAL;
7142
7143 /*
7144 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7145 * Note that pitch changes could also affect these register.
7146 */
7147 if (INTEL_INFO(dev)->gen > 3 &&
7148 (fb->offsets[0] != crtc->fb->offsets[0] ||
7149 fb->pitches[0] != crtc->fb->pitches[0]))
7150 return -EINVAL;
7151
7152 work = kzalloc(sizeof *work, GFP_KERNEL);
7153 if (work == NULL)
7154 return -ENOMEM;
7155
7156 work->event = event;
7157 work->crtc = crtc;
7158 intel_fb = to_intel_framebuffer(crtc->fb);
7159 work->old_fb_obj = intel_fb->obj;
7160 INIT_WORK(&work->work, intel_unpin_work_fn);
7161
7162 ret = drm_vblank_get(dev, intel_crtc->pipe);
7163 if (ret)
7164 goto free_work;
7165
7166 /* We borrow the event spin lock for protecting unpin_work */
7167 spin_lock_irqsave(&dev->event_lock, flags);
7168 if (intel_crtc->unpin_work) {
7169 spin_unlock_irqrestore(&dev->event_lock, flags);
7170 kfree(work);
7171 drm_vblank_put(dev, intel_crtc->pipe);
7172
7173 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7174 return -EBUSY;
7175 }
7176 intel_crtc->unpin_work = work;
7177 spin_unlock_irqrestore(&dev->event_lock, flags);
7178
7179 intel_fb = to_intel_framebuffer(fb);
7180 obj = intel_fb->obj;
7181
7182 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7183 flush_workqueue(dev_priv->wq);
7184
7185 ret = i915_mutex_lock_interruptible(dev);
7186 if (ret)
7187 goto cleanup;
7188
7189 /* Reference the objects for the scheduled work. */
7190 drm_gem_object_reference(&work->old_fb_obj->base);
7191 drm_gem_object_reference(&obj->base);
7192
7193 crtc->fb = fb;
7194
7195 work->pending_flip_obj = obj;
7196
7197 work->enable_stall_check = true;
7198
7199 atomic_inc(&intel_crtc->unpin_work_count);
7200
7201 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7202 if (ret)
7203 goto cleanup_pending;
7204
7205 intel_disable_fbc(dev);
7206 intel_mark_fb_busy(obj);
7207 mutex_unlock(&dev->struct_mutex);
7208
7209 trace_i915_flip_request(intel_crtc->plane, obj);
7210
7211 return 0;
7212
7213cleanup_pending:
7214 atomic_dec(&intel_crtc->unpin_work_count);
7215 drm_gem_object_unreference(&work->old_fb_obj->base);
7216 drm_gem_object_unreference(&obj->base);
7217 mutex_unlock(&dev->struct_mutex);
7218
7219cleanup:
7220 spin_lock_irqsave(&dev->event_lock, flags);
7221 intel_crtc->unpin_work = NULL;
7222 spin_unlock_irqrestore(&dev->event_lock, flags);
7223
7224 drm_vblank_put(dev, intel_crtc->pipe);
7225free_work:
7226 kfree(work);
7227
7228 return ret;
7229}
7230
7231static struct drm_crtc_helper_funcs intel_helper_funcs = {
7232 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7233 .load_lut = intel_crtc_load_lut,
7234 .disable = intel_crtc_noop,
7235};
7236
7237bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7238{
7239 struct intel_encoder *other_encoder;
7240 struct drm_crtc *crtc = &encoder->new_crtc->base;
7241
7242 if (WARN_ON(!crtc))
7243 return false;
7244
7245 list_for_each_entry(other_encoder,
7246 &crtc->dev->mode_config.encoder_list,
7247 base.head) {
7248
7249 if (&other_encoder->new_crtc->base != crtc ||
7250 encoder == other_encoder)
7251 continue;
7252 else
7253 return true;
7254 }
7255
7256 return false;
7257}
7258
7259static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7260 struct drm_crtc *crtc)
7261{
7262 struct drm_device *dev;
7263 struct drm_crtc *tmp;
7264 int crtc_mask = 1;
7265
7266 WARN(!crtc, "checking null crtc?\n");
7267
7268 dev = crtc->dev;
7269
7270 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7271 if (tmp == crtc)
7272 break;
7273 crtc_mask <<= 1;
7274 }
7275
7276 if (encoder->possible_crtcs & crtc_mask)
7277 return true;
7278 return false;
7279}
7280
7281/**
7282 * intel_modeset_update_staged_output_state
7283 *
7284 * Updates the staged output configuration state, e.g. after we've read out the
7285 * current hw state.
7286 */
7287static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7288{
7289 struct intel_encoder *encoder;
7290 struct intel_connector *connector;
7291
7292 list_for_each_entry(connector, &dev->mode_config.connector_list,
7293 base.head) {
7294 connector->new_encoder =
7295 to_intel_encoder(connector->base.encoder);
7296 }
7297
7298 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7299 base.head) {
7300 encoder->new_crtc =
7301 to_intel_crtc(encoder->base.crtc);
7302 }
7303}
7304
7305/**
7306 * intel_modeset_commit_output_state
7307 *
7308 * This function copies the stage display pipe configuration to the real one.
7309 */
7310static void intel_modeset_commit_output_state(struct drm_device *dev)
7311{
7312 struct intel_encoder *encoder;
7313 struct intel_connector *connector;
7314
7315 list_for_each_entry(connector, &dev->mode_config.connector_list,
7316 base.head) {
7317 connector->base.encoder = &connector->new_encoder->base;
7318 }
7319
7320 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7321 base.head) {
7322 encoder->base.crtc = &encoder->new_crtc->base;
7323 }
7324}
7325
7326static struct drm_display_mode *
7327intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7328 struct drm_display_mode *mode)
7329{
7330 struct drm_device *dev = crtc->dev;
7331 struct drm_display_mode *adjusted_mode;
7332 struct drm_encoder_helper_funcs *encoder_funcs;
7333 struct intel_encoder *encoder;
7334
7335 adjusted_mode = drm_mode_duplicate(dev, mode);
7336 if (!adjusted_mode)
7337 return ERR_PTR(-ENOMEM);
7338
7339 /* Pass our mode to the connectors and the CRTC to give them a chance to
7340 * adjust it according to limitations or connector properties, and also
7341 * a chance to reject the mode entirely.
7342 */
7343 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7344 base.head) {
7345
7346 if (&encoder->new_crtc->base != crtc)
7347 continue;
7348 encoder_funcs = encoder->base.helper_private;
7349 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7350 adjusted_mode))) {
7351 DRM_DEBUG_KMS("Encoder fixup failed\n");
7352 goto fail;
7353 }
7354 }
7355
7356 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7357 DRM_DEBUG_KMS("CRTC fixup failed\n");
7358 goto fail;
7359 }
7360 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7361
7362 return adjusted_mode;
7363fail:
7364 drm_mode_destroy(dev, adjusted_mode);
7365 return ERR_PTR(-EINVAL);
7366}
7367
7368/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7369 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7370static void
7371intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7372 unsigned *prepare_pipes, unsigned *disable_pipes)
7373{
7374 struct intel_crtc *intel_crtc;
7375 struct drm_device *dev = crtc->dev;
7376 struct intel_encoder *encoder;
7377 struct intel_connector *connector;
7378 struct drm_crtc *tmp_crtc;
7379
7380 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7381
7382 /* Check which crtcs have changed outputs connected to them, these need
7383 * to be part of the prepare_pipes mask. We don't (yet) support global
7384 * modeset across multiple crtcs, so modeset_pipes will only have one
7385 * bit set at most. */
7386 list_for_each_entry(connector, &dev->mode_config.connector_list,
7387 base.head) {
7388 if (connector->base.encoder == &connector->new_encoder->base)
7389 continue;
7390
7391 if (connector->base.encoder) {
7392 tmp_crtc = connector->base.encoder->crtc;
7393
7394 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7395 }
7396
7397 if (connector->new_encoder)
7398 *prepare_pipes |=
7399 1 << connector->new_encoder->new_crtc->pipe;
7400 }
7401
7402 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7403 base.head) {
7404 if (encoder->base.crtc == &encoder->new_crtc->base)
7405 continue;
7406
7407 if (encoder->base.crtc) {
7408 tmp_crtc = encoder->base.crtc;
7409
7410 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7411 }
7412
7413 if (encoder->new_crtc)
7414 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7415 }
7416
7417 /* Check for any pipes that will be fully disabled ... */
7418 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7419 base.head) {
7420 bool used = false;
7421
7422 /* Don't try to disable disabled crtcs. */
7423 if (!intel_crtc->base.enabled)
7424 continue;
7425
7426 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7427 base.head) {
7428 if (encoder->new_crtc == intel_crtc)
7429 used = true;
7430 }
7431
7432 if (!used)
7433 *disable_pipes |= 1 << intel_crtc->pipe;
7434 }
7435
7436
7437 /* set_mode is also used to update properties on life display pipes. */
7438 intel_crtc = to_intel_crtc(crtc);
7439 if (crtc->enabled)
7440 *prepare_pipes |= 1 << intel_crtc->pipe;
7441
7442 /* We only support modeset on one single crtc, hence we need to do that
7443 * only for the passed in crtc iff we change anything else than just
7444 * disable crtcs.
7445 *
7446 * This is actually not true, to be fully compatible with the old crtc
7447 * helper we automatically disable _any_ output (i.e. doesn't need to be
7448 * connected to the crtc we're modesetting on) if it's disconnected.
7449 * Which is a rather nutty api (since changed the output configuration
7450 * without userspace's explicit request can lead to confusion), but
7451 * alas. Hence we currently need to modeset on all pipes we prepare. */
7452 if (*prepare_pipes)
7453 *modeset_pipes = *prepare_pipes;
7454
7455 /* ... and mask these out. */
7456 *modeset_pipes &= ~(*disable_pipes);
7457 *prepare_pipes &= ~(*disable_pipes);
7458}
7459
7460static bool intel_crtc_in_use(struct drm_crtc *crtc)
7461{
7462 struct drm_encoder *encoder;
7463 struct drm_device *dev = crtc->dev;
7464
7465 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7466 if (encoder->crtc == crtc)
7467 return true;
7468
7469 return false;
7470}
7471
7472static void
7473intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7474{
7475 struct intel_encoder *intel_encoder;
7476 struct intel_crtc *intel_crtc;
7477 struct drm_connector *connector;
7478
7479 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7480 base.head) {
7481 if (!intel_encoder->base.crtc)
7482 continue;
7483
7484 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7485
7486 if (prepare_pipes & (1 << intel_crtc->pipe))
7487 intel_encoder->connectors_active = false;
7488 }
7489
7490 intel_modeset_commit_output_state(dev);
7491
7492 /* Update computed state. */
7493 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7494 base.head) {
7495 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7496 }
7497
7498 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7499 if (!connector->encoder || !connector->encoder->crtc)
7500 continue;
7501
7502 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7503
7504 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7505 struct drm_property *dpms_property =
7506 dev->mode_config.dpms_property;
7507
7508 connector->dpms = DRM_MODE_DPMS_ON;
7509 drm_object_property_set_value(&connector->base,
7510 dpms_property,
7511 DRM_MODE_DPMS_ON);
7512
7513 intel_encoder = to_intel_encoder(connector->encoder);
7514 intel_encoder->connectors_active = true;
7515 }
7516 }
7517
7518}
7519
7520#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7521 list_for_each_entry((intel_crtc), \
7522 &(dev)->mode_config.crtc_list, \
7523 base.head) \
7524 if (mask & (1 <<(intel_crtc)->pipe)) \
7525
7526void
7527intel_modeset_check_state(struct drm_device *dev)
7528{
7529 struct intel_crtc *crtc;
7530 struct intel_encoder *encoder;
7531 struct intel_connector *connector;
7532
7533 list_for_each_entry(connector, &dev->mode_config.connector_list,
7534 base.head) {
7535 /* This also checks the encoder/connector hw state with the
7536 * ->get_hw_state callbacks. */
7537 intel_connector_check_state(connector);
7538
7539 WARN(&connector->new_encoder->base != connector->base.encoder,
7540 "connector's staged encoder doesn't match current encoder\n");
7541 }
7542
7543 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7544 base.head) {
7545 bool enabled = false;
7546 bool active = false;
7547 enum pipe pipe, tracked_pipe;
7548
7549 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7550 encoder->base.base.id,
7551 drm_get_encoder_name(&encoder->base));
7552
7553 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7554 "encoder's stage crtc doesn't match current crtc\n");
7555 WARN(encoder->connectors_active && !encoder->base.crtc,
7556 "encoder's active_connectors set, but no crtc\n");
7557
7558 list_for_each_entry(connector, &dev->mode_config.connector_list,
7559 base.head) {
7560 if (connector->base.encoder != &encoder->base)
7561 continue;
7562 enabled = true;
7563 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7564 active = true;
7565 }
7566 WARN(!!encoder->base.crtc != enabled,
7567 "encoder's enabled state mismatch "
7568 "(expected %i, found %i)\n",
7569 !!encoder->base.crtc, enabled);
7570 WARN(active && !encoder->base.crtc,
7571 "active encoder with no crtc\n");
7572
7573 WARN(encoder->connectors_active != active,
7574 "encoder's computed active state doesn't match tracked active state "
7575 "(expected %i, found %i)\n", active, encoder->connectors_active);
7576
7577 active = encoder->get_hw_state(encoder, &pipe);
7578 WARN(active != encoder->connectors_active,
7579 "encoder's hw state doesn't match sw tracking "
7580 "(expected %i, found %i)\n",
7581 encoder->connectors_active, active);
7582
7583 if (!encoder->base.crtc)
7584 continue;
7585
7586 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7587 WARN(active && pipe != tracked_pipe,
7588 "active encoder's pipe doesn't match"
7589 "(expected %i, found %i)\n",
7590 tracked_pipe, pipe);
7591
7592 }
7593
7594 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7595 base.head) {
7596 bool enabled = false;
7597 bool active = false;
7598
7599 DRM_DEBUG_KMS("[CRTC:%d]\n",
7600 crtc->base.base.id);
7601
7602 WARN(crtc->active && !crtc->base.enabled,
7603 "active crtc, but not enabled in sw tracking\n");
7604
7605 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7606 base.head) {
7607 if (encoder->base.crtc != &crtc->base)
7608 continue;
7609 enabled = true;
7610 if (encoder->connectors_active)
7611 active = true;
7612 }
7613 WARN(active != crtc->active,
7614 "crtc's computed active state doesn't match tracked active state "
7615 "(expected %i, found %i)\n", active, crtc->active);
7616 WARN(enabled != crtc->base.enabled,
7617 "crtc's computed enabled state doesn't match tracked enabled state "
7618 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7619
7620 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7621 }
7622}
7623
7624int intel_set_mode(struct drm_crtc *crtc,
7625 struct drm_display_mode *mode,
7626 int x, int y, struct drm_framebuffer *fb)
7627{
7628 struct drm_device *dev = crtc->dev;
7629 drm_i915_private_t *dev_priv = dev->dev_private;
7630 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7631 struct intel_crtc *intel_crtc;
7632 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7633 int ret = 0;
7634
7635 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7636 if (!saved_mode)
7637 return -ENOMEM;
7638 saved_hwmode = saved_mode + 1;
7639
7640 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7641 &prepare_pipes, &disable_pipes);
7642
7643 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7644 modeset_pipes, prepare_pipes, disable_pipes);
7645
7646 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7647 intel_crtc_disable(&intel_crtc->base);
7648
7649 *saved_hwmode = crtc->hwmode;
7650 *saved_mode = crtc->mode;
7651
7652 /* Hack: Because we don't (yet) support global modeset on multiple
7653 * crtcs, we don't keep track of the new mode for more than one crtc.
7654 * Hence simply check whether any bit is set in modeset_pipes in all the
7655 * pieces of code that are not yet converted to deal with mutliple crtcs
7656 * changing their mode at the same time. */
7657 adjusted_mode = NULL;
7658 if (modeset_pipes) {
7659 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7660 if (IS_ERR(adjusted_mode)) {
7661 ret = PTR_ERR(adjusted_mode);
7662 goto out;
7663 }
7664 }
7665
7666 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7667 if (intel_crtc->base.enabled)
7668 dev_priv->display.crtc_disable(&intel_crtc->base);
7669 }
7670
7671 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7672 * to set it here already despite that we pass it down the callchain.
7673 */
7674 if (modeset_pipes)
7675 crtc->mode = *mode;
7676
7677 /* Only after disabling all output pipelines that will be changed can we
7678 * update the the output configuration. */
7679 intel_modeset_update_state(dev, prepare_pipes);
7680
7681 if (dev_priv->display.modeset_global_resources)
7682 dev_priv->display.modeset_global_resources(dev);
7683
7684 /* Set up the DPLL and any encoders state that needs to adjust or depend
7685 * on the DPLL.
7686 */
7687 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7688 ret = intel_crtc_mode_set(&intel_crtc->base,
7689 mode, adjusted_mode,
7690 x, y, fb);
7691 if (ret)
7692 goto done;
7693 }
7694
7695 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7696 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7697 dev_priv->display.crtc_enable(&intel_crtc->base);
7698
7699 if (modeset_pipes) {
7700 /* Store real post-adjustment hardware mode. */
7701 crtc->hwmode = *adjusted_mode;
7702
7703 /* Calculate and store various constants which
7704 * are later needed by vblank and swap-completion
7705 * timestamping. They are derived from true hwmode.
7706 */
7707 drm_calc_timestamping_constants(crtc);
7708 }
7709
7710 /* FIXME: add subpixel order */
7711done:
7712 drm_mode_destroy(dev, adjusted_mode);
7713 if (ret && crtc->enabled) {
7714 crtc->hwmode = *saved_hwmode;
7715 crtc->mode = *saved_mode;
7716 } else {
7717 intel_modeset_check_state(dev);
7718 }
7719
7720out:
7721 kfree(saved_mode);
7722 return ret;
7723}
7724
7725void intel_crtc_restore_mode(struct drm_crtc *crtc)
7726{
7727 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7728}
7729
7730#undef for_each_intel_crtc_masked
7731
7732static void intel_set_config_free(struct intel_set_config *config)
7733{
7734 if (!config)
7735 return;
7736
7737 kfree(config->save_connector_encoders);
7738 kfree(config->save_encoder_crtcs);
7739 kfree(config);
7740}
7741
7742static int intel_set_config_save_state(struct drm_device *dev,
7743 struct intel_set_config *config)
7744{
7745 struct drm_encoder *encoder;
7746 struct drm_connector *connector;
7747 int count;
7748
7749 config->save_encoder_crtcs =
7750 kcalloc(dev->mode_config.num_encoder,
7751 sizeof(struct drm_crtc *), GFP_KERNEL);
7752 if (!config->save_encoder_crtcs)
7753 return -ENOMEM;
7754
7755 config->save_connector_encoders =
7756 kcalloc(dev->mode_config.num_connector,
7757 sizeof(struct drm_encoder *), GFP_KERNEL);
7758 if (!config->save_connector_encoders)
7759 return -ENOMEM;
7760
7761 /* Copy data. Note that driver private data is not affected.
7762 * Should anything bad happen only the expected state is
7763 * restored, not the drivers personal bookkeeping.
7764 */
7765 count = 0;
7766 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7767 config->save_encoder_crtcs[count++] = encoder->crtc;
7768 }
7769
7770 count = 0;
7771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7772 config->save_connector_encoders[count++] = connector->encoder;
7773 }
7774
7775 return 0;
7776}
7777
7778static void intel_set_config_restore_state(struct drm_device *dev,
7779 struct intel_set_config *config)
7780{
7781 struct intel_encoder *encoder;
7782 struct intel_connector *connector;
7783 int count;
7784
7785 count = 0;
7786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7787 encoder->new_crtc =
7788 to_intel_crtc(config->save_encoder_crtcs[count++]);
7789 }
7790
7791 count = 0;
7792 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7793 connector->new_encoder =
7794 to_intel_encoder(config->save_connector_encoders[count++]);
7795 }
7796}
7797
7798static void
7799intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7800 struct intel_set_config *config)
7801{
7802
7803 /* We should be able to check here if the fb has the same properties
7804 * and then just flip_or_move it */
7805 if (set->crtc->fb != set->fb) {
7806 /* If we have no fb then treat it as a full mode set */
7807 if (set->crtc->fb == NULL) {
7808 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7809 config->mode_changed = true;
7810 } else if (set->fb == NULL) {
7811 config->mode_changed = true;
7812 } else if (set->fb->depth != set->crtc->fb->depth) {
7813 config->mode_changed = true;
7814 } else if (set->fb->bits_per_pixel !=
7815 set->crtc->fb->bits_per_pixel) {
7816 config->mode_changed = true;
7817 } else
7818 config->fb_changed = true;
7819 }
7820
7821 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7822 config->fb_changed = true;
7823
7824 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7825 DRM_DEBUG_KMS("modes are different, full mode set\n");
7826 drm_mode_debug_printmodeline(&set->crtc->mode);
7827 drm_mode_debug_printmodeline(set->mode);
7828 config->mode_changed = true;
7829 }
7830}
7831
7832static int
7833intel_modeset_stage_output_state(struct drm_device *dev,
7834 struct drm_mode_set *set,
7835 struct intel_set_config *config)
7836{
7837 struct drm_crtc *new_crtc;
7838 struct intel_connector *connector;
7839 struct intel_encoder *encoder;
7840 int count, ro;
7841
7842 /* The upper layers ensure that we either disabl a crtc or have a list
7843 * of connectors. For paranoia, double-check this. */
7844 WARN_ON(!set->fb && (set->num_connectors != 0));
7845 WARN_ON(set->fb && (set->num_connectors == 0));
7846
7847 count = 0;
7848 list_for_each_entry(connector, &dev->mode_config.connector_list,
7849 base.head) {
7850 /* Otherwise traverse passed in connector list and get encoders
7851 * for them. */
7852 for (ro = 0; ro < set->num_connectors; ro++) {
7853 if (set->connectors[ro] == &connector->base) {
7854 connector->new_encoder = connector->encoder;
7855 break;
7856 }
7857 }
7858
7859 /* If we disable the crtc, disable all its connectors. Also, if
7860 * the connector is on the changing crtc but not on the new
7861 * connector list, disable it. */
7862 if ((!set->fb || ro == set->num_connectors) &&
7863 connector->base.encoder &&
7864 connector->base.encoder->crtc == set->crtc) {
7865 connector->new_encoder = NULL;
7866
7867 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7868 connector->base.base.id,
7869 drm_get_connector_name(&connector->base));
7870 }
7871
7872
7873 if (&connector->new_encoder->base != connector->base.encoder) {
7874 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7875 config->mode_changed = true;
7876 }
7877 }
7878 /* connector->new_encoder is now updated for all connectors. */
7879
7880 /* Update crtc of enabled connectors. */
7881 count = 0;
7882 list_for_each_entry(connector, &dev->mode_config.connector_list,
7883 base.head) {
7884 if (!connector->new_encoder)
7885 continue;
7886
7887 new_crtc = connector->new_encoder->base.crtc;
7888
7889 for (ro = 0; ro < set->num_connectors; ro++) {
7890 if (set->connectors[ro] == &connector->base)
7891 new_crtc = set->crtc;
7892 }
7893
7894 /* Make sure the new CRTC will work with the encoder */
7895 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7896 new_crtc)) {
7897 return -EINVAL;
7898 }
7899 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7900
7901 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7902 connector->base.base.id,
7903 drm_get_connector_name(&connector->base),
7904 new_crtc->base.id);
7905 }
7906
7907 /* Check for any encoders that needs to be disabled. */
7908 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7909 base.head) {
7910 list_for_each_entry(connector,
7911 &dev->mode_config.connector_list,
7912 base.head) {
7913 if (connector->new_encoder == encoder) {
7914 WARN_ON(!connector->new_encoder->new_crtc);
7915
7916 goto next_encoder;
7917 }
7918 }
7919 encoder->new_crtc = NULL;
7920next_encoder:
7921 /* Only now check for crtc changes so we don't miss encoders
7922 * that will be disabled. */
7923 if (&encoder->new_crtc->base != encoder->base.crtc) {
7924 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7925 config->mode_changed = true;
7926 }
7927 }
7928 /* Now we've also updated encoder->new_crtc for all encoders. */
7929
7930 return 0;
7931}
7932
7933static int intel_crtc_set_config(struct drm_mode_set *set)
7934{
7935 struct drm_device *dev;
7936 struct drm_mode_set save_set;
7937 struct intel_set_config *config;
7938 int ret;
7939
7940 BUG_ON(!set);
7941 BUG_ON(!set->crtc);
7942 BUG_ON(!set->crtc->helper_private);
7943
7944 if (!set->mode)
7945 set->fb = NULL;
7946
7947 /* The fb helper likes to play gross jokes with ->mode_set_config.
7948 * Unfortunately the crtc helper doesn't do much at all for this case,
7949 * so we have to cope with this madness until the fb helper is fixed up. */
7950 if (set->fb && set->num_connectors == 0)
7951 return 0;
7952
7953 if (set->fb) {
7954 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7955 set->crtc->base.id, set->fb->base.id,
7956 (int)set->num_connectors, set->x, set->y);
7957 } else {
7958 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7959 }
7960
7961 dev = set->crtc->dev;
7962
7963 ret = -ENOMEM;
7964 config = kzalloc(sizeof(*config), GFP_KERNEL);
7965 if (!config)
7966 goto out_config;
7967
7968 ret = intel_set_config_save_state(dev, config);
7969 if (ret)
7970 goto out_config;
7971
7972 save_set.crtc = set->crtc;
7973 save_set.mode = &set->crtc->mode;
7974 save_set.x = set->crtc->x;
7975 save_set.y = set->crtc->y;
7976 save_set.fb = set->crtc->fb;
7977
7978 /* Compute whether we need a full modeset, only an fb base update or no
7979 * change at all. In the future we might also check whether only the
7980 * mode changed, e.g. for LVDS where we only change the panel fitter in
7981 * such cases. */
7982 intel_set_config_compute_mode_changes(set, config);
7983
7984 ret = intel_modeset_stage_output_state(dev, set, config);
7985 if (ret)
7986 goto fail;
7987
7988 if (config->mode_changed) {
7989 if (set->mode) {
7990 DRM_DEBUG_KMS("attempting to set mode from"
7991 " userspace\n");
7992 drm_mode_debug_printmodeline(set->mode);
7993 }
7994
7995 ret = intel_set_mode(set->crtc, set->mode,
7996 set->x, set->y, set->fb);
7997 if (ret) {
7998 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
7999 set->crtc->base.id, ret);
8000 goto fail;
8001 }
8002 } else if (config->fb_changed) {
8003 ret = intel_pipe_set_base(set->crtc,
8004 set->x, set->y, set->fb);
8005 }
8006
8007 intel_set_config_free(config);
8008
8009 return 0;
8010
8011fail:
8012 intel_set_config_restore_state(dev, config);
8013
8014 /* Try to restore the config */
8015 if (config->mode_changed &&
8016 intel_set_mode(save_set.crtc, save_set.mode,
8017 save_set.x, save_set.y, save_set.fb))
8018 DRM_ERROR("failed to restore config after modeset failure\n");
8019
8020out_config:
8021 intel_set_config_free(config);
8022 return ret;
8023}
8024
8025static const struct drm_crtc_funcs intel_crtc_funcs = {
8026 .cursor_set = intel_crtc_cursor_set,
8027 .cursor_move = intel_crtc_cursor_move,
8028 .gamma_set = intel_crtc_gamma_set,
8029 .set_config = intel_crtc_set_config,
8030 .destroy = intel_crtc_destroy,
8031 .page_flip = intel_crtc_page_flip,
8032};
8033
8034static void intel_cpu_pll_init(struct drm_device *dev)
8035{
8036 if (HAS_DDI(dev))
8037 intel_ddi_pll_init(dev);
8038}
8039
8040static void intel_pch_pll_init(struct drm_device *dev)
8041{
8042 drm_i915_private_t *dev_priv = dev->dev_private;
8043 int i;
8044
8045 if (dev_priv->num_pch_pll == 0) {
8046 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8047 return;
8048 }
8049
8050 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8051 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8052 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8053 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8054 }
8055}
8056
8057static void intel_crtc_init(struct drm_device *dev, int pipe)
8058{
8059 drm_i915_private_t *dev_priv = dev->dev_private;
8060 struct intel_crtc *intel_crtc;
8061 int i;
8062
8063 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8064 if (intel_crtc == NULL)
8065 return;
8066
8067 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8068
8069 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8070 for (i = 0; i < 256; i++) {
8071 intel_crtc->lut_r[i] = i;
8072 intel_crtc->lut_g[i] = i;
8073 intel_crtc->lut_b[i] = i;
8074 }
8075
8076 /* Swap pipes & planes for FBC on pre-965 */
8077 intel_crtc->pipe = pipe;
8078 intel_crtc->plane = pipe;
8079 intel_crtc->cpu_transcoder = pipe;
8080 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8081 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8082 intel_crtc->plane = !pipe;
8083 }
8084
8085 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8086 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8087 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8088 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8089
8090 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8091
8092 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8093}
8094
8095int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8096 struct drm_file *file)
8097{
8098 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8099 struct drm_mode_object *drmmode_obj;
8100 struct intel_crtc *crtc;
8101
8102 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8103 return -ENODEV;
8104
8105 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8106 DRM_MODE_OBJECT_CRTC);
8107
8108 if (!drmmode_obj) {
8109 DRM_ERROR("no such CRTC id\n");
8110 return -EINVAL;
8111 }
8112
8113 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8114 pipe_from_crtc_id->pipe = crtc->pipe;
8115
8116 return 0;
8117}
8118
8119static int intel_encoder_clones(struct intel_encoder *encoder)
8120{
8121 struct drm_device *dev = encoder->base.dev;
8122 struct intel_encoder *source_encoder;
8123 int index_mask = 0;
8124 int entry = 0;
8125
8126 list_for_each_entry(source_encoder,
8127 &dev->mode_config.encoder_list, base.head) {
8128
8129 if (encoder == source_encoder)
8130 index_mask |= (1 << entry);
8131
8132 /* Intel hw has only one MUX where enocoders could be cloned. */
8133 if (encoder->cloneable && source_encoder->cloneable)
8134 index_mask |= (1 << entry);
8135
8136 entry++;
8137 }
8138
8139 return index_mask;
8140}
8141
8142static bool has_edp_a(struct drm_device *dev)
8143{
8144 struct drm_i915_private *dev_priv = dev->dev_private;
8145
8146 if (!IS_MOBILE(dev))
8147 return false;
8148
8149 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8150 return false;
8151
8152 if (IS_GEN5(dev) &&
8153 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8154 return false;
8155
8156 return true;
8157}
8158
8159static void intel_setup_outputs(struct drm_device *dev)
8160{
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162 struct intel_encoder *encoder;
8163 bool dpd_is_edp = false;
8164 bool has_lvds;
8165
8166 has_lvds = intel_lvds_init(dev);
8167 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8168 /* disable the panel fitter on everything but LVDS */
8169 I915_WRITE(PFIT_CONTROL, 0);
8170 }
8171
8172 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8173 intel_crt_init(dev);
8174
8175 if (HAS_DDI(dev)) {
8176 int found;
8177
8178 /* Haswell uses DDI functions to detect digital outputs */
8179 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8180 /* DDI A only supports eDP */
8181 if (found)
8182 intel_ddi_init(dev, PORT_A);
8183
8184 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8185 * register */
8186 found = I915_READ(SFUSE_STRAP);
8187
8188 if (found & SFUSE_STRAP_DDIB_DETECTED)
8189 intel_ddi_init(dev, PORT_B);
8190 if (found & SFUSE_STRAP_DDIC_DETECTED)
8191 intel_ddi_init(dev, PORT_C);
8192 if (found & SFUSE_STRAP_DDID_DETECTED)
8193 intel_ddi_init(dev, PORT_D);
8194 } else if (HAS_PCH_SPLIT(dev)) {
8195 int found;
8196 dpd_is_edp = intel_dpd_is_edp(dev);
8197
8198 if (has_edp_a(dev))
8199 intel_dp_init(dev, DP_A, PORT_A);
8200
8201 if (I915_READ(HDMIB) & PORT_DETECTED) {
8202 /* PCH SDVOB multiplex with HDMIB */
8203 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8204 if (!found)
8205 intel_hdmi_init(dev, HDMIB, PORT_B);
8206 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8207 intel_dp_init(dev, PCH_DP_B, PORT_B);
8208 }
8209
8210 if (I915_READ(HDMIC) & PORT_DETECTED)
8211 intel_hdmi_init(dev, HDMIC, PORT_C);
8212
8213 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8214 intel_hdmi_init(dev, HDMID, PORT_D);
8215
8216 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8217 intel_dp_init(dev, PCH_DP_C, PORT_C);
8218
8219 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8220 intel_dp_init(dev, PCH_DP_D, PORT_D);
8221 } else if (IS_VALLEYVIEW(dev)) {
8222 int found;
8223
8224 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8225 if (I915_READ(DP_C) & DP_DETECTED)
8226 intel_dp_init(dev, DP_C, PORT_C);
8227
8228 if (I915_READ(SDVOB) & PORT_DETECTED) {
8229 /* SDVOB multiplex with HDMIB */
8230 found = intel_sdvo_init(dev, SDVOB, true);
8231 if (!found)
8232 intel_hdmi_init(dev, SDVOB, PORT_B);
8233 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8234 intel_dp_init(dev, DP_B, PORT_B);
8235 }
8236
8237 if (I915_READ(SDVOC) & PORT_DETECTED)
8238 intel_hdmi_init(dev, SDVOC, PORT_C);
8239
8240 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8241 bool found = false;
8242
8243 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8244 DRM_DEBUG_KMS("probing SDVOB\n");
8245 found = intel_sdvo_init(dev, SDVOB, true);
8246 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8247 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8248 intel_hdmi_init(dev, SDVOB, PORT_B);
8249 }
8250
8251 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8252 DRM_DEBUG_KMS("probing DP_B\n");
8253 intel_dp_init(dev, DP_B, PORT_B);
8254 }
8255 }
8256
8257 /* Before G4X SDVOC doesn't have its own detect register */
8258
8259 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8260 DRM_DEBUG_KMS("probing SDVOC\n");
8261 found = intel_sdvo_init(dev, SDVOC, false);
8262 }
8263
8264 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8265
8266 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8267 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8268 intel_hdmi_init(dev, SDVOC, PORT_C);
8269 }
8270 if (SUPPORTS_INTEGRATED_DP(dev)) {
8271 DRM_DEBUG_KMS("probing DP_C\n");
8272 intel_dp_init(dev, DP_C, PORT_C);
8273 }
8274 }
8275
8276 if (SUPPORTS_INTEGRATED_DP(dev) &&
8277 (I915_READ(DP_D) & DP_DETECTED)) {
8278 DRM_DEBUG_KMS("probing DP_D\n");
8279 intel_dp_init(dev, DP_D, PORT_D);
8280 }
8281 } else if (IS_GEN2(dev))
8282 intel_dvo_init(dev);
8283
8284 if (SUPPORTS_TV(dev))
8285 intel_tv_init(dev);
8286
8287 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8288 encoder->base.possible_crtcs = encoder->crtc_mask;
8289 encoder->base.possible_clones =
8290 intel_encoder_clones(encoder);
8291 }
8292
8293 intel_init_pch_refclk(dev);
8294
8295 drm_helper_move_panel_connectors_to_head(dev);
8296}
8297
8298static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8299{
8300 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8301
8302 drm_framebuffer_cleanup(fb);
8303 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8304
8305 kfree(intel_fb);
8306}
8307
8308static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8309 struct drm_file *file,
8310 unsigned int *handle)
8311{
8312 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8313 struct drm_i915_gem_object *obj = intel_fb->obj;
8314
8315 return drm_gem_handle_create(file, &obj->base, handle);
8316}
8317
8318static const struct drm_framebuffer_funcs intel_fb_funcs = {
8319 .destroy = intel_user_framebuffer_destroy,
8320 .create_handle = intel_user_framebuffer_create_handle,
8321};
8322
8323int intel_framebuffer_init(struct drm_device *dev,
8324 struct intel_framebuffer *intel_fb,
8325 struct drm_mode_fb_cmd2 *mode_cmd,
8326 struct drm_i915_gem_object *obj)
8327{
8328 int ret;
8329
8330 if (obj->tiling_mode == I915_TILING_Y)
8331 return -EINVAL;
8332
8333 if (mode_cmd->pitches[0] & 63)
8334 return -EINVAL;
8335
8336 /* FIXME <= Gen4 stride limits are bit unclear */
8337 if (mode_cmd->pitches[0] > 32768)
8338 return -EINVAL;
8339
8340 if (obj->tiling_mode != I915_TILING_NONE &&
8341 mode_cmd->pitches[0] != obj->stride)
8342 return -EINVAL;
8343
8344 /* Reject formats not supported by any plane early. */
8345 switch (mode_cmd->pixel_format) {
8346 case DRM_FORMAT_C8:
8347 case DRM_FORMAT_RGB565:
8348 case DRM_FORMAT_XRGB8888:
8349 case DRM_FORMAT_ARGB8888:
8350 break;
8351 case DRM_FORMAT_XRGB1555:
8352 case DRM_FORMAT_ARGB1555:
8353 if (INTEL_INFO(dev)->gen > 3)
8354 return -EINVAL;
8355 break;
8356 case DRM_FORMAT_XBGR8888:
8357 case DRM_FORMAT_ABGR8888:
8358 case DRM_FORMAT_XRGB2101010:
8359 case DRM_FORMAT_ARGB2101010:
8360 case DRM_FORMAT_XBGR2101010:
8361 case DRM_FORMAT_ABGR2101010:
8362 if (INTEL_INFO(dev)->gen < 4)
8363 return -EINVAL;
8364 break;
8365 case DRM_FORMAT_YUYV:
8366 case DRM_FORMAT_UYVY:
8367 case DRM_FORMAT_YVYU:
8368 case DRM_FORMAT_VYUY:
8369 if (INTEL_INFO(dev)->gen < 6)
8370 return -EINVAL;
8371 break;
8372 default:
8373 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8374 return -EINVAL;
8375 }
8376
8377 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8378 if (mode_cmd->offsets[0] != 0)
8379 return -EINVAL;
8380
8381 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8382 if (ret) {
8383 DRM_ERROR("framebuffer init failed %d\n", ret);
8384 return ret;
8385 }
8386
8387 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8388 intel_fb->obj = obj;
8389 return 0;
8390}
8391
8392static struct drm_framebuffer *
8393intel_user_framebuffer_create(struct drm_device *dev,
8394 struct drm_file *filp,
8395 struct drm_mode_fb_cmd2 *mode_cmd)
8396{
8397 struct drm_i915_gem_object *obj;
8398
8399 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8400 mode_cmd->handles[0]));
8401 if (&obj->base == NULL)
8402 return ERR_PTR(-ENOENT);
8403
8404 return intel_framebuffer_create(dev, mode_cmd, obj);
8405}
8406
8407static const struct drm_mode_config_funcs intel_mode_funcs = {
8408 .fb_create = intel_user_framebuffer_create,
8409 .output_poll_changed = intel_fb_output_poll_changed,
8410};
8411
8412/* Set up chip specific display functions */
8413static void intel_init_display(struct drm_device *dev)
8414{
8415 struct drm_i915_private *dev_priv = dev->dev_private;
8416
8417 /* We always want a DPMS function */
8418 if (HAS_DDI(dev)) {
8419 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8420 dev_priv->display.crtc_enable = haswell_crtc_enable;
8421 dev_priv->display.crtc_disable = haswell_crtc_disable;
8422 dev_priv->display.off = haswell_crtc_off;
8423 dev_priv->display.update_plane = ironlake_update_plane;
8424 } else if (HAS_PCH_SPLIT(dev)) {
8425 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8426 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8427 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8428 dev_priv->display.off = ironlake_crtc_off;
8429 dev_priv->display.update_plane = ironlake_update_plane;
8430 } else {
8431 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8432 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8433 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8434 dev_priv->display.off = i9xx_crtc_off;
8435 dev_priv->display.update_plane = i9xx_update_plane;
8436 }
8437
8438 /* Returns the core display clock speed */
8439 if (IS_VALLEYVIEW(dev))
8440 dev_priv->display.get_display_clock_speed =
8441 valleyview_get_display_clock_speed;
8442 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8443 dev_priv->display.get_display_clock_speed =
8444 i945_get_display_clock_speed;
8445 else if (IS_I915G(dev))
8446 dev_priv->display.get_display_clock_speed =
8447 i915_get_display_clock_speed;
8448 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8449 dev_priv->display.get_display_clock_speed =
8450 i9xx_misc_get_display_clock_speed;
8451 else if (IS_I915GM(dev))
8452 dev_priv->display.get_display_clock_speed =
8453 i915gm_get_display_clock_speed;
8454 else if (IS_I865G(dev))
8455 dev_priv->display.get_display_clock_speed =
8456 i865_get_display_clock_speed;
8457 else if (IS_I85X(dev))
8458 dev_priv->display.get_display_clock_speed =
8459 i855_get_display_clock_speed;
8460 else /* 852, 830 */
8461 dev_priv->display.get_display_clock_speed =
8462 i830_get_display_clock_speed;
8463
8464 if (HAS_PCH_SPLIT(dev)) {
8465 if (IS_GEN5(dev)) {
8466 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8467 dev_priv->display.write_eld = ironlake_write_eld;
8468 } else if (IS_GEN6(dev)) {
8469 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8470 dev_priv->display.write_eld = ironlake_write_eld;
8471 } else if (IS_IVYBRIDGE(dev)) {
8472 /* FIXME: detect B0+ stepping and use auto training */
8473 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8474 dev_priv->display.write_eld = ironlake_write_eld;
8475 dev_priv->display.modeset_global_resources =
8476 ivb_modeset_global_resources;
8477 } else if (IS_HASWELL(dev)) {
8478 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8479 dev_priv->display.write_eld = haswell_write_eld;
8480 }
8481 } else if (IS_G4X(dev)) {
8482 dev_priv->display.write_eld = g4x_write_eld;
8483 }
8484
8485 /* Default just returns -ENODEV to indicate unsupported */
8486 dev_priv->display.queue_flip = intel_default_queue_flip;
8487
8488 switch (INTEL_INFO(dev)->gen) {
8489 case 2:
8490 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8491 break;
8492
8493 case 3:
8494 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8495 break;
8496
8497 case 4:
8498 case 5:
8499 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8500 break;
8501
8502 case 6:
8503 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8504 break;
8505 case 7:
8506 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8507 break;
8508 }
8509}
8510
8511/*
8512 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8513 * resume, or other times. This quirk makes sure that's the case for
8514 * affected systems.
8515 */
8516static void quirk_pipea_force(struct drm_device *dev)
8517{
8518 struct drm_i915_private *dev_priv = dev->dev_private;
8519
8520 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8521 DRM_INFO("applying pipe a force quirk\n");
8522}
8523
8524/*
8525 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8526 */
8527static void quirk_ssc_force_disable(struct drm_device *dev)
8528{
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8531 DRM_INFO("applying lvds SSC disable quirk\n");
8532}
8533
8534/*
8535 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8536 * brightness value
8537 */
8538static void quirk_invert_brightness(struct drm_device *dev)
8539{
8540 struct drm_i915_private *dev_priv = dev->dev_private;
8541 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8542 DRM_INFO("applying inverted panel brightness quirk\n");
8543}
8544
8545struct intel_quirk {
8546 int device;
8547 int subsystem_vendor;
8548 int subsystem_device;
8549 void (*hook)(struct drm_device *dev);
8550};
8551
8552/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8553struct intel_dmi_quirk {
8554 void (*hook)(struct drm_device *dev);
8555 const struct dmi_system_id (*dmi_id_list)[];
8556};
8557
8558static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8559{
8560 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8561 return 1;
8562}
8563
8564static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8565 {
8566 .dmi_id_list = &(const struct dmi_system_id[]) {
8567 {
8568 .callback = intel_dmi_reverse_brightness,
8569 .ident = "NCR Corporation",
8570 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8571 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8572 },
8573 },
8574 { } /* terminating entry */
8575 },
8576 .hook = quirk_invert_brightness,
8577 },
8578};
8579
8580static struct intel_quirk intel_quirks[] = {
8581 /* HP Mini needs pipe A force quirk (LP: #322104) */
8582 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8583
8584 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8585 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8586
8587 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8588 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8589
8590 /* 830/845 need to leave pipe A & dpll A up */
8591 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8592 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8593
8594 /* Lenovo U160 cannot use SSC on LVDS */
8595 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8596
8597 /* Sony Vaio Y cannot use SSC on LVDS */
8598 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8599
8600 /* Acer Aspire 5734Z must invert backlight brightness */
8601 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8602};
8603
8604static void intel_init_quirks(struct drm_device *dev)
8605{
8606 struct pci_dev *d = dev->pdev;
8607 int i;
8608
8609 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8610 struct intel_quirk *q = &intel_quirks[i];
8611
8612 if (d->device == q->device &&
8613 (d->subsystem_vendor == q->subsystem_vendor ||
8614 q->subsystem_vendor == PCI_ANY_ID) &&
8615 (d->subsystem_device == q->subsystem_device ||
8616 q->subsystem_device == PCI_ANY_ID))
8617 q->hook(dev);
8618 }
8619 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8620 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8621 intel_dmi_quirks[i].hook(dev);
8622 }
8623}
8624
8625/* Disable the VGA plane that we never use */
8626static void i915_disable_vga(struct drm_device *dev)
8627{
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629 u8 sr1;
8630 u32 vga_reg;
8631
8632 if (HAS_PCH_SPLIT(dev))
8633 vga_reg = CPU_VGACNTRL;
8634 else
8635 vga_reg = VGACNTRL;
8636
8637 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8638 outb(SR01, VGA_SR_INDEX);
8639 sr1 = inb(VGA_SR_DATA);
8640 outb(sr1 | 1<<5, VGA_SR_DATA);
8641 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8642 udelay(300);
8643
8644 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8645 POSTING_READ(vga_reg);
8646}
8647
8648void intel_modeset_init_hw(struct drm_device *dev)
8649{
8650 /* We attempt to init the necessary power wells early in the initialization
8651 * time, so the subsystems that expect power to be enabled can work.
8652 */
8653 intel_init_power_wells(dev);
8654
8655 intel_prepare_ddi(dev);
8656
8657 intel_init_clock_gating(dev);
8658
8659 mutex_lock(&dev->struct_mutex);
8660 intel_enable_gt_powersave(dev);
8661 mutex_unlock(&dev->struct_mutex);
8662}
8663
8664void intel_modeset_init(struct drm_device *dev)
8665{
8666 struct drm_i915_private *dev_priv = dev->dev_private;
8667 int i, ret;
8668
8669 drm_mode_config_init(dev);
8670
8671 dev->mode_config.min_width = 0;
8672 dev->mode_config.min_height = 0;
8673
8674 dev->mode_config.preferred_depth = 24;
8675 dev->mode_config.prefer_shadow = 1;
8676
8677 dev->mode_config.funcs = &intel_mode_funcs;
8678
8679 intel_init_quirks(dev);
8680
8681 intel_init_pm(dev);
8682
8683 intel_init_display(dev);
8684
8685 if (IS_GEN2(dev)) {
8686 dev->mode_config.max_width = 2048;
8687 dev->mode_config.max_height = 2048;
8688 } else if (IS_GEN3(dev)) {
8689 dev->mode_config.max_width = 4096;
8690 dev->mode_config.max_height = 4096;
8691 } else {
8692 dev->mode_config.max_width = 8192;
8693 dev->mode_config.max_height = 8192;
8694 }
8695 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8696
8697 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8698 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8699
8700 for (i = 0; i < dev_priv->num_pipe; i++) {
8701 intel_crtc_init(dev, i);
8702 ret = intel_plane_init(dev, i);
8703 if (ret)
8704 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8705 }
8706
8707 intel_cpu_pll_init(dev);
8708 intel_pch_pll_init(dev);
8709
8710 /* Just disable it once at startup */
8711 i915_disable_vga(dev);
8712 intel_setup_outputs(dev);
8713
8714 /* Just in case the BIOS is doing something questionable. */
8715 intel_disable_fbc(dev);
8716}
8717
8718static void
8719intel_connector_break_all_links(struct intel_connector *connector)
8720{
8721 connector->base.dpms = DRM_MODE_DPMS_OFF;
8722 connector->base.encoder = NULL;
8723 connector->encoder->connectors_active = false;
8724 connector->encoder->base.crtc = NULL;
8725}
8726
8727static void intel_enable_pipe_a(struct drm_device *dev)
8728{
8729 struct intel_connector *connector;
8730 struct drm_connector *crt = NULL;
8731 struct intel_load_detect_pipe load_detect_temp;
8732
8733 /* We can't just switch on the pipe A, we need to set things up with a
8734 * proper mode and output configuration. As a gross hack, enable pipe A
8735 * by enabling the load detect pipe once. */
8736 list_for_each_entry(connector,
8737 &dev->mode_config.connector_list,
8738 base.head) {
8739 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8740 crt = &connector->base;
8741 break;
8742 }
8743 }
8744
8745 if (!crt)
8746 return;
8747
8748 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8749 intel_release_load_detect_pipe(crt, &load_detect_temp);
8750
8751
8752}
8753
8754static bool
8755intel_check_plane_mapping(struct intel_crtc *crtc)
8756{
8757 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8758 u32 reg, val;
8759
8760 if (dev_priv->num_pipe == 1)
8761 return true;
8762
8763 reg = DSPCNTR(!crtc->plane);
8764 val = I915_READ(reg);
8765
8766 if ((val & DISPLAY_PLANE_ENABLE) &&
8767 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8768 return false;
8769
8770 return true;
8771}
8772
8773static void intel_sanitize_crtc(struct intel_crtc *crtc)
8774{
8775 struct drm_device *dev = crtc->base.dev;
8776 struct drm_i915_private *dev_priv = dev->dev_private;
8777 u32 reg;
8778
8779 /* Clear any frame start delays used for debugging left by the BIOS */
8780 reg = PIPECONF(crtc->cpu_transcoder);
8781 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8782
8783 /* We need to sanitize the plane -> pipe mapping first because this will
8784 * disable the crtc (and hence change the state) if it is wrong. Note
8785 * that gen4+ has a fixed plane -> pipe mapping. */
8786 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8787 struct intel_connector *connector;
8788 bool plane;
8789
8790 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8791 crtc->base.base.id);
8792
8793 /* Pipe has the wrong plane attached and the plane is active.
8794 * Temporarily change the plane mapping and disable everything
8795 * ... */
8796 plane = crtc->plane;
8797 crtc->plane = !plane;
8798 dev_priv->display.crtc_disable(&crtc->base);
8799 crtc->plane = plane;
8800
8801 /* ... and break all links. */
8802 list_for_each_entry(connector, &dev->mode_config.connector_list,
8803 base.head) {
8804 if (connector->encoder->base.crtc != &crtc->base)
8805 continue;
8806
8807 intel_connector_break_all_links(connector);
8808 }
8809
8810 WARN_ON(crtc->active);
8811 crtc->base.enabled = false;
8812 }
8813
8814 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8815 crtc->pipe == PIPE_A && !crtc->active) {
8816 /* BIOS forgot to enable pipe A, this mostly happens after
8817 * resume. Force-enable the pipe to fix this, the update_dpms
8818 * call below we restore the pipe to the right state, but leave
8819 * the required bits on. */
8820 intel_enable_pipe_a(dev);
8821 }
8822
8823 /* Adjust the state of the output pipe according to whether we
8824 * have active connectors/encoders. */
8825 intel_crtc_update_dpms(&crtc->base);
8826
8827 if (crtc->active != crtc->base.enabled) {
8828 struct intel_encoder *encoder;
8829
8830 /* This can happen either due to bugs in the get_hw_state
8831 * functions or because the pipe is force-enabled due to the
8832 * pipe A quirk. */
8833 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8834 crtc->base.base.id,
8835 crtc->base.enabled ? "enabled" : "disabled",
8836 crtc->active ? "enabled" : "disabled");
8837
8838 crtc->base.enabled = crtc->active;
8839
8840 /* Because we only establish the connector -> encoder ->
8841 * crtc links if something is active, this means the
8842 * crtc is now deactivated. Break the links. connector
8843 * -> encoder links are only establish when things are
8844 * actually up, hence no need to break them. */
8845 WARN_ON(crtc->active);
8846
8847 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8848 WARN_ON(encoder->connectors_active);
8849 encoder->base.crtc = NULL;
8850 }
8851 }
8852}
8853
8854static void intel_sanitize_encoder(struct intel_encoder *encoder)
8855{
8856 struct intel_connector *connector;
8857 struct drm_device *dev = encoder->base.dev;
8858
8859 /* We need to check both for a crtc link (meaning that the
8860 * encoder is active and trying to read from a pipe) and the
8861 * pipe itself being active. */
8862 bool has_active_crtc = encoder->base.crtc &&
8863 to_intel_crtc(encoder->base.crtc)->active;
8864
8865 if (encoder->connectors_active && !has_active_crtc) {
8866 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8867 encoder->base.base.id,
8868 drm_get_encoder_name(&encoder->base));
8869
8870 /* Connector is active, but has no active pipe. This is
8871 * fallout from our resume register restoring. Disable
8872 * the encoder manually again. */
8873 if (encoder->base.crtc) {
8874 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8875 encoder->base.base.id,
8876 drm_get_encoder_name(&encoder->base));
8877 encoder->disable(encoder);
8878 }
8879
8880 /* Inconsistent output/port/pipe state happens presumably due to
8881 * a bug in one of the get_hw_state functions. Or someplace else
8882 * in our code, like the register restore mess on resume. Clamp
8883 * things to off as a safer default. */
8884 list_for_each_entry(connector,
8885 &dev->mode_config.connector_list,
8886 base.head) {
8887 if (connector->encoder != encoder)
8888 continue;
8889
8890 intel_connector_break_all_links(connector);
8891 }
8892 }
8893 /* Enabled encoders without active connectors will be fixed in
8894 * the crtc fixup. */
8895}
8896
8897static void i915_redisable_vga(struct drm_device *dev)
8898{
8899 struct drm_i915_private *dev_priv = dev->dev_private;
8900 u32 vga_reg;
8901
8902 if (HAS_PCH_SPLIT(dev))
8903 vga_reg = CPU_VGACNTRL;
8904 else
8905 vga_reg = VGACNTRL;
8906
8907 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8908 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8909 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8910 POSTING_READ(vga_reg);
8911 }
8912}
8913
8914/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8915 * and i915 state tracking structures. */
8916void intel_modeset_setup_hw_state(struct drm_device *dev,
8917 bool force_restore)
8918{
8919 struct drm_i915_private *dev_priv = dev->dev_private;
8920 enum pipe pipe;
8921 u32 tmp;
8922 struct intel_crtc *crtc;
8923 struct intel_encoder *encoder;
8924 struct intel_connector *connector;
8925
8926 if (HAS_DDI(dev)) {
8927 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8928
8929 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8930 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8931 case TRANS_DDI_EDP_INPUT_A_ON:
8932 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8933 pipe = PIPE_A;
8934 break;
8935 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8936 pipe = PIPE_B;
8937 break;
8938 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8939 pipe = PIPE_C;
8940 break;
8941 }
8942
8943 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8944 crtc->cpu_transcoder = TRANSCODER_EDP;
8945
8946 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8947 pipe_name(pipe));
8948 }
8949 }
8950
8951 for_each_pipe(pipe) {
8952 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8953
8954 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8955 if (tmp & PIPECONF_ENABLE)
8956 crtc->active = true;
8957 else
8958 crtc->active = false;
8959
8960 crtc->base.enabled = crtc->active;
8961
8962 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8963 crtc->base.base.id,
8964 crtc->active ? "enabled" : "disabled");
8965 }
8966
8967 if (HAS_DDI(dev))
8968 intel_ddi_setup_hw_pll_state(dev);
8969
8970 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8971 base.head) {
8972 pipe = 0;
8973
8974 if (encoder->get_hw_state(encoder, &pipe)) {
8975 encoder->base.crtc =
8976 dev_priv->pipe_to_crtc_mapping[pipe];
8977 } else {
8978 encoder->base.crtc = NULL;
8979 }
8980
8981 encoder->connectors_active = false;
8982 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8983 encoder->base.base.id,
8984 drm_get_encoder_name(&encoder->base),
8985 encoder->base.crtc ? "enabled" : "disabled",
8986 pipe);
8987 }
8988
8989 list_for_each_entry(connector, &dev->mode_config.connector_list,
8990 base.head) {
8991 if (connector->get_hw_state(connector)) {
8992 connector->base.dpms = DRM_MODE_DPMS_ON;
8993 connector->encoder->connectors_active = true;
8994 connector->base.encoder = &connector->encoder->base;
8995 } else {
8996 connector->base.dpms = DRM_MODE_DPMS_OFF;
8997 connector->base.encoder = NULL;
8998 }
8999 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9000 connector->base.base.id,
9001 drm_get_connector_name(&connector->base),
9002 connector->base.encoder ? "enabled" : "disabled");
9003 }
9004
9005 /* HW state is read out, now we need to sanitize this mess. */
9006 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9007 base.head) {
9008 intel_sanitize_encoder(encoder);
9009 }
9010
9011 for_each_pipe(pipe) {
9012 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9013 intel_sanitize_crtc(crtc);
9014 }
9015
9016 if (force_restore) {
9017 for_each_pipe(pipe) {
9018 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9019 }
9020
9021 i915_redisable_vga(dev);
9022 } else {
9023 intel_modeset_update_staged_output_state(dev);
9024 }
9025
9026 intel_modeset_check_state(dev);
9027
9028 drm_mode_config_reset(dev);
9029}
9030
9031void intel_modeset_gem_init(struct drm_device *dev)
9032{
9033 intel_modeset_init_hw(dev);
9034
9035 intel_setup_overlay(dev);
9036
9037 intel_modeset_setup_hw_state(dev, false);
9038}
9039
9040void intel_modeset_cleanup(struct drm_device *dev)
9041{
9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043 struct drm_crtc *crtc;
9044 struct intel_crtc *intel_crtc;
9045
9046 drm_kms_helper_poll_fini(dev);
9047 mutex_lock(&dev->struct_mutex);
9048
9049 intel_unregister_dsm_handler();
9050
9051
9052 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9053 /* Skip inactive CRTCs */
9054 if (!crtc->fb)
9055 continue;
9056
9057 intel_crtc = to_intel_crtc(crtc);
9058 intel_increase_pllclock(crtc);
9059 }
9060
9061 intel_disable_fbc(dev);
9062
9063 intel_disable_gt_powersave(dev);
9064
9065 ironlake_teardown_rc6(dev);
9066
9067 if (IS_VALLEYVIEW(dev))
9068 vlv_init_dpio(dev);
9069
9070 mutex_unlock(&dev->struct_mutex);
9071
9072 /* Disable the irq before mode object teardown, for the irq might
9073 * enqueue unpin/hotplug work. */
9074 drm_irq_uninstall(dev);
9075 cancel_work_sync(&dev_priv->hotplug_work);
9076 cancel_work_sync(&dev_priv->rps.work);
9077
9078 /* flush any delayed tasks or pending work */
9079 flush_scheduled_work();
9080
9081 drm_mode_config_cleanup(dev);
9082
9083 intel_cleanup_overlay(dev);
9084}
9085
9086/*
9087 * Return which encoder is currently attached for connector.
9088 */
9089struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9090{
9091 return &intel_attached_encoder(connector)->base;
9092}
9093
9094void intel_connector_attach_encoder(struct intel_connector *connector,
9095 struct intel_encoder *encoder)
9096{
9097 connector->encoder = encoder;
9098 drm_mode_connector_attach_encoder(&connector->base,
9099 &encoder->base);
9100}
9101
9102/*
9103 * set vga decode state - true == enable VGA decode
9104 */
9105int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9106{
9107 struct drm_i915_private *dev_priv = dev->dev_private;
9108 u16 gmch_ctrl;
9109
9110 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9111 if (state)
9112 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9113 else
9114 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9115 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9116 return 0;
9117}
9118
9119#ifdef CONFIG_DEBUG_FS
9120#include <linux/seq_file.h>
9121
9122struct intel_display_error_state {
9123 struct intel_cursor_error_state {
9124 u32 control;
9125 u32 position;
9126 u32 base;
9127 u32 size;
9128 } cursor[I915_MAX_PIPES];
9129
9130 struct intel_pipe_error_state {
9131 u32 conf;
9132 u32 source;
9133
9134 u32 htotal;
9135 u32 hblank;
9136 u32 hsync;
9137 u32 vtotal;
9138 u32 vblank;
9139 u32 vsync;
9140 } pipe[I915_MAX_PIPES];
9141
9142 struct intel_plane_error_state {
9143 u32 control;
9144 u32 stride;
9145 u32 size;
9146 u32 pos;
9147 u32 addr;
9148 u32 surface;
9149 u32 tile_offset;
9150 } plane[I915_MAX_PIPES];
9151};
9152
9153struct intel_display_error_state *
9154intel_display_capture_error_state(struct drm_device *dev)
9155{
9156 drm_i915_private_t *dev_priv = dev->dev_private;
9157 struct intel_display_error_state *error;
9158 enum transcoder cpu_transcoder;
9159 int i;
9160
9161 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9162 if (error == NULL)
9163 return NULL;
9164
9165 for_each_pipe(i) {
9166 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9167
9168 error->cursor[i].control = I915_READ(CURCNTR(i));
9169 error->cursor[i].position = I915_READ(CURPOS(i));
9170 error->cursor[i].base = I915_READ(CURBASE(i));
9171
9172 error->plane[i].control = I915_READ(DSPCNTR(i));
9173 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9174 error->plane[i].size = I915_READ(DSPSIZE(i));
9175 error->plane[i].pos = I915_READ(DSPPOS(i));
9176 error->plane[i].addr = I915_READ(DSPADDR(i));
9177 if (INTEL_INFO(dev)->gen >= 4) {
9178 error->plane[i].surface = I915_READ(DSPSURF(i));
9179 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9180 }
9181
9182 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9183 error->pipe[i].source = I915_READ(PIPESRC(i));
9184 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9185 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9186 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9187 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9188 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9189 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9190 }
9191
9192 return error;
9193}
9194
9195void
9196intel_display_print_error_state(struct seq_file *m,
9197 struct drm_device *dev,
9198 struct intel_display_error_state *error)
9199{
9200 drm_i915_private_t *dev_priv = dev->dev_private;
9201 int i;
9202
9203 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9204 for_each_pipe(i) {
9205 seq_printf(m, "Pipe [%d]:\n", i);
9206 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9207 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9208 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9209 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9210 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9211 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9212 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9213 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9214
9215 seq_printf(m, "Plane [%d]:\n", i);
9216 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9217 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9218 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9219 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9220 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9221 if (INTEL_INFO(dev)->gen >= 4) {
9222 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9223 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9224 }
9225
9226 seq_printf(m, "Cursor [%d]:\n", i);
9227 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9228 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9229 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9230 }
9231}
9232#endif
Linux kernel - Deliverables
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