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drm/i915: Exit early from psr_status if PSR is not supported by the device
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_atomic_helper.h>
41#include <drm/drm_dp_helper.h>
42#include <drm/drm_crtc_helper.h>
43#include <drm/drm_plane_helper.h>
44#include <drm/drm_rect.h>
45#include <linux/dma_remapping.h>
46
47/* Primary plane formats supported by all gen */
48#define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54/* Primary plane formats for gen <= 3 */
55static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59};
60
61/* Primary plane formats for gen >= 4 */
62static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70};
71
72/* Cursor formats */
73static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75};
76
77static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96static void haswell_set_pipeconf(struct drm_crtc *crtc);
97static void intel_set_pipe_csc(struct drm_crtc *crtc);
98static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106{
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111}
112
113typedef struct {
114 int min, max;
115} intel_range_t;
116
117typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120} intel_p2_t;
121
122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126};
127
128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146}
147
148static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159};
160
161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
174static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185};
186
187static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211};
212
213
214static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268};
269
270static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283};
284
285static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296};
297
298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314};
315
316static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340};
341
342/* LVDS 100mhz refclk limits. */
343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367};
368
369static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383};
384
385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
401static void vlv_clock(int refclk, intel_clock_t *clock)
402{
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409}
410
411/**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415{
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424}
425
426/**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433{
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442}
443
444static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446{
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466}
467
468static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469{
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487}
488
489static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490{
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521}
522
523/* m1 is reserved as 0 in Pineview, n is a ring counter */
524static void pineview_clock(int refclk, intel_clock_t *clock)
525{
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532}
533
534static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535{
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537}
538
539static void i9xx_clock(int refclk, intel_clock_t *clock)
540{
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547}
548
549static void chv_clock(int refclk, intel_clock_t *clock)
550{
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558}
559
560#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561/**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569{
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599}
600
601static bool
602i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605{
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660}
661
662static bool
663pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666{
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719}
720
721static bool
722g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725{
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776}
777
778static bool
779vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782{
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833}
834
835static bool
836chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839{
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885}
886
887bool intel_crtc_active(struct drm_crtc *crtc)
888{
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902}
903
904enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906{
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911}
912
913static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914{
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930}
931
932/*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949{
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967}
968
969/*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978{
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012}
1013
1014static const char *state_string(bool enabled)
1015{
1016 return enabled ? "on" : "off";
1017}
1018
1019/* Only for pre-ILK configs */
1020void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022{
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033}
1034
1035/* XXX: the dsi pll is shared between MIPI DSI ports */
1036static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037{
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049}
1050#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053struct intel_shared_dpll *
1054intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055{
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062}
1063
1064/* For ILK+ */
1065void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068{
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080}
1081
1082static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084{
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104}
1105#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110{
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121}
1122#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142}
1143
1144void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146{
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157}
1158
1159void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161{
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199}
1200
1201static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203{
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215}
1216#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221{
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245}
1246
1247static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249{
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260}
1261
1262#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293}
1294
1295static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297{
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(dev_priv, pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(dev_priv, pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330}
1331
1332static void assert_vblank_disabled(struct drm_crtc *crtc)
1333{
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336}
1337
1338static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339{
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349}
1350
1351static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353{
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364}
1365
1366static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368{
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385}
1386
1387static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389{
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
1406static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408{
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420}
1421
1422static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424{
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435}
1436
1437static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439{
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448}
1449
1450static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452{
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461}
1462
1463static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465{
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488}
1489
1490static void intel_init_dpio(struct drm_device *dev)
1491{
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508}
1509
1510static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512{
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547}
1548
1549static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551{
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586}
1587
1588static int intel_num_dvo_pipes(struct drm_device *dev)
1589{
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598}
1599
1600static void i9xx_enable_pll(struct intel_crtc *crtc)
1601{
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655}
1656
1657/**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666static void i9xx_disable_pll(struct intel_crtc *crtc)
1667{
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692}
1693
1694static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695{
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710}
1711
1712static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713{
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746}
1747
1748void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750{
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774}
1775
1776static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777{
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793}
1794
1795/**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804{
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831}
1832
1833static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834{
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866}
1867
1868static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870{
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922}
1923
1924static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926{
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953}
1954
1955static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957{
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983}
1984
1985static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986{
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000}
2001
2002/**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009static void intel_enable_pipe(struct intel_crtc *crtc)
2010{
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059}
2060
2061/**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071static void intel_disable_pipe(struct intel_crtc *crtc)
2072{
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107}
2108
2109/*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115{
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121}
2122
2123/**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132{
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155}
2156
2157/**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166{
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181}
2182
2183static bool need_vtd_wa(struct drm_device *dev)
2184{
2185#ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188#endif
2189 return false;
2190}
2191
2192int
2193intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2196{
2197 int tile_height;
2198 uint32_t bits_per_pixel;
2199
2200 switch (fb_format_modifier) {
2201 case DRM_FORMAT_MOD_NONE:
2202 tile_height = 1;
2203 break;
2204 case I915_FORMAT_MOD_X_TILED:
2205 tile_height = IS_GEN2(dev) ? 16 : 8;
2206 break;
2207 case I915_FORMAT_MOD_Y_TILED:
2208 tile_height = 32;
2209 break;
2210 case I915_FORMAT_MOD_Yf_TILED:
2211 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2212 switch (bits_per_pixel) {
2213 default:
2214 case 8:
2215 tile_height = 64;
2216 break;
2217 case 16:
2218 case 32:
2219 tile_height = 32;
2220 break;
2221 case 64:
2222 tile_height = 16;
2223 break;
2224 case 128:
2225 WARN_ONCE(1,
2226 "128-bit pixels are not supported for display!");
2227 tile_height = 16;
2228 break;
2229 }
2230 break;
2231 default:
2232 MISSING_CASE(fb_format_modifier);
2233 tile_height = 1;
2234 break;
2235 }
2236
2237 return ALIGN(height, tile_height);
2238}
2239
2240int
2241intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2242 struct drm_framebuffer *fb,
2243 struct intel_engine_cs *pipelined)
2244{
2245 struct drm_device *dev = fb->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 u32 alignment;
2249 int ret;
2250
2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2252
2253 switch (fb->modifier[0]) {
2254 case DRM_FORMAT_MOD_NONE:
2255 if (INTEL_INFO(dev)->gen >= 9)
2256 alignment = 256 * 1024;
2257 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2258 alignment = 128 * 1024;
2259 else if (INTEL_INFO(dev)->gen >= 4)
2260 alignment = 4 * 1024;
2261 else
2262 alignment = 64 * 1024;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 if (INTEL_INFO(dev)->gen >= 9)
2266 alignment = 256 * 1024;
2267 else {
2268 /* pin() will align the object as required by fence */
2269 alignment = 0;
2270 }
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 case I915_FORMAT_MOD_Yf_TILED:
2274 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2275 "Y tiling bo slipped through, driver bug!\n"))
2276 return -EINVAL;
2277 alignment = 1 * 1024 * 1024;
2278 break;
2279 default:
2280 MISSING_CASE(fb->modifier[0]);
2281 return -EINVAL;
2282 }
2283
2284 /* Note that the w/a also requires 64 PTE of padding following the
2285 * bo. We currently fill all unused PTE with the shadow page and so
2286 * we should always have valid PTE following the scanout preventing
2287 * the VT-d warning.
2288 */
2289 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2290 alignment = 256 * 1024;
2291
2292 /*
2293 * Global gtt pte registers are special registers which actually forward
2294 * writes to a chunk of system memory. Which means that there is no risk
2295 * that the register values disappear as soon as we call
2296 * intel_runtime_pm_put(), so it is correct to wrap only the
2297 * pin/unpin/fence and not more.
2298 */
2299 intel_runtime_pm_get(dev_priv);
2300
2301 dev_priv->mm.interruptible = false;
2302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2303 if (ret)
2304 goto err_interruptible;
2305
2306 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307 * fence, whereas 965+ only requires a fence if using
2308 * framebuffer compression. For simplicity, we always install
2309 * a fence as the cost is not that onerous.
2310 */
2311 ret = i915_gem_object_get_fence(obj);
2312 if (ret)
2313 goto err_unpin;
2314
2315 i915_gem_object_pin_fence(obj);
2316
2317 dev_priv->mm.interruptible = true;
2318 intel_runtime_pm_put(dev_priv);
2319 return 0;
2320
2321err_unpin:
2322 i915_gem_object_unpin_from_display_plane(obj);
2323err_interruptible:
2324 dev_priv->mm.interruptible = true;
2325 intel_runtime_pm_put(dev_priv);
2326 return ret;
2327}
2328
2329static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2330{
2331 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2332
2333 i915_gem_object_unpin_fence(obj);
2334 i915_gem_object_unpin_from_display_plane(obj);
2335}
2336
2337/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338 * is assumed to be a power-of-two. */
2339unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2340 unsigned int tiling_mode,
2341 unsigned int cpp,
2342 unsigned int pitch)
2343{
2344 if (tiling_mode != I915_TILING_NONE) {
2345 unsigned int tile_rows, tiles;
2346
2347 tile_rows = *y / 8;
2348 *y %= 8;
2349
2350 tiles = *x / (512/cpp);
2351 *x %= 512/cpp;
2352
2353 return tile_rows * pitch * 8 + tiles * 4096;
2354 } else {
2355 unsigned int offset;
2356
2357 offset = *y * pitch + *x * cpp;
2358 *y = 0;
2359 *x = (offset & 4095) / cpp;
2360 return offset & -4096;
2361 }
2362}
2363
2364static int i9xx_format_to_fourcc(int format)
2365{
2366 switch (format) {
2367 case DISPPLANE_8BPP:
2368 return DRM_FORMAT_C8;
2369 case DISPPLANE_BGRX555:
2370 return DRM_FORMAT_XRGB1555;
2371 case DISPPLANE_BGRX565:
2372 return DRM_FORMAT_RGB565;
2373 default:
2374 case DISPPLANE_BGRX888:
2375 return DRM_FORMAT_XRGB8888;
2376 case DISPPLANE_RGBX888:
2377 return DRM_FORMAT_XBGR8888;
2378 case DISPPLANE_BGRX101010:
2379 return DRM_FORMAT_XRGB2101010;
2380 case DISPPLANE_RGBX101010:
2381 return DRM_FORMAT_XBGR2101010;
2382 }
2383}
2384
2385static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2386{
2387 switch (format) {
2388 case PLANE_CTL_FORMAT_RGB_565:
2389 return DRM_FORMAT_RGB565;
2390 default:
2391 case PLANE_CTL_FORMAT_XRGB_8888:
2392 if (rgb_order) {
2393 if (alpha)
2394 return DRM_FORMAT_ABGR8888;
2395 else
2396 return DRM_FORMAT_XBGR8888;
2397 } else {
2398 if (alpha)
2399 return DRM_FORMAT_ARGB8888;
2400 else
2401 return DRM_FORMAT_XRGB8888;
2402 }
2403 case PLANE_CTL_FORMAT_XRGB_2101010:
2404 if (rgb_order)
2405 return DRM_FORMAT_XBGR2101010;
2406 else
2407 return DRM_FORMAT_XRGB2101010;
2408 }
2409}
2410
2411static bool
2412intel_alloc_plane_obj(struct intel_crtc *crtc,
2413 struct intel_initial_plane_config *plane_config)
2414{
2415 struct drm_device *dev = crtc->base.dev;
2416 struct drm_i915_gem_object *obj = NULL;
2417 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2418 struct drm_framebuffer *fb = &plane_config->fb->base;
2419 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2420 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2421 PAGE_SIZE);
2422
2423 size_aligned -= base_aligned;
2424
2425 if (plane_config->size == 0)
2426 return false;
2427
2428 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2429 base_aligned,
2430 base_aligned,
2431 size_aligned);
2432 if (!obj)
2433 return false;
2434
2435 obj->tiling_mode = plane_config->tiling;
2436 if (obj->tiling_mode == I915_TILING_X)
2437 obj->stride = fb->pitches[0];
2438
2439 mode_cmd.pixel_format = fb->pixel_format;
2440 mode_cmd.width = fb->width;
2441 mode_cmd.height = fb->height;
2442 mode_cmd.pitches[0] = fb->pitches[0];
2443 mode_cmd.modifier[0] = fb->modifier[0];
2444 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2445
2446 mutex_lock(&dev->struct_mutex);
2447
2448 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2449 &mode_cmd, obj)) {
2450 DRM_DEBUG_KMS("intel fb init failed\n");
2451 goto out_unref_obj;
2452 }
2453
2454 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2455 mutex_unlock(&dev->struct_mutex);
2456
2457 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2458 return true;
2459
2460out_unref_obj:
2461 drm_gem_object_unreference(&obj->base);
2462 mutex_unlock(&dev->struct_mutex);
2463 return false;
2464}
2465
2466/* Update plane->state->fb to match plane->fb after driver-internal updates */
2467static void
2468update_state_fb(struct drm_plane *plane)
2469{
2470 if (plane->fb == plane->state->fb)
2471 return;
2472
2473 if (plane->state->fb)
2474 drm_framebuffer_unreference(plane->state->fb);
2475 plane->state->fb = plane->fb;
2476 if (plane->state->fb)
2477 drm_framebuffer_reference(plane->state->fb);
2478}
2479
2480static void
2481intel_find_plane_obj(struct intel_crtc *intel_crtc,
2482 struct intel_initial_plane_config *plane_config)
2483{
2484 struct drm_device *dev = intel_crtc->base.dev;
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct drm_crtc *c;
2487 struct intel_crtc *i;
2488 struct drm_i915_gem_object *obj;
2489
2490 if (!plane_config->fb)
2491 return;
2492
2493 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2494 struct drm_plane *primary = intel_crtc->base.primary;
2495
2496 primary->fb = &plane_config->fb->base;
2497 primary->state->crtc = &intel_crtc->base;
2498 update_state_fb(primary);
2499
2500 return;
2501 }
2502
2503 kfree(plane_config->fb);
2504
2505 /*
2506 * Failed to alloc the obj, check to see if we should share
2507 * an fb with another CRTC instead
2508 */
2509 for_each_crtc(dev, c) {
2510 i = to_intel_crtc(c);
2511
2512 if (c == &intel_crtc->base)
2513 continue;
2514
2515 if (!i->active)
2516 continue;
2517
2518 obj = intel_fb_obj(c->primary->fb);
2519 if (obj == NULL)
2520 continue;
2521
2522 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2523 struct drm_plane *primary = intel_crtc->base.primary;
2524
2525 if (obj->tiling_mode != I915_TILING_NONE)
2526 dev_priv->preserve_bios_swizzle = true;
2527
2528 drm_framebuffer_reference(c->primary->fb);
2529 primary->fb = c->primary->fb;
2530 primary->state->crtc = &intel_crtc->base;
2531 update_state_fb(intel_crtc->base.primary);
2532 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2533 break;
2534 }
2535 }
2536
2537}
2538
2539static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2540 struct drm_framebuffer *fb,
2541 int x, int y)
2542{
2543 struct drm_device *dev = crtc->dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2546 struct drm_i915_gem_object *obj;
2547 int plane = intel_crtc->plane;
2548 unsigned long linear_offset;
2549 u32 dspcntr;
2550 u32 reg = DSPCNTR(plane);
2551 int pixel_size;
2552
2553 if (!intel_crtc->primary_enabled) {
2554 I915_WRITE(reg, 0);
2555 if (INTEL_INFO(dev)->gen >= 4)
2556 I915_WRITE(DSPSURF(plane), 0);
2557 else
2558 I915_WRITE(DSPADDR(plane), 0);
2559 POSTING_READ(reg);
2560 return;
2561 }
2562
2563 obj = intel_fb_obj(fb);
2564 if (WARN_ON(obj == NULL))
2565 return;
2566
2567 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2568
2569 dspcntr = DISPPLANE_GAMMA_ENABLE;
2570
2571 dspcntr |= DISPLAY_PLANE_ENABLE;
2572
2573 if (INTEL_INFO(dev)->gen < 4) {
2574 if (intel_crtc->pipe == PIPE_B)
2575 dspcntr |= DISPPLANE_SEL_PIPE_B;
2576
2577 /* pipesrc and dspsize control the size that is scaled from,
2578 * which should always be the user's requested size.
2579 */
2580 I915_WRITE(DSPSIZE(plane),
2581 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2582 (intel_crtc->config->pipe_src_w - 1));
2583 I915_WRITE(DSPPOS(plane), 0);
2584 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2585 I915_WRITE(PRIMSIZE(plane),
2586 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2587 (intel_crtc->config->pipe_src_w - 1));
2588 I915_WRITE(PRIMPOS(plane), 0);
2589 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2590 }
2591
2592 switch (fb->pixel_format) {
2593 case DRM_FORMAT_C8:
2594 dspcntr |= DISPPLANE_8BPP;
2595 break;
2596 case DRM_FORMAT_XRGB1555:
2597 case DRM_FORMAT_ARGB1555:
2598 dspcntr |= DISPPLANE_BGRX555;
2599 break;
2600 case DRM_FORMAT_RGB565:
2601 dspcntr |= DISPPLANE_BGRX565;
2602 break;
2603 case DRM_FORMAT_XRGB8888:
2604 case DRM_FORMAT_ARGB8888:
2605 dspcntr |= DISPPLANE_BGRX888;
2606 break;
2607 case DRM_FORMAT_XBGR8888:
2608 case DRM_FORMAT_ABGR8888:
2609 dspcntr |= DISPPLANE_RGBX888;
2610 break;
2611 case DRM_FORMAT_XRGB2101010:
2612 case DRM_FORMAT_ARGB2101010:
2613 dspcntr |= DISPPLANE_BGRX101010;
2614 break;
2615 case DRM_FORMAT_XBGR2101010:
2616 case DRM_FORMAT_ABGR2101010:
2617 dspcntr |= DISPPLANE_RGBX101010;
2618 break;
2619 default:
2620 BUG();
2621 }
2622
2623 if (INTEL_INFO(dev)->gen >= 4 &&
2624 obj->tiling_mode != I915_TILING_NONE)
2625 dspcntr |= DISPPLANE_TILED;
2626
2627 if (IS_G4X(dev))
2628 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2629
2630 linear_offset = y * fb->pitches[0] + x * pixel_size;
2631
2632 if (INTEL_INFO(dev)->gen >= 4) {
2633 intel_crtc->dspaddr_offset =
2634 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2635 pixel_size,
2636 fb->pitches[0]);
2637 linear_offset -= intel_crtc->dspaddr_offset;
2638 } else {
2639 intel_crtc->dspaddr_offset = linear_offset;
2640 }
2641
2642 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2643 dspcntr |= DISPPLANE_ROTATE_180;
2644
2645 x += (intel_crtc->config->pipe_src_w - 1);
2646 y += (intel_crtc->config->pipe_src_h - 1);
2647
2648 /* Finding the last pixel of the last line of the display
2649 data and adding to linear_offset*/
2650 linear_offset +=
2651 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2652 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2653 }
2654
2655 I915_WRITE(reg, dspcntr);
2656
2657 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2658 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2659 fb->pitches[0]);
2660 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2661 if (INTEL_INFO(dev)->gen >= 4) {
2662 I915_WRITE(DSPSURF(plane),
2663 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2664 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2665 I915_WRITE(DSPLINOFF(plane), linear_offset);
2666 } else
2667 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2668 POSTING_READ(reg);
2669}
2670
2671static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2672 struct drm_framebuffer *fb,
2673 int x, int y)
2674{
2675 struct drm_device *dev = crtc->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678 struct drm_i915_gem_object *obj;
2679 int plane = intel_crtc->plane;
2680 unsigned long linear_offset;
2681 u32 dspcntr;
2682 u32 reg = DSPCNTR(plane);
2683 int pixel_size;
2684
2685 if (!intel_crtc->primary_enabled) {
2686 I915_WRITE(reg, 0);
2687 I915_WRITE(DSPSURF(plane), 0);
2688 POSTING_READ(reg);
2689 return;
2690 }
2691
2692 obj = intel_fb_obj(fb);
2693 if (WARN_ON(obj == NULL))
2694 return;
2695
2696 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2697
2698 dspcntr = DISPPLANE_GAMMA_ENABLE;
2699
2700 dspcntr |= DISPLAY_PLANE_ENABLE;
2701
2702 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2703 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2704
2705 switch (fb->pixel_format) {
2706 case DRM_FORMAT_C8:
2707 dspcntr |= DISPPLANE_8BPP;
2708 break;
2709 case DRM_FORMAT_RGB565:
2710 dspcntr |= DISPPLANE_BGRX565;
2711 break;
2712 case DRM_FORMAT_XRGB8888:
2713 case DRM_FORMAT_ARGB8888:
2714 dspcntr |= DISPPLANE_BGRX888;
2715 break;
2716 case DRM_FORMAT_XBGR8888:
2717 case DRM_FORMAT_ABGR8888:
2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
2721 case DRM_FORMAT_ARGB2101010:
2722 dspcntr |= DISPPLANE_BGRX101010;
2723 break;
2724 case DRM_FORMAT_XBGR2101010:
2725 case DRM_FORMAT_ABGR2101010:
2726 dspcntr |= DISPPLANE_RGBX101010;
2727 break;
2728 default:
2729 BUG();
2730 }
2731
2732 if (obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
2734
2735 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
2739 intel_crtc->dspaddr_offset =
2740 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2741 pixel_size,
2742 fb->pitches[0]);
2743 linear_offset -= intel_crtc->dspaddr_offset;
2744 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2745 dspcntr |= DISPPLANE_ROTATE_180;
2746
2747 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2748 x += (intel_crtc->config->pipe_src_w - 1);
2749 y += (intel_crtc->config->pipe_src_h - 1);
2750
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2753 linear_offset +=
2754 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756 }
2757 }
2758
2759 I915_WRITE(reg, dspcntr);
2760
2761 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2762 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2763 fb->pitches[0]);
2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2768 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2769 } else {
2770 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2771 I915_WRITE(DSPLINOFF(plane), linear_offset);
2772 }
2773 POSTING_READ(reg);
2774}
2775
2776u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2777 uint32_t pixel_format)
2778{
2779 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2780
2781 /*
2782 * The stride is either expressed as a multiple of 64 bytes
2783 * chunks for linear buffers or in number of tiles for tiled
2784 * buffers.
2785 */
2786 switch (fb_modifier) {
2787 case DRM_FORMAT_MOD_NONE:
2788 return 64;
2789 case I915_FORMAT_MOD_X_TILED:
2790 if (INTEL_INFO(dev)->gen == 2)
2791 return 128;
2792 return 512;
2793 case I915_FORMAT_MOD_Y_TILED:
2794 /* No need to check for old gens and Y tiling since this is
2795 * about the display engine and those will be blocked before
2796 * we get here.
2797 */
2798 return 128;
2799 case I915_FORMAT_MOD_Yf_TILED:
2800 if (bits_per_pixel == 8)
2801 return 64;
2802 else
2803 return 128;
2804 default:
2805 MISSING_CASE(fb_modifier);
2806 return 64;
2807 }
2808}
2809
2810static void skylake_update_primary_plane(struct drm_crtc *crtc,
2811 struct drm_framebuffer *fb,
2812 int x, int y)
2813{
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 struct drm_i915_gem_object *obj;
2818 int pipe = intel_crtc->pipe;
2819 u32 plane_ctl, stride_div;
2820
2821 if (!intel_crtc->primary_enabled) {
2822 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2823 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2824 POSTING_READ(PLANE_CTL(pipe, 0));
2825 return;
2826 }
2827
2828 plane_ctl = PLANE_CTL_ENABLE |
2829 PLANE_CTL_PIPE_GAMMA_ENABLE |
2830 PLANE_CTL_PIPE_CSC_ENABLE;
2831
2832 switch (fb->pixel_format) {
2833 case DRM_FORMAT_RGB565:
2834 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2835 break;
2836 case DRM_FORMAT_XRGB8888:
2837 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2838 break;
2839 case DRM_FORMAT_ARGB8888:
2840 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2841 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2842 break;
2843 case DRM_FORMAT_XBGR8888:
2844 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2845 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2846 break;
2847 case DRM_FORMAT_ABGR8888:
2848 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2851 break;
2852 case DRM_FORMAT_XRGB2101010:
2853 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2854 break;
2855 case DRM_FORMAT_XBGR2101010:
2856 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858 break;
2859 default:
2860 BUG();
2861 }
2862
2863 switch (fb->modifier[0]) {
2864 case DRM_FORMAT_MOD_NONE:
2865 break;
2866 case I915_FORMAT_MOD_X_TILED:
2867 plane_ctl |= PLANE_CTL_TILED_X;
2868 break;
2869 case I915_FORMAT_MOD_Y_TILED:
2870 plane_ctl |= PLANE_CTL_TILED_Y;
2871 break;
2872 case I915_FORMAT_MOD_Yf_TILED:
2873 plane_ctl |= PLANE_CTL_TILED_YF;
2874 break;
2875 default:
2876 MISSING_CASE(fb->modifier[0]);
2877 }
2878
2879 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2881 plane_ctl |= PLANE_CTL_ROTATE_180;
2882
2883 obj = intel_fb_obj(fb);
2884 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2885 fb->pixel_format);
2886
2887 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2888
2889 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2890 i915_gem_obj_ggtt_offset(obj),
2891 x, y, fb->width, fb->height,
2892 fb->pitches[0]);
2893
2894 I915_WRITE(PLANE_POS(pipe, 0), 0);
2895 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2896 I915_WRITE(PLANE_SIZE(pipe, 0),
2897 (intel_crtc->config->pipe_src_h - 1) << 16 |
2898 (intel_crtc->config->pipe_src_w - 1));
2899 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2900 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2901
2902 POSTING_READ(PLANE_SURF(pipe, 0));
2903}
2904
2905/* Assume fb object is pinned & idle & fenced and just update base pointers */
2906static int
2907intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2908 int x, int y, enum mode_set_atomic state)
2909{
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912
2913 if (dev_priv->display.disable_fbc)
2914 dev_priv->display.disable_fbc(dev);
2915
2916 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2917
2918 return 0;
2919}
2920
2921static void intel_complete_page_flips(struct drm_device *dev)
2922{
2923 struct drm_crtc *crtc;
2924
2925 for_each_crtc(dev, crtc) {
2926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2927 enum plane plane = intel_crtc->plane;
2928
2929 intel_prepare_page_flip(dev, plane);
2930 intel_finish_page_flip_plane(dev, plane);
2931 }
2932}
2933
2934static void intel_update_primary_planes(struct drm_device *dev)
2935{
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 struct drm_crtc *crtc;
2938
2939 for_each_crtc(dev, crtc) {
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941
2942 drm_modeset_lock(&crtc->mutex, NULL);
2943 /*
2944 * FIXME: Once we have proper support for primary planes (and
2945 * disabling them without disabling the entire crtc) allow again
2946 * a NULL crtc->primary->fb.
2947 */
2948 if (intel_crtc->active && crtc->primary->fb)
2949 dev_priv->display.update_primary_plane(crtc,
2950 crtc->primary->fb,
2951 crtc->x,
2952 crtc->y);
2953 drm_modeset_unlock(&crtc->mutex);
2954 }
2955}
2956
2957void intel_prepare_reset(struct drm_device *dev)
2958{
2959 struct drm_i915_private *dev_priv = to_i915(dev);
2960 struct intel_crtc *crtc;
2961
2962 /* no reset support for gen2 */
2963 if (IS_GEN2(dev))
2964 return;
2965
2966 /* reset doesn't touch the display */
2967 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2968 return;
2969
2970 drm_modeset_lock_all(dev);
2971
2972 /*
2973 * Disabling the crtcs gracefully seems nicer. Also the
2974 * g33 docs say we should at least disable all the planes.
2975 */
2976 for_each_intel_crtc(dev, crtc) {
2977 if (crtc->active)
2978 dev_priv->display.crtc_disable(&crtc->base);
2979 }
2980}
2981
2982void intel_finish_reset(struct drm_device *dev)
2983{
2984 struct drm_i915_private *dev_priv = to_i915(dev);
2985
2986 /*
2987 * Flips in the rings will be nuked by the reset,
2988 * so complete all pending flips so that user space
2989 * will get its events and not get stuck.
2990 */
2991 intel_complete_page_flips(dev);
2992
2993 /* no reset support for gen2 */
2994 if (IS_GEN2(dev))
2995 return;
2996
2997 /* reset doesn't touch the display */
2998 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2999 /*
3000 * Flips in the rings have been nuked by the reset,
3001 * so update the base address of all primary
3002 * planes to the the last fb to make sure we're
3003 * showing the correct fb after a reset.
3004 */
3005 intel_update_primary_planes(dev);
3006 return;
3007 }
3008
3009 /*
3010 * The display has been reset as well,
3011 * so need a full re-initialization.
3012 */
3013 intel_runtime_pm_disable_interrupts(dev_priv);
3014 intel_runtime_pm_enable_interrupts(dev_priv);
3015
3016 intel_modeset_init_hw(dev);
3017
3018 spin_lock_irq(&dev_priv->irq_lock);
3019 if (dev_priv->display.hpd_irq_setup)
3020 dev_priv->display.hpd_irq_setup(dev);
3021 spin_unlock_irq(&dev_priv->irq_lock);
3022
3023 intel_modeset_setup_hw_state(dev, true);
3024
3025 intel_hpd_init(dev_priv);
3026
3027 drm_modeset_unlock_all(dev);
3028}
3029
3030static int
3031intel_finish_fb(struct drm_framebuffer *old_fb)
3032{
3033 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3034 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3035 bool was_interruptible = dev_priv->mm.interruptible;
3036 int ret;
3037
3038 /* Big Hammer, we also need to ensure that any pending
3039 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3040 * current scanout is retired before unpinning the old
3041 * framebuffer.
3042 *
3043 * This should only fail upon a hung GPU, in which case we
3044 * can safely continue.
3045 */
3046 dev_priv->mm.interruptible = false;
3047 ret = i915_gem_object_finish_gpu(obj);
3048 dev_priv->mm.interruptible = was_interruptible;
3049
3050 return ret;
3051}
3052
3053static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3054{
3055 struct drm_device *dev = crtc->dev;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058 bool pending;
3059
3060 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3061 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3062 return false;
3063
3064 spin_lock_irq(&dev->event_lock);
3065 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3066 spin_unlock_irq(&dev->event_lock);
3067
3068 return pending;
3069}
3070
3071static void intel_update_pipe_size(struct intel_crtc *crtc)
3072{
3073 struct drm_device *dev = crtc->base.dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 const struct drm_display_mode *adjusted_mode;
3076
3077 if (!i915.fastboot)
3078 return;
3079
3080 /*
3081 * Update pipe size and adjust fitter if needed: the reason for this is
3082 * that in compute_mode_changes we check the native mode (not the pfit
3083 * mode) to see if we can flip rather than do a full mode set. In the
3084 * fastboot case, we'll flip, but if we don't update the pipesrc and
3085 * pfit state, we'll end up with a big fb scanned out into the wrong
3086 * sized surface.
3087 *
3088 * To fix this properly, we need to hoist the checks up into
3089 * compute_mode_changes (or above), check the actual pfit state and
3090 * whether the platform allows pfit disable with pipe active, and only
3091 * then update the pipesrc and pfit state, even on the flip path.
3092 */
3093
3094 adjusted_mode = &crtc->config->base.adjusted_mode;
3095
3096 I915_WRITE(PIPESRC(crtc->pipe),
3097 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3098 (adjusted_mode->crtc_vdisplay - 1));
3099 if (!crtc->config->pch_pfit.enabled &&
3100 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3101 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3102 I915_WRITE(PF_CTL(crtc->pipe), 0);
3103 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3104 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3105 }
3106 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3107 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3108}
3109
3110static void intel_fdi_normal_train(struct drm_crtc *crtc)
3111{
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115 int pipe = intel_crtc->pipe;
3116 u32 reg, temp;
3117
3118 /* enable normal train */
3119 reg = FDI_TX_CTL(pipe);
3120 temp = I915_READ(reg);
3121 if (IS_IVYBRIDGE(dev)) {
3122 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3123 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3124 } else {
3125 temp &= ~FDI_LINK_TRAIN_NONE;
3126 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3127 }
3128 I915_WRITE(reg, temp);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 if (HAS_PCH_CPT(dev)) {
3133 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3134 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3135 } else {
3136 temp &= ~FDI_LINK_TRAIN_NONE;
3137 temp |= FDI_LINK_TRAIN_NONE;
3138 }
3139 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3140
3141 /* wait one idle pattern time */
3142 POSTING_READ(reg);
3143 udelay(1000);
3144
3145 /* IVB wants error correction enabled */
3146 if (IS_IVYBRIDGE(dev))
3147 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3148 FDI_FE_ERRC_ENABLE);
3149}
3150
3151static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3152{
3153 return crtc->base.state->enable && crtc->active &&
3154 crtc->config->has_pch_encoder;
3155}
3156
3157static void ivb_modeset_global_resources(struct drm_device *dev)
3158{
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160 struct intel_crtc *pipe_B_crtc =
3161 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3162 struct intel_crtc *pipe_C_crtc =
3163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3164 uint32_t temp;
3165
3166 /*
3167 * When everything is off disable fdi C so that we could enable fdi B
3168 * with all lanes. Note that we don't care about enabled pipes without
3169 * an enabled pch encoder.
3170 */
3171 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3172 !pipe_has_enabled_pch(pipe_C_crtc)) {
3173 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3174 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3175
3176 temp = I915_READ(SOUTH_CHICKEN1);
3177 temp &= ~FDI_BC_BIFURCATION_SELECT;
3178 DRM_DEBUG_KMS("disabling fdi C rx\n");
3179 I915_WRITE(SOUTH_CHICKEN1, temp);
3180 }
3181}
3182
3183/* The FDI link training functions for ILK/Ibexpeak. */
3184static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 int pipe = intel_crtc->pipe;
3190 u32 reg, temp, tries;
3191
3192 /* FDI needs bits from pipe first */
3193 assert_pipe_enabled(dev_priv, pipe);
3194
3195 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3196 for train result */
3197 reg = FDI_RX_IMR(pipe);
3198 temp = I915_READ(reg);
3199 temp &= ~FDI_RX_SYMBOL_LOCK;
3200 temp &= ~FDI_RX_BIT_LOCK;
3201 I915_WRITE(reg, temp);
3202 I915_READ(reg);
3203 udelay(150);
3204
3205 /* enable CPU FDI TX and PCH FDI RX */
3206 reg = FDI_TX_CTL(pipe);
3207 temp = I915_READ(reg);
3208 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3209 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3210 temp &= ~FDI_LINK_TRAIN_NONE;
3211 temp |= FDI_LINK_TRAIN_PATTERN_1;
3212 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3213
3214 reg = FDI_RX_CTL(pipe);
3215 temp = I915_READ(reg);
3216 temp &= ~FDI_LINK_TRAIN_NONE;
3217 temp |= FDI_LINK_TRAIN_PATTERN_1;
3218 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3219
3220 POSTING_READ(reg);
3221 udelay(150);
3222
3223 /* Ironlake workaround, enable clock pointer after FDI enable*/
3224 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3226 FDI_RX_PHASE_SYNC_POINTER_EN);
3227
3228 reg = FDI_RX_IIR(pipe);
3229 for (tries = 0; tries < 5; tries++) {
3230 temp = I915_READ(reg);
3231 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3232
3233 if ((temp & FDI_RX_BIT_LOCK)) {
3234 DRM_DEBUG_KMS("FDI train 1 done.\n");
3235 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3236 break;
3237 }
3238 }
3239 if (tries == 5)
3240 DRM_ERROR("FDI train 1 fail!\n");
3241
3242 /* Train 2 */
3243 reg = FDI_TX_CTL(pipe);
3244 temp = I915_READ(reg);
3245 temp &= ~FDI_LINK_TRAIN_NONE;
3246 temp |= FDI_LINK_TRAIN_PATTERN_2;
3247 I915_WRITE(reg, temp);
3248
3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
3251 temp &= ~FDI_LINK_TRAIN_NONE;
3252 temp |= FDI_LINK_TRAIN_PATTERN_2;
3253 I915_WRITE(reg, temp);
3254
3255 POSTING_READ(reg);
3256 udelay(150);
3257
3258 reg = FDI_RX_IIR(pipe);
3259 for (tries = 0; tries < 5; tries++) {
3260 temp = I915_READ(reg);
3261 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3262
3263 if (temp & FDI_RX_SYMBOL_LOCK) {
3264 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3265 DRM_DEBUG_KMS("FDI train 2 done.\n");
3266 break;
3267 }
3268 }
3269 if (tries == 5)
3270 DRM_ERROR("FDI train 2 fail!\n");
3271
3272 DRM_DEBUG_KMS("FDI train done\n");
3273
3274}
3275
3276static const int snb_b_fdi_train_param[] = {
3277 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3278 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3279 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3280 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3281};
3282
3283/* The FDI link training functions for SNB/Cougarpoint. */
3284static void gen6_fdi_link_train(struct drm_crtc *crtc)
3285{
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 int pipe = intel_crtc->pipe;
3290 u32 reg, temp, i, retry;
3291
3292 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3293 for train result */
3294 reg = FDI_RX_IMR(pipe);
3295 temp = I915_READ(reg);
3296 temp &= ~FDI_RX_SYMBOL_LOCK;
3297 temp &= ~FDI_RX_BIT_LOCK;
3298 I915_WRITE(reg, temp);
3299
3300 POSTING_READ(reg);
3301 udelay(150);
3302
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 /* SNB-B */
3312 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 if (HAS_PCH_CPT(dev)) {
3321 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3322 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3323 } else {
3324 temp &= ~FDI_LINK_TRAIN_NONE;
3325 temp |= FDI_LINK_TRAIN_PATTERN_1;
3326 }
3327 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3328
3329 POSTING_READ(reg);
3330 udelay(150);
3331
3332 for (i = 0; i < 4; i++) {
3333 reg = FDI_TX_CTL(pipe);
3334 temp = I915_READ(reg);
3335 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3336 temp |= snb_b_fdi_train_param[i];
3337 I915_WRITE(reg, temp);
3338
3339 POSTING_READ(reg);
3340 udelay(500);
3341
3342 for (retry = 0; retry < 5; retry++) {
3343 reg = FDI_RX_IIR(pipe);
3344 temp = I915_READ(reg);
3345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3346 if (temp & FDI_RX_BIT_LOCK) {
3347 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3348 DRM_DEBUG_KMS("FDI train 1 done.\n");
3349 break;
3350 }
3351 udelay(50);
3352 }
3353 if (retry < 5)
3354 break;
3355 }
3356 if (i == 4)
3357 DRM_ERROR("FDI train 1 fail!\n");
3358
3359 /* Train 2 */
3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_PATTERN_2;
3364 if (IS_GEN6(dev)) {
3365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3366 /* SNB-B */
3367 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3368 }
3369 I915_WRITE(reg, temp);
3370
3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (HAS_PCH_CPT(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3376 } else {
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 }
3380 I915_WRITE(reg, temp);
3381
3382 POSTING_READ(reg);
3383 udelay(150);
3384
3385 for (i = 0; i < 4; i++) {
3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
3388 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3389 temp |= snb_b_fdi_train_param[i];
3390 I915_WRITE(reg, temp);
3391
3392 POSTING_READ(reg);
3393 udelay(500);
3394
3395 for (retry = 0; retry < 5; retry++) {
3396 reg = FDI_RX_IIR(pipe);
3397 temp = I915_READ(reg);
3398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3399 if (temp & FDI_RX_SYMBOL_LOCK) {
3400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3401 DRM_DEBUG_KMS("FDI train 2 done.\n");
3402 break;
3403 }
3404 udelay(50);
3405 }
3406 if (retry < 5)
3407 break;
3408 }
3409 if (i == 4)
3410 DRM_ERROR("FDI train 2 fail!\n");
3411
3412 DRM_DEBUG_KMS("FDI train done.\n");
3413}
3414
3415/* Manual link training for Ivy Bridge A0 parts */
3416static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3417{
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 u32 reg, temp, i, j;
3423
3424 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3425 for train result */
3426 reg = FDI_RX_IMR(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_RX_SYMBOL_LOCK;
3429 temp &= ~FDI_RX_BIT_LOCK;
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(150);
3434
3435 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3436 I915_READ(FDI_RX_IIR(pipe)));
3437
3438 /* Try each vswing and preemphasis setting twice before moving on */
3439 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3440 /* disable first in case we need to retry */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3444 temp &= ~FDI_TX_ENABLE;
3445 I915_WRITE(reg, temp);
3446
3447 reg = FDI_RX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_LINK_TRAIN_AUTO;
3450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3451 temp &= ~FDI_RX_ENABLE;
3452 I915_WRITE(reg, temp);
3453
3454 /* enable CPU FDI TX and PCH FDI RX */
3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461 temp |= snb_b_fdi_train_param[j/2];
3462 temp |= FDI_COMPOSITE_SYNC;
3463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3464
3465 I915_WRITE(FDI_RX_MISC(pipe),
3466 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3467
3468 reg = FDI_RX_CTL(pipe);
3469 temp = I915_READ(reg);
3470 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3471 temp |= FDI_COMPOSITE_SYNC;
3472 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3473
3474 POSTING_READ(reg);
3475 udelay(1); /* should be 0.5us */
3476
3477 for (i = 0; i < 4; i++) {
3478 reg = FDI_RX_IIR(pipe);
3479 temp = I915_READ(reg);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3481
3482 if (temp & FDI_RX_BIT_LOCK ||
3483 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3485 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3486 i);
3487 break;
3488 }
3489 udelay(1); /* should be 0.5us */
3490 }
3491 if (i == 4) {
3492 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3493 continue;
3494 }
3495
3496 /* Train 2 */
3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
3499 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3500 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3501 I915_WRITE(reg, temp);
3502
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3506 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
3510 udelay(2); /* should be 1.5us */
3511
3512 for (i = 0; i < 4; i++) {
3513 reg = FDI_RX_IIR(pipe);
3514 temp = I915_READ(reg);
3515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3516
3517 if (temp & FDI_RX_SYMBOL_LOCK ||
3518 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3521 i);
3522 goto train_done;
3523 }
3524 udelay(2); /* should be 1.5us */
3525 }
3526 if (i == 4)
3527 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3528 }
3529
3530train_done:
3531 DRM_DEBUG_KMS("FDI train done.\n");
3532}
3533
3534static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3535{
3536 struct drm_device *dev = intel_crtc->base.dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538 int pipe = intel_crtc->pipe;
3539 u32 reg, temp;
3540
3541
3542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3543 reg = FDI_RX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3547 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3548 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3549
3550 POSTING_READ(reg);
3551 udelay(200);
3552
3553 /* Switch from Rawclk to PCDclk */
3554 temp = I915_READ(reg);
3555 I915_WRITE(reg, temp | FDI_PCDCLK);
3556
3557 POSTING_READ(reg);
3558 udelay(200);
3559
3560 /* Enable CPU FDI TX PLL, always on for Ironlake */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3564 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3565
3566 POSTING_READ(reg);
3567 udelay(100);
3568 }
3569}
3570
3571static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3572{
3573 struct drm_device *dev = intel_crtc->base.dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 int pipe = intel_crtc->pipe;
3576 u32 reg, temp;
3577
3578 /* Switch from PCDclk to Rawclk */
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3582
3583 /* Disable CPU FDI TX PLL */
3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3587
3588 POSTING_READ(reg);
3589 udelay(100);
3590
3591 reg = FDI_RX_CTL(pipe);
3592 temp = I915_READ(reg);
3593 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3594
3595 /* Wait for the clocks to turn off. */
3596 POSTING_READ(reg);
3597 udelay(100);
3598}
3599
3600static void ironlake_fdi_disable(struct drm_crtc *crtc)
3601{
3602 struct drm_device *dev = crtc->dev;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605 int pipe = intel_crtc->pipe;
3606 u32 reg, temp;
3607
3608 /* disable CPU FDI tx and PCH FDI rx */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3612 POSTING_READ(reg);
3613
3614 reg = FDI_RX_CTL(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~(0x7 << 16);
3617 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3618 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3619
3620 POSTING_READ(reg);
3621 udelay(100);
3622
3623 /* Ironlake workaround, disable clock pointer after downing FDI */
3624 if (HAS_PCH_IBX(dev))
3625 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3626
3627 /* still set train pattern 1 */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 temp &= ~FDI_LINK_TRAIN_NONE;
3631 temp |= FDI_LINK_TRAIN_PATTERN_1;
3632 I915_WRITE(reg, temp);
3633
3634 reg = FDI_RX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 if (HAS_PCH_CPT(dev)) {
3637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639 } else {
3640 temp &= ~FDI_LINK_TRAIN_NONE;
3641 temp |= FDI_LINK_TRAIN_PATTERN_1;
3642 }
3643 /* BPC in FDI rx is consistent with that in PIPECONF */
3644 temp &= ~(0x07 << 16);
3645 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3646 I915_WRITE(reg, temp);
3647
3648 POSTING_READ(reg);
3649 udelay(100);
3650}
3651
3652bool intel_has_pending_fb_unpin(struct drm_device *dev)
3653{
3654 struct intel_crtc *crtc;
3655
3656 /* Note that we don't need to be called with mode_config.lock here
3657 * as our list of CRTC objects is static for the lifetime of the
3658 * device and so cannot disappear as we iterate. Similarly, we can
3659 * happily treat the predicates as racy, atomic checks as userspace
3660 * cannot claim and pin a new fb without at least acquring the
3661 * struct_mutex and so serialising with us.
3662 */
3663 for_each_intel_crtc(dev, crtc) {
3664 if (atomic_read(&crtc->unpin_work_count) == 0)
3665 continue;
3666
3667 if (crtc->unpin_work)
3668 intel_wait_for_vblank(dev, crtc->pipe);
3669
3670 return true;
3671 }
3672
3673 return false;
3674}
3675
3676static void page_flip_completed(struct intel_crtc *intel_crtc)
3677{
3678 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3679 struct intel_unpin_work *work = intel_crtc->unpin_work;
3680
3681 /* ensure that the unpin work is consistent wrt ->pending. */
3682 smp_rmb();
3683 intel_crtc->unpin_work = NULL;
3684
3685 if (work->event)
3686 drm_send_vblank_event(intel_crtc->base.dev,
3687 intel_crtc->pipe,
3688 work->event);
3689
3690 drm_crtc_vblank_put(&intel_crtc->base);
3691
3692 wake_up_all(&dev_priv->pending_flip_queue);
3693 queue_work(dev_priv->wq, &work->work);
3694
3695 trace_i915_flip_complete(intel_crtc->plane,
3696 work->pending_flip_obj);
3697}
3698
3699void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3700{
3701 struct drm_device *dev = crtc->dev;
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703
3704 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3705 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3706 !intel_crtc_has_pending_flip(crtc),
3707 60*HZ) == 0)) {
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3709
3710 spin_lock_irq(&dev->event_lock);
3711 if (intel_crtc->unpin_work) {
3712 WARN_ONCE(1, "Removing stuck page flip\n");
3713 page_flip_completed(intel_crtc);
3714 }
3715 spin_unlock_irq(&dev->event_lock);
3716 }
3717
3718 if (crtc->primary->fb) {
3719 mutex_lock(&dev->struct_mutex);
3720 intel_finish_fb(crtc->primary->fb);
3721 mutex_unlock(&dev->struct_mutex);
3722 }
3723}
3724
3725/* Program iCLKIP clock to the desired frequency */
3726static void lpt_program_iclkip(struct drm_crtc *crtc)
3727{
3728 struct drm_device *dev = crtc->dev;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3731 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3732 u32 temp;
3733
3734 mutex_lock(&dev_priv->dpio_lock);
3735
3736 /* It is necessary to ungate the pixclk gate prior to programming
3737 * the divisors, and gate it back when it is done.
3738 */
3739 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3740
3741 /* Disable SSCCTL */
3742 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3743 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3744 SBI_SSCCTL_DISABLE,
3745 SBI_ICLK);
3746
3747 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3748 if (clock == 20000) {
3749 auxdiv = 1;
3750 divsel = 0x41;
3751 phaseinc = 0x20;
3752 } else {
3753 /* The iCLK virtual clock root frequency is in MHz,
3754 * but the adjusted_mode->crtc_clock in in KHz. To get the
3755 * divisors, it is necessary to divide one by another, so we
3756 * convert the virtual clock precision to KHz here for higher
3757 * precision.
3758 */
3759 u32 iclk_virtual_root_freq = 172800 * 1000;
3760 u32 iclk_pi_range = 64;
3761 u32 desired_divisor, msb_divisor_value, pi_value;
3762
3763 desired_divisor = (iclk_virtual_root_freq / clock);
3764 msb_divisor_value = desired_divisor / iclk_pi_range;
3765 pi_value = desired_divisor % iclk_pi_range;
3766
3767 auxdiv = 0;
3768 divsel = msb_divisor_value - 2;
3769 phaseinc = pi_value;
3770 }
3771
3772 /* This should not happen with any sane values */
3773 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3774 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3775 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3776 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3777
3778 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3779 clock,
3780 auxdiv,
3781 divsel,
3782 phasedir,
3783 phaseinc);
3784
3785 /* Program SSCDIVINTPHASE6 */
3786 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3787 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3788 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3789 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3790 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3791 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3792 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3793 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3794
3795 /* Program SSCAUXDIV */
3796 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3797 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3798 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3799 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3800
3801 /* Enable modulator and associated divider */
3802 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3803 temp &= ~SBI_SSCCTL_DISABLE;
3804 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3805
3806 /* Wait for initialization time */
3807 udelay(24);
3808
3809 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3810
3811 mutex_unlock(&dev_priv->dpio_lock);
3812}
3813
3814static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3815 enum pipe pch_transcoder)
3816{
3817 struct drm_device *dev = crtc->base.dev;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3820
3821 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3822 I915_READ(HTOTAL(cpu_transcoder)));
3823 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3824 I915_READ(HBLANK(cpu_transcoder)));
3825 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3826 I915_READ(HSYNC(cpu_transcoder)));
3827
3828 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3829 I915_READ(VTOTAL(cpu_transcoder)));
3830 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3831 I915_READ(VBLANK(cpu_transcoder)));
3832 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3833 I915_READ(VSYNC(cpu_transcoder)));
3834 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3835 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3836}
3837
3838static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 uint32_t temp;
3842
3843 temp = I915_READ(SOUTH_CHICKEN1);
3844 if (temp & FDI_BC_BIFURCATION_SELECT)
3845 return;
3846
3847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3848 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3849
3850 temp |= FDI_BC_BIFURCATION_SELECT;
3851 DRM_DEBUG_KMS("enabling fdi C rx\n");
3852 I915_WRITE(SOUTH_CHICKEN1, temp);
3853 POSTING_READ(SOUTH_CHICKEN1);
3854}
3855
3856static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3857{
3858 struct drm_device *dev = intel_crtc->base.dev;
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861 switch (intel_crtc->pipe) {
3862 case PIPE_A:
3863 break;
3864 case PIPE_B:
3865 if (intel_crtc->config->fdi_lanes > 2)
3866 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3867 else
3868 cpt_enable_fdi_bc_bifurcation(dev);
3869
3870 break;
3871 case PIPE_C:
3872 cpt_enable_fdi_bc_bifurcation(dev);
3873
3874 break;
3875 default:
3876 BUG();
3877 }
3878}
3879
3880/*
3881 * Enable PCH resources required for PCH ports:
3882 * - PCH PLLs
3883 * - FDI training & RX/TX
3884 * - update transcoder timings
3885 * - DP transcoding bits
3886 * - transcoder
3887 */
3888static void ironlake_pch_enable(struct drm_crtc *crtc)
3889{
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 int pipe = intel_crtc->pipe;
3894 u32 reg, temp;
3895
3896 assert_pch_transcoder_disabled(dev_priv, pipe);
3897
3898 if (IS_IVYBRIDGE(dev))
3899 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3900
3901 /* Write the TU size bits before fdi link training, so that error
3902 * detection works. */
3903 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3904 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3905
3906 /* For PCH output, training FDI link */
3907 dev_priv->display.fdi_link_train(crtc);
3908
3909 /* We need to program the right clock selection before writing the pixel
3910 * mutliplier into the DPLL. */
3911 if (HAS_PCH_CPT(dev)) {
3912 u32 sel;
3913
3914 temp = I915_READ(PCH_DPLL_SEL);
3915 temp |= TRANS_DPLL_ENABLE(pipe);
3916 sel = TRANS_DPLLB_SEL(pipe);
3917 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3918 temp |= sel;
3919 else
3920 temp &= ~sel;
3921 I915_WRITE(PCH_DPLL_SEL, temp);
3922 }
3923
3924 /* XXX: pch pll's can be enabled any time before we enable the PCH
3925 * transcoder, and we actually should do this to not upset any PCH
3926 * transcoder that already use the clock when we share it.
3927 *
3928 * Note that enable_shared_dpll tries to do the right thing, but
3929 * get_shared_dpll unconditionally resets the pll - we need that to have
3930 * the right LVDS enable sequence. */
3931 intel_enable_shared_dpll(intel_crtc);
3932
3933 /* set transcoder timing, panel must allow it */
3934 assert_panel_unlocked(dev_priv, pipe);
3935 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3936
3937 intel_fdi_normal_train(crtc);
3938
3939 /* For PCH DP, enable TRANS_DP_CTL */
3940 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3941 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3942 reg = TRANS_DP_CTL(pipe);
3943 temp = I915_READ(reg);
3944 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3945 TRANS_DP_SYNC_MASK |
3946 TRANS_DP_BPC_MASK);
3947 temp |= (TRANS_DP_OUTPUT_ENABLE |
3948 TRANS_DP_ENH_FRAMING);
3949 temp |= bpc << 9; /* same format but at 11:9 */
3950
3951 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3952 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3953 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3954 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3955
3956 switch (intel_trans_dp_port_sel(crtc)) {
3957 case PCH_DP_B:
3958 temp |= TRANS_DP_PORT_SEL_B;
3959 break;
3960 case PCH_DP_C:
3961 temp |= TRANS_DP_PORT_SEL_C;
3962 break;
3963 case PCH_DP_D:
3964 temp |= TRANS_DP_PORT_SEL_D;
3965 break;
3966 default:
3967 BUG();
3968 }
3969
3970 I915_WRITE(reg, temp);
3971 }
3972
3973 ironlake_enable_pch_transcoder(dev_priv, pipe);
3974}
3975
3976static void lpt_pch_enable(struct drm_crtc *crtc)
3977{
3978 struct drm_device *dev = crtc->dev;
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3981 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3982
3983 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3984
3985 lpt_program_iclkip(crtc);
3986
3987 /* Set transcoder timing. */
3988 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3989
3990 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3991}
3992
3993void intel_put_shared_dpll(struct intel_crtc *crtc)
3994{
3995 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3996
3997 if (pll == NULL)
3998 return;
3999
4000 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4001 WARN(1, "bad %s crtc mask\n", pll->name);
4002 return;
4003 }
4004
4005 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4006 if (pll->config.crtc_mask == 0) {
4007 WARN_ON(pll->on);
4008 WARN_ON(pll->active);
4009 }
4010
4011 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4012}
4013
4014struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4015 struct intel_crtc_state *crtc_state)
4016{
4017 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4018 struct intel_shared_dpll *pll;
4019 enum intel_dpll_id i;
4020
4021 if (HAS_PCH_IBX(dev_priv->dev)) {
4022 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4023 i = (enum intel_dpll_id) crtc->pipe;
4024 pll = &dev_priv->shared_dplls[i];
4025
4026 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4027 crtc->base.base.id, pll->name);
4028
4029 WARN_ON(pll->new_config->crtc_mask);
4030
4031 goto found;
4032 }
4033
4034 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4035 pll = &dev_priv->shared_dplls[i];
4036
4037 /* Only want to check enabled timings first */
4038 if (pll->new_config->crtc_mask == 0)
4039 continue;
4040
4041 if (memcmp(&crtc_state->dpll_hw_state,
4042 &pll->new_config->hw_state,
4043 sizeof(pll->new_config->hw_state)) == 0) {
4044 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4045 crtc->base.base.id, pll->name,
4046 pll->new_config->crtc_mask,
4047 pll->active);
4048 goto found;
4049 }
4050 }
4051
4052 /* Ok no matching timings, maybe there's a free one? */
4053 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4054 pll = &dev_priv->shared_dplls[i];
4055 if (pll->new_config->crtc_mask == 0) {
4056 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4057 crtc->base.base.id, pll->name);
4058 goto found;
4059 }
4060 }
4061
4062 return NULL;
4063
4064found:
4065 if (pll->new_config->crtc_mask == 0)
4066 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4067
4068 crtc_state->shared_dpll = i;
4069 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4070 pipe_name(crtc->pipe));
4071
4072 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4073
4074 return pll;
4075}
4076
4077/**
4078 * intel_shared_dpll_start_config - start a new PLL staged config
4079 * @dev_priv: DRM device
4080 * @clear_pipes: mask of pipes that will have their PLLs freed
4081 *
4082 * Starts a new PLL staged config, copying the current config but
4083 * releasing the references of pipes specified in clear_pipes.
4084 */
4085static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4086 unsigned clear_pipes)
4087{
4088 struct intel_shared_dpll *pll;
4089 enum intel_dpll_id i;
4090
4091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4092 pll = &dev_priv->shared_dplls[i];
4093
4094 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4095 GFP_KERNEL);
4096 if (!pll->new_config)
4097 goto cleanup;
4098
4099 pll->new_config->crtc_mask &= ~clear_pipes;
4100 }
4101
4102 return 0;
4103
4104cleanup:
4105 while (--i >= 0) {
4106 pll = &dev_priv->shared_dplls[i];
4107 kfree(pll->new_config);
4108 pll->new_config = NULL;
4109 }
4110
4111 return -ENOMEM;
4112}
4113
4114static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4115{
4116 struct intel_shared_dpll *pll;
4117 enum intel_dpll_id i;
4118
4119 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4120 pll = &dev_priv->shared_dplls[i];
4121
4122 WARN_ON(pll->new_config == &pll->config);
4123
4124 pll->config = *pll->new_config;
4125 kfree(pll->new_config);
4126 pll->new_config = NULL;
4127 }
4128}
4129
4130static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4131{
4132 struct intel_shared_dpll *pll;
4133 enum intel_dpll_id i;
4134
4135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4136 pll = &dev_priv->shared_dplls[i];
4137
4138 WARN_ON(pll->new_config == &pll->config);
4139
4140 kfree(pll->new_config);
4141 pll->new_config = NULL;
4142 }
4143}
4144
4145static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4146{
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int dslreg = PIPEDSL(pipe);
4149 u32 temp;
4150
4151 temp = I915_READ(dslreg);
4152 udelay(500);
4153 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4154 if (wait_for(I915_READ(dslreg) != temp, 5))
4155 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4156 }
4157}
4158
4159static void skylake_pfit_enable(struct intel_crtc *crtc)
4160{
4161 struct drm_device *dev = crtc->base.dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 int pipe = crtc->pipe;
4164
4165 if (crtc->config->pch_pfit.enabled) {
4166 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4167 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4168 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4169 }
4170}
4171
4172static void ironlake_pfit_enable(struct intel_crtc *crtc)
4173{
4174 struct drm_device *dev = crtc->base.dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 int pipe = crtc->pipe;
4177
4178 if (crtc->config->pch_pfit.enabled) {
4179 /* Force use of hard-coded filter coefficients
4180 * as some pre-programmed values are broken,
4181 * e.g. x201.
4182 */
4183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4185 PF_PIPE_SEL_IVB(pipe));
4186 else
4187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4188 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4190 }
4191}
4192
4193static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4194{
4195 struct drm_device *dev = crtc->dev;
4196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4197 struct drm_plane *plane;
4198 struct intel_plane *intel_plane;
4199
4200 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4201 intel_plane = to_intel_plane(plane);
4202 if (intel_plane->pipe == pipe)
4203 intel_plane_restore(&intel_plane->base);
4204 }
4205}
4206
4207/*
4208 * Disable a plane internally without actually modifying the plane's state.
4209 * This will allow us to easily restore the plane later by just reprogramming
4210 * its state.
4211 */
4212static void disable_plane_internal(struct drm_plane *plane)
4213{
4214 struct intel_plane *intel_plane = to_intel_plane(plane);
4215 struct drm_plane_state *state =
4216 plane->funcs->atomic_duplicate_state(plane);
4217 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4218
4219 intel_state->visible = false;
4220 intel_plane->commit_plane(plane, intel_state);
4221
4222 intel_plane_destroy_state(plane, state);
4223}
4224
4225static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4226{
4227 struct drm_device *dev = crtc->dev;
4228 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4229 struct drm_plane *plane;
4230 struct intel_plane *intel_plane;
4231
4232 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4233 intel_plane = to_intel_plane(plane);
4234 if (plane->fb && intel_plane->pipe == pipe)
4235 disable_plane_internal(plane);
4236 }
4237}
4238
4239void hsw_enable_ips(struct intel_crtc *crtc)
4240{
4241 struct drm_device *dev = crtc->base.dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244 if (!crtc->config->ips_enabled)
4245 return;
4246
4247 /* We can only enable IPS after we enable a plane and wait for a vblank */
4248 intel_wait_for_vblank(dev, crtc->pipe);
4249
4250 assert_plane_enabled(dev_priv, crtc->plane);
4251 if (IS_BROADWELL(dev)) {
4252 mutex_lock(&dev_priv->rps.hw_lock);
4253 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4254 mutex_unlock(&dev_priv->rps.hw_lock);
4255 /* Quoting Art Runyan: "its not safe to expect any particular
4256 * value in IPS_CTL bit 31 after enabling IPS through the
4257 * mailbox." Moreover, the mailbox may return a bogus state,
4258 * so we need to just enable it and continue on.
4259 */
4260 } else {
4261 I915_WRITE(IPS_CTL, IPS_ENABLE);
4262 /* The bit only becomes 1 in the next vblank, so this wait here
4263 * is essentially intel_wait_for_vblank. If we don't have this
4264 * and don't wait for vblanks until the end of crtc_enable, then
4265 * the HW state readout code will complain that the expected
4266 * IPS_CTL value is not the one we read. */
4267 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4268 DRM_ERROR("Timed out waiting for IPS enable\n");
4269 }
4270}
4271
4272void hsw_disable_ips(struct intel_crtc *crtc)
4273{
4274 struct drm_device *dev = crtc->base.dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276
4277 if (!crtc->config->ips_enabled)
4278 return;
4279
4280 assert_plane_enabled(dev_priv, crtc->plane);
4281 if (IS_BROADWELL(dev)) {
4282 mutex_lock(&dev_priv->rps.hw_lock);
4283 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4284 mutex_unlock(&dev_priv->rps.hw_lock);
4285 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4286 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4287 DRM_ERROR("Timed out waiting for IPS disable\n");
4288 } else {
4289 I915_WRITE(IPS_CTL, 0);
4290 POSTING_READ(IPS_CTL);
4291 }
4292
4293 /* We need to wait for a vblank before we can disable the plane. */
4294 intel_wait_for_vblank(dev, crtc->pipe);
4295}
4296
4297/** Loads the palette/gamma unit for the CRTC with the prepared values */
4298static void intel_crtc_load_lut(struct drm_crtc *crtc)
4299{
4300 struct drm_device *dev = crtc->dev;
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303 enum pipe pipe = intel_crtc->pipe;
4304 int palreg = PALETTE(pipe);
4305 int i;
4306 bool reenable_ips = false;
4307
4308 /* The clocks have to be on to load the palette. */
4309 if (!crtc->state->enable || !intel_crtc->active)
4310 return;
4311
4312 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4313 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4314 assert_dsi_pll_enabled(dev_priv);
4315 else
4316 assert_pll_enabled(dev_priv, pipe);
4317 }
4318
4319 /* use legacy palette for Ironlake */
4320 if (!HAS_GMCH_DISPLAY(dev))
4321 palreg = LGC_PALETTE(pipe);
4322
4323 /* Workaround : Do not read or write the pipe palette/gamma data while
4324 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4325 */
4326 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4327 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4328 GAMMA_MODE_MODE_SPLIT)) {
4329 hsw_disable_ips(intel_crtc);
4330 reenable_ips = true;
4331 }
4332
4333 for (i = 0; i < 256; i++) {
4334 I915_WRITE(palreg + 4 * i,
4335 (intel_crtc->lut_r[i] << 16) |
4336 (intel_crtc->lut_g[i] << 8) |
4337 intel_crtc->lut_b[i]);
4338 }
4339
4340 if (reenable_ips)
4341 hsw_enable_ips(intel_crtc);
4342}
4343
4344static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4345{
4346 if (!enable && intel_crtc->overlay) {
4347 struct drm_device *dev = intel_crtc->base.dev;
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350 mutex_lock(&dev->struct_mutex);
4351 dev_priv->mm.interruptible = false;
4352 (void) intel_overlay_switch_off(intel_crtc->overlay);
4353 dev_priv->mm.interruptible = true;
4354 mutex_unlock(&dev->struct_mutex);
4355 }
4356
4357 /* Let userspace switch the overlay on again. In most cases userspace
4358 * has to recompute where to put it anyway.
4359 */
4360}
4361
4362static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4363{
4364 struct drm_device *dev = crtc->dev;
4365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366 int pipe = intel_crtc->pipe;
4367
4368 intel_enable_primary_hw_plane(crtc->primary, crtc);
4369 intel_enable_sprite_planes(crtc);
4370 intel_crtc_update_cursor(crtc, true);
4371 intel_crtc_dpms_overlay(intel_crtc, true);
4372
4373 hsw_enable_ips(intel_crtc);
4374
4375 mutex_lock(&dev->struct_mutex);
4376 intel_fbc_update(dev);
4377 mutex_unlock(&dev->struct_mutex);
4378
4379 /*
4380 * FIXME: Once we grow proper nuclear flip support out of this we need
4381 * to compute the mask of flip planes precisely. For the time being
4382 * consider this a flip from a NULL plane.
4383 */
4384 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4385}
4386
4387static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4388{
4389 struct drm_device *dev = crtc->dev;
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392 int pipe = intel_crtc->pipe;
4393
4394 intel_crtc_wait_for_pending_flips(crtc);
4395
4396 if (dev_priv->fbc.crtc == intel_crtc)
4397 intel_fbc_disable(dev);
4398
4399 hsw_disable_ips(intel_crtc);
4400
4401 intel_crtc_dpms_overlay(intel_crtc, false);
4402 intel_crtc_update_cursor(crtc, false);
4403 intel_disable_sprite_planes(crtc);
4404 intel_disable_primary_hw_plane(crtc->primary, crtc);
4405
4406 /*
4407 * FIXME: Once we grow proper nuclear flip support out of this we need
4408 * to compute the mask of flip planes precisely. For the time being
4409 * consider this a flip to a NULL plane.
4410 */
4411 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4412}
4413
4414static void ironlake_crtc_enable(struct drm_crtc *crtc)
4415{
4416 struct drm_device *dev = crtc->dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4419 struct intel_encoder *encoder;
4420 int pipe = intel_crtc->pipe;
4421
4422 WARN_ON(!crtc->state->enable);
4423
4424 if (intel_crtc->active)
4425 return;
4426
4427 if (intel_crtc->config->has_pch_encoder)
4428 intel_prepare_shared_dpll(intel_crtc);
4429
4430 if (intel_crtc->config->has_dp_encoder)
4431 intel_dp_set_m_n(intel_crtc, M1_N1);
4432
4433 intel_set_pipe_timings(intel_crtc);
4434
4435 if (intel_crtc->config->has_pch_encoder) {
4436 intel_cpu_transcoder_set_m_n(intel_crtc,
4437 &intel_crtc->config->fdi_m_n, NULL);
4438 }
4439
4440 ironlake_set_pipeconf(crtc);
4441
4442 intel_crtc->active = true;
4443
4444 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4445 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4446
4447 for_each_encoder_on_crtc(dev, crtc, encoder)
4448 if (encoder->pre_enable)
4449 encoder->pre_enable(encoder);
4450
4451 if (intel_crtc->config->has_pch_encoder) {
4452 /* Note: FDI PLL enabling _must_ be done before we enable the
4453 * cpu pipes, hence this is separate from all the other fdi/pch
4454 * enabling. */
4455 ironlake_fdi_pll_enable(intel_crtc);
4456 } else {
4457 assert_fdi_tx_disabled(dev_priv, pipe);
4458 assert_fdi_rx_disabled(dev_priv, pipe);
4459 }
4460
4461 ironlake_pfit_enable(intel_crtc);
4462
4463 /*
4464 * On ILK+ LUT must be loaded before the pipe is running but with
4465 * clocks enabled
4466 */
4467 intel_crtc_load_lut(crtc);
4468
4469 intel_update_watermarks(crtc);
4470 intel_enable_pipe(intel_crtc);
4471
4472 if (intel_crtc->config->has_pch_encoder)
4473 ironlake_pch_enable(crtc);
4474
4475 assert_vblank_disabled(crtc);
4476 drm_crtc_vblank_on(crtc);
4477
4478 for_each_encoder_on_crtc(dev, crtc, encoder)
4479 encoder->enable(encoder);
4480
4481 if (HAS_PCH_CPT(dev))
4482 cpt_verify_modeset(dev, intel_crtc->pipe);
4483
4484 intel_crtc_enable_planes(crtc);
4485}
4486
4487/* IPS only exists on ULT machines and is tied to pipe A. */
4488static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4489{
4490 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4491}
4492
4493/*
4494 * This implements the workaround described in the "notes" section of the mode
4495 * set sequence documentation. When going from no pipes or single pipe to
4496 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4497 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4498 */
4499static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4500{
4501 struct drm_device *dev = crtc->base.dev;
4502 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4503
4504 /* We want to get the other_active_crtc only if there's only 1 other
4505 * active crtc. */
4506 for_each_intel_crtc(dev, crtc_it) {
4507 if (!crtc_it->active || crtc_it == crtc)
4508 continue;
4509
4510 if (other_active_crtc)
4511 return;
4512
4513 other_active_crtc = crtc_it;
4514 }
4515 if (!other_active_crtc)
4516 return;
4517
4518 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4519 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4520}
4521
4522static void haswell_crtc_enable(struct drm_crtc *crtc)
4523{
4524 struct drm_device *dev = crtc->dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4527 struct intel_encoder *encoder;
4528 int pipe = intel_crtc->pipe;
4529
4530 WARN_ON(!crtc->state->enable);
4531
4532 if (intel_crtc->active)
4533 return;
4534
4535 if (intel_crtc_to_shared_dpll(intel_crtc))
4536 intel_enable_shared_dpll(intel_crtc);
4537
4538 if (intel_crtc->config->has_dp_encoder)
4539 intel_dp_set_m_n(intel_crtc, M1_N1);
4540
4541 intel_set_pipe_timings(intel_crtc);
4542
4543 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4544 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4545 intel_crtc->config->pixel_multiplier - 1);
4546 }
4547
4548 if (intel_crtc->config->has_pch_encoder) {
4549 intel_cpu_transcoder_set_m_n(intel_crtc,
4550 &intel_crtc->config->fdi_m_n, NULL);
4551 }
4552
4553 haswell_set_pipeconf(crtc);
4554
4555 intel_set_pipe_csc(crtc);
4556
4557 intel_crtc->active = true;
4558
4559 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4560 for_each_encoder_on_crtc(dev, crtc, encoder)
4561 if (encoder->pre_enable)
4562 encoder->pre_enable(encoder);
4563
4564 if (intel_crtc->config->has_pch_encoder) {
4565 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4566 true);
4567 dev_priv->display.fdi_link_train(crtc);
4568 }
4569
4570 intel_ddi_enable_pipe_clock(intel_crtc);
4571
4572 if (IS_SKYLAKE(dev))
4573 skylake_pfit_enable(intel_crtc);
4574 else
4575 ironlake_pfit_enable(intel_crtc);
4576
4577 /*
4578 * On ILK+ LUT must be loaded before the pipe is running but with
4579 * clocks enabled
4580 */
4581 intel_crtc_load_lut(crtc);
4582
4583 intel_ddi_set_pipe_settings(crtc);
4584 intel_ddi_enable_transcoder_func(crtc);
4585
4586 intel_update_watermarks(crtc);
4587 intel_enable_pipe(intel_crtc);
4588
4589 if (intel_crtc->config->has_pch_encoder)
4590 lpt_pch_enable(crtc);
4591
4592 if (intel_crtc->config->dp_encoder_is_mst)
4593 intel_ddi_set_vc_payload_alloc(crtc, true);
4594
4595 assert_vblank_disabled(crtc);
4596 drm_crtc_vblank_on(crtc);
4597
4598 for_each_encoder_on_crtc(dev, crtc, encoder) {
4599 encoder->enable(encoder);
4600 intel_opregion_notify_encoder(encoder, true);
4601 }
4602
4603 /* If we change the relative order between pipe/planes enabling, we need
4604 * to change the workaround. */
4605 haswell_mode_set_planes_workaround(intel_crtc);
4606 intel_crtc_enable_planes(crtc);
4607}
4608
4609static void skylake_pfit_disable(struct intel_crtc *crtc)
4610{
4611 struct drm_device *dev = crtc->base.dev;
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613 int pipe = crtc->pipe;
4614
4615 /* To avoid upsetting the power well on haswell only disable the pfit if
4616 * it's in use. The hw state code will make sure we get this right. */
4617 if (crtc->config->pch_pfit.enabled) {
4618 I915_WRITE(PS_CTL(pipe), 0);
4619 I915_WRITE(PS_WIN_POS(pipe), 0);
4620 I915_WRITE(PS_WIN_SZ(pipe), 0);
4621 }
4622}
4623
4624static void ironlake_pfit_disable(struct intel_crtc *crtc)
4625{
4626 struct drm_device *dev = crtc->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 int pipe = crtc->pipe;
4629
4630 /* To avoid upsetting the power well on haswell only disable the pfit if
4631 * it's in use. The hw state code will make sure we get this right. */
4632 if (crtc->config->pch_pfit.enabled) {
4633 I915_WRITE(PF_CTL(pipe), 0);
4634 I915_WRITE(PF_WIN_POS(pipe), 0);
4635 I915_WRITE(PF_WIN_SZ(pipe), 0);
4636 }
4637}
4638
4639static void ironlake_crtc_disable(struct drm_crtc *crtc)
4640{
4641 struct drm_device *dev = crtc->dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4644 struct intel_encoder *encoder;
4645 int pipe = intel_crtc->pipe;
4646 u32 reg, temp;
4647
4648 if (!intel_crtc->active)
4649 return;
4650
4651 intel_crtc_disable_planes(crtc);
4652
4653 for_each_encoder_on_crtc(dev, crtc, encoder)
4654 encoder->disable(encoder);
4655
4656 drm_crtc_vblank_off(crtc);
4657 assert_vblank_disabled(crtc);
4658
4659 if (intel_crtc->config->has_pch_encoder)
4660 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4661
4662 intel_disable_pipe(intel_crtc);
4663
4664 ironlake_pfit_disable(intel_crtc);
4665
4666 for_each_encoder_on_crtc(dev, crtc, encoder)
4667 if (encoder->post_disable)
4668 encoder->post_disable(encoder);
4669
4670 if (intel_crtc->config->has_pch_encoder) {
4671 ironlake_fdi_disable(crtc);
4672
4673 ironlake_disable_pch_transcoder(dev_priv, pipe);
4674
4675 if (HAS_PCH_CPT(dev)) {
4676 /* disable TRANS_DP_CTL */
4677 reg = TRANS_DP_CTL(pipe);
4678 temp = I915_READ(reg);
4679 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4680 TRANS_DP_PORT_SEL_MASK);
4681 temp |= TRANS_DP_PORT_SEL_NONE;
4682 I915_WRITE(reg, temp);
4683
4684 /* disable DPLL_SEL */
4685 temp = I915_READ(PCH_DPLL_SEL);
4686 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4687 I915_WRITE(PCH_DPLL_SEL, temp);
4688 }
4689
4690 /* disable PCH DPLL */
4691 intel_disable_shared_dpll(intel_crtc);
4692
4693 ironlake_fdi_pll_disable(intel_crtc);
4694 }
4695
4696 intel_crtc->active = false;
4697 intel_update_watermarks(crtc);
4698
4699 mutex_lock(&dev->struct_mutex);
4700 intel_fbc_update(dev);
4701 mutex_unlock(&dev->struct_mutex);
4702}
4703
4704static void haswell_crtc_disable(struct drm_crtc *crtc)
4705{
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 struct intel_encoder *encoder;
4710 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4711
4712 if (!intel_crtc->active)
4713 return;
4714
4715 intel_crtc_disable_planes(crtc);
4716
4717 for_each_encoder_on_crtc(dev, crtc, encoder) {
4718 intel_opregion_notify_encoder(encoder, false);
4719 encoder->disable(encoder);
4720 }
4721
4722 drm_crtc_vblank_off(crtc);
4723 assert_vblank_disabled(crtc);
4724
4725 if (intel_crtc->config->has_pch_encoder)
4726 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4727 false);
4728 intel_disable_pipe(intel_crtc);
4729
4730 if (intel_crtc->config->dp_encoder_is_mst)
4731 intel_ddi_set_vc_payload_alloc(crtc, false);
4732
4733 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4734
4735 if (IS_SKYLAKE(dev))
4736 skylake_pfit_disable(intel_crtc);
4737 else
4738 ironlake_pfit_disable(intel_crtc);
4739
4740 intel_ddi_disable_pipe_clock(intel_crtc);
4741
4742 if (intel_crtc->config->has_pch_encoder) {
4743 lpt_disable_pch_transcoder(dev_priv);
4744 intel_ddi_fdi_disable(crtc);
4745 }
4746
4747 for_each_encoder_on_crtc(dev, crtc, encoder)
4748 if (encoder->post_disable)
4749 encoder->post_disable(encoder);
4750
4751 intel_crtc->active = false;
4752 intel_update_watermarks(crtc);
4753
4754 mutex_lock(&dev->struct_mutex);
4755 intel_fbc_update(dev);
4756 mutex_unlock(&dev->struct_mutex);
4757
4758 if (intel_crtc_to_shared_dpll(intel_crtc))
4759 intel_disable_shared_dpll(intel_crtc);
4760}
4761
4762static void ironlake_crtc_off(struct drm_crtc *crtc)
4763{
4764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4765 intel_put_shared_dpll(intel_crtc);
4766}
4767
4768
4769static void i9xx_pfit_enable(struct intel_crtc *crtc)
4770{
4771 struct drm_device *dev = crtc->base.dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct intel_crtc_state *pipe_config = crtc->config;
4774
4775 if (!pipe_config->gmch_pfit.control)
4776 return;
4777
4778 /*
4779 * The panel fitter should only be adjusted whilst the pipe is disabled,
4780 * according to register description and PRM.
4781 */
4782 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4783 assert_pipe_disabled(dev_priv, crtc->pipe);
4784
4785 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4786 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4787
4788 /* Border color in case we don't scale up to the full screen. Black by
4789 * default, change to something else for debugging. */
4790 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4791}
4792
4793static enum intel_display_power_domain port_to_power_domain(enum port port)
4794{
4795 switch (port) {
4796 case PORT_A:
4797 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4798 case PORT_B:
4799 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4800 case PORT_C:
4801 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4802 case PORT_D:
4803 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4804 default:
4805 WARN_ON_ONCE(1);
4806 return POWER_DOMAIN_PORT_OTHER;
4807 }
4808}
4809
4810#define for_each_power_domain(domain, mask) \
4811 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4812 if ((1 << (domain)) & (mask))
4813
4814enum intel_display_power_domain
4815intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4816{
4817 struct drm_device *dev = intel_encoder->base.dev;
4818 struct intel_digital_port *intel_dig_port;
4819
4820 switch (intel_encoder->type) {
4821 case INTEL_OUTPUT_UNKNOWN:
4822 /* Only DDI platforms should ever use this output type */
4823 WARN_ON_ONCE(!HAS_DDI(dev));
4824 case INTEL_OUTPUT_DISPLAYPORT:
4825 case INTEL_OUTPUT_HDMI:
4826 case INTEL_OUTPUT_EDP:
4827 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4828 return port_to_power_domain(intel_dig_port->port);
4829 case INTEL_OUTPUT_DP_MST:
4830 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4831 return port_to_power_domain(intel_dig_port->port);
4832 case INTEL_OUTPUT_ANALOG:
4833 return POWER_DOMAIN_PORT_CRT;
4834 case INTEL_OUTPUT_DSI:
4835 return POWER_DOMAIN_PORT_DSI;
4836 default:
4837 return POWER_DOMAIN_PORT_OTHER;
4838 }
4839}
4840
4841static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4842{
4843 struct drm_device *dev = crtc->dev;
4844 struct intel_encoder *intel_encoder;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846 enum pipe pipe = intel_crtc->pipe;
4847 unsigned long mask;
4848 enum transcoder transcoder;
4849
4850 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4851
4852 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4853 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4854 if (intel_crtc->config->pch_pfit.enabled ||
4855 intel_crtc->config->pch_pfit.force_thru)
4856 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4857
4858 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4859 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4860
4861 return mask;
4862}
4863
4864static void modeset_update_crtc_power_domains(struct drm_device *dev)
4865{
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4868 struct intel_crtc *crtc;
4869
4870 /*
4871 * First get all needed power domains, then put all unneeded, to avoid
4872 * any unnecessary toggling of the power wells.
4873 */
4874 for_each_intel_crtc(dev, crtc) {
4875 enum intel_display_power_domain domain;
4876
4877 if (!crtc->base.state->enable)
4878 continue;
4879
4880 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4881
4882 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4883 intel_display_power_get(dev_priv, domain);
4884 }
4885
4886 if (dev_priv->display.modeset_global_resources)
4887 dev_priv->display.modeset_global_resources(dev);
4888
4889 for_each_intel_crtc(dev, crtc) {
4890 enum intel_display_power_domain domain;
4891
4892 for_each_power_domain(domain, crtc->enabled_power_domains)
4893 intel_display_power_put(dev_priv, domain);
4894
4895 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4896 }
4897
4898 intel_display_set_init_power(dev_priv, false);
4899}
4900
4901/* returns HPLL frequency in kHz */
4902static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4903{
4904 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4905
4906 /* Obtain SKU information */
4907 mutex_lock(&dev_priv->dpio_lock);
4908 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4909 CCK_FUSE_HPLL_FREQ_MASK;
4910 mutex_unlock(&dev_priv->dpio_lock);
4911
4912 return vco_freq[hpll_freq] * 1000;
4913}
4914
4915static void vlv_update_cdclk(struct drm_device *dev)
4916{
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918
4919 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4920 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4921 dev_priv->vlv_cdclk_freq);
4922
4923 /*
4924 * Program the gmbus_freq based on the cdclk frequency.
4925 * BSpec erroneously claims we should aim for 4MHz, but
4926 * in fact 1MHz is the correct frequency.
4927 */
4928 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4929}
4930
4931/* Adjust CDclk dividers to allow high res or save power if possible */
4932static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4933{
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935 u32 val, cmd;
4936
4937 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4938
4939 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4940 cmd = 2;
4941 else if (cdclk == 266667)
4942 cmd = 1;
4943 else
4944 cmd = 0;
4945
4946 mutex_lock(&dev_priv->rps.hw_lock);
4947 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4948 val &= ~DSPFREQGUAR_MASK;
4949 val |= (cmd << DSPFREQGUAR_SHIFT);
4950 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4951 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4952 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4953 50)) {
4954 DRM_ERROR("timed out waiting for CDclk change\n");
4955 }
4956 mutex_unlock(&dev_priv->rps.hw_lock);
4957
4958 if (cdclk == 400000) {
4959 u32 divider;
4960
4961 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4962
4963 mutex_lock(&dev_priv->dpio_lock);
4964 /* adjust cdclk divider */
4965 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4966 val &= ~DISPLAY_FREQUENCY_VALUES;
4967 val |= divider;
4968 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4969
4970 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4971 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4972 50))
4973 DRM_ERROR("timed out waiting for CDclk change\n");
4974 mutex_unlock(&dev_priv->dpio_lock);
4975 }
4976
4977 mutex_lock(&dev_priv->dpio_lock);
4978 /* adjust self-refresh exit latency value */
4979 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4980 val &= ~0x7f;
4981
4982 /*
4983 * For high bandwidth configs, we set a higher latency in the bunit
4984 * so that the core display fetch happens in time to avoid underruns.
4985 */
4986 if (cdclk == 400000)
4987 val |= 4500 / 250; /* 4.5 usec */
4988 else
4989 val |= 3000 / 250; /* 3.0 usec */
4990 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4991 mutex_unlock(&dev_priv->dpio_lock);
4992
4993 vlv_update_cdclk(dev);
4994}
4995
4996static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4997{
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 u32 val, cmd;
5000
5001 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5002
5003 switch (cdclk) {
5004 case 333333:
5005 case 320000:
5006 case 266667:
5007 case 200000:
5008 break;
5009 default:
5010 MISSING_CASE(cdclk);
5011 return;
5012 }
5013
5014 /*
5015 * Specs are full of misinformation, but testing on actual
5016 * hardware has shown that we just need to write the desired
5017 * CCK divider into the Punit register.
5018 */
5019 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5020
5021 mutex_lock(&dev_priv->rps.hw_lock);
5022 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5023 val &= ~DSPFREQGUAR_MASK_CHV;
5024 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5025 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5026 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5027 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5028 50)) {
5029 DRM_ERROR("timed out waiting for CDclk change\n");
5030 }
5031 mutex_unlock(&dev_priv->rps.hw_lock);
5032
5033 vlv_update_cdclk(dev);
5034}
5035
5036static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5037 int max_pixclk)
5038{
5039 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5040 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5041
5042 /*
5043 * Really only a few cases to deal with, as only 4 CDclks are supported:
5044 * 200MHz
5045 * 267MHz
5046 * 320/333MHz (depends on HPLL freq)
5047 * 400MHz (VLV only)
5048 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5049 * of the lower bin and adjust if needed.
5050 *
5051 * We seem to get an unstable or solid color picture at 200MHz.
5052 * Not sure what's wrong. For now use 200MHz only when all pipes
5053 * are off.
5054 */
5055 if (!IS_CHERRYVIEW(dev_priv) &&
5056 max_pixclk > freq_320*limit/100)
5057 return 400000;
5058 else if (max_pixclk > 266667*limit/100)
5059 return freq_320;
5060 else if (max_pixclk > 0)
5061 return 266667;
5062 else
5063 return 200000;
5064}
5065
5066/* compute the max pixel clock for new configuration */
5067static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5068{
5069 struct drm_device *dev = dev_priv->dev;
5070 struct intel_crtc *intel_crtc;
5071 int max_pixclk = 0;
5072
5073 for_each_intel_crtc(dev, intel_crtc) {
5074 if (intel_crtc->new_enabled)
5075 max_pixclk = max(max_pixclk,
5076 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5077 }
5078
5079 return max_pixclk;
5080}
5081
5082static void valleyview_modeset_global_pipes(struct drm_device *dev,
5083 unsigned *prepare_pipes)
5084{
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 struct intel_crtc *intel_crtc;
5087 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5088
5089 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5090 dev_priv->vlv_cdclk_freq)
5091 return;
5092
5093 /* disable/enable all currently active pipes while we change cdclk */
5094 for_each_intel_crtc(dev, intel_crtc)
5095 if (intel_crtc->base.state->enable)
5096 *prepare_pipes |= (1 << intel_crtc->pipe);
5097}
5098
5099static void valleyview_modeset_global_resources(struct drm_device *dev)
5100{
5101 struct drm_i915_private *dev_priv = dev->dev_private;
5102 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5103 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5104
5105 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5106 /*
5107 * FIXME: We can end up here with all power domains off, yet
5108 * with a CDCLK frequency other than the minimum. To account
5109 * for this take the PIPE-A power domain, which covers the HW
5110 * blocks needed for the following programming. This can be
5111 * removed once it's guaranteed that we get here either with
5112 * the minimum CDCLK set, or the required power domains
5113 * enabled.
5114 */
5115 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5116
5117 if (IS_CHERRYVIEW(dev))
5118 cherryview_set_cdclk(dev, req_cdclk);
5119 else
5120 valleyview_set_cdclk(dev, req_cdclk);
5121
5122 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5123 }
5124}
5125
5126static void valleyview_crtc_enable(struct drm_crtc *crtc)
5127{
5128 struct drm_device *dev = crtc->dev;
5129 struct drm_i915_private *dev_priv = to_i915(dev);
5130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5131 struct intel_encoder *encoder;
5132 int pipe = intel_crtc->pipe;
5133 bool is_dsi;
5134
5135 WARN_ON(!crtc->state->enable);
5136
5137 if (intel_crtc->active)
5138 return;
5139
5140 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5141
5142 if (!is_dsi) {
5143 if (IS_CHERRYVIEW(dev))
5144 chv_prepare_pll(intel_crtc, intel_crtc->config);
5145 else
5146 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5147 }
5148
5149 if (intel_crtc->config->has_dp_encoder)
5150 intel_dp_set_m_n(intel_crtc, M1_N1);
5151
5152 intel_set_pipe_timings(intel_crtc);
5153
5154 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5156
5157 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5158 I915_WRITE(CHV_CANVAS(pipe), 0);
5159 }
5160
5161 i9xx_set_pipeconf(intel_crtc);
5162
5163 intel_crtc->active = true;
5164
5165 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5166
5167 for_each_encoder_on_crtc(dev, crtc, encoder)
5168 if (encoder->pre_pll_enable)
5169 encoder->pre_pll_enable(encoder);
5170
5171 if (!is_dsi) {
5172 if (IS_CHERRYVIEW(dev))
5173 chv_enable_pll(intel_crtc, intel_crtc->config);
5174 else
5175 vlv_enable_pll(intel_crtc, intel_crtc->config);
5176 }
5177
5178 for_each_encoder_on_crtc(dev, crtc, encoder)
5179 if (encoder->pre_enable)
5180 encoder->pre_enable(encoder);
5181
5182 i9xx_pfit_enable(intel_crtc);
5183
5184 intel_crtc_load_lut(crtc);
5185
5186 intel_update_watermarks(crtc);
5187 intel_enable_pipe(intel_crtc);
5188
5189 assert_vblank_disabled(crtc);
5190 drm_crtc_vblank_on(crtc);
5191
5192 for_each_encoder_on_crtc(dev, crtc, encoder)
5193 encoder->enable(encoder);
5194
5195 intel_crtc_enable_planes(crtc);
5196
5197 /* Underruns don't raise interrupts, so check manually. */
5198 i9xx_check_fifo_underruns(dev_priv);
5199}
5200
5201static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5202{
5203 struct drm_device *dev = crtc->base.dev;
5204 struct drm_i915_private *dev_priv = dev->dev_private;
5205
5206 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5207 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5208}
5209
5210static void i9xx_crtc_enable(struct drm_crtc *crtc)
5211{
5212 struct drm_device *dev = crtc->dev;
5213 struct drm_i915_private *dev_priv = to_i915(dev);
5214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5215 struct intel_encoder *encoder;
5216 int pipe = intel_crtc->pipe;
5217
5218 WARN_ON(!crtc->state->enable);
5219
5220 if (intel_crtc->active)
5221 return;
5222
5223 i9xx_set_pll_dividers(intel_crtc);
5224
5225 if (intel_crtc->config->has_dp_encoder)
5226 intel_dp_set_m_n(intel_crtc, M1_N1);
5227
5228 intel_set_pipe_timings(intel_crtc);
5229
5230 i9xx_set_pipeconf(intel_crtc);
5231
5232 intel_crtc->active = true;
5233
5234 if (!IS_GEN2(dev))
5235 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5236
5237 for_each_encoder_on_crtc(dev, crtc, encoder)
5238 if (encoder->pre_enable)
5239 encoder->pre_enable(encoder);
5240
5241 i9xx_enable_pll(intel_crtc);
5242
5243 i9xx_pfit_enable(intel_crtc);
5244
5245 intel_crtc_load_lut(crtc);
5246
5247 intel_update_watermarks(crtc);
5248 intel_enable_pipe(intel_crtc);
5249
5250 assert_vblank_disabled(crtc);
5251 drm_crtc_vblank_on(crtc);
5252
5253 for_each_encoder_on_crtc(dev, crtc, encoder)
5254 encoder->enable(encoder);
5255
5256 intel_crtc_enable_planes(crtc);
5257
5258 /*
5259 * Gen2 reports pipe underruns whenever all planes are disabled.
5260 * So don't enable underrun reporting before at least some planes
5261 * are enabled.
5262 * FIXME: Need to fix the logic to work when we turn off all planes
5263 * but leave the pipe running.
5264 */
5265 if (IS_GEN2(dev))
5266 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5267
5268 /* Underruns don't raise interrupts, so check manually. */
5269 i9xx_check_fifo_underruns(dev_priv);
5270}
5271
5272static void i9xx_pfit_disable(struct intel_crtc *crtc)
5273{
5274 struct drm_device *dev = crtc->base.dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276
5277 if (!crtc->config->gmch_pfit.control)
5278 return;
5279
5280 assert_pipe_disabled(dev_priv, crtc->pipe);
5281
5282 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5283 I915_READ(PFIT_CONTROL));
5284 I915_WRITE(PFIT_CONTROL, 0);
5285}
5286
5287static void i9xx_crtc_disable(struct drm_crtc *crtc)
5288{
5289 struct drm_device *dev = crtc->dev;
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5292 struct intel_encoder *encoder;
5293 int pipe = intel_crtc->pipe;
5294
5295 if (!intel_crtc->active)
5296 return;
5297
5298 /*
5299 * Gen2 reports pipe underruns whenever all planes are disabled.
5300 * So diasble underrun reporting before all the planes get disabled.
5301 * FIXME: Need to fix the logic to work when we turn off all planes
5302 * but leave the pipe running.
5303 */
5304 if (IS_GEN2(dev))
5305 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5306
5307 /*
5308 * Vblank time updates from the shadow to live plane control register
5309 * are blocked if the memory self-refresh mode is active at that
5310 * moment. So to make sure the plane gets truly disabled, disable
5311 * first the self-refresh mode. The self-refresh enable bit in turn
5312 * will be checked/applied by the HW only at the next frame start
5313 * event which is after the vblank start event, so we need to have a
5314 * wait-for-vblank between disabling the plane and the pipe.
5315 */
5316 intel_set_memory_cxsr(dev_priv, false);
5317 intel_crtc_disable_planes(crtc);
5318
5319 /*
5320 * On gen2 planes are double buffered but the pipe isn't, so we must
5321 * wait for planes to fully turn off before disabling the pipe.
5322 * We also need to wait on all gmch platforms because of the
5323 * self-refresh mode constraint explained above.
5324 */
5325 intel_wait_for_vblank(dev, pipe);
5326
5327 for_each_encoder_on_crtc(dev, crtc, encoder)
5328 encoder->disable(encoder);
5329
5330 drm_crtc_vblank_off(crtc);
5331 assert_vblank_disabled(crtc);
5332
5333 intel_disable_pipe(intel_crtc);
5334
5335 i9xx_pfit_disable(intel_crtc);
5336
5337 for_each_encoder_on_crtc(dev, crtc, encoder)
5338 if (encoder->post_disable)
5339 encoder->post_disable(encoder);
5340
5341 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5342 if (IS_CHERRYVIEW(dev))
5343 chv_disable_pll(dev_priv, pipe);
5344 else if (IS_VALLEYVIEW(dev))
5345 vlv_disable_pll(dev_priv, pipe);
5346 else
5347 i9xx_disable_pll(intel_crtc);
5348 }
5349
5350 if (!IS_GEN2(dev))
5351 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5352
5353 intel_crtc->active = false;
5354 intel_update_watermarks(crtc);
5355
5356 mutex_lock(&dev->struct_mutex);
5357 intel_fbc_update(dev);
5358 mutex_unlock(&dev->struct_mutex);
5359}
5360
5361static void i9xx_crtc_off(struct drm_crtc *crtc)
5362{
5363}
5364
5365/* Master function to enable/disable CRTC and corresponding power wells */
5366void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5367{
5368 struct drm_device *dev = crtc->dev;
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5371 enum intel_display_power_domain domain;
5372 unsigned long domains;
5373
5374 if (enable) {
5375 if (!intel_crtc->active) {
5376 domains = get_crtc_power_domains(crtc);
5377 for_each_power_domain(domain, domains)
5378 intel_display_power_get(dev_priv, domain);
5379 intel_crtc->enabled_power_domains = domains;
5380
5381 dev_priv->display.crtc_enable(crtc);
5382 }
5383 } else {
5384 if (intel_crtc->active) {
5385 dev_priv->display.crtc_disable(crtc);
5386
5387 domains = intel_crtc->enabled_power_domains;
5388 for_each_power_domain(domain, domains)
5389 intel_display_power_put(dev_priv, domain);
5390 intel_crtc->enabled_power_domains = 0;
5391 }
5392 }
5393}
5394
5395/**
5396 * Sets the power management mode of the pipe and plane.
5397 */
5398void intel_crtc_update_dpms(struct drm_crtc *crtc)
5399{
5400 struct drm_device *dev = crtc->dev;
5401 struct intel_encoder *intel_encoder;
5402 bool enable = false;
5403
5404 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5405 enable |= intel_encoder->connectors_active;
5406
5407 intel_crtc_control(crtc, enable);
5408}
5409
5410static void intel_crtc_disable(struct drm_crtc *crtc)
5411{
5412 struct drm_device *dev = crtc->dev;
5413 struct drm_connector *connector;
5414 struct drm_i915_private *dev_priv = dev->dev_private;
5415
5416 /* crtc should still be enabled when we disable it. */
5417 WARN_ON(!crtc->state->enable);
5418
5419 dev_priv->display.crtc_disable(crtc);
5420 dev_priv->display.off(crtc);
5421
5422 crtc->primary->funcs->disable_plane(crtc->primary);
5423
5424 /* Update computed state. */
5425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5426 if (!connector->encoder || !connector->encoder->crtc)
5427 continue;
5428
5429 if (connector->encoder->crtc != crtc)
5430 continue;
5431
5432 connector->dpms = DRM_MODE_DPMS_OFF;
5433 to_intel_encoder(connector->encoder)->connectors_active = false;
5434 }
5435}
5436
5437void intel_encoder_destroy(struct drm_encoder *encoder)
5438{
5439 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5440
5441 drm_encoder_cleanup(encoder);
5442 kfree(intel_encoder);
5443}
5444
5445/* Simple dpms helper for encoders with just one connector, no cloning and only
5446 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5447 * state of the entire output pipe. */
5448static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5449{
5450 if (mode == DRM_MODE_DPMS_ON) {
5451 encoder->connectors_active = true;
5452
5453 intel_crtc_update_dpms(encoder->base.crtc);
5454 } else {
5455 encoder->connectors_active = false;
5456
5457 intel_crtc_update_dpms(encoder->base.crtc);
5458 }
5459}
5460
5461/* Cross check the actual hw state with our own modeset state tracking (and it's
5462 * internal consistency). */
5463static void intel_connector_check_state(struct intel_connector *connector)
5464{
5465 if (connector->get_hw_state(connector)) {
5466 struct intel_encoder *encoder = connector->encoder;
5467 struct drm_crtc *crtc;
5468 bool encoder_enabled;
5469 enum pipe pipe;
5470
5471 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5472 connector->base.base.id,
5473 connector->base.name);
5474
5475 /* there is no real hw state for MST connectors */
5476 if (connector->mst_port)
5477 return;
5478
5479 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5480 "wrong connector dpms state\n");
5481 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5482 "active connector not linked to encoder\n");
5483
5484 if (encoder) {
5485 I915_STATE_WARN(!encoder->connectors_active,
5486 "encoder->connectors_active not set\n");
5487
5488 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5489 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5490 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5491 return;
5492
5493 crtc = encoder->base.crtc;
5494
5495 I915_STATE_WARN(!crtc->state->enable,
5496 "crtc not enabled\n");
5497 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5498 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5499 "encoder active on the wrong pipe\n");
5500 }
5501 }
5502}
5503
5504/* Even simpler default implementation, if there's really no special case to
5505 * consider. */
5506void intel_connector_dpms(struct drm_connector *connector, int mode)
5507{
5508 /* All the simple cases only support two dpms states. */
5509 if (mode != DRM_MODE_DPMS_ON)
5510 mode = DRM_MODE_DPMS_OFF;
5511
5512 if (mode == connector->dpms)
5513 return;
5514
5515 connector->dpms = mode;
5516
5517 /* Only need to change hw state when actually enabled */
5518 if (connector->encoder)
5519 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5520
5521 intel_modeset_check_state(connector->dev);
5522}
5523
5524/* Simple connector->get_hw_state implementation for encoders that support only
5525 * one connector and no cloning and hence the encoder state determines the state
5526 * of the connector. */
5527bool intel_connector_get_hw_state(struct intel_connector *connector)
5528{
5529 enum pipe pipe = 0;
5530 struct intel_encoder *encoder = connector->encoder;
5531
5532 return encoder->get_hw_state(encoder, &pipe);
5533}
5534
5535static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5536 struct intel_crtc_state *pipe_config)
5537{
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5539 struct intel_crtc *pipe_B_crtc =
5540 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5541
5542 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5543 pipe_name(pipe), pipe_config->fdi_lanes);
5544 if (pipe_config->fdi_lanes > 4) {
5545 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5546 pipe_name(pipe), pipe_config->fdi_lanes);
5547 return false;
5548 }
5549
5550 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5551 if (pipe_config->fdi_lanes > 2) {
5552 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5553 pipe_config->fdi_lanes);
5554 return false;
5555 } else {
5556 return true;
5557 }
5558 }
5559
5560 if (INTEL_INFO(dev)->num_pipes == 2)
5561 return true;
5562
5563 /* Ivybridge 3 pipe is really complicated */
5564 switch (pipe) {
5565 case PIPE_A:
5566 return true;
5567 case PIPE_B:
5568 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5569 pipe_config->fdi_lanes > 2) {
5570 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5571 pipe_name(pipe), pipe_config->fdi_lanes);
5572 return false;
5573 }
5574 return true;
5575 case PIPE_C:
5576 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5577 pipe_B_crtc->config->fdi_lanes <= 2) {
5578 if (pipe_config->fdi_lanes > 2) {
5579 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5580 pipe_name(pipe), pipe_config->fdi_lanes);
5581 return false;
5582 }
5583 } else {
5584 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5585 return false;
5586 }
5587 return true;
5588 default:
5589 BUG();
5590 }
5591}
5592
5593#define RETRY 1
5594static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5595 struct intel_crtc_state *pipe_config)
5596{
5597 struct drm_device *dev = intel_crtc->base.dev;
5598 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5599 int lane, link_bw, fdi_dotclock;
5600 bool setup_ok, needs_recompute = false;
5601
5602retry:
5603 /* FDI is a binary signal running at ~2.7GHz, encoding
5604 * each output octet as 10 bits. The actual frequency
5605 * is stored as a divider into a 100MHz clock, and the
5606 * mode pixel clock is stored in units of 1KHz.
5607 * Hence the bw of each lane in terms of the mode signal
5608 * is:
5609 */
5610 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5611
5612 fdi_dotclock = adjusted_mode->crtc_clock;
5613
5614 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5615 pipe_config->pipe_bpp);
5616
5617 pipe_config->fdi_lanes = lane;
5618
5619 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5620 link_bw, &pipe_config->fdi_m_n);
5621
5622 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5623 intel_crtc->pipe, pipe_config);
5624 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5625 pipe_config->pipe_bpp -= 2*3;
5626 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5627 pipe_config->pipe_bpp);
5628 needs_recompute = true;
5629 pipe_config->bw_constrained = true;
5630
5631 goto retry;
5632 }
5633
5634 if (needs_recompute)
5635 return RETRY;
5636
5637 return setup_ok ? 0 : -EINVAL;
5638}
5639
5640static void hsw_compute_ips_config(struct intel_crtc *crtc,
5641 struct intel_crtc_state *pipe_config)
5642{
5643 pipe_config->ips_enabled = i915.enable_ips &&
5644 hsw_crtc_supports_ips(crtc) &&
5645 pipe_config->pipe_bpp <= 24;
5646}
5647
5648static int intel_crtc_compute_config(struct intel_crtc *crtc,
5649 struct intel_crtc_state *pipe_config)
5650{
5651 struct drm_device *dev = crtc->base.dev;
5652 struct drm_i915_private *dev_priv = dev->dev_private;
5653 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5654
5655 /* FIXME should check pixel clock limits on all platforms */
5656 if (INTEL_INFO(dev)->gen < 4) {
5657 int clock_limit =
5658 dev_priv->display.get_display_clock_speed(dev);
5659
5660 /*
5661 * Enable pixel doubling when the dot clock
5662 * is > 90% of the (display) core speed.
5663 *
5664 * GDG double wide on either pipe,
5665 * otherwise pipe A only.
5666 */
5667 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5668 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5669 clock_limit *= 2;
5670 pipe_config->double_wide = true;
5671 }
5672
5673 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5674 return -EINVAL;
5675 }
5676
5677 /*
5678 * Pipe horizontal size must be even in:
5679 * - DVO ganged mode
5680 * - LVDS dual channel mode
5681 * - Double wide pipe
5682 */
5683 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5684 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5685 pipe_config->pipe_src_w &= ~1;
5686
5687 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5688 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5689 */
5690 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5691 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5692 return -EINVAL;
5693
5694 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5695 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5696 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5697 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5698 * for lvds. */
5699 pipe_config->pipe_bpp = 8*3;
5700 }
5701
5702 if (HAS_IPS(dev))
5703 hsw_compute_ips_config(crtc, pipe_config);
5704
5705 if (pipe_config->has_pch_encoder)
5706 return ironlake_fdi_compute_config(crtc, pipe_config);
5707
5708 return 0;
5709}
5710
5711static int valleyview_get_display_clock_speed(struct drm_device *dev)
5712{
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 u32 val;
5715 int divider;
5716
5717 if (dev_priv->hpll_freq == 0)
5718 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5719
5720 mutex_lock(&dev_priv->dpio_lock);
5721 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5722 mutex_unlock(&dev_priv->dpio_lock);
5723
5724 divider = val & DISPLAY_FREQUENCY_VALUES;
5725
5726 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5727 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5728 "cdclk change in progress\n");
5729
5730 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5731}
5732
5733static int i945_get_display_clock_speed(struct drm_device *dev)
5734{
5735 return 400000;
5736}
5737
5738static int i915_get_display_clock_speed(struct drm_device *dev)
5739{
5740 return 333000;
5741}
5742
5743static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5744{
5745 return 200000;
5746}
5747
5748static int pnv_get_display_clock_speed(struct drm_device *dev)
5749{
5750 u16 gcfgc = 0;
5751
5752 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5753
5754 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5755 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5756 return 267000;
5757 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5758 return 333000;
5759 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5760 return 444000;
5761 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5762 return 200000;
5763 default:
5764 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5765 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5766 return 133000;
5767 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5768 return 167000;
5769 }
5770}
5771
5772static int i915gm_get_display_clock_speed(struct drm_device *dev)
5773{
5774 u16 gcfgc = 0;
5775
5776 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5777
5778 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5779 return 133000;
5780 else {
5781 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5782 case GC_DISPLAY_CLOCK_333_MHZ:
5783 return 333000;
5784 default:
5785 case GC_DISPLAY_CLOCK_190_200_MHZ:
5786 return 190000;
5787 }
5788 }
5789}
5790
5791static int i865_get_display_clock_speed(struct drm_device *dev)
5792{
5793 return 266000;
5794}
5795
5796static int i855_get_display_clock_speed(struct drm_device *dev)
5797{
5798 u16 hpllcc = 0;
5799 /* Assume that the hardware is in the high speed state. This
5800 * should be the default.
5801 */
5802 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5803 case GC_CLOCK_133_200:
5804 case GC_CLOCK_100_200:
5805 return 200000;
5806 case GC_CLOCK_166_250:
5807 return 250000;
5808 case GC_CLOCK_100_133:
5809 return 133000;
5810 }
5811
5812 /* Shouldn't happen */
5813 return 0;
5814}
5815
5816static int i830_get_display_clock_speed(struct drm_device *dev)
5817{
5818 return 133000;
5819}
5820
5821static void
5822intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5823{
5824 while (*num > DATA_LINK_M_N_MASK ||
5825 *den > DATA_LINK_M_N_MASK) {
5826 *num >>= 1;
5827 *den >>= 1;
5828 }
5829}
5830
5831static void compute_m_n(unsigned int m, unsigned int n,
5832 uint32_t *ret_m, uint32_t *ret_n)
5833{
5834 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5835 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5836 intel_reduce_m_n_ratio(ret_m, ret_n);
5837}
5838
5839void
5840intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5841 int pixel_clock, int link_clock,
5842 struct intel_link_m_n *m_n)
5843{
5844 m_n->tu = 64;
5845
5846 compute_m_n(bits_per_pixel * pixel_clock,
5847 link_clock * nlanes * 8,
5848 &m_n->gmch_m, &m_n->gmch_n);
5849
5850 compute_m_n(pixel_clock, link_clock,
5851 &m_n->link_m, &m_n->link_n);
5852}
5853
5854static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5855{
5856 if (i915.panel_use_ssc >= 0)
5857 return i915.panel_use_ssc != 0;
5858 return dev_priv->vbt.lvds_use_ssc
5859 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5860}
5861
5862static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5863{
5864 struct drm_device *dev = crtc->base.dev;
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866 int refclk;
5867
5868 if (IS_VALLEYVIEW(dev)) {
5869 refclk = 100000;
5870 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5871 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5872 refclk = dev_priv->vbt.lvds_ssc_freq;
5873 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5874 } else if (!IS_GEN2(dev)) {
5875 refclk = 96000;
5876 } else {
5877 refclk = 48000;
5878 }
5879
5880 return refclk;
5881}
5882
5883static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5884{
5885 return (1 << dpll->n) << 16 | dpll->m2;
5886}
5887
5888static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5889{
5890 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5891}
5892
5893static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5894 struct intel_crtc_state *crtc_state,
5895 intel_clock_t *reduced_clock)
5896{
5897 struct drm_device *dev = crtc->base.dev;
5898 u32 fp, fp2 = 0;
5899
5900 if (IS_PINEVIEW(dev)) {
5901 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5902 if (reduced_clock)
5903 fp2 = pnv_dpll_compute_fp(reduced_clock);
5904 } else {
5905 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5906 if (reduced_clock)
5907 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5908 }
5909
5910 crtc_state->dpll_hw_state.fp0 = fp;
5911
5912 crtc->lowfreq_avail = false;
5913 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5914 reduced_clock && i915.powersave) {
5915 crtc_state->dpll_hw_state.fp1 = fp2;
5916 crtc->lowfreq_avail = true;
5917 } else {
5918 crtc_state->dpll_hw_state.fp1 = fp;
5919 }
5920}
5921
5922static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5923 pipe)
5924{
5925 u32 reg_val;
5926
5927 /*
5928 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5929 * and set it to a reasonable value instead.
5930 */
5931 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5932 reg_val &= 0xffffff00;
5933 reg_val |= 0x00000030;
5934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5935
5936 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5937 reg_val &= 0x8cffffff;
5938 reg_val = 0x8c000000;
5939 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5940
5941 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5942 reg_val &= 0xffffff00;
5943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5944
5945 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5946 reg_val &= 0x00ffffff;
5947 reg_val |= 0xb0000000;
5948 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5949}
5950
5951static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5952 struct intel_link_m_n *m_n)
5953{
5954 struct drm_device *dev = crtc->base.dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 int pipe = crtc->pipe;
5957
5958 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5959 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5960 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5961 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5962}
5963
5964static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5965 struct intel_link_m_n *m_n,
5966 struct intel_link_m_n *m2_n2)
5967{
5968 struct drm_device *dev = crtc->base.dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5970 int pipe = crtc->pipe;
5971 enum transcoder transcoder = crtc->config->cpu_transcoder;
5972
5973 if (INTEL_INFO(dev)->gen >= 5) {
5974 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5975 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5976 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5977 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5978 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5979 * for gen < 8) and if DRRS is supported (to make sure the
5980 * registers are not unnecessarily accessed).
5981 */
5982 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5983 crtc->config->has_drrs) {
5984 I915_WRITE(PIPE_DATA_M2(transcoder),
5985 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5986 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5987 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5988 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5989 }
5990 } else {
5991 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5992 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5993 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5994 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5995 }
5996}
5997
5998void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
5999{
6000 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6001
6002 if (m_n == M1_N1) {
6003 dp_m_n = &crtc->config->dp_m_n;
6004 dp_m2_n2 = &crtc->config->dp_m2_n2;
6005 } else if (m_n == M2_N2) {
6006
6007 /*
6008 * M2_N2 registers are not supported. Hence m2_n2 divider value
6009 * needs to be programmed into M1_N1.
6010 */
6011 dp_m_n = &crtc->config->dp_m2_n2;
6012 } else {
6013 DRM_ERROR("Unsupported divider value\n");
6014 return;
6015 }
6016
6017 if (crtc->config->has_pch_encoder)
6018 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6019 else
6020 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6021}
6022
6023static void vlv_update_pll(struct intel_crtc *crtc,
6024 struct intel_crtc_state *pipe_config)
6025{
6026 u32 dpll, dpll_md;
6027
6028 /*
6029 * Enable DPIO clock input. We should never disable the reference
6030 * clock for pipe B, since VGA hotplug / manual detection depends
6031 * on it.
6032 */
6033 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6034 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6035 /* We should never disable this, set it here for state tracking */
6036 if (crtc->pipe == PIPE_B)
6037 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6038 dpll |= DPLL_VCO_ENABLE;
6039 pipe_config->dpll_hw_state.dpll = dpll;
6040
6041 dpll_md = (pipe_config->pixel_multiplier - 1)
6042 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6043 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6044}
6045
6046static void vlv_prepare_pll(struct intel_crtc *crtc,
6047 const struct intel_crtc_state *pipe_config)
6048{
6049 struct drm_device *dev = crtc->base.dev;
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051 int pipe = crtc->pipe;
6052 u32 mdiv;
6053 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6054 u32 coreclk, reg_val;
6055
6056 mutex_lock(&dev_priv->dpio_lock);
6057
6058 bestn = pipe_config->dpll.n;
6059 bestm1 = pipe_config->dpll.m1;
6060 bestm2 = pipe_config->dpll.m2;
6061 bestp1 = pipe_config->dpll.p1;
6062 bestp2 = pipe_config->dpll.p2;
6063
6064 /* See eDP HDMI DPIO driver vbios notes doc */
6065
6066 /* PLL B needs special handling */
6067 if (pipe == PIPE_B)
6068 vlv_pllb_recal_opamp(dev_priv, pipe);
6069
6070 /* Set up Tx target for periodic Rcomp update */
6071 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6072
6073 /* Disable target IRef on PLL */
6074 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6075 reg_val &= 0x00ffffff;
6076 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6077
6078 /* Disable fast lock */
6079 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6080
6081 /* Set idtafcrecal before PLL is enabled */
6082 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6083 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6084 mdiv |= ((bestn << DPIO_N_SHIFT));
6085 mdiv |= (1 << DPIO_K_SHIFT);
6086
6087 /*
6088 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6089 * but we don't support that).
6090 * Note: don't use the DAC post divider as it seems unstable.
6091 */
6092 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6093 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6094
6095 mdiv |= DPIO_ENABLE_CALIBRATION;
6096 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6097
6098 /* Set HBR and RBR LPF coefficients */
6099 if (pipe_config->port_clock == 162000 ||
6100 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6101 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6102 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6103 0x009f0003);
6104 else
6105 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6106 0x00d0000f);
6107
6108 if (pipe_config->has_dp_encoder) {
6109 /* Use SSC source */
6110 if (pipe == PIPE_A)
6111 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6112 0x0df40000);
6113 else
6114 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6115 0x0df70000);
6116 } else { /* HDMI or VGA */
6117 /* Use bend source */
6118 if (pipe == PIPE_A)
6119 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6120 0x0df70000);
6121 else
6122 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6123 0x0df40000);
6124 }
6125
6126 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6127 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6129 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6130 coreclk |= 0x01000000;
6131 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6132
6133 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6134 mutex_unlock(&dev_priv->dpio_lock);
6135}
6136
6137static void chv_update_pll(struct intel_crtc *crtc,
6138 struct intel_crtc_state *pipe_config)
6139{
6140 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6141 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6142 DPLL_VCO_ENABLE;
6143 if (crtc->pipe != PIPE_A)
6144 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6145
6146 pipe_config->dpll_hw_state.dpll_md =
6147 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6148}
6149
6150static void chv_prepare_pll(struct intel_crtc *crtc,
6151 const struct intel_crtc_state *pipe_config)
6152{
6153 struct drm_device *dev = crtc->base.dev;
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 int pipe = crtc->pipe;
6156 int dpll_reg = DPLL(crtc->pipe);
6157 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6158 u32 loopfilter, intcoeff;
6159 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6160 int refclk;
6161
6162 bestn = pipe_config->dpll.n;
6163 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6164 bestm1 = pipe_config->dpll.m1;
6165 bestm2 = pipe_config->dpll.m2 >> 22;
6166 bestp1 = pipe_config->dpll.p1;
6167 bestp2 = pipe_config->dpll.p2;
6168
6169 /*
6170 * Enable Refclk and SSC
6171 */
6172 I915_WRITE(dpll_reg,
6173 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6174
6175 mutex_lock(&dev_priv->dpio_lock);
6176
6177 /* p1 and p2 divider */
6178 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6179 5 << DPIO_CHV_S1_DIV_SHIFT |
6180 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6181 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6182 1 << DPIO_CHV_K_DIV_SHIFT);
6183
6184 /* Feedback post-divider - m2 */
6185 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6186
6187 /* Feedback refclk divider - n and m1 */
6188 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6189 DPIO_CHV_M1_DIV_BY_2 |
6190 1 << DPIO_CHV_N_DIV_SHIFT);
6191
6192 /* M2 fraction division */
6193 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6194
6195 /* M2 fraction division enable */
6196 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6197 DPIO_CHV_FRAC_DIV_EN |
6198 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6199
6200 /* Loop filter */
6201 refclk = i9xx_get_refclk(crtc, 0);
6202 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6203 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6204 if (refclk == 100000)
6205 intcoeff = 11;
6206 else if (refclk == 38400)
6207 intcoeff = 10;
6208 else
6209 intcoeff = 9;
6210 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6211 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6212
6213 /* AFC Recal */
6214 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6215 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6216 DPIO_AFC_RECAL);
6217
6218 mutex_unlock(&dev_priv->dpio_lock);
6219}
6220
6221/**
6222 * vlv_force_pll_on - forcibly enable just the PLL
6223 * @dev_priv: i915 private structure
6224 * @pipe: pipe PLL to enable
6225 * @dpll: PLL configuration
6226 *
6227 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6228 * in cases where we need the PLL enabled even when @pipe is not going to
6229 * be enabled.
6230 */
6231void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6232 const struct dpll *dpll)
6233{
6234 struct intel_crtc *crtc =
6235 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6236 struct intel_crtc_state pipe_config = {
6237 .pixel_multiplier = 1,
6238 .dpll = *dpll,
6239 };
6240
6241 if (IS_CHERRYVIEW(dev)) {
6242 chv_update_pll(crtc, &pipe_config);
6243 chv_prepare_pll(crtc, &pipe_config);
6244 chv_enable_pll(crtc, &pipe_config);
6245 } else {
6246 vlv_update_pll(crtc, &pipe_config);
6247 vlv_prepare_pll(crtc, &pipe_config);
6248 vlv_enable_pll(crtc, &pipe_config);
6249 }
6250}
6251
6252/**
6253 * vlv_force_pll_off - forcibly disable just the PLL
6254 * @dev_priv: i915 private structure
6255 * @pipe: pipe PLL to disable
6256 *
6257 * Disable the PLL for @pipe. To be used in cases where we need
6258 * the PLL enabled even when @pipe is not going to be enabled.
6259 */
6260void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6261{
6262 if (IS_CHERRYVIEW(dev))
6263 chv_disable_pll(to_i915(dev), pipe);
6264 else
6265 vlv_disable_pll(to_i915(dev), pipe);
6266}
6267
6268static void i9xx_update_pll(struct intel_crtc *crtc,
6269 struct intel_crtc_state *crtc_state,
6270 intel_clock_t *reduced_clock,
6271 int num_connectors)
6272{
6273 struct drm_device *dev = crtc->base.dev;
6274 struct drm_i915_private *dev_priv = dev->dev_private;
6275 u32 dpll;
6276 bool is_sdvo;
6277 struct dpll *clock = &crtc_state->dpll;
6278
6279 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6280
6281 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6282 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6283
6284 dpll = DPLL_VGA_MODE_DIS;
6285
6286 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6287 dpll |= DPLLB_MODE_LVDS;
6288 else
6289 dpll |= DPLLB_MODE_DAC_SERIAL;
6290
6291 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6292 dpll |= (crtc_state->pixel_multiplier - 1)
6293 << SDVO_MULTIPLIER_SHIFT_HIRES;
6294 }
6295
6296 if (is_sdvo)
6297 dpll |= DPLL_SDVO_HIGH_SPEED;
6298
6299 if (crtc_state->has_dp_encoder)
6300 dpll |= DPLL_SDVO_HIGH_SPEED;
6301
6302 /* compute bitmask from p1 value */
6303 if (IS_PINEVIEW(dev))
6304 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6305 else {
6306 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6307 if (IS_G4X(dev) && reduced_clock)
6308 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6309 }
6310 switch (clock->p2) {
6311 case 5:
6312 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6313 break;
6314 case 7:
6315 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6316 break;
6317 case 10:
6318 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6319 break;
6320 case 14:
6321 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6322 break;
6323 }
6324 if (INTEL_INFO(dev)->gen >= 4)
6325 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6326
6327 if (crtc_state->sdvo_tv_clock)
6328 dpll |= PLL_REF_INPUT_TVCLKINBC;
6329 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6330 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6331 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6332 else
6333 dpll |= PLL_REF_INPUT_DREFCLK;
6334
6335 dpll |= DPLL_VCO_ENABLE;
6336 crtc_state->dpll_hw_state.dpll = dpll;
6337
6338 if (INTEL_INFO(dev)->gen >= 4) {
6339 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6340 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6341 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6342 }
6343}
6344
6345static void i8xx_update_pll(struct intel_crtc *crtc,
6346 struct intel_crtc_state *crtc_state,
6347 intel_clock_t *reduced_clock,
6348 int num_connectors)
6349{
6350 struct drm_device *dev = crtc->base.dev;
6351 struct drm_i915_private *dev_priv = dev->dev_private;
6352 u32 dpll;
6353 struct dpll *clock = &crtc_state->dpll;
6354
6355 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6356
6357 dpll = DPLL_VGA_MODE_DIS;
6358
6359 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6360 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6361 } else {
6362 if (clock->p1 == 2)
6363 dpll |= PLL_P1_DIVIDE_BY_TWO;
6364 else
6365 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6366 if (clock->p2 == 4)
6367 dpll |= PLL_P2_DIVIDE_BY_4;
6368 }
6369
6370 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6371 dpll |= DPLL_DVO_2X_MODE;
6372
6373 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6374 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6375 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6376 else
6377 dpll |= PLL_REF_INPUT_DREFCLK;
6378
6379 dpll |= DPLL_VCO_ENABLE;
6380 crtc_state->dpll_hw_state.dpll = dpll;
6381}
6382
6383static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6384{
6385 struct drm_device *dev = intel_crtc->base.dev;
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6387 enum pipe pipe = intel_crtc->pipe;
6388 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6389 struct drm_display_mode *adjusted_mode =
6390 &intel_crtc->config->base.adjusted_mode;
6391 uint32_t crtc_vtotal, crtc_vblank_end;
6392 int vsyncshift = 0;
6393
6394 /* We need to be careful not to changed the adjusted mode, for otherwise
6395 * the hw state checker will get angry at the mismatch. */
6396 crtc_vtotal = adjusted_mode->crtc_vtotal;
6397 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6398
6399 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6400 /* the chip adds 2 halflines automatically */
6401 crtc_vtotal -= 1;
6402 crtc_vblank_end -= 1;
6403
6404 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6405 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6406 else
6407 vsyncshift = adjusted_mode->crtc_hsync_start -
6408 adjusted_mode->crtc_htotal / 2;
6409 if (vsyncshift < 0)
6410 vsyncshift += adjusted_mode->crtc_htotal;
6411 }
6412
6413 if (INTEL_INFO(dev)->gen > 3)
6414 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6415
6416 I915_WRITE(HTOTAL(cpu_transcoder),
6417 (adjusted_mode->crtc_hdisplay - 1) |
6418 ((adjusted_mode->crtc_htotal - 1) << 16));
6419 I915_WRITE(HBLANK(cpu_transcoder),
6420 (adjusted_mode->crtc_hblank_start - 1) |
6421 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6422 I915_WRITE(HSYNC(cpu_transcoder),
6423 (adjusted_mode->crtc_hsync_start - 1) |
6424 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6425
6426 I915_WRITE(VTOTAL(cpu_transcoder),
6427 (adjusted_mode->crtc_vdisplay - 1) |
6428 ((crtc_vtotal - 1) << 16));
6429 I915_WRITE(VBLANK(cpu_transcoder),
6430 (adjusted_mode->crtc_vblank_start - 1) |
6431 ((crtc_vblank_end - 1) << 16));
6432 I915_WRITE(VSYNC(cpu_transcoder),
6433 (adjusted_mode->crtc_vsync_start - 1) |
6434 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6435
6436 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6437 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6438 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6439 * bits. */
6440 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6441 (pipe == PIPE_B || pipe == PIPE_C))
6442 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6443
6444 /* pipesrc controls the size that is scaled from, which should
6445 * always be the user's requested size.
6446 */
6447 I915_WRITE(PIPESRC(pipe),
6448 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6449 (intel_crtc->config->pipe_src_h - 1));
6450}
6451
6452static void intel_get_pipe_timings(struct intel_crtc *crtc,
6453 struct intel_crtc_state *pipe_config)
6454{
6455 struct drm_device *dev = crtc->base.dev;
6456 struct drm_i915_private *dev_priv = dev->dev_private;
6457 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6458 uint32_t tmp;
6459
6460 tmp = I915_READ(HTOTAL(cpu_transcoder));
6461 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6462 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6463 tmp = I915_READ(HBLANK(cpu_transcoder));
6464 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6465 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6466 tmp = I915_READ(HSYNC(cpu_transcoder));
6467 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6468 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6469
6470 tmp = I915_READ(VTOTAL(cpu_transcoder));
6471 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6472 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6473 tmp = I915_READ(VBLANK(cpu_transcoder));
6474 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6475 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6476 tmp = I915_READ(VSYNC(cpu_transcoder));
6477 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6478 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6479
6480 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6481 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6482 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6483 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6484 }
6485
6486 tmp = I915_READ(PIPESRC(crtc->pipe));
6487 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6488 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6489
6490 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6491 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6492}
6493
6494void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6495 struct intel_crtc_state *pipe_config)
6496{
6497 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6498 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6499 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6500 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6501
6502 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6503 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6504 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6505 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6506
6507 mode->flags = pipe_config->base.adjusted_mode.flags;
6508
6509 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6510 mode->flags |= pipe_config->base.adjusted_mode.flags;
6511}
6512
6513static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6514{
6515 struct drm_device *dev = intel_crtc->base.dev;
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 uint32_t pipeconf;
6518
6519 pipeconf = 0;
6520
6521 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6522 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6523 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6524
6525 if (intel_crtc->config->double_wide)
6526 pipeconf |= PIPECONF_DOUBLE_WIDE;
6527
6528 /* only g4x and later have fancy bpc/dither controls */
6529 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6530 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6531 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6532 pipeconf |= PIPECONF_DITHER_EN |
6533 PIPECONF_DITHER_TYPE_SP;
6534
6535 switch (intel_crtc->config->pipe_bpp) {
6536 case 18:
6537 pipeconf |= PIPECONF_6BPC;
6538 break;
6539 case 24:
6540 pipeconf |= PIPECONF_8BPC;
6541 break;
6542 case 30:
6543 pipeconf |= PIPECONF_10BPC;
6544 break;
6545 default:
6546 /* Case prevented by intel_choose_pipe_bpp_dither. */
6547 BUG();
6548 }
6549 }
6550
6551 if (HAS_PIPE_CXSR(dev)) {
6552 if (intel_crtc->lowfreq_avail) {
6553 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6554 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6555 } else {
6556 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6557 }
6558 }
6559
6560 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6561 if (INTEL_INFO(dev)->gen < 4 ||
6562 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6563 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6564 else
6565 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6566 } else
6567 pipeconf |= PIPECONF_PROGRESSIVE;
6568
6569 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6570 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6571
6572 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6573 POSTING_READ(PIPECONF(intel_crtc->pipe));
6574}
6575
6576static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6577 struct intel_crtc_state *crtc_state)
6578{
6579 struct drm_device *dev = crtc->base.dev;
6580 struct drm_i915_private *dev_priv = dev->dev_private;
6581 int refclk, num_connectors = 0;
6582 intel_clock_t clock, reduced_clock;
6583 bool ok, has_reduced_clock = false;
6584 bool is_lvds = false, is_dsi = false;
6585 struct intel_encoder *encoder;
6586 const intel_limit_t *limit;
6587
6588 for_each_intel_encoder(dev, encoder) {
6589 if (encoder->new_crtc != crtc)
6590 continue;
6591
6592 switch (encoder->type) {
6593 case INTEL_OUTPUT_LVDS:
6594 is_lvds = true;
6595 break;
6596 case INTEL_OUTPUT_DSI:
6597 is_dsi = true;
6598 break;
6599 default:
6600 break;
6601 }
6602
6603 num_connectors++;
6604 }
6605
6606 if (is_dsi)
6607 return 0;
6608
6609 if (!crtc_state->clock_set) {
6610 refclk = i9xx_get_refclk(crtc, num_connectors);
6611
6612 /*
6613 * Returns a set of divisors for the desired target clock with
6614 * the given refclk, or FALSE. The returned values represent
6615 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6616 * 2) / p1 / p2.
6617 */
6618 limit = intel_limit(crtc, refclk);
6619 ok = dev_priv->display.find_dpll(limit, crtc,
6620 crtc_state->port_clock,
6621 refclk, NULL, &clock);
6622 if (!ok) {
6623 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6624 return -EINVAL;
6625 }
6626
6627 if (is_lvds && dev_priv->lvds_downclock_avail) {
6628 /*
6629 * Ensure we match the reduced clock's P to the target
6630 * clock. If the clocks don't match, we can't switch
6631 * the display clock by using the FP0/FP1. In such case
6632 * we will disable the LVDS downclock feature.
6633 */
6634 has_reduced_clock =
6635 dev_priv->display.find_dpll(limit, crtc,
6636 dev_priv->lvds_downclock,
6637 refclk, &clock,
6638 &reduced_clock);
6639 }
6640 /* Compat-code for transition, will disappear. */
6641 crtc_state->dpll.n = clock.n;
6642 crtc_state->dpll.m1 = clock.m1;
6643 crtc_state->dpll.m2 = clock.m2;
6644 crtc_state->dpll.p1 = clock.p1;
6645 crtc_state->dpll.p2 = clock.p2;
6646 }
6647
6648 if (IS_GEN2(dev)) {
6649 i8xx_update_pll(crtc, crtc_state,
6650 has_reduced_clock ? &reduced_clock : NULL,
6651 num_connectors);
6652 } else if (IS_CHERRYVIEW(dev)) {
6653 chv_update_pll(crtc, crtc_state);
6654 } else if (IS_VALLEYVIEW(dev)) {
6655 vlv_update_pll(crtc, crtc_state);
6656 } else {
6657 i9xx_update_pll(crtc, crtc_state,
6658 has_reduced_clock ? &reduced_clock : NULL,
6659 num_connectors);
6660 }
6661
6662 return 0;
6663}
6664
6665static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6666 struct intel_crtc_state *pipe_config)
6667{
6668 struct drm_device *dev = crtc->base.dev;
6669 struct drm_i915_private *dev_priv = dev->dev_private;
6670 uint32_t tmp;
6671
6672 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6673 return;
6674
6675 tmp = I915_READ(PFIT_CONTROL);
6676 if (!(tmp & PFIT_ENABLE))
6677 return;
6678
6679 /* Check whether the pfit is attached to our pipe. */
6680 if (INTEL_INFO(dev)->gen < 4) {
6681 if (crtc->pipe != PIPE_B)
6682 return;
6683 } else {
6684 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6685 return;
6686 }
6687
6688 pipe_config->gmch_pfit.control = tmp;
6689 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6690 if (INTEL_INFO(dev)->gen < 5)
6691 pipe_config->gmch_pfit.lvds_border_bits =
6692 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6693}
6694
6695static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6696 struct intel_crtc_state *pipe_config)
6697{
6698 struct drm_device *dev = crtc->base.dev;
6699 struct drm_i915_private *dev_priv = dev->dev_private;
6700 int pipe = pipe_config->cpu_transcoder;
6701 intel_clock_t clock;
6702 u32 mdiv;
6703 int refclk = 100000;
6704
6705 /* In case of MIPI DPLL will not even be used */
6706 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6707 return;
6708
6709 mutex_lock(&dev_priv->dpio_lock);
6710 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6711 mutex_unlock(&dev_priv->dpio_lock);
6712
6713 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6714 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6715 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6716 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6717 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6718
6719 vlv_clock(refclk, &clock);
6720
6721 /* clock.dot is the fast clock */
6722 pipe_config->port_clock = clock.dot / 5;
6723}
6724
6725static void
6726i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6727 struct intel_initial_plane_config *plane_config)
6728{
6729 struct drm_device *dev = crtc->base.dev;
6730 struct drm_i915_private *dev_priv = dev->dev_private;
6731 u32 val, base, offset;
6732 int pipe = crtc->pipe, plane = crtc->plane;
6733 int fourcc, pixel_format;
6734 int aligned_height;
6735 struct drm_framebuffer *fb;
6736 struct intel_framebuffer *intel_fb;
6737
6738 val = I915_READ(DSPCNTR(plane));
6739 if (!(val & DISPLAY_PLANE_ENABLE))
6740 return;
6741
6742 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6743 if (!intel_fb) {
6744 DRM_DEBUG_KMS("failed to alloc fb\n");
6745 return;
6746 }
6747
6748 fb = &intel_fb->base;
6749
6750 if (INTEL_INFO(dev)->gen >= 4) {
6751 if (val & DISPPLANE_TILED) {
6752 plane_config->tiling = I915_TILING_X;
6753 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6754 }
6755 }
6756
6757 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6758 fourcc = i9xx_format_to_fourcc(pixel_format);
6759 fb->pixel_format = fourcc;
6760 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6761
6762 if (INTEL_INFO(dev)->gen >= 4) {
6763 if (plane_config->tiling)
6764 offset = I915_READ(DSPTILEOFF(plane));
6765 else
6766 offset = I915_READ(DSPLINOFF(plane));
6767 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6768 } else {
6769 base = I915_READ(DSPADDR(plane));
6770 }
6771 plane_config->base = base;
6772
6773 val = I915_READ(PIPESRC(pipe));
6774 fb->width = ((val >> 16) & 0xfff) + 1;
6775 fb->height = ((val >> 0) & 0xfff) + 1;
6776
6777 val = I915_READ(DSPSTRIDE(pipe));
6778 fb->pitches[0] = val & 0xffffffc0;
6779
6780 aligned_height = intel_fb_align_height(dev, fb->height,
6781 fb->pixel_format,
6782 fb->modifier[0]);
6783
6784 plane_config->size = fb->pitches[0] * aligned_height;
6785
6786 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6787 pipe_name(pipe), plane, fb->width, fb->height,
6788 fb->bits_per_pixel, base, fb->pitches[0],
6789 plane_config->size);
6790
6791 plane_config->fb = intel_fb;
6792}
6793
6794static void chv_crtc_clock_get(struct intel_crtc *crtc,
6795 struct intel_crtc_state *pipe_config)
6796{
6797 struct drm_device *dev = crtc->base.dev;
6798 struct drm_i915_private *dev_priv = dev->dev_private;
6799 int pipe = pipe_config->cpu_transcoder;
6800 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6801 intel_clock_t clock;
6802 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6803 int refclk = 100000;
6804
6805 mutex_lock(&dev_priv->dpio_lock);
6806 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6807 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6808 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6809 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6810 mutex_unlock(&dev_priv->dpio_lock);
6811
6812 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6813 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6814 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6815 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6816 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6817
6818 chv_clock(refclk, &clock);
6819
6820 /* clock.dot is the fast clock */
6821 pipe_config->port_clock = clock.dot / 5;
6822}
6823
6824static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6825 struct intel_crtc_state *pipe_config)
6826{
6827 struct drm_device *dev = crtc->base.dev;
6828 struct drm_i915_private *dev_priv = dev->dev_private;
6829 uint32_t tmp;
6830
6831 if (!intel_display_power_is_enabled(dev_priv,
6832 POWER_DOMAIN_PIPE(crtc->pipe)))
6833 return false;
6834
6835 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6836 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6837
6838 tmp = I915_READ(PIPECONF(crtc->pipe));
6839 if (!(tmp & PIPECONF_ENABLE))
6840 return false;
6841
6842 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6843 switch (tmp & PIPECONF_BPC_MASK) {
6844 case PIPECONF_6BPC:
6845 pipe_config->pipe_bpp = 18;
6846 break;
6847 case PIPECONF_8BPC:
6848 pipe_config->pipe_bpp = 24;
6849 break;
6850 case PIPECONF_10BPC:
6851 pipe_config->pipe_bpp = 30;
6852 break;
6853 default:
6854 break;
6855 }
6856 }
6857
6858 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6859 pipe_config->limited_color_range = true;
6860
6861 if (INTEL_INFO(dev)->gen < 4)
6862 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6863
6864 intel_get_pipe_timings(crtc, pipe_config);
6865
6866 i9xx_get_pfit_config(crtc, pipe_config);
6867
6868 if (INTEL_INFO(dev)->gen >= 4) {
6869 tmp = I915_READ(DPLL_MD(crtc->pipe));
6870 pipe_config->pixel_multiplier =
6871 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6872 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6873 pipe_config->dpll_hw_state.dpll_md = tmp;
6874 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6875 tmp = I915_READ(DPLL(crtc->pipe));
6876 pipe_config->pixel_multiplier =
6877 ((tmp & SDVO_MULTIPLIER_MASK)
6878 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6879 } else {
6880 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6881 * port and will be fixed up in the encoder->get_config
6882 * function. */
6883 pipe_config->pixel_multiplier = 1;
6884 }
6885 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6886 if (!IS_VALLEYVIEW(dev)) {
6887 /*
6888 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6889 * on 830. Filter it out here so that we don't
6890 * report errors due to that.
6891 */
6892 if (IS_I830(dev))
6893 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6894
6895 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6896 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6897 } else {
6898 /* Mask out read-only status bits. */
6899 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6900 DPLL_PORTC_READY_MASK |
6901 DPLL_PORTB_READY_MASK);
6902 }
6903
6904 if (IS_CHERRYVIEW(dev))
6905 chv_crtc_clock_get(crtc, pipe_config);
6906 else if (IS_VALLEYVIEW(dev))
6907 vlv_crtc_clock_get(crtc, pipe_config);
6908 else
6909 i9xx_crtc_clock_get(crtc, pipe_config);
6910
6911 return true;
6912}
6913
6914static void ironlake_init_pch_refclk(struct drm_device *dev)
6915{
6916 struct drm_i915_private *dev_priv = dev->dev_private;
6917 struct intel_encoder *encoder;
6918 u32 val, final;
6919 bool has_lvds = false;
6920 bool has_cpu_edp = false;
6921 bool has_panel = false;
6922 bool has_ck505 = false;
6923 bool can_ssc = false;
6924
6925 /* We need to take the global config into account */
6926 for_each_intel_encoder(dev, encoder) {
6927 switch (encoder->type) {
6928 case INTEL_OUTPUT_LVDS:
6929 has_panel = true;
6930 has_lvds = true;
6931 break;
6932 case INTEL_OUTPUT_EDP:
6933 has_panel = true;
6934 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6935 has_cpu_edp = true;
6936 break;
6937 default:
6938 break;
6939 }
6940 }
6941
6942 if (HAS_PCH_IBX(dev)) {
6943 has_ck505 = dev_priv->vbt.display_clock_mode;
6944 can_ssc = has_ck505;
6945 } else {
6946 has_ck505 = false;
6947 can_ssc = true;
6948 }
6949
6950 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6951 has_panel, has_lvds, has_ck505);
6952
6953 /* Ironlake: try to setup display ref clock before DPLL
6954 * enabling. This is only under driver's control after
6955 * PCH B stepping, previous chipset stepping should be
6956 * ignoring this setting.
6957 */
6958 val = I915_READ(PCH_DREF_CONTROL);
6959
6960 /* As we must carefully and slowly disable/enable each source in turn,
6961 * compute the final state we want first and check if we need to
6962 * make any changes at all.
6963 */
6964 final = val;
6965 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6966 if (has_ck505)
6967 final |= DREF_NONSPREAD_CK505_ENABLE;
6968 else
6969 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6970
6971 final &= ~DREF_SSC_SOURCE_MASK;
6972 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6973 final &= ~DREF_SSC1_ENABLE;
6974
6975 if (has_panel) {
6976 final |= DREF_SSC_SOURCE_ENABLE;
6977
6978 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6979 final |= DREF_SSC1_ENABLE;
6980
6981 if (has_cpu_edp) {
6982 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6983 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6984 else
6985 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6986 } else
6987 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6988 } else {
6989 final |= DREF_SSC_SOURCE_DISABLE;
6990 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6991 }
6992
6993 if (final == val)
6994 return;
6995
6996 /* Always enable nonspread source */
6997 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6998
6999 if (has_ck505)
7000 val |= DREF_NONSPREAD_CK505_ENABLE;
7001 else
7002 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7003
7004 if (has_panel) {
7005 val &= ~DREF_SSC_SOURCE_MASK;
7006 val |= DREF_SSC_SOURCE_ENABLE;
7007
7008 /* SSC must be turned on before enabling the CPU output */
7009 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7010 DRM_DEBUG_KMS("Using SSC on panel\n");
7011 val |= DREF_SSC1_ENABLE;
7012 } else
7013 val &= ~DREF_SSC1_ENABLE;
7014
7015 /* Get SSC going before enabling the outputs */
7016 I915_WRITE(PCH_DREF_CONTROL, val);
7017 POSTING_READ(PCH_DREF_CONTROL);
7018 udelay(200);
7019
7020 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7021
7022 /* Enable CPU source on CPU attached eDP */
7023 if (has_cpu_edp) {
7024 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7025 DRM_DEBUG_KMS("Using SSC on eDP\n");
7026 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7027 } else
7028 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7029 } else
7030 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7031
7032 I915_WRITE(PCH_DREF_CONTROL, val);
7033 POSTING_READ(PCH_DREF_CONTROL);
7034 udelay(200);
7035 } else {
7036 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7037
7038 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7039
7040 /* Turn off CPU output */
7041 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7042
7043 I915_WRITE(PCH_DREF_CONTROL, val);
7044 POSTING_READ(PCH_DREF_CONTROL);
7045 udelay(200);
7046
7047 /* Turn off the SSC source */
7048 val &= ~DREF_SSC_SOURCE_MASK;
7049 val |= DREF_SSC_SOURCE_DISABLE;
7050
7051 /* Turn off SSC1 */
7052 val &= ~DREF_SSC1_ENABLE;
7053
7054 I915_WRITE(PCH_DREF_CONTROL, val);
7055 POSTING_READ(PCH_DREF_CONTROL);
7056 udelay(200);
7057 }
7058
7059 BUG_ON(val != final);
7060}
7061
7062static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7063{
7064 uint32_t tmp;
7065
7066 tmp = I915_READ(SOUTH_CHICKEN2);
7067 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7068 I915_WRITE(SOUTH_CHICKEN2, tmp);
7069
7070 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7071 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7072 DRM_ERROR("FDI mPHY reset assert timeout\n");
7073
7074 tmp = I915_READ(SOUTH_CHICKEN2);
7075 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7076 I915_WRITE(SOUTH_CHICKEN2, tmp);
7077
7078 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7079 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7080 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7081}
7082
7083/* WaMPhyProgramming:hsw */
7084static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7085{
7086 uint32_t tmp;
7087
7088 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7089 tmp &= ~(0xFF << 24);
7090 tmp |= (0x12 << 24);
7091 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7092
7093 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7094 tmp |= (1 << 11);
7095 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7096
7097 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7098 tmp |= (1 << 11);
7099 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7100
7101 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7102 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7103 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7104
7105 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7106 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7107 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7108
7109 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7110 tmp &= ~(7 << 13);
7111 tmp |= (5 << 13);
7112 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7113
7114 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7115 tmp &= ~(7 << 13);
7116 tmp |= (5 << 13);
7117 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7118
7119 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7120 tmp &= ~0xFF;
7121 tmp |= 0x1C;
7122 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7123
7124 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7125 tmp &= ~0xFF;
7126 tmp |= 0x1C;
7127 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7128
7129 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7130 tmp &= ~(0xFF << 16);
7131 tmp |= (0x1C << 16);
7132 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7133
7134 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7135 tmp &= ~(0xFF << 16);
7136 tmp |= (0x1C << 16);
7137 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7138
7139 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7140 tmp |= (1 << 27);
7141 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7142
7143 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7144 tmp |= (1 << 27);
7145 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7146
7147 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7148 tmp &= ~(0xF << 28);
7149 tmp |= (4 << 28);
7150 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7151
7152 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7153 tmp &= ~(0xF << 28);
7154 tmp |= (4 << 28);
7155 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7156}
7157
7158/* Implements 3 different sequences from BSpec chapter "Display iCLK
7159 * Programming" based on the parameters passed:
7160 * - Sequence to enable CLKOUT_DP
7161 * - Sequence to enable CLKOUT_DP without spread
7162 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7163 */
7164static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7165 bool with_fdi)
7166{
7167 struct drm_i915_private *dev_priv = dev->dev_private;
7168 uint32_t reg, tmp;
7169
7170 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7171 with_spread = true;
7172 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7173 with_fdi, "LP PCH doesn't have FDI\n"))
7174 with_fdi = false;
7175
7176 mutex_lock(&dev_priv->dpio_lock);
7177
7178 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7179 tmp &= ~SBI_SSCCTL_DISABLE;
7180 tmp |= SBI_SSCCTL_PATHALT;
7181 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7182
7183 udelay(24);
7184
7185 if (with_spread) {
7186 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7187 tmp &= ~SBI_SSCCTL_PATHALT;
7188 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7189
7190 if (with_fdi) {
7191 lpt_reset_fdi_mphy(dev_priv);
7192 lpt_program_fdi_mphy(dev_priv);
7193 }
7194 }
7195
7196 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7197 SBI_GEN0 : SBI_DBUFF0;
7198 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7199 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7200 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7201
7202 mutex_unlock(&dev_priv->dpio_lock);
7203}
7204
7205/* Sequence to disable CLKOUT_DP */
7206static void lpt_disable_clkout_dp(struct drm_device *dev)
7207{
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 uint32_t reg, tmp;
7210
7211 mutex_lock(&dev_priv->dpio_lock);
7212
7213 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7214 SBI_GEN0 : SBI_DBUFF0;
7215 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7216 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7217 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7218
7219 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7220 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7221 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7222 tmp |= SBI_SSCCTL_PATHALT;
7223 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7224 udelay(32);
7225 }
7226 tmp |= SBI_SSCCTL_DISABLE;
7227 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7228 }
7229
7230 mutex_unlock(&dev_priv->dpio_lock);
7231}
7232
7233static void lpt_init_pch_refclk(struct drm_device *dev)
7234{
7235 struct intel_encoder *encoder;
7236 bool has_vga = false;
7237
7238 for_each_intel_encoder(dev, encoder) {
7239 switch (encoder->type) {
7240 case INTEL_OUTPUT_ANALOG:
7241 has_vga = true;
7242 break;
7243 default:
7244 break;
7245 }
7246 }
7247
7248 if (has_vga)
7249 lpt_enable_clkout_dp(dev, true, true);
7250 else
7251 lpt_disable_clkout_dp(dev);
7252}
7253
7254/*
7255 * Initialize reference clocks when the driver loads
7256 */
7257void intel_init_pch_refclk(struct drm_device *dev)
7258{
7259 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7260 ironlake_init_pch_refclk(dev);
7261 else if (HAS_PCH_LPT(dev))
7262 lpt_init_pch_refclk(dev);
7263}
7264
7265static int ironlake_get_refclk(struct drm_crtc *crtc)
7266{
7267 struct drm_device *dev = crtc->dev;
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 struct intel_encoder *encoder;
7270 int num_connectors = 0;
7271 bool is_lvds = false;
7272
7273 for_each_intel_encoder(dev, encoder) {
7274 if (encoder->new_crtc != to_intel_crtc(crtc))
7275 continue;
7276
7277 switch (encoder->type) {
7278 case INTEL_OUTPUT_LVDS:
7279 is_lvds = true;
7280 break;
7281 default:
7282 break;
7283 }
7284 num_connectors++;
7285 }
7286
7287 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7288 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7289 dev_priv->vbt.lvds_ssc_freq);
7290 return dev_priv->vbt.lvds_ssc_freq;
7291 }
7292
7293 return 120000;
7294}
7295
7296static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7297{
7298 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7300 int pipe = intel_crtc->pipe;
7301 uint32_t val;
7302
7303 val = 0;
7304
7305 switch (intel_crtc->config->pipe_bpp) {
7306 case 18:
7307 val |= PIPECONF_6BPC;
7308 break;
7309 case 24:
7310 val |= PIPECONF_8BPC;
7311 break;
7312 case 30:
7313 val |= PIPECONF_10BPC;
7314 break;
7315 case 36:
7316 val |= PIPECONF_12BPC;
7317 break;
7318 default:
7319 /* Case prevented by intel_choose_pipe_bpp_dither. */
7320 BUG();
7321 }
7322
7323 if (intel_crtc->config->dither)
7324 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7325
7326 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7327 val |= PIPECONF_INTERLACED_ILK;
7328 else
7329 val |= PIPECONF_PROGRESSIVE;
7330
7331 if (intel_crtc->config->limited_color_range)
7332 val |= PIPECONF_COLOR_RANGE_SELECT;
7333
7334 I915_WRITE(PIPECONF(pipe), val);
7335 POSTING_READ(PIPECONF(pipe));
7336}
7337
7338/*
7339 * Set up the pipe CSC unit.
7340 *
7341 * Currently only full range RGB to limited range RGB conversion
7342 * is supported, but eventually this should handle various
7343 * RGB<->YCbCr scenarios as well.
7344 */
7345static void intel_set_pipe_csc(struct drm_crtc *crtc)
7346{
7347 struct drm_device *dev = crtc->dev;
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7350 int pipe = intel_crtc->pipe;
7351 uint16_t coeff = 0x7800; /* 1.0 */
7352
7353 /*
7354 * TODO: Check what kind of values actually come out of the pipe
7355 * with these coeff/postoff values and adjust to get the best
7356 * accuracy. Perhaps we even need to take the bpc value into
7357 * consideration.
7358 */
7359
7360 if (intel_crtc->config->limited_color_range)
7361 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7362
7363 /*
7364 * GY/GU and RY/RU should be the other way around according
7365 * to BSpec, but reality doesn't agree. Just set them up in
7366 * a way that results in the correct picture.
7367 */
7368 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7369 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7370
7371 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7372 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7373
7374 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7375 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7376
7377 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7378 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7379 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7380
7381 if (INTEL_INFO(dev)->gen > 6) {
7382 uint16_t postoff = 0;
7383
7384 if (intel_crtc->config->limited_color_range)
7385 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7386
7387 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7388 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7389 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7390
7391 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7392 } else {
7393 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7394
7395 if (intel_crtc->config->limited_color_range)
7396 mode |= CSC_BLACK_SCREEN_OFFSET;
7397
7398 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7399 }
7400}
7401
7402static void haswell_set_pipeconf(struct drm_crtc *crtc)
7403{
7404 struct drm_device *dev = crtc->dev;
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407 enum pipe pipe = intel_crtc->pipe;
7408 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7409 uint32_t val;
7410
7411 val = 0;
7412
7413 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7414 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7415
7416 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7417 val |= PIPECONF_INTERLACED_ILK;
7418 else
7419 val |= PIPECONF_PROGRESSIVE;
7420
7421 I915_WRITE(PIPECONF(cpu_transcoder), val);
7422 POSTING_READ(PIPECONF(cpu_transcoder));
7423
7424 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7425 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7426
7427 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7428 val = 0;
7429
7430 switch (intel_crtc->config->pipe_bpp) {
7431 case 18:
7432 val |= PIPEMISC_DITHER_6_BPC;
7433 break;
7434 case 24:
7435 val |= PIPEMISC_DITHER_8_BPC;
7436 break;
7437 case 30:
7438 val |= PIPEMISC_DITHER_10_BPC;
7439 break;
7440 case 36:
7441 val |= PIPEMISC_DITHER_12_BPC;
7442 break;
7443 default:
7444 /* Case prevented by pipe_config_set_bpp. */
7445 BUG();
7446 }
7447
7448 if (intel_crtc->config->dither)
7449 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7450
7451 I915_WRITE(PIPEMISC(pipe), val);
7452 }
7453}
7454
7455static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7456 struct intel_crtc_state *crtc_state,
7457 intel_clock_t *clock,
7458 bool *has_reduced_clock,
7459 intel_clock_t *reduced_clock)
7460{
7461 struct drm_device *dev = crtc->dev;
7462 struct drm_i915_private *dev_priv = dev->dev_private;
7463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7464 int refclk;
7465 const intel_limit_t *limit;
7466 bool ret, is_lvds = false;
7467
7468 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7469
7470 refclk = ironlake_get_refclk(crtc);
7471
7472 /*
7473 * Returns a set of divisors for the desired target clock with the given
7474 * refclk, or FALSE. The returned values represent the clock equation:
7475 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7476 */
7477 limit = intel_limit(intel_crtc, refclk);
7478 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7479 crtc_state->port_clock,
7480 refclk, NULL, clock);
7481 if (!ret)
7482 return false;
7483
7484 if (is_lvds && dev_priv->lvds_downclock_avail) {
7485 /*
7486 * Ensure we match the reduced clock's P to the target clock.
7487 * If the clocks don't match, we can't switch the display clock
7488 * by using the FP0/FP1. In such case we will disable the LVDS
7489 * downclock feature.
7490 */
7491 *has_reduced_clock =
7492 dev_priv->display.find_dpll(limit, intel_crtc,
7493 dev_priv->lvds_downclock,
7494 refclk, clock,
7495 reduced_clock);
7496 }
7497
7498 return true;
7499}
7500
7501int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7502{
7503 /*
7504 * Account for spread spectrum to avoid
7505 * oversubscribing the link. Max center spread
7506 * is 2.5%; use 5% for safety's sake.
7507 */
7508 u32 bps = target_clock * bpp * 21 / 20;
7509 return DIV_ROUND_UP(bps, link_bw * 8);
7510}
7511
7512static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7513{
7514 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7515}
7516
7517static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7518 struct intel_crtc_state *crtc_state,
7519 u32 *fp,
7520 intel_clock_t *reduced_clock, u32 *fp2)
7521{
7522 struct drm_crtc *crtc = &intel_crtc->base;
7523 struct drm_device *dev = crtc->dev;
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525 struct intel_encoder *intel_encoder;
7526 uint32_t dpll;
7527 int factor, num_connectors = 0;
7528 bool is_lvds = false, is_sdvo = false;
7529
7530 for_each_intel_encoder(dev, intel_encoder) {
7531 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7532 continue;
7533
7534 switch (intel_encoder->type) {
7535 case INTEL_OUTPUT_LVDS:
7536 is_lvds = true;
7537 break;
7538 case INTEL_OUTPUT_SDVO:
7539 case INTEL_OUTPUT_HDMI:
7540 is_sdvo = true;
7541 break;
7542 default:
7543 break;
7544 }
7545
7546 num_connectors++;
7547 }
7548
7549 /* Enable autotuning of the PLL clock (if permissible) */
7550 factor = 21;
7551 if (is_lvds) {
7552 if ((intel_panel_use_ssc(dev_priv) &&
7553 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7554 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7555 factor = 25;
7556 } else if (crtc_state->sdvo_tv_clock)
7557 factor = 20;
7558
7559 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7560 *fp |= FP_CB_TUNE;
7561
7562 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7563 *fp2 |= FP_CB_TUNE;
7564
7565 dpll = 0;
7566
7567 if (is_lvds)
7568 dpll |= DPLLB_MODE_LVDS;
7569 else
7570 dpll |= DPLLB_MODE_DAC_SERIAL;
7571
7572 dpll |= (crtc_state->pixel_multiplier - 1)
7573 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7574
7575 if (is_sdvo)
7576 dpll |= DPLL_SDVO_HIGH_SPEED;
7577 if (crtc_state->has_dp_encoder)
7578 dpll |= DPLL_SDVO_HIGH_SPEED;
7579
7580 /* compute bitmask from p1 value */
7581 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7582 /* also FPA1 */
7583 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7584
7585 switch (crtc_state->dpll.p2) {
7586 case 5:
7587 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7588 break;
7589 case 7:
7590 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7591 break;
7592 case 10:
7593 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7594 break;
7595 case 14:
7596 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7597 break;
7598 }
7599
7600 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7602 else
7603 dpll |= PLL_REF_INPUT_DREFCLK;
7604
7605 return dpll | DPLL_VCO_ENABLE;
7606}
7607
7608static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7609 struct intel_crtc_state *crtc_state)
7610{
7611 struct drm_device *dev = crtc->base.dev;
7612 intel_clock_t clock, reduced_clock;
7613 u32 dpll = 0, fp = 0, fp2 = 0;
7614 bool ok, has_reduced_clock = false;
7615 bool is_lvds = false;
7616 struct intel_shared_dpll *pll;
7617
7618 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7619
7620 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7621 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7622
7623 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7624 &has_reduced_clock, &reduced_clock);
7625 if (!ok && !crtc_state->clock_set) {
7626 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7627 return -EINVAL;
7628 }
7629 /* Compat-code for transition, will disappear. */
7630 if (!crtc_state->clock_set) {
7631 crtc_state->dpll.n = clock.n;
7632 crtc_state->dpll.m1 = clock.m1;
7633 crtc_state->dpll.m2 = clock.m2;
7634 crtc_state->dpll.p1 = clock.p1;
7635 crtc_state->dpll.p2 = clock.p2;
7636 }
7637
7638 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7639 if (crtc_state->has_pch_encoder) {
7640 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7641 if (has_reduced_clock)
7642 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7643
7644 dpll = ironlake_compute_dpll(crtc, crtc_state,
7645 &fp, &reduced_clock,
7646 has_reduced_clock ? &fp2 : NULL);
7647
7648 crtc_state->dpll_hw_state.dpll = dpll;
7649 crtc_state->dpll_hw_state.fp0 = fp;
7650 if (has_reduced_clock)
7651 crtc_state->dpll_hw_state.fp1 = fp2;
7652 else
7653 crtc_state->dpll_hw_state.fp1 = fp;
7654
7655 pll = intel_get_shared_dpll(crtc, crtc_state);
7656 if (pll == NULL) {
7657 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7658 pipe_name(crtc->pipe));
7659 return -EINVAL;
7660 }
7661 }
7662
7663 if (is_lvds && has_reduced_clock && i915.powersave)
7664 crtc->lowfreq_avail = true;
7665 else
7666 crtc->lowfreq_avail = false;
7667
7668 return 0;
7669}
7670
7671static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7672 struct intel_link_m_n *m_n)
7673{
7674 struct drm_device *dev = crtc->base.dev;
7675 struct drm_i915_private *dev_priv = dev->dev_private;
7676 enum pipe pipe = crtc->pipe;
7677
7678 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7679 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7680 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7681 & ~TU_SIZE_MASK;
7682 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7683 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7684 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7685}
7686
7687static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7688 enum transcoder transcoder,
7689 struct intel_link_m_n *m_n,
7690 struct intel_link_m_n *m2_n2)
7691{
7692 struct drm_device *dev = crtc->base.dev;
7693 struct drm_i915_private *dev_priv = dev->dev_private;
7694 enum pipe pipe = crtc->pipe;
7695
7696 if (INTEL_INFO(dev)->gen >= 5) {
7697 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7698 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7699 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7700 & ~TU_SIZE_MASK;
7701 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7702 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7703 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7704 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7705 * gen < 8) and if DRRS is supported (to make sure the
7706 * registers are not unnecessarily read).
7707 */
7708 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7709 crtc->config->has_drrs) {
7710 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7711 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7712 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7713 & ~TU_SIZE_MASK;
7714 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7715 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7716 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7717 }
7718 } else {
7719 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7720 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7721 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7722 & ~TU_SIZE_MASK;
7723 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7724 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7725 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7726 }
7727}
7728
7729void intel_dp_get_m_n(struct intel_crtc *crtc,
7730 struct intel_crtc_state *pipe_config)
7731{
7732 if (pipe_config->has_pch_encoder)
7733 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7734 else
7735 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7736 &pipe_config->dp_m_n,
7737 &pipe_config->dp_m2_n2);
7738}
7739
7740static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7741 struct intel_crtc_state *pipe_config)
7742{
7743 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7744 &pipe_config->fdi_m_n, NULL);
7745}
7746
7747static void skylake_get_pfit_config(struct intel_crtc *crtc,
7748 struct intel_crtc_state *pipe_config)
7749{
7750 struct drm_device *dev = crtc->base.dev;
7751 struct drm_i915_private *dev_priv = dev->dev_private;
7752 uint32_t tmp;
7753
7754 tmp = I915_READ(PS_CTL(crtc->pipe));
7755
7756 if (tmp & PS_ENABLE) {
7757 pipe_config->pch_pfit.enabled = true;
7758 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7759 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7760 }
7761}
7762
7763static void
7764skylake_get_initial_plane_config(struct intel_crtc *crtc,
7765 struct intel_initial_plane_config *plane_config)
7766{
7767 struct drm_device *dev = crtc->base.dev;
7768 struct drm_i915_private *dev_priv = dev->dev_private;
7769 u32 val, base, offset, stride_mult, tiling;
7770 int pipe = crtc->pipe;
7771 int fourcc, pixel_format;
7772 int aligned_height;
7773 struct drm_framebuffer *fb;
7774 struct intel_framebuffer *intel_fb;
7775
7776 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7777 if (!intel_fb) {
7778 DRM_DEBUG_KMS("failed to alloc fb\n");
7779 return;
7780 }
7781
7782 fb = &intel_fb->base;
7783
7784 val = I915_READ(PLANE_CTL(pipe, 0));
7785 if (!(val & PLANE_CTL_ENABLE))
7786 goto error;
7787
7788 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7789 fourcc = skl_format_to_fourcc(pixel_format,
7790 val & PLANE_CTL_ORDER_RGBX,
7791 val & PLANE_CTL_ALPHA_MASK);
7792 fb->pixel_format = fourcc;
7793 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7794
7795 tiling = val & PLANE_CTL_TILED_MASK;
7796 switch (tiling) {
7797 case PLANE_CTL_TILED_LINEAR:
7798 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7799 break;
7800 case PLANE_CTL_TILED_X:
7801 plane_config->tiling = I915_TILING_X;
7802 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7803 break;
7804 case PLANE_CTL_TILED_Y:
7805 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7806 break;
7807 case PLANE_CTL_TILED_YF:
7808 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7809 break;
7810 default:
7811 MISSING_CASE(tiling);
7812 goto error;
7813 }
7814
7815 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7816 plane_config->base = base;
7817
7818 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7819
7820 val = I915_READ(PLANE_SIZE(pipe, 0));
7821 fb->height = ((val >> 16) & 0xfff) + 1;
7822 fb->width = ((val >> 0) & 0x1fff) + 1;
7823
7824 val = I915_READ(PLANE_STRIDE(pipe, 0));
7825 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7826 fb->pixel_format);
7827 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7828
7829 aligned_height = intel_fb_align_height(dev, fb->height,
7830 fb->pixel_format,
7831 fb->modifier[0]);
7832
7833 plane_config->size = fb->pitches[0] * aligned_height;
7834
7835 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7836 pipe_name(pipe), fb->width, fb->height,
7837 fb->bits_per_pixel, base, fb->pitches[0],
7838 plane_config->size);
7839
7840 plane_config->fb = intel_fb;
7841 return;
7842
7843error:
7844 kfree(fb);
7845}
7846
7847static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7848 struct intel_crtc_state *pipe_config)
7849{
7850 struct drm_device *dev = crtc->base.dev;
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 uint32_t tmp;
7853
7854 tmp = I915_READ(PF_CTL(crtc->pipe));
7855
7856 if (tmp & PF_ENABLE) {
7857 pipe_config->pch_pfit.enabled = true;
7858 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7859 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7860
7861 /* We currently do not free assignements of panel fitters on
7862 * ivb/hsw (since we don't use the higher upscaling modes which
7863 * differentiates them) so just WARN about this case for now. */
7864 if (IS_GEN7(dev)) {
7865 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7866 PF_PIPE_SEL_IVB(crtc->pipe));
7867 }
7868 }
7869}
7870
7871static void
7872ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7873 struct intel_initial_plane_config *plane_config)
7874{
7875 struct drm_device *dev = crtc->base.dev;
7876 struct drm_i915_private *dev_priv = dev->dev_private;
7877 u32 val, base, offset;
7878 int pipe = crtc->pipe;
7879 int fourcc, pixel_format;
7880 int aligned_height;
7881 struct drm_framebuffer *fb;
7882 struct intel_framebuffer *intel_fb;
7883
7884 val = I915_READ(DSPCNTR(pipe));
7885 if (!(val & DISPLAY_PLANE_ENABLE))
7886 return;
7887
7888 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7889 if (!intel_fb) {
7890 DRM_DEBUG_KMS("failed to alloc fb\n");
7891 return;
7892 }
7893
7894 fb = &intel_fb->base;
7895
7896 if (INTEL_INFO(dev)->gen >= 4) {
7897 if (val & DISPPLANE_TILED) {
7898 plane_config->tiling = I915_TILING_X;
7899 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7900 }
7901 }
7902
7903 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7904 fourcc = i9xx_format_to_fourcc(pixel_format);
7905 fb->pixel_format = fourcc;
7906 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7907
7908 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7909 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7910 offset = I915_READ(DSPOFFSET(pipe));
7911 } else {
7912 if (plane_config->tiling)
7913 offset = I915_READ(DSPTILEOFF(pipe));
7914 else
7915 offset = I915_READ(DSPLINOFF(pipe));
7916 }
7917 plane_config->base = base;
7918
7919 val = I915_READ(PIPESRC(pipe));
7920 fb->width = ((val >> 16) & 0xfff) + 1;
7921 fb->height = ((val >> 0) & 0xfff) + 1;
7922
7923 val = I915_READ(DSPSTRIDE(pipe));
7924 fb->pitches[0] = val & 0xffffffc0;
7925
7926 aligned_height = intel_fb_align_height(dev, fb->height,
7927 fb->pixel_format,
7928 fb->modifier[0]);
7929
7930 plane_config->size = fb->pitches[0] * aligned_height;
7931
7932 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7933 pipe_name(pipe), fb->width, fb->height,
7934 fb->bits_per_pixel, base, fb->pitches[0],
7935 plane_config->size);
7936
7937 plane_config->fb = intel_fb;
7938}
7939
7940static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7941 struct intel_crtc_state *pipe_config)
7942{
7943 struct drm_device *dev = crtc->base.dev;
7944 struct drm_i915_private *dev_priv = dev->dev_private;
7945 uint32_t tmp;
7946
7947 if (!intel_display_power_is_enabled(dev_priv,
7948 POWER_DOMAIN_PIPE(crtc->pipe)))
7949 return false;
7950
7951 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7952 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7953
7954 tmp = I915_READ(PIPECONF(crtc->pipe));
7955 if (!(tmp & PIPECONF_ENABLE))
7956 return false;
7957
7958 switch (tmp & PIPECONF_BPC_MASK) {
7959 case PIPECONF_6BPC:
7960 pipe_config->pipe_bpp = 18;
7961 break;
7962 case PIPECONF_8BPC:
7963 pipe_config->pipe_bpp = 24;
7964 break;
7965 case PIPECONF_10BPC:
7966 pipe_config->pipe_bpp = 30;
7967 break;
7968 case PIPECONF_12BPC:
7969 pipe_config->pipe_bpp = 36;
7970 break;
7971 default:
7972 break;
7973 }
7974
7975 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7976 pipe_config->limited_color_range = true;
7977
7978 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7979 struct intel_shared_dpll *pll;
7980
7981 pipe_config->has_pch_encoder = true;
7982
7983 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7984 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7985 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7986
7987 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7988
7989 if (HAS_PCH_IBX(dev_priv->dev)) {
7990 pipe_config->shared_dpll =
7991 (enum intel_dpll_id) crtc->pipe;
7992 } else {
7993 tmp = I915_READ(PCH_DPLL_SEL);
7994 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7995 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7996 else
7997 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7998 }
7999
8000 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8001
8002 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8003 &pipe_config->dpll_hw_state));
8004
8005 tmp = pipe_config->dpll_hw_state.dpll;
8006 pipe_config->pixel_multiplier =
8007 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8008 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8009
8010 ironlake_pch_clock_get(crtc, pipe_config);
8011 } else {
8012 pipe_config->pixel_multiplier = 1;
8013 }
8014
8015 intel_get_pipe_timings(crtc, pipe_config);
8016
8017 ironlake_get_pfit_config(crtc, pipe_config);
8018
8019 return true;
8020}
8021
8022static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8023{
8024 struct drm_device *dev = dev_priv->dev;
8025 struct intel_crtc *crtc;
8026
8027 for_each_intel_crtc(dev, crtc)
8028 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8029 pipe_name(crtc->pipe));
8030
8031 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8032 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8033 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8034 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8035 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8036 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8037 "CPU PWM1 enabled\n");
8038 if (IS_HASWELL(dev))
8039 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8040 "CPU PWM2 enabled\n");
8041 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8042 "PCH PWM1 enabled\n");
8043 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8044 "Utility pin enabled\n");
8045 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8046
8047 /*
8048 * In theory we can still leave IRQs enabled, as long as only the HPD
8049 * interrupts remain enabled. We used to check for that, but since it's
8050 * gen-specific and since we only disable LCPLL after we fully disable
8051 * the interrupts, the check below should be enough.
8052 */
8053 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8054}
8055
8056static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8057{
8058 struct drm_device *dev = dev_priv->dev;
8059
8060 if (IS_HASWELL(dev))
8061 return I915_READ(D_COMP_HSW);
8062 else
8063 return I915_READ(D_COMP_BDW);
8064}
8065
8066static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8067{
8068 struct drm_device *dev = dev_priv->dev;
8069
8070 if (IS_HASWELL(dev)) {
8071 mutex_lock(&dev_priv->rps.hw_lock);
8072 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8073 val))
8074 DRM_ERROR("Failed to write to D_COMP\n");
8075 mutex_unlock(&dev_priv->rps.hw_lock);
8076 } else {
8077 I915_WRITE(D_COMP_BDW, val);
8078 POSTING_READ(D_COMP_BDW);
8079 }
8080}
8081
8082/*
8083 * This function implements pieces of two sequences from BSpec:
8084 * - Sequence for display software to disable LCPLL
8085 * - Sequence for display software to allow package C8+
8086 * The steps implemented here are just the steps that actually touch the LCPLL
8087 * register. Callers should take care of disabling all the display engine
8088 * functions, doing the mode unset, fixing interrupts, etc.
8089 */
8090static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8091 bool switch_to_fclk, bool allow_power_down)
8092{
8093 uint32_t val;
8094
8095 assert_can_disable_lcpll(dev_priv);
8096
8097 val = I915_READ(LCPLL_CTL);
8098
8099 if (switch_to_fclk) {
8100 val |= LCPLL_CD_SOURCE_FCLK;
8101 I915_WRITE(LCPLL_CTL, val);
8102
8103 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8104 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8105 DRM_ERROR("Switching to FCLK failed\n");
8106
8107 val = I915_READ(LCPLL_CTL);
8108 }
8109
8110 val |= LCPLL_PLL_DISABLE;
8111 I915_WRITE(LCPLL_CTL, val);
8112 POSTING_READ(LCPLL_CTL);
8113
8114 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8115 DRM_ERROR("LCPLL still locked\n");
8116
8117 val = hsw_read_dcomp(dev_priv);
8118 val |= D_COMP_COMP_DISABLE;
8119 hsw_write_dcomp(dev_priv, val);
8120 ndelay(100);
8121
8122 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8123 1))
8124 DRM_ERROR("D_COMP RCOMP still in progress\n");
8125
8126 if (allow_power_down) {
8127 val = I915_READ(LCPLL_CTL);
8128 val |= LCPLL_POWER_DOWN_ALLOW;
8129 I915_WRITE(LCPLL_CTL, val);
8130 POSTING_READ(LCPLL_CTL);
8131 }
8132}
8133
8134/*
8135 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8136 * source.
8137 */
8138static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8139{
8140 uint32_t val;
8141
8142 val = I915_READ(LCPLL_CTL);
8143
8144 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8145 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8146 return;
8147
8148 /*
8149 * Make sure we're not on PC8 state before disabling PC8, otherwise
8150 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8151 */
8152 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8153
8154 if (val & LCPLL_POWER_DOWN_ALLOW) {
8155 val &= ~LCPLL_POWER_DOWN_ALLOW;
8156 I915_WRITE(LCPLL_CTL, val);
8157 POSTING_READ(LCPLL_CTL);
8158 }
8159
8160 val = hsw_read_dcomp(dev_priv);
8161 val |= D_COMP_COMP_FORCE;
8162 val &= ~D_COMP_COMP_DISABLE;
8163 hsw_write_dcomp(dev_priv, val);
8164
8165 val = I915_READ(LCPLL_CTL);
8166 val &= ~LCPLL_PLL_DISABLE;
8167 I915_WRITE(LCPLL_CTL, val);
8168
8169 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8170 DRM_ERROR("LCPLL not locked yet\n");
8171
8172 if (val & LCPLL_CD_SOURCE_FCLK) {
8173 val = I915_READ(LCPLL_CTL);
8174 val &= ~LCPLL_CD_SOURCE_FCLK;
8175 I915_WRITE(LCPLL_CTL, val);
8176
8177 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8178 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8179 DRM_ERROR("Switching back to LCPLL failed\n");
8180 }
8181
8182 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8183}
8184
8185/*
8186 * Package states C8 and deeper are really deep PC states that can only be
8187 * reached when all the devices on the system allow it, so even if the graphics
8188 * device allows PC8+, it doesn't mean the system will actually get to these
8189 * states. Our driver only allows PC8+ when going into runtime PM.
8190 *
8191 * The requirements for PC8+ are that all the outputs are disabled, the power
8192 * well is disabled and most interrupts are disabled, and these are also
8193 * requirements for runtime PM. When these conditions are met, we manually do
8194 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8195 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8196 * hang the machine.
8197 *
8198 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8199 * the state of some registers, so when we come back from PC8+ we need to
8200 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8201 * need to take care of the registers kept by RC6. Notice that this happens even
8202 * if we don't put the device in PCI D3 state (which is what currently happens
8203 * because of the runtime PM support).
8204 *
8205 * For more, read "Display Sequences for Package C8" on the hardware
8206 * documentation.
8207 */
8208void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8209{
8210 struct drm_device *dev = dev_priv->dev;
8211 uint32_t val;
8212
8213 DRM_DEBUG_KMS("Enabling package C8+\n");
8214
8215 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8216 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8217 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8218 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8219 }
8220
8221 lpt_disable_clkout_dp(dev);
8222 hsw_disable_lcpll(dev_priv, true, true);
8223}
8224
8225void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8226{
8227 struct drm_device *dev = dev_priv->dev;
8228 uint32_t val;
8229
8230 DRM_DEBUG_KMS("Disabling package C8+\n");
8231
8232 hsw_restore_lcpll(dev_priv);
8233 lpt_init_pch_refclk(dev);
8234
8235 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8236 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8237 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8238 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8239 }
8240
8241 intel_prepare_ddi(dev);
8242}
8243
8244static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8245 struct intel_crtc_state *crtc_state)
8246{
8247 if (!intel_ddi_pll_select(crtc, crtc_state))
8248 return -EINVAL;
8249
8250 crtc->lowfreq_avail = false;
8251
8252 return 0;
8253}
8254
8255static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8256 enum port port,
8257 struct intel_crtc_state *pipe_config)
8258{
8259 u32 temp, dpll_ctl1;
8260
8261 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8262 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8263
8264 switch (pipe_config->ddi_pll_sel) {
8265 case SKL_DPLL0:
8266 /*
8267 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8268 * of the shared DPLL framework and thus needs to be read out
8269 * separately
8270 */
8271 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8272 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8273 break;
8274 case SKL_DPLL1:
8275 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8276 break;
8277 case SKL_DPLL2:
8278 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8279 break;
8280 case SKL_DPLL3:
8281 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8282 break;
8283 }
8284}
8285
8286static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8287 enum port port,
8288 struct intel_crtc_state *pipe_config)
8289{
8290 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8291
8292 switch (pipe_config->ddi_pll_sel) {
8293 case PORT_CLK_SEL_WRPLL1:
8294 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8295 break;
8296 case PORT_CLK_SEL_WRPLL2:
8297 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8298 break;
8299 }
8300}
8301
8302static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8303 struct intel_crtc_state *pipe_config)
8304{
8305 struct drm_device *dev = crtc->base.dev;
8306 struct drm_i915_private *dev_priv = dev->dev_private;
8307 struct intel_shared_dpll *pll;
8308 enum port port;
8309 uint32_t tmp;
8310
8311 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8312
8313 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8314
8315 if (IS_SKYLAKE(dev))
8316 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8317 else
8318 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8319
8320 if (pipe_config->shared_dpll >= 0) {
8321 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8322
8323 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8324 &pipe_config->dpll_hw_state));
8325 }
8326
8327 /*
8328 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8329 * DDI E. So just check whether this pipe is wired to DDI E and whether
8330 * the PCH transcoder is on.
8331 */
8332 if (INTEL_INFO(dev)->gen < 9 &&
8333 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8334 pipe_config->has_pch_encoder = true;
8335
8336 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8337 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8338 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8339
8340 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8341 }
8342}
8343
8344static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8345 struct intel_crtc_state *pipe_config)
8346{
8347 struct drm_device *dev = crtc->base.dev;
8348 struct drm_i915_private *dev_priv = dev->dev_private;
8349 enum intel_display_power_domain pfit_domain;
8350 uint32_t tmp;
8351
8352 if (!intel_display_power_is_enabled(dev_priv,
8353 POWER_DOMAIN_PIPE(crtc->pipe)))
8354 return false;
8355
8356 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8357 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8358
8359 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8360 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8361 enum pipe trans_edp_pipe;
8362 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8363 default:
8364 WARN(1, "unknown pipe linked to edp transcoder\n");
8365 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8366 case TRANS_DDI_EDP_INPUT_A_ON:
8367 trans_edp_pipe = PIPE_A;
8368 break;
8369 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8370 trans_edp_pipe = PIPE_B;
8371 break;
8372 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8373 trans_edp_pipe = PIPE_C;
8374 break;
8375 }
8376
8377 if (trans_edp_pipe == crtc->pipe)
8378 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8379 }
8380
8381 if (!intel_display_power_is_enabled(dev_priv,
8382 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8383 return false;
8384
8385 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8386 if (!(tmp & PIPECONF_ENABLE))
8387 return false;
8388
8389 haswell_get_ddi_port_state(crtc, pipe_config);
8390
8391 intel_get_pipe_timings(crtc, pipe_config);
8392
8393 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8394 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8395 if (IS_SKYLAKE(dev))
8396 skylake_get_pfit_config(crtc, pipe_config);
8397 else
8398 ironlake_get_pfit_config(crtc, pipe_config);
8399 }
8400
8401 if (IS_HASWELL(dev))
8402 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8403 (I915_READ(IPS_CTL) & IPS_ENABLE);
8404
8405 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8406 pipe_config->pixel_multiplier =
8407 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8408 } else {
8409 pipe_config->pixel_multiplier = 1;
8410 }
8411
8412 return true;
8413}
8414
8415static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8416{
8417 struct drm_device *dev = crtc->dev;
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8420 uint32_t cntl = 0, size = 0;
8421
8422 if (base) {
8423 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8424 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8425 unsigned int stride = roundup_pow_of_two(width) * 4;
8426
8427 switch (stride) {
8428 default:
8429 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8430 width, stride);
8431 stride = 256;
8432 /* fallthrough */
8433 case 256:
8434 case 512:
8435 case 1024:
8436 case 2048:
8437 break;
8438 }
8439
8440 cntl |= CURSOR_ENABLE |
8441 CURSOR_GAMMA_ENABLE |
8442 CURSOR_FORMAT_ARGB |
8443 CURSOR_STRIDE(stride);
8444
8445 size = (height << 12) | width;
8446 }
8447
8448 if (intel_crtc->cursor_cntl != 0 &&
8449 (intel_crtc->cursor_base != base ||
8450 intel_crtc->cursor_size != size ||
8451 intel_crtc->cursor_cntl != cntl)) {
8452 /* On these chipsets we can only modify the base/size/stride
8453 * whilst the cursor is disabled.
8454 */
8455 I915_WRITE(_CURACNTR, 0);
8456 POSTING_READ(_CURACNTR);
8457 intel_crtc->cursor_cntl = 0;
8458 }
8459
8460 if (intel_crtc->cursor_base != base) {
8461 I915_WRITE(_CURABASE, base);
8462 intel_crtc->cursor_base = base;
8463 }
8464
8465 if (intel_crtc->cursor_size != size) {
8466 I915_WRITE(CURSIZE, size);
8467 intel_crtc->cursor_size = size;
8468 }
8469
8470 if (intel_crtc->cursor_cntl != cntl) {
8471 I915_WRITE(_CURACNTR, cntl);
8472 POSTING_READ(_CURACNTR);
8473 intel_crtc->cursor_cntl = cntl;
8474 }
8475}
8476
8477static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8478{
8479 struct drm_device *dev = crtc->dev;
8480 struct drm_i915_private *dev_priv = dev->dev_private;
8481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8482 int pipe = intel_crtc->pipe;
8483 uint32_t cntl;
8484
8485 cntl = 0;
8486 if (base) {
8487 cntl = MCURSOR_GAMMA_ENABLE;
8488 switch (intel_crtc->base.cursor->state->crtc_w) {
8489 case 64:
8490 cntl |= CURSOR_MODE_64_ARGB_AX;
8491 break;
8492 case 128:
8493 cntl |= CURSOR_MODE_128_ARGB_AX;
8494 break;
8495 case 256:
8496 cntl |= CURSOR_MODE_256_ARGB_AX;
8497 break;
8498 default:
8499 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8500 return;
8501 }
8502 cntl |= pipe << 28; /* Connect to correct pipe */
8503
8504 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8505 cntl |= CURSOR_PIPE_CSC_ENABLE;
8506 }
8507
8508 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8509 cntl |= CURSOR_ROTATE_180;
8510
8511 if (intel_crtc->cursor_cntl != cntl) {
8512 I915_WRITE(CURCNTR(pipe), cntl);
8513 POSTING_READ(CURCNTR(pipe));
8514 intel_crtc->cursor_cntl = cntl;
8515 }
8516
8517 /* and commit changes on next vblank */
8518 I915_WRITE(CURBASE(pipe), base);
8519 POSTING_READ(CURBASE(pipe));
8520
8521 intel_crtc->cursor_base = base;
8522}
8523
8524/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8525static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8526 bool on)
8527{
8528 struct drm_device *dev = crtc->dev;
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8531 int pipe = intel_crtc->pipe;
8532 int x = crtc->cursor_x;
8533 int y = crtc->cursor_y;
8534 u32 base = 0, pos = 0;
8535
8536 if (on)
8537 base = intel_crtc->cursor_addr;
8538
8539 if (x >= intel_crtc->config->pipe_src_w)
8540 base = 0;
8541
8542 if (y >= intel_crtc->config->pipe_src_h)
8543 base = 0;
8544
8545 if (x < 0) {
8546 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8547 base = 0;
8548
8549 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8550 x = -x;
8551 }
8552 pos |= x << CURSOR_X_SHIFT;
8553
8554 if (y < 0) {
8555 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8556 base = 0;
8557
8558 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8559 y = -y;
8560 }
8561 pos |= y << CURSOR_Y_SHIFT;
8562
8563 if (base == 0 && intel_crtc->cursor_base == 0)
8564 return;
8565
8566 I915_WRITE(CURPOS(pipe), pos);
8567
8568 /* ILK+ do this automagically */
8569 if (HAS_GMCH_DISPLAY(dev) &&
8570 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8571 base += (intel_crtc->base.cursor->state->crtc_h *
8572 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8573 }
8574
8575 if (IS_845G(dev) || IS_I865G(dev))
8576 i845_update_cursor(crtc, base);
8577 else
8578 i9xx_update_cursor(crtc, base);
8579}
8580
8581static bool cursor_size_ok(struct drm_device *dev,
8582 uint32_t width, uint32_t height)
8583{
8584 if (width == 0 || height == 0)
8585 return false;
8586
8587 /*
8588 * 845g/865g are special in that they are only limited by
8589 * the width of their cursors, the height is arbitrary up to
8590 * the precision of the register. Everything else requires
8591 * square cursors, limited to a few power-of-two sizes.
8592 */
8593 if (IS_845G(dev) || IS_I865G(dev)) {
8594 if ((width & 63) != 0)
8595 return false;
8596
8597 if (width > (IS_845G(dev) ? 64 : 512))
8598 return false;
8599
8600 if (height > 1023)
8601 return false;
8602 } else {
8603 switch (width | height) {
8604 case 256:
8605 case 128:
8606 if (IS_GEN2(dev))
8607 return false;
8608 case 64:
8609 break;
8610 default:
8611 return false;
8612 }
8613 }
8614
8615 return true;
8616}
8617
8618static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8619 u16 *blue, uint32_t start, uint32_t size)
8620{
8621 int end = (start + size > 256) ? 256 : start + size, i;
8622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623
8624 for (i = start; i < end; i++) {
8625 intel_crtc->lut_r[i] = red[i] >> 8;
8626 intel_crtc->lut_g[i] = green[i] >> 8;
8627 intel_crtc->lut_b[i] = blue[i] >> 8;
8628 }
8629
8630 intel_crtc_load_lut(crtc);
8631}
8632
8633/* VESA 640x480x72Hz mode to set on the pipe */
8634static struct drm_display_mode load_detect_mode = {
8635 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8636 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8637};
8638
8639struct drm_framebuffer *
8640__intel_framebuffer_create(struct drm_device *dev,
8641 struct drm_mode_fb_cmd2 *mode_cmd,
8642 struct drm_i915_gem_object *obj)
8643{
8644 struct intel_framebuffer *intel_fb;
8645 int ret;
8646
8647 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8648 if (!intel_fb) {
8649 drm_gem_object_unreference(&obj->base);
8650 return ERR_PTR(-ENOMEM);
8651 }
8652
8653 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8654 if (ret)
8655 goto err;
8656
8657 return &intel_fb->base;
8658err:
8659 drm_gem_object_unreference(&obj->base);
8660 kfree(intel_fb);
8661
8662 return ERR_PTR(ret);
8663}
8664
8665static struct drm_framebuffer *
8666intel_framebuffer_create(struct drm_device *dev,
8667 struct drm_mode_fb_cmd2 *mode_cmd,
8668 struct drm_i915_gem_object *obj)
8669{
8670 struct drm_framebuffer *fb;
8671 int ret;
8672
8673 ret = i915_mutex_lock_interruptible(dev);
8674 if (ret)
8675 return ERR_PTR(ret);
8676 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8677 mutex_unlock(&dev->struct_mutex);
8678
8679 return fb;
8680}
8681
8682static u32
8683intel_framebuffer_pitch_for_width(int width, int bpp)
8684{
8685 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8686 return ALIGN(pitch, 64);
8687}
8688
8689static u32
8690intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8691{
8692 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8693 return PAGE_ALIGN(pitch * mode->vdisplay);
8694}
8695
8696static struct drm_framebuffer *
8697intel_framebuffer_create_for_mode(struct drm_device *dev,
8698 struct drm_display_mode *mode,
8699 int depth, int bpp)
8700{
8701 struct drm_i915_gem_object *obj;
8702 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8703
8704 obj = i915_gem_alloc_object(dev,
8705 intel_framebuffer_size_for_mode(mode, bpp));
8706 if (obj == NULL)
8707 return ERR_PTR(-ENOMEM);
8708
8709 mode_cmd.width = mode->hdisplay;
8710 mode_cmd.height = mode->vdisplay;
8711 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8712 bpp);
8713 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8714
8715 return intel_framebuffer_create(dev, &mode_cmd, obj);
8716}
8717
8718static struct drm_framebuffer *
8719mode_fits_in_fbdev(struct drm_device *dev,
8720 struct drm_display_mode *mode)
8721{
8722#ifdef CONFIG_DRM_I915_FBDEV
8723 struct drm_i915_private *dev_priv = dev->dev_private;
8724 struct drm_i915_gem_object *obj;
8725 struct drm_framebuffer *fb;
8726
8727 if (!dev_priv->fbdev)
8728 return NULL;
8729
8730 if (!dev_priv->fbdev->fb)
8731 return NULL;
8732
8733 obj = dev_priv->fbdev->fb->obj;
8734 BUG_ON(!obj);
8735
8736 fb = &dev_priv->fbdev->fb->base;
8737 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8738 fb->bits_per_pixel))
8739 return NULL;
8740
8741 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8742 return NULL;
8743
8744 return fb;
8745#else
8746 return NULL;
8747#endif
8748}
8749
8750bool intel_get_load_detect_pipe(struct drm_connector *connector,
8751 struct drm_display_mode *mode,
8752 struct intel_load_detect_pipe *old,
8753 struct drm_modeset_acquire_ctx *ctx)
8754{
8755 struct intel_crtc *intel_crtc;
8756 struct intel_encoder *intel_encoder =
8757 intel_attached_encoder(connector);
8758 struct drm_crtc *possible_crtc;
8759 struct drm_encoder *encoder = &intel_encoder->base;
8760 struct drm_crtc *crtc = NULL;
8761 struct drm_device *dev = encoder->dev;
8762 struct drm_framebuffer *fb;
8763 struct drm_mode_config *config = &dev->mode_config;
8764 int ret, i = -1;
8765
8766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8767 connector->base.id, connector->name,
8768 encoder->base.id, encoder->name);
8769
8770retry:
8771 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8772 if (ret)
8773 goto fail_unlock;
8774
8775 /*
8776 * Algorithm gets a little messy:
8777 *
8778 * - if the connector already has an assigned crtc, use it (but make
8779 * sure it's on first)
8780 *
8781 * - try to find the first unused crtc that can drive this connector,
8782 * and use that if we find one
8783 */
8784
8785 /* See if we already have a CRTC for this connector */
8786 if (encoder->crtc) {
8787 crtc = encoder->crtc;
8788
8789 ret = drm_modeset_lock(&crtc->mutex, ctx);
8790 if (ret)
8791 goto fail_unlock;
8792 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8793 if (ret)
8794 goto fail_unlock;
8795
8796 old->dpms_mode = connector->dpms;
8797 old->load_detect_temp = false;
8798
8799 /* Make sure the crtc and connector are running */
8800 if (connector->dpms != DRM_MODE_DPMS_ON)
8801 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8802
8803 return true;
8804 }
8805
8806 /* Find an unused one (if possible) */
8807 for_each_crtc(dev, possible_crtc) {
8808 i++;
8809 if (!(encoder->possible_crtcs & (1 << i)))
8810 continue;
8811 if (possible_crtc->state->enable)
8812 continue;
8813 /* This can occur when applying the pipe A quirk on resume. */
8814 if (to_intel_crtc(possible_crtc)->new_enabled)
8815 continue;
8816
8817 crtc = possible_crtc;
8818 break;
8819 }
8820
8821 /*
8822 * If we didn't find an unused CRTC, don't use any.
8823 */
8824 if (!crtc) {
8825 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8826 goto fail_unlock;
8827 }
8828
8829 ret = drm_modeset_lock(&crtc->mutex, ctx);
8830 if (ret)
8831 goto fail_unlock;
8832 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8833 if (ret)
8834 goto fail_unlock;
8835 intel_encoder->new_crtc = to_intel_crtc(crtc);
8836 to_intel_connector(connector)->new_encoder = intel_encoder;
8837
8838 intel_crtc = to_intel_crtc(crtc);
8839 intel_crtc->new_enabled = true;
8840 intel_crtc->new_config = intel_crtc->config;
8841 old->dpms_mode = connector->dpms;
8842 old->load_detect_temp = true;
8843 old->release_fb = NULL;
8844
8845 if (!mode)
8846 mode = &load_detect_mode;
8847
8848 /* We need a framebuffer large enough to accommodate all accesses
8849 * that the plane may generate whilst we perform load detection.
8850 * We can not rely on the fbcon either being present (we get called
8851 * during its initialisation to detect all boot displays, or it may
8852 * not even exist) or that it is large enough to satisfy the
8853 * requested mode.
8854 */
8855 fb = mode_fits_in_fbdev(dev, mode);
8856 if (fb == NULL) {
8857 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8858 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8859 old->release_fb = fb;
8860 } else
8861 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8862 if (IS_ERR(fb)) {
8863 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8864 goto fail;
8865 }
8866
8867 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8868 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8869 if (old->release_fb)
8870 old->release_fb->funcs->destroy(old->release_fb);
8871 goto fail;
8872 }
8873 crtc->primary->crtc = crtc;
8874
8875 /* let the connector get through one full cycle before testing */
8876 intel_wait_for_vblank(dev, intel_crtc->pipe);
8877 return true;
8878
8879 fail:
8880 intel_crtc->new_enabled = crtc->state->enable;
8881 if (intel_crtc->new_enabled)
8882 intel_crtc->new_config = intel_crtc->config;
8883 else
8884 intel_crtc->new_config = NULL;
8885fail_unlock:
8886 if (ret == -EDEADLK) {
8887 drm_modeset_backoff(ctx);
8888 goto retry;
8889 }
8890
8891 return false;
8892}
8893
8894void intel_release_load_detect_pipe(struct drm_connector *connector,
8895 struct intel_load_detect_pipe *old)
8896{
8897 struct intel_encoder *intel_encoder =
8898 intel_attached_encoder(connector);
8899 struct drm_encoder *encoder = &intel_encoder->base;
8900 struct drm_crtc *crtc = encoder->crtc;
8901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8902
8903 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8904 connector->base.id, connector->name,
8905 encoder->base.id, encoder->name);
8906
8907 if (old->load_detect_temp) {
8908 to_intel_connector(connector)->new_encoder = NULL;
8909 intel_encoder->new_crtc = NULL;
8910 intel_crtc->new_enabled = false;
8911 intel_crtc->new_config = NULL;
8912 intel_set_mode(crtc, NULL, 0, 0, NULL);
8913
8914 if (old->release_fb) {
8915 drm_framebuffer_unregister_private(old->release_fb);
8916 drm_framebuffer_unreference(old->release_fb);
8917 }
8918
8919 return;
8920 }
8921
8922 /* Switch crtc and encoder back off if necessary */
8923 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8924 connector->funcs->dpms(connector, old->dpms_mode);
8925}
8926
8927static int i9xx_pll_refclk(struct drm_device *dev,
8928 const struct intel_crtc_state *pipe_config)
8929{
8930 struct drm_i915_private *dev_priv = dev->dev_private;
8931 u32 dpll = pipe_config->dpll_hw_state.dpll;
8932
8933 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8934 return dev_priv->vbt.lvds_ssc_freq;
8935 else if (HAS_PCH_SPLIT(dev))
8936 return 120000;
8937 else if (!IS_GEN2(dev))
8938 return 96000;
8939 else
8940 return 48000;
8941}
8942
8943/* Returns the clock of the currently programmed mode of the given pipe. */
8944static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8945 struct intel_crtc_state *pipe_config)
8946{
8947 struct drm_device *dev = crtc->base.dev;
8948 struct drm_i915_private *dev_priv = dev->dev_private;
8949 int pipe = pipe_config->cpu_transcoder;
8950 u32 dpll = pipe_config->dpll_hw_state.dpll;
8951 u32 fp;
8952 intel_clock_t clock;
8953 int refclk = i9xx_pll_refclk(dev, pipe_config);
8954
8955 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8956 fp = pipe_config->dpll_hw_state.fp0;
8957 else
8958 fp = pipe_config->dpll_hw_state.fp1;
8959
8960 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8961 if (IS_PINEVIEW(dev)) {
8962 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8963 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8964 } else {
8965 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8966 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8967 }
8968
8969 if (!IS_GEN2(dev)) {
8970 if (IS_PINEVIEW(dev))
8971 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8972 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8973 else
8974 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8975 DPLL_FPA01_P1_POST_DIV_SHIFT);
8976
8977 switch (dpll & DPLL_MODE_MASK) {
8978 case DPLLB_MODE_DAC_SERIAL:
8979 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8980 5 : 10;
8981 break;
8982 case DPLLB_MODE_LVDS:
8983 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8984 7 : 14;
8985 break;
8986 default:
8987 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8988 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8989 return;
8990 }
8991
8992 if (IS_PINEVIEW(dev))
8993 pineview_clock(refclk, &clock);
8994 else
8995 i9xx_clock(refclk, &clock);
8996 } else {
8997 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8998 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8999
9000 if (is_lvds) {
9001 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9002 DPLL_FPA01_P1_POST_DIV_SHIFT);
9003
9004 if (lvds & LVDS_CLKB_POWER_UP)
9005 clock.p2 = 7;
9006 else
9007 clock.p2 = 14;
9008 } else {
9009 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9010 clock.p1 = 2;
9011 else {
9012 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9013 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9014 }
9015 if (dpll & PLL_P2_DIVIDE_BY_4)
9016 clock.p2 = 4;
9017 else
9018 clock.p2 = 2;
9019 }
9020
9021 i9xx_clock(refclk, &clock);
9022 }
9023
9024 /*
9025 * This value includes pixel_multiplier. We will use
9026 * port_clock to compute adjusted_mode.crtc_clock in the
9027 * encoder's get_config() function.
9028 */
9029 pipe_config->port_clock = clock.dot;
9030}
9031
9032int intel_dotclock_calculate(int link_freq,
9033 const struct intel_link_m_n *m_n)
9034{
9035 /*
9036 * The calculation for the data clock is:
9037 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9038 * But we want to avoid losing precison if possible, so:
9039 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9040 *
9041 * and the link clock is simpler:
9042 * link_clock = (m * link_clock) / n
9043 */
9044
9045 if (!m_n->link_n)
9046 return 0;
9047
9048 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9049}
9050
9051static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9052 struct intel_crtc_state *pipe_config)
9053{
9054 struct drm_device *dev = crtc->base.dev;
9055
9056 /* read out port_clock from the DPLL */
9057 i9xx_crtc_clock_get(crtc, pipe_config);
9058
9059 /*
9060 * This value does not include pixel_multiplier.
9061 * We will check that port_clock and adjusted_mode.crtc_clock
9062 * agree once we know their relationship in the encoder's
9063 * get_config() function.
9064 */
9065 pipe_config->base.adjusted_mode.crtc_clock =
9066 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9067 &pipe_config->fdi_m_n);
9068}
9069
9070/** Returns the currently programmed mode of the given pipe. */
9071struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9072 struct drm_crtc *crtc)
9073{
9074 struct drm_i915_private *dev_priv = dev->dev_private;
9075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9076 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9077 struct drm_display_mode *mode;
9078 struct intel_crtc_state pipe_config;
9079 int htot = I915_READ(HTOTAL(cpu_transcoder));
9080 int hsync = I915_READ(HSYNC(cpu_transcoder));
9081 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9082 int vsync = I915_READ(VSYNC(cpu_transcoder));
9083 enum pipe pipe = intel_crtc->pipe;
9084
9085 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9086 if (!mode)
9087 return NULL;
9088
9089 /*
9090 * Construct a pipe_config sufficient for getting the clock info
9091 * back out of crtc_clock_get.
9092 *
9093 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9094 * to use a real value here instead.
9095 */
9096 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9097 pipe_config.pixel_multiplier = 1;
9098 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9099 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9100 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9101 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9102
9103 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9104 mode->hdisplay = (htot & 0xffff) + 1;
9105 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9106 mode->hsync_start = (hsync & 0xffff) + 1;
9107 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9108 mode->vdisplay = (vtot & 0xffff) + 1;
9109 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9110 mode->vsync_start = (vsync & 0xffff) + 1;
9111 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9112
9113 drm_mode_set_name(mode);
9114
9115 return mode;
9116}
9117
9118static void intel_decrease_pllclock(struct drm_crtc *crtc)
9119{
9120 struct drm_device *dev = crtc->dev;
9121 struct drm_i915_private *dev_priv = dev->dev_private;
9122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9123
9124 if (!HAS_GMCH_DISPLAY(dev))
9125 return;
9126
9127 if (!dev_priv->lvds_downclock_avail)
9128 return;
9129
9130 /*
9131 * Since this is called by a timer, we should never get here in
9132 * the manual case.
9133 */
9134 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9135 int pipe = intel_crtc->pipe;
9136 int dpll_reg = DPLL(pipe);
9137 int dpll;
9138
9139 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9140
9141 assert_panel_unlocked(dev_priv, pipe);
9142
9143 dpll = I915_READ(dpll_reg);
9144 dpll |= DISPLAY_RATE_SELECT_FPA1;
9145 I915_WRITE(dpll_reg, dpll);
9146 intel_wait_for_vblank(dev, pipe);
9147 dpll = I915_READ(dpll_reg);
9148 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9149 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9150 }
9151
9152}
9153
9154void intel_mark_busy(struct drm_device *dev)
9155{
9156 struct drm_i915_private *dev_priv = dev->dev_private;
9157
9158 if (dev_priv->mm.busy)
9159 return;
9160
9161 intel_runtime_pm_get(dev_priv);
9162 i915_update_gfx_val(dev_priv);
9163 dev_priv->mm.busy = true;
9164}
9165
9166void intel_mark_idle(struct drm_device *dev)
9167{
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 struct drm_crtc *crtc;
9170
9171 if (!dev_priv->mm.busy)
9172 return;
9173
9174 dev_priv->mm.busy = false;
9175
9176 if (!i915.powersave)
9177 goto out;
9178
9179 for_each_crtc(dev, crtc) {
9180 if (!crtc->primary->fb)
9181 continue;
9182
9183 intel_decrease_pllclock(crtc);
9184 }
9185
9186 if (INTEL_INFO(dev)->gen >= 6)
9187 gen6_rps_idle(dev->dev_private);
9188
9189out:
9190 intel_runtime_pm_put(dev_priv);
9191}
9192
9193static void intel_crtc_set_state(struct intel_crtc *crtc,
9194 struct intel_crtc_state *crtc_state)
9195{
9196 kfree(crtc->config);
9197 crtc->config = crtc_state;
9198 crtc->base.state = &crtc_state->base;
9199}
9200
9201static void intel_crtc_destroy(struct drm_crtc *crtc)
9202{
9203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9204 struct drm_device *dev = crtc->dev;
9205 struct intel_unpin_work *work;
9206
9207 spin_lock_irq(&dev->event_lock);
9208 work = intel_crtc->unpin_work;
9209 intel_crtc->unpin_work = NULL;
9210 spin_unlock_irq(&dev->event_lock);
9211
9212 if (work) {
9213 cancel_work_sync(&work->work);
9214 kfree(work);
9215 }
9216
9217 intel_crtc_set_state(intel_crtc, NULL);
9218 drm_crtc_cleanup(crtc);
9219
9220 kfree(intel_crtc);
9221}
9222
9223static void intel_unpin_work_fn(struct work_struct *__work)
9224{
9225 struct intel_unpin_work *work =
9226 container_of(__work, struct intel_unpin_work, work);
9227 struct drm_device *dev = work->crtc->dev;
9228 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9229
9230 mutex_lock(&dev->struct_mutex);
9231 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9232 drm_gem_object_unreference(&work->pending_flip_obj->base);
9233 drm_framebuffer_unreference(work->old_fb);
9234
9235 intel_fbc_update(dev);
9236
9237 if (work->flip_queued_req)
9238 i915_gem_request_assign(&work->flip_queued_req, NULL);
9239 mutex_unlock(&dev->struct_mutex);
9240
9241 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9242
9243 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9244 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9245
9246 kfree(work);
9247}
9248
9249static void do_intel_finish_page_flip(struct drm_device *dev,
9250 struct drm_crtc *crtc)
9251{
9252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9253 struct intel_unpin_work *work;
9254 unsigned long flags;
9255
9256 /* Ignore early vblank irqs */
9257 if (intel_crtc == NULL)
9258 return;
9259
9260 /*
9261 * This is called both by irq handlers and the reset code (to complete
9262 * lost pageflips) so needs the full irqsave spinlocks.
9263 */
9264 spin_lock_irqsave(&dev->event_lock, flags);
9265 work = intel_crtc->unpin_work;
9266
9267 /* Ensure we don't miss a work->pending update ... */
9268 smp_rmb();
9269
9270 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9271 spin_unlock_irqrestore(&dev->event_lock, flags);
9272 return;
9273 }
9274
9275 page_flip_completed(intel_crtc);
9276
9277 spin_unlock_irqrestore(&dev->event_lock, flags);
9278}
9279
9280void intel_finish_page_flip(struct drm_device *dev, int pipe)
9281{
9282 struct drm_i915_private *dev_priv = dev->dev_private;
9283 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9284
9285 do_intel_finish_page_flip(dev, crtc);
9286}
9287
9288void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9289{
9290 struct drm_i915_private *dev_priv = dev->dev_private;
9291 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9292
9293 do_intel_finish_page_flip(dev, crtc);
9294}
9295
9296/* Is 'a' after or equal to 'b'? */
9297static bool g4x_flip_count_after_eq(u32 a, u32 b)
9298{
9299 return !((a - b) & 0x80000000);
9300}
9301
9302static bool page_flip_finished(struct intel_crtc *crtc)
9303{
9304 struct drm_device *dev = crtc->base.dev;
9305 struct drm_i915_private *dev_priv = dev->dev_private;
9306
9307 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9308 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9309 return true;
9310
9311 /*
9312 * The relevant registers doen't exist on pre-ctg.
9313 * As the flip done interrupt doesn't trigger for mmio
9314 * flips on gmch platforms, a flip count check isn't
9315 * really needed there. But since ctg has the registers,
9316 * include it in the check anyway.
9317 */
9318 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9319 return true;
9320
9321 /*
9322 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9323 * used the same base address. In that case the mmio flip might
9324 * have completed, but the CS hasn't even executed the flip yet.
9325 *
9326 * A flip count check isn't enough as the CS might have updated
9327 * the base address just after start of vblank, but before we
9328 * managed to process the interrupt. This means we'd complete the
9329 * CS flip too soon.
9330 *
9331 * Combining both checks should get us a good enough result. It may
9332 * still happen that the CS flip has been executed, but has not
9333 * yet actually completed. But in case the base address is the same
9334 * anyway, we don't really care.
9335 */
9336 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9337 crtc->unpin_work->gtt_offset &&
9338 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9339 crtc->unpin_work->flip_count);
9340}
9341
9342void intel_prepare_page_flip(struct drm_device *dev, int plane)
9343{
9344 struct drm_i915_private *dev_priv = dev->dev_private;
9345 struct intel_crtc *intel_crtc =
9346 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9347 unsigned long flags;
9348
9349
9350 /*
9351 * This is called both by irq handlers and the reset code (to complete
9352 * lost pageflips) so needs the full irqsave spinlocks.
9353 *
9354 * NB: An MMIO update of the plane base pointer will also
9355 * generate a page-flip completion irq, i.e. every modeset
9356 * is also accompanied by a spurious intel_prepare_page_flip().
9357 */
9358 spin_lock_irqsave(&dev->event_lock, flags);
9359 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9360 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9361 spin_unlock_irqrestore(&dev->event_lock, flags);
9362}
9363
9364static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9365{
9366 /* Ensure that the work item is consistent when activating it ... */
9367 smp_wmb();
9368 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9369 /* and that it is marked active as soon as the irq could fire. */
9370 smp_wmb();
9371}
9372
9373static int intel_gen2_queue_flip(struct drm_device *dev,
9374 struct drm_crtc *crtc,
9375 struct drm_framebuffer *fb,
9376 struct drm_i915_gem_object *obj,
9377 struct intel_engine_cs *ring,
9378 uint32_t flags)
9379{
9380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9381 u32 flip_mask;
9382 int ret;
9383
9384 ret = intel_ring_begin(ring, 6);
9385 if (ret)
9386 return ret;
9387
9388 /* Can't queue multiple flips, so wait for the previous
9389 * one to finish before executing the next.
9390 */
9391 if (intel_crtc->plane)
9392 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9393 else
9394 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9395 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9396 intel_ring_emit(ring, MI_NOOP);
9397 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9398 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9399 intel_ring_emit(ring, fb->pitches[0]);
9400 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9401 intel_ring_emit(ring, 0); /* aux display base address, unused */
9402
9403 intel_mark_page_flip_active(intel_crtc);
9404 __intel_ring_advance(ring);
9405 return 0;
9406}
9407
9408static int intel_gen3_queue_flip(struct drm_device *dev,
9409 struct drm_crtc *crtc,
9410 struct drm_framebuffer *fb,
9411 struct drm_i915_gem_object *obj,
9412 struct intel_engine_cs *ring,
9413 uint32_t flags)
9414{
9415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9416 u32 flip_mask;
9417 int ret;
9418
9419 ret = intel_ring_begin(ring, 6);
9420 if (ret)
9421 return ret;
9422
9423 if (intel_crtc->plane)
9424 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9425 else
9426 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9427 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9428 intel_ring_emit(ring, MI_NOOP);
9429 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9430 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9431 intel_ring_emit(ring, fb->pitches[0]);
9432 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9433 intel_ring_emit(ring, MI_NOOP);
9434
9435 intel_mark_page_flip_active(intel_crtc);
9436 __intel_ring_advance(ring);
9437 return 0;
9438}
9439
9440static int intel_gen4_queue_flip(struct drm_device *dev,
9441 struct drm_crtc *crtc,
9442 struct drm_framebuffer *fb,
9443 struct drm_i915_gem_object *obj,
9444 struct intel_engine_cs *ring,
9445 uint32_t flags)
9446{
9447 struct drm_i915_private *dev_priv = dev->dev_private;
9448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9449 uint32_t pf, pipesrc;
9450 int ret;
9451
9452 ret = intel_ring_begin(ring, 4);
9453 if (ret)
9454 return ret;
9455
9456 /* i965+ uses the linear or tiled offsets from the
9457 * Display Registers (which do not change across a page-flip)
9458 * so we need only reprogram the base address.
9459 */
9460 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9461 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9462 intel_ring_emit(ring, fb->pitches[0]);
9463 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9464 obj->tiling_mode);
9465
9466 /* XXX Enabling the panel-fitter across page-flip is so far
9467 * untested on non-native modes, so ignore it for now.
9468 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9469 */
9470 pf = 0;
9471 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9472 intel_ring_emit(ring, pf | pipesrc);
9473
9474 intel_mark_page_flip_active(intel_crtc);
9475 __intel_ring_advance(ring);
9476 return 0;
9477}
9478
9479static int intel_gen6_queue_flip(struct drm_device *dev,
9480 struct drm_crtc *crtc,
9481 struct drm_framebuffer *fb,
9482 struct drm_i915_gem_object *obj,
9483 struct intel_engine_cs *ring,
9484 uint32_t flags)
9485{
9486 struct drm_i915_private *dev_priv = dev->dev_private;
9487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9488 uint32_t pf, pipesrc;
9489 int ret;
9490
9491 ret = intel_ring_begin(ring, 4);
9492 if (ret)
9493 return ret;
9494
9495 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9496 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9497 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9498 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9499
9500 /* Contrary to the suggestions in the documentation,
9501 * "Enable Panel Fitter" does not seem to be required when page
9502 * flipping with a non-native mode, and worse causes a normal
9503 * modeset to fail.
9504 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9505 */
9506 pf = 0;
9507 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9508 intel_ring_emit(ring, pf | pipesrc);
9509
9510 intel_mark_page_flip_active(intel_crtc);
9511 __intel_ring_advance(ring);
9512 return 0;
9513}
9514
9515static int intel_gen7_queue_flip(struct drm_device *dev,
9516 struct drm_crtc *crtc,
9517 struct drm_framebuffer *fb,
9518 struct drm_i915_gem_object *obj,
9519 struct intel_engine_cs *ring,
9520 uint32_t flags)
9521{
9522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9523 uint32_t plane_bit = 0;
9524 int len, ret;
9525
9526 switch (intel_crtc->plane) {
9527 case PLANE_A:
9528 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9529 break;
9530 case PLANE_B:
9531 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9532 break;
9533 case PLANE_C:
9534 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9535 break;
9536 default:
9537 WARN_ONCE(1, "unknown plane in flip command\n");
9538 return -ENODEV;
9539 }
9540
9541 len = 4;
9542 if (ring->id == RCS) {
9543 len += 6;
9544 /*
9545 * On Gen 8, SRM is now taking an extra dword to accommodate
9546 * 48bits addresses, and we need a NOOP for the batch size to
9547 * stay even.
9548 */
9549 if (IS_GEN8(dev))
9550 len += 2;
9551 }
9552
9553 /*
9554 * BSpec MI_DISPLAY_FLIP for IVB:
9555 * "The full packet must be contained within the same cache line."
9556 *
9557 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9558 * cacheline, if we ever start emitting more commands before
9559 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9560 * then do the cacheline alignment, and finally emit the
9561 * MI_DISPLAY_FLIP.
9562 */
9563 ret = intel_ring_cacheline_align(ring);
9564 if (ret)
9565 return ret;
9566
9567 ret = intel_ring_begin(ring, len);
9568 if (ret)
9569 return ret;
9570
9571 /* Unmask the flip-done completion message. Note that the bspec says that
9572 * we should do this for both the BCS and RCS, and that we must not unmask
9573 * more than one flip event at any time (or ensure that one flip message
9574 * can be sent by waiting for flip-done prior to queueing new flips).
9575 * Experimentation says that BCS works despite DERRMR masking all
9576 * flip-done completion events and that unmasking all planes at once
9577 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9578 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9579 */
9580 if (ring->id == RCS) {
9581 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9582 intel_ring_emit(ring, DERRMR);
9583 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9584 DERRMR_PIPEB_PRI_FLIP_DONE |
9585 DERRMR_PIPEC_PRI_FLIP_DONE));
9586 if (IS_GEN8(dev))
9587 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9588 MI_SRM_LRM_GLOBAL_GTT);
9589 else
9590 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9591 MI_SRM_LRM_GLOBAL_GTT);
9592 intel_ring_emit(ring, DERRMR);
9593 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9594 if (IS_GEN8(dev)) {
9595 intel_ring_emit(ring, 0);
9596 intel_ring_emit(ring, MI_NOOP);
9597 }
9598 }
9599
9600 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9601 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9602 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9603 intel_ring_emit(ring, (MI_NOOP));
9604
9605 intel_mark_page_flip_active(intel_crtc);
9606 __intel_ring_advance(ring);
9607 return 0;
9608}
9609
9610static bool use_mmio_flip(struct intel_engine_cs *ring,
9611 struct drm_i915_gem_object *obj)
9612{
9613 /*
9614 * This is not being used for older platforms, because
9615 * non-availability of flip done interrupt forces us to use
9616 * CS flips. Older platforms derive flip done using some clever
9617 * tricks involving the flip_pending status bits and vblank irqs.
9618 * So using MMIO flips there would disrupt this mechanism.
9619 */
9620
9621 if (ring == NULL)
9622 return true;
9623
9624 if (INTEL_INFO(ring->dev)->gen < 5)
9625 return false;
9626
9627 if (i915.use_mmio_flip < 0)
9628 return false;
9629 else if (i915.use_mmio_flip > 0)
9630 return true;
9631 else if (i915.enable_execlists)
9632 return true;
9633 else
9634 return ring != i915_gem_request_get_ring(obj->last_read_req);
9635}
9636
9637static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9638{
9639 struct drm_device *dev = intel_crtc->base.dev;
9640 struct drm_i915_private *dev_priv = dev->dev_private;
9641 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9642 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9643 struct drm_i915_gem_object *obj = intel_fb->obj;
9644 const enum pipe pipe = intel_crtc->pipe;
9645 u32 ctl, stride;
9646
9647 ctl = I915_READ(PLANE_CTL(pipe, 0));
9648 ctl &= ~PLANE_CTL_TILED_MASK;
9649 if (obj->tiling_mode == I915_TILING_X)
9650 ctl |= PLANE_CTL_TILED_X;
9651
9652 /*
9653 * The stride is either expressed as a multiple of 64 bytes chunks for
9654 * linear buffers or in number of tiles for tiled buffers.
9655 */
9656 stride = fb->pitches[0] >> 6;
9657 if (obj->tiling_mode == I915_TILING_X)
9658 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9659
9660 /*
9661 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9662 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9663 */
9664 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9665 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9666
9667 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9668 POSTING_READ(PLANE_SURF(pipe, 0));
9669}
9670
9671static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9672{
9673 struct drm_device *dev = intel_crtc->base.dev;
9674 struct drm_i915_private *dev_priv = dev->dev_private;
9675 struct intel_framebuffer *intel_fb =
9676 to_intel_framebuffer(intel_crtc->base.primary->fb);
9677 struct drm_i915_gem_object *obj = intel_fb->obj;
9678 u32 dspcntr;
9679 u32 reg;
9680
9681 reg = DSPCNTR(intel_crtc->plane);
9682 dspcntr = I915_READ(reg);
9683
9684 if (obj->tiling_mode != I915_TILING_NONE)
9685 dspcntr |= DISPPLANE_TILED;
9686 else
9687 dspcntr &= ~DISPPLANE_TILED;
9688
9689 I915_WRITE(reg, dspcntr);
9690
9691 I915_WRITE(DSPSURF(intel_crtc->plane),
9692 intel_crtc->unpin_work->gtt_offset);
9693 POSTING_READ(DSPSURF(intel_crtc->plane));
9694
9695}
9696
9697/*
9698 * XXX: This is the temporary way to update the plane registers until we get
9699 * around to using the usual plane update functions for MMIO flips
9700 */
9701static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9702{
9703 struct drm_device *dev = intel_crtc->base.dev;
9704 bool atomic_update;
9705 u32 start_vbl_count;
9706
9707 intel_mark_page_flip_active(intel_crtc);
9708
9709 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9710
9711 if (INTEL_INFO(dev)->gen >= 9)
9712 skl_do_mmio_flip(intel_crtc);
9713 else
9714 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9715 ilk_do_mmio_flip(intel_crtc);
9716
9717 if (atomic_update)
9718 intel_pipe_update_end(intel_crtc, start_vbl_count);
9719}
9720
9721static void intel_mmio_flip_work_func(struct work_struct *work)
9722{
9723 struct intel_crtc *crtc =
9724 container_of(work, struct intel_crtc, mmio_flip.work);
9725 struct intel_mmio_flip *mmio_flip;
9726
9727 mmio_flip = &crtc->mmio_flip;
9728 if (mmio_flip->req)
9729 WARN_ON(__i915_wait_request(mmio_flip->req,
9730 crtc->reset_counter,
9731 false, NULL, NULL) != 0);
9732
9733 intel_do_mmio_flip(crtc);
9734 if (mmio_flip->req) {
9735 mutex_lock(&crtc->base.dev->struct_mutex);
9736 i915_gem_request_assign(&mmio_flip->req, NULL);
9737 mutex_unlock(&crtc->base.dev->struct_mutex);
9738 }
9739}
9740
9741static int intel_queue_mmio_flip(struct drm_device *dev,
9742 struct drm_crtc *crtc,
9743 struct drm_framebuffer *fb,
9744 struct drm_i915_gem_object *obj,
9745 struct intel_engine_cs *ring,
9746 uint32_t flags)
9747{
9748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9749
9750 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9751 obj->last_write_req);
9752
9753 schedule_work(&intel_crtc->mmio_flip.work);
9754
9755 return 0;
9756}
9757
9758static int intel_default_queue_flip(struct drm_device *dev,
9759 struct drm_crtc *crtc,
9760 struct drm_framebuffer *fb,
9761 struct drm_i915_gem_object *obj,
9762 struct intel_engine_cs *ring,
9763 uint32_t flags)
9764{
9765 return -ENODEV;
9766}
9767
9768static bool __intel_pageflip_stall_check(struct drm_device *dev,
9769 struct drm_crtc *crtc)
9770{
9771 struct drm_i915_private *dev_priv = dev->dev_private;
9772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9773 struct intel_unpin_work *work = intel_crtc->unpin_work;
9774 u32 addr;
9775
9776 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9777 return true;
9778
9779 if (!work->enable_stall_check)
9780 return false;
9781
9782 if (work->flip_ready_vblank == 0) {
9783 if (work->flip_queued_req &&
9784 !i915_gem_request_completed(work->flip_queued_req, true))
9785 return false;
9786
9787 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9788 }
9789
9790 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9791 return false;
9792
9793 /* Potential stall - if we see that the flip has happened,
9794 * assume a missed interrupt. */
9795 if (INTEL_INFO(dev)->gen >= 4)
9796 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9797 else
9798 addr = I915_READ(DSPADDR(intel_crtc->plane));
9799
9800 /* There is a potential issue here with a false positive after a flip
9801 * to the same address. We could address this by checking for a
9802 * non-incrementing frame counter.
9803 */
9804 return addr == work->gtt_offset;
9805}
9806
9807void intel_check_page_flip(struct drm_device *dev, int pipe)
9808{
9809 struct drm_i915_private *dev_priv = dev->dev_private;
9810 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9812
9813 WARN_ON(!in_irq());
9814
9815 if (crtc == NULL)
9816 return;
9817
9818 spin_lock(&dev->event_lock);
9819 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9820 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9821 intel_crtc->unpin_work->flip_queued_vblank,
9822 drm_vblank_count(dev, pipe));
9823 page_flip_completed(intel_crtc);
9824 }
9825 spin_unlock(&dev->event_lock);
9826}
9827
9828static int intel_crtc_page_flip(struct drm_crtc *crtc,
9829 struct drm_framebuffer *fb,
9830 struct drm_pending_vblank_event *event,
9831 uint32_t page_flip_flags)
9832{
9833 struct drm_device *dev = crtc->dev;
9834 struct drm_i915_private *dev_priv = dev->dev_private;
9835 struct drm_framebuffer *old_fb = crtc->primary->fb;
9836 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9838 struct drm_plane *primary = crtc->primary;
9839 enum pipe pipe = intel_crtc->pipe;
9840 struct intel_unpin_work *work;
9841 struct intel_engine_cs *ring;
9842 int ret;
9843
9844 /*
9845 * drm_mode_page_flip_ioctl() should already catch this, but double
9846 * check to be safe. In the future we may enable pageflipping from
9847 * a disabled primary plane.
9848 */
9849 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9850 return -EBUSY;
9851
9852 /* Can't change pixel format via MI display flips. */
9853 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9854 return -EINVAL;
9855
9856 /*
9857 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9858 * Note that pitch changes could also affect these register.
9859 */
9860 if (INTEL_INFO(dev)->gen > 3 &&
9861 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9862 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9863 return -EINVAL;
9864
9865 if (i915_terminally_wedged(&dev_priv->gpu_error))
9866 goto out_hang;
9867
9868 work = kzalloc(sizeof(*work), GFP_KERNEL);
9869 if (work == NULL)
9870 return -ENOMEM;
9871
9872 work->event = event;
9873 work->crtc = crtc;
9874 work->old_fb = old_fb;
9875 INIT_WORK(&work->work, intel_unpin_work_fn);
9876
9877 ret = drm_crtc_vblank_get(crtc);
9878 if (ret)
9879 goto free_work;
9880
9881 /* We borrow the event spin lock for protecting unpin_work */
9882 spin_lock_irq(&dev->event_lock);
9883 if (intel_crtc->unpin_work) {
9884 /* Before declaring the flip queue wedged, check if
9885 * the hardware completed the operation behind our backs.
9886 */
9887 if (__intel_pageflip_stall_check(dev, crtc)) {
9888 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9889 page_flip_completed(intel_crtc);
9890 } else {
9891 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9892 spin_unlock_irq(&dev->event_lock);
9893
9894 drm_crtc_vblank_put(crtc);
9895 kfree(work);
9896 return -EBUSY;
9897 }
9898 }
9899 intel_crtc->unpin_work = work;
9900 spin_unlock_irq(&dev->event_lock);
9901
9902 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9903 flush_workqueue(dev_priv->wq);
9904
9905 ret = i915_mutex_lock_interruptible(dev);
9906 if (ret)
9907 goto cleanup;
9908
9909 /* Reference the objects for the scheduled work. */
9910 drm_framebuffer_reference(work->old_fb);
9911 drm_gem_object_reference(&obj->base);
9912
9913 crtc->primary->fb = fb;
9914 update_state_fb(crtc->primary);
9915
9916 work->pending_flip_obj = obj;
9917
9918 atomic_inc(&intel_crtc->unpin_work_count);
9919 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9920
9921 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9922 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9923
9924 if (IS_VALLEYVIEW(dev)) {
9925 ring = &dev_priv->ring[BCS];
9926 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9927 /* vlv: DISPLAY_FLIP fails to change tiling */
9928 ring = NULL;
9929 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9930 ring = &dev_priv->ring[BCS];
9931 } else if (INTEL_INFO(dev)->gen >= 7) {
9932 ring = i915_gem_request_get_ring(obj->last_read_req);
9933 if (ring == NULL || ring->id != RCS)
9934 ring = &dev_priv->ring[BCS];
9935 } else {
9936 ring = &dev_priv->ring[RCS];
9937 }
9938
9939 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9940 if (ret)
9941 goto cleanup_pending;
9942
9943 work->gtt_offset =
9944 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9945
9946 if (use_mmio_flip(ring, obj)) {
9947 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9948 page_flip_flags);
9949 if (ret)
9950 goto cleanup_unpin;
9951
9952 i915_gem_request_assign(&work->flip_queued_req,
9953 obj->last_write_req);
9954 } else {
9955 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9956 page_flip_flags);
9957 if (ret)
9958 goto cleanup_unpin;
9959
9960 i915_gem_request_assign(&work->flip_queued_req,
9961 intel_ring_get_request(ring));
9962 }
9963
9964 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9965 work->enable_stall_check = true;
9966
9967 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9968 INTEL_FRONTBUFFER_PRIMARY(pipe));
9969
9970 intel_fbc_disable(dev);
9971 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9972 mutex_unlock(&dev->struct_mutex);
9973
9974 trace_i915_flip_request(intel_crtc->plane, obj);
9975
9976 return 0;
9977
9978cleanup_unpin:
9979 intel_unpin_fb_obj(obj);
9980cleanup_pending:
9981 atomic_dec(&intel_crtc->unpin_work_count);
9982 crtc->primary->fb = old_fb;
9983 update_state_fb(crtc->primary);
9984 drm_framebuffer_unreference(work->old_fb);
9985 drm_gem_object_unreference(&obj->base);
9986 mutex_unlock(&dev->struct_mutex);
9987
9988cleanup:
9989 spin_lock_irq(&dev->event_lock);
9990 intel_crtc->unpin_work = NULL;
9991 spin_unlock_irq(&dev->event_lock);
9992
9993 drm_crtc_vblank_put(crtc);
9994free_work:
9995 kfree(work);
9996
9997 if (ret == -EIO) {
9998out_hang:
9999 ret = intel_plane_restore(primary);
10000 if (ret == 0 && event) {
10001 spin_lock_irq(&dev->event_lock);
10002 drm_send_vblank_event(dev, pipe, event);
10003 spin_unlock_irq(&dev->event_lock);
10004 }
10005 }
10006 return ret;
10007}
10008
10009static struct drm_crtc_helper_funcs intel_helper_funcs = {
10010 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10011 .load_lut = intel_crtc_load_lut,
10012 .atomic_begin = intel_begin_crtc_commit,
10013 .atomic_flush = intel_finish_crtc_commit,
10014};
10015
10016/**
10017 * intel_modeset_update_staged_output_state
10018 *
10019 * Updates the staged output configuration state, e.g. after we've read out the
10020 * current hw state.
10021 */
10022static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10023{
10024 struct intel_crtc *crtc;
10025 struct intel_encoder *encoder;
10026 struct intel_connector *connector;
10027
10028 for_each_intel_connector(dev, connector) {
10029 connector->new_encoder =
10030 to_intel_encoder(connector->base.encoder);
10031 }
10032
10033 for_each_intel_encoder(dev, encoder) {
10034 encoder->new_crtc =
10035 to_intel_crtc(encoder->base.crtc);
10036 }
10037
10038 for_each_intel_crtc(dev, crtc) {
10039 crtc->new_enabled = crtc->base.state->enable;
10040
10041 if (crtc->new_enabled)
10042 crtc->new_config = crtc->config;
10043 else
10044 crtc->new_config = NULL;
10045 }
10046}
10047
10048/**
10049 * intel_modeset_commit_output_state
10050 *
10051 * This function copies the stage display pipe configuration to the real one.
10052 */
10053static void intel_modeset_commit_output_state(struct drm_device *dev)
10054{
10055 struct intel_crtc *crtc;
10056 struct intel_encoder *encoder;
10057 struct intel_connector *connector;
10058
10059 for_each_intel_connector(dev, connector) {
10060 connector->base.encoder = &connector->new_encoder->base;
10061 }
10062
10063 for_each_intel_encoder(dev, encoder) {
10064 encoder->base.crtc = &encoder->new_crtc->base;
10065 }
10066
10067 for_each_intel_crtc(dev, crtc) {
10068 crtc->base.state->enable = crtc->new_enabled;
10069 crtc->base.enabled = crtc->new_enabled;
10070 }
10071}
10072
10073static void
10074connected_sink_compute_bpp(struct intel_connector *connector,
10075 struct intel_crtc_state *pipe_config)
10076{
10077 int bpp = pipe_config->pipe_bpp;
10078
10079 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10080 connector->base.base.id,
10081 connector->base.name);
10082
10083 /* Don't use an invalid EDID bpc value */
10084 if (connector->base.display_info.bpc &&
10085 connector->base.display_info.bpc * 3 < bpp) {
10086 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10087 bpp, connector->base.display_info.bpc*3);
10088 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10089 }
10090
10091 /* Clamp bpp to 8 on screens without EDID 1.4 */
10092 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10093 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10094 bpp);
10095 pipe_config->pipe_bpp = 24;
10096 }
10097}
10098
10099static int
10100compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10101 struct drm_framebuffer *fb,
10102 struct intel_crtc_state *pipe_config)
10103{
10104 struct drm_device *dev = crtc->base.dev;
10105 struct intel_connector *connector;
10106 int bpp;
10107
10108 switch (fb->pixel_format) {
10109 case DRM_FORMAT_C8:
10110 bpp = 8*3; /* since we go through a colormap */
10111 break;
10112 case DRM_FORMAT_XRGB1555:
10113 case DRM_FORMAT_ARGB1555:
10114 /* checked in intel_framebuffer_init already */
10115 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10116 return -EINVAL;
10117 case DRM_FORMAT_RGB565:
10118 bpp = 6*3; /* min is 18bpp */
10119 break;
10120 case DRM_FORMAT_XBGR8888:
10121 case DRM_FORMAT_ABGR8888:
10122 /* checked in intel_framebuffer_init already */
10123 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10124 return -EINVAL;
10125 case DRM_FORMAT_XRGB8888:
10126 case DRM_FORMAT_ARGB8888:
10127 bpp = 8*3;
10128 break;
10129 case DRM_FORMAT_XRGB2101010:
10130 case DRM_FORMAT_ARGB2101010:
10131 case DRM_FORMAT_XBGR2101010:
10132 case DRM_FORMAT_ABGR2101010:
10133 /* checked in intel_framebuffer_init already */
10134 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10135 return -EINVAL;
10136 bpp = 10*3;
10137 break;
10138 /* TODO: gen4+ supports 16 bpc floating point, too. */
10139 default:
10140 DRM_DEBUG_KMS("unsupported depth\n");
10141 return -EINVAL;
10142 }
10143
10144 pipe_config->pipe_bpp = bpp;
10145
10146 /* Clamp display bpp to EDID value */
10147 for_each_intel_connector(dev, connector) {
10148 if (!connector->new_encoder ||
10149 connector->new_encoder->new_crtc != crtc)
10150 continue;
10151
10152 connected_sink_compute_bpp(connector, pipe_config);
10153 }
10154
10155 return bpp;
10156}
10157
10158static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10159{
10160 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10161 "type: 0x%x flags: 0x%x\n",
10162 mode->crtc_clock,
10163 mode->crtc_hdisplay, mode->crtc_hsync_start,
10164 mode->crtc_hsync_end, mode->crtc_htotal,
10165 mode->crtc_vdisplay, mode->crtc_vsync_start,
10166 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10167}
10168
10169static void intel_dump_pipe_config(struct intel_crtc *crtc,
10170 struct intel_crtc_state *pipe_config,
10171 const char *context)
10172{
10173 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10174 context, pipe_name(crtc->pipe));
10175
10176 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10177 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10178 pipe_config->pipe_bpp, pipe_config->dither);
10179 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10180 pipe_config->has_pch_encoder,
10181 pipe_config->fdi_lanes,
10182 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10183 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10184 pipe_config->fdi_m_n.tu);
10185 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10186 pipe_config->has_dp_encoder,
10187 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10188 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10189 pipe_config->dp_m_n.tu);
10190
10191 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10192 pipe_config->has_dp_encoder,
10193 pipe_config->dp_m2_n2.gmch_m,
10194 pipe_config->dp_m2_n2.gmch_n,
10195 pipe_config->dp_m2_n2.link_m,
10196 pipe_config->dp_m2_n2.link_n,
10197 pipe_config->dp_m2_n2.tu);
10198
10199 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10200 pipe_config->has_audio,
10201 pipe_config->has_infoframe);
10202
10203 DRM_DEBUG_KMS("requested mode:\n");
10204 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10205 DRM_DEBUG_KMS("adjusted mode:\n");
10206 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10207 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10208 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10209 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10210 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10211 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10212 pipe_config->gmch_pfit.control,
10213 pipe_config->gmch_pfit.pgm_ratios,
10214 pipe_config->gmch_pfit.lvds_border_bits);
10215 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10216 pipe_config->pch_pfit.pos,
10217 pipe_config->pch_pfit.size,
10218 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10219 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10220 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10221}
10222
10223static bool encoders_cloneable(const struct intel_encoder *a,
10224 const struct intel_encoder *b)
10225{
10226 /* masks could be asymmetric, so check both ways */
10227 return a == b || (a->cloneable & (1 << b->type) &&
10228 b->cloneable & (1 << a->type));
10229}
10230
10231static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10232 struct intel_encoder *encoder)
10233{
10234 struct drm_device *dev = crtc->base.dev;
10235 struct intel_encoder *source_encoder;
10236
10237 for_each_intel_encoder(dev, source_encoder) {
10238 if (source_encoder->new_crtc != crtc)
10239 continue;
10240
10241 if (!encoders_cloneable(encoder, source_encoder))
10242 return false;
10243 }
10244
10245 return true;
10246}
10247
10248static bool check_encoder_cloning(struct intel_crtc *crtc)
10249{
10250 struct drm_device *dev = crtc->base.dev;
10251 struct intel_encoder *encoder;
10252
10253 for_each_intel_encoder(dev, encoder) {
10254 if (encoder->new_crtc != crtc)
10255 continue;
10256
10257 if (!check_single_encoder_cloning(crtc, encoder))
10258 return false;
10259 }
10260
10261 return true;
10262}
10263
10264static bool check_digital_port_conflicts(struct drm_device *dev)
10265{
10266 struct intel_connector *connector;
10267 unsigned int used_ports = 0;
10268
10269 /*
10270 * Walk the connector list instead of the encoder
10271 * list to detect the problem on ddi platforms
10272 * where there's just one encoder per digital port.
10273 */
10274 for_each_intel_connector(dev, connector) {
10275 struct intel_encoder *encoder = connector->new_encoder;
10276
10277 if (!encoder)
10278 continue;
10279
10280 WARN_ON(!encoder->new_crtc);
10281
10282 switch (encoder->type) {
10283 unsigned int port_mask;
10284 case INTEL_OUTPUT_UNKNOWN:
10285 if (WARN_ON(!HAS_DDI(dev)))
10286 break;
10287 case INTEL_OUTPUT_DISPLAYPORT:
10288 case INTEL_OUTPUT_HDMI:
10289 case INTEL_OUTPUT_EDP:
10290 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10291
10292 /* the same port mustn't appear more than once */
10293 if (used_ports & port_mask)
10294 return false;
10295
10296 used_ports |= port_mask;
10297 default:
10298 break;
10299 }
10300 }
10301
10302 return true;
10303}
10304
10305static struct intel_crtc_state *
10306intel_modeset_pipe_config(struct drm_crtc *crtc,
10307 struct drm_framebuffer *fb,
10308 struct drm_display_mode *mode)
10309{
10310 struct drm_device *dev = crtc->dev;
10311 struct intel_encoder *encoder;
10312 struct intel_crtc_state *pipe_config;
10313 int plane_bpp, ret = -EINVAL;
10314 bool retry = true;
10315
10316 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10317 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10318 return ERR_PTR(-EINVAL);
10319 }
10320
10321 if (!check_digital_port_conflicts(dev)) {
10322 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10323 return ERR_PTR(-EINVAL);
10324 }
10325
10326 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10327 if (!pipe_config)
10328 return ERR_PTR(-ENOMEM);
10329
10330 pipe_config->base.crtc = crtc;
10331 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10332 drm_mode_copy(&pipe_config->base.mode, mode);
10333
10334 pipe_config->cpu_transcoder =
10335 (enum transcoder) to_intel_crtc(crtc)->pipe;
10336 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10337
10338 /*
10339 * Sanitize sync polarity flags based on requested ones. If neither
10340 * positive or negative polarity is requested, treat this as meaning
10341 * negative polarity.
10342 */
10343 if (!(pipe_config->base.adjusted_mode.flags &
10344 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10345 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10346
10347 if (!(pipe_config->base.adjusted_mode.flags &
10348 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10349 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10350
10351 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10352 * plane pixel format and any sink constraints into account. Returns the
10353 * source plane bpp so that dithering can be selected on mismatches
10354 * after encoders and crtc also have had their say. */
10355 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10356 fb, pipe_config);
10357 if (plane_bpp < 0)
10358 goto fail;
10359
10360 /*
10361 * Determine the real pipe dimensions. Note that stereo modes can
10362 * increase the actual pipe size due to the frame doubling and
10363 * insertion of additional space for blanks between the frame. This
10364 * is stored in the crtc timings. We use the requested mode to do this
10365 * computation to clearly distinguish it from the adjusted mode, which
10366 * can be changed by the connectors in the below retry loop.
10367 */
10368 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10369 &pipe_config->pipe_src_w,
10370 &pipe_config->pipe_src_h);
10371
10372encoder_retry:
10373 /* Ensure the port clock defaults are reset when retrying. */
10374 pipe_config->port_clock = 0;
10375 pipe_config->pixel_multiplier = 1;
10376
10377 /* Fill in default crtc timings, allow encoders to overwrite them. */
10378 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10379 CRTC_STEREO_DOUBLE);
10380
10381 /* Pass our mode to the connectors and the CRTC to give them a chance to
10382 * adjust it according to limitations or connector properties, and also
10383 * a chance to reject the mode entirely.
10384 */
10385 for_each_intel_encoder(dev, encoder) {
10386
10387 if (&encoder->new_crtc->base != crtc)
10388 continue;
10389
10390 if (!(encoder->compute_config(encoder, pipe_config))) {
10391 DRM_DEBUG_KMS("Encoder config failure\n");
10392 goto fail;
10393 }
10394 }
10395
10396 /* Set default port clock if not overwritten by the encoder. Needs to be
10397 * done afterwards in case the encoder adjusts the mode. */
10398 if (!pipe_config->port_clock)
10399 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10400 * pipe_config->pixel_multiplier;
10401
10402 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10403 if (ret < 0) {
10404 DRM_DEBUG_KMS("CRTC fixup failed\n");
10405 goto fail;
10406 }
10407
10408 if (ret == RETRY) {
10409 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10410 ret = -EINVAL;
10411 goto fail;
10412 }
10413
10414 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10415 retry = false;
10416 goto encoder_retry;
10417 }
10418
10419 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10420 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10421 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10422
10423 return pipe_config;
10424fail:
10425 kfree(pipe_config);
10426 return ERR_PTR(ret);
10427}
10428
10429/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10430 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10431static void
10432intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10433 unsigned *prepare_pipes, unsigned *disable_pipes)
10434{
10435 struct intel_crtc *intel_crtc;
10436 struct drm_device *dev = crtc->dev;
10437 struct intel_encoder *encoder;
10438 struct intel_connector *connector;
10439 struct drm_crtc *tmp_crtc;
10440
10441 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10442
10443 /* Check which crtcs have changed outputs connected to them, these need
10444 * to be part of the prepare_pipes mask. We don't (yet) support global
10445 * modeset across multiple crtcs, so modeset_pipes will only have one
10446 * bit set at most. */
10447 for_each_intel_connector(dev, connector) {
10448 if (connector->base.encoder == &connector->new_encoder->base)
10449 continue;
10450
10451 if (connector->base.encoder) {
10452 tmp_crtc = connector->base.encoder->crtc;
10453
10454 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10455 }
10456
10457 if (connector->new_encoder)
10458 *prepare_pipes |=
10459 1 << connector->new_encoder->new_crtc->pipe;
10460 }
10461
10462 for_each_intel_encoder(dev, encoder) {
10463 if (encoder->base.crtc == &encoder->new_crtc->base)
10464 continue;
10465
10466 if (encoder->base.crtc) {
10467 tmp_crtc = encoder->base.crtc;
10468
10469 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10470 }
10471
10472 if (encoder->new_crtc)
10473 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10474 }
10475
10476 /* Check for pipes that will be enabled/disabled ... */
10477 for_each_intel_crtc(dev, intel_crtc) {
10478 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10479 continue;
10480
10481 if (!intel_crtc->new_enabled)
10482 *disable_pipes |= 1 << intel_crtc->pipe;
10483 else
10484 *prepare_pipes |= 1 << intel_crtc->pipe;
10485 }
10486
10487
10488 /* set_mode is also used to update properties on life display pipes. */
10489 intel_crtc = to_intel_crtc(crtc);
10490 if (intel_crtc->new_enabled)
10491 *prepare_pipes |= 1 << intel_crtc->pipe;
10492
10493 /*
10494 * For simplicity do a full modeset on any pipe where the output routing
10495 * changed. We could be more clever, but that would require us to be
10496 * more careful with calling the relevant encoder->mode_set functions.
10497 */
10498 if (*prepare_pipes)
10499 *modeset_pipes = *prepare_pipes;
10500
10501 /* ... and mask these out. */
10502 *modeset_pipes &= ~(*disable_pipes);
10503 *prepare_pipes &= ~(*disable_pipes);
10504
10505 /*
10506 * HACK: We don't (yet) fully support global modesets. intel_set_config
10507 * obies this rule, but the modeset restore mode of
10508 * intel_modeset_setup_hw_state does not.
10509 */
10510 *modeset_pipes &= 1 << intel_crtc->pipe;
10511 *prepare_pipes &= 1 << intel_crtc->pipe;
10512
10513 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10514 *modeset_pipes, *prepare_pipes, *disable_pipes);
10515}
10516
10517static bool intel_crtc_in_use(struct drm_crtc *crtc)
10518{
10519 struct drm_encoder *encoder;
10520 struct drm_device *dev = crtc->dev;
10521
10522 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10523 if (encoder->crtc == crtc)
10524 return true;
10525
10526 return false;
10527}
10528
10529static void
10530intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10531{
10532 struct drm_i915_private *dev_priv = dev->dev_private;
10533 struct intel_encoder *intel_encoder;
10534 struct intel_crtc *intel_crtc;
10535 struct drm_connector *connector;
10536
10537 intel_shared_dpll_commit(dev_priv);
10538
10539 for_each_intel_encoder(dev, intel_encoder) {
10540 if (!intel_encoder->base.crtc)
10541 continue;
10542
10543 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10544
10545 if (prepare_pipes & (1 << intel_crtc->pipe))
10546 intel_encoder->connectors_active = false;
10547 }
10548
10549 intel_modeset_commit_output_state(dev);
10550
10551 /* Double check state. */
10552 for_each_intel_crtc(dev, intel_crtc) {
10553 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10554 WARN_ON(intel_crtc->new_config &&
10555 intel_crtc->new_config != intel_crtc->config);
10556 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10557 }
10558
10559 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10560 if (!connector->encoder || !connector->encoder->crtc)
10561 continue;
10562
10563 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10564
10565 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10566 struct drm_property *dpms_property =
10567 dev->mode_config.dpms_property;
10568
10569 connector->dpms = DRM_MODE_DPMS_ON;
10570 drm_object_property_set_value(&connector->base,
10571 dpms_property,
10572 DRM_MODE_DPMS_ON);
10573
10574 intel_encoder = to_intel_encoder(connector->encoder);
10575 intel_encoder->connectors_active = true;
10576 }
10577 }
10578
10579}
10580
10581static bool intel_fuzzy_clock_check(int clock1, int clock2)
10582{
10583 int diff;
10584
10585 if (clock1 == clock2)
10586 return true;
10587
10588 if (!clock1 || !clock2)
10589 return false;
10590
10591 diff = abs(clock1 - clock2);
10592
10593 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10594 return true;
10595
10596 return false;
10597}
10598
10599#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10600 list_for_each_entry((intel_crtc), \
10601 &(dev)->mode_config.crtc_list, \
10602 base.head) \
10603 if (mask & (1 <<(intel_crtc)->pipe))
10604
10605static bool
10606intel_pipe_config_compare(struct drm_device *dev,
10607 struct intel_crtc_state *current_config,
10608 struct intel_crtc_state *pipe_config)
10609{
10610#define PIPE_CONF_CHECK_X(name) \
10611 if (current_config->name != pipe_config->name) { \
10612 DRM_ERROR("mismatch in " #name " " \
10613 "(expected 0x%08x, found 0x%08x)\n", \
10614 current_config->name, \
10615 pipe_config->name); \
10616 return false; \
10617 }
10618
10619#define PIPE_CONF_CHECK_I(name) \
10620 if (current_config->name != pipe_config->name) { \
10621 DRM_ERROR("mismatch in " #name " " \
10622 "(expected %i, found %i)\n", \
10623 current_config->name, \
10624 pipe_config->name); \
10625 return false; \
10626 }
10627
10628/* This is required for BDW+ where there is only one set of registers for
10629 * switching between high and low RR.
10630 * This macro can be used whenever a comparison has to be made between one
10631 * hw state and multiple sw state variables.
10632 */
10633#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10634 if ((current_config->name != pipe_config->name) && \
10635 (current_config->alt_name != pipe_config->name)) { \
10636 DRM_ERROR("mismatch in " #name " " \
10637 "(expected %i or %i, found %i)\n", \
10638 current_config->name, \
10639 current_config->alt_name, \
10640 pipe_config->name); \
10641 return false; \
10642 }
10643
10644#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10645 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10646 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10647 "(expected %i, found %i)\n", \
10648 current_config->name & (mask), \
10649 pipe_config->name & (mask)); \
10650 return false; \
10651 }
10652
10653#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10654 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10655 DRM_ERROR("mismatch in " #name " " \
10656 "(expected %i, found %i)\n", \
10657 current_config->name, \
10658 pipe_config->name); \
10659 return false; \
10660 }
10661
10662#define PIPE_CONF_QUIRK(quirk) \
10663 ((current_config->quirks | pipe_config->quirks) & (quirk))
10664
10665 PIPE_CONF_CHECK_I(cpu_transcoder);
10666
10667 PIPE_CONF_CHECK_I(has_pch_encoder);
10668 PIPE_CONF_CHECK_I(fdi_lanes);
10669 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10670 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10671 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10672 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10673 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10674
10675 PIPE_CONF_CHECK_I(has_dp_encoder);
10676
10677 if (INTEL_INFO(dev)->gen < 8) {
10678 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10679 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10680 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10681 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10682 PIPE_CONF_CHECK_I(dp_m_n.tu);
10683
10684 if (current_config->has_drrs) {
10685 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10686 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10687 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10688 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10689 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10690 }
10691 } else {
10692 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10693 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10694 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10695 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10696 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10697 }
10698
10699 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10700 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10701 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10702 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10703 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10704 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10705
10706 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10707 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10708 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10709 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10710 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10711 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10712
10713 PIPE_CONF_CHECK_I(pixel_multiplier);
10714 PIPE_CONF_CHECK_I(has_hdmi_sink);
10715 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10716 IS_VALLEYVIEW(dev))
10717 PIPE_CONF_CHECK_I(limited_color_range);
10718 PIPE_CONF_CHECK_I(has_infoframe);
10719
10720 PIPE_CONF_CHECK_I(has_audio);
10721
10722 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10723 DRM_MODE_FLAG_INTERLACE);
10724
10725 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10726 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10727 DRM_MODE_FLAG_PHSYNC);
10728 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10729 DRM_MODE_FLAG_NHSYNC);
10730 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10731 DRM_MODE_FLAG_PVSYNC);
10732 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10733 DRM_MODE_FLAG_NVSYNC);
10734 }
10735
10736 PIPE_CONF_CHECK_I(pipe_src_w);
10737 PIPE_CONF_CHECK_I(pipe_src_h);
10738
10739 /*
10740 * FIXME: BIOS likes to set up a cloned config with lvds+external
10741 * screen. Since we don't yet re-compute the pipe config when moving
10742 * just the lvds port away to another pipe the sw tracking won't match.
10743 *
10744 * Proper atomic modesets with recomputed global state will fix this.
10745 * Until then just don't check gmch state for inherited modes.
10746 */
10747 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10748 PIPE_CONF_CHECK_I(gmch_pfit.control);
10749 /* pfit ratios are autocomputed by the hw on gen4+ */
10750 if (INTEL_INFO(dev)->gen < 4)
10751 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10752 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10753 }
10754
10755 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10756 if (current_config->pch_pfit.enabled) {
10757 PIPE_CONF_CHECK_I(pch_pfit.pos);
10758 PIPE_CONF_CHECK_I(pch_pfit.size);
10759 }
10760
10761 /* BDW+ don't expose a synchronous way to read the state */
10762 if (IS_HASWELL(dev))
10763 PIPE_CONF_CHECK_I(ips_enabled);
10764
10765 PIPE_CONF_CHECK_I(double_wide);
10766
10767 PIPE_CONF_CHECK_X(ddi_pll_sel);
10768
10769 PIPE_CONF_CHECK_I(shared_dpll);
10770 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10771 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10772 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10773 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10774 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10775 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10776 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10777 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10778
10779 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10780 PIPE_CONF_CHECK_I(pipe_bpp);
10781
10782 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10783 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10784
10785#undef PIPE_CONF_CHECK_X
10786#undef PIPE_CONF_CHECK_I
10787#undef PIPE_CONF_CHECK_I_ALT
10788#undef PIPE_CONF_CHECK_FLAGS
10789#undef PIPE_CONF_CHECK_CLOCK_FUZZY
10790#undef PIPE_CONF_QUIRK
10791
10792 return true;
10793}
10794
10795static void check_wm_state(struct drm_device *dev)
10796{
10797 struct drm_i915_private *dev_priv = dev->dev_private;
10798 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10799 struct intel_crtc *intel_crtc;
10800 int plane;
10801
10802 if (INTEL_INFO(dev)->gen < 9)
10803 return;
10804
10805 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10806 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10807
10808 for_each_intel_crtc(dev, intel_crtc) {
10809 struct skl_ddb_entry *hw_entry, *sw_entry;
10810 const enum pipe pipe = intel_crtc->pipe;
10811
10812 if (!intel_crtc->active)
10813 continue;
10814
10815 /* planes */
10816 for_each_plane(dev_priv, pipe, plane) {
10817 hw_entry = &hw_ddb.plane[pipe][plane];
10818 sw_entry = &sw_ddb->plane[pipe][plane];
10819
10820 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10821 continue;
10822
10823 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10824 "(expected (%u,%u), found (%u,%u))\n",
10825 pipe_name(pipe), plane + 1,
10826 sw_entry->start, sw_entry->end,
10827 hw_entry->start, hw_entry->end);
10828 }
10829
10830 /* cursor */
10831 hw_entry = &hw_ddb.cursor[pipe];
10832 sw_entry = &sw_ddb->cursor[pipe];
10833
10834 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10835 continue;
10836
10837 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10838 "(expected (%u,%u), found (%u,%u))\n",
10839 pipe_name(pipe),
10840 sw_entry->start, sw_entry->end,
10841 hw_entry->start, hw_entry->end);
10842 }
10843}
10844
10845static void
10846check_connector_state(struct drm_device *dev)
10847{
10848 struct intel_connector *connector;
10849
10850 for_each_intel_connector(dev, connector) {
10851 /* This also checks the encoder/connector hw state with the
10852 * ->get_hw_state callbacks. */
10853 intel_connector_check_state(connector);
10854
10855 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10856 "connector's staged encoder doesn't match current encoder\n");
10857 }
10858}
10859
10860static void
10861check_encoder_state(struct drm_device *dev)
10862{
10863 struct intel_encoder *encoder;
10864 struct intel_connector *connector;
10865
10866 for_each_intel_encoder(dev, encoder) {
10867 bool enabled = false;
10868 bool active = false;
10869 enum pipe pipe, tracked_pipe;
10870
10871 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10872 encoder->base.base.id,
10873 encoder->base.name);
10874
10875 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10876 "encoder's stage crtc doesn't match current crtc\n");
10877 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10878 "encoder's active_connectors set, but no crtc\n");
10879
10880 for_each_intel_connector(dev, connector) {
10881 if (connector->base.encoder != &encoder->base)
10882 continue;
10883 enabled = true;
10884 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10885 active = true;
10886 }
10887 /*
10888 * for MST connectors if we unplug the connector is gone
10889 * away but the encoder is still connected to a crtc
10890 * until a modeset happens in response to the hotplug.
10891 */
10892 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10893 continue;
10894
10895 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10896 "encoder's enabled state mismatch "
10897 "(expected %i, found %i)\n",
10898 !!encoder->base.crtc, enabled);
10899 I915_STATE_WARN(active && !encoder->base.crtc,
10900 "active encoder with no crtc\n");
10901
10902 I915_STATE_WARN(encoder->connectors_active != active,
10903 "encoder's computed active state doesn't match tracked active state "
10904 "(expected %i, found %i)\n", active, encoder->connectors_active);
10905
10906 active = encoder->get_hw_state(encoder, &pipe);
10907 I915_STATE_WARN(active != encoder->connectors_active,
10908 "encoder's hw state doesn't match sw tracking "
10909 "(expected %i, found %i)\n",
10910 encoder->connectors_active, active);
10911
10912 if (!encoder->base.crtc)
10913 continue;
10914
10915 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10916 I915_STATE_WARN(active && pipe != tracked_pipe,
10917 "active encoder's pipe doesn't match"
10918 "(expected %i, found %i)\n",
10919 tracked_pipe, pipe);
10920
10921 }
10922}
10923
10924static void
10925check_crtc_state(struct drm_device *dev)
10926{
10927 struct drm_i915_private *dev_priv = dev->dev_private;
10928 struct intel_crtc *crtc;
10929 struct intel_encoder *encoder;
10930 struct intel_crtc_state pipe_config;
10931
10932 for_each_intel_crtc(dev, crtc) {
10933 bool enabled = false;
10934 bool active = false;
10935
10936 memset(&pipe_config, 0, sizeof(pipe_config));
10937
10938 DRM_DEBUG_KMS("[CRTC:%d]\n",
10939 crtc->base.base.id);
10940
10941 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10942 "active crtc, but not enabled in sw tracking\n");
10943
10944 for_each_intel_encoder(dev, encoder) {
10945 if (encoder->base.crtc != &crtc->base)
10946 continue;
10947 enabled = true;
10948 if (encoder->connectors_active)
10949 active = true;
10950 }
10951
10952 I915_STATE_WARN(active != crtc->active,
10953 "crtc's computed active state doesn't match tracked active state "
10954 "(expected %i, found %i)\n", active, crtc->active);
10955 I915_STATE_WARN(enabled != crtc->base.state->enable,
10956 "crtc's computed enabled state doesn't match tracked enabled state "
10957 "(expected %i, found %i)\n", enabled,
10958 crtc->base.state->enable);
10959
10960 active = dev_priv->display.get_pipe_config(crtc,
10961 &pipe_config);
10962
10963 /* hw state is inconsistent with the pipe quirk */
10964 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10965 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10966 active = crtc->active;
10967
10968 for_each_intel_encoder(dev, encoder) {
10969 enum pipe pipe;
10970 if (encoder->base.crtc != &crtc->base)
10971 continue;
10972 if (encoder->get_hw_state(encoder, &pipe))
10973 encoder->get_config(encoder, &pipe_config);
10974 }
10975
10976 I915_STATE_WARN(crtc->active != active,
10977 "crtc active state doesn't match with hw state "
10978 "(expected %i, found %i)\n", crtc->active, active);
10979
10980 if (active &&
10981 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10982 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10983 intel_dump_pipe_config(crtc, &pipe_config,
10984 "[hw state]");
10985 intel_dump_pipe_config(crtc, crtc->config,
10986 "[sw state]");
10987 }
10988 }
10989}
10990
10991static void
10992check_shared_dpll_state(struct drm_device *dev)
10993{
10994 struct drm_i915_private *dev_priv = dev->dev_private;
10995 struct intel_crtc *crtc;
10996 struct intel_dpll_hw_state dpll_hw_state;
10997 int i;
10998
10999 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11000 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11001 int enabled_crtcs = 0, active_crtcs = 0;
11002 bool active;
11003
11004 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11005
11006 DRM_DEBUG_KMS("%s\n", pll->name);
11007
11008 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11009
11010 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11011 "more active pll users than references: %i vs %i\n",
11012 pll->active, hweight32(pll->config.crtc_mask));
11013 I915_STATE_WARN(pll->active && !pll->on,
11014 "pll in active use but not on in sw tracking\n");
11015 I915_STATE_WARN(pll->on && !pll->active,
11016 "pll in on but not on in use in sw tracking\n");
11017 I915_STATE_WARN(pll->on != active,
11018 "pll on state mismatch (expected %i, found %i)\n",
11019 pll->on, active);
11020
11021 for_each_intel_crtc(dev, crtc) {
11022 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11023 enabled_crtcs++;
11024 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11025 active_crtcs++;
11026 }
11027 I915_STATE_WARN(pll->active != active_crtcs,
11028 "pll active crtcs mismatch (expected %i, found %i)\n",
11029 pll->active, active_crtcs);
11030 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11031 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11032 hweight32(pll->config.crtc_mask), enabled_crtcs);
11033
11034 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11035 sizeof(dpll_hw_state)),
11036 "pll hw state mismatch\n");
11037 }
11038}
11039
11040void
11041intel_modeset_check_state(struct drm_device *dev)
11042{
11043 check_wm_state(dev);
11044 check_connector_state(dev);
11045 check_encoder_state(dev);
11046 check_crtc_state(dev);
11047 check_shared_dpll_state(dev);
11048}
11049
11050void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11051 int dotclock)
11052{
11053 /*
11054 * FDI already provided one idea for the dotclock.
11055 * Yell if the encoder disagrees.
11056 */
11057 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11058 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11059 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11060}
11061
11062static void update_scanline_offset(struct intel_crtc *crtc)
11063{
11064 struct drm_device *dev = crtc->base.dev;
11065
11066 /*
11067 * The scanline counter increments at the leading edge of hsync.
11068 *
11069 * On most platforms it starts counting from vtotal-1 on the
11070 * first active line. That means the scanline counter value is
11071 * always one less than what we would expect. Ie. just after
11072 * start of vblank, which also occurs at start of hsync (on the
11073 * last active line), the scanline counter will read vblank_start-1.
11074 *
11075 * On gen2 the scanline counter starts counting from 1 instead
11076 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11077 * to keep the value positive), instead of adding one.
11078 *
11079 * On HSW+ the behaviour of the scanline counter depends on the output
11080 * type. For DP ports it behaves like most other platforms, but on HDMI
11081 * there's an extra 1 line difference. So we need to add two instead of
11082 * one to the value.
11083 */
11084 if (IS_GEN2(dev)) {
11085 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11086 int vtotal;
11087
11088 vtotal = mode->crtc_vtotal;
11089 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11090 vtotal /= 2;
11091
11092 crtc->scanline_offset = vtotal - 1;
11093 } else if (HAS_DDI(dev) &&
11094 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11095 crtc->scanline_offset = 2;
11096 } else
11097 crtc->scanline_offset = 1;
11098}
11099
11100static struct intel_crtc_state *
11101intel_modeset_compute_config(struct drm_crtc *crtc,
11102 struct drm_display_mode *mode,
11103 struct drm_framebuffer *fb,
11104 unsigned *modeset_pipes,
11105 unsigned *prepare_pipes,
11106 unsigned *disable_pipes)
11107{
11108 struct intel_crtc_state *pipe_config = NULL;
11109
11110 intel_modeset_affected_pipes(crtc, modeset_pipes,
11111 prepare_pipes, disable_pipes);
11112
11113 if ((*modeset_pipes) == 0)
11114 goto out;
11115
11116 /*
11117 * Note this needs changes when we start tracking multiple modes
11118 * and crtcs. At that point we'll need to compute the whole config
11119 * (i.e. one pipe_config for each crtc) rather than just the one
11120 * for this crtc.
11121 */
11122 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11123 if (IS_ERR(pipe_config)) {
11124 goto out;
11125 }
11126 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11127 "[modeset]");
11128
11129out:
11130 return pipe_config;
11131}
11132
11133static int __intel_set_mode_setup_plls(struct drm_device *dev,
11134 unsigned modeset_pipes,
11135 unsigned disable_pipes)
11136{
11137 struct drm_i915_private *dev_priv = to_i915(dev);
11138 unsigned clear_pipes = modeset_pipes | disable_pipes;
11139 struct intel_crtc *intel_crtc;
11140 int ret = 0;
11141
11142 if (!dev_priv->display.crtc_compute_clock)
11143 return 0;
11144
11145 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11146 if (ret)
11147 goto done;
11148
11149 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11150 struct intel_crtc_state *state = intel_crtc->new_config;
11151 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11152 state);
11153 if (ret) {
11154 intel_shared_dpll_abort_config(dev_priv);
11155 goto done;
11156 }
11157 }
11158
11159done:
11160 return ret;
11161}
11162
11163static int __intel_set_mode(struct drm_crtc *crtc,
11164 struct drm_display_mode *mode,
11165 int x, int y, struct drm_framebuffer *fb,
11166 struct intel_crtc_state *pipe_config,
11167 unsigned modeset_pipes,
11168 unsigned prepare_pipes,
11169 unsigned disable_pipes)
11170{
11171 struct drm_device *dev = crtc->dev;
11172 struct drm_i915_private *dev_priv = dev->dev_private;
11173 struct drm_display_mode *saved_mode;
11174 struct intel_crtc *intel_crtc;
11175 int ret = 0;
11176
11177 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11178 if (!saved_mode)
11179 return -ENOMEM;
11180
11181 *saved_mode = crtc->mode;
11182
11183 if (modeset_pipes)
11184 to_intel_crtc(crtc)->new_config = pipe_config;
11185
11186 /*
11187 * See if the config requires any additional preparation, e.g.
11188 * to adjust global state with pipes off. We need to do this
11189 * here so we can get the modeset_pipe updated config for the new
11190 * mode set on this crtc. For other crtcs we need to use the
11191 * adjusted_mode bits in the crtc directly.
11192 */
11193 if (IS_VALLEYVIEW(dev)) {
11194 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11195
11196 /* may have added more to prepare_pipes than we should */
11197 prepare_pipes &= ~disable_pipes;
11198 }
11199
11200 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11201 if (ret)
11202 goto done;
11203
11204 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11205 intel_crtc_disable(&intel_crtc->base);
11206
11207 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11208 if (intel_crtc->base.state->enable)
11209 dev_priv->display.crtc_disable(&intel_crtc->base);
11210 }
11211
11212 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11213 * to set it here already despite that we pass it down the callchain.
11214 *
11215 * Note we'll need to fix this up when we start tracking multiple
11216 * pipes; here we assume a single modeset_pipe and only track the
11217 * single crtc and mode.
11218 */
11219 if (modeset_pipes) {
11220 crtc->mode = *mode;
11221 /* mode_set/enable/disable functions rely on a correct pipe
11222 * config. */
11223 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11224
11225 /*
11226 * Calculate and store various constants which
11227 * are later needed by vblank and swap-completion
11228 * timestamping. They are derived from true hwmode.
11229 */
11230 drm_calc_timestamping_constants(crtc,
11231 &pipe_config->base.adjusted_mode);
11232 }
11233
11234 /* Only after disabling all output pipelines that will be changed can we
11235 * update the the output configuration. */
11236 intel_modeset_update_state(dev, prepare_pipes);
11237
11238 modeset_update_crtc_power_domains(dev);
11239
11240 /* Set up the DPLL and any encoders state that needs to adjust or depend
11241 * on the DPLL.
11242 */
11243 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11244 struct drm_plane *primary = intel_crtc->base.primary;
11245 int vdisplay, hdisplay;
11246
11247 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11248 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11249 fb, 0, 0,
11250 hdisplay, vdisplay,
11251 x << 16, y << 16,
11252 hdisplay << 16, vdisplay << 16);
11253 }
11254
11255 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11256 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11257 update_scanline_offset(intel_crtc);
11258
11259 dev_priv->display.crtc_enable(&intel_crtc->base);
11260 }
11261
11262 /* FIXME: add subpixel order */
11263done:
11264 if (ret && crtc->state->enable)
11265 crtc->mode = *saved_mode;
11266
11267 kfree(saved_mode);
11268 return ret;
11269}
11270
11271static int intel_set_mode_pipes(struct drm_crtc *crtc,
11272 struct drm_display_mode *mode,
11273 int x, int y, struct drm_framebuffer *fb,
11274 struct intel_crtc_state *pipe_config,
11275 unsigned modeset_pipes,
11276 unsigned prepare_pipes,
11277 unsigned disable_pipes)
11278{
11279 int ret;
11280
11281 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11282 prepare_pipes, disable_pipes);
11283
11284 if (ret == 0)
11285 intel_modeset_check_state(crtc->dev);
11286
11287 return ret;
11288}
11289
11290static int intel_set_mode(struct drm_crtc *crtc,
11291 struct drm_display_mode *mode,
11292 int x, int y, struct drm_framebuffer *fb)
11293{
11294 struct intel_crtc_state *pipe_config;
11295 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11296
11297 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11298 &modeset_pipes,
11299 &prepare_pipes,
11300 &disable_pipes);
11301
11302 if (IS_ERR(pipe_config))
11303 return PTR_ERR(pipe_config);
11304
11305 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11306 modeset_pipes, prepare_pipes,
11307 disable_pipes);
11308}
11309
11310void intel_crtc_restore_mode(struct drm_crtc *crtc)
11311{
11312 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11313}
11314
11315#undef for_each_intel_crtc_masked
11316
11317static void intel_set_config_free(struct intel_set_config *config)
11318{
11319 if (!config)
11320 return;
11321
11322 kfree(config->save_connector_encoders);
11323 kfree(config->save_encoder_crtcs);
11324 kfree(config->save_crtc_enabled);
11325 kfree(config);
11326}
11327
11328static int intel_set_config_save_state(struct drm_device *dev,
11329 struct intel_set_config *config)
11330{
11331 struct drm_crtc *crtc;
11332 struct drm_encoder *encoder;
11333 struct drm_connector *connector;
11334 int count;
11335
11336 config->save_crtc_enabled =
11337 kcalloc(dev->mode_config.num_crtc,
11338 sizeof(bool), GFP_KERNEL);
11339 if (!config->save_crtc_enabled)
11340 return -ENOMEM;
11341
11342 config->save_encoder_crtcs =
11343 kcalloc(dev->mode_config.num_encoder,
11344 sizeof(struct drm_crtc *), GFP_KERNEL);
11345 if (!config->save_encoder_crtcs)
11346 return -ENOMEM;
11347
11348 config->save_connector_encoders =
11349 kcalloc(dev->mode_config.num_connector,
11350 sizeof(struct drm_encoder *), GFP_KERNEL);
11351 if (!config->save_connector_encoders)
11352 return -ENOMEM;
11353
11354 /* Copy data. Note that driver private data is not affected.
11355 * Should anything bad happen only the expected state is
11356 * restored, not the drivers personal bookkeeping.
11357 */
11358 count = 0;
11359 for_each_crtc(dev, crtc) {
11360 config->save_crtc_enabled[count++] = crtc->state->enable;
11361 }
11362
11363 count = 0;
11364 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11365 config->save_encoder_crtcs[count++] = encoder->crtc;
11366 }
11367
11368 count = 0;
11369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11370 config->save_connector_encoders[count++] = connector->encoder;
11371 }
11372
11373 return 0;
11374}
11375
11376static void intel_set_config_restore_state(struct drm_device *dev,
11377 struct intel_set_config *config)
11378{
11379 struct intel_crtc *crtc;
11380 struct intel_encoder *encoder;
11381 struct intel_connector *connector;
11382 int count;
11383
11384 count = 0;
11385 for_each_intel_crtc(dev, crtc) {
11386 crtc->new_enabled = config->save_crtc_enabled[count++];
11387
11388 if (crtc->new_enabled)
11389 crtc->new_config = crtc->config;
11390 else
11391 crtc->new_config = NULL;
11392 }
11393
11394 count = 0;
11395 for_each_intel_encoder(dev, encoder) {
11396 encoder->new_crtc =
11397 to_intel_crtc(config->save_encoder_crtcs[count++]);
11398 }
11399
11400 count = 0;
11401 for_each_intel_connector(dev, connector) {
11402 connector->new_encoder =
11403 to_intel_encoder(config->save_connector_encoders[count++]);
11404 }
11405}
11406
11407static bool
11408is_crtc_connector_off(struct drm_mode_set *set)
11409{
11410 int i;
11411
11412 if (set->num_connectors == 0)
11413 return false;
11414
11415 if (WARN_ON(set->connectors == NULL))
11416 return false;
11417
11418 for (i = 0; i < set->num_connectors; i++)
11419 if (set->connectors[i]->encoder &&
11420 set->connectors[i]->encoder->crtc == set->crtc &&
11421 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11422 return true;
11423
11424 return false;
11425}
11426
11427static void
11428intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11429 struct intel_set_config *config)
11430{
11431
11432 /* We should be able to check here if the fb has the same properties
11433 * and then just flip_or_move it */
11434 if (is_crtc_connector_off(set)) {
11435 config->mode_changed = true;
11436 } else if (set->crtc->primary->fb != set->fb) {
11437 /*
11438 * If we have no fb, we can only flip as long as the crtc is
11439 * active, otherwise we need a full mode set. The crtc may
11440 * be active if we've only disabled the primary plane, or
11441 * in fastboot situations.
11442 */
11443 if (set->crtc->primary->fb == NULL) {
11444 struct intel_crtc *intel_crtc =
11445 to_intel_crtc(set->crtc);
11446
11447 if (intel_crtc->active) {
11448 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11449 config->fb_changed = true;
11450 } else {
11451 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11452 config->mode_changed = true;
11453 }
11454 } else if (set->fb == NULL) {
11455 config->mode_changed = true;
11456 } else if (set->fb->pixel_format !=
11457 set->crtc->primary->fb->pixel_format) {
11458 config->mode_changed = true;
11459 } else {
11460 config->fb_changed = true;
11461 }
11462 }
11463
11464 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11465 config->fb_changed = true;
11466
11467 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11468 DRM_DEBUG_KMS("modes are different, full mode set\n");
11469 drm_mode_debug_printmodeline(&set->crtc->mode);
11470 drm_mode_debug_printmodeline(set->mode);
11471 config->mode_changed = true;
11472 }
11473
11474 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11475 set->crtc->base.id, config->mode_changed, config->fb_changed);
11476}
11477
11478static int
11479intel_modeset_stage_output_state(struct drm_device *dev,
11480 struct drm_mode_set *set,
11481 struct intel_set_config *config)
11482{
11483 struct intel_connector *connector;
11484 struct intel_encoder *encoder;
11485 struct intel_crtc *crtc;
11486 int ro;
11487
11488 /* The upper layers ensure that we either disable a crtc or have a list
11489 * of connectors. For paranoia, double-check this. */
11490 WARN_ON(!set->fb && (set->num_connectors != 0));
11491 WARN_ON(set->fb && (set->num_connectors == 0));
11492
11493 for_each_intel_connector(dev, connector) {
11494 /* Otherwise traverse passed in connector list and get encoders
11495 * for them. */
11496 for (ro = 0; ro < set->num_connectors; ro++) {
11497 if (set->connectors[ro] == &connector->base) {
11498 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11499 break;
11500 }
11501 }
11502
11503 /* If we disable the crtc, disable all its connectors. Also, if
11504 * the connector is on the changing crtc but not on the new
11505 * connector list, disable it. */
11506 if ((!set->fb || ro == set->num_connectors) &&
11507 connector->base.encoder &&
11508 connector->base.encoder->crtc == set->crtc) {
11509 connector->new_encoder = NULL;
11510
11511 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11512 connector->base.base.id,
11513 connector->base.name);
11514 }
11515
11516
11517 if (&connector->new_encoder->base != connector->base.encoder) {
11518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11519 connector->base.base.id,
11520 connector->base.name);
11521 config->mode_changed = true;
11522 }
11523 }
11524 /* connector->new_encoder is now updated for all connectors. */
11525
11526 /* Update crtc of enabled connectors. */
11527 for_each_intel_connector(dev, connector) {
11528 struct drm_crtc *new_crtc;
11529
11530 if (!connector->new_encoder)
11531 continue;
11532
11533 new_crtc = connector->new_encoder->base.crtc;
11534
11535 for (ro = 0; ro < set->num_connectors; ro++) {
11536 if (set->connectors[ro] == &connector->base)
11537 new_crtc = set->crtc;
11538 }
11539
11540 /* Make sure the new CRTC will work with the encoder */
11541 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11542 new_crtc)) {
11543 return -EINVAL;
11544 }
11545 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11546
11547 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11548 connector->base.base.id,
11549 connector->base.name,
11550 new_crtc->base.id);
11551 }
11552
11553 /* Check for any encoders that needs to be disabled. */
11554 for_each_intel_encoder(dev, encoder) {
11555 int num_connectors = 0;
11556 for_each_intel_connector(dev, connector) {
11557 if (connector->new_encoder == encoder) {
11558 WARN_ON(!connector->new_encoder->new_crtc);
11559 num_connectors++;
11560 }
11561 }
11562
11563 if (num_connectors == 0)
11564 encoder->new_crtc = NULL;
11565 else if (num_connectors > 1)
11566 return -EINVAL;
11567
11568 /* Only now check for crtc changes so we don't miss encoders
11569 * that will be disabled. */
11570 if (&encoder->new_crtc->base != encoder->base.crtc) {
11571 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11572 encoder->base.base.id,
11573 encoder->base.name);
11574 config->mode_changed = true;
11575 }
11576 }
11577 /* Now we've also updated encoder->new_crtc for all encoders. */
11578 for_each_intel_connector(dev, connector) {
11579 if (connector->new_encoder)
11580 if (connector->new_encoder != connector->encoder)
11581 connector->encoder = connector->new_encoder;
11582 }
11583 for_each_intel_crtc(dev, crtc) {
11584 crtc->new_enabled = false;
11585
11586 for_each_intel_encoder(dev, encoder) {
11587 if (encoder->new_crtc == crtc) {
11588 crtc->new_enabled = true;
11589 break;
11590 }
11591 }
11592
11593 if (crtc->new_enabled != crtc->base.state->enable) {
11594 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11595 crtc->base.base.id,
11596 crtc->new_enabled ? "en" : "dis");
11597 config->mode_changed = true;
11598 }
11599
11600 if (crtc->new_enabled)
11601 crtc->new_config = crtc->config;
11602 else
11603 crtc->new_config = NULL;
11604 }
11605
11606 return 0;
11607}
11608
11609static void disable_crtc_nofb(struct intel_crtc *crtc)
11610{
11611 struct drm_device *dev = crtc->base.dev;
11612 struct intel_encoder *encoder;
11613 struct intel_connector *connector;
11614
11615 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11616 pipe_name(crtc->pipe));
11617
11618 for_each_intel_connector(dev, connector) {
11619 if (connector->new_encoder &&
11620 connector->new_encoder->new_crtc == crtc)
11621 connector->new_encoder = NULL;
11622 }
11623
11624 for_each_intel_encoder(dev, encoder) {
11625 if (encoder->new_crtc == crtc)
11626 encoder->new_crtc = NULL;
11627 }
11628
11629 crtc->new_enabled = false;
11630 crtc->new_config = NULL;
11631}
11632
11633static int intel_crtc_set_config(struct drm_mode_set *set)
11634{
11635 struct drm_device *dev;
11636 struct drm_mode_set save_set;
11637 struct intel_set_config *config;
11638 struct intel_crtc_state *pipe_config;
11639 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11640 int ret;
11641
11642 BUG_ON(!set);
11643 BUG_ON(!set->crtc);
11644 BUG_ON(!set->crtc->helper_private);
11645
11646 /* Enforce sane interface api - has been abused by the fb helper. */
11647 BUG_ON(!set->mode && set->fb);
11648 BUG_ON(set->fb && set->num_connectors == 0);
11649
11650 if (set->fb) {
11651 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11652 set->crtc->base.id, set->fb->base.id,
11653 (int)set->num_connectors, set->x, set->y);
11654 } else {
11655 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11656 }
11657
11658 dev = set->crtc->dev;
11659
11660 ret = -ENOMEM;
11661 config = kzalloc(sizeof(*config), GFP_KERNEL);
11662 if (!config)
11663 goto out_config;
11664
11665 ret = intel_set_config_save_state(dev, config);
11666 if (ret)
11667 goto out_config;
11668
11669 save_set.crtc = set->crtc;
11670 save_set.mode = &set->crtc->mode;
11671 save_set.x = set->crtc->x;
11672 save_set.y = set->crtc->y;
11673 save_set.fb = set->crtc->primary->fb;
11674
11675 /* Compute whether we need a full modeset, only an fb base update or no
11676 * change at all. In the future we might also check whether only the
11677 * mode changed, e.g. for LVDS where we only change the panel fitter in
11678 * such cases. */
11679 intel_set_config_compute_mode_changes(set, config);
11680
11681 ret = intel_modeset_stage_output_state(dev, set, config);
11682 if (ret)
11683 goto fail;
11684
11685 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11686 set->fb,
11687 &modeset_pipes,
11688 &prepare_pipes,
11689 &disable_pipes);
11690 if (IS_ERR(pipe_config)) {
11691 ret = PTR_ERR(pipe_config);
11692 goto fail;
11693 } else if (pipe_config) {
11694 if (pipe_config->has_audio !=
11695 to_intel_crtc(set->crtc)->config->has_audio)
11696 config->mode_changed = true;
11697
11698 /*
11699 * Note we have an issue here with infoframes: current code
11700 * only updates them on the full mode set path per hw
11701 * requirements. So here we should be checking for any
11702 * required changes and forcing a mode set.
11703 */
11704 }
11705
11706 /* set_mode will free it in the mode_changed case */
11707 if (!config->mode_changed)
11708 kfree(pipe_config);
11709
11710 intel_update_pipe_size(to_intel_crtc(set->crtc));
11711
11712 if (config->mode_changed) {
11713 ret = intel_set_mode_pipes(set->crtc, set->mode,
11714 set->x, set->y, set->fb, pipe_config,
11715 modeset_pipes, prepare_pipes,
11716 disable_pipes);
11717 } else if (config->fb_changed) {
11718 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11719 struct drm_plane *primary = set->crtc->primary;
11720 int vdisplay, hdisplay;
11721
11722 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11723 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11724 0, 0, hdisplay, vdisplay,
11725 set->x << 16, set->y << 16,
11726 hdisplay << 16, vdisplay << 16);
11727
11728 /*
11729 * We need to make sure the primary plane is re-enabled if it
11730 * has previously been turned off.
11731 */
11732 if (!intel_crtc->primary_enabled && ret == 0) {
11733 WARN_ON(!intel_crtc->active);
11734 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11735 }
11736
11737 /*
11738 * In the fastboot case this may be our only check of the
11739 * state after boot. It would be better to only do it on
11740 * the first update, but we don't have a nice way of doing that
11741 * (and really, set_config isn't used much for high freq page
11742 * flipping, so increasing its cost here shouldn't be a big
11743 * deal).
11744 */
11745 if (i915.fastboot && ret == 0)
11746 intel_modeset_check_state(set->crtc->dev);
11747 }
11748
11749 if (ret) {
11750 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11751 set->crtc->base.id, ret);
11752fail:
11753 intel_set_config_restore_state(dev, config);
11754
11755 /*
11756 * HACK: if the pipe was on, but we didn't have a framebuffer,
11757 * force the pipe off to avoid oopsing in the modeset code
11758 * due to fb==NULL. This should only happen during boot since
11759 * we don't yet reconstruct the FB from the hardware state.
11760 */
11761 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11762 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11763
11764 /* Try to restore the config */
11765 if (config->mode_changed &&
11766 intel_set_mode(save_set.crtc, save_set.mode,
11767 save_set.x, save_set.y, save_set.fb))
11768 DRM_ERROR("failed to restore config after modeset failure\n");
11769 }
11770
11771out_config:
11772 intel_set_config_free(config);
11773 return ret;
11774}
11775
11776static const struct drm_crtc_funcs intel_crtc_funcs = {
11777 .gamma_set = intel_crtc_gamma_set,
11778 .set_config = intel_crtc_set_config,
11779 .destroy = intel_crtc_destroy,
11780 .page_flip = intel_crtc_page_flip,
11781 .atomic_duplicate_state = intel_crtc_duplicate_state,
11782 .atomic_destroy_state = intel_crtc_destroy_state,
11783};
11784
11785static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11786 struct intel_shared_dpll *pll,
11787 struct intel_dpll_hw_state *hw_state)
11788{
11789 uint32_t val;
11790
11791 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11792 return false;
11793
11794 val = I915_READ(PCH_DPLL(pll->id));
11795 hw_state->dpll = val;
11796 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11797 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11798
11799 return val & DPLL_VCO_ENABLE;
11800}
11801
11802static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11803 struct intel_shared_dpll *pll)
11804{
11805 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11806 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11807}
11808
11809static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11810 struct intel_shared_dpll *pll)
11811{
11812 /* PCH refclock must be enabled first */
11813 ibx_assert_pch_refclk_enabled(dev_priv);
11814
11815 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11816
11817 /* Wait for the clocks to stabilize. */
11818 POSTING_READ(PCH_DPLL(pll->id));
11819 udelay(150);
11820
11821 /* The pixel multiplier can only be updated once the
11822 * DPLL is enabled and the clocks are stable.
11823 *
11824 * So write it again.
11825 */
11826 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11827 POSTING_READ(PCH_DPLL(pll->id));
11828 udelay(200);
11829}
11830
11831static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11832 struct intel_shared_dpll *pll)
11833{
11834 struct drm_device *dev = dev_priv->dev;
11835 struct intel_crtc *crtc;
11836
11837 /* Make sure no transcoder isn't still depending on us. */
11838 for_each_intel_crtc(dev, crtc) {
11839 if (intel_crtc_to_shared_dpll(crtc) == pll)
11840 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11841 }
11842
11843 I915_WRITE(PCH_DPLL(pll->id), 0);
11844 POSTING_READ(PCH_DPLL(pll->id));
11845 udelay(200);
11846}
11847
11848static char *ibx_pch_dpll_names[] = {
11849 "PCH DPLL A",
11850 "PCH DPLL B",
11851};
11852
11853static void ibx_pch_dpll_init(struct drm_device *dev)
11854{
11855 struct drm_i915_private *dev_priv = dev->dev_private;
11856 int i;
11857
11858 dev_priv->num_shared_dpll = 2;
11859
11860 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11861 dev_priv->shared_dplls[i].id = i;
11862 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11863 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11864 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11865 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11866 dev_priv->shared_dplls[i].get_hw_state =
11867 ibx_pch_dpll_get_hw_state;
11868 }
11869}
11870
11871static void intel_shared_dpll_init(struct drm_device *dev)
11872{
11873 struct drm_i915_private *dev_priv = dev->dev_private;
11874
11875 if (HAS_DDI(dev))
11876 intel_ddi_pll_init(dev);
11877 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11878 ibx_pch_dpll_init(dev);
11879 else
11880 dev_priv->num_shared_dpll = 0;
11881
11882 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11883}
11884
11885/**
11886 * intel_prepare_plane_fb - Prepare fb for usage on plane
11887 * @plane: drm plane to prepare for
11888 * @fb: framebuffer to prepare for presentation
11889 *
11890 * Prepares a framebuffer for usage on a display plane. Generally this
11891 * involves pinning the underlying object and updating the frontbuffer tracking
11892 * bits. Some older platforms need special physical address handling for
11893 * cursor planes.
11894 *
11895 * Returns 0 on success, negative error code on failure.
11896 */
11897int
11898intel_prepare_plane_fb(struct drm_plane *plane,
11899 struct drm_framebuffer *fb,
11900 const struct drm_plane_state *new_state)
11901{
11902 struct drm_device *dev = plane->dev;
11903 struct intel_plane *intel_plane = to_intel_plane(plane);
11904 enum pipe pipe = intel_plane->pipe;
11905 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11906 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11907 unsigned frontbuffer_bits = 0;
11908 int ret = 0;
11909
11910 if (!obj)
11911 return 0;
11912
11913 switch (plane->type) {
11914 case DRM_PLANE_TYPE_PRIMARY:
11915 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11916 break;
11917 case DRM_PLANE_TYPE_CURSOR:
11918 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11919 break;
11920 case DRM_PLANE_TYPE_OVERLAY:
11921 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11922 break;
11923 }
11924
11925 mutex_lock(&dev->struct_mutex);
11926
11927 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11928 INTEL_INFO(dev)->cursor_needs_physical) {
11929 int align = IS_I830(dev) ? 16 * 1024 : 256;
11930 ret = i915_gem_object_attach_phys(obj, align);
11931 if (ret)
11932 DRM_DEBUG_KMS("failed to attach phys object\n");
11933 } else {
11934 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11935 }
11936
11937 if (ret == 0)
11938 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11939
11940 mutex_unlock(&dev->struct_mutex);
11941
11942 return ret;
11943}
11944
11945/**
11946 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11947 * @plane: drm plane to clean up for
11948 * @fb: old framebuffer that was on plane
11949 *
11950 * Cleans up a framebuffer that has just been removed from a plane.
11951 */
11952void
11953intel_cleanup_plane_fb(struct drm_plane *plane,
11954 struct drm_framebuffer *fb,
11955 const struct drm_plane_state *old_state)
11956{
11957 struct drm_device *dev = plane->dev;
11958 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11959
11960 if (WARN_ON(!obj))
11961 return;
11962
11963 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11964 !INTEL_INFO(dev)->cursor_needs_physical) {
11965 mutex_lock(&dev->struct_mutex);
11966 intel_unpin_fb_obj(obj);
11967 mutex_unlock(&dev->struct_mutex);
11968 }
11969}
11970
11971static int
11972intel_check_primary_plane(struct drm_plane *plane,
11973 struct intel_plane_state *state)
11974{
11975 struct drm_device *dev = plane->dev;
11976 struct drm_i915_private *dev_priv = dev->dev_private;
11977 struct drm_crtc *crtc = state->base.crtc;
11978 struct intel_crtc *intel_crtc;
11979 struct drm_framebuffer *fb = state->base.fb;
11980 struct drm_rect *dest = &state->dst;
11981 struct drm_rect *src = &state->src;
11982 const struct drm_rect *clip = &state->clip;
11983 int ret;
11984
11985 crtc = crtc ? crtc : plane->crtc;
11986 intel_crtc = to_intel_crtc(crtc);
11987
11988 ret = drm_plane_helper_check_update(plane, crtc, fb,
11989 src, dest, clip,
11990 DRM_PLANE_HELPER_NO_SCALING,
11991 DRM_PLANE_HELPER_NO_SCALING,
11992 false, true, &state->visible);
11993 if (ret)
11994 return ret;
11995
11996 if (intel_crtc->active) {
11997 intel_crtc->atomic.wait_for_flips = true;
11998
11999 /*
12000 * FBC does not work on some platforms for rotated
12001 * planes, so disable it when rotation is not 0 and
12002 * update it when rotation is set back to 0.
12003 *
12004 * FIXME: This is redundant with the fbc update done in
12005 * the primary plane enable function except that that
12006 * one is done too late. We eventually need to unify
12007 * this.
12008 */
12009 if (intel_crtc->primary_enabled &&
12010 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12011 dev_priv->fbc.crtc == intel_crtc &&
12012 state->base.rotation != BIT(DRM_ROTATE_0)) {
12013 intel_crtc->atomic.disable_fbc = true;
12014 }
12015
12016 if (state->visible) {
12017 /*
12018 * BDW signals flip done immediately if the plane
12019 * is disabled, even if the plane enable is already
12020 * armed to occur at the next vblank :(
12021 */
12022 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12023 intel_crtc->atomic.wait_vblank = true;
12024 }
12025
12026 intel_crtc->atomic.fb_bits |=
12027 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12028
12029 intel_crtc->atomic.update_fbc = true;
12030
12031 /* Update watermarks on tiling changes. */
12032 if (!plane->state->fb || !state->base.fb ||
12033 plane->state->fb->modifier[0] !=
12034 state->base.fb->modifier[0])
12035 intel_crtc->atomic.update_wm = true;
12036 }
12037
12038 return 0;
12039}
12040
12041static void
12042intel_commit_primary_plane(struct drm_plane *plane,
12043 struct intel_plane_state *state)
12044{
12045 struct drm_crtc *crtc = state->base.crtc;
12046 struct drm_framebuffer *fb = state->base.fb;
12047 struct drm_device *dev = plane->dev;
12048 struct drm_i915_private *dev_priv = dev->dev_private;
12049 struct intel_crtc *intel_crtc;
12050 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12051 struct intel_plane *intel_plane = to_intel_plane(plane);
12052 struct drm_rect *src = &state->src;
12053
12054 crtc = crtc ? crtc : plane->crtc;
12055 intel_crtc = to_intel_crtc(crtc);
12056
12057 plane->fb = fb;
12058 crtc->x = src->x1 >> 16;
12059 crtc->y = src->y1 >> 16;
12060
12061 intel_plane->obj = obj;
12062
12063 if (intel_crtc->active) {
12064 if (state->visible) {
12065 /* FIXME: kill this fastboot hack */
12066 intel_update_pipe_size(intel_crtc);
12067
12068 intel_crtc->primary_enabled = true;
12069
12070 dev_priv->display.update_primary_plane(crtc, plane->fb,
12071 crtc->x, crtc->y);
12072 } else {
12073 /*
12074 * If clipping results in a non-visible primary plane,
12075 * we'll disable the primary plane. Note that this is
12076 * a bit different than what happens if userspace
12077 * explicitly disables the plane by passing fb=0
12078 * because plane->fb still gets set and pinned.
12079 */
12080 intel_disable_primary_hw_plane(plane, crtc);
12081 }
12082 }
12083}
12084
12085static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12086{
12087 struct drm_device *dev = crtc->dev;
12088 struct drm_i915_private *dev_priv = dev->dev_private;
12089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12090 struct intel_plane *intel_plane;
12091 struct drm_plane *p;
12092 unsigned fb_bits = 0;
12093
12094 /* Track fb's for any planes being disabled */
12095 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12096 intel_plane = to_intel_plane(p);
12097
12098 if (intel_crtc->atomic.disabled_planes &
12099 (1 << drm_plane_index(p))) {
12100 switch (p->type) {
12101 case DRM_PLANE_TYPE_PRIMARY:
12102 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12103 break;
12104 case DRM_PLANE_TYPE_CURSOR:
12105 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12106 break;
12107 case DRM_PLANE_TYPE_OVERLAY:
12108 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12109 break;
12110 }
12111
12112 mutex_lock(&dev->struct_mutex);
12113 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12114 mutex_unlock(&dev->struct_mutex);
12115 }
12116 }
12117
12118 if (intel_crtc->atomic.wait_for_flips)
12119 intel_crtc_wait_for_pending_flips(crtc);
12120
12121 if (intel_crtc->atomic.disable_fbc)
12122 intel_fbc_disable(dev);
12123
12124 if (intel_crtc->atomic.pre_disable_primary)
12125 intel_pre_disable_primary(crtc);
12126
12127 if (intel_crtc->atomic.update_wm)
12128 intel_update_watermarks(crtc);
12129
12130 intel_runtime_pm_get(dev_priv);
12131
12132 /* Perform vblank evasion around commit operation */
12133 if (intel_crtc->active)
12134 intel_crtc->atomic.evade =
12135 intel_pipe_update_start(intel_crtc,
12136 &intel_crtc->atomic.start_vbl_count);
12137}
12138
12139static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12140{
12141 struct drm_device *dev = crtc->dev;
12142 struct drm_i915_private *dev_priv = dev->dev_private;
12143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12144 struct drm_plane *p;
12145
12146 if (intel_crtc->atomic.evade)
12147 intel_pipe_update_end(intel_crtc,
12148 intel_crtc->atomic.start_vbl_count);
12149
12150 intel_runtime_pm_put(dev_priv);
12151
12152 if (intel_crtc->atomic.wait_vblank)
12153 intel_wait_for_vblank(dev, intel_crtc->pipe);
12154
12155 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12156
12157 if (intel_crtc->atomic.update_fbc) {
12158 mutex_lock(&dev->struct_mutex);
12159 intel_fbc_update(dev);
12160 mutex_unlock(&dev->struct_mutex);
12161 }
12162
12163 if (intel_crtc->atomic.post_enable_primary)
12164 intel_post_enable_primary(crtc);
12165
12166 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12167 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12168 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12169 false, false);
12170
12171 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12172}
12173
12174/**
12175 * intel_plane_destroy - destroy a plane
12176 * @plane: plane to destroy
12177 *
12178 * Common destruction function for all types of planes (primary, cursor,
12179 * sprite).
12180 */
12181void intel_plane_destroy(struct drm_plane *plane)
12182{
12183 struct intel_plane *intel_plane = to_intel_plane(plane);
12184 drm_plane_cleanup(plane);
12185 kfree(intel_plane);
12186}
12187
12188const struct drm_plane_funcs intel_plane_funcs = {
12189 .update_plane = drm_plane_helper_update,
12190 .disable_plane = drm_plane_helper_disable,
12191 .destroy = intel_plane_destroy,
12192 .set_property = drm_atomic_helper_plane_set_property,
12193 .atomic_get_property = intel_plane_atomic_get_property,
12194 .atomic_set_property = intel_plane_atomic_set_property,
12195 .atomic_duplicate_state = intel_plane_duplicate_state,
12196 .atomic_destroy_state = intel_plane_destroy_state,
12197
12198};
12199
12200static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12201 int pipe)
12202{
12203 struct intel_plane *primary;
12204 struct intel_plane_state *state;
12205 const uint32_t *intel_primary_formats;
12206 int num_formats;
12207
12208 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12209 if (primary == NULL)
12210 return NULL;
12211
12212 state = intel_create_plane_state(&primary->base);
12213 if (!state) {
12214 kfree(primary);
12215 return NULL;
12216 }
12217 primary->base.state = &state->base;
12218
12219 primary->can_scale = false;
12220 primary->max_downscale = 1;
12221 primary->pipe = pipe;
12222 primary->plane = pipe;
12223 primary->check_plane = intel_check_primary_plane;
12224 primary->commit_plane = intel_commit_primary_plane;
12225 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12226 primary->plane = !pipe;
12227
12228 if (INTEL_INFO(dev)->gen <= 3) {
12229 intel_primary_formats = intel_primary_formats_gen2;
12230 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12231 } else {
12232 intel_primary_formats = intel_primary_formats_gen4;
12233 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12234 }
12235
12236 drm_universal_plane_init(dev, &primary->base, 0,
12237 &intel_plane_funcs,
12238 intel_primary_formats, num_formats,
12239 DRM_PLANE_TYPE_PRIMARY);
12240
12241 if (INTEL_INFO(dev)->gen >= 4) {
12242 if (!dev->mode_config.rotation_property)
12243 dev->mode_config.rotation_property =
12244 drm_mode_create_rotation_property(dev,
12245 BIT(DRM_ROTATE_0) |
12246 BIT(DRM_ROTATE_180));
12247 if (dev->mode_config.rotation_property)
12248 drm_object_attach_property(&primary->base.base,
12249 dev->mode_config.rotation_property,
12250 state->base.rotation);
12251 }
12252
12253 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12254
12255 return &primary->base;
12256}
12257
12258static int
12259intel_check_cursor_plane(struct drm_plane *plane,
12260 struct intel_plane_state *state)
12261{
12262 struct drm_crtc *crtc = state->base.crtc;
12263 struct drm_device *dev = plane->dev;
12264 struct drm_framebuffer *fb = state->base.fb;
12265 struct drm_rect *dest = &state->dst;
12266 struct drm_rect *src = &state->src;
12267 const struct drm_rect *clip = &state->clip;
12268 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12269 struct intel_crtc *intel_crtc;
12270 unsigned stride;
12271 int ret;
12272
12273 crtc = crtc ? crtc : plane->crtc;
12274 intel_crtc = to_intel_crtc(crtc);
12275
12276 ret = drm_plane_helper_check_update(plane, crtc, fb,
12277 src, dest, clip,
12278 DRM_PLANE_HELPER_NO_SCALING,
12279 DRM_PLANE_HELPER_NO_SCALING,
12280 true, true, &state->visible);
12281 if (ret)
12282 return ret;
12283
12284
12285 /* if we want to turn off the cursor ignore width and height */
12286 if (!obj)
12287 goto finish;
12288
12289 /* Check for which cursor types we support */
12290 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12291 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12292 state->base.crtc_w, state->base.crtc_h);
12293 return -EINVAL;
12294 }
12295
12296 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12297 if (obj->base.size < stride * state->base.crtc_h) {
12298 DRM_DEBUG_KMS("buffer is too small\n");
12299 return -ENOMEM;
12300 }
12301
12302 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12303 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12304 ret = -EINVAL;
12305 }
12306
12307finish:
12308 if (intel_crtc->active) {
12309 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12310 intel_crtc->atomic.update_wm = true;
12311
12312 intel_crtc->atomic.fb_bits |=
12313 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12314 }
12315
12316 return ret;
12317}
12318
12319static void
12320intel_commit_cursor_plane(struct drm_plane *plane,
12321 struct intel_plane_state *state)
12322{
12323 struct drm_crtc *crtc = state->base.crtc;
12324 struct drm_device *dev = plane->dev;
12325 struct intel_crtc *intel_crtc;
12326 struct intel_plane *intel_plane = to_intel_plane(plane);
12327 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12328 uint32_t addr;
12329
12330 crtc = crtc ? crtc : plane->crtc;
12331 intel_crtc = to_intel_crtc(crtc);
12332
12333 plane->fb = state->base.fb;
12334 crtc->cursor_x = state->base.crtc_x;
12335 crtc->cursor_y = state->base.crtc_y;
12336
12337 intel_plane->obj = obj;
12338
12339 if (intel_crtc->cursor_bo == obj)
12340 goto update;
12341
12342 if (!obj)
12343 addr = 0;
12344 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12345 addr = i915_gem_obj_ggtt_offset(obj);
12346 else
12347 addr = obj->phys_handle->busaddr;
12348
12349 intel_crtc->cursor_addr = addr;
12350 intel_crtc->cursor_bo = obj;
12351update:
12352
12353 if (intel_crtc->active)
12354 intel_crtc_update_cursor(crtc, state->visible);
12355}
12356
12357static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12358 int pipe)
12359{
12360 struct intel_plane *cursor;
12361 struct intel_plane_state *state;
12362
12363 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12364 if (cursor == NULL)
12365 return NULL;
12366
12367 state = intel_create_plane_state(&cursor->base);
12368 if (!state) {
12369 kfree(cursor);
12370 return NULL;
12371 }
12372 cursor->base.state = &state->base;
12373
12374 cursor->can_scale = false;
12375 cursor->max_downscale = 1;
12376 cursor->pipe = pipe;
12377 cursor->plane = pipe;
12378 cursor->check_plane = intel_check_cursor_plane;
12379 cursor->commit_plane = intel_commit_cursor_plane;
12380
12381 drm_universal_plane_init(dev, &cursor->base, 0,
12382 &intel_plane_funcs,
12383 intel_cursor_formats,
12384 ARRAY_SIZE(intel_cursor_formats),
12385 DRM_PLANE_TYPE_CURSOR);
12386
12387 if (INTEL_INFO(dev)->gen >= 4) {
12388 if (!dev->mode_config.rotation_property)
12389 dev->mode_config.rotation_property =
12390 drm_mode_create_rotation_property(dev,
12391 BIT(DRM_ROTATE_0) |
12392 BIT(DRM_ROTATE_180));
12393 if (dev->mode_config.rotation_property)
12394 drm_object_attach_property(&cursor->base.base,
12395 dev->mode_config.rotation_property,
12396 state->base.rotation);
12397 }
12398
12399 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12400
12401 return &cursor->base;
12402}
12403
12404static void intel_crtc_init(struct drm_device *dev, int pipe)
12405{
12406 struct drm_i915_private *dev_priv = dev->dev_private;
12407 struct intel_crtc *intel_crtc;
12408 struct intel_crtc_state *crtc_state = NULL;
12409 struct drm_plane *primary = NULL;
12410 struct drm_plane *cursor = NULL;
12411 int i, ret;
12412
12413 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12414 if (intel_crtc == NULL)
12415 return;
12416
12417 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12418 if (!crtc_state)
12419 goto fail;
12420 intel_crtc_set_state(intel_crtc, crtc_state);
12421 crtc_state->base.crtc = &intel_crtc->base;
12422
12423 primary = intel_primary_plane_create(dev, pipe);
12424 if (!primary)
12425 goto fail;
12426
12427 cursor = intel_cursor_plane_create(dev, pipe);
12428 if (!cursor)
12429 goto fail;
12430
12431 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12432 cursor, &intel_crtc_funcs);
12433 if (ret)
12434 goto fail;
12435
12436 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12437 for (i = 0; i < 256; i++) {
12438 intel_crtc->lut_r[i] = i;
12439 intel_crtc->lut_g[i] = i;
12440 intel_crtc->lut_b[i] = i;
12441 }
12442
12443 /*
12444 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12445 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12446 */
12447 intel_crtc->pipe = pipe;
12448 intel_crtc->plane = pipe;
12449 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12450 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12451 intel_crtc->plane = !pipe;
12452 }
12453
12454 intel_crtc->cursor_base = ~0;
12455 intel_crtc->cursor_cntl = ~0;
12456 intel_crtc->cursor_size = ~0;
12457
12458 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12459 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12460 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12461 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12462
12463 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12464
12465 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12466
12467 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12468 return;
12469
12470fail:
12471 if (primary)
12472 drm_plane_cleanup(primary);
12473 if (cursor)
12474 drm_plane_cleanup(cursor);
12475 kfree(crtc_state);
12476 kfree(intel_crtc);
12477}
12478
12479enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12480{
12481 struct drm_encoder *encoder = connector->base.encoder;
12482 struct drm_device *dev = connector->base.dev;
12483
12484 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12485
12486 if (!encoder || WARN_ON(!encoder->crtc))
12487 return INVALID_PIPE;
12488
12489 return to_intel_crtc(encoder->crtc)->pipe;
12490}
12491
12492int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12493 struct drm_file *file)
12494{
12495 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12496 struct drm_crtc *drmmode_crtc;
12497 struct intel_crtc *crtc;
12498
12499 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12500
12501 if (!drmmode_crtc) {
12502 DRM_ERROR("no such CRTC id\n");
12503 return -ENOENT;
12504 }
12505
12506 crtc = to_intel_crtc(drmmode_crtc);
12507 pipe_from_crtc_id->pipe = crtc->pipe;
12508
12509 return 0;
12510}
12511
12512static int intel_encoder_clones(struct intel_encoder *encoder)
12513{
12514 struct drm_device *dev = encoder->base.dev;
12515 struct intel_encoder *source_encoder;
12516 int index_mask = 0;
12517 int entry = 0;
12518
12519 for_each_intel_encoder(dev, source_encoder) {
12520 if (encoders_cloneable(encoder, source_encoder))
12521 index_mask |= (1 << entry);
12522
12523 entry++;
12524 }
12525
12526 return index_mask;
12527}
12528
12529static bool has_edp_a(struct drm_device *dev)
12530{
12531 struct drm_i915_private *dev_priv = dev->dev_private;
12532
12533 if (!IS_MOBILE(dev))
12534 return false;
12535
12536 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12537 return false;
12538
12539 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12540 return false;
12541
12542 return true;
12543}
12544
12545static bool intel_crt_present(struct drm_device *dev)
12546{
12547 struct drm_i915_private *dev_priv = dev->dev_private;
12548
12549 if (INTEL_INFO(dev)->gen >= 9)
12550 return false;
12551
12552 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12553 return false;
12554
12555 if (IS_CHERRYVIEW(dev))
12556 return false;
12557
12558 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12559 return false;
12560
12561 return true;
12562}
12563
12564static void intel_setup_outputs(struct drm_device *dev)
12565{
12566 struct drm_i915_private *dev_priv = dev->dev_private;
12567 struct intel_encoder *encoder;
12568 struct drm_connector *connector;
12569 bool dpd_is_edp = false;
12570
12571 intel_lvds_init(dev);
12572
12573 if (intel_crt_present(dev))
12574 intel_crt_init(dev);
12575
12576 if (HAS_DDI(dev)) {
12577 int found;
12578
12579 /*
12580 * Haswell uses DDI functions to detect digital outputs.
12581 * On SKL pre-D0 the strap isn't connected, so we assume
12582 * it's there.
12583 */
12584 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12585 /* WaIgnoreDDIAStrap: skl */
12586 if (found ||
12587 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12588 intel_ddi_init(dev, PORT_A);
12589
12590 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12591 * register */
12592 found = I915_READ(SFUSE_STRAP);
12593
12594 if (found & SFUSE_STRAP_DDIB_DETECTED)
12595 intel_ddi_init(dev, PORT_B);
12596 if (found & SFUSE_STRAP_DDIC_DETECTED)
12597 intel_ddi_init(dev, PORT_C);
12598 if (found & SFUSE_STRAP_DDID_DETECTED)
12599 intel_ddi_init(dev, PORT_D);
12600 } else if (HAS_PCH_SPLIT(dev)) {
12601 int found;
12602 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12603
12604 if (has_edp_a(dev))
12605 intel_dp_init(dev, DP_A, PORT_A);
12606
12607 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12608 /* PCH SDVOB multiplex with HDMIB */
12609 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12610 if (!found)
12611 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12612 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12613 intel_dp_init(dev, PCH_DP_B, PORT_B);
12614 }
12615
12616 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12617 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12618
12619 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12620 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12621
12622 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12623 intel_dp_init(dev, PCH_DP_C, PORT_C);
12624
12625 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12626 intel_dp_init(dev, PCH_DP_D, PORT_D);
12627 } else if (IS_VALLEYVIEW(dev)) {
12628 /*
12629 * The DP_DETECTED bit is the latched state of the DDC
12630 * SDA pin at boot. However since eDP doesn't require DDC
12631 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12632 * eDP ports may have been muxed to an alternate function.
12633 * Thus we can't rely on the DP_DETECTED bit alone to detect
12634 * eDP ports. Consult the VBT as well as DP_DETECTED to
12635 * detect eDP ports.
12636 */
12637 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12638 !intel_dp_is_edp(dev, PORT_B))
12639 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12640 PORT_B);
12641 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12642 intel_dp_is_edp(dev, PORT_B))
12643 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12644
12645 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12646 !intel_dp_is_edp(dev, PORT_C))
12647 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12648 PORT_C);
12649 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12650 intel_dp_is_edp(dev, PORT_C))
12651 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12652
12653 if (IS_CHERRYVIEW(dev)) {
12654 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12655 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12656 PORT_D);
12657 /* eDP not supported on port D, so don't check VBT */
12658 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12659 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12660 }
12661
12662 intel_dsi_init(dev);
12663 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12664 bool found = false;
12665
12666 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12667 DRM_DEBUG_KMS("probing SDVOB\n");
12668 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12669 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12670 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12671 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12672 }
12673
12674 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12675 intel_dp_init(dev, DP_B, PORT_B);
12676 }
12677
12678 /* Before G4X SDVOC doesn't have its own detect register */
12679
12680 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12681 DRM_DEBUG_KMS("probing SDVOC\n");
12682 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12683 }
12684
12685 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12686
12687 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12688 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12689 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12690 }
12691 if (SUPPORTS_INTEGRATED_DP(dev))
12692 intel_dp_init(dev, DP_C, PORT_C);
12693 }
12694
12695 if (SUPPORTS_INTEGRATED_DP(dev) &&
12696 (I915_READ(DP_D) & DP_DETECTED))
12697 intel_dp_init(dev, DP_D, PORT_D);
12698 } else if (IS_GEN2(dev))
12699 intel_dvo_init(dev);
12700
12701 if (SUPPORTS_TV(dev))
12702 intel_tv_init(dev);
12703
12704 /*
12705 * FIXME: We don't have full atomic support yet, but we want to be
12706 * able to enable/test plane updates via the atomic interface in the
12707 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12708 * will take some atomic codepaths to lookup properties during
12709 * drmModeGetConnector() that unconditionally dereference
12710 * connector->state.
12711 *
12712 * We create a dummy connector state here for each connector to ensure
12713 * the DRM core doesn't try to dereference a NULL connector->state.
12714 * The actual connector properties will never be updated or contain
12715 * useful information, but since we're doing this specifically for
12716 * testing/debug of the plane operations (and only when a specific
12717 * kernel module option is given), that shouldn't really matter.
12718 *
12719 * Once atomic support for crtc's + connectors lands, this loop should
12720 * be removed since we'll be setting up real connector state, which
12721 * will contain Intel-specific properties.
12722 */
12723 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12724 list_for_each_entry(connector,
12725 &dev->mode_config.connector_list,
12726 head) {
12727 if (!WARN_ON(connector->state)) {
12728 connector->state =
12729 kzalloc(sizeof(*connector->state),
12730 GFP_KERNEL);
12731 }
12732 }
12733 }
12734
12735 intel_psr_init(dev);
12736
12737 for_each_intel_encoder(dev, encoder) {
12738 encoder->base.possible_crtcs = encoder->crtc_mask;
12739 encoder->base.possible_clones =
12740 intel_encoder_clones(encoder);
12741 }
12742
12743 intel_init_pch_refclk(dev);
12744
12745 drm_helper_move_panel_connectors_to_head(dev);
12746}
12747
12748static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12749{
12750 struct drm_device *dev = fb->dev;
12751 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12752
12753 drm_framebuffer_cleanup(fb);
12754 mutex_lock(&dev->struct_mutex);
12755 WARN_ON(!intel_fb->obj->framebuffer_references--);
12756 drm_gem_object_unreference(&intel_fb->obj->base);
12757 mutex_unlock(&dev->struct_mutex);
12758 kfree(intel_fb);
12759}
12760
12761static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12762 struct drm_file *file,
12763 unsigned int *handle)
12764{
12765 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12766 struct drm_i915_gem_object *obj = intel_fb->obj;
12767
12768 return drm_gem_handle_create(file, &obj->base, handle);
12769}
12770
12771static const struct drm_framebuffer_funcs intel_fb_funcs = {
12772 .destroy = intel_user_framebuffer_destroy,
12773 .create_handle = intel_user_framebuffer_create_handle,
12774};
12775
12776static
12777u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12778 uint32_t pixel_format)
12779{
12780 u32 gen = INTEL_INFO(dev)->gen;
12781
12782 if (gen >= 9) {
12783 /* "The stride in bytes must not exceed the of the size of 8K
12784 * pixels and 32K bytes."
12785 */
12786 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12787 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12788 return 32*1024;
12789 } else if (gen >= 4) {
12790 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12791 return 16*1024;
12792 else
12793 return 32*1024;
12794 } else if (gen >= 3) {
12795 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12796 return 8*1024;
12797 else
12798 return 16*1024;
12799 } else {
12800 /* XXX DSPC is limited to 4k tiled */
12801 return 8*1024;
12802 }
12803}
12804
12805static int intel_framebuffer_init(struct drm_device *dev,
12806 struct intel_framebuffer *intel_fb,
12807 struct drm_mode_fb_cmd2 *mode_cmd,
12808 struct drm_i915_gem_object *obj)
12809{
12810 int aligned_height;
12811 int ret;
12812 u32 pitch_limit, stride_alignment;
12813
12814 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12815
12816 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12817 /* Enforce that fb modifier and tiling mode match, but only for
12818 * X-tiled. This is needed for FBC. */
12819 if (!!(obj->tiling_mode == I915_TILING_X) !=
12820 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12821 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12822 return -EINVAL;
12823 }
12824 } else {
12825 if (obj->tiling_mode == I915_TILING_X)
12826 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12827 else if (obj->tiling_mode == I915_TILING_Y) {
12828 DRM_DEBUG("No Y tiling for legacy addfb\n");
12829 return -EINVAL;
12830 }
12831 }
12832
12833 /* Passed in modifier sanity checking. */
12834 switch (mode_cmd->modifier[0]) {
12835 case I915_FORMAT_MOD_Y_TILED:
12836 case I915_FORMAT_MOD_Yf_TILED:
12837 if (INTEL_INFO(dev)->gen < 9) {
12838 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12839 mode_cmd->modifier[0]);
12840 return -EINVAL;
12841 }
12842 case DRM_FORMAT_MOD_NONE:
12843 case I915_FORMAT_MOD_X_TILED:
12844 break;
12845 default:
12846 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12847 mode_cmd->modifier[0]);
12848 return -EINVAL;
12849 }
12850
12851 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12852 mode_cmd->pixel_format);
12853 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12854 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12855 mode_cmd->pitches[0], stride_alignment);
12856 return -EINVAL;
12857 }
12858
12859 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12860 mode_cmd->pixel_format);
12861 if (mode_cmd->pitches[0] > pitch_limit) {
12862 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12863 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12864 "tiled" : "linear",
12865 mode_cmd->pitches[0], pitch_limit);
12866 return -EINVAL;
12867 }
12868
12869 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12870 mode_cmd->pitches[0] != obj->stride) {
12871 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12872 mode_cmd->pitches[0], obj->stride);
12873 return -EINVAL;
12874 }
12875
12876 /* Reject formats not supported by any plane early. */
12877 switch (mode_cmd->pixel_format) {
12878 case DRM_FORMAT_C8:
12879 case DRM_FORMAT_RGB565:
12880 case DRM_FORMAT_XRGB8888:
12881 case DRM_FORMAT_ARGB8888:
12882 break;
12883 case DRM_FORMAT_XRGB1555:
12884 case DRM_FORMAT_ARGB1555:
12885 if (INTEL_INFO(dev)->gen > 3) {
12886 DRM_DEBUG("unsupported pixel format: %s\n",
12887 drm_get_format_name(mode_cmd->pixel_format));
12888 return -EINVAL;
12889 }
12890 break;
12891 case DRM_FORMAT_XBGR8888:
12892 case DRM_FORMAT_ABGR8888:
12893 case DRM_FORMAT_XRGB2101010:
12894 case DRM_FORMAT_ARGB2101010:
12895 case DRM_FORMAT_XBGR2101010:
12896 case DRM_FORMAT_ABGR2101010:
12897 if (INTEL_INFO(dev)->gen < 4) {
12898 DRM_DEBUG("unsupported pixel format: %s\n",
12899 drm_get_format_name(mode_cmd->pixel_format));
12900 return -EINVAL;
12901 }
12902 break;
12903 case DRM_FORMAT_YUYV:
12904 case DRM_FORMAT_UYVY:
12905 case DRM_FORMAT_YVYU:
12906 case DRM_FORMAT_VYUY:
12907 if (INTEL_INFO(dev)->gen < 5) {
12908 DRM_DEBUG("unsupported pixel format: %s\n",
12909 drm_get_format_name(mode_cmd->pixel_format));
12910 return -EINVAL;
12911 }
12912 break;
12913 default:
12914 DRM_DEBUG("unsupported pixel format: %s\n",
12915 drm_get_format_name(mode_cmd->pixel_format));
12916 return -EINVAL;
12917 }
12918
12919 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12920 if (mode_cmd->offsets[0] != 0)
12921 return -EINVAL;
12922
12923 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12924 mode_cmd->pixel_format,
12925 mode_cmd->modifier[0]);
12926 /* FIXME drm helper for size checks (especially planar formats)? */
12927 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12928 return -EINVAL;
12929
12930 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12931 intel_fb->obj = obj;
12932 intel_fb->obj->framebuffer_references++;
12933
12934 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12935 if (ret) {
12936 DRM_ERROR("framebuffer init failed %d\n", ret);
12937 return ret;
12938 }
12939
12940 return 0;
12941}
12942
12943static struct drm_framebuffer *
12944intel_user_framebuffer_create(struct drm_device *dev,
12945 struct drm_file *filp,
12946 struct drm_mode_fb_cmd2 *mode_cmd)
12947{
12948 struct drm_i915_gem_object *obj;
12949
12950 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12951 mode_cmd->handles[0]));
12952 if (&obj->base == NULL)
12953 return ERR_PTR(-ENOENT);
12954
12955 return intel_framebuffer_create(dev, mode_cmd, obj);
12956}
12957
12958#ifndef CONFIG_DRM_I915_FBDEV
12959static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12960{
12961}
12962#endif
12963
12964static const struct drm_mode_config_funcs intel_mode_funcs = {
12965 .fb_create = intel_user_framebuffer_create,
12966 .output_poll_changed = intel_fbdev_output_poll_changed,
12967 .atomic_check = intel_atomic_check,
12968 .atomic_commit = intel_atomic_commit,
12969};
12970
12971/* Set up chip specific display functions */
12972static void intel_init_display(struct drm_device *dev)
12973{
12974 struct drm_i915_private *dev_priv = dev->dev_private;
12975
12976 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12977 dev_priv->display.find_dpll = g4x_find_best_dpll;
12978 else if (IS_CHERRYVIEW(dev))
12979 dev_priv->display.find_dpll = chv_find_best_dpll;
12980 else if (IS_VALLEYVIEW(dev))
12981 dev_priv->display.find_dpll = vlv_find_best_dpll;
12982 else if (IS_PINEVIEW(dev))
12983 dev_priv->display.find_dpll = pnv_find_best_dpll;
12984 else
12985 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12986
12987 if (INTEL_INFO(dev)->gen >= 9) {
12988 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12989 dev_priv->display.get_initial_plane_config =
12990 skylake_get_initial_plane_config;
12991 dev_priv->display.crtc_compute_clock =
12992 haswell_crtc_compute_clock;
12993 dev_priv->display.crtc_enable = haswell_crtc_enable;
12994 dev_priv->display.crtc_disable = haswell_crtc_disable;
12995 dev_priv->display.off = ironlake_crtc_off;
12996 dev_priv->display.update_primary_plane =
12997 skylake_update_primary_plane;
12998 } else if (HAS_DDI(dev)) {
12999 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13000 dev_priv->display.get_initial_plane_config =
13001 ironlake_get_initial_plane_config;
13002 dev_priv->display.crtc_compute_clock =
13003 haswell_crtc_compute_clock;
13004 dev_priv->display.crtc_enable = haswell_crtc_enable;
13005 dev_priv->display.crtc_disable = haswell_crtc_disable;
13006 dev_priv->display.off = ironlake_crtc_off;
13007 dev_priv->display.update_primary_plane =
13008 ironlake_update_primary_plane;
13009 } else if (HAS_PCH_SPLIT(dev)) {
13010 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13011 dev_priv->display.get_initial_plane_config =
13012 ironlake_get_initial_plane_config;
13013 dev_priv->display.crtc_compute_clock =
13014 ironlake_crtc_compute_clock;
13015 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13016 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13017 dev_priv->display.off = ironlake_crtc_off;
13018 dev_priv->display.update_primary_plane =
13019 ironlake_update_primary_plane;
13020 } else if (IS_VALLEYVIEW(dev)) {
13021 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13022 dev_priv->display.get_initial_plane_config =
13023 i9xx_get_initial_plane_config;
13024 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13025 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13026 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13027 dev_priv->display.off = i9xx_crtc_off;
13028 dev_priv->display.update_primary_plane =
13029 i9xx_update_primary_plane;
13030 } else {
13031 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13032 dev_priv->display.get_initial_plane_config =
13033 i9xx_get_initial_plane_config;
13034 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13035 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13036 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13037 dev_priv->display.off = i9xx_crtc_off;
13038 dev_priv->display.update_primary_plane =
13039 i9xx_update_primary_plane;
13040 }
13041
13042 /* Returns the core display clock speed */
13043 if (IS_VALLEYVIEW(dev))
13044 dev_priv->display.get_display_clock_speed =
13045 valleyview_get_display_clock_speed;
13046 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13047 dev_priv->display.get_display_clock_speed =
13048 i945_get_display_clock_speed;
13049 else if (IS_I915G(dev))
13050 dev_priv->display.get_display_clock_speed =
13051 i915_get_display_clock_speed;
13052 else if (IS_I945GM(dev) || IS_845G(dev))
13053 dev_priv->display.get_display_clock_speed =
13054 i9xx_misc_get_display_clock_speed;
13055 else if (IS_PINEVIEW(dev))
13056 dev_priv->display.get_display_clock_speed =
13057 pnv_get_display_clock_speed;
13058 else if (IS_I915GM(dev))
13059 dev_priv->display.get_display_clock_speed =
13060 i915gm_get_display_clock_speed;
13061 else if (IS_I865G(dev))
13062 dev_priv->display.get_display_clock_speed =
13063 i865_get_display_clock_speed;
13064 else if (IS_I85X(dev))
13065 dev_priv->display.get_display_clock_speed =
13066 i855_get_display_clock_speed;
13067 else /* 852, 830 */
13068 dev_priv->display.get_display_clock_speed =
13069 i830_get_display_clock_speed;
13070
13071 if (IS_GEN5(dev)) {
13072 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13073 } else if (IS_GEN6(dev)) {
13074 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13075 } else if (IS_IVYBRIDGE(dev)) {
13076 /* FIXME: detect B0+ stepping and use auto training */
13077 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13078 dev_priv->display.modeset_global_resources =
13079 ivb_modeset_global_resources;
13080 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13081 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13082 } else if (IS_VALLEYVIEW(dev)) {
13083 dev_priv->display.modeset_global_resources =
13084 valleyview_modeset_global_resources;
13085 }
13086
13087 switch (INTEL_INFO(dev)->gen) {
13088 case 2:
13089 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13090 break;
13091
13092 case 3:
13093 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13094 break;
13095
13096 case 4:
13097 case 5:
13098 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13099 break;
13100
13101 case 6:
13102 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13103 break;
13104 case 7:
13105 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13106 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13107 break;
13108 case 9:
13109 /* Drop through - unsupported since execlist only. */
13110 default:
13111 /* Default just returns -ENODEV to indicate unsupported */
13112 dev_priv->display.queue_flip = intel_default_queue_flip;
13113 }
13114
13115 intel_panel_init_backlight_funcs(dev);
13116
13117 mutex_init(&dev_priv->pps_mutex);
13118}
13119
13120/*
13121 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13122 * resume, or other times. This quirk makes sure that's the case for
13123 * affected systems.
13124 */
13125static void quirk_pipea_force(struct drm_device *dev)
13126{
13127 struct drm_i915_private *dev_priv = dev->dev_private;
13128
13129 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13130 DRM_INFO("applying pipe a force quirk\n");
13131}
13132
13133static void quirk_pipeb_force(struct drm_device *dev)
13134{
13135 struct drm_i915_private *dev_priv = dev->dev_private;
13136
13137 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13138 DRM_INFO("applying pipe b force quirk\n");
13139}
13140
13141/*
13142 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13143 */
13144static void quirk_ssc_force_disable(struct drm_device *dev)
13145{
13146 struct drm_i915_private *dev_priv = dev->dev_private;
13147 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13148 DRM_INFO("applying lvds SSC disable quirk\n");
13149}
13150
13151/*
13152 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13153 * brightness value
13154 */
13155static void quirk_invert_brightness(struct drm_device *dev)
13156{
13157 struct drm_i915_private *dev_priv = dev->dev_private;
13158 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13159 DRM_INFO("applying inverted panel brightness quirk\n");
13160}
13161
13162/* Some VBT's incorrectly indicate no backlight is present */
13163static void quirk_backlight_present(struct drm_device *dev)
13164{
13165 struct drm_i915_private *dev_priv = dev->dev_private;
13166 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13167 DRM_INFO("applying backlight present quirk\n");
13168}
13169
13170struct intel_quirk {
13171 int device;
13172 int subsystem_vendor;
13173 int subsystem_device;
13174 void (*hook)(struct drm_device *dev);
13175};
13176
13177/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13178struct intel_dmi_quirk {
13179 void (*hook)(struct drm_device *dev);
13180 const struct dmi_system_id (*dmi_id_list)[];
13181};
13182
13183static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13184{
13185 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13186 return 1;
13187}
13188
13189static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13190 {
13191 .dmi_id_list = &(const struct dmi_system_id[]) {
13192 {
13193 .callback = intel_dmi_reverse_brightness,
13194 .ident = "NCR Corporation",
13195 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13196 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13197 },
13198 },
13199 { } /* terminating entry */
13200 },
13201 .hook = quirk_invert_brightness,
13202 },
13203};
13204
13205static struct intel_quirk intel_quirks[] = {
13206 /* HP Mini needs pipe A force quirk (LP: #322104) */
13207 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13208
13209 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13210 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13211
13212 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13213 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13214
13215 /* 830 needs to leave pipe A & dpll A up */
13216 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13217
13218 /* 830 needs to leave pipe B & dpll B up */
13219 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13220
13221 /* Lenovo U160 cannot use SSC on LVDS */
13222 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13223
13224 /* Sony Vaio Y cannot use SSC on LVDS */
13225 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13226
13227 /* Acer Aspire 5734Z must invert backlight brightness */
13228 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13229
13230 /* Acer/eMachines G725 */
13231 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13232
13233 /* Acer/eMachines e725 */
13234 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13235
13236 /* Acer/Packard Bell NCL20 */
13237 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13238
13239 /* Acer Aspire 4736Z */
13240 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13241
13242 /* Acer Aspire 5336 */
13243 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13244
13245 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13246 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13247
13248 /* Acer C720 Chromebook (Core i3 4005U) */
13249 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13250
13251 /* Apple Macbook 2,1 (Core 2 T7400) */
13252 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13253
13254 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13255 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13256
13257 /* HP Chromebook 14 (Celeron 2955U) */
13258 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13259
13260 /* Dell Chromebook 11 */
13261 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13262};
13263
13264static void intel_init_quirks(struct drm_device *dev)
13265{
13266 struct pci_dev *d = dev->pdev;
13267 int i;
13268
13269 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13270 struct intel_quirk *q = &intel_quirks[i];
13271
13272 if (d->device == q->device &&
13273 (d->subsystem_vendor == q->subsystem_vendor ||
13274 q->subsystem_vendor == PCI_ANY_ID) &&
13275 (d->subsystem_device == q->subsystem_device ||
13276 q->subsystem_device == PCI_ANY_ID))
13277 q->hook(dev);
13278 }
13279 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13280 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13281 intel_dmi_quirks[i].hook(dev);
13282 }
13283}
13284
13285/* Disable the VGA plane that we never use */
13286static void i915_disable_vga(struct drm_device *dev)
13287{
13288 struct drm_i915_private *dev_priv = dev->dev_private;
13289 u8 sr1;
13290 u32 vga_reg = i915_vgacntrl_reg(dev);
13291
13292 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13293 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13294 outb(SR01, VGA_SR_INDEX);
13295 sr1 = inb(VGA_SR_DATA);
13296 outb(sr1 | 1<<5, VGA_SR_DATA);
13297 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13298 udelay(300);
13299
13300 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13301 POSTING_READ(vga_reg);
13302}
13303
13304void intel_modeset_init_hw(struct drm_device *dev)
13305{
13306 intel_prepare_ddi(dev);
13307
13308 if (IS_VALLEYVIEW(dev))
13309 vlv_update_cdclk(dev);
13310
13311 intel_init_clock_gating(dev);
13312
13313 intel_enable_gt_powersave(dev);
13314}
13315
13316void intel_modeset_init(struct drm_device *dev)
13317{
13318 struct drm_i915_private *dev_priv = dev->dev_private;
13319 int sprite, ret;
13320 enum pipe pipe;
13321 struct intel_crtc *crtc;
13322
13323 drm_mode_config_init(dev);
13324
13325 dev->mode_config.min_width = 0;
13326 dev->mode_config.min_height = 0;
13327
13328 dev->mode_config.preferred_depth = 24;
13329 dev->mode_config.prefer_shadow = 1;
13330
13331 dev->mode_config.allow_fb_modifiers = true;
13332
13333 dev->mode_config.funcs = &intel_mode_funcs;
13334
13335 intel_init_quirks(dev);
13336
13337 intel_init_pm(dev);
13338
13339 if (INTEL_INFO(dev)->num_pipes == 0)
13340 return;
13341
13342 intel_init_display(dev);
13343 intel_init_audio(dev);
13344
13345 if (IS_GEN2(dev)) {
13346 dev->mode_config.max_width = 2048;
13347 dev->mode_config.max_height = 2048;
13348 } else if (IS_GEN3(dev)) {
13349 dev->mode_config.max_width = 4096;
13350 dev->mode_config.max_height = 4096;
13351 } else {
13352 dev->mode_config.max_width = 8192;
13353 dev->mode_config.max_height = 8192;
13354 }
13355
13356 if (IS_845G(dev) || IS_I865G(dev)) {
13357 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13358 dev->mode_config.cursor_height = 1023;
13359 } else if (IS_GEN2(dev)) {
13360 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13361 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13362 } else {
13363 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13364 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13365 }
13366
13367 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13368
13369 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13370 INTEL_INFO(dev)->num_pipes,
13371 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13372
13373 for_each_pipe(dev_priv, pipe) {
13374 intel_crtc_init(dev, pipe);
13375 for_each_sprite(dev_priv, pipe, sprite) {
13376 ret = intel_plane_init(dev, pipe, sprite);
13377 if (ret)
13378 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13379 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13380 }
13381 }
13382
13383 intel_init_dpio(dev);
13384
13385 intel_shared_dpll_init(dev);
13386
13387 /* Just disable it once at startup */
13388 i915_disable_vga(dev);
13389 intel_setup_outputs(dev);
13390
13391 /* Just in case the BIOS is doing something questionable. */
13392 intel_fbc_disable(dev);
13393
13394 drm_modeset_lock_all(dev);
13395 intel_modeset_setup_hw_state(dev, false);
13396 drm_modeset_unlock_all(dev);
13397
13398 for_each_intel_crtc(dev, crtc) {
13399 if (!crtc->active)
13400 continue;
13401
13402 /*
13403 * Note that reserving the BIOS fb up front prevents us
13404 * from stuffing other stolen allocations like the ring
13405 * on top. This prevents some ugliness at boot time, and
13406 * can even allow for smooth boot transitions if the BIOS
13407 * fb is large enough for the active pipe configuration.
13408 */
13409 if (dev_priv->display.get_initial_plane_config) {
13410 dev_priv->display.get_initial_plane_config(crtc,
13411 &crtc->plane_config);
13412 /*
13413 * If the fb is shared between multiple heads, we'll
13414 * just get the first one.
13415 */
13416 intel_find_plane_obj(crtc, &crtc->plane_config);
13417 }
13418 }
13419}
13420
13421static void intel_enable_pipe_a(struct drm_device *dev)
13422{
13423 struct intel_connector *connector;
13424 struct drm_connector *crt = NULL;
13425 struct intel_load_detect_pipe load_detect_temp;
13426 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13427
13428 /* We can't just switch on the pipe A, we need to set things up with a
13429 * proper mode and output configuration. As a gross hack, enable pipe A
13430 * by enabling the load detect pipe once. */
13431 for_each_intel_connector(dev, connector) {
13432 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13433 crt = &connector->base;
13434 break;
13435 }
13436 }
13437
13438 if (!crt)
13439 return;
13440
13441 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13442 intel_release_load_detect_pipe(crt, &load_detect_temp);
13443}
13444
13445static bool
13446intel_check_plane_mapping(struct intel_crtc *crtc)
13447{
13448 struct drm_device *dev = crtc->base.dev;
13449 struct drm_i915_private *dev_priv = dev->dev_private;
13450 u32 reg, val;
13451
13452 if (INTEL_INFO(dev)->num_pipes == 1)
13453 return true;
13454
13455 reg = DSPCNTR(!crtc->plane);
13456 val = I915_READ(reg);
13457
13458 if ((val & DISPLAY_PLANE_ENABLE) &&
13459 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13460 return false;
13461
13462 return true;
13463}
13464
13465static void intel_sanitize_crtc(struct intel_crtc *crtc)
13466{
13467 struct drm_device *dev = crtc->base.dev;
13468 struct drm_i915_private *dev_priv = dev->dev_private;
13469 u32 reg;
13470
13471 /* Clear any frame start delays used for debugging left by the BIOS */
13472 reg = PIPECONF(crtc->config->cpu_transcoder);
13473 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13474
13475 /* restore vblank interrupts to correct state */
13476 drm_crtc_vblank_reset(&crtc->base);
13477 if (crtc->active) {
13478 update_scanline_offset(crtc);
13479 drm_crtc_vblank_on(&crtc->base);
13480 }
13481
13482 /* We need to sanitize the plane -> pipe mapping first because this will
13483 * disable the crtc (and hence change the state) if it is wrong. Note
13484 * that gen4+ has a fixed plane -> pipe mapping. */
13485 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13486 struct intel_connector *connector;
13487 bool plane;
13488
13489 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13490 crtc->base.base.id);
13491
13492 /* Pipe has the wrong plane attached and the plane is active.
13493 * Temporarily change the plane mapping and disable everything
13494 * ... */
13495 plane = crtc->plane;
13496 crtc->plane = !plane;
13497 crtc->primary_enabled = true;
13498 dev_priv->display.crtc_disable(&crtc->base);
13499 crtc->plane = plane;
13500
13501 /* ... and break all links. */
13502 for_each_intel_connector(dev, connector) {
13503 if (connector->encoder->base.crtc != &crtc->base)
13504 continue;
13505
13506 connector->base.dpms = DRM_MODE_DPMS_OFF;
13507 connector->base.encoder = NULL;
13508 }
13509 /* multiple connectors may have the same encoder:
13510 * handle them and break crtc link separately */
13511 for_each_intel_connector(dev, connector)
13512 if (connector->encoder->base.crtc == &crtc->base) {
13513 connector->encoder->base.crtc = NULL;
13514 connector->encoder->connectors_active = false;
13515 }
13516
13517 WARN_ON(crtc->active);
13518 crtc->base.state->enable = false;
13519 crtc->base.enabled = false;
13520 }
13521
13522 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13523 crtc->pipe == PIPE_A && !crtc->active) {
13524 /* BIOS forgot to enable pipe A, this mostly happens after
13525 * resume. Force-enable the pipe to fix this, the update_dpms
13526 * call below we restore the pipe to the right state, but leave
13527 * the required bits on. */
13528 intel_enable_pipe_a(dev);
13529 }
13530
13531 /* Adjust the state of the output pipe according to whether we
13532 * have active connectors/encoders. */
13533 intel_crtc_update_dpms(&crtc->base);
13534
13535 if (crtc->active != crtc->base.state->enable) {
13536 struct intel_encoder *encoder;
13537
13538 /* This can happen either due to bugs in the get_hw_state
13539 * functions or because the pipe is force-enabled due to the
13540 * pipe A quirk. */
13541 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13542 crtc->base.base.id,
13543 crtc->base.state->enable ? "enabled" : "disabled",
13544 crtc->active ? "enabled" : "disabled");
13545
13546 crtc->base.state->enable = crtc->active;
13547 crtc->base.enabled = crtc->active;
13548
13549 /* Because we only establish the connector -> encoder ->
13550 * crtc links if something is active, this means the
13551 * crtc is now deactivated. Break the links. connector
13552 * -> encoder links are only establish when things are
13553 * actually up, hence no need to break them. */
13554 WARN_ON(crtc->active);
13555
13556 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13557 WARN_ON(encoder->connectors_active);
13558 encoder->base.crtc = NULL;
13559 }
13560 }
13561
13562 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13563 /*
13564 * We start out with underrun reporting disabled to avoid races.
13565 * For correct bookkeeping mark this on active crtcs.
13566 *
13567 * Also on gmch platforms we dont have any hardware bits to
13568 * disable the underrun reporting. Which means we need to start
13569 * out with underrun reporting disabled also on inactive pipes,
13570 * since otherwise we'll complain about the garbage we read when
13571 * e.g. coming up after runtime pm.
13572 *
13573 * No protection against concurrent access is required - at
13574 * worst a fifo underrun happens which also sets this to false.
13575 */
13576 crtc->cpu_fifo_underrun_disabled = true;
13577 crtc->pch_fifo_underrun_disabled = true;
13578 }
13579}
13580
13581static void intel_sanitize_encoder(struct intel_encoder *encoder)
13582{
13583 struct intel_connector *connector;
13584 struct drm_device *dev = encoder->base.dev;
13585
13586 /* We need to check both for a crtc link (meaning that the
13587 * encoder is active and trying to read from a pipe) and the
13588 * pipe itself being active. */
13589 bool has_active_crtc = encoder->base.crtc &&
13590 to_intel_crtc(encoder->base.crtc)->active;
13591
13592 if (encoder->connectors_active && !has_active_crtc) {
13593 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13594 encoder->base.base.id,
13595 encoder->base.name);
13596
13597 /* Connector is active, but has no active pipe. This is
13598 * fallout from our resume register restoring. Disable
13599 * the encoder manually again. */
13600 if (encoder->base.crtc) {
13601 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13602 encoder->base.base.id,
13603 encoder->base.name);
13604 encoder->disable(encoder);
13605 if (encoder->post_disable)
13606 encoder->post_disable(encoder);
13607 }
13608 encoder->base.crtc = NULL;
13609 encoder->connectors_active = false;
13610
13611 /* Inconsistent output/port/pipe state happens presumably due to
13612 * a bug in one of the get_hw_state functions. Or someplace else
13613 * in our code, like the register restore mess on resume. Clamp
13614 * things to off as a safer default. */
13615 for_each_intel_connector(dev, connector) {
13616 if (connector->encoder != encoder)
13617 continue;
13618 connector->base.dpms = DRM_MODE_DPMS_OFF;
13619 connector->base.encoder = NULL;
13620 }
13621 }
13622 /* Enabled encoders without active connectors will be fixed in
13623 * the crtc fixup. */
13624}
13625
13626void i915_redisable_vga_power_on(struct drm_device *dev)
13627{
13628 struct drm_i915_private *dev_priv = dev->dev_private;
13629 u32 vga_reg = i915_vgacntrl_reg(dev);
13630
13631 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13632 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13633 i915_disable_vga(dev);
13634 }
13635}
13636
13637void i915_redisable_vga(struct drm_device *dev)
13638{
13639 struct drm_i915_private *dev_priv = dev->dev_private;
13640
13641 /* This function can be called both from intel_modeset_setup_hw_state or
13642 * at a very early point in our resume sequence, where the power well
13643 * structures are not yet restored. Since this function is at a very
13644 * paranoid "someone might have enabled VGA while we were not looking"
13645 * level, just check if the power well is enabled instead of trying to
13646 * follow the "don't touch the power well if we don't need it" policy
13647 * the rest of the driver uses. */
13648 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13649 return;
13650
13651 i915_redisable_vga_power_on(dev);
13652}
13653
13654static bool primary_get_hw_state(struct intel_crtc *crtc)
13655{
13656 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13657
13658 if (!crtc->active)
13659 return false;
13660
13661 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13662}
13663
13664static void intel_modeset_readout_hw_state(struct drm_device *dev)
13665{
13666 struct drm_i915_private *dev_priv = dev->dev_private;
13667 enum pipe pipe;
13668 struct intel_crtc *crtc;
13669 struct intel_encoder *encoder;
13670 struct intel_connector *connector;
13671 int i;
13672
13673 for_each_intel_crtc(dev, crtc) {
13674 memset(crtc->config, 0, sizeof(*crtc->config));
13675
13676 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13677
13678 crtc->active = dev_priv->display.get_pipe_config(crtc,
13679 crtc->config);
13680
13681 crtc->base.state->enable = crtc->active;
13682 crtc->base.enabled = crtc->active;
13683 crtc->primary_enabled = primary_get_hw_state(crtc);
13684
13685 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13686 crtc->base.base.id,
13687 crtc->active ? "enabled" : "disabled");
13688 }
13689
13690 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13691 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13692
13693 pll->on = pll->get_hw_state(dev_priv, pll,
13694 &pll->config.hw_state);
13695 pll->active = 0;
13696 pll->config.crtc_mask = 0;
13697 for_each_intel_crtc(dev, crtc) {
13698 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13699 pll->active++;
13700 pll->config.crtc_mask |= 1 << crtc->pipe;
13701 }
13702 }
13703
13704 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13705 pll->name, pll->config.crtc_mask, pll->on);
13706
13707 if (pll->config.crtc_mask)
13708 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13709 }
13710
13711 for_each_intel_encoder(dev, encoder) {
13712 pipe = 0;
13713
13714 if (encoder->get_hw_state(encoder, &pipe)) {
13715 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13716 encoder->base.crtc = &crtc->base;
13717 encoder->get_config(encoder, crtc->config);
13718 } else {
13719 encoder->base.crtc = NULL;
13720 }
13721
13722 encoder->connectors_active = false;
13723 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13724 encoder->base.base.id,
13725 encoder->base.name,
13726 encoder->base.crtc ? "enabled" : "disabled",
13727 pipe_name(pipe));
13728 }
13729
13730 for_each_intel_connector(dev, connector) {
13731 if (connector->get_hw_state(connector)) {
13732 connector->base.dpms = DRM_MODE_DPMS_ON;
13733 connector->encoder->connectors_active = true;
13734 connector->base.encoder = &connector->encoder->base;
13735 } else {
13736 connector->base.dpms = DRM_MODE_DPMS_OFF;
13737 connector->base.encoder = NULL;
13738 }
13739 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13740 connector->base.base.id,
13741 connector->base.name,
13742 connector->base.encoder ? "enabled" : "disabled");
13743 }
13744}
13745
13746/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13747 * and i915 state tracking structures. */
13748void intel_modeset_setup_hw_state(struct drm_device *dev,
13749 bool force_restore)
13750{
13751 struct drm_i915_private *dev_priv = dev->dev_private;
13752 enum pipe pipe;
13753 struct intel_crtc *crtc;
13754 struct intel_encoder *encoder;
13755 int i;
13756
13757 intel_modeset_readout_hw_state(dev);
13758
13759 /*
13760 * Now that we have the config, copy it to each CRTC struct
13761 * Note that this could go away if we move to using crtc_config
13762 * checking everywhere.
13763 */
13764 for_each_intel_crtc(dev, crtc) {
13765 if (crtc->active && i915.fastboot) {
13766 intel_mode_from_pipe_config(&crtc->base.mode,
13767 crtc->config);
13768 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13769 crtc->base.base.id);
13770 drm_mode_debug_printmodeline(&crtc->base.mode);
13771 }
13772 }
13773
13774 /* HW state is read out, now we need to sanitize this mess. */
13775 for_each_intel_encoder(dev, encoder) {
13776 intel_sanitize_encoder(encoder);
13777 }
13778
13779 for_each_pipe(dev_priv, pipe) {
13780 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13781 intel_sanitize_crtc(crtc);
13782 intel_dump_pipe_config(crtc, crtc->config,
13783 "[setup_hw_state]");
13784 }
13785
13786 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13787 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13788
13789 if (!pll->on || pll->active)
13790 continue;
13791
13792 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13793
13794 pll->disable(dev_priv, pll);
13795 pll->on = false;
13796 }
13797
13798 if (IS_GEN9(dev))
13799 skl_wm_get_hw_state(dev);
13800 else if (HAS_PCH_SPLIT(dev))
13801 ilk_wm_get_hw_state(dev);
13802
13803 if (force_restore) {
13804 i915_redisable_vga(dev);
13805
13806 /*
13807 * We need to use raw interfaces for restoring state to avoid
13808 * checking (bogus) intermediate states.
13809 */
13810 for_each_pipe(dev_priv, pipe) {
13811 struct drm_crtc *crtc =
13812 dev_priv->pipe_to_crtc_mapping[pipe];
13813
13814 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13815 crtc->primary->fb);
13816 }
13817 } else {
13818 intel_modeset_update_staged_output_state(dev);
13819 }
13820
13821 intel_modeset_check_state(dev);
13822}
13823
13824void intel_modeset_gem_init(struct drm_device *dev)
13825{
13826 struct drm_i915_private *dev_priv = dev->dev_private;
13827 struct drm_crtc *c;
13828 struct drm_i915_gem_object *obj;
13829
13830 mutex_lock(&dev->struct_mutex);
13831 intel_init_gt_powersave(dev);
13832 mutex_unlock(&dev->struct_mutex);
13833
13834 /*
13835 * There may be no VBT; and if the BIOS enabled SSC we can
13836 * just keep using it to avoid unnecessary flicker. Whereas if the
13837 * BIOS isn't using it, don't assume it will work even if the VBT
13838 * indicates as much.
13839 */
13840 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13841 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13842 DREF_SSC1_ENABLE);
13843
13844 intel_modeset_init_hw(dev);
13845
13846 intel_setup_overlay(dev);
13847
13848 /*
13849 * Make sure any fbs we allocated at startup are properly
13850 * pinned & fenced. When we do the allocation it's too early
13851 * for this.
13852 */
13853 mutex_lock(&dev->struct_mutex);
13854 for_each_crtc(dev, c) {
13855 obj = intel_fb_obj(c->primary->fb);
13856 if (obj == NULL)
13857 continue;
13858
13859 if (intel_pin_and_fence_fb_obj(c->primary,
13860 c->primary->fb,
13861 NULL)) {
13862 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13863 to_intel_crtc(c)->pipe);
13864 drm_framebuffer_unreference(c->primary->fb);
13865 c->primary->fb = NULL;
13866 update_state_fb(c->primary);
13867 }
13868 }
13869 mutex_unlock(&dev->struct_mutex);
13870
13871 intel_backlight_register(dev);
13872}
13873
13874void intel_connector_unregister(struct intel_connector *intel_connector)
13875{
13876 struct drm_connector *connector = &intel_connector->base;
13877
13878 intel_panel_destroy_backlight(connector);
13879 drm_connector_unregister(connector);
13880}
13881
13882void intel_modeset_cleanup(struct drm_device *dev)
13883{
13884 struct drm_i915_private *dev_priv = dev->dev_private;
13885 struct drm_connector *connector;
13886
13887 intel_disable_gt_powersave(dev);
13888
13889 intel_backlight_unregister(dev);
13890
13891 /*
13892 * Interrupts and polling as the first thing to avoid creating havoc.
13893 * Too much stuff here (turning of connectors, ...) would
13894 * experience fancy races otherwise.
13895 */
13896 intel_irq_uninstall(dev_priv);
13897
13898 /*
13899 * Due to the hpd irq storm handling the hotplug work can re-arm the
13900 * poll handlers. Hence disable polling after hpd handling is shut down.
13901 */
13902 drm_kms_helper_poll_fini(dev);
13903
13904 mutex_lock(&dev->struct_mutex);
13905
13906 intel_unregister_dsm_handler();
13907
13908 intel_fbc_disable(dev);
13909
13910 mutex_unlock(&dev->struct_mutex);
13911
13912 /* flush any delayed tasks or pending work */
13913 flush_scheduled_work();
13914
13915 /* destroy the backlight and sysfs files before encoders/connectors */
13916 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13917 struct intel_connector *intel_connector;
13918
13919 intel_connector = to_intel_connector(connector);
13920 intel_connector->unregister(intel_connector);
13921 }
13922
13923 drm_mode_config_cleanup(dev);
13924
13925 intel_cleanup_overlay(dev);
13926
13927 mutex_lock(&dev->struct_mutex);
13928 intel_cleanup_gt_powersave(dev);
13929 mutex_unlock(&dev->struct_mutex);
13930}
13931
13932/*
13933 * Return which encoder is currently attached for connector.
13934 */
13935struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13936{
13937 return &intel_attached_encoder(connector)->base;
13938}
13939
13940void intel_connector_attach_encoder(struct intel_connector *connector,
13941 struct intel_encoder *encoder)
13942{
13943 connector->encoder = encoder;
13944 drm_mode_connector_attach_encoder(&connector->base,
13945 &encoder->base);
13946}
13947
13948/*
13949 * set vga decode state - true == enable VGA decode
13950 */
13951int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13952{
13953 struct drm_i915_private *dev_priv = dev->dev_private;
13954 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13955 u16 gmch_ctrl;
13956
13957 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13958 DRM_ERROR("failed to read control word\n");
13959 return -EIO;
13960 }
13961
13962 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13963 return 0;
13964
13965 if (state)
13966 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13967 else
13968 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13969
13970 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13971 DRM_ERROR("failed to write control word\n");
13972 return -EIO;
13973 }
13974
13975 return 0;
13976}
13977
13978struct intel_display_error_state {
13979
13980 u32 power_well_driver;
13981
13982 int num_transcoders;
13983
13984 struct intel_cursor_error_state {
13985 u32 control;
13986 u32 position;
13987 u32 base;
13988 u32 size;
13989 } cursor[I915_MAX_PIPES];
13990
13991 struct intel_pipe_error_state {
13992 bool power_domain_on;
13993 u32 source;
13994 u32 stat;
13995 } pipe[I915_MAX_PIPES];
13996
13997 struct intel_plane_error_state {
13998 u32 control;
13999 u32 stride;
14000 u32 size;
14001 u32 pos;
14002 u32 addr;
14003 u32 surface;
14004 u32 tile_offset;
14005 } plane[I915_MAX_PIPES];
14006
14007 struct intel_transcoder_error_state {
14008 bool power_domain_on;
14009 enum transcoder cpu_transcoder;
14010
14011 u32 conf;
14012
14013 u32 htotal;
14014 u32 hblank;
14015 u32 hsync;
14016 u32 vtotal;
14017 u32 vblank;
14018 u32 vsync;
14019 } transcoder[4];
14020};
14021
14022struct intel_display_error_state *
14023intel_display_capture_error_state(struct drm_device *dev)
14024{
14025 struct drm_i915_private *dev_priv = dev->dev_private;
14026 struct intel_display_error_state *error;
14027 int transcoders[] = {
14028 TRANSCODER_A,
14029 TRANSCODER_B,
14030 TRANSCODER_C,
14031 TRANSCODER_EDP,
14032 };
14033 int i;
14034
14035 if (INTEL_INFO(dev)->num_pipes == 0)
14036 return NULL;
14037
14038 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14039 if (error == NULL)
14040 return NULL;
14041
14042 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14043 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14044
14045 for_each_pipe(dev_priv, i) {
14046 error->pipe[i].power_domain_on =
14047 __intel_display_power_is_enabled(dev_priv,
14048 POWER_DOMAIN_PIPE(i));
14049 if (!error->pipe[i].power_domain_on)
14050 continue;
14051
14052 error->cursor[i].control = I915_READ(CURCNTR(i));
14053 error->cursor[i].position = I915_READ(CURPOS(i));
14054 error->cursor[i].base = I915_READ(CURBASE(i));
14055
14056 error->plane[i].control = I915_READ(DSPCNTR(i));
14057 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14058 if (INTEL_INFO(dev)->gen <= 3) {
14059 error->plane[i].size = I915_READ(DSPSIZE(i));
14060 error->plane[i].pos = I915_READ(DSPPOS(i));
14061 }
14062 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14063 error->plane[i].addr = I915_READ(DSPADDR(i));
14064 if (INTEL_INFO(dev)->gen >= 4) {
14065 error->plane[i].surface = I915_READ(DSPSURF(i));
14066 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14067 }
14068
14069 error->pipe[i].source = I915_READ(PIPESRC(i));
14070
14071 if (HAS_GMCH_DISPLAY(dev))
14072 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14073 }
14074
14075 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14076 if (HAS_DDI(dev_priv->dev))
14077 error->num_transcoders++; /* Account for eDP. */
14078
14079 for (i = 0; i < error->num_transcoders; i++) {
14080 enum transcoder cpu_transcoder = transcoders[i];
14081
14082 error->transcoder[i].power_domain_on =
14083 __intel_display_power_is_enabled(dev_priv,
14084 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14085 if (!error->transcoder[i].power_domain_on)
14086 continue;
14087
14088 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14089
14090 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14091 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14092 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14093 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14094 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14095 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14096 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14097 }
14098
14099 return error;
14100}
14101
14102#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14103
14104void
14105intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14106 struct drm_device *dev,
14107 struct intel_display_error_state *error)
14108{
14109 struct drm_i915_private *dev_priv = dev->dev_private;
14110 int i;
14111
14112 if (!error)
14113 return;
14114
14115 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14116 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14117 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14118 error->power_well_driver);
14119 for_each_pipe(dev_priv, i) {
14120 err_printf(m, "Pipe [%d]:\n", i);
14121 err_printf(m, " Power: %s\n",
14122 error->pipe[i].power_domain_on ? "on" : "off");
14123 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14124 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14125
14126 err_printf(m, "Plane [%d]:\n", i);
14127 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14128 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14129 if (INTEL_INFO(dev)->gen <= 3) {
14130 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14131 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14132 }
14133 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14134 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14135 if (INTEL_INFO(dev)->gen >= 4) {
14136 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14137 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14138 }
14139
14140 err_printf(m, "Cursor [%d]:\n", i);
14141 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14142 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14143 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14144 }
14145
14146 for (i = 0; i < error->num_transcoders; i++) {
14147 err_printf(m, "CPU transcoder: %c\n",
14148 transcoder_name(error->transcoder[i].cpu_transcoder));
14149 err_printf(m, " Power: %s\n",
14150 error->transcoder[i].power_domain_on ? "on" : "off");
14151 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14152 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14153 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14154 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14155 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14156 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14157 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14158 }
14159}
14160
14161void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14162{
14163 struct intel_crtc *crtc;
14164
14165 for_each_intel_crtc(dev, crtc) {
14166 struct intel_unpin_work *work;
14167
14168 spin_lock_irq(&dev->event_lock);
14169
14170 work = crtc->unpin_work;
14171
14172 if (work && work->event &&
14173 work->event->base.file_priv == file) {
14174 kfree(work->event);
14175 work->event = NULL;
14176 }
14177
14178 spin_unlock_irq(&dev->event_lock);
14179 }
14180}
Linux kernel - Deliverables
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