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drm/i915: register backlight device also when backlight class is a module
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
42#include <linux/dma_remapping.h>
43
44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45static void intel_increase_pllclock(struct drm_crtc *crtc);
46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
57typedef struct {
58 int min, max;
59} intel_range_t;
60
61typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64} intel_p2_t;
65
66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
70};
71
72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
90}
91
92static const intel_limit_t intel_limits_i8xx_dac = {
93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
103};
104
105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
118static const intel_limit_t intel_limits_i8xx_lvds = {
119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
129};
130
131static const intel_limit_t intel_limits_i9xx_sdvo = {
132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
155};
156
157
158static const intel_limit_t intel_limits_g4x_sdvo = {
159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
170 },
171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
197 },
198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
211 },
212};
213
214static const intel_limit_t intel_limits_pineview_sdvo = {
215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
217 /* Pineview's Ncounter is a ring counter */
218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
220 /* Pineview only has one combined m divider, which we treat as m2. */
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
227};
228
229static const intel_limit_t intel_limits_pineview_lvds = {
230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
240};
241
242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
247static const intel_limit_t intel_limits_ironlake_dac = {
248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
258};
259
260static const intel_limit_t intel_limits_ironlake_single_lvds = {
261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
284};
285
286/* LVDS 100mhz refclk limits. */
287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
308 .p1 = { .min = 2, .max = 6 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
311};
312
313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 1, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
337};
338
339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
341{
342 struct drm_device *dev = crtc->dev;
343 const intel_limit_t *limit;
344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
346 if (intel_is_dual_link_lvds(dev)) {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
352 if (refclk == 100000)
353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
357 } else
358 limit = &intel_limits_ironlake_dac;
359
360 return limit;
361}
362
363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 if (intel_is_dual_link_lvds(dev))
370 limit = &intel_limits_g4x_dual_channel_lvds;
371 else
372 limit = &intel_limits_g4x_single_channel_lvds;
373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
375 limit = &intel_limits_g4x_hdmi;
376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
377 limit = &intel_limits_g4x_sdvo;
378 } else /* The option is for other outputs */
379 limit = &intel_limits_i9xx_sdvo;
380
381 return limit;
382}
383
384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
389 if (HAS_PCH_SPLIT(dev))
390 limit = intel_ironlake_limit(crtc, refclk);
391 else if (IS_G4X(dev)) {
392 limit = intel_g4x_limit(crtc);
393 } else if (IS_PINEVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
395 limit = &intel_limits_pineview_lvds;
396 else
397 limit = &intel_limits_pineview_sdvo;
398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else
402 limit = &intel_limits_vlv_hdmi;
403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
410 limit = &intel_limits_i8xx_lvds;
411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
412 limit = &intel_limits_i8xx_dvo;
413 else
414 limit = &intel_limits_i8xx_dac;
415 }
416 return limit;
417}
418
419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
421{
422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
433static void i9xx_clock(int refclk, intel_clock_t *clock)
434{
435 clock->m = i9xx_dpll_compute_m(clock);
436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
445{
446 struct drm_device *dev = crtc->dev;
447 struct intel_encoder *encoder;
448
449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
451 return true;
452
453 return false;
454}
455
456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
465{
466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
467 INTELPllInvalid("p1 out of range\n");
468 if (clock->p < limit->p.min || limit->p.max < clock->p)
469 INTELPllInvalid("p out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
475 INTELPllInvalid("m1 <= m2\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 if (clock->n < limit->n.min || limit->n.max < clock->n)
479 INTELPllInvalid("n out of range\n");
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
487
488 return true;
489}
490
491static bool
492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
495{
496 struct drm_device *dev = crtc->dev;
497 intel_clock_t clock;
498 int err = target;
499
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
501 /*
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
505 */
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
517 memset(best_clock, 0, sizeof(*best_clock));
518
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
529 int this_err;
530
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
556{
557 struct drm_device *dev = crtc->dev;
558 intel_clock_t clock;
559 int err = target;
560
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
562 /*
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
566 */
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
578 memset(best_clock, 0, sizeof(*best_clock));
579
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
588 int this_err;
589
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
593 continue;
594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
611static bool
612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
615{
616 struct drm_device *dev = crtc->dev;
617 intel_clock_t clock;
618 int max_n;
619 bool found;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
652 continue;
653
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
665 return found;
666}
667
668static bool
669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
679 flag = 0;
680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
735
736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
751}
752
753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
759 return intel_crtc->config.cpu_transcoder;
760}
761
762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 int pipestat_reg = PIPESTAT(pipe);
785
786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
807 /* Wait for vblank interrupt bit to set */
808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
829 *
830 */
831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
836
837 if (INTEL_INFO(dev)->gen >= 4) {
838 int reg = PIPECONF(cpu_transcoder);
839
840 /* Wait for the Pipe State to go off */
841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
843 WARN(1, "pipe_off wait timed out\n");
844 } else {
845 u32 last_line, line_mask;
846 int reg = PIPEDSL(pipe);
847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
854 /* Wait for the display line to settle */
855 do {
856 last_line = I915_READ(reg) & line_mask;
857 mdelay(5);
858 } while (((I915_READ(reg) & line_mask) != last_line) &&
859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
861 WARN(1, "pipe_off wait timed out\n");
862 }
863}
864
865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
930
931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
949struct intel_shared_dpll *
950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
954 if (crtc->config.shared_dpll < 0)
955 return NULL;
956
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
958}
959
960/* For ILK+ */
961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
964{
965 bool cur_state;
966 struct intel_dpll_hw_state hw_state;
967
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
973 if (WARN (!pll,
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
975 return;
976
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
981}
982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
991
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1038 return;
1039
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047{
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058}
1059
1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
1066 bool locked = true;
1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1086 pipe_name(pipe));
1087}
1088
1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1111{
1112 int reg;
1113 u32 val;
1114 bool cur_state;
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
1117
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1134}
1135
1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1138{
1139 int reg;
1140 u32 val;
1141 bool cur_state;
1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1149}
1150
1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
1157 struct drm_device *dev = dev_priv->dev;
1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
1169 return;
1170 }
1171
1172 /* Need to check both planes against the pipe */
1173 for_each_pipe(i) {
1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1181 }
1182}
1183
1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
1187 struct drm_device *dev = dev_priv->dev;
1188 int reg, i;
1189 u32 val;
1190
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1211 }
1212}
1213
1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
1243}
1244
1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
1266 if ((val & SDVO_ENABLE) == 0)
1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271 return false;
1272 } else {
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1312{
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1317
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1330
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
1341
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356 pipe_name(pipe));
1357
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361}
1362
1363static void vlv_enable_pll(struct intel_crtc *crtc)
1364{
1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
1369
1370 assert_pipe_disabled(dev_priv, crtc->pipe);
1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1377 assert_panel_unlocked(dev_priv, crtc->pipe);
1378
1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
1388
1389 /* We do this three times for luck */
1390 I915_WRITE(reg, dpll);
1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
1393 I915_WRITE(reg, dpll);
1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
1396 I915_WRITE(reg, dpll);
1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
1401static void i9xx_enable_pll(struct intel_crtc *crtc)
1402{
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1407
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1409
1410 /* No really, not for ILK+ */
1411 BUG_ON(dev_priv->info->gen >= 5);
1412
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1416
1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
1434
1435 /* We do this three times for luck */
1436 I915_WRITE(reg, dpll);
1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
1439 I915_WRITE(reg, dpll);
1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
1442 I915_WRITE(reg, dpll);
1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
1448 * i9xx_disable_pll - disable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1457{
1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
1467}
1468
1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
1483/**
1484 * ironlake_enable_shared_dpll - enable PCH PLL
1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1492{
1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1495
1496 /* PCH PLLs only available on ILK, SNB and IVB */
1497 BUG_ON(dev_priv->info->gen < 5);
1498 if (WARN_ON(pll == NULL))
1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
1503
1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
1506 crtc->base.base.id);
1507
1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
1510 assert_shared_dpll_enabled(dev_priv, pll);
1511 return;
1512 }
1513 WARN_ON(pll->on);
1514
1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1516 pll->enable(dev_priv, pll);
1517 pll->on = true;
1518}
1519
1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1521{
1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1524
1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
1527 if (WARN_ON(pll == NULL))
1528 return;
1529
1530 if (WARN_ON(pll->refcount == 0))
1531 return;
1532
1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
1535 crtc->base.base.id);
1536
1537 if (WARN_ON(pll->active == 0)) {
1538 assert_shared_dpll_disabled(dev_priv, pll);
1539 return;
1540 }
1541
1542 assert_shared_dpll_enabled(dev_priv, pll);
1543 WARN_ON(!pll->on);
1544 if (--pll->active)
1545 return;
1546
1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1548 pll->disable(dev_priv, pll);
1549 pll->on = false;
1550}
1551
1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
1554{
1555 struct drm_device *dev = dev_priv->dev;
1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1558 uint32_t reg, val, pipeconf_val;
1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
1564 assert_shared_dpll_enabled(dev_priv,
1565 intel_crtc_to_shared_dpll(intel_crtc));
1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
1578 }
1579
1580 reg = PCH_TRANSCONF(pipe);
1581 val = I915_READ(reg);
1582 pipeconf_val = I915_READ(PIPECONF(pipe));
1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
1591 }
1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1606}
1607
1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1609 enum transcoder cpu_transcoder)
1610{
1611 u32 val, pipeconf_val;
1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
1616 /* FDI must be feeding us bits for PCH ports */
1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1619
1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
1625 val = TRANS_ENABLE;
1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1627
1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
1630 val |= TRANS_INTERLACED;
1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1636 DRM_ERROR("Failed to enable PCH transcoder\n");
1637}
1638
1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
1641{
1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
1652 reg = PCH_TRANSCONF(pipe);
1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
1667}
1668
1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1670{
1671 u32 val;
1672
1673 val = I915_READ(LPT_TRANSCONF);
1674 val &= ~TRANS_ENABLE;
1675 I915_WRITE(LPT_TRANSCONF, val);
1676 /* wait for PCH transcoder off, transcoder state */
1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1678 DRM_ERROR("Failed to disable PCH transcoder\n");
1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1683 I915_WRITE(_TRANSA_CHICKEN2, val);
1684}
1685
1686/**
1687 * intel_enable_pipe - enable a pipe, asserting requirements
1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1701 bool pch_port, bool dsi)
1702{
1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1705 enum pipe pch_transcoder;
1706 int reg;
1707 u32 val;
1708
1709 assert_planes_disabled(dev_priv, pipe);
1710 assert_cursor_disabled(dev_priv, pipe);
1711 assert_sprites_disabled(dev_priv, pipe);
1712
1713 if (HAS_PCH_LPT(dev_priv->dev))
1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
1737
1738 reg = PIPECONF(cpu_transcoder);
1739 val = I915_READ(reg);
1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
1748 * intel_disable_pipe - disable a pipe, asserting requirements
1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
1772 assert_cursor_disabled(dev_priv, pipe);
1773 assert_sprites_disabled(dev_priv, pipe);
1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
1779 reg = PIPECONF(cpu_transcoder);
1780 val = I915_READ(reg);
1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1793 enum plane plane)
1794{
1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1799}
1800
1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1824 intel_flush_display_plane(dev_priv, plane);
1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
1861int
1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
1863 struct drm_i915_gem_object *obj,
1864 struct intel_ring_buffer *pipelined)
1865{
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 u32 alignment;
1868 int ret;
1869
1870 switch (obj->tiling_mode) {
1871 case I915_TILING_NONE:
1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
1874 else if (INTEL_INFO(dev)->gen >= 4)
1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
1901 dev_priv->mm.interruptible = false;
1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1903 if (ret)
1904 goto err_interruptible;
1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
1911 ret = i915_gem_object_get_fence(obj);
1912 if (ret)
1913 goto err_unpin;
1914
1915 i915_gem_object_pin_fence(obj);
1916
1917 dev_priv->mm.interruptible = true;
1918 return 0;
1919
1920err_unpin:
1921 i915_gem_object_unpin_from_display_plane(obj);
1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
1924 return ret;
1925}
1926
1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
1930 i915_gem_object_unpin_from_display_plane(obj);
1931}
1932
1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
1939{
1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
1942
1943 tile_rows = *y / 8;
1944 *y %= 8;
1945
1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
1958}
1959
1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
1969 unsigned long linear_offset;
1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
1984
1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
1996 break;
1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
2015 break;
2016 default:
2017 BUG();
2018 }
2019
2020 if (INTEL_INFO(dev)->gen >= 4) {
2021 if (obj->tiling_mode != I915_TILING_NONE)
2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
2030 I915_WRITE(reg, dspcntr);
2031
2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2033
2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
2041 intel_crtc->dspaddr_offset = linear_offset;
2042 }
2043
2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
2053 } else
2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2055 POSTING_READ(reg);
2056
2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
2069 unsigned long linear_offset;
2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
2076 case 2:
2077 break;
2078 default:
2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
2096 break;
2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
2112 break;
2113 default:
2114 BUG();
2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2126
2127 I915_WRITE(reg, dspcntr);
2128
2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2130 intel_crtc->dspaddr_offset =
2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
2134 linear_offset -= intel_crtc->dspaddr_offset;
2135
2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160
2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
2163 intel_increase_pllclock(crtc);
2164
2165 return dev_priv->display.update_plane(crtc, fb, x, y);
2166}
2167
2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
2256static int
2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2258 struct drm_framebuffer *fb)
2259{
2260 struct drm_device *dev = crtc->dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263 struct drm_framebuffer *old_fb;
2264 int ret;
2265
2266 /* no fb bound */
2267 if (!fb) {
2268 DRM_ERROR("No FB bound\n");
2269 return 0;
2270 }
2271
2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
2276 return -EINVAL;
2277 }
2278
2279 mutex_lock(&dev->struct_mutex);
2280 ret = intel_pin_and_fence_fb_obj(dev,
2281 to_intel_framebuffer(fb)->obj,
2282 NULL);
2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
2285 DRM_ERROR("pin & fence failed\n");
2286 return ret;
2287 }
2288
2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2304 if (ret) {
2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2306 mutex_unlock(&dev->struct_mutex);
2307 DRM_ERROR("failed to update base address\n");
2308 return ret;
2309 }
2310
2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
2313 crtc->x = x;
2314 crtc->y = y;
2315
2316 if (old_fb) {
2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2320 }
2321
2322 intel_update_fbc(dev);
2323 intel_edp_psr_update(dev);
2324 mutex_unlock(&dev->struct_mutex);
2325
2326 intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328 return 0;
2329}
2330
2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
2342 if (IS_IVYBRIDGE(dev)) {
2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348 }
2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
2370}
2371
2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
2410 int plane = intel_crtc->plane;
2411 u32 reg, temp, tries;
2412
2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
2425 udelay(150);
2426
2427 /* enable CPU FDI TX and PCH FDI RX */
2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
2443 udelay(150);
2444
2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450 reg = FDI_RX_IIR(pipe);
2451 for (tries = 0; tries < 5; tries++) {
2452 temp = I915_READ(reg);
2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458 break;
2459 }
2460 }
2461 if (tries == 5)
2462 DRM_ERROR("FDI train 1 fail!\n");
2463
2464 /* Train 2 */
2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2470
2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
2478 udelay(150);
2479
2480 reg = FDI_RX_IIR(pipe);
2481 for (tries = 0; tries < 5; tries++) {
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
2490 }
2491 if (tries == 5)
2492 DRM_ERROR("FDI train 2 fail!\n");
2493
2494 DRM_DEBUG_KMS("FDI train done\n");
2495
2496}
2497
2498static const int snb_b_fdi_train_param[] = {
2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
2512 u32 reg, temp, i, retry;
2513
2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
2523 udelay(150);
2524
2525 /* enable CPU FDI TX and PCH FDI RX */
2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
2552 udelay(150);
2553
2554 for (i = 0; i < 4; i++) {
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
2562 udelay(500);
2563
2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
2574 }
2575 if (retry < 5)
2576 break;
2577 }
2578 if (i == 4)
2579 DRM_ERROR("FDI train 1 fail!\n");
2580
2581 /* Train 2 */
2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
2591 I915_WRITE(reg, temp);
2592
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
2605 udelay(150);
2606
2607 for (i = 0; i < 4; i++) {
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
2615 udelay(500);
2616
2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
2627 }
2628 if (retry < 5)
2629 break;
2630 }
2631 if (i == 4)
2632 DRM_ERROR("FDI train 2 fail!\n");
2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i, j;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
2668
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
2675
2676 /* enable CPU FDI TX and PCH FDI RX */
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2686
2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2689
2690 reg = FDI_RX_CTL(pipe);
2691 temp = I915_READ(reg);
2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2695
2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
2698
2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
2717
2718 /* Train 2 */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
2732 udelay(2); /* should be 1.5us */
2733
2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2738
2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
2747 }
2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2750 }
2751
2752train_done:
2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2757{
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763
2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
2780 udelay(200);
2781
2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2787
2788 POSTING_READ(reg);
2789 udelay(100);
2790 }
2791}
2792
2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2848 }
2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 unsigned long flags;
2881 bool pending;
2882
2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
2896 struct drm_device *dev = crtc->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
2910}
2911
2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
2921 mutex_lock(&dev_priv->dpio_lock);
2922
2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2935 if (clock == 20000) {
2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
2950 desired_divisor = (iclk_virtual_root_freq / clock);
2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2966 clock,
2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2981
2982 /* Program SSCAUXDIV */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2987
2988 /* Enable modulator and associated divider */
2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2990 temp &= ~SBI_SSCCTL_DISABLE;
2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997
2998 mutex_unlock(&dev_priv->dpio_lock);
2999}
3000
3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
3039 u32 reg, temp;
3040
3041 assert_pch_transcoder_disabled(dev_priv, pipe);
3042
3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
3048 /* For PCH output, training FDI link */
3049 dev_priv->display.fdi_link_train(crtc);
3050
3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
3053 if (HAS_PCH_CPT(dev)) {
3054 u32 sel;
3055
3056 temp = I915_READ(PCH_DPLL_SEL);
3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3060 temp |= sel;
3061 else
3062 temp &= ~sel;
3063 I915_WRITE(PCH_DPLL_SEL, temp);
3064 }
3065
3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3078
3079 intel_fdi_normal_train(crtc);
3080
3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
3093 temp |= bpc << 9; /* same format but at 11:9 */
3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
3102 temp |= TRANS_DP_PORT_SEL_B;
3103 break;
3104 case PCH_DP_C:
3105 temp |= TRANS_DP_PORT_SEL_C;
3106 break;
3107 case PCH_DP_D:
3108 temp |= TRANS_DP_PORT_SEL_D;
3109 break;
3110 default:
3111 BUG();
3112 }
3113
3114 I915_WRITE(reg, temp);
3115 }
3116
3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
3118}
3119
3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3126
3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3128
3129 lpt_program_iclkip(crtc);
3130
3131 /* Set transcoder timing. */
3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3133
3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3135}
3136
3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
3138{
3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
3145 WARN(1, "bad %s refcount\n", pll->name);
3146 return;
3147 }
3148
3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3155}
3156
3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3158{
3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
3162
3163 if (pll) {
3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
3166 intel_put_shared_dpll(crtc);
3167 }
3168
3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171 i = (enum intel_dpll_id) crtc->pipe;
3172 pll = &dev_priv->shared_dplls[i];
3173
3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
3176
3177 goto found;
3178 }
3179
3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3190 crtc->base.base.id,
3191 pll->name, pll->refcount, pll->active);
3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
3200 if (pll->refcount == 0) {
3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
3210 crtc->config.shared_dpll = i;
3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
3213
3214 if (pll->active == 0) {
3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3219 WARN_ON(pll->on);
3220 assert_shared_dpll_disabled(dev_priv, pll);
3221
3222 pll->mode_set(dev_priv, pll);
3223 }
3224 pll->refcount++;
3225
3226 return pll;
3227}
3228
3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 int dslreg = PIPEDSL(pipe);
3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3238 if (wait_for(I915_READ(dslreg) != temp, 5))
3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3240 }
3241}
3242
3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
3249 if (crtc->config.pch_pfit.size) {
3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3261 }
3262}
3263
3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
3286static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 struct intel_encoder *encoder;
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
3294
3295 WARN_ON(!crtc->enabled);
3296
3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
3305 for_each_encoder_on_crtc(dev, crtc, encoder)
3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
3308
3309 if (intel_crtc->config.has_pch_encoder) {
3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3312 * enabling. */
3313 ironlake_fdi_pll_enable(intel_crtc);
3314 } else {
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3317 }
3318
3319 ironlake_pfit_enable(intel_crtc);
3320
3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
3327 intel_update_watermarks(crtc);
3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder, false);
3330 intel_enable_plane(dev_priv, plane, pipe);
3331 intel_enable_planes(crtc);
3332 intel_crtc_update_cursor(crtc, true);
3333
3334 if (intel_crtc->config.has_pch_encoder)
3335 ironlake_pch_enable(crtc);
3336
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3340
3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
3343
3344 if (HAS_PCH_CPT(dev))
3345 cpt_verify_modeset(dev, intel_crtc->pipe);
3346
3347 /*
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3353 * happening.
3354 */
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
3356}
3357
3358/* IPS only exists on ULT machines and is tied to pipe A. */
3359static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360{
3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3362}
3363
3364static void hsw_enable_ips(struct intel_crtc *crtc)
3365{
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368 if (!crtc->config.ips_enabled)
3369 return;
3370
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3377}
3378
3379static void hsw_disable_ips(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 if (!crtc->config.ips_enabled)
3385 return;
3386
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389
3390 /* We need to wait for a vblank before we can disable the plane. */
3391 intel_wait_for_vblank(dev, crtc->pipe);
3392}
3393
3394static void haswell_crtc_enable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
3409
3410 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411 if (intel_crtc->config.has_pch_encoder)
3412 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
3414 if (intel_crtc->config.has_pch_encoder)
3415 dev_priv->display.fdi_link_train(crtc);
3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 if (encoder->pre_enable)
3419 encoder->pre_enable(encoder);
3420
3421 intel_ddi_enable_pipe_clock(intel_crtc);
3422
3423 ironlake_pfit_enable(intel_crtc);
3424
3425 /*
3426 * On ILK+ LUT must be loaded before the pipe is running but with
3427 * clocks enabled
3428 */
3429 intel_crtc_load_lut(crtc);
3430
3431 intel_ddi_set_pipe_settings(crtc);
3432 intel_ddi_enable_transcoder_func(crtc);
3433
3434 intel_update_watermarks(crtc);
3435 intel_enable_pipe(dev_priv, pipe,
3436 intel_crtc->config.has_pch_encoder, false);
3437 intel_enable_plane(dev_priv, plane, pipe);
3438 intel_enable_planes(crtc);
3439 intel_crtc_update_cursor(crtc, true);
3440
3441 hsw_enable_ips(intel_crtc);
3442
3443 if (intel_crtc->config.has_pch_encoder)
3444 lpt_pch_enable(crtc);
3445
3446 mutex_lock(&dev->struct_mutex);
3447 intel_update_fbc(dev);
3448 mutex_unlock(&dev->struct_mutex);
3449
3450 for_each_encoder_on_crtc(dev, crtc, encoder) {
3451 encoder->enable(encoder);
3452 intel_opregion_notify_encoder(encoder, true);
3453 }
3454
3455 /*
3456 * There seems to be a race in PCH platform hw (at least on some
3457 * outputs) where an enabled pipe still completes any pageflip right
3458 * away (as if the pipe is off) instead of waiting for vblank. As soon
3459 * as the first vblank happend, everything works as expected. Hence just
3460 * wait for one vblank before returning to avoid strange things
3461 * happening.
3462 */
3463 intel_wait_for_vblank(dev, intel_crtc->pipe);
3464}
3465
3466static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467{
3468 struct drm_device *dev = crtc->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 int pipe = crtc->pipe;
3471
3472 /* To avoid upsetting the power well on haswell only disable the pfit if
3473 * it's in use. The hw state code will make sure we get this right. */
3474 if (crtc->config.pch_pfit.size) {
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_POS(pipe), 0);
3477 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478 }
3479}
3480
3481static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482{
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3486 struct intel_encoder *encoder;
3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
3489 u32 reg, temp;
3490
3491
3492 if (!intel_crtc->active)
3493 return;
3494
3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->disable(encoder);
3497
3498 intel_crtc_wait_for_pending_flips(crtc);
3499 drm_vblank_off(dev, pipe);
3500
3501 if (dev_priv->fbc.plane == plane)
3502 intel_disable_fbc(dev);
3503
3504 intel_crtc_update_cursor(crtc, false);
3505 intel_disable_planes(crtc);
3506 intel_disable_plane(dev_priv, plane, pipe);
3507
3508 if (intel_crtc->config.has_pch_encoder)
3509 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
3511 intel_disable_pipe(dev_priv, pipe);
3512
3513 ironlake_pfit_disable(intel_crtc);
3514
3515 for_each_encoder_on_crtc(dev, crtc, encoder)
3516 if (encoder->post_disable)
3517 encoder->post_disable(encoder);
3518
3519 if (intel_crtc->config.has_pch_encoder) {
3520 ironlake_fdi_disable(crtc);
3521
3522 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3524
3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530 TRANS_DP_PORT_SEL_MASK);
3531 temp |= TRANS_DP_PORT_SEL_NONE;
3532 I915_WRITE(reg, temp);
3533
3534 /* disable DPLL_SEL */
3535 temp = I915_READ(PCH_DPLL_SEL);
3536 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3537 I915_WRITE(PCH_DPLL_SEL, temp);
3538 }
3539
3540 /* disable PCH DPLL */
3541 intel_disable_shared_dpll(intel_crtc);
3542
3543 ironlake_fdi_pll_disable(intel_crtc);
3544 }
3545
3546 intel_crtc->active = false;
3547 intel_update_watermarks(crtc);
3548
3549 mutex_lock(&dev->struct_mutex);
3550 intel_update_fbc(dev);
3551 mutex_unlock(&dev->struct_mutex);
3552}
3553
3554static void haswell_crtc_disable(struct drm_crtc *crtc)
3555{
3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
3562 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3563
3564 if (!intel_crtc->active)
3565 return;
3566
3567 for_each_encoder_on_crtc(dev, crtc, encoder) {
3568 intel_opregion_notify_encoder(encoder, false);
3569 encoder->disable(encoder);
3570 }
3571
3572 intel_crtc_wait_for_pending_flips(crtc);
3573 drm_vblank_off(dev, pipe);
3574
3575 /* FBC must be disabled before disabling the plane on HSW. */
3576 if (dev_priv->fbc.plane == plane)
3577 intel_disable_fbc(dev);
3578
3579 hsw_disable_ips(intel_crtc);
3580
3581 intel_crtc_update_cursor(crtc, false);
3582 intel_disable_planes(crtc);
3583 intel_disable_plane(dev_priv, plane, pipe);
3584
3585 if (intel_crtc->config.has_pch_encoder)
3586 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3587 intel_disable_pipe(dev_priv, pipe);
3588
3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3590
3591 ironlake_pfit_disable(intel_crtc);
3592
3593 intel_ddi_disable_pipe_clock(intel_crtc);
3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
3599 if (intel_crtc->config.has_pch_encoder) {
3600 lpt_disable_pch_transcoder(dev_priv);
3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3602 intel_ddi_fdi_disable(crtc);
3603 }
3604
3605 intel_crtc->active = false;
3606 intel_update_watermarks(crtc);
3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 intel_put_shared_dpll(intel_crtc);
3617}
3618
3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
3621 intel_ddi_put_crtc_pll(crtc);
3622}
3623
3624static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625{
3626 if (!enable && intel_crtc->overlay) {
3627 struct drm_device *dev = intel_crtc->base.dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629
3630 mutex_lock(&dev->struct_mutex);
3631 dev_priv->mm.interruptible = false;
3632 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633 dev_priv->mm.interruptible = true;
3634 mutex_unlock(&dev->struct_mutex);
3635 }
3636
3637 /* Let userspace switch the overlay on again. In most cases userspace
3638 * has to recompute where to put it anyway.
3639 */
3640}
3641
3642/**
3643 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644 * cursor plane briefly if not already running after enabling the display
3645 * plane.
3646 * This workaround avoids occasional blank screens when self refresh is
3647 * enabled.
3648 */
3649static void
3650g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651{
3652 u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654 if ((cntl & CURSOR_MODE) == 0) {
3655 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659 intel_wait_for_vblank(dev_priv->dev, pipe);
3660 I915_WRITE(CURCNTR(pipe), cntl);
3661 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663 }
3664}
3665
3666static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc_config *pipe_config = &crtc->config;
3671
3672 if (!crtc->config.gmch_pfit.control)
3673 return;
3674
3675 /*
3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
3678 */
3679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680 assert_pipe_disabled(dev_priv, crtc->pipe);
3681
3682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3684
3685 /* Border color in case we don't scale up to the full screen. Black by
3686 * default, change to something else for debugging. */
3687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3688}
3689
3690static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691{
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
3698 bool is_dsi;
3699
3700 WARN_ON(!crtc->enabled);
3701
3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_pll_enable)
3709 encoder->pre_pll_enable(encoder);
3710
3711 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
3713 if (!is_dsi)
3714 vlv_enable_pll(intel_crtc);
3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_enable)
3718 encoder->pre_enable(encoder);
3719
3720 i9xx_pfit_enable(intel_crtc);
3721
3722 intel_crtc_load_lut(crtc);
3723
3724 intel_update_watermarks(crtc);
3725 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3726 intel_enable_plane(dev_priv, plane, pipe);
3727 intel_enable_planes(crtc);
3728 intel_crtc_update_cursor(crtc, true);
3729
3730 intel_update_fbc(dev);
3731
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
3734}
3735
3736static void i9xx_crtc_enable(struct drm_crtc *crtc)
3737{
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 struct intel_encoder *encoder;
3742 int pipe = intel_crtc->pipe;
3743 int plane = intel_crtc->plane;
3744
3745 WARN_ON(!crtc->enabled);
3746
3747 if (intel_crtc->active)
3748 return;
3749
3750 intel_crtc->active = true;
3751
3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 if (encoder->pre_enable)
3754 encoder->pre_enable(encoder);
3755
3756 i9xx_enable_pll(intel_crtc);
3757
3758 i9xx_pfit_enable(intel_crtc);
3759
3760 intel_crtc_load_lut(crtc);
3761
3762 intel_update_watermarks(crtc);
3763 intel_enable_pipe(dev_priv, pipe, false, false);
3764 intel_enable_plane(dev_priv, plane, pipe);
3765 intel_enable_planes(crtc);
3766 /* The fixup needs to happen before cursor is enabled */
3767 if (IS_G4X(dev))
3768 g4x_fixup_plane(dev_priv, pipe);
3769 intel_crtc_update_cursor(crtc, true);
3770
3771 /* Give the overlay scaler a chance to enable if it's on this pipe */
3772 intel_crtc_dpms_overlay(intel_crtc, true);
3773
3774 intel_update_fbc(dev);
3775
3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
3778}
3779
3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784
3785 if (!crtc->config.gmch_pfit.control)
3786 return;
3787
3788 assert_pipe_disabled(dev_priv, crtc->pipe);
3789
3790 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791 I915_READ(PFIT_CONTROL));
3792 I915_WRITE(PFIT_CONTROL, 0);
3793}
3794
3795static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800 struct intel_encoder *encoder;
3801 int pipe = intel_crtc->pipe;
3802 int plane = intel_crtc->plane;
3803
3804 if (!intel_crtc->active)
3805 return;
3806
3807 for_each_encoder_on_crtc(dev, crtc, encoder)
3808 encoder->disable(encoder);
3809
3810 /* Give the overlay scaler a chance to disable if it's on this pipe */
3811 intel_crtc_wait_for_pending_flips(crtc);
3812 drm_vblank_off(dev, pipe);
3813
3814 if (dev_priv->fbc.plane == plane)
3815 intel_disable_fbc(dev);
3816
3817 intel_crtc_dpms_overlay(intel_crtc, false);
3818 intel_crtc_update_cursor(crtc, false);
3819 intel_disable_planes(crtc);
3820 intel_disable_plane(dev_priv, plane, pipe);
3821
3822 intel_disable_pipe(dev_priv, pipe);
3823
3824 i9xx_pfit_disable(intel_crtc);
3825
3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 if (encoder->post_disable)
3828 encoder->post_disable(encoder);
3829
3830 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831 i9xx_disable_pll(dev_priv, pipe);
3832
3833 intel_crtc->active = false;
3834 intel_update_watermarks(crtc);
3835
3836 intel_update_fbc(dev);
3837}
3838
3839static void i9xx_crtc_off(struct drm_crtc *crtc)
3840{
3841}
3842
3843static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844 bool enabled)
3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_master_private *master_priv;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
3850
3851 if (!dev->primary->master)
3852 return;
3853
3854 master_priv = dev->primary->master->driver_priv;
3855 if (!master_priv->sarea_priv)
3856 return;
3857
3858 switch (pipe) {
3859 case 0:
3860 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862 break;
3863 case 1:
3864 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866 break;
3867 default:
3868 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3869 break;
3870 }
3871}
3872
3873/**
3874 * Sets the power management mode of the pipe and plane.
3875 */
3876void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_encoder *intel_encoder;
3881 bool enable = false;
3882
3883 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884 enable |= intel_encoder->connectors_active;
3885
3886 if (enable)
3887 dev_priv->display.crtc_enable(crtc);
3888 else
3889 dev_priv->display.crtc_disable(crtc);
3890
3891 intel_crtc_update_sarea(crtc, enable);
3892}
3893
3894static void intel_crtc_disable(struct drm_crtc *crtc)
3895{
3896 struct drm_device *dev = crtc->dev;
3897 struct drm_connector *connector;
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3900
3901 /* crtc should still be enabled when we disable it. */
3902 WARN_ON(!crtc->enabled);
3903
3904 dev_priv->display.crtc_disable(crtc);
3905 intel_crtc->eld_vld = false;
3906 intel_crtc_update_sarea(crtc, false);
3907 dev_priv->display.off(crtc);
3908
3909 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3910 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3916 mutex_unlock(&dev->struct_mutex);
3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
3930 }
3931}
3932
3933void intel_encoder_destroy(struct drm_encoder *encoder)
3934{
3935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3936
3937 drm_encoder_cleanup(encoder);
3938 kfree(intel_encoder);
3939}
3940
3941/* Simple dpms helper for encoders with just one connector, no cloning and only
3942 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943 * state of the entire output pipe. */
3944static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3945{
3946 if (mode == DRM_MODE_DPMS_ON) {
3947 encoder->connectors_active = true;
3948
3949 intel_crtc_update_dpms(encoder->base.crtc);
3950 } else {
3951 encoder->connectors_active = false;
3952
3953 intel_crtc_update_dpms(encoder->base.crtc);
3954 }
3955}
3956
3957/* Cross check the actual hw state with our own modeset state tracking (and it's
3958 * internal consistency). */
3959static void intel_connector_check_state(struct intel_connector *connector)
3960{
3961 if (connector->get_hw_state(connector)) {
3962 struct intel_encoder *encoder = connector->encoder;
3963 struct drm_crtc *crtc;
3964 bool encoder_enabled;
3965 enum pipe pipe;
3966
3967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968 connector->base.base.id,
3969 drm_get_connector_name(&connector->base));
3970
3971 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972 "wrong connector dpms state\n");
3973 WARN(connector->base.encoder != &encoder->base,
3974 "active connector not linked to encoder\n");
3975 WARN(!encoder->connectors_active,
3976 "encoder->connectors_active not set\n");
3977
3978 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979 WARN(!encoder_enabled, "encoder not enabled\n");
3980 if (WARN_ON(!encoder->base.crtc))
3981 return;
3982
3983 crtc = encoder->base.crtc;
3984
3985 WARN(!crtc->enabled, "crtc not enabled\n");
3986 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988 "encoder active on the wrong pipe\n");
3989 }
3990}
3991
3992/* Even simpler default implementation, if there's really no special case to
3993 * consider. */
3994void intel_connector_dpms(struct drm_connector *connector, int mode)
3995{
3996 struct intel_encoder *encoder = intel_attached_encoder(connector);
3997
3998 /* All the simple cases only support two dpms states. */
3999 if (mode != DRM_MODE_DPMS_ON)
4000 mode = DRM_MODE_DPMS_OFF;
4001
4002 if (mode == connector->dpms)
4003 return;
4004
4005 connector->dpms = mode;
4006
4007 /* Only need to change hw state when actually enabled */
4008 if (encoder->base.crtc)
4009 intel_encoder_dpms(encoder, mode);
4010 else
4011 WARN_ON(encoder->connectors_active != false);
4012
4013 intel_modeset_check_state(connector->dev);
4014}
4015
4016/* Simple connector->get_hw_state implementation for encoders that support only
4017 * one connector and no cloning and hence the encoder state determines the state
4018 * of the connector. */
4019bool intel_connector_get_hw_state(struct intel_connector *connector)
4020{
4021 enum pipe pipe = 0;
4022 struct intel_encoder *encoder = connector->encoder;
4023
4024 return encoder->get_hw_state(encoder, &pipe);
4025}
4026
4027static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028 struct intel_crtc_config *pipe_config)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *pipe_B_crtc =
4032 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 if (pipe_config->fdi_lanes > 4) {
4037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038 pipe_name(pipe), pipe_config->fdi_lanes);
4039 return false;
4040 }
4041
4042 if (IS_HASWELL(dev)) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045 pipe_config->fdi_lanes);
4046 return false;
4047 } else {
4048 return true;
4049 }
4050 }
4051
4052 if (INTEL_INFO(dev)->num_pipes == 2)
4053 return true;
4054
4055 /* Ivybridge 3 pipe is really complicated */
4056 switch (pipe) {
4057 case PIPE_A:
4058 return true;
4059 case PIPE_B:
4060 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061 pipe_config->fdi_lanes > 2) {
4062 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063 pipe_name(pipe), pipe_config->fdi_lanes);
4064 return false;
4065 }
4066 return true;
4067 case PIPE_C:
4068 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4069 pipe_B_crtc->config.fdi_lanes <= 2) {
4070 if (pipe_config->fdi_lanes > 2) {
4071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072 pipe_name(pipe), pipe_config->fdi_lanes);
4073 return false;
4074 }
4075 } else {
4076 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077 return false;
4078 }
4079 return true;
4080 default:
4081 BUG();
4082 }
4083}
4084
4085#define RETRY 1
4086static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087 struct intel_crtc_config *pipe_config)
4088{
4089 struct drm_device *dev = intel_crtc->base.dev;
4090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4091 int lane, link_bw, fdi_dotclock;
4092 bool setup_ok, needs_recompute = false;
4093
4094retry:
4095 /* FDI is a binary signal running at ~2.7GHz, encoding
4096 * each output octet as 10 bits. The actual frequency
4097 * is stored as a divider into a 100MHz clock, and the
4098 * mode pixel clock is stored in units of 1KHz.
4099 * Hence the bw of each lane in terms of the mode signal
4100 * is:
4101 */
4102 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
4104 fdi_dotclock = adjusted_mode->clock;
4105
4106 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4107 pipe_config->pipe_bpp);
4108
4109 pipe_config->fdi_lanes = lane;
4110
4111 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4112 link_bw, &pipe_config->fdi_m_n);
4113
4114 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115 intel_crtc->pipe, pipe_config);
4116 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117 pipe_config->pipe_bpp -= 2*3;
4118 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119 pipe_config->pipe_bpp);
4120 needs_recompute = true;
4121 pipe_config->bw_constrained = true;
4122
4123 goto retry;
4124 }
4125
4126 if (needs_recompute)
4127 return RETRY;
4128
4129 return setup_ok ? 0 : -EINVAL;
4130}
4131
4132static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133 struct intel_crtc_config *pipe_config)
4134{
4135 pipe_config->ips_enabled = i915_enable_ips &&
4136 hsw_crtc_supports_ips(crtc) &&
4137 pipe_config->pipe_bpp <= 24;
4138}
4139
4140static int intel_crtc_compute_config(struct intel_crtc *crtc,
4141 struct intel_crtc_config *pipe_config)
4142{
4143 struct drm_device *dev = crtc->base.dev;
4144 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4145
4146 /* FIXME should check pixel clock limits on all platforms */
4147 if (INTEL_INFO(dev)->gen < 4) {
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 int clock_limit =
4150 dev_priv->display.get_display_clock_speed(dev);
4151
4152 /*
4153 * Enable pixel doubling when the dot clock
4154 * is > 90% of the (display) core speed.
4155 *
4156 * GDG double wide on either pipe,
4157 * otherwise pipe A only.
4158 */
4159 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4160 adjusted_mode->clock > clock_limit * 9 / 10) {
4161 clock_limit *= 2;
4162 pipe_config->double_wide = true;
4163 }
4164
4165 if (adjusted_mode->clock > clock_limit * 9 / 10)
4166 return -EINVAL;
4167 }
4168
4169 /*
4170 * Pipe horizontal size must be even in:
4171 * - DVO ganged mode
4172 * - LVDS dual channel mode
4173 * - Double wide pipe
4174 */
4175 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4176 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4177 pipe_config->pipe_src_w &= ~1;
4178
4179 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4180 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4181 */
4182 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4183 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4184 return -EINVAL;
4185
4186 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4187 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4188 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4189 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4190 * for lvds. */
4191 pipe_config->pipe_bpp = 8*3;
4192 }
4193
4194 if (HAS_IPS(dev))
4195 hsw_compute_ips_config(crtc, pipe_config);
4196
4197 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4198 * clock survives for now. */
4199 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4200 pipe_config->shared_dpll = crtc->config.shared_dpll;
4201
4202 if (pipe_config->has_pch_encoder)
4203 return ironlake_fdi_compute_config(crtc, pipe_config);
4204
4205 return 0;
4206}
4207
4208static int valleyview_get_display_clock_speed(struct drm_device *dev)
4209{
4210 return 400000; /* FIXME */
4211}
4212
4213static int i945_get_display_clock_speed(struct drm_device *dev)
4214{
4215 return 400000;
4216}
4217
4218static int i915_get_display_clock_speed(struct drm_device *dev)
4219{
4220 return 333000;
4221}
4222
4223static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4224{
4225 return 200000;
4226}
4227
4228static int pnv_get_display_clock_speed(struct drm_device *dev)
4229{
4230 u16 gcfgc = 0;
4231
4232 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4233
4234 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4235 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4236 return 267000;
4237 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4238 return 333000;
4239 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4240 return 444000;
4241 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4242 return 200000;
4243 default:
4244 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4245 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4246 return 133000;
4247 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4248 return 167000;
4249 }
4250}
4251
4252static int i915gm_get_display_clock_speed(struct drm_device *dev)
4253{
4254 u16 gcfgc = 0;
4255
4256 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4257
4258 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4259 return 133000;
4260 else {
4261 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4262 case GC_DISPLAY_CLOCK_333_MHZ:
4263 return 333000;
4264 default:
4265 case GC_DISPLAY_CLOCK_190_200_MHZ:
4266 return 190000;
4267 }
4268 }
4269}
4270
4271static int i865_get_display_clock_speed(struct drm_device *dev)
4272{
4273 return 266000;
4274}
4275
4276static int i855_get_display_clock_speed(struct drm_device *dev)
4277{
4278 u16 hpllcc = 0;
4279 /* Assume that the hardware is in the high speed state. This
4280 * should be the default.
4281 */
4282 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4283 case GC_CLOCK_133_200:
4284 case GC_CLOCK_100_200:
4285 return 200000;
4286 case GC_CLOCK_166_250:
4287 return 250000;
4288 case GC_CLOCK_100_133:
4289 return 133000;
4290 }
4291
4292 /* Shouldn't happen */
4293 return 0;
4294}
4295
4296static int i830_get_display_clock_speed(struct drm_device *dev)
4297{
4298 return 133000;
4299}
4300
4301static void
4302intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4303{
4304 while (*num > DATA_LINK_M_N_MASK ||
4305 *den > DATA_LINK_M_N_MASK) {
4306 *num >>= 1;
4307 *den >>= 1;
4308 }
4309}
4310
4311static void compute_m_n(unsigned int m, unsigned int n,
4312 uint32_t *ret_m, uint32_t *ret_n)
4313{
4314 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4315 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4316 intel_reduce_m_n_ratio(ret_m, ret_n);
4317}
4318
4319void
4320intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4321 int pixel_clock, int link_clock,
4322 struct intel_link_m_n *m_n)
4323{
4324 m_n->tu = 64;
4325
4326 compute_m_n(bits_per_pixel * pixel_clock,
4327 link_clock * nlanes * 8,
4328 &m_n->gmch_m, &m_n->gmch_n);
4329
4330 compute_m_n(pixel_clock, link_clock,
4331 &m_n->link_m, &m_n->link_n);
4332}
4333
4334static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4335{
4336 if (i915_panel_use_ssc >= 0)
4337 return i915_panel_use_ssc != 0;
4338 return dev_priv->vbt.lvds_use_ssc
4339 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4340}
4341
4342static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4343{
4344 struct drm_device *dev = crtc->dev;
4345 struct drm_i915_private *dev_priv = dev->dev_private;
4346 int refclk;
4347
4348 if (IS_VALLEYVIEW(dev)) {
4349 refclk = 100000;
4350 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4351 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4352 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4353 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4354 refclk / 1000);
4355 } else if (!IS_GEN2(dev)) {
4356 refclk = 96000;
4357 } else {
4358 refclk = 48000;
4359 }
4360
4361 return refclk;
4362}
4363
4364static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4365{
4366 return (1 << dpll->n) << 16 | dpll->m2;
4367}
4368
4369static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4370{
4371 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4372}
4373
4374static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4375 intel_clock_t *reduced_clock)
4376{
4377 struct drm_device *dev = crtc->base.dev;
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 int pipe = crtc->pipe;
4380 u32 fp, fp2 = 0;
4381
4382 if (IS_PINEVIEW(dev)) {
4383 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4384 if (reduced_clock)
4385 fp2 = pnv_dpll_compute_fp(reduced_clock);
4386 } else {
4387 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4388 if (reduced_clock)
4389 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4390 }
4391
4392 I915_WRITE(FP0(pipe), fp);
4393 crtc->config.dpll_hw_state.fp0 = fp;
4394
4395 crtc->lowfreq_avail = false;
4396 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4397 reduced_clock && i915_powersave) {
4398 I915_WRITE(FP1(pipe), fp2);
4399 crtc->config.dpll_hw_state.fp1 = fp2;
4400 crtc->lowfreq_avail = true;
4401 } else {
4402 I915_WRITE(FP1(pipe), fp);
4403 crtc->config.dpll_hw_state.fp1 = fp;
4404 }
4405}
4406
4407static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4408 pipe)
4409{
4410 u32 reg_val;
4411
4412 /*
4413 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4414 * and set it to a reasonable value instead.
4415 */
4416 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4417 reg_val &= 0xffffff00;
4418 reg_val |= 0x00000030;
4419 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4420
4421 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4422 reg_val &= 0x8cffffff;
4423 reg_val = 0x8c000000;
4424 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4425
4426 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4427 reg_val &= 0xffffff00;
4428 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4429
4430 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4431 reg_val &= 0x00ffffff;
4432 reg_val |= 0xb0000000;
4433 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4434}
4435
4436static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4437 struct intel_link_m_n *m_n)
4438{
4439 struct drm_device *dev = crtc->base.dev;
4440 struct drm_i915_private *dev_priv = dev->dev_private;
4441 int pipe = crtc->pipe;
4442
4443 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4444 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4445 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4446 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4447}
4448
4449static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4450 struct intel_link_m_n *m_n)
4451{
4452 struct drm_device *dev = crtc->base.dev;
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454 int pipe = crtc->pipe;
4455 enum transcoder transcoder = crtc->config.cpu_transcoder;
4456
4457 if (INTEL_INFO(dev)->gen >= 5) {
4458 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4459 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4460 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4461 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4462 } else {
4463 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4464 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4465 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4466 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4467 }
4468}
4469
4470static void intel_dp_set_m_n(struct intel_crtc *crtc)
4471{
4472 if (crtc->config.has_pch_encoder)
4473 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4474 else
4475 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4476}
4477
4478static void vlv_update_pll(struct intel_crtc *crtc)
4479{
4480 struct drm_device *dev = crtc->base.dev;
4481 struct drm_i915_private *dev_priv = dev->dev_private;
4482 int pipe = crtc->pipe;
4483 u32 dpll, mdiv;
4484 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4485 u32 coreclk, reg_val, dpll_md;
4486
4487 mutex_lock(&dev_priv->dpio_lock);
4488
4489 bestn = crtc->config.dpll.n;
4490 bestm1 = crtc->config.dpll.m1;
4491 bestm2 = crtc->config.dpll.m2;
4492 bestp1 = crtc->config.dpll.p1;
4493 bestp2 = crtc->config.dpll.p2;
4494
4495 /* See eDP HDMI DPIO driver vbios notes doc */
4496
4497 /* PLL B needs special handling */
4498 if (pipe)
4499 vlv_pllb_recal_opamp(dev_priv, pipe);
4500
4501 /* Set up Tx target for periodic Rcomp update */
4502 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4503
4504 /* Disable target IRef on PLL */
4505 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4506 reg_val &= 0x00ffffff;
4507 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4508
4509 /* Disable fast lock */
4510 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4511
4512 /* Set idtafcrecal before PLL is enabled */
4513 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4514 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4515 mdiv |= ((bestn << DPIO_N_SHIFT));
4516 mdiv |= (1 << DPIO_K_SHIFT);
4517
4518 /*
4519 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4520 * but we don't support that).
4521 * Note: don't use the DAC post divider as it seems unstable.
4522 */
4523 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4524 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4525
4526 mdiv |= DPIO_ENABLE_CALIBRATION;
4527 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4528
4529 /* Set HBR and RBR LPF coefficients */
4530 if (crtc->config.port_clock == 162000 ||
4531 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4533 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4534 0x009f0003);
4535 else
4536 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4537 0x00d0000f);
4538
4539 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4540 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4541 /* Use SSC source */
4542 if (!pipe)
4543 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4544 0x0df40000);
4545 else
4546 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4547 0x0df70000);
4548 } else { /* HDMI or VGA */
4549 /* Use bend source */
4550 if (!pipe)
4551 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4552 0x0df70000);
4553 else
4554 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4555 0x0df40000);
4556 }
4557
4558 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4559 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4560 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4561 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4562 coreclk |= 0x01000000;
4563 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4564
4565 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4566
4567 /* Enable DPIO clock input */
4568 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4569 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4570 if (pipe)
4571 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4572
4573 dpll |= DPLL_VCO_ENABLE;
4574 crtc->config.dpll_hw_state.dpll = dpll;
4575
4576 dpll_md = (crtc->config.pixel_multiplier - 1)
4577 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4578 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4579
4580 if (crtc->config.has_dp_encoder)
4581 intel_dp_set_m_n(crtc);
4582
4583 mutex_unlock(&dev_priv->dpio_lock);
4584}
4585
4586static void i9xx_update_pll(struct intel_crtc *crtc,
4587 intel_clock_t *reduced_clock,
4588 int num_connectors)
4589{
4590 struct drm_device *dev = crtc->base.dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 u32 dpll;
4593 bool is_sdvo;
4594 struct dpll *clock = &crtc->config.dpll;
4595
4596 i9xx_update_pll_dividers(crtc, reduced_clock);
4597
4598 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4599 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4600
4601 dpll = DPLL_VGA_MODE_DIS;
4602
4603 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4604 dpll |= DPLLB_MODE_LVDS;
4605 else
4606 dpll |= DPLLB_MODE_DAC_SERIAL;
4607
4608 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4609 dpll |= (crtc->config.pixel_multiplier - 1)
4610 << SDVO_MULTIPLIER_SHIFT_HIRES;
4611 }
4612
4613 if (is_sdvo)
4614 dpll |= DPLL_SDVO_HIGH_SPEED;
4615
4616 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4617 dpll |= DPLL_SDVO_HIGH_SPEED;
4618
4619 /* compute bitmask from p1 value */
4620 if (IS_PINEVIEW(dev))
4621 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4622 else {
4623 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4624 if (IS_G4X(dev) && reduced_clock)
4625 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4626 }
4627 switch (clock->p2) {
4628 case 5:
4629 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4630 break;
4631 case 7:
4632 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4633 break;
4634 case 10:
4635 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4636 break;
4637 case 14:
4638 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4639 break;
4640 }
4641 if (INTEL_INFO(dev)->gen >= 4)
4642 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4643
4644 if (crtc->config.sdvo_tv_clock)
4645 dpll |= PLL_REF_INPUT_TVCLKINBC;
4646 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4647 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4648 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4649 else
4650 dpll |= PLL_REF_INPUT_DREFCLK;
4651
4652 dpll |= DPLL_VCO_ENABLE;
4653 crtc->config.dpll_hw_state.dpll = dpll;
4654
4655 if (INTEL_INFO(dev)->gen >= 4) {
4656 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4657 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4658 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4659 }
4660
4661 if (crtc->config.has_dp_encoder)
4662 intel_dp_set_m_n(crtc);
4663}
4664
4665static void i8xx_update_pll(struct intel_crtc *crtc,
4666 intel_clock_t *reduced_clock,
4667 int num_connectors)
4668{
4669 struct drm_device *dev = crtc->base.dev;
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671 u32 dpll;
4672 struct dpll *clock = &crtc->config.dpll;
4673
4674 i9xx_update_pll_dividers(crtc, reduced_clock);
4675
4676 dpll = DPLL_VGA_MODE_DIS;
4677
4678 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4679 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4680 } else {
4681 if (clock->p1 == 2)
4682 dpll |= PLL_P1_DIVIDE_BY_TWO;
4683 else
4684 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4685 if (clock->p2 == 4)
4686 dpll |= PLL_P2_DIVIDE_BY_4;
4687 }
4688
4689 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4690 dpll |= DPLL_DVO_2X_MODE;
4691
4692 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4693 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4694 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4695 else
4696 dpll |= PLL_REF_INPUT_DREFCLK;
4697
4698 dpll |= DPLL_VCO_ENABLE;
4699 crtc->config.dpll_hw_state.dpll = dpll;
4700}
4701
4702static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4703{
4704 struct drm_device *dev = intel_crtc->base.dev;
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706 enum pipe pipe = intel_crtc->pipe;
4707 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4708 struct drm_display_mode *adjusted_mode =
4709 &intel_crtc->config.adjusted_mode;
4710 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4711
4712 /* We need to be careful not to changed the adjusted mode, for otherwise
4713 * the hw state checker will get angry at the mismatch. */
4714 crtc_vtotal = adjusted_mode->crtc_vtotal;
4715 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4716
4717 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4718 /* the chip adds 2 halflines automatically */
4719 crtc_vtotal -= 1;
4720 crtc_vblank_end -= 1;
4721 vsyncshift = adjusted_mode->crtc_hsync_start
4722 - adjusted_mode->crtc_htotal / 2;
4723 } else {
4724 vsyncshift = 0;
4725 }
4726
4727 if (INTEL_INFO(dev)->gen > 3)
4728 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4729
4730 I915_WRITE(HTOTAL(cpu_transcoder),
4731 (adjusted_mode->crtc_hdisplay - 1) |
4732 ((adjusted_mode->crtc_htotal - 1) << 16));
4733 I915_WRITE(HBLANK(cpu_transcoder),
4734 (adjusted_mode->crtc_hblank_start - 1) |
4735 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4736 I915_WRITE(HSYNC(cpu_transcoder),
4737 (adjusted_mode->crtc_hsync_start - 1) |
4738 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4739
4740 I915_WRITE(VTOTAL(cpu_transcoder),
4741 (adjusted_mode->crtc_vdisplay - 1) |
4742 ((crtc_vtotal - 1) << 16));
4743 I915_WRITE(VBLANK(cpu_transcoder),
4744 (adjusted_mode->crtc_vblank_start - 1) |
4745 ((crtc_vblank_end - 1) << 16));
4746 I915_WRITE(VSYNC(cpu_transcoder),
4747 (adjusted_mode->crtc_vsync_start - 1) |
4748 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4749
4750 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4751 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4752 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4753 * bits. */
4754 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4755 (pipe == PIPE_B || pipe == PIPE_C))
4756 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4757
4758 /* pipesrc controls the size that is scaled from, which should
4759 * always be the user's requested size.
4760 */
4761 I915_WRITE(PIPESRC(pipe),
4762 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4763 (intel_crtc->config.pipe_src_h - 1));
4764}
4765
4766static void intel_get_pipe_timings(struct intel_crtc *crtc,
4767 struct intel_crtc_config *pipe_config)
4768{
4769 struct drm_device *dev = crtc->base.dev;
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4771 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4772 uint32_t tmp;
4773
4774 tmp = I915_READ(HTOTAL(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4777 tmp = I915_READ(HBLANK(cpu_transcoder));
4778 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4779 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4780 tmp = I915_READ(HSYNC(cpu_transcoder));
4781 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4782 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4783
4784 tmp = I915_READ(VTOTAL(cpu_transcoder));
4785 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4786 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4787 tmp = I915_READ(VBLANK(cpu_transcoder));
4788 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4789 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4790 tmp = I915_READ(VSYNC(cpu_transcoder));
4791 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4792 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4793
4794 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4795 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4796 pipe_config->adjusted_mode.crtc_vtotal += 1;
4797 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4798 }
4799
4800 tmp = I915_READ(PIPESRC(crtc->pipe));
4801 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4802 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4803
4804 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4805 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4806}
4807
4808static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4809 struct intel_crtc_config *pipe_config)
4810{
4811 struct drm_crtc *crtc = &intel_crtc->base;
4812
4813 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4814 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4815 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4816 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4817
4818 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4819 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4820 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4821 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4822
4823 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4824
4825 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4826 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4827}
4828
4829static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4830{
4831 struct drm_device *dev = intel_crtc->base.dev;
4832 struct drm_i915_private *dev_priv = dev->dev_private;
4833 uint32_t pipeconf;
4834
4835 pipeconf = 0;
4836
4837 if (intel_crtc->config.double_wide)
4838 pipeconf |= PIPECONF_DOUBLE_WIDE;
4839
4840 /* only g4x and later have fancy bpc/dither controls */
4841 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4842 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4843 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4844 pipeconf |= PIPECONF_DITHER_EN |
4845 PIPECONF_DITHER_TYPE_SP;
4846
4847 switch (intel_crtc->config.pipe_bpp) {
4848 case 18:
4849 pipeconf |= PIPECONF_6BPC;
4850 break;
4851 case 24:
4852 pipeconf |= PIPECONF_8BPC;
4853 break;
4854 case 30:
4855 pipeconf |= PIPECONF_10BPC;
4856 break;
4857 default:
4858 /* Case prevented by intel_choose_pipe_bpp_dither. */
4859 BUG();
4860 }
4861 }
4862
4863 if (HAS_PIPE_CXSR(dev)) {
4864 if (intel_crtc->lowfreq_avail) {
4865 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4866 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4867 } else {
4868 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4869 }
4870 }
4871
4872 if (!IS_GEN2(dev) &&
4873 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4874 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4875 else
4876 pipeconf |= PIPECONF_PROGRESSIVE;
4877
4878 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4879 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4880
4881 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4882 POSTING_READ(PIPECONF(intel_crtc->pipe));
4883}
4884
4885static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4886 int x, int y,
4887 struct drm_framebuffer *fb)
4888{
4889 struct drm_device *dev = crtc->dev;
4890 struct drm_i915_private *dev_priv = dev->dev_private;
4891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4892 int pipe = intel_crtc->pipe;
4893 int plane = intel_crtc->plane;
4894 int refclk, num_connectors = 0;
4895 intel_clock_t clock, reduced_clock;
4896 u32 dspcntr;
4897 bool ok, has_reduced_clock = false;
4898 bool is_lvds = false, is_dsi = false;
4899 struct intel_encoder *encoder;
4900 const intel_limit_t *limit;
4901 int ret;
4902
4903 for_each_encoder_on_crtc(dev, crtc, encoder) {
4904 switch (encoder->type) {
4905 case INTEL_OUTPUT_LVDS:
4906 is_lvds = true;
4907 break;
4908 case INTEL_OUTPUT_DSI:
4909 is_dsi = true;
4910 break;
4911 }
4912
4913 num_connectors++;
4914 }
4915
4916 refclk = i9xx_get_refclk(crtc, num_connectors);
4917
4918 if (!is_dsi && !intel_crtc->config.clock_set) {
4919 /*
4920 * Returns a set of divisors for the desired target clock with
4921 * the given refclk, or FALSE. The returned values represent
4922 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4923 * 2) / p1 / p2.
4924 */
4925 limit = intel_limit(crtc, refclk);
4926 ok = dev_priv->display.find_dpll(limit, crtc,
4927 intel_crtc->config.port_clock,
4928 refclk, NULL, &clock);
4929 if (!ok && !intel_crtc->config.clock_set) {
4930 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4931 return -EINVAL;
4932 }
4933 }
4934
4935 /* Ensure that the cursor is valid for the new mode before changing... */
4936 intel_crtc_update_cursor(crtc, true);
4937
4938 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
4939 /*
4940 * Ensure we match the reduced clock's P to the target clock.
4941 * If the clocks don't match, we can't switch the display clock
4942 * by using the FP0/FP1. In such case we will disable the LVDS
4943 * downclock feature.
4944 */
4945 limit = intel_limit(crtc, refclk);
4946 has_reduced_clock =
4947 dev_priv->display.find_dpll(limit, crtc,
4948 dev_priv->lvds_downclock,
4949 refclk, &clock,
4950 &reduced_clock);
4951 }
4952 /* Compat-code for transition, will disappear. */
4953 if (!intel_crtc->config.clock_set) {
4954 intel_crtc->config.dpll.n = clock.n;
4955 intel_crtc->config.dpll.m1 = clock.m1;
4956 intel_crtc->config.dpll.m2 = clock.m2;
4957 intel_crtc->config.dpll.p1 = clock.p1;
4958 intel_crtc->config.dpll.p2 = clock.p2;
4959 }
4960
4961 if (IS_GEN2(dev)) {
4962 i8xx_update_pll(intel_crtc,
4963 has_reduced_clock ? &reduced_clock : NULL,
4964 num_connectors);
4965 } else if (IS_VALLEYVIEW(dev)) {
4966 if (!is_dsi)
4967 vlv_update_pll(intel_crtc);
4968 } else {
4969 i9xx_update_pll(intel_crtc,
4970 has_reduced_clock ? &reduced_clock : NULL,
4971 num_connectors);
4972 }
4973
4974 /* Set up the display plane register */
4975 dspcntr = DISPPLANE_GAMMA_ENABLE;
4976
4977 if (!IS_VALLEYVIEW(dev)) {
4978 if (pipe == 0)
4979 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4980 else
4981 dspcntr |= DISPPLANE_SEL_PIPE_B;
4982 }
4983
4984 intel_set_pipe_timings(intel_crtc);
4985
4986 /* pipesrc and dspsize control the size that is scaled from,
4987 * which should always be the user's requested size.
4988 */
4989 I915_WRITE(DSPSIZE(plane),
4990 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4991 (intel_crtc->config.pipe_src_w - 1));
4992 I915_WRITE(DSPPOS(plane), 0);
4993
4994 i9xx_set_pipeconf(intel_crtc);
4995
4996 I915_WRITE(DSPCNTR(plane), dspcntr);
4997 POSTING_READ(DSPCNTR(plane));
4998
4999 ret = intel_pipe_set_base(crtc, x, y, fb);
5000
5001 return ret;
5002}
5003
5004static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5005 struct intel_crtc_config *pipe_config)
5006{
5007 struct drm_device *dev = crtc->base.dev;
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 uint32_t tmp;
5010
5011 tmp = I915_READ(PFIT_CONTROL);
5012 if (!(tmp & PFIT_ENABLE))
5013 return;
5014
5015 /* Check whether the pfit is attached to our pipe. */
5016 if (INTEL_INFO(dev)->gen < 4) {
5017 if (crtc->pipe != PIPE_B)
5018 return;
5019 } else {
5020 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5021 return;
5022 }
5023
5024 pipe_config->gmch_pfit.control = tmp;
5025 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5026 if (INTEL_INFO(dev)->gen < 5)
5027 pipe_config->gmch_pfit.lvds_border_bits =
5028 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5029}
5030
5031static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5032 struct intel_crtc_config *pipe_config)
5033{
5034 struct drm_device *dev = crtc->base.dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 uint32_t tmp;
5037
5038 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5039 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5040
5041 tmp = I915_READ(PIPECONF(crtc->pipe));
5042 if (!(tmp & PIPECONF_ENABLE))
5043 return false;
5044
5045 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5046 switch (tmp & PIPECONF_BPC_MASK) {
5047 case PIPECONF_6BPC:
5048 pipe_config->pipe_bpp = 18;
5049 break;
5050 case PIPECONF_8BPC:
5051 pipe_config->pipe_bpp = 24;
5052 break;
5053 case PIPECONF_10BPC:
5054 pipe_config->pipe_bpp = 30;
5055 break;
5056 default:
5057 break;
5058 }
5059 }
5060
5061 if (INTEL_INFO(dev)->gen < 4)
5062 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5063
5064 intel_get_pipe_timings(crtc, pipe_config);
5065
5066 i9xx_get_pfit_config(crtc, pipe_config);
5067
5068 if (INTEL_INFO(dev)->gen >= 4) {
5069 tmp = I915_READ(DPLL_MD(crtc->pipe));
5070 pipe_config->pixel_multiplier =
5071 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5072 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5073 pipe_config->dpll_hw_state.dpll_md = tmp;
5074 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5075 tmp = I915_READ(DPLL(crtc->pipe));
5076 pipe_config->pixel_multiplier =
5077 ((tmp & SDVO_MULTIPLIER_MASK)
5078 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5079 } else {
5080 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5081 * port and will be fixed up in the encoder->get_config
5082 * function. */
5083 pipe_config->pixel_multiplier = 1;
5084 }
5085 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5086 if (!IS_VALLEYVIEW(dev)) {
5087 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5088 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5089 } else {
5090 /* Mask out read-only status bits. */
5091 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5092 DPLL_PORTC_READY_MASK |
5093 DPLL_PORTB_READY_MASK);
5094 }
5095
5096 i9xx_crtc_clock_get(crtc, pipe_config);
5097
5098 return true;
5099}
5100
5101static void ironlake_init_pch_refclk(struct drm_device *dev)
5102{
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct drm_mode_config *mode_config = &dev->mode_config;
5105 struct intel_encoder *encoder;
5106 u32 val, final;
5107 bool has_lvds = false;
5108 bool has_cpu_edp = false;
5109 bool has_panel = false;
5110 bool has_ck505 = false;
5111 bool can_ssc = false;
5112
5113 /* We need to take the global config into account */
5114 list_for_each_entry(encoder, &mode_config->encoder_list,
5115 base.head) {
5116 switch (encoder->type) {
5117 case INTEL_OUTPUT_LVDS:
5118 has_panel = true;
5119 has_lvds = true;
5120 break;
5121 case INTEL_OUTPUT_EDP:
5122 has_panel = true;
5123 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5124 has_cpu_edp = true;
5125 break;
5126 }
5127 }
5128
5129 if (HAS_PCH_IBX(dev)) {
5130 has_ck505 = dev_priv->vbt.display_clock_mode;
5131 can_ssc = has_ck505;
5132 } else {
5133 has_ck505 = false;
5134 can_ssc = true;
5135 }
5136
5137 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5138 has_panel, has_lvds, has_ck505);
5139
5140 /* Ironlake: try to setup display ref clock before DPLL
5141 * enabling. This is only under driver's control after
5142 * PCH B stepping, previous chipset stepping should be
5143 * ignoring this setting.
5144 */
5145 val = I915_READ(PCH_DREF_CONTROL);
5146
5147 /* As we must carefully and slowly disable/enable each source in turn,
5148 * compute the final state we want first and check if we need to
5149 * make any changes at all.
5150 */
5151 final = val;
5152 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5153 if (has_ck505)
5154 final |= DREF_NONSPREAD_CK505_ENABLE;
5155 else
5156 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5157
5158 final &= ~DREF_SSC_SOURCE_MASK;
5159 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5160 final &= ~DREF_SSC1_ENABLE;
5161
5162 if (has_panel) {
5163 final |= DREF_SSC_SOURCE_ENABLE;
5164
5165 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5166 final |= DREF_SSC1_ENABLE;
5167
5168 if (has_cpu_edp) {
5169 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5170 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5171 else
5172 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5173 } else
5174 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5175 } else {
5176 final |= DREF_SSC_SOURCE_DISABLE;
5177 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5178 }
5179
5180 if (final == val)
5181 return;
5182
5183 /* Always enable nonspread source */
5184 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5185
5186 if (has_ck505)
5187 val |= DREF_NONSPREAD_CK505_ENABLE;
5188 else
5189 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5190
5191 if (has_panel) {
5192 val &= ~DREF_SSC_SOURCE_MASK;
5193 val |= DREF_SSC_SOURCE_ENABLE;
5194
5195 /* SSC must be turned on before enabling the CPU output */
5196 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5197 DRM_DEBUG_KMS("Using SSC on panel\n");
5198 val |= DREF_SSC1_ENABLE;
5199 } else
5200 val &= ~DREF_SSC1_ENABLE;
5201
5202 /* Get SSC going before enabling the outputs */
5203 I915_WRITE(PCH_DREF_CONTROL, val);
5204 POSTING_READ(PCH_DREF_CONTROL);
5205 udelay(200);
5206
5207 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5208
5209 /* Enable CPU source on CPU attached eDP */
5210 if (has_cpu_edp) {
5211 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5212 DRM_DEBUG_KMS("Using SSC on eDP\n");
5213 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5214 }
5215 else
5216 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5217 } else
5218 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5219
5220 I915_WRITE(PCH_DREF_CONTROL, val);
5221 POSTING_READ(PCH_DREF_CONTROL);
5222 udelay(200);
5223 } else {
5224 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5225
5226 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5227
5228 /* Turn off CPU output */
5229 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5230
5231 I915_WRITE(PCH_DREF_CONTROL, val);
5232 POSTING_READ(PCH_DREF_CONTROL);
5233 udelay(200);
5234
5235 /* Turn off the SSC source */
5236 val &= ~DREF_SSC_SOURCE_MASK;
5237 val |= DREF_SSC_SOURCE_DISABLE;
5238
5239 /* Turn off SSC1 */
5240 val &= ~DREF_SSC1_ENABLE;
5241
5242 I915_WRITE(PCH_DREF_CONTROL, val);
5243 POSTING_READ(PCH_DREF_CONTROL);
5244 udelay(200);
5245 }
5246
5247 BUG_ON(val != final);
5248}
5249
5250static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5251{
5252 uint32_t tmp;
5253
5254 tmp = I915_READ(SOUTH_CHICKEN2);
5255 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5256 I915_WRITE(SOUTH_CHICKEN2, tmp);
5257
5258 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5259 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5260 DRM_ERROR("FDI mPHY reset assert timeout\n");
5261
5262 tmp = I915_READ(SOUTH_CHICKEN2);
5263 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5264 I915_WRITE(SOUTH_CHICKEN2, tmp);
5265
5266 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5267 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5268 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5269}
5270
5271/* WaMPhyProgramming:hsw */
5272static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5273{
5274 uint32_t tmp;
5275
5276 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5277 tmp &= ~(0xFF << 24);
5278 tmp |= (0x12 << 24);
5279 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5280
5281 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5282 tmp |= (1 << 11);
5283 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5284
5285 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5286 tmp |= (1 << 11);
5287 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5290 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5291 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5292
5293 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5294 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5295 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5296
5297 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5298 tmp &= ~(7 << 13);
5299 tmp |= (5 << 13);
5300 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5301
5302 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5303 tmp &= ~(7 << 13);
5304 tmp |= (5 << 13);
5305 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5306
5307 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5308 tmp &= ~0xFF;
5309 tmp |= 0x1C;
5310 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5311
5312 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5313 tmp &= ~0xFF;
5314 tmp |= 0x1C;
5315 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5316
5317 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5318 tmp &= ~(0xFF << 16);
5319 tmp |= (0x1C << 16);
5320 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5321
5322 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5323 tmp &= ~(0xFF << 16);
5324 tmp |= (0x1C << 16);
5325 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5326
5327 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5328 tmp |= (1 << 27);
5329 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5330
5331 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5332 tmp |= (1 << 27);
5333 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5334
5335 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5336 tmp &= ~(0xF << 28);
5337 tmp |= (4 << 28);
5338 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5339
5340 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5341 tmp &= ~(0xF << 28);
5342 tmp |= (4 << 28);
5343 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5344}
5345
5346/* Implements 3 different sequences from BSpec chapter "Display iCLK
5347 * Programming" based on the parameters passed:
5348 * - Sequence to enable CLKOUT_DP
5349 * - Sequence to enable CLKOUT_DP without spread
5350 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5351 */
5352static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5353 bool with_fdi)
5354{
5355 struct drm_i915_private *dev_priv = dev->dev_private;
5356 uint32_t reg, tmp;
5357
5358 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5359 with_spread = true;
5360 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5361 with_fdi, "LP PCH doesn't have FDI\n"))
5362 with_fdi = false;
5363
5364 mutex_lock(&dev_priv->dpio_lock);
5365
5366 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5367 tmp &= ~SBI_SSCCTL_DISABLE;
5368 tmp |= SBI_SSCCTL_PATHALT;
5369 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5370
5371 udelay(24);
5372
5373 if (with_spread) {
5374 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5375 tmp &= ~SBI_SSCCTL_PATHALT;
5376 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5377
5378 if (with_fdi) {
5379 lpt_reset_fdi_mphy(dev_priv);
5380 lpt_program_fdi_mphy(dev_priv);
5381 }
5382 }
5383
5384 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5385 SBI_GEN0 : SBI_DBUFF0;
5386 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5387 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5388 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5389
5390 mutex_unlock(&dev_priv->dpio_lock);
5391}
5392
5393/* Sequence to disable CLKOUT_DP */
5394static void lpt_disable_clkout_dp(struct drm_device *dev)
5395{
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 uint32_t reg, tmp;
5398
5399 mutex_lock(&dev_priv->dpio_lock);
5400
5401 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5402 SBI_GEN0 : SBI_DBUFF0;
5403 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5404 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5405 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5406
5407 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5408 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5409 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5410 tmp |= SBI_SSCCTL_PATHALT;
5411 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5412 udelay(32);
5413 }
5414 tmp |= SBI_SSCCTL_DISABLE;
5415 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5416 }
5417
5418 mutex_unlock(&dev_priv->dpio_lock);
5419}
5420
5421static void lpt_init_pch_refclk(struct drm_device *dev)
5422{
5423 struct drm_mode_config *mode_config = &dev->mode_config;
5424 struct intel_encoder *encoder;
5425 bool has_vga = false;
5426
5427 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5428 switch (encoder->type) {
5429 case INTEL_OUTPUT_ANALOG:
5430 has_vga = true;
5431 break;
5432 }
5433 }
5434
5435 if (has_vga)
5436 lpt_enable_clkout_dp(dev, true, true);
5437 else
5438 lpt_disable_clkout_dp(dev);
5439}
5440
5441/*
5442 * Initialize reference clocks when the driver loads
5443 */
5444void intel_init_pch_refclk(struct drm_device *dev)
5445{
5446 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5447 ironlake_init_pch_refclk(dev);
5448 else if (HAS_PCH_LPT(dev))
5449 lpt_init_pch_refclk(dev);
5450}
5451
5452static int ironlake_get_refclk(struct drm_crtc *crtc)
5453{
5454 struct drm_device *dev = crtc->dev;
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 struct intel_encoder *encoder;
5457 int num_connectors = 0;
5458 bool is_lvds = false;
5459
5460 for_each_encoder_on_crtc(dev, crtc, encoder) {
5461 switch (encoder->type) {
5462 case INTEL_OUTPUT_LVDS:
5463 is_lvds = true;
5464 break;
5465 }
5466 num_connectors++;
5467 }
5468
5469 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5470 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5471 dev_priv->vbt.lvds_ssc_freq);
5472 return dev_priv->vbt.lvds_ssc_freq * 1000;
5473 }
5474
5475 return 120000;
5476}
5477
5478static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5479{
5480 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5482 int pipe = intel_crtc->pipe;
5483 uint32_t val;
5484
5485 val = 0;
5486
5487 switch (intel_crtc->config.pipe_bpp) {
5488 case 18:
5489 val |= PIPECONF_6BPC;
5490 break;
5491 case 24:
5492 val |= PIPECONF_8BPC;
5493 break;
5494 case 30:
5495 val |= PIPECONF_10BPC;
5496 break;
5497 case 36:
5498 val |= PIPECONF_12BPC;
5499 break;
5500 default:
5501 /* Case prevented by intel_choose_pipe_bpp_dither. */
5502 BUG();
5503 }
5504
5505 if (intel_crtc->config.dither)
5506 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5507
5508 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5509 val |= PIPECONF_INTERLACED_ILK;
5510 else
5511 val |= PIPECONF_PROGRESSIVE;
5512
5513 if (intel_crtc->config.limited_color_range)
5514 val |= PIPECONF_COLOR_RANGE_SELECT;
5515
5516 I915_WRITE(PIPECONF(pipe), val);
5517 POSTING_READ(PIPECONF(pipe));
5518}
5519
5520/*
5521 * Set up the pipe CSC unit.
5522 *
5523 * Currently only full range RGB to limited range RGB conversion
5524 * is supported, but eventually this should handle various
5525 * RGB<->YCbCr scenarios as well.
5526 */
5527static void intel_set_pipe_csc(struct drm_crtc *crtc)
5528{
5529 struct drm_device *dev = crtc->dev;
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5532 int pipe = intel_crtc->pipe;
5533 uint16_t coeff = 0x7800; /* 1.0 */
5534
5535 /*
5536 * TODO: Check what kind of values actually come out of the pipe
5537 * with these coeff/postoff values and adjust to get the best
5538 * accuracy. Perhaps we even need to take the bpc value into
5539 * consideration.
5540 */
5541
5542 if (intel_crtc->config.limited_color_range)
5543 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5544
5545 /*
5546 * GY/GU and RY/RU should be the other way around according
5547 * to BSpec, but reality doesn't agree. Just set them up in
5548 * a way that results in the correct picture.
5549 */
5550 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5551 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5552
5553 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5554 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5555
5556 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5557 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5558
5559 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5560 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5561 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5562
5563 if (INTEL_INFO(dev)->gen > 6) {
5564 uint16_t postoff = 0;
5565
5566 if (intel_crtc->config.limited_color_range)
5567 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5568
5569 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5570 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5571 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5572
5573 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5574 } else {
5575 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5576
5577 if (intel_crtc->config.limited_color_range)
5578 mode |= CSC_BLACK_SCREEN_OFFSET;
5579
5580 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5581 }
5582}
5583
5584static void haswell_set_pipeconf(struct drm_crtc *crtc)
5585{
5586 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5589 uint32_t val;
5590
5591 val = 0;
5592
5593 if (intel_crtc->config.dither)
5594 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5595
5596 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5597 val |= PIPECONF_INTERLACED_ILK;
5598 else
5599 val |= PIPECONF_PROGRESSIVE;
5600
5601 I915_WRITE(PIPECONF(cpu_transcoder), val);
5602 POSTING_READ(PIPECONF(cpu_transcoder));
5603
5604 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5605 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5606}
5607
5608static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5609 intel_clock_t *clock,
5610 bool *has_reduced_clock,
5611 intel_clock_t *reduced_clock)
5612{
5613 struct drm_device *dev = crtc->dev;
5614 struct drm_i915_private *dev_priv = dev->dev_private;
5615 struct intel_encoder *intel_encoder;
5616 int refclk;
5617 const intel_limit_t *limit;
5618 bool ret, is_lvds = false;
5619
5620 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5621 switch (intel_encoder->type) {
5622 case INTEL_OUTPUT_LVDS:
5623 is_lvds = true;
5624 break;
5625 }
5626 }
5627
5628 refclk = ironlake_get_refclk(crtc);
5629
5630 /*
5631 * Returns a set of divisors for the desired target clock with the given
5632 * refclk, or FALSE. The returned values represent the clock equation:
5633 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5634 */
5635 limit = intel_limit(crtc, refclk);
5636 ret = dev_priv->display.find_dpll(limit, crtc,
5637 to_intel_crtc(crtc)->config.port_clock,
5638 refclk, NULL, clock);
5639 if (!ret)
5640 return false;
5641
5642 if (is_lvds && dev_priv->lvds_downclock_avail) {
5643 /*
5644 * Ensure we match the reduced clock's P to the target clock.
5645 * If the clocks don't match, we can't switch the display clock
5646 * by using the FP0/FP1. In such case we will disable the LVDS
5647 * downclock feature.
5648 */
5649 *has_reduced_clock =
5650 dev_priv->display.find_dpll(limit, crtc,
5651 dev_priv->lvds_downclock,
5652 refclk, clock,
5653 reduced_clock);
5654 }
5655
5656 return true;
5657}
5658
5659static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5660{
5661 struct drm_i915_private *dev_priv = dev->dev_private;
5662 uint32_t temp;
5663
5664 temp = I915_READ(SOUTH_CHICKEN1);
5665 if (temp & FDI_BC_BIFURCATION_SELECT)
5666 return;
5667
5668 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5669 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5670
5671 temp |= FDI_BC_BIFURCATION_SELECT;
5672 DRM_DEBUG_KMS("enabling fdi C rx\n");
5673 I915_WRITE(SOUTH_CHICKEN1, temp);
5674 POSTING_READ(SOUTH_CHICKEN1);
5675}
5676
5677static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5678{
5679 struct drm_device *dev = intel_crtc->base.dev;
5680 struct drm_i915_private *dev_priv = dev->dev_private;
5681
5682 switch (intel_crtc->pipe) {
5683 case PIPE_A:
5684 break;
5685 case PIPE_B:
5686 if (intel_crtc->config.fdi_lanes > 2)
5687 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5688 else
5689 cpt_enable_fdi_bc_bifurcation(dev);
5690
5691 break;
5692 case PIPE_C:
5693 cpt_enable_fdi_bc_bifurcation(dev);
5694
5695 break;
5696 default:
5697 BUG();
5698 }
5699}
5700
5701int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5702{
5703 /*
5704 * Account for spread spectrum to avoid
5705 * oversubscribing the link. Max center spread
5706 * is 2.5%; use 5% for safety's sake.
5707 */
5708 u32 bps = target_clock * bpp * 21 / 20;
5709 return bps / (link_bw * 8) + 1;
5710}
5711
5712static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5713{
5714 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5715}
5716
5717static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5718 u32 *fp,
5719 intel_clock_t *reduced_clock, u32 *fp2)
5720{
5721 struct drm_crtc *crtc = &intel_crtc->base;
5722 struct drm_device *dev = crtc->dev;
5723 struct drm_i915_private *dev_priv = dev->dev_private;
5724 struct intel_encoder *intel_encoder;
5725 uint32_t dpll;
5726 int factor, num_connectors = 0;
5727 bool is_lvds = false, is_sdvo = false;
5728
5729 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5730 switch (intel_encoder->type) {
5731 case INTEL_OUTPUT_LVDS:
5732 is_lvds = true;
5733 break;
5734 case INTEL_OUTPUT_SDVO:
5735 case INTEL_OUTPUT_HDMI:
5736 is_sdvo = true;
5737 break;
5738 }
5739
5740 num_connectors++;
5741 }
5742
5743 /* Enable autotuning of the PLL clock (if permissible) */
5744 factor = 21;
5745 if (is_lvds) {
5746 if ((intel_panel_use_ssc(dev_priv) &&
5747 dev_priv->vbt.lvds_ssc_freq == 100) ||
5748 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5749 factor = 25;
5750 } else if (intel_crtc->config.sdvo_tv_clock)
5751 factor = 20;
5752
5753 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5754 *fp |= FP_CB_TUNE;
5755
5756 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5757 *fp2 |= FP_CB_TUNE;
5758
5759 dpll = 0;
5760
5761 if (is_lvds)
5762 dpll |= DPLLB_MODE_LVDS;
5763 else
5764 dpll |= DPLLB_MODE_DAC_SERIAL;
5765
5766 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5767 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5768
5769 if (is_sdvo)
5770 dpll |= DPLL_SDVO_HIGH_SPEED;
5771 if (intel_crtc->config.has_dp_encoder)
5772 dpll |= DPLL_SDVO_HIGH_SPEED;
5773
5774 /* compute bitmask from p1 value */
5775 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5776 /* also FPA1 */
5777 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5778
5779 switch (intel_crtc->config.dpll.p2) {
5780 case 5:
5781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5782 break;
5783 case 7:
5784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5785 break;
5786 case 10:
5787 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5788 break;
5789 case 14:
5790 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5791 break;
5792 }
5793
5794 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5795 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5796 else
5797 dpll |= PLL_REF_INPUT_DREFCLK;
5798
5799 return dpll | DPLL_VCO_ENABLE;
5800}
5801
5802static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5803 int x, int y,
5804 struct drm_framebuffer *fb)
5805{
5806 struct drm_device *dev = crtc->dev;
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5809 int pipe = intel_crtc->pipe;
5810 int plane = intel_crtc->plane;
5811 int num_connectors = 0;
5812 intel_clock_t clock, reduced_clock;
5813 u32 dpll = 0, fp = 0, fp2 = 0;
5814 bool ok, has_reduced_clock = false;
5815 bool is_lvds = false;
5816 struct intel_encoder *encoder;
5817 struct intel_shared_dpll *pll;
5818 int ret;
5819
5820 for_each_encoder_on_crtc(dev, crtc, encoder) {
5821 switch (encoder->type) {
5822 case INTEL_OUTPUT_LVDS:
5823 is_lvds = true;
5824 break;
5825 }
5826
5827 num_connectors++;
5828 }
5829
5830 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5831 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5832
5833 ok = ironlake_compute_clocks(crtc, &clock,
5834 &has_reduced_clock, &reduced_clock);
5835 if (!ok && !intel_crtc->config.clock_set) {
5836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5837 return -EINVAL;
5838 }
5839 /* Compat-code for transition, will disappear. */
5840 if (!intel_crtc->config.clock_set) {
5841 intel_crtc->config.dpll.n = clock.n;
5842 intel_crtc->config.dpll.m1 = clock.m1;
5843 intel_crtc->config.dpll.m2 = clock.m2;
5844 intel_crtc->config.dpll.p1 = clock.p1;
5845 intel_crtc->config.dpll.p2 = clock.p2;
5846 }
5847
5848 /* Ensure that the cursor is valid for the new mode before changing... */
5849 intel_crtc_update_cursor(crtc, true);
5850
5851 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5852 if (intel_crtc->config.has_pch_encoder) {
5853 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5854 if (has_reduced_clock)
5855 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5856
5857 dpll = ironlake_compute_dpll(intel_crtc,
5858 &fp, &reduced_clock,
5859 has_reduced_clock ? &fp2 : NULL);
5860
5861 intel_crtc->config.dpll_hw_state.dpll = dpll;
5862 intel_crtc->config.dpll_hw_state.fp0 = fp;
5863 if (has_reduced_clock)
5864 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5865 else
5866 intel_crtc->config.dpll_hw_state.fp1 = fp;
5867
5868 pll = intel_get_shared_dpll(intel_crtc);
5869 if (pll == NULL) {
5870 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5871 pipe_name(pipe));
5872 return -EINVAL;
5873 }
5874 } else
5875 intel_put_shared_dpll(intel_crtc);
5876
5877 if (intel_crtc->config.has_dp_encoder)
5878 intel_dp_set_m_n(intel_crtc);
5879
5880 if (is_lvds && has_reduced_clock && i915_powersave)
5881 intel_crtc->lowfreq_avail = true;
5882 else
5883 intel_crtc->lowfreq_avail = false;
5884
5885 if (intel_crtc->config.has_pch_encoder) {
5886 pll = intel_crtc_to_shared_dpll(intel_crtc);
5887
5888 }
5889
5890 intel_set_pipe_timings(intel_crtc);
5891
5892 if (intel_crtc->config.has_pch_encoder) {
5893 intel_cpu_transcoder_set_m_n(intel_crtc,
5894 &intel_crtc->config.fdi_m_n);
5895 }
5896
5897 if (IS_IVYBRIDGE(dev))
5898 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5899
5900 ironlake_set_pipeconf(crtc);
5901
5902 /* Set up the display plane register */
5903 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5904 POSTING_READ(DSPCNTR(plane));
5905
5906 ret = intel_pipe_set_base(crtc, x, y, fb);
5907
5908 return ret;
5909}
5910
5911static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5912 struct intel_link_m_n *m_n)
5913{
5914 struct drm_device *dev = crtc->base.dev;
5915 struct drm_i915_private *dev_priv = dev->dev_private;
5916 enum pipe pipe = crtc->pipe;
5917
5918 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5919 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5920 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5921 & ~TU_SIZE_MASK;
5922 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5923 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5924 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5925}
5926
5927static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5928 enum transcoder transcoder,
5929 struct intel_link_m_n *m_n)
5930{
5931 struct drm_device *dev = crtc->base.dev;
5932 struct drm_i915_private *dev_priv = dev->dev_private;
5933 enum pipe pipe = crtc->pipe;
5934
5935 if (INTEL_INFO(dev)->gen >= 5) {
5936 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5937 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5938 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5939 & ~TU_SIZE_MASK;
5940 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5941 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5942 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5943 } else {
5944 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5945 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5946 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5947 & ~TU_SIZE_MASK;
5948 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5949 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5950 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5951 }
5952}
5953
5954void intel_dp_get_m_n(struct intel_crtc *crtc,
5955 struct intel_crtc_config *pipe_config)
5956{
5957 if (crtc->config.has_pch_encoder)
5958 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5959 else
5960 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5961 &pipe_config->dp_m_n);
5962}
5963
5964static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5965 struct intel_crtc_config *pipe_config)
5966{
5967 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5968 &pipe_config->fdi_m_n);
5969}
5970
5971static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5972 struct intel_crtc_config *pipe_config)
5973{
5974 struct drm_device *dev = crtc->base.dev;
5975 struct drm_i915_private *dev_priv = dev->dev_private;
5976 uint32_t tmp;
5977
5978 tmp = I915_READ(PF_CTL(crtc->pipe));
5979
5980 if (tmp & PF_ENABLE) {
5981 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5982 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5983
5984 /* We currently do not free assignements of panel fitters on
5985 * ivb/hsw (since we don't use the higher upscaling modes which
5986 * differentiates them) so just WARN about this case for now. */
5987 if (IS_GEN7(dev)) {
5988 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5989 PF_PIPE_SEL_IVB(crtc->pipe));
5990 }
5991 }
5992}
5993
5994static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5995 struct intel_crtc_config *pipe_config)
5996{
5997 struct drm_device *dev = crtc->base.dev;
5998 struct drm_i915_private *dev_priv = dev->dev_private;
5999 uint32_t tmp;
6000
6001 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6002 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6003
6004 tmp = I915_READ(PIPECONF(crtc->pipe));
6005 if (!(tmp & PIPECONF_ENABLE))
6006 return false;
6007
6008 switch (tmp & PIPECONF_BPC_MASK) {
6009 case PIPECONF_6BPC:
6010 pipe_config->pipe_bpp = 18;
6011 break;
6012 case PIPECONF_8BPC:
6013 pipe_config->pipe_bpp = 24;
6014 break;
6015 case PIPECONF_10BPC:
6016 pipe_config->pipe_bpp = 30;
6017 break;
6018 case PIPECONF_12BPC:
6019 pipe_config->pipe_bpp = 36;
6020 break;
6021 default:
6022 break;
6023 }
6024
6025 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6026 struct intel_shared_dpll *pll;
6027
6028 pipe_config->has_pch_encoder = true;
6029
6030 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6031 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6032 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6033
6034 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6035
6036 if (HAS_PCH_IBX(dev_priv->dev)) {
6037 pipe_config->shared_dpll =
6038 (enum intel_dpll_id) crtc->pipe;
6039 } else {
6040 tmp = I915_READ(PCH_DPLL_SEL);
6041 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6042 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6043 else
6044 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6045 }
6046
6047 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6048
6049 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6050 &pipe_config->dpll_hw_state));
6051
6052 tmp = pipe_config->dpll_hw_state.dpll;
6053 pipe_config->pixel_multiplier =
6054 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6055 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6056
6057 ironlake_pch_clock_get(crtc, pipe_config);
6058 } else {
6059 pipe_config->pixel_multiplier = 1;
6060 }
6061
6062 intel_get_pipe_timings(crtc, pipe_config);
6063
6064 ironlake_get_pfit_config(crtc, pipe_config);
6065
6066 return true;
6067}
6068
6069static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6070{
6071 struct drm_device *dev = dev_priv->dev;
6072 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6073 struct intel_crtc *crtc;
6074 unsigned long irqflags;
6075 uint32_t val;
6076
6077 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6078 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6079 pipe_name(crtc->pipe));
6080
6081 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6082 WARN(plls->spll_refcount, "SPLL enabled\n");
6083 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6084 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6085 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6086 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6087 "CPU PWM1 enabled\n");
6088 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6089 "CPU PWM2 enabled\n");
6090 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6091 "PCH PWM1 enabled\n");
6092 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6093 "Utility pin enabled\n");
6094 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6095
6096 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6097 val = I915_READ(DEIMR);
6098 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6099 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6100 val = I915_READ(SDEIMR);
6101 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6102 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6103 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6104}
6105
6106/*
6107 * This function implements pieces of two sequences from BSpec:
6108 * - Sequence for display software to disable LCPLL
6109 * - Sequence for display software to allow package C8+
6110 * The steps implemented here are just the steps that actually touch the LCPLL
6111 * register. Callers should take care of disabling all the display engine
6112 * functions, doing the mode unset, fixing interrupts, etc.
6113 */
6114void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6115 bool switch_to_fclk, bool allow_power_down)
6116{
6117 uint32_t val;
6118
6119 assert_can_disable_lcpll(dev_priv);
6120
6121 val = I915_READ(LCPLL_CTL);
6122
6123 if (switch_to_fclk) {
6124 val |= LCPLL_CD_SOURCE_FCLK;
6125 I915_WRITE(LCPLL_CTL, val);
6126
6127 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6128 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6129 DRM_ERROR("Switching to FCLK failed\n");
6130
6131 val = I915_READ(LCPLL_CTL);
6132 }
6133
6134 val |= LCPLL_PLL_DISABLE;
6135 I915_WRITE(LCPLL_CTL, val);
6136 POSTING_READ(LCPLL_CTL);
6137
6138 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6139 DRM_ERROR("LCPLL still locked\n");
6140
6141 val = I915_READ(D_COMP);
6142 val |= D_COMP_COMP_DISABLE;
6143 mutex_lock(&dev_priv->rps.hw_lock);
6144 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6145 DRM_ERROR("Failed to disable D_COMP\n");
6146 mutex_unlock(&dev_priv->rps.hw_lock);
6147 POSTING_READ(D_COMP);
6148 ndelay(100);
6149
6150 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6151 DRM_ERROR("D_COMP RCOMP still in progress\n");
6152
6153 if (allow_power_down) {
6154 val = I915_READ(LCPLL_CTL);
6155 val |= LCPLL_POWER_DOWN_ALLOW;
6156 I915_WRITE(LCPLL_CTL, val);
6157 POSTING_READ(LCPLL_CTL);
6158 }
6159}
6160
6161/*
6162 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6163 * source.
6164 */
6165void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6166{
6167 uint32_t val;
6168
6169 val = I915_READ(LCPLL_CTL);
6170
6171 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6172 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6173 return;
6174
6175 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6176 * we'll hang the machine! */
6177 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6178
6179 if (val & LCPLL_POWER_DOWN_ALLOW) {
6180 val &= ~LCPLL_POWER_DOWN_ALLOW;
6181 I915_WRITE(LCPLL_CTL, val);
6182 POSTING_READ(LCPLL_CTL);
6183 }
6184
6185 val = I915_READ(D_COMP);
6186 val |= D_COMP_COMP_FORCE;
6187 val &= ~D_COMP_COMP_DISABLE;
6188 mutex_lock(&dev_priv->rps.hw_lock);
6189 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6190 DRM_ERROR("Failed to enable D_COMP\n");
6191 mutex_unlock(&dev_priv->rps.hw_lock);
6192 POSTING_READ(D_COMP);
6193
6194 val = I915_READ(LCPLL_CTL);
6195 val &= ~LCPLL_PLL_DISABLE;
6196 I915_WRITE(LCPLL_CTL, val);
6197
6198 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6199 DRM_ERROR("LCPLL not locked yet\n");
6200
6201 if (val & LCPLL_CD_SOURCE_FCLK) {
6202 val = I915_READ(LCPLL_CTL);
6203 val &= ~LCPLL_CD_SOURCE_FCLK;
6204 I915_WRITE(LCPLL_CTL, val);
6205
6206 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6207 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6208 DRM_ERROR("Switching back to LCPLL failed\n");
6209 }
6210
6211 dev_priv->uncore.funcs.force_wake_put(dev_priv);
6212}
6213
6214void hsw_enable_pc8_work(struct work_struct *__work)
6215{
6216 struct drm_i915_private *dev_priv =
6217 container_of(to_delayed_work(__work), struct drm_i915_private,
6218 pc8.enable_work);
6219 struct drm_device *dev = dev_priv->dev;
6220 uint32_t val;
6221
6222 if (dev_priv->pc8.enabled)
6223 return;
6224
6225 DRM_DEBUG_KMS("Enabling package C8+\n");
6226
6227 dev_priv->pc8.enabled = true;
6228
6229 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6230 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6231 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6232 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6233 }
6234
6235 lpt_disable_clkout_dp(dev);
6236 hsw_pc8_disable_interrupts(dev);
6237 hsw_disable_lcpll(dev_priv, true, true);
6238}
6239
6240static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6241{
6242 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6243 WARN(dev_priv->pc8.disable_count < 1,
6244 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6245
6246 dev_priv->pc8.disable_count--;
6247 if (dev_priv->pc8.disable_count != 0)
6248 return;
6249
6250 schedule_delayed_work(&dev_priv->pc8.enable_work,
6251 msecs_to_jiffies(i915_pc8_timeout));
6252}
6253
6254static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6255{
6256 struct drm_device *dev = dev_priv->dev;
6257 uint32_t val;
6258
6259 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6260 WARN(dev_priv->pc8.disable_count < 0,
6261 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6262
6263 dev_priv->pc8.disable_count++;
6264 if (dev_priv->pc8.disable_count != 1)
6265 return;
6266
6267 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6268 if (!dev_priv->pc8.enabled)
6269 return;
6270
6271 DRM_DEBUG_KMS("Disabling package C8+\n");
6272
6273 hsw_restore_lcpll(dev_priv);
6274 hsw_pc8_restore_interrupts(dev);
6275 lpt_init_pch_refclk(dev);
6276
6277 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6278 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6279 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6280 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6281 }
6282
6283 intel_prepare_ddi(dev);
6284 i915_gem_init_swizzling(dev);
6285 mutex_lock(&dev_priv->rps.hw_lock);
6286 gen6_update_ring_freq(dev);
6287 mutex_unlock(&dev_priv->rps.hw_lock);
6288 dev_priv->pc8.enabled = false;
6289}
6290
6291void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6292{
6293 mutex_lock(&dev_priv->pc8.lock);
6294 __hsw_enable_package_c8(dev_priv);
6295 mutex_unlock(&dev_priv->pc8.lock);
6296}
6297
6298void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6299{
6300 mutex_lock(&dev_priv->pc8.lock);
6301 __hsw_disable_package_c8(dev_priv);
6302 mutex_unlock(&dev_priv->pc8.lock);
6303}
6304
6305static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6306{
6307 struct drm_device *dev = dev_priv->dev;
6308 struct intel_crtc *crtc;
6309 uint32_t val;
6310
6311 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6312 if (crtc->base.enabled)
6313 return false;
6314
6315 /* This case is still possible since we have the i915.disable_power_well
6316 * parameter and also the KVMr or something else might be requesting the
6317 * power well. */
6318 val = I915_READ(HSW_PWR_WELL_DRIVER);
6319 if (val != 0) {
6320 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6321 return false;
6322 }
6323
6324 return true;
6325}
6326
6327/* Since we're called from modeset_global_resources there's no way to
6328 * symmetrically increase and decrease the refcount, so we use
6329 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6330 * or not.
6331 */
6332static void hsw_update_package_c8(struct drm_device *dev)
6333{
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335 bool allow;
6336
6337 if (!i915_enable_pc8)
6338 return;
6339
6340 mutex_lock(&dev_priv->pc8.lock);
6341
6342 allow = hsw_can_enable_package_c8(dev_priv);
6343
6344 if (allow == dev_priv->pc8.requirements_met)
6345 goto done;
6346
6347 dev_priv->pc8.requirements_met = allow;
6348
6349 if (allow)
6350 __hsw_enable_package_c8(dev_priv);
6351 else
6352 __hsw_disable_package_c8(dev_priv);
6353
6354done:
6355 mutex_unlock(&dev_priv->pc8.lock);
6356}
6357
6358static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6359{
6360 if (!dev_priv->pc8.gpu_idle) {
6361 dev_priv->pc8.gpu_idle = true;
6362 hsw_enable_package_c8(dev_priv);
6363 }
6364}
6365
6366static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6367{
6368 if (dev_priv->pc8.gpu_idle) {
6369 dev_priv->pc8.gpu_idle = false;
6370 hsw_disable_package_c8(dev_priv);
6371 }
6372}
6373
6374static void haswell_modeset_global_resources(struct drm_device *dev)
6375{
6376 bool enable = false;
6377 struct intel_crtc *crtc;
6378
6379 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6380 if (!crtc->base.enabled)
6381 continue;
6382
6383 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6384 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6385 enable = true;
6386 }
6387
6388 intel_set_power_well(dev, enable);
6389
6390 hsw_update_package_c8(dev);
6391}
6392
6393static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6394 int x, int y,
6395 struct drm_framebuffer *fb)
6396{
6397 struct drm_device *dev = crtc->dev;
6398 struct drm_i915_private *dev_priv = dev->dev_private;
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6400 int plane = intel_crtc->plane;
6401 int ret;
6402
6403 if (!intel_ddi_pll_mode_set(crtc))
6404 return -EINVAL;
6405
6406 /* Ensure that the cursor is valid for the new mode before changing... */
6407 intel_crtc_update_cursor(crtc, true);
6408
6409 if (intel_crtc->config.has_dp_encoder)
6410 intel_dp_set_m_n(intel_crtc);
6411
6412 intel_crtc->lowfreq_avail = false;
6413
6414 intel_set_pipe_timings(intel_crtc);
6415
6416 if (intel_crtc->config.has_pch_encoder) {
6417 intel_cpu_transcoder_set_m_n(intel_crtc,
6418 &intel_crtc->config.fdi_m_n);
6419 }
6420
6421 haswell_set_pipeconf(crtc);
6422
6423 intel_set_pipe_csc(crtc);
6424
6425 /* Set up the display plane register */
6426 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6427 POSTING_READ(DSPCNTR(plane));
6428
6429 ret = intel_pipe_set_base(crtc, x, y, fb);
6430
6431 return ret;
6432}
6433
6434static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6435 struct intel_crtc_config *pipe_config)
6436{
6437 struct drm_device *dev = crtc->base.dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 enum intel_display_power_domain pfit_domain;
6440 uint32_t tmp;
6441
6442 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6443 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6444
6445 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6446 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6447 enum pipe trans_edp_pipe;
6448 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6449 default:
6450 WARN(1, "unknown pipe linked to edp transcoder\n");
6451 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6452 case TRANS_DDI_EDP_INPUT_A_ON:
6453 trans_edp_pipe = PIPE_A;
6454 break;
6455 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6456 trans_edp_pipe = PIPE_B;
6457 break;
6458 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6459 trans_edp_pipe = PIPE_C;
6460 break;
6461 }
6462
6463 if (trans_edp_pipe == crtc->pipe)
6464 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6465 }
6466
6467 if (!intel_display_power_enabled(dev,
6468 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6469 return false;
6470
6471 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6472 if (!(tmp & PIPECONF_ENABLE))
6473 return false;
6474
6475 /*
6476 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6477 * DDI E. So just check whether this pipe is wired to DDI E and whether
6478 * the PCH transcoder is on.
6479 */
6480 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6481 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6482 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6483 pipe_config->has_pch_encoder = true;
6484
6485 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6486 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6487 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6488
6489 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6490 }
6491
6492 intel_get_pipe_timings(crtc, pipe_config);
6493
6494 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6495 if (intel_display_power_enabled(dev, pfit_domain))
6496 ironlake_get_pfit_config(crtc, pipe_config);
6497
6498 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6499 (I915_READ(IPS_CTL) & IPS_ENABLE);
6500
6501 pipe_config->pixel_multiplier = 1;
6502
6503 return true;
6504}
6505
6506static int intel_crtc_mode_set(struct drm_crtc *crtc,
6507 int x, int y,
6508 struct drm_framebuffer *fb)
6509{
6510 struct drm_device *dev = crtc->dev;
6511 struct drm_i915_private *dev_priv = dev->dev_private;
6512 struct intel_encoder *encoder;
6513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6514 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6515 int pipe = intel_crtc->pipe;
6516 int ret;
6517
6518 drm_vblank_pre_modeset(dev, pipe);
6519
6520 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6521
6522 drm_vblank_post_modeset(dev, pipe);
6523
6524 if (ret != 0)
6525 return ret;
6526
6527 for_each_encoder_on_crtc(dev, crtc, encoder) {
6528 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6529 encoder->base.base.id,
6530 drm_get_encoder_name(&encoder->base),
6531 mode->base.id, mode->name);
6532 encoder->mode_set(encoder);
6533 }
6534
6535 return 0;
6536}
6537
6538static bool intel_eld_uptodate(struct drm_connector *connector,
6539 int reg_eldv, uint32_t bits_eldv,
6540 int reg_elda, uint32_t bits_elda,
6541 int reg_edid)
6542{
6543 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6544 uint8_t *eld = connector->eld;
6545 uint32_t i;
6546
6547 i = I915_READ(reg_eldv);
6548 i &= bits_eldv;
6549
6550 if (!eld[0])
6551 return !i;
6552
6553 if (!i)
6554 return false;
6555
6556 i = I915_READ(reg_elda);
6557 i &= ~bits_elda;
6558 I915_WRITE(reg_elda, i);
6559
6560 for (i = 0; i < eld[2]; i++)
6561 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6562 return false;
6563
6564 return true;
6565}
6566
6567static void g4x_write_eld(struct drm_connector *connector,
6568 struct drm_crtc *crtc)
6569{
6570 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6571 uint8_t *eld = connector->eld;
6572 uint32_t eldv;
6573 uint32_t len;
6574 uint32_t i;
6575
6576 i = I915_READ(G4X_AUD_VID_DID);
6577
6578 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6579 eldv = G4X_ELDV_DEVCL_DEVBLC;
6580 else
6581 eldv = G4X_ELDV_DEVCTG;
6582
6583 if (intel_eld_uptodate(connector,
6584 G4X_AUD_CNTL_ST, eldv,
6585 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6586 G4X_HDMIW_HDMIEDID))
6587 return;
6588
6589 i = I915_READ(G4X_AUD_CNTL_ST);
6590 i &= ~(eldv | G4X_ELD_ADDR);
6591 len = (i >> 9) & 0x1f; /* ELD buffer size */
6592 I915_WRITE(G4X_AUD_CNTL_ST, i);
6593
6594 if (!eld[0])
6595 return;
6596
6597 len = min_t(uint8_t, eld[2], len);
6598 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6599 for (i = 0; i < len; i++)
6600 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6601
6602 i = I915_READ(G4X_AUD_CNTL_ST);
6603 i |= eldv;
6604 I915_WRITE(G4X_AUD_CNTL_ST, i);
6605}
6606
6607static void haswell_write_eld(struct drm_connector *connector,
6608 struct drm_crtc *crtc)
6609{
6610 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6611 uint8_t *eld = connector->eld;
6612 struct drm_device *dev = crtc->dev;
6613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6614 uint32_t eldv;
6615 uint32_t i;
6616 int len;
6617 int pipe = to_intel_crtc(crtc)->pipe;
6618 int tmp;
6619
6620 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6621 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6622 int aud_config = HSW_AUD_CFG(pipe);
6623 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6624
6625
6626 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6627
6628 /* Audio output enable */
6629 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6630 tmp = I915_READ(aud_cntrl_st2);
6631 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6632 I915_WRITE(aud_cntrl_st2, tmp);
6633
6634 /* Wait for 1 vertical blank */
6635 intel_wait_for_vblank(dev, pipe);
6636
6637 /* Set ELD valid state */
6638 tmp = I915_READ(aud_cntrl_st2);
6639 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6640 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6641 I915_WRITE(aud_cntrl_st2, tmp);
6642 tmp = I915_READ(aud_cntrl_st2);
6643 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6644
6645 /* Enable HDMI mode */
6646 tmp = I915_READ(aud_config);
6647 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6648 /* clear N_programing_enable and N_value_index */
6649 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6650 I915_WRITE(aud_config, tmp);
6651
6652 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6653
6654 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6655 intel_crtc->eld_vld = true;
6656
6657 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6658 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6659 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6660 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6661 } else
6662 I915_WRITE(aud_config, 0);
6663
6664 if (intel_eld_uptodate(connector,
6665 aud_cntrl_st2, eldv,
6666 aud_cntl_st, IBX_ELD_ADDRESS,
6667 hdmiw_hdmiedid))
6668 return;
6669
6670 i = I915_READ(aud_cntrl_st2);
6671 i &= ~eldv;
6672 I915_WRITE(aud_cntrl_st2, i);
6673
6674 if (!eld[0])
6675 return;
6676
6677 i = I915_READ(aud_cntl_st);
6678 i &= ~IBX_ELD_ADDRESS;
6679 I915_WRITE(aud_cntl_st, i);
6680 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6681 DRM_DEBUG_DRIVER("port num:%d\n", i);
6682
6683 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6684 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6685 for (i = 0; i < len; i++)
6686 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6687
6688 i = I915_READ(aud_cntrl_st2);
6689 i |= eldv;
6690 I915_WRITE(aud_cntrl_st2, i);
6691
6692}
6693
6694static void ironlake_write_eld(struct drm_connector *connector,
6695 struct drm_crtc *crtc)
6696{
6697 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6698 uint8_t *eld = connector->eld;
6699 uint32_t eldv;
6700 uint32_t i;
6701 int len;
6702 int hdmiw_hdmiedid;
6703 int aud_config;
6704 int aud_cntl_st;
6705 int aud_cntrl_st2;
6706 int pipe = to_intel_crtc(crtc)->pipe;
6707
6708 if (HAS_PCH_IBX(connector->dev)) {
6709 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6710 aud_config = IBX_AUD_CFG(pipe);
6711 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6712 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6713 } else {
6714 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6715 aud_config = CPT_AUD_CFG(pipe);
6716 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6717 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6718 }
6719
6720 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6721
6722 i = I915_READ(aud_cntl_st);
6723 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6724 if (!i) {
6725 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6726 /* operate blindly on all ports */
6727 eldv = IBX_ELD_VALIDB;
6728 eldv |= IBX_ELD_VALIDB << 4;
6729 eldv |= IBX_ELD_VALIDB << 8;
6730 } else {
6731 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6732 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6733 }
6734
6735 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6736 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6737 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6738 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6739 } else
6740 I915_WRITE(aud_config, 0);
6741
6742 if (intel_eld_uptodate(connector,
6743 aud_cntrl_st2, eldv,
6744 aud_cntl_st, IBX_ELD_ADDRESS,
6745 hdmiw_hdmiedid))
6746 return;
6747
6748 i = I915_READ(aud_cntrl_st2);
6749 i &= ~eldv;
6750 I915_WRITE(aud_cntrl_st2, i);
6751
6752 if (!eld[0])
6753 return;
6754
6755 i = I915_READ(aud_cntl_st);
6756 i &= ~IBX_ELD_ADDRESS;
6757 I915_WRITE(aud_cntl_st, i);
6758
6759 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6760 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6761 for (i = 0; i < len; i++)
6762 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6763
6764 i = I915_READ(aud_cntrl_st2);
6765 i |= eldv;
6766 I915_WRITE(aud_cntrl_st2, i);
6767}
6768
6769void intel_write_eld(struct drm_encoder *encoder,
6770 struct drm_display_mode *mode)
6771{
6772 struct drm_crtc *crtc = encoder->crtc;
6773 struct drm_connector *connector;
6774 struct drm_device *dev = encoder->dev;
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776
6777 connector = drm_select_eld(encoder, mode);
6778 if (!connector)
6779 return;
6780
6781 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782 connector->base.id,
6783 drm_get_connector_name(connector),
6784 connector->encoder->base.id,
6785 drm_get_encoder_name(connector->encoder));
6786
6787 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6788
6789 if (dev_priv->display.write_eld)
6790 dev_priv->display.write_eld(connector, crtc);
6791}
6792
6793/** Loads the palette/gamma unit for the CRTC with the prepared values */
6794void intel_crtc_load_lut(struct drm_crtc *crtc)
6795{
6796 struct drm_device *dev = crtc->dev;
6797 struct drm_i915_private *dev_priv = dev->dev_private;
6798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6799 enum pipe pipe = intel_crtc->pipe;
6800 int palreg = PALETTE(pipe);
6801 int i;
6802 bool reenable_ips = false;
6803
6804 /* The clocks have to be on to load the palette. */
6805 if (!crtc->enabled || !intel_crtc->active)
6806 return;
6807
6808 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6809 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6810 assert_dsi_pll_enabled(dev_priv);
6811 else
6812 assert_pll_enabled(dev_priv, pipe);
6813 }
6814
6815 /* use legacy palette for Ironlake */
6816 if (HAS_PCH_SPLIT(dev))
6817 palreg = LGC_PALETTE(pipe);
6818
6819 /* Workaround : Do not read or write the pipe palette/gamma data while
6820 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6821 */
6822 if (intel_crtc->config.ips_enabled &&
6823 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6824 GAMMA_MODE_MODE_SPLIT)) {
6825 hsw_disable_ips(intel_crtc);
6826 reenable_ips = true;
6827 }
6828
6829 for (i = 0; i < 256; i++) {
6830 I915_WRITE(palreg + 4 * i,
6831 (intel_crtc->lut_r[i] << 16) |
6832 (intel_crtc->lut_g[i] << 8) |
6833 intel_crtc->lut_b[i]);
6834 }
6835
6836 if (reenable_ips)
6837 hsw_enable_ips(intel_crtc);
6838}
6839
6840static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6841{
6842 struct drm_device *dev = crtc->dev;
6843 struct drm_i915_private *dev_priv = dev->dev_private;
6844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6845 bool visible = base != 0;
6846 u32 cntl;
6847
6848 if (intel_crtc->cursor_visible == visible)
6849 return;
6850
6851 cntl = I915_READ(_CURACNTR);
6852 if (visible) {
6853 /* On these chipsets we can only modify the base whilst
6854 * the cursor is disabled.
6855 */
6856 I915_WRITE(_CURABASE, base);
6857
6858 cntl &= ~(CURSOR_FORMAT_MASK);
6859 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6860 cntl |= CURSOR_ENABLE |
6861 CURSOR_GAMMA_ENABLE |
6862 CURSOR_FORMAT_ARGB;
6863 } else
6864 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6865 I915_WRITE(_CURACNTR, cntl);
6866
6867 intel_crtc->cursor_visible = visible;
6868}
6869
6870static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6871{
6872 struct drm_device *dev = crtc->dev;
6873 struct drm_i915_private *dev_priv = dev->dev_private;
6874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6875 int pipe = intel_crtc->pipe;
6876 bool visible = base != 0;
6877
6878 if (intel_crtc->cursor_visible != visible) {
6879 uint32_t cntl = I915_READ(CURCNTR(pipe));
6880 if (base) {
6881 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6882 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6883 cntl |= pipe << 28; /* Connect to correct pipe */
6884 } else {
6885 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6886 cntl |= CURSOR_MODE_DISABLE;
6887 }
6888 I915_WRITE(CURCNTR(pipe), cntl);
6889
6890 intel_crtc->cursor_visible = visible;
6891 }
6892 /* and commit changes on next vblank */
6893 I915_WRITE(CURBASE(pipe), base);
6894}
6895
6896static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6897{
6898 struct drm_device *dev = crtc->dev;
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 int pipe = intel_crtc->pipe;
6902 bool visible = base != 0;
6903
6904 if (intel_crtc->cursor_visible != visible) {
6905 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6906 if (base) {
6907 cntl &= ~CURSOR_MODE;
6908 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6909 } else {
6910 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6911 cntl |= CURSOR_MODE_DISABLE;
6912 }
6913 if (IS_HASWELL(dev)) {
6914 cntl |= CURSOR_PIPE_CSC_ENABLE;
6915 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6916 }
6917 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6918
6919 intel_crtc->cursor_visible = visible;
6920 }
6921 /* and commit changes on next vblank */
6922 I915_WRITE(CURBASE_IVB(pipe), base);
6923}
6924
6925/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6926static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6927 bool on)
6928{
6929 struct drm_device *dev = crtc->dev;
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6932 int pipe = intel_crtc->pipe;
6933 int x = intel_crtc->cursor_x;
6934 int y = intel_crtc->cursor_y;
6935 u32 base = 0, pos = 0;
6936 bool visible;
6937
6938 if (on)
6939 base = intel_crtc->cursor_addr;
6940
6941 if (x >= intel_crtc->config.pipe_src_w)
6942 base = 0;
6943
6944 if (y >= intel_crtc->config.pipe_src_h)
6945 base = 0;
6946
6947 if (x < 0) {
6948 if (x + intel_crtc->cursor_width <= 0)
6949 base = 0;
6950
6951 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6952 x = -x;
6953 }
6954 pos |= x << CURSOR_X_SHIFT;
6955
6956 if (y < 0) {
6957 if (y + intel_crtc->cursor_height <= 0)
6958 base = 0;
6959
6960 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6961 y = -y;
6962 }
6963 pos |= y << CURSOR_Y_SHIFT;
6964
6965 visible = base != 0;
6966 if (!visible && !intel_crtc->cursor_visible)
6967 return;
6968
6969 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6970 I915_WRITE(CURPOS_IVB(pipe), pos);
6971 ivb_update_cursor(crtc, base);
6972 } else {
6973 I915_WRITE(CURPOS(pipe), pos);
6974 if (IS_845G(dev) || IS_I865G(dev))
6975 i845_update_cursor(crtc, base);
6976 else
6977 i9xx_update_cursor(crtc, base);
6978 }
6979}
6980
6981static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6982 struct drm_file *file,
6983 uint32_t handle,
6984 uint32_t width, uint32_t height)
6985{
6986 struct drm_device *dev = crtc->dev;
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989 struct drm_i915_gem_object *obj;
6990 uint32_t addr;
6991 int ret;
6992
6993 /* if we want to turn off the cursor ignore width and height */
6994 if (!handle) {
6995 DRM_DEBUG_KMS("cursor off\n");
6996 addr = 0;
6997 obj = NULL;
6998 mutex_lock(&dev->struct_mutex);
6999 goto finish;
7000 }
7001
7002 /* Currently we only support 64x64 cursors */
7003 if (width != 64 || height != 64) {
7004 DRM_ERROR("we currently only support 64x64 cursors\n");
7005 return -EINVAL;
7006 }
7007
7008 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7009 if (&obj->base == NULL)
7010 return -ENOENT;
7011
7012 if (obj->base.size < width * height * 4) {
7013 DRM_ERROR("buffer is to small\n");
7014 ret = -ENOMEM;
7015 goto fail;
7016 }
7017
7018 /* we only need to pin inside GTT if cursor is non-phy */
7019 mutex_lock(&dev->struct_mutex);
7020 if (!dev_priv->info->cursor_needs_physical) {
7021 unsigned alignment;
7022
7023 if (obj->tiling_mode) {
7024 DRM_ERROR("cursor cannot be tiled\n");
7025 ret = -EINVAL;
7026 goto fail_locked;
7027 }
7028
7029 /* Note that the w/a also requires 2 PTE of padding following
7030 * the bo. We currently fill all unused PTE with the shadow
7031 * page and so we should always have valid PTE following the
7032 * cursor preventing the VT-d warning.
7033 */
7034 alignment = 0;
7035 if (need_vtd_wa(dev))
7036 alignment = 64*1024;
7037
7038 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7039 if (ret) {
7040 DRM_ERROR("failed to move cursor bo into the GTT\n");
7041 goto fail_locked;
7042 }
7043
7044 ret = i915_gem_object_put_fence(obj);
7045 if (ret) {
7046 DRM_ERROR("failed to release fence for cursor");
7047 goto fail_unpin;
7048 }
7049
7050 addr = i915_gem_obj_ggtt_offset(obj);
7051 } else {
7052 int align = IS_I830(dev) ? 16 * 1024 : 256;
7053 ret = i915_gem_attach_phys_object(dev, obj,
7054 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7055 align);
7056 if (ret) {
7057 DRM_ERROR("failed to attach phys object\n");
7058 goto fail_locked;
7059 }
7060 addr = obj->phys_obj->handle->busaddr;
7061 }
7062
7063 if (IS_GEN2(dev))
7064 I915_WRITE(CURSIZE, (height << 12) | width);
7065
7066 finish:
7067 if (intel_crtc->cursor_bo) {
7068 if (dev_priv->info->cursor_needs_physical) {
7069 if (intel_crtc->cursor_bo != obj)
7070 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7071 } else
7072 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7073 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7074 }
7075
7076 mutex_unlock(&dev->struct_mutex);
7077
7078 intel_crtc->cursor_addr = addr;
7079 intel_crtc->cursor_bo = obj;
7080 intel_crtc->cursor_width = width;
7081 intel_crtc->cursor_height = height;
7082
7083 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7084
7085 return 0;
7086fail_unpin:
7087 i915_gem_object_unpin_from_display_plane(obj);
7088fail_locked:
7089 mutex_unlock(&dev->struct_mutex);
7090fail:
7091 drm_gem_object_unreference_unlocked(&obj->base);
7092 return ret;
7093}
7094
7095static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7096{
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7098
7099 intel_crtc->cursor_x = x;
7100 intel_crtc->cursor_y = y;
7101
7102 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7103
7104 return 0;
7105}
7106
7107/** Sets the color ramps on behalf of RandR */
7108void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7109 u16 blue, int regno)
7110{
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7112
7113 intel_crtc->lut_r[regno] = red >> 8;
7114 intel_crtc->lut_g[regno] = green >> 8;
7115 intel_crtc->lut_b[regno] = blue >> 8;
7116}
7117
7118void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7119 u16 *blue, int regno)
7120{
7121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7122
7123 *red = intel_crtc->lut_r[regno] << 8;
7124 *green = intel_crtc->lut_g[regno] << 8;
7125 *blue = intel_crtc->lut_b[regno] << 8;
7126}
7127
7128static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7129 u16 *blue, uint32_t start, uint32_t size)
7130{
7131 int end = (start + size > 256) ? 256 : start + size, i;
7132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133
7134 for (i = start; i < end; i++) {
7135 intel_crtc->lut_r[i] = red[i] >> 8;
7136 intel_crtc->lut_g[i] = green[i] >> 8;
7137 intel_crtc->lut_b[i] = blue[i] >> 8;
7138 }
7139
7140 intel_crtc_load_lut(crtc);
7141}
7142
7143/* VESA 640x480x72Hz mode to set on the pipe */
7144static struct drm_display_mode load_detect_mode = {
7145 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7146 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7147};
7148
7149static struct drm_framebuffer *
7150intel_framebuffer_create(struct drm_device *dev,
7151 struct drm_mode_fb_cmd2 *mode_cmd,
7152 struct drm_i915_gem_object *obj)
7153{
7154 struct intel_framebuffer *intel_fb;
7155 int ret;
7156
7157 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7158 if (!intel_fb) {
7159 drm_gem_object_unreference_unlocked(&obj->base);
7160 return ERR_PTR(-ENOMEM);
7161 }
7162
7163 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7164 if (ret) {
7165 drm_gem_object_unreference_unlocked(&obj->base);
7166 kfree(intel_fb);
7167 return ERR_PTR(ret);
7168 }
7169
7170 return &intel_fb->base;
7171}
7172
7173static u32
7174intel_framebuffer_pitch_for_width(int width, int bpp)
7175{
7176 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7177 return ALIGN(pitch, 64);
7178}
7179
7180static u32
7181intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7182{
7183 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7184 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7185}
7186
7187static struct drm_framebuffer *
7188intel_framebuffer_create_for_mode(struct drm_device *dev,
7189 struct drm_display_mode *mode,
7190 int depth, int bpp)
7191{
7192 struct drm_i915_gem_object *obj;
7193 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7194
7195 obj = i915_gem_alloc_object(dev,
7196 intel_framebuffer_size_for_mode(mode, bpp));
7197 if (obj == NULL)
7198 return ERR_PTR(-ENOMEM);
7199
7200 mode_cmd.width = mode->hdisplay;
7201 mode_cmd.height = mode->vdisplay;
7202 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7203 bpp);
7204 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7205
7206 return intel_framebuffer_create(dev, &mode_cmd, obj);
7207}
7208
7209static struct drm_framebuffer *
7210mode_fits_in_fbdev(struct drm_device *dev,
7211 struct drm_display_mode *mode)
7212{
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 struct drm_i915_gem_object *obj;
7215 struct drm_framebuffer *fb;
7216
7217 if (dev_priv->fbdev == NULL)
7218 return NULL;
7219
7220 obj = dev_priv->fbdev->ifb.obj;
7221 if (obj == NULL)
7222 return NULL;
7223
7224 fb = &dev_priv->fbdev->ifb.base;
7225 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7226 fb->bits_per_pixel))
7227 return NULL;
7228
7229 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7230 return NULL;
7231
7232 return fb;
7233}
7234
7235bool intel_get_load_detect_pipe(struct drm_connector *connector,
7236 struct drm_display_mode *mode,
7237 struct intel_load_detect_pipe *old)
7238{
7239 struct intel_crtc *intel_crtc;
7240 struct intel_encoder *intel_encoder =
7241 intel_attached_encoder(connector);
7242 struct drm_crtc *possible_crtc;
7243 struct drm_encoder *encoder = &intel_encoder->base;
7244 struct drm_crtc *crtc = NULL;
7245 struct drm_device *dev = encoder->dev;
7246 struct drm_framebuffer *fb;
7247 int i = -1;
7248
7249 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7250 connector->base.id, drm_get_connector_name(connector),
7251 encoder->base.id, drm_get_encoder_name(encoder));
7252
7253 /*
7254 * Algorithm gets a little messy:
7255 *
7256 * - if the connector already has an assigned crtc, use it (but make
7257 * sure it's on first)
7258 *
7259 * - try to find the first unused crtc that can drive this connector,
7260 * and use that if we find one
7261 */
7262
7263 /* See if we already have a CRTC for this connector */
7264 if (encoder->crtc) {
7265 crtc = encoder->crtc;
7266
7267 mutex_lock(&crtc->mutex);
7268
7269 old->dpms_mode = connector->dpms;
7270 old->load_detect_temp = false;
7271
7272 /* Make sure the crtc and connector are running */
7273 if (connector->dpms != DRM_MODE_DPMS_ON)
7274 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7275
7276 return true;
7277 }
7278
7279 /* Find an unused one (if possible) */
7280 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7281 i++;
7282 if (!(encoder->possible_crtcs & (1 << i)))
7283 continue;
7284 if (!possible_crtc->enabled) {
7285 crtc = possible_crtc;
7286 break;
7287 }
7288 }
7289
7290 /*
7291 * If we didn't find an unused CRTC, don't use any.
7292 */
7293 if (!crtc) {
7294 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7295 return false;
7296 }
7297
7298 mutex_lock(&crtc->mutex);
7299 intel_encoder->new_crtc = to_intel_crtc(crtc);
7300 to_intel_connector(connector)->new_encoder = intel_encoder;
7301
7302 intel_crtc = to_intel_crtc(crtc);
7303 old->dpms_mode = connector->dpms;
7304 old->load_detect_temp = true;
7305 old->release_fb = NULL;
7306
7307 if (!mode)
7308 mode = &load_detect_mode;
7309
7310 /* We need a framebuffer large enough to accommodate all accesses
7311 * that the plane may generate whilst we perform load detection.
7312 * We can not rely on the fbcon either being present (we get called
7313 * during its initialisation to detect all boot displays, or it may
7314 * not even exist) or that it is large enough to satisfy the
7315 * requested mode.
7316 */
7317 fb = mode_fits_in_fbdev(dev, mode);
7318 if (fb == NULL) {
7319 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7320 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7321 old->release_fb = fb;
7322 } else
7323 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7324 if (IS_ERR(fb)) {
7325 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7326 mutex_unlock(&crtc->mutex);
7327 return false;
7328 }
7329
7330 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7331 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7332 if (old->release_fb)
7333 old->release_fb->funcs->destroy(old->release_fb);
7334 mutex_unlock(&crtc->mutex);
7335 return false;
7336 }
7337
7338 /* let the connector get through one full cycle before testing */
7339 intel_wait_for_vblank(dev, intel_crtc->pipe);
7340 return true;
7341}
7342
7343void intel_release_load_detect_pipe(struct drm_connector *connector,
7344 struct intel_load_detect_pipe *old)
7345{
7346 struct intel_encoder *intel_encoder =
7347 intel_attached_encoder(connector);
7348 struct drm_encoder *encoder = &intel_encoder->base;
7349 struct drm_crtc *crtc = encoder->crtc;
7350
7351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7352 connector->base.id, drm_get_connector_name(connector),
7353 encoder->base.id, drm_get_encoder_name(encoder));
7354
7355 if (old->load_detect_temp) {
7356 to_intel_connector(connector)->new_encoder = NULL;
7357 intel_encoder->new_crtc = NULL;
7358 intel_set_mode(crtc, NULL, 0, 0, NULL);
7359
7360 if (old->release_fb) {
7361 drm_framebuffer_unregister_private(old->release_fb);
7362 drm_framebuffer_unreference(old->release_fb);
7363 }
7364
7365 mutex_unlock(&crtc->mutex);
7366 return;
7367 }
7368
7369 /* Switch crtc and encoder back off if necessary */
7370 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7371 connector->funcs->dpms(connector, old->dpms_mode);
7372
7373 mutex_unlock(&crtc->mutex);
7374}
7375
7376static int i9xx_pll_refclk(struct drm_device *dev,
7377 const struct intel_crtc_config *pipe_config)
7378{
7379 struct drm_i915_private *dev_priv = dev->dev_private;
7380 u32 dpll = pipe_config->dpll_hw_state.dpll;
7381
7382 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7383 return dev_priv->vbt.lvds_ssc_freq * 1000;
7384 else if (HAS_PCH_SPLIT(dev))
7385 return 120000;
7386 else if (!IS_GEN2(dev))
7387 return 96000;
7388 else
7389 return 48000;
7390}
7391
7392/* Returns the clock of the currently programmed mode of the given pipe. */
7393static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7394 struct intel_crtc_config *pipe_config)
7395{
7396 struct drm_device *dev = crtc->base.dev;
7397 struct drm_i915_private *dev_priv = dev->dev_private;
7398 int pipe = pipe_config->cpu_transcoder;
7399 u32 dpll = pipe_config->dpll_hw_state.dpll;
7400 u32 fp;
7401 intel_clock_t clock;
7402 int refclk = i9xx_pll_refclk(dev, pipe_config);
7403
7404 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7405 fp = pipe_config->dpll_hw_state.fp0;
7406 else
7407 fp = pipe_config->dpll_hw_state.fp1;
7408
7409 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7410 if (IS_PINEVIEW(dev)) {
7411 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7412 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7413 } else {
7414 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7415 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7416 }
7417
7418 if (!IS_GEN2(dev)) {
7419 if (IS_PINEVIEW(dev))
7420 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7421 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7422 else
7423 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7424 DPLL_FPA01_P1_POST_DIV_SHIFT);
7425
7426 switch (dpll & DPLL_MODE_MASK) {
7427 case DPLLB_MODE_DAC_SERIAL:
7428 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7429 5 : 10;
7430 break;
7431 case DPLLB_MODE_LVDS:
7432 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7433 7 : 14;
7434 break;
7435 default:
7436 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7437 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7438 return;
7439 }
7440
7441 if (IS_PINEVIEW(dev))
7442 pineview_clock(refclk, &clock);
7443 else
7444 i9xx_clock(refclk, &clock);
7445 } else {
7446 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7447
7448 if (is_lvds) {
7449 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7450 DPLL_FPA01_P1_POST_DIV_SHIFT);
7451 clock.p2 = 14;
7452 } else {
7453 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7454 clock.p1 = 2;
7455 else {
7456 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7457 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7458 }
7459 if (dpll & PLL_P2_DIVIDE_BY_4)
7460 clock.p2 = 4;
7461 else
7462 clock.p2 = 2;
7463 }
7464
7465 i9xx_clock(refclk, &clock);
7466 }
7467
7468 /*
7469 * This value includes pixel_multiplier. We will use
7470 * port_clock to compute adjusted_mode.clock in the
7471 * encoder's get_config() function.
7472 */
7473 pipe_config->port_clock = clock.dot;
7474}
7475
7476int intel_dotclock_calculate(int link_freq,
7477 const struct intel_link_m_n *m_n)
7478{
7479 /*
7480 * The calculation for the data clock is:
7481 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7482 * But we want to avoid losing precison if possible, so:
7483 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7484 *
7485 * and the link clock is simpler:
7486 * link_clock = (m * link_clock) / n
7487 */
7488
7489 if (!m_n->link_n)
7490 return 0;
7491
7492 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7493}
7494
7495static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7496 struct intel_crtc_config *pipe_config)
7497{
7498 struct drm_device *dev = crtc->base.dev;
7499
7500 /* read out port_clock from the DPLL */
7501 i9xx_crtc_clock_get(crtc, pipe_config);
7502
7503 /*
7504 * This value does not include pixel_multiplier.
7505 * We will check that port_clock and adjusted_mode.clock
7506 * agree once we know their relationship in the encoder's
7507 * get_config() function.
7508 */
7509 pipe_config->adjusted_mode.clock =
7510 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7511 &pipe_config->fdi_m_n);
7512}
7513
7514/** Returns the currently programmed mode of the given pipe. */
7515struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7516 struct drm_crtc *crtc)
7517{
7518 struct drm_i915_private *dev_priv = dev->dev_private;
7519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7520 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7521 struct drm_display_mode *mode;
7522 struct intel_crtc_config pipe_config;
7523 int htot = I915_READ(HTOTAL(cpu_transcoder));
7524 int hsync = I915_READ(HSYNC(cpu_transcoder));
7525 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7526 int vsync = I915_READ(VSYNC(cpu_transcoder));
7527 enum pipe pipe = intel_crtc->pipe;
7528
7529 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7530 if (!mode)
7531 return NULL;
7532
7533 /*
7534 * Construct a pipe_config sufficient for getting the clock info
7535 * back out of crtc_clock_get.
7536 *
7537 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7538 * to use a real value here instead.
7539 */
7540 pipe_config.cpu_transcoder = (enum transcoder) pipe;
7541 pipe_config.pixel_multiplier = 1;
7542 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7543 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7544 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7545 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7546
7547 mode->clock = pipe_config.adjusted_mode.clock;
7548 mode->hdisplay = (htot & 0xffff) + 1;
7549 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7550 mode->hsync_start = (hsync & 0xffff) + 1;
7551 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7552 mode->vdisplay = (vtot & 0xffff) + 1;
7553 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7554 mode->vsync_start = (vsync & 0xffff) + 1;
7555 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7556
7557 drm_mode_set_name(mode);
7558
7559 return mode;
7560}
7561
7562static void intel_increase_pllclock(struct drm_crtc *crtc)
7563{
7564 struct drm_device *dev = crtc->dev;
7565 drm_i915_private_t *dev_priv = dev->dev_private;
7566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7567 int pipe = intel_crtc->pipe;
7568 int dpll_reg = DPLL(pipe);
7569 int dpll;
7570
7571 if (HAS_PCH_SPLIT(dev))
7572 return;
7573
7574 if (!dev_priv->lvds_downclock_avail)
7575 return;
7576
7577 dpll = I915_READ(dpll_reg);
7578 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7579 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7580
7581 assert_panel_unlocked(dev_priv, pipe);
7582
7583 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7584 I915_WRITE(dpll_reg, dpll);
7585 intel_wait_for_vblank(dev, pipe);
7586
7587 dpll = I915_READ(dpll_reg);
7588 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7589 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7590 }
7591}
7592
7593static void intel_decrease_pllclock(struct drm_crtc *crtc)
7594{
7595 struct drm_device *dev = crtc->dev;
7596 drm_i915_private_t *dev_priv = dev->dev_private;
7597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7598
7599 if (HAS_PCH_SPLIT(dev))
7600 return;
7601
7602 if (!dev_priv->lvds_downclock_avail)
7603 return;
7604
7605 /*
7606 * Since this is called by a timer, we should never get here in
7607 * the manual case.
7608 */
7609 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7610 int pipe = intel_crtc->pipe;
7611 int dpll_reg = DPLL(pipe);
7612 int dpll;
7613
7614 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7615
7616 assert_panel_unlocked(dev_priv, pipe);
7617
7618 dpll = I915_READ(dpll_reg);
7619 dpll |= DISPLAY_RATE_SELECT_FPA1;
7620 I915_WRITE(dpll_reg, dpll);
7621 intel_wait_for_vblank(dev, pipe);
7622 dpll = I915_READ(dpll_reg);
7623 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7624 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7625 }
7626
7627}
7628
7629void intel_mark_busy(struct drm_device *dev)
7630{
7631 struct drm_i915_private *dev_priv = dev->dev_private;
7632
7633 hsw_package_c8_gpu_busy(dev_priv);
7634 i915_update_gfx_val(dev_priv);
7635}
7636
7637void intel_mark_idle(struct drm_device *dev)
7638{
7639 struct drm_i915_private *dev_priv = dev->dev_private;
7640 struct drm_crtc *crtc;
7641
7642 hsw_package_c8_gpu_idle(dev_priv);
7643
7644 if (!i915_powersave)
7645 return;
7646
7647 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7648 if (!crtc->fb)
7649 continue;
7650
7651 intel_decrease_pllclock(crtc);
7652 }
7653}
7654
7655void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7656 struct intel_ring_buffer *ring)
7657{
7658 struct drm_device *dev = obj->base.dev;
7659 struct drm_crtc *crtc;
7660
7661 if (!i915_powersave)
7662 return;
7663
7664 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7665 if (!crtc->fb)
7666 continue;
7667
7668 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7669 continue;
7670
7671 intel_increase_pllclock(crtc);
7672 if (ring && intel_fbc_enabled(dev))
7673 ring->fbc_dirty = true;
7674 }
7675}
7676
7677static void intel_crtc_destroy(struct drm_crtc *crtc)
7678{
7679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7680 struct drm_device *dev = crtc->dev;
7681 struct intel_unpin_work *work;
7682 unsigned long flags;
7683
7684 spin_lock_irqsave(&dev->event_lock, flags);
7685 work = intel_crtc->unpin_work;
7686 intel_crtc->unpin_work = NULL;
7687 spin_unlock_irqrestore(&dev->event_lock, flags);
7688
7689 if (work) {
7690 cancel_work_sync(&work->work);
7691 kfree(work);
7692 }
7693
7694 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7695
7696 drm_crtc_cleanup(crtc);
7697
7698 kfree(intel_crtc);
7699}
7700
7701static void intel_unpin_work_fn(struct work_struct *__work)
7702{
7703 struct intel_unpin_work *work =
7704 container_of(__work, struct intel_unpin_work, work);
7705 struct drm_device *dev = work->crtc->dev;
7706
7707 mutex_lock(&dev->struct_mutex);
7708 intel_unpin_fb_obj(work->old_fb_obj);
7709 drm_gem_object_unreference(&work->pending_flip_obj->base);
7710 drm_gem_object_unreference(&work->old_fb_obj->base);
7711
7712 intel_update_fbc(dev);
7713 mutex_unlock(&dev->struct_mutex);
7714
7715 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7716 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7717
7718 kfree(work);
7719}
7720
7721static void do_intel_finish_page_flip(struct drm_device *dev,
7722 struct drm_crtc *crtc)
7723{
7724 drm_i915_private_t *dev_priv = dev->dev_private;
7725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7726 struct intel_unpin_work *work;
7727 unsigned long flags;
7728
7729 /* Ignore early vblank irqs */
7730 if (intel_crtc == NULL)
7731 return;
7732
7733 spin_lock_irqsave(&dev->event_lock, flags);
7734 work = intel_crtc->unpin_work;
7735
7736 /* Ensure we don't miss a work->pending update ... */
7737 smp_rmb();
7738
7739 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7740 spin_unlock_irqrestore(&dev->event_lock, flags);
7741 return;
7742 }
7743
7744 /* and that the unpin work is consistent wrt ->pending. */
7745 smp_rmb();
7746
7747 intel_crtc->unpin_work = NULL;
7748
7749 if (work->event)
7750 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7751
7752 drm_vblank_put(dev, intel_crtc->pipe);
7753
7754 spin_unlock_irqrestore(&dev->event_lock, flags);
7755
7756 wake_up_all(&dev_priv->pending_flip_queue);
7757
7758 queue_work(dev_priv->wq, &work->work);
7759
7760 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7761}
7762
7763void intel_finish_page_flip(struct drm_device *dev, int pipe)
7764{
7765 drm_i915_private_t *dev_priv = dev->dev_private;
7766 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7767
7768 do_intel_finish_page_flip(dev, crtc);
7769}
7770
7771void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7772{
7773 drm_i915_private_t *dev_priv = dev->dev_private;
7774 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7775
7776 do_intel_finish_page_flip(dev, crtc);
7777}
7778
7779void intel_prepare_page_flip(struct drm_device *dev, int plane)
7780{
7781 drm_i915_private_t *dev_priv = dev->dev_private;
7782 struct intel_crtc *intel_crtc =
7783 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7784 unsigned long flags;
7785
7786 /* NB: An MMIO update of the plane base pointer will also
7787 * generate a page-flip completion irq, i.e. every modeset
7788 * is also accompanied by a spurious intel_prepare_page_flip().
7789 */
7790 spin_lock_irqsave(&dev->event_lock, flags);
7791 if (intel_crtc->unpin_work)
7792 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7793 spin_unlock_irqrestore(&dev->event_lock, flags);
7794}
7795
7796inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7797{
7798 /* Ensure that the work item is consistent when activating it ... */
7799 smp_wmb();
7800 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7801 /* and that it is marked active as soon as the irq could fire. */
7802 smp_wmb();
7803}
7804
7805static int intel_gen2_queue_flip(struct drm_device *dev,
7806 struct drm_crtc *crtc,
7807 struct drm_framebuffer *fb,
7808 struct drm_i915_gem_object *obj,
7809 uint32_t flags)
7810{
7811 struct drm_i915_private *dev_priv = dev->dev_private;
7812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7813 u32 flip_mask;
7814 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7815 int ret;
7816
7817 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7818 if (ret)
7819 goto err;
7820
7821 ret = intel_ring_begin(ring, 6);
7822 if (ret)
7823 goto err_unpin;
7824
7825 /* Can't queue multiple flips, so wait for the previous
7826 * one to finish before executing the next.
7827 */
7828 if (intel_crtc->plane)
7829 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7830 else
7831 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7832 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7833 intel_ring_emit(ring, MI_NOOP);
7834 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7835 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7836 intel_ring_emit(ring, fb->pitches[0]);
7837 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7838 intel_ring_emit(ring, 0); /* aux display base address, unused */
7839
7840 intel_mark_page_flip_active(intel_crtc);
7841 __intel_ring_advance(ring);
7842 return 0;
7843
7844err_unpin:
7845 intel_unpin_fb_obj(obj);
7846err:
7847 return ret;
7848}
7849
7850static int intel_gen3_queue_flip(struct drm_device *dev,
7851 struct drm_crtc *crtc,
7852 struct drm_framebuffer *fb,
7853 struct drm_i915_gem_object *obj,
7854 uint32_t flags)
7855{
7856 struct drm_i915_private *dev_priv = dev->dev_private;
7857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7858 u32 flip_mask;
7859 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7860 int ret;
7861
7862 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7863 if (ret)
7864 goto err;
7865
7866 ret = intel_ring_begin(ring, 6);
7867 if (ret)
7868 goto err_unpin;
7869
7870 if (intel_crtc->plane)
7871 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7872 else
7873 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7874 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7875 intel_ring_emit(ring, MI_NOOP);
7876 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7877 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7878 intel_ring_emit(ring, fb->pitches[0]);
7879 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7880 intel_ring_emit(ring, MI_NOOP);
7881
7882 intel_mark_page_flip_active(intel_crtc);
7883 __intel_ring_advance(ring);
7884 return 0;
7885
7886err_unpin:
7887 intel_unpin_fb_obj(obj);
7888err:
7889 return ret;
7890}
7891
7892static int intel_gen4_queue_flip(struct drm_device *dev,
7893 struct drm_crtc *crtc,
7894 struct drm_framebuffer *fb,
7895 struct drm_i915_gem_object *obj,
7896 uint32_t flags)
7897{
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7900 uint32_t pf, pipesrc;
7901 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7902 int ret;
7903
7904 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7905 if (ret)
7906 goto err;
7907
7908 ret = intel_ring_begin(ring, 4);
7909 if (ret)
7910 goto err_unpin;
7911
7912 /* i965+ uses the linear or tiled offsets from the
7913 * Display Registers (which do not change across a page-flip)
7914 * so we need only reprogram the base address.
7915 */
7916 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7917 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7918 intel_ring_emit(ring, fb->pitches[0]);
7919 intel_ring_emit(ring,
7920 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7921 obj->tiling_mode);
7922
7923 /* XXX Enabling the panel-fitter across page-flip is so far
7924 * untested on non-native modes, so ignore it for now.
7925 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7926 */
7927 pf = 0;
7928 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7929 intel_ring_emit(ring, pf | pipesrc);
7930
7931 intel_mark_page_flip_active(intel_crtc);
7932 __intel_ring_advance(ring);
7933 return 0;
7934
7935err_unpin:
7936 intel_unpin_fb_obj(obj);
7937err:
7938 return ret;
7939}
7940
7941static int intel_gen6_queue_flip(struct drm_device *dev,
7942 struct drm_crtc *crtc,
7943 struct drm_framebuffer *fb,
7944 struct drm_i915_gem_object *obj,
7945 uint32_t flags)
7946{
7947 struct drm_i915_private *dev_priv = dev->dev_private;
7948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7949 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7950 uint32_t pf, pipesrc;
7951 int ret;
7952
7953 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7954 if (ret)
7955 goto err;
7956
7957 ret = intel_ring_begin(ring, 4);
7958 if (ret)
7959 goto err_unpin;
7960
7961 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7962 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7963 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7964 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7965
7966 /* Contrary to the suggestions in the documentation,
7967 * "Enable Panel Fitter" does not seem to be required when page
7968 * flipping with a non-native mode, and worse causes a normal
7969 * modeset to fail.
7970 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7971 */
7972 pf = 0;
7973 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7974 intel_ring_emit(ring, pf | pipesrc);
7975
7976 intel_mark_page_flip_active(intel_crtc);
7977 __intel_ring_advance(ring);
7978 return 0;
7979
7980err_unpin:
7981 intel_unpin_fb_obj(obj);
7982err:
7983 return ret;
7984}
7985
7986static int intel_gen7_queue_flip(struct drm_device *dev,
7987 struct drm_crtc *crtc,
7988 struct drm_framebuffer *fb,
7989 struct drm_i915_gem_object *obj,
7990 uint32_t flags)
7991{
7992 struct drm_i915_private *dev_priv = dev->dev_private;
7993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7994 struct intel_ring_buffer *ring;
7995 uint32_t plane_bit = 0;
7996 int len, ret;
7997
7998 ring = obj->ring;
7999 if (ring == NULL || ring->id != RCS)
8000 ring = &dev_priv->ring[BCS];
8001
8002 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8003 if (ret)
8004 goto err;
8005
8006 switch(intel_crtc->plane) {
8007 case PLANE_A:
8008 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8009 break;
8010 case PLANE_B:
8011 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8012 break;
8013 case PLANE_C:
8014 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8015 break;
8016 default:
8017 WARN_ONCE(1, "unknown plane in flip command\n");
8018 ret = -ENODEV;
8019 goto err_unpin;
8020 }
8021
8022 len = 4;
8023 if (ring->id == RCS)
8024 len += 6;
8025
8026 ret = intel_ring_begin(ring, len);
8027 if (ret)
8028 goto err_unpin;
8029
8030 /* Unmask the flip-done completion message. Note that the bspec says that
8031 * we should do this for both the BCS and RCS, and that we must not unmask
8032 * more than one flip event at any time (or ensure that one flip message
8033 * can be sent by waiting for flip-done prior to queueing new flips).
8034 * Experimentation says that BCS works despite DERRMR masking all
8035 * flip-done completion events and that unmasking all planes at once
8036 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8037 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8038 */
8039 if (ring->id == RCS) {
8040 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8041 intel_ring_emit(ring, DERRMR);
8042 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8043 DERRMR_PIPEB_PRI_FLIP_DONE |
8044 DERRMR_PIPEC_PRI_FLIP_DONE));
8045 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8046 intel_ring_emit(ring, DERRMR);
8047 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8048 }
8049
8050 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8051 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8052 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8053 intel_ring_emit(ring, (MI_NOOP));
8054
8055 intel_mark_page_flip_active(intel_crtc);
8056 __intel_ring_advance(ring);
8057 return 0;
8058
8059err_unpin:
8060 intel_unpin_fb_obj(obj);
8061err:
8062 return ret;
8063}
8064
8065static int intel_default_queue_flip(struct drm_device *dev,
8066 struct drm_crtc *crtc,
8067 struct drm_framebuffer *fb,
8068 struct drm_i915_gem_object *obj,
8069 uint32_t flags)
8070{
8071 return -ENODEV;
8072}
8073
8074static int intel_crtc_page_flip(struct drm_crtc *crtc,
8075 struct drm_framebuffer *fb,
8076 struct drm_pending_vblank_event *event,
8077 uint32_t page_flip_flags)
8078{
8079 struct drm_device *dev = crtc->dev;
8080 struct drm_i915_private *dev_priv = dev->dev_private;
8081 struct drm_framebuffer *old_fb = crtc->fb;
8082 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8084 struct intel_unpin_work *work;
8085 unsigned long flags;
8086 int ret;
8087
8088 /* Can't change pixel format via MI display flips. */
8089 if (fb->pixel_format != crtc->fb->pixel_format)
8090 return -EINVAL;
8091
8092 /*
8093 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8094 * Note that pitch changes could also affect these register.
8095 */
8096 if (INTEL_INFO(dev)->gen > 3 &&
8097 (fb->offsets[0] != crtc->fb->offsets[0] ||
8098 fb->pitches[0] != crtc->fb->pitches[0]))
8099 return -EINVAL;
8100
8101 work = kzalloc(sizeof *work, GFP_KERNEL);
8102 if (work == NULL)
8103 return -ENOMEM;
8104
8105 work->event = event;
8106 work->crtc = crtc;
8107 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8108 INIT_WORK(&work->work, intel_unpin_work_fn);
8109
8110 ret = drm_vblank_get(dev, intel_crtc->pipe);
8111 if (ret)
8112 goto free_work;
8113
8114 /* We borrow the event spin lock for protecting unpin_work */
8115 spin_lock_irqsave(&dev->event_lock, flags);
8116 if (intel_crtc->unpin_work) {
8117 spin_unlock_irqrestore(&dev->event_lock, flags);
8118 kfree(work);
8119 drm_vblank_put(dev, intel_crtc->pipe);
8120
8121 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8122 return -EBUSY;
8123 }
8124 intel_crtc->unpin_work = work;
8125 spin_unlock_irqrestore(&dev->event_lock, flags);
8126
8127 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8128 flush_workqueue(dev_priv->wq);
8129
8130 ret = i915_mutex_lock_interruptible(dev);
8131 if (ret)
8132 goto cleanup;
8133
8134 /* Reference the objects for the scheduled work. */
8135 drm_gem_object_reference(&work->old_fb_obj->base);
8136 drm_gem_object_reference(&obj->base);
8137
8138 crtc->fb = fb;
8139
8140 work->pending_flip_obj = obj;
8141
8142 work->enable_stall_check = true;
8143
8144 atomic_inc(&intel_crtc->unpin_work_count);
8145 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8146
8147 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8148 if (ret)
8149 goto cleanup_pending;
8150
8151 intel_disable_fbc(dev);
8152 intel_mark_fb_busy(obj, NULL);
8153 mutex_unlock(&dev->struct_mutex);
8154
8155 trace_i915_flip_request(intel_crtc->plane, obj);
8156
8157 return 0;
8158
8159cleanup_pending:
8160 atomic_dec(&intel_crtc->unpin_work_count);
8161 crtc->fb = old_fb;
8162 drm_gem_object_unreference(&work->old_fb_obj->base);
8163 drm_gem_object_unreference(&obj->base);
8164 mutex_unlock(&dev->struct_mutex);
8165
8166cleanup:
8167 spin_lock_irqsave(&dev->event_lock, flags);
8168 intel_crtc->unpin_work = NULL;
8169 spin_unlock_irqrestore(&dev->event_lock, flags);
8170
8171 drm_vblank_put(dev, intel_crtc->pipe);
8172free_work:
8173 kfree(work);
8174
8175 return ret;
8176}
8177
8178static struct drm_crtc_helper_funcs intel_helper_funcs = {
8179 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8180 .load_lut = intel_crtc_load_lut,
8181};
8182
8183static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8184 struct drm_crtc *crtc)
8185{
8186 struct drm_device *dev;
8187 struct drm_crtc *tmp;
8188 int crtc_mask = 1;
8189
8190 WARN(!crtc, "checking null crtc?\n");
8191
8192 dev = crtc->dev;
8193
8194 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8195 if (tmp == crtc)
8196 break;
8197 crtc_mask <<= 1;
8198 }
8199
8200 if (encoder->possible_crtcs & crtc_mask)
8201 return true;
8202 return false;
8203}
8204
8205/**
8206 * intel_modeset_update_staged_output_state
8207 *
8208 * Updates the staged output configuration state, e.g. after we've read out the
8209 * current hw state.
8210 */
8211static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8212{
8213 struct intel_encoder *encoder;
8214 struct intel_connector *connector;
8215
8216 list_for_each_entry(connector, &dev->mode_config.connector_list,
8217 base.head) {
8218 connector->new_encoder =
8219 to_intel_encoder(connector->base.encoder);
8220 }
8221
8222 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8223 base.head) {
8224 encoder->new_crtc =
8225 to_intel_crtc(encoder->base.crtc);
8226 }
8227}
8228
8229/**
8230 * intel_modeset_commit_output_state
8231 *
8232 * This function copies the stage display pipe configuration to the real one.
8233 */
8234static void intel_modeset_commit_output_state(struct drm_device *dev)
8235{
8236 struct intel_encoder *encoder;
8237 struct intel_connector *connector;
8238
8239 list_for_each_entry(connector, &dev->mode_config.connector_list,
8240 base.head) {
8241 connector->base.encoder = &connector->new_encoder->base;
8242 }
8243
8244 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8245 base.head) {
8246 encoder->base.crtc = &encoder->new_crtc->base;
8247 }
8248}
8249
8250static void
8251connected_sink_compute_bpp(struct intel_connector * connector,
8252 struct intel_crtc_config *pipe_config)
8253{
8254 int bpp = pipe_config->pipe_bpp;
8255
8256 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8257 connector->base.base.id,
8258 drm_get_connector_name(&connector->base));
8259
8260 /* Don't use an invalid EDID bpc value */
8261 if (connector->base.display_info.bpc &&
8262 connector->base.display_info.bpc * 3 < bpp) {
8263 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8264 bpp, connector->base.display_info.bpc*3);
8265 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8266 }
8267
8268 /* Clamp bpp to 8 on screens without EDID 1.4 */
8269 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8270 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8271 bpp);
8272 pipe_config->pipe_bpp = 24;
8273 }
8274}
8275
8276static int
8277compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8278 struct drm_framebuffer *fb,
8279 struct intel_crtc_config *pipe_config)
8280{
8281 struct drm_device *dev = crtc->base.dev;
8282 struct intel_connector *connector;
8283 int bpp;
8284
8285 switch (fb->pixel_format) {
8286 case DRM_FORMAT_C8:
8287 bpp = 8*3; /* since we go through a colormap */
8288 break;
8289 case DRM_FORMAT_XRGB1555:
8290 case DRM_FORMAT_ARGB1555:
8291 /* checked in intel_framebuffer_init already */
8292 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8293 return -EINVAL;
8294 case DRM_FORMAT_RGB565:
8295 bpp = 6*3; /* min is 18bpp */
8296 break;
8297 case DRM_FORMAT_XBGR8888:
8298 case DRM_FORMAT_ABGR8888:
8299 /* checked in intel_framebuffer_init already */
8300 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8301 return -EINVAL;
8302 case DRM_FORMAT_XRGB8888:
8303 case DRM_FORMAT_ARGB8888:
8304 bpp = 8*3;
8305 break;
8306 case DRM_FORMAT_XRGB2101010:
8307 case DRM_FORMAT_ARGB2101010:
8308 case DRM_FORMAT_XBGR2101010:
8309 case DRM_FORMAT_ABGR2101010:
8310 /* checked in intel_framebuffer_init already */
8311 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8312 return -EINVAL;
8313 bpp = 10*3;
8314 break;
8315 /* TODO: gen4+ supports 16 bpc floating point, too. */
8316 default:
8317 DRM_DEBUG_KMS("unsupported depth\n");
8318 return -EINVAL;
8319 }
8320
8321 pipe_config->pipe_bpp = bpp;
8322
8323 /* Clamp display bpp to EDID value */
8324 list_for_each_entry(connector, &dev->mode_config.connector_list,
8325 base.head) {
8326 if (!connector->new_encoder ||
8327 connector->new_encoder->new_crtc != crtc)
8328 continue;
8329
8330 connected_sink_compute_bpp(connector, pipe_config);
8331 }
8332
8333 return bpp;
8334}
8335
8336static void intel_dump_pipe_config(struct intel_crtc *crtc,
8337 struct intel_crtc_config *pipe_config,
8338 const char *context)
8339{
8340 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8341 context, pipe_name(crtc->pipe));
8342
8343 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8344 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8345 pipe_config->pipe_bpp, pipe_config->dither);
8346 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8347 pipe_config->has_pch_encoder,
8348 pipe_config->fdi_lanes,
8349 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8350 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8351 pipe_config->fdi_m_n.tu);
8352 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8353 pipe_config->has_dp_encoder,
8354 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8355 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8356 pipe_config->dp_m_n.tu);
8357 DRM_DEBUG_KMS("requested mode:\n");
8358 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8359 DRM_DEBUG_KMS("adjusted mode:\n");
8360 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8361 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8362 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8363 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8364 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8365 pipe_config->gmch_pfit.control,
8366 pipe_config->gmch_pfit.pgm_ratios,
8367 pipe_config->gmch_pfit.lvds_border_bits);
8368 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8369 pipe_config->pch_pfit.pos,
8370 pipe_config->pch_pfit.size);
8371 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8372 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8373}
8374
8375static bool check_encoder_cloning(struct drm_crtc *crtc)
8376{
8377 int num_encoders = 0;
8378 bool uncloneable_encoders = false;
8379 struct intel_encoder *encoder;
8380
8381 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8382 base.head) {
8383 if (&encoder->new_crtc->base != crtc)
8384 continue;
8385
8386 num_encoders++;
8387 if (!encoder->cloneable)
8388 uncloneable_encoders = true;
8389 }
8390
8391 return !(num_encoders > 1 && uncloneable_encoders);
8392}
8393
8394static struct intel_crtc_config *
8395intel_modeset_pipe_config(struct drm_crtc *crtc,
8396 struct drm_framebuffer *fb,
8397 struct drm_display_mode *mode)
8398{
8399 struct drm_device *dev = crtc->dev;
8400 struct intel_encoder *encoder;
8401 struct intel_crtc_config *pipe_config;
8402 int plane_bpp, ret = -EINVAL;
8403 bool retry = true;
8404
8405 if (!check_encoder_cloning(crtc)) {
8406 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8407 return ERR_PTR(-EINVAL);
8408 }
8409
8410 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8411 if (!pipe_config)
8412 return ERR_PTR(-ENOMEM);
8413
8414 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8415 drm_mode_copy(&pipe_config->requested_mode, mode);
8416
8417 pipe_config->pipe_src_w = mode->hdisplay;
8418 pipe_config->pipe_src_h = mode->vdisplay;
8419
8420 pipe_config->cpu_transcoder =
8421 (enum transcoder) to_intel_crtc(crtc)->pipe;
8422 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8423
8424 /*
8425 * Sanitize sync polarity flags based on requested ones. If neither
8426 * positive or negative polarity is requested, treat this as meaning
8427 * negative polarity.
8428 */
8429 if (!(pipe_config->adjusted_mode.flags &
8430 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8431 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8432
8433 if (!(pipe_config->adjusted_mode.flags &
8434 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8435 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8436
8437 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8438 * plane pixel format and any sink constraints into account. Returns the
8439 * source plane bpp so that dithering can be selected on mismatches
8440 * after encoders and crtc also have had their say. */
8441 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8442 fb, pipe_config);
8443 if (plane_bpp < 0)
8444 goto fail;
8445
8446encoder_retry:
8447 /* Ensure the port clock defaults are reset when retrying. */
8448 pipe_config->port_clock = 0;
8449 pipe_config->pixel_multiplier = 1;
8450
8451 /* Fill in default crtc timings, allow encoders to overwrite them. */
8452 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8453
8454 /* Pass our mode to the connectors and the CRTC to give them a chance to
8455 * adjust it according to limitations or connector properties, and also
8456 * a chance to reject the mode entirely.
8457 */
8458 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8459 base.head) {
8460
8461 if (&encoder->new_crtc->base != crtc)
8462 continue;
8463
8464 if (!(encoder->compute_config(encoder, pipe_config))) {
8465 DRM_DEBUG_KMS("Encoder config failure\n");
8466 goto fail;
8467 }
8468 }
8469
8470 /* Set default port clock if not overwritten by the encoder. Needs to be
8471 * done afterwards in case the encoder adjusts the mode. */
8472 if (!pipe_config->port_clock)
8473 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8474 pipe_config->pixel_multiplier;
8475
8476 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8477 if (ret < 0) {
8478 DRM_DEBUG_KMS("CRTC fixup failed\n");
8479 goto fail;
8480 }
8481
8482 if (ret == RETRY) {
8483 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8484 ret = -EINVAL;
8485 goto fail;
8486 }
8487
8488 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8489 retry = false;
8490 goto encoder_retry;
8491 }
8492
8493 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8494 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8495 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8496
8497 return pipe_config;
8498fail:
8499 kfree(pipe_config);
8500 return ERR_PTR(ret);
8501}
8502
8503/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8504 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8505static void
8506intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8507 unsigned *prepare_pipes, unsigned *disable_pipes)
8508{
8509 struct intel_crtc *intel_crtc;
8510 struct drm_device *dev = crtc->dev;
8511 struct intel_encoder *encoder;
8512 struct intel_connector *connector;
8513 struct drm_crtc *tmp_crtc;
8514
8515 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8516
8517 /* Check which crtcs have changed outputs connected to them, these need
8518 * to be part of the prepare_pipes mask. We don't (yet) support global
8519 * modeset across multiple crtcs, so modeset_pipes will only have one
8520 * bit set at most. */
8521 list_for_each_entry(connector, &dev->mode_config.connector_list,
8522 base.head) {
8523 if (connector->base.encoder == &connector->new_encoder->base)
8524 continue;
8525
8526 if (connector->base.encoder) {
8527 tmp_crtc = connector->base.encoder->crtc;
8528
8529 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8530 }
8531
8532 if (connector->new_encoder)
8533 *prepare_pipes |=
8534 1 << connector->new_encoder->new_crtc->pipe;
8535 }
8536
8537 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8538 base.head) {
8539 if (encoder->base.crtc == &encoder->new_crtc->base)
8540 continue;
8541
8542 if (encoder->base.crtc) {
8543 tmp_crtc = encoder->base.crtc;
8544
8545 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8546 }
8547
8548 if (encoder->new_crtc)
8549 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8550 }
8551
8552 /* Check for any pipes that will be fully disabled ... */
8553 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8554 base.head) {
8555 bool used = false;
8556
8557 /* Don't try to disable disabled crtcs. */
8558 if (!intel_crtc->base.enabled)
8559 continue;
8560
8561 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8562 base.head) {
8563 if (encoder->new_crtc == intel_crtc)
8564 used = true;
8565 }
8566
8567 if (!used)
8568 *disable_pipes |= 1 << intel_crtc->pipe;
8569 }
8570
8571
8572 /* set_mode is also used to update properties on life display pipes. */
8573 intel_crtc = to_intel_crtc(crtc);
8574 if (crtc->enabled)
8575 *prepare_pipes |= 1 << intel_crtc->pipe;
8576
8577 /*
8578 * For simplicity do a full modeset on any pipe where the output routing
8579 * changed. We could be more clever, but that would require us to be
8580 * more careful with calling the relevant encoder->mode_set functions.
8581 */
8582 if (*prepare_pipes)
8583 *modeset_pipes = *prepare_pipes;
8584
8585 /* ... and mask these out. */
8586 *modeset_pipes &= ~(*disable_pipes);
8587 *prepare_pipes &= ~(*disable_pipes);
8588
8589 /*
8590 * HACK: We don't (yet) fully support global modesets. intel_set_config
8591 * obies this rule, but the modeset restore mode of
8592 * intel_modeset_setup_hw_state does not.
8593 */
8594 *modeset_pipes &= 1 << intel_crtc->pipe;
8595 *prepare_pipes &= 1 << intel_crtc->pipe;
8596
8597 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8598 *modeset_pipes, *prepare_pipes, *disable_pipes);
8599}
8600
8601static bool intel_crtc_in_use(struct drm_crtc *crtc)
8602{
8603 struct drm_encoder *encoder;
8604 struct drm_device *dev = crtc->dev;
8605
8606 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8607 if (encoder->crtc == crtc)
8608 return true;
8609
8610 return false;
8611}
8612
8613static void
8614intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8615{
8616 struct intel_encoder *intel_encoder;
8617 struct intel_crtc *intel_crtc;
8618 struct drm_connector *connector;
8619
8620 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8621 base.head) {
8622 if (!intel_encoder->base.crtc)
8623 continue;
8624
8625 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8626
8627 if (prepare_pipes & (1 << intel_crtc->pipe))
8628 intel_encoder->connectors_active = false;
8629 }
8630
8631 intel_modeset_commit_output_state(dev);
8632
8633 /* Update computed state. */
8634 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8635 base.head) {
8636 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8637 }
8638
8639 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8640 if (!connector->encoder || !connector->encoder->crtc)
8641 continue;
8642
8643 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8644
8645 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8646 struct drm_property *dpms_property =
8647 dev->mode_config.dpms_property;
8648
8649 connector->dpms = DRM_MODE_DPMS_ON;
8650 drm_object_property_set_value(&connector->base,
8651 dpms_property,
8652 DRM_MODE_DPMS_ON);
8653
8654 intel_encoder = to_intel_encoder(connector->encoder);
8655 intel_encoder->connectors_active = true;
8656 }
8657 }
8658
8659}
8660
8661static bool intel_fuzzy_clock_check(int clock1, int clock2)
8662{
8663 int diff;
8664
8665 if (clock1 == clock2)
8666 return true;
8667
8668 if (!clock1 || !clock2)
8669 return false;
8670
8671 diff = abs(clock1 - clock2);
8672
8673 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8674 return true;
8675
8676 return false;
8677}
8678
8679#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8680 list_for_each_entry((intel_crtc), \
8681 &(dev)->mode_config.crtc_list, \
8682 base.head) \
8683 if (mask & (1 <<(intel_crtc)->pipe))
8684
8685static bool
8686intel_pipe_config_compare(struct drm_device *dev,
8687 struct intel_crtc_config *current_config,
8688 struct intel_crtc_config *pipe_config)
8689{
8690#define PIPE_CONF_CHECK_X(name) \
8691 if (current_config->name != pipe_config->name) { \
8692 DRM_ERROR("mismatch in " #name " " \
8693 "(expected 0x%08x, found 0x%08x)\n", \
8694 current_config->name, \
8695 pipe_config->name); \
8696 return false; \
8697 }
8698
8699#define PIPE_CONF_CHECK_I(name) \
8700 if (current_config->name != pipe_config->name) { \
8701 DRM_ERROR("mismatch in " #name " " \
8702 "(expected %i, found %i)\n", \
8703 current_config->name, \
8704 pipe_config->name); \
8705 return false; \
8706 }
8707
8708#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8709 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8710 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8711 "(expected %i, found %i)\n", \
8712 current_config->name & (mask), \
8713 pipe_config->name & (mask)); \
8714 return false; \
8715 }
8716
8717#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8718 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8719 DRM_ERROR("mismatch in " #name " " \
8720 "(expected %i, found %i)\n", \
8721 current_config->name, \
8722 pipe_config->name); \
8723 return false; \
8724 }
8725
8726#define PIPE_CONF_QUIRK(quirk) \
8727 ((current_config->quirks | pipe_config->quirks) & (quirk))
8728
8729 PIPE_CONF_CHECK_I(cpu_transcoder);
8730
8731 PIPE_CONF_CHECK_I(has_pch_encoder);
8732 PIPE_CONF_CHECK_I(fdi_lanes);
8733 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8734 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8735 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8736 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8737 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8738
8739 PIPE_CONF_CHECK_I(has_dp_encoder);
8740 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8741 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8742 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8743 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8744 PIPE_CONF_CHECK_I(dp_m_n.tu);
8745
8746 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8747 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8748 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8749 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8750 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8751 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8752
8753 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8754 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8755 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8756 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8757 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8758 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8759
8760 PIPE_CONF_CHECK_I(pixel_multiplier);
8761
8762 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8763 DRM_MODE_FLAG_INTERLACE);
8764
8765 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8766 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8767 DRM_MODE_FLAG_PHSYNC);
8768 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8769 DRM_MODE_FLAG_NHSYNC);
8770 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8771 DRM_MODE_FLAG_PVSYNC);
8772 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8773 DRM_MODE_FLAG_NVSYNC);
8774 }
8775
8776 PIPE_CONF_CHECK_I(pipe_src_w);
8777 PIPE_CONF_CHECK_I(pipe_src_h);
8778
8779 PIPE_CONF_CHECK_I(gmch_pfit.control);
8780 /* pfit ratios are autocomputed by the hw on gen4+ */
8781 if (INTEL_INFO(dev)->gen < 4)
8782 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8783 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8784 PIPE_CONF_CHECK_I(pch_pfit.pos);
8785 PIPE_CONF_CHECK_I(pch_pfit.size);
8786
8787 PIPE_CONF_CHECK_I(ips_enabled);
8788
8789 PIPE_CONF_CHECK_I(double_wide);
8790
8791 PIPE_CONF_CHECK_I(shared_dpll);
8792 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8793 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8794 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8795 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8796
8797 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8798 PIPE_CONF_CHECK_I(pipe_bpp);
8799
8800 if (!IS_HASWELL(dev)) {
8801 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
8802 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8803 }
8804
8805#undef PIPE_CONF_CHECK_X
8806#undef PIPE_CONF_CHECK_I
8807#undef PIPE_CONF_CHECK_FLAGS
8808#undef PIPE_CONF_CHECK_CLOCK_FUZZY
8809#undef PIPE_CONF_QUIRK
8810
8811 return true;
8812}
8813
8814static void
8815check_connector_state(struct drm_device *dev)
8816{
8817 struct intel_connector *connector;
8818
8819 list_for_each_entry(connector, &dev->mode_config.connector_list,
8820 base.head) {
8821 /* This also checks the encoder/connector hw state with the
8822 * ->get_hw_state callbacks. */
8823 intel_connector_check_state(connector);
8824
8825 WARN(&connector->new_encoder->base != connector->base.encoder,
8826 "connector's staged encoder doesn't match current encoder\n");
8827 }
8828}
8829
8830static void
8831check_encoder_state(struct drm_device *dev)
8832{
8833 struct intel_encoder *encoder;
8834 struct intel_connector *connector;
8835
8836 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8837 base.head) {
8838 bool enabled = false;
8839 bool active = false;
8840 enum pipe pipe, tracked_pipe;
8841
8842 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8843 encoder->base.base.id,
8844 drm_get_encoder_name(&encoder->base));
8845
8846 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8847 "encoder's stage crtc doesn't match current crtc\n");
8848 WARN(encoder->connectors_active && !encoder->base.crtc,
8849 "encoder's active_connectors set, but no crtc\n");
8850
8851 list_for_each_entry(connector, &dev->mode_config.connector_list,
8852 base.head) {
8853 if (connector->base.encoder != &encoder->base)
8854 continue;
8855 enabled = true;
8856 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8857 active = true;
8858 }
8859 WARN(!!encoder->base.crtc != enabled,
8860 "encoder's enabled state mismatch "
8861 "(expected %i, found %i)\n",
8862 !!encoder->base.crtc, enabled);
8863 WARN(active && !encoder->base.crtc,
8864 "active encoder with no crtc\n");
8865
8866 WARN(encoder->connectors_active != active,
8867 "encoder's computed active state doesn't match tracked active state "
8868 "(expected %i, found %i)\n", active, encoder->connectors_active);
8869
8870 active = encoder->get_hw_state(encoder, &pipe);
8871 WARN(active != encoder->connectors_active,
8872 "encoder's hw state doesn't match sw tracking "
8873 "(expected %i, found %i)\n",
8874 encoder->connectors_active, active);
8875
8876 if (!encoder->base.crtc)
8877 continue;
8878
8879 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8880 WARN(active && pipe != tracked_pipe,
8881 "active encoder's pipe doesn't match"
8882 "(expected %i, found %i)\n",
8883 tracked_pipe, pipe);
8884
8885 }
8886}
8887
8888static void
8889check_crtc_state(struct drm_device *dev)
8890{
8891 drm_i915_private_t *dev_priv = dev->dev_private;
8892 struct intel_crtc *crtc;
8893 struct intel_encoder *encoder;
8894 struct intel_crtc_config pipe_config;
8895
8896 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8897 base.head) {
8898 bool enabled = false;
8899 bool active = false;
8900
8901 memset(&pipe_config, 0, sizeof(pipe_config));
8902
8903 DRM_DEBUG_KMS("[CRTC:%d]\n",
8904 crtc->base.base.id);
8905
8906 WARN(crtc->active && !crtc->base.enabled,
8907 "active crtc, but not enabled in sw tracking\n");
8908
8909 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8910 base.head) {
8911 if (encoder->base.crtc != &crtc->base)
8912 continue;
8913 enabled = true;
8914 if (encoder->connectors_active)
8915 active = true;
8916 }
8917
8918 WARN(active != crtc->active,
8919 "crtc's computed active state doesn't match tracked active state "
8920 "(expected %i, found %i)\n", active, crtc->active);
8921 WARN(enabled != crtc->base.enabled,
8922 "crtc's computed enabled state doesn't match tracked enabled state "
8923 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8924
8925 active = dev_priv->display.get_pipe_config(crtc,
8926 &pipe_config);
8927
8928 /* hw state is inconsistent with the pipe A quirk */
8929 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8930 active = crtc->active;
8931
8932 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8933 base.head) {
8934 enum pipe pipe;
8935 if (encoder->base.crtc != &crtc->base)
8936 continue;
8937 if (encoder->get_config &&
8938 encoder->get_hw_state(encoder, &pipe))
8939 encoder->get_config(encoder, &pipe_config);
8940 }
8941
8942 WARN(crtc->active != active,
8943 "crtc active state doesn't match with hw state "
8944 "(expected %i, found %i)\n", crtc->active, active);
8945
8946 if (active &&
8947 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8948 WARN(1, "pipe state doesn't match!\n");
8949 intel_dump_pipe_config(crtc, &pipe_config,
8950 "[hw state]");
8951 intel_dump_pipe_config(crtc, &crtc->config,
8952 "[sw state]");
8953 }
8954 }
8955}
8956
8957static void
8958check_shared_dpll_state(struct drm_device *dev)
8959{
8960 drm_i915_private_t *dev_priv = dev->dev_private;
8961 struct intel_crtc *crtc;
8962 struct intel_dpll_hw_state dpll_hw_state;
8963 int i;
8964
8965 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8966 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8967 int enabled_crtcs = 0, active_crtcs = 0;
8968 bool active;
8969
8970 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8971
8972 DRM_DEBUG_KMS("%s\n", pll->name);
8973
8974 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8975
8976 WARN(pll->active > pll->refcount,
8977 "more active pll users than references: %i vs %i\n",
8978 pll->active, pll->refcount);
8979 WARN(pll->active && !pll->on,
8980 "pll in active use but not on in sw tracking\n");
8981 WARN(pll->on && !pll->active,
8982 "pll in on but not on in use in sw tracking\n");
8983 WARN(pll->on != active,
8984 "pll on state mismatch (expected %i, found %i)\n",
8985 pll->on, active);
8986
8987 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8988 base.head) {
8989 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8990 enabled_crtcs++;
8991 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8992 active_crtcs++;
8993 }
8994 WARN(pll->active != active_crtcs,
8995 "pll active crtcs mismatch (expected %i, found %i)\n",
8996 pll->active, active_crtcs);
8997 WARN(pll->refcount != enabled_crtcs,
8998 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8999 pll->refcount, enabled_crtcs);
9000
9001 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9002 sizeof(dpll_hw_state)),
9003 "pll hw state mismatch\n");
9004 }
9005}
9006
9007void
9008intel_modeset_check_state(struct drm_device *dev)
9009{
9010 check_connector_state(dev);
9011 check_encoder_state(dev);
9012 check_crtc_state(dev);
9013 check_shared_dpll_state(dev);
9014}
9015
9016void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9017 int dotclock)
9018{
9019 /*
9020 * FDI already provided one idea for the dotclock.
9021 * Yell if the encoder disagrees.
9022 */
9023 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9024 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9025 pipe_config->adjusted_mode.clock, dotclock);
9026}
9027
9028static int __intel_set_mode(struct drm_crtc *crtc,
9029 struct drm_display_mode *mode,
9030 int x, int y, struct drm_framebuffer *fb)
9031{
9032 struct drm_device *dev = crtc->dev;
9033 drm_i915_private_t *dev_priv = dev->dev_private;
9034 struct drm_display_mode *saved_mode, *saved_hwmode;
9035 struct intel_crtc_config *pipe_config = NULL;
9036 struct intel_crtc *intel_crtc;
9037 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9038 int ret = 0;
9039
9040 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
9041 if (!saved_mode)
9042 return -ENOMEM;
9043 saved_hwmode = saved_mode + 1;
9044
9045 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9046 &prepare_pipes, &disable_pipes);
9047
9048 *saved_hwmode = crtc->hwmode;
9049 *saved_mode = crtc->mode;
9050
9051 /* Hack: Because we don't (yet) support global modeset on multiple
9052 * crtcs, we don't keep track of the new mode for more than one crtc.
9053 * Hence simply check whether any bit is set in modeset_pipes in all the
9054 * pieces of code that are not yet converted to deal with mutliple crtcs
9055 * changing their mode at the same time. */
9056 if (modeset_pipes) {
9057 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9058 if (IS_ERR(pipe_config)) {
9059 ret = PTR_ERR(pipe_config);
9060 pipe_config = NULL;
9061
9062 goto out;
9063 }
9064 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9065 "[modeset]");
9066 }
9067
9068 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9069 intel_crtc_disable(&intel_crtc->base);
9070
9071 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9072 if (intel_crtc->base.enabled)
9073 dev_priv->display.crtc_disable(&intel_crtc->base);
9074 }
9075
9076 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9077 * to set it here already despite that we pass it down the callchain.
9078 */
9079 if (modeset_pipes) {
9080 crtc->mode = *mode;
9081 /* mode_set/enable/disable functions rely on a correct pipe
9082 * config. */
9083 to_intel_crtc(crtc)->config = *pipe_config;
9084 }
9085
9086 /* Only after disabling all output pipelines that will be changed can we
9087 * update the the output configuration. */
9088 intel_modeset_update_state(dev, prepare_pipes);
9089
9090 if (dev_priv->display.modeset_global_resources)
9091 dev_priv->display.modeset_global_resources(dev);
9092
9093 /* Set up the DPLL and any encoders state that needs to adjust or depend
9094 * on the DPLL.
9095 */
9096 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9097 ret = intel_crtc_mode_set(&intel_crtc->base,
9098 x, y, fb);
9099 if (ret)
9100 goto done;
9101 }
9102
9103 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9104 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9105 dev_priv->display.crtc_enable(&intel_crtc->base);
9106
9107 if (modeset_pipes) {
9108 /* Store real post-adjustment hardware mode. */
9109 crtc->hwmode = pipe_config->adjusted_mode;
9110
9111 /* Calculate and store various constants which
9112 * are later needed by vblank and swap-completion
9113 * timestamping. They are derived from true hwmode.
9114 */
9115 drm_calc_timestamping_constants(crtc);
9116 }
9117
9118 /* FIXME: add subpixel order */
9119done:
9120 if (ret && crtc->enabled) {
9121 crtc->hwmode = *saved_hwmode;
9122 crtc->mode = *saved_mode;
9123 }
9124
9125out:
9126 kfree(pipe_config);
9127 kfree(saved_mode);
9128 return ret;
9129}
9130
9131static int intel_set_mode(struct drm_crtc *crtc,
9132 struct drm_display_mode *mode,
9133 int x, int y, struct drm_framebuffer *fb)
9134{
9135 int ret;
9136
9137 ret = __intel_set_mode(crtc, mode, x, y, fb);
9138
9139 if (ret == 0)
9140 intel_modeset_check_state(crtc->dev);
9141
9142 return ret;
9143}
9144
9145void intel_crtc_restore_mode(struct drm_crtc *crtc)
9146{
9147 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9148}
9149
9150#undef for_each_intel_crtc_masked
9151
9152static void intel_set_config_free(struct intel_set_config *config)
9153{
9154 if (!config)
9155 return;
9156
9157 kfree(config->save_connector_encoders);
9158 kfree(config->save_encoder_crtcs);
9159 kfree(config);
9160}
9161
9162static int intel_set_config_save_state(struct drm_device *dev,
9163 struct intel_set_config *config)
9164{
9165 struct drm_encoder *encoder;
9166 struct drm_connector *connector;
9167 int count;
9168
9169 config->save_encoder_crtcs =
9170 kcalloc(dev->mode_config.num_encoder,
9171 sizeof(struct drm_crtc *), GFP_KERNEL);
9172 if (!config->save_encoder_crtcs)
9173 return -ENOMEM;
9174
9175 config->save_connector_encoders =
9176 kcalloc(dev->mode_config.num_connector,
9177 sizeof(struct drm_encoder *), GFP_KERNEL);
9178 if (!config->save_connector_encoders)
9179 return -ENOMEM;
9180
9181 /* Copy data. Note that driver private data is not affected.
9182 * Should anything bad happen only the expected state is
9183 * restored, not the drivers personal bookkeeping.
9184 */
9185 count = 0;
9186 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9187 config->save_encoder_crtcs[count++] = encoder->crtc;
9188 }
9189
9190 count = 0;
9191 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9192 config->save_connector_encoders[count++] = connector->encoder;
9193 }
9194
9195 return 0;
9196}
9197
9198static void intel_set_config_restore_state(struct drm_device *dev,
9199 struct intel_set_config *config)
9200{
9201 struct intel_encoder *encoder;
9202 struct intel_connector *connector;
9203 int count;
9204
9205 count = 0;
9206 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9207 encoder->new_crtc =
9208 to_intel_crtc(config->save_encoder_crtcs[count++]);
9209 }
9210
9211 count = 0;
9212 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9213 connector->new_encoder =
9214 to_intel_encoder(config->save_connector_encoders[count++]);
9215 }
9216}
9217
9218static bool
9219is_crtc_connector_off(struct drm_mode_set *set)
9220{
9221 int i;
9222
9223 if (set->num_connectors == 0)
9224 return false;
9225
9226 if (WARN_ON(set->connectors == NULL))
9227 return false;
9228
9229 for (i = 0; i < set->num_connectors; i++)
9230 if (set->connectors[i]->encoder &&
9231 set->connectors[i]->encoder->crtc == set->crtc &&
9232 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9233 return true;
9234
9235 return false;
9236}
9237
9238static void
9239intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9240 struct intel_set_config *config)
9241{
9242
9243 /* We should be able to check here if the fb has the same properties
9244 * and then just flip_or_move it */
9245 if (is_crtc_connector_off(set)) {
9246 config->mode_changed = true;
9247 } else if (set->crtc->fb != set->fb) {
9248 /* If we have no fb then treat it as a full mode set */
9249 if (set->crtc->fb == NULL) {
9250 struct intel_crtc *intel_crtc =
9251 to_intel_crtc(set->crtc);
9252
9253 if (intel_crtc->active && i915_fastboot) {
9254 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9255 config->fb_changed = true;
9256 } else {
9257 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9258 config->mode_changed = true;
9259 }
9260 } else if (set->fb == NULL) {
9261 config->mode_changed = true;
9262 } else if (set->fb->pixel_format !=
9263 set->crtc->fb->pixel_format) {
9264 config->mode_changed = true;
9265 } else {
9266 config->fb_changed = true;
9267 }
9268 }
9269
9270 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9271 config->fb_changed = true;
9272
9273 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9274 DRM_DEBUG_KMS("modes are different, full mode set\n");
9275 drm_mode_debug_printmodeline(&set->crtc->mode);
9276 drm_mode_debug_printmodeline(set->mode);
9277 config->mode_changed = true;
9278 }
9279
9280 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9281 set->crtc->base.id, config->mode_changed, config->fb_changed);
9282}
9283
9284static int
9285intel_modeset_stage_output_state(struct drm_device *dev,
9286 struct drm_mode_set *set,
9287 struct intel_set_config *config)
9288{
9289 struct drm_crtc *new_crtc;
9290 struct intel_connector *connector;
9291 struct intel_encoder *encoder;
9292 int ro;
9293
9294 /* The upper layers ensure that we either disable a crtc or have a list
9295 * of connectors. For paranoia, double-check this. */
9296 WARN_ON(!set->fb && (set->num_connectors != 0));
9297 WARN_ON(set->fb && (set->num_connectors == 0));
9298
9299 list_for_each_entry(connector, &dev->mode_config.connector_list,
9300 base.head) {
9301 /* Otherwise traverse passed in connector list and get encoders
9302 * for them. */
9303 for (ro = 0; ro < set->num_connectors; ro++) {
9304 if (set->connectors[ro] == &connector->base) {
9305 connector->new_encoder = connector->encoder;
9306 break;
9307 }
9308 }
9309
9310 /* If we disable the crtc, disable all its connectors. Also, if
9311 * the connector is on the changing crtc but not on the new
9312 * connector list, disable it. */
9313 if ((!set->fb || ro == set->num_connectors) &&
9314 connector->base.encoder &&
9315 connector->base.encoder->crtc == set->crtc) {
9316 connector->new_encoder = NULL;
9317
9318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9319 connector->base.base.id,
9320 drm_get_connector_name(&connector->base));
9321 }
9322
9323
9324 if (&connector->new_encoder->base != connector->base.encoder) {
9325 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9326 config->mode_changed = true;
9327 }
9328 }
9329 /* connector->new_encoder is now updated for all connectors. */
9330
9331 /* Update crtc of enabled connectors. */
9332 list_for_each_entry(connector, &dev->mode_config.connector_list,
9333 base.head) {
9334 if (!connector->new_encoder)
9335 continue;
9336
9337 new_crtc = connector->new_encoder->base.crtc;
9338
9339 for (ro = 0; ro < set->num_connectors; ro++) {
9340 if (set->connectors[ro] == &connector->base)
9341 new_crtc = set->crtc;
9342 }
9343
9344 /* Make sure the new CRTC will work with the encoder */
9345 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9346 new_crtc)) {
9347 return -EINVAL;
9348 }
9349 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9350
9351 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9352 connector->base.base.id,
9353 drm_get_connector_name(&connector->base),
9354 new_crtc->base.id);
9355 }
9356
9357 /* Check for any encoders that needs to be disabled. */
9358 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9359 base.head) {
9360 list_for_each_entry(connector,
9361 &dev->mode_config.connector_list,
9362 base.head) {
9363 if (connector->new_encoder == encoder) {
9364 WARN_ON(!connector->new_encoder->new_crtc);
9365
9366 goto next_encoder;
9367 }
9368 }
9369 encoder->new_crtc = NULL;
9370next_encoder:
9371 /* Only now check for crtc changes so we don't miss encoders
9372 * that will be disabled. */
9373 if (&encoder->new_crtc->base != encoder->base.crtc) {
9374 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9375 config->mode_changed = true;
9376 }
9377 }
9378 /* Now we've also updated encoder->new_crtc for all encoders. */
9379
9380 return 0;
9381}
9382
9383static int intel_crtc_set_config(struct drm_mode_set *set)
9384{
9385 struct drm_device *dev;
9386 struct drm_mode_set save_set;
9387 struct intel_set_config *config;
9388 int ret;
9389
9390 BUG_ON(!set);
9391 BUG_ON(!set->crtc);
9392 BUG_ON(!set->crtc->helper_private);
9393
9394 /* Enforce sane interface api - has been abused by the fb helper. */
9395 BUG_ON(!set->mode && set->fb);
9396 BUG_ON(set->fb && set->num_connectors == 0);
9397
9398 if (set->fb) {
9399 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9400 set->crtc->base.id, set->fb->base.id,
9401 (int)set->num_connectors, set->x, set->y);
9402 } else {
9403 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9404 }
9405
9406 dev = set->crtc->dev;
9407
9408 ret = -ENOMEM;
9409 config = kzalloc(sizeof(*config), GFP_KERNEL);
9410 if (!config)
9411 goto out_config;
9412
9413 ret = intel_set_config_save_state(dev, config);
9414 if (ret)
9415 goto out_config;
9416
9417 save_set.crtc = set->crtc;
9418 save_set.mode = &set->crtc->mode;
9419 save_set.x = set->crtc->x;
9420 save_set.y = set->crtc->y;
9421 save_set.fb = set->crtc->fb;
9422
9423 /* Compute whether we need a full modeset, only an fb base update or no
9424 * change at all. In the future we might also check whether only the
9425 * mode changed, e.g. for LVDS where we only change the panel fitter in
9426 * such cases. */
9427 intel_set_config_compute_mode_changes(set, config);
9428
9429 ret = intel_modeset_stage_output_state(dev, set, config);
9430 if (ret)
9431 goto fail;
9432
9433 if (config->mode_changed) {
9434 ret = intel_set_mode(set->crtc, set->mode,
9435 set->x, set->y, set->fb);
9436 } else if (config->fb_changed) {
9437 intel_crtc_wait_for_pending_flips(set->crtc);
9438
9439 ret = intel_pipe_set_base(set->crtc,
9440 set->x, set->y, set->fb);
9441 }
9442
9443 if (ret) {
9444 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9445 set->crtc->base.id, ret);
9446fail:
9447 intel_set_config_restore_state(dev, config);
9448
9449 /* Try to restore the config */
9450 if (config->mode_changed &&
9451 intel_set_mode(save_set.crtc, save_set.mode,
9452 save_set.x, save_set.y, save_set.fb))
9453 DRM_ERROR("failed to restore config after modeset failure\n");
9454 }
9455
9456out_config:
9457 intel_set_config_free(config);
9458 return ret;
9459}
9460
9461static const struct drm_crtc_funcs intel_crtc_funcs = {
9462 .cursor_set = intel_crtc_cursor_set,
9463 .cursor_move = intel_crtc_cursor_move,
9464 .gamma_set = intel_crtc_gamma_set,
9465 .set_config = intel_crtc_set_config,
9466 .destroy = intel_crtc_destroy,
9467 .page_flip = intel_crtc_page_flip,
9468};
9469
9470static void intel_cpu_pll_init(struct drm_device *dev)
9471{
9472 if (HAS_DDI(dev))
9473 intel_ddi_pll_init(dev);
9474}
9475
9476static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9477 struct intel_shared_dpll *pll,
9478 struct intel_dpll_hw_state *hw_state)
9479{
9480 uint32_t val;
9481
9482 val = I915_READ(PCH_DPLL(pll->id));
9483 hw_state->dpll = val;
9484 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9485 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9486
9487 return val & DPLL_VCO_ENABLE;
9488}
9489
9490static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9491 struct intel_shared_dpll *pll)
9492{
9493 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9494 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9495}
9496
9497static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9498 struct intel_shared_dpll *pll)
9499{
9500 /* PCH refclock must be enabled first */
9501 assert_pch_refclk_enabled(dev_priv);
9502
9503 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9504
9505 /* Wait for the clocks to stabilize. */
9506 POSTING_READ(PCH_DPLL(pll->id));
9507 udelay(150);
9508
9509 /* The pixel multiplier can only be updated once the
9510 * DPLL is enabled and the clocks are stable.
9511 *
9512 * So write it again.
9513 */
9514 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9515 POSTING_READ(PCH_DPLL(pll->id));
9516 udelay(200);
9517}
9518
9519static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9520 struct intel_shared_dpll *pll)
9521{
9522 struct drm_device *dev = dev_priv->dev;
9523 struct intel_crtc *crtc;
9524
9525 /* Make sure no transcoder isn't still depending on us. */
9526 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9527 if (intel_crtc_to_shared_dpll(crtc) == pll)
9528 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9529 }
9530
9531 I915_WRITE(PCH_DPLL(pll->id), 0);
9532 POSTING_READ(PCH_DPLL(pll->id));
9533 udelay(200);
9534}
9535
9536static char *ibx_pch_dpll_names[] = {
9537 "PCH DPLL A",
9538 "PCH DPLL B",
9539};
9540
9541static void ibx_pch_dpll_init(struct drm_device *dev)
9542{
9543 struct drm_i915_private *dev_priv = dev->dev_private;
9544 int i;
9545
9546 dev_priv->num_shared_dpll = 2;
9547
9548 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9549 dev_priv->shared_dplls[i].id = i;
9550 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9551 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9552 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9553 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9554 dev_priv->shared_dplls[i].get_hw_state =
9555 ibx_pch_dpll_get_hw_state;
9556 }
9557}
9558
9559static void intel_shared_dpll_init(struct drm_device *dev)
9560{
9561 struct drm_i915_private *dev_priv = dev->dev_private;
9562
9563 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9564 ibx_pch_dpll_init(dev);
9565 else
9566 dev_priv->num_shared_dpll = 0;
9567
9568 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9569 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9570 dev_priv->num_shared_dpll);
9571}
9572
9573static void intel_crtc_init(struct drm_device *dev, int pipe)
9574{
9575 drm_i915_private_t *dev_priv = dev->dev_private;
9576 struct intel_crtc *intel_crtc;
9577 int i;
9578
9579 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9580 if (intel_crtc == NULL)
9581 return;
9582
9583 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9584
9585 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9586 for (i = 0; i < 256; i++) {
9587 intel_crtc->lut_r[i] = i;
9588 intel_crtc->lut_g[i] = i;
9589 intel_crtc->lut_b[i] = i;
9590 }
9591
9592 /* Swap pipes & planes for FBC on pre-965 */
9593 intel_crtc->pipe = pipe;
9594 intel_crtc->plane = pipe;
9595 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9596 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9597 intel_crtc->plane = !pipe;
9598 }
9599
9600 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9601 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9602 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9603 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9604
9605 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9606}
9607
9608int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9609 struct drm_file *file)
9610{
9611 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9612 struct drm_mode_object *drmmode_obj;
9613 struct intel_crtc *crtc;
9614
9615 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9616 return -ENODEV;
9617
9618 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9619 DRM_MODE_OBJECT_CRTC);
9620
9621 if (!drmmode_obj) {
9622 DRM_ERROR("no such CRTC id\n");
9623 return -EINVAL;
9624 }
9625
9626 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9627 pipe_from_crtc_id->pipe = crtc->pipe;
9628
9629 return 0;
9630}
9631
9632static int intel_encoder_clones(struct intel_encoder *encoder)
9633{
9634 struct drm_device *dev = encoder->base.dev;
9635 struct intel_encoder *source_encoder;
9636 int index_mask = 0;
9637 int entry = 0;
9638
9639 list_for_each_entry(source_encoder,
9640 &dev->mode_config.encoder_list, base.head) {
9641
9642 if (encoder == source_encoder)
9643 index_mask |= (1 << entry);
9644
9645 /* Intel hw has only one MUX where enocoders could be cloned. */
9646 if (encoder->cloneable && source_encoder->cloneable)
9647 index_mask |= (1 << entry);
9648
9649 entry++;
9650 }
9651
9652 return index_mask;
9653}
9654
9655static bool has_edp_a(struct drm_device *dev)
9656{
9657 struct drm_i915_private *dev_priv = dev->dev_private;
9658
9659 if (!IS_MOBILE(dev))
9660 return false;
9661
9662 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9663 return false;
9664
9665 if (IS_GEN5(dev) &&
9666 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9667 return false;
9668
9669 return true;
9670}
9671
9672static void intel_setup_outputs(struct drm_device *dev)
9673{
9674 struct drm_i915_private *dev_priv = dev->dev_private;
9675 struct intel_encoder *encoder;
9676 bool dpd_is_edp = false;
9677
9678 intel_lvds_init(dev);
9679
9680 if (!IS_ULT(dev))
9681 intel_crt_init(dev);
9682
9683 if (HAS_DDI(dev)) {
9684 int found;
9685
9686 /* Haswell uses DDI functions to detect digital outputs */
9687 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9688 /* DDI A only supports eDP */
9689 if (found)
9690 intel_ddi_init(dev, PORT_A);
9691
9692 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9693 * register */
9694 found = I915_READ(SFUSE_STRAP);
9695
9696 if (found & SFUSE_STRAP_DDIB_DETECTED)
9697 intel_ddi_init(dev, PORT_B);
9698 if (found & SFUSE_STRAP_DDIC_DETECTED)
9699 intel_ddi_init(dev, PORT_C);
9700 if (found & SFUSE_STRAP_DDID_DETECTED)
9701 intel_ddi_init(dev, PORT_D);
9702 } else if (HAS_PCH_SPLIT(dev)) {
9703 int found;
9704 dpd_is_edp = intel_dpd_is_edp(dev);
9705
9706 if (has_edp_a(dev))
9707 intel_dp_init(dev, DP_A, PORT_A);
9708
9709 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9710 /* PCH SDVOB multiplex with HDMIB */
9711 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9712 if (!found)
9713 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9714 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9715 intel_dp_init(dev, PCH_DP_B, PORT_B);
9716 }
9717
9718 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9719 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9720
9721 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9722 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9723
9724 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9725 intel_dp_init(dev, PCH_DP_C, PORT_C);
9726
9727 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9728 intel_dp_init(dev, PCH_DP_D, PORT_D);
9729 } else if (IS_VALLEYVIEW(dev)) {
9730 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9731 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9732 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9733 PORT_C);
9734 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9735 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9736 PORT_C);
9737 }
9738
9739 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9740 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9741 PORT_B);
9742 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9743 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9744 }
9745
9746 intel_dsi_init(dev);
9747 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9748 bool found = false;
9749
9750 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9751 DRM_DEBUG_KMS("probing SDVOB\n");
9752 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9753 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9754 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9755 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9756 }
9757
9758 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9759 intel_dp_init(dev, DP_B, PORT_B);
9760 }
9761
9762 /* Before G4X SDVOC doesn't have its own detect register */
9763
9764 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9765 DRM_DEBUG_KMS("probing SDVOC\n");
9766 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9767 }
9768
9769 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9770
9771 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9772 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9773 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9774 }
9775 if (SUPPORTS_INTEGRATED_DP(dev))
9776 intel_dp_init(dev, DP_C, PORT_C);
9777 }
9778
9779 if (SUPPORTS_INTEGRATED_DP(dev) &&
9780 (I915_READ(DP_D) & DP_DETECTED))
9781 intel_dp_init(dev, DP_D, PORT_D);
9782 } else if (IS_GEN2(dev))
9783 intel_dvo_init(dev);
9784
9785 if (SUPPORTS_TV(dev))
9786 intel_tv_init(dev);
9787
9788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9789 encoder->base.possible_crtcs = encoder->crtc_mask;
9790 encoder->base.possible_clones =
9791 intel_encoder_clones(encoder);
9792 }
9793
9794 intel_init_pch_refclk(dev);
9795
9796 drm_helper_move_panel_connectors_to_head(dev);
9797}
9798
9799void intel_framebuffer_fini(struct intel_framebuffer *fb)
9800{
9801 drm_framebuffer_cleanup(&fb->base);
9802 drm_gem_object_unreference_unlocked(&fb->obj->base);
9803}
9804
9805static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9806{
9807 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9808
9809 intel_framebuffer_fini(intel_fb);
9810 kfree(intel_fb);
9811}
9812
9813static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9814 struct drm_file *file,
9815 unsigned int *handle)
9816{
9817 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9818 struct drm_i915_gem_object *obj = intel_fb->obj;
9819
9820 return drm_gem_handle_create(file, &obj->base, handle);
9821}
9822
9823static const struct drm_framebuffer_funcs intel_fb_funcs = {
9824 .destroy = intel_user_framebuffer_destroy,
9825 .create_handle = intel_user_framebuffer_create_handle,
9826};
9827
9828int intel_framebuffer_init(struct drm_device *dev,
9829 struct intel_framebuffer *intel_fb,
9830 struct drm_mode_fb_cmd2 *mode_cmd,
9831 struct drm_i915_gem_object *obj)
9832{
9833 int pitch_limit;
9834 int ret;
9835
9836 if (obj->tiling_mode == I915_TILING_Y) {
9837 DRM_DEBUG("hardware does not support tiling Y\n");
9838 return -EINVAL;
9839 }
9840
9841 if (mode_cmd->pitches[0] & 63) {
9842 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9843 mode_cmd->pitches[0]);
9844 return -EINVAL;
9845 }
9846
9847 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9848 pitch_limit = 32*1024;
9849 } else if (INTEL_INFO(dev)->gen >= 4) {
9850 if (obj->tiling_mode)
9851 pitch_limit = 16*1024;
9852 else
9853 pitch_limit = 32*1024;
9854 } else if (INTEL_INFO(dev)->gen >= 3) {
9855 if (obj->tiling_mode)
9856 pitch_limit = 8*1024;
9857 else
9858 pitch_limit = 16*1024;
9859 } else
9860 /* XXX DSPC is limited to 4k tiled */
9861 pitch_limit = 8*1024;
9862
9863 if (mode_cmd->pitches[0] > pitch_limit) {
9864 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9865 obj->tiling_mode ? "tiled" : "linear",
9866 mode_cmd->pitches[0], pitch_limit);
9867 return -EINVAL;
9868 }
9869
9870 if (obj->tiling_mode != I915_TILING_NONE &&
9871 mode_cmd->pitches[0] != obj->stride) {
9872 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9873 mode_cmd->pitches[0], obj->stride);
9874 return -EINVAL;
9875 }
9876
9877 /* Reject formats not supported by any plane early. */
9878 switch (mode_cmd->pixel_format) {
9879 case DRM_FORMAT_C8:
9880 case DRM_FORMAT_RGB565:
9881 case DRM_FORMAT_XRGB8888:
9882 case DRM_FORMAT_ARGB8888:
9883 break;
9884 case DRM_FORMAT_XRGB1555:
9885 case DRM_FORMAT_ARGB1555:
9886 if (INTEL_INFO(dev)->gen > 3) {
9887 DRM_DEBUG("unsupported pixel format: %s\n",
9888 drm_get_format_name(mode_cmd->pixel_format));
9889 return -EINVAL;
9890 }
9891 break;
9892 case DRM_FORMAT_XBGR8888:
9893 case DRM_FORMAT_ABGR8888:
9894 case DRM_FORMAT_XRGB2101010:
9895 case DRM_FORMAT_ARGB2101010:
9896 case DRM_FORMAT_XBGR2101010:
9897 case DRM_FORMAT_ABGR2101010:
9898 if (INTEL_INFO(dev)->gen < 4) {
9899 DRM_DEBUG("unsupported pixel format: %s\n",
9900 drm_get_format_name(mode_cmd->pixel_format));
9901 return -EINVAL;
9902 }
9903 break;
9904 case DRM_FORMAT_YUYV:
9905 case DRM_FORMAT_UYVY:
9906 case DRM_FORMAT_YVYU:
9907 case DRM_FORMAT_VYUY:
9908 if (INTEL_INFO(dev)->gen < 5) {
9909 DRM_DEBUG("unsupported pixel format: %s\n",
9910 drm_get_format_name(mode_cmd->pixel_format));
9911 return -EINVAL;
9912 }
9913 break;
9914 default:
9915 DRM_DEBUG("unsupported pixel format: %s\n",
9916 drm_get_format_name(mode_cmd->pixel_format));
9917 return -EINVAL;
9918 }
9919
9920 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9921 if (mode_cmd->offsets[0] != 0)
9922 return -EINVAL;
9923
9924 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9925 intel_fb->obj = obj;
9926
9927 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9928 if (ret) {
9929 DRM_ERROR("framebuffer init failed %d\n", ret);
9930 return ret;
9931 }
9932
9933 return 0;
9934}
9935
9936static struct drm_framebuffer *
9937intel_user_framebuffer_create(struct drm_device *dev,
9938 struct drm_file *filp,
9939 struct drm_mode_fb_cmd2 *mode_cmd)
9940{
9941 struct drm_i915_gem_object *obj;
9942
9943 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9944 mode_cmd->handles[0]));
9945 if (&obj->base == NULL)
9946 return ERR_PTR(-ENOENT);
9947
9948 return intel_framebuffer_create(dev, mode_cmd, obj);
9949}
9950
9951static const struct drm_mode_config_funcs intel_mode_funcs = {
9952 .fb_create = intel_user_framebuffer_create,
9953 .output_poll_changed = intel_fb_output_poll_changed,
9954};
9955
9956/* Set up chip specific display functions */
9957static void intel_init_display(struct drm_device *dev)
9958{
9959 struct drm_i915_private *dev_priv = dev->dev_private;
9960
9961 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9962 dev_priv->display.find_dpll = g4x_find_best_dpll;
9963 else if (IS_VALLEYVIEW(dev))
9964 dev_priv->display.find_dpll = vlv_find_best_dpll;
9965 else if (IS_PINEVIEW(dev))
9966 dev_priv->display.find_dpll = pnv_find_best_dpll;
9967 else
9968 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9969
9970 if (HAS_DDI(dev)) {
9971 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9972 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9973 dev_priv->display.crtc_enable = haswell_crtc_enable;
9974 dev_priv->display.crtc_disable = haswell_crtc_disable;
9975 dev_priv->display.off = haswell_crtc_off;
9976 dev_priv->display.update_plane = ironlake_update_plane;
9977 } else if (HAS_PCH_SPLIT(dev)) {
9978 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9979 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9980 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9981 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9982 dev_priv->display.off = ironlake_crtc_off;
9983 dev_priv->display.update_plane = ironlake_update_plane;
9984 } else if (IS_VALLEYVIEW(dev)) {
9985 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9986 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9987 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9988 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9989 dev_priv->display.off = i9xx_crtc_off;
9990 dev_priv->display.update_plane = i9xx_update_plane;
9991 } else {
9992 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9993 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9994 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9995 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9996 dev_priv->display.off = i9xx_crtc_off;
9997 dev_priv->display.update_plane = i9xx_update_plane;
9998 }
9999
10000 /* Returns the core display clock speed */
10001 if (IS_VALLEYVIEW(dev))
10002 dev_priv->display.get_display_clock_speed =
10003 valleyview_get_display_clock_speed;
10004 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10005 dev_priv->display.get_display_clock_speed =
10006 i945_get_display_clock_speed;
10007 else if (IS_I915G(dev))
10008 dev_priv->display.get_display_clock_speed =
10009 i915_get_display_clock_speed;
10010 else if (IS_I945GM(dev) || IS_845G(dev))
10011 dev_priv->display.get_display_clock_speed =
10012 i9xx_misc_get_display_clock_speed;
10013 else if (IS_PINEVIEW(dev))
10014 dev_priv->display.get_display_clock_speed =
10015 pnv_get_display_clock_speed;
10016 else if (IS_I915GM(dev))
10017 dev_priv->display.get_display_clock_speed =
10018 i915gm_get_display_clock_speed;
10019 else if (IS_I865G(dev))
10020 dev_priv->display.get_display_clock_speed =
10021 i865_get_display_clock_speed;
10022 else if (IS_I85X(dev))
10023 dev_priv->display.get_display_clock_speed =
10024 i855_get_display_clock_speed;
10025 else /* 852, 830 */
10026 dev_priv->display.get_display_clock_speed =
10027 i830_get_display_clock_speed;
10028
10029 if (HAS_PCH_SPLIT(dev)) {
10030 if (IS_GEN5(dev)) {
10031 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10032 dev_priv->display.write_eld = ironlake_write_eld;
10033 } else if (IS_GEN6(dev)) {
10034 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10035 dev_priv->display.write_eld = ironlake_write_eld;
10036 } else if (IS_IVYBRIDGE(dev)) {
10037 /* FIXME: detect B0+ stepping and use auto training */
10038 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10039 dev_priv->display.write_eld = ironlake_write_eld;
10040 dev_priv->display.modeset_global_resources =
10041 ivb_modeset_global_resources;
10042 } else if (IS_HASWELL(dev)) {
10043 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10044 dev_priv->display.write_eld = haswell_write_eld;
10045 dev_priv->display.modeset_global_resources =
10046 haswell_modeset_global_resources;
10047 }
10048 } else if (IS_G4X(dev)) {
10049 dev_priv->display.write_eld = g4x_write_eld;
10050 }
10051
10052 /* Default just returns -ENODEV to indicate unsupported */
10053 dev_priv->display.queue_flip = intel_default_queue_flip;
10054
10055 switch (INTEL_INFO(dev)->gen) {
10056 case 2:
10057 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10058 break;
10059
10060 case 3:
10061 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10062 break;
10063
10064 case 4:
10065 case 5:
10066 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10067 break;
10068
10069 case 6:
10070 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10071 break;
10072 case 7:
10073 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10074 break;
10075 }
10076}
10077
10078/*
10079 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10080 * resume, or other times. This quirk makes sure that's the case for
10081 * affected systems.
10082 */
10083static void quirk_pipea_force(struct drm_device *dev)
10084{
10085 struct drm_i915_private *dev_priv = dev->dev_private;
10086
10087 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10088 DRM_INFO("applying pipe a force quirk\n");
10089}
10090
10091/*
10092 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10093 */
10094static void quirk_ssc_force_disable(struct drm_device *dev)
10095{
10096 struct drm_i915_private *dev_priv = dev->dev_private;
10097 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10098 DRM_INFO("applying lvds SSC disable quirk\n");
10099}
10100
10101/*
10102 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10103 * brightness value
10104 */
10105static void quirk_invert_brightness(struct drm_device *dev)
10106{
10107 struct drm_i915_private *dev_priv = dev->dev_private;
10108 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10109 DRM_INFO("applying inverted panel brightness quirk\n");
10110}
10111
10112/*
10113 * Some machines (Dell XPS13) suffer broken backlight controls if
10114 * BLM_PCH_PWM_ENABLE is set.
10115 */
10116static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10117{
10118 struct drm_i915_private *dev_priv = dev->dev_private;
10119 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10120 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10121}
10122
10123struct intel_quirk {
10124 int device;
10125 int subsystem_vendor;
10126 int subsystem_device;
10127 void (*hook)(struct drm_device *dev);
10128};
10129
10130/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10131struct intel_dmi_quirk {
10132 void (*hook)(struct drm_device *dev);
10133 const struct dmi_system_id (*dmi_id_list)[];
10134};
10135
10136static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10137{
10138 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10139 return 1;
10140}
10141
10142static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10143 {
10144 .dmi_id_list = &(const struct dmi_system_id[]) {
10145 {
10146 .callback = intel_dmi_reverse_brightness,
10147 .ident = "NCR Corporation",
10148 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10149 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10150 },
10151 },
10152 { } /* terminating entry */
10153 },
10154 .hook = quirk_invert_brightness,
10155 },
10156};
10157
10158static struct intel_quirk intel_quirks[] = {
10159 /* HP Mini needs pipe A force quirk (LP: #322104) */
10160 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10161
10162 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10163 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10164
10165 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10166 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10167
10168 /* 830/845 need to leave pipe A & dpll A up */
10169 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10170 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10171
10172 /* Lenovo U160 cannot use SSC on LVDS */
10173 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10174
10175 /* Sony Vaio Y cannot use SSC on LVDS */
10176 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10177
10178 /* Acer Aspire 5734Z must invert backlight brightness */
10179 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10180
10181 /* Acer/eMachines G725 */
10182 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10183
10184 /* Acer/eMachines e725 */
10185 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10186
10187 /* Acer/Packard Bell NCL20 */
10188 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10189
10190 /* Acer Aspire 4736Z */
10191 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10192
10193 /* Dell XPS13 HD Sandy Bridge */
10194 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10195 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10196 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10197};
10198
10199static void intel_init_quirks(struct drm_device *dev)
10200{
10201 struct pci_dev *d = dev->pdev;
10202 int i;
10203
10204 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10205 struct intel_quirk *q = &intel_quirks[i];
10206
10207 if (d->device == q->device &&
10208 (d->subsystem_vendor == q->subsystem_vendor ||
10209 q->subsystem_vendor == PCI_ANY_ID) &&
10210 (d->subsystem_device == q->subsystem_device ||
10211 q->subsystem_device == PCI_ANY_ID))
10212 q->hook(dev);
10213 }
10214 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10215 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10216 intel_dmi_quirks[i].hook(dev);
10217 }
10218}
10219
10220/* Disable the VGA plane that we never use */
10221static void i915_disable_vga(struct drm_device *dev)
10222{
10223 struct drm_i915_private *dev_priv = dev->dev_private;
10224 u8 sr1;
10225 u32 vga_reg = i915_vgacntrl_reg(dev);
10226
10227 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10228 outb(SR01, VGA_SR_INDEX);
10229 sr1 = inb(VGA_SR_DATA);
10230 outb(sr1 | 1<<5, VGA_SR_DATA);
10231
10232 /* Disable VGA memory on Intel HD */
10233 if (HAS_PCH_SPLIT(dev)) {
10234 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10235 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10236 VGA_RSRC_NORMAL_IO |
10237 VGA_RSRC_NORMAL_MEM);
10238 }
10239
10240 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10241 udelay(300);
10242
10243 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10244 POSTING_READ(vga_reg);
10245}
10246
10247static void i915_enable_vga(struct drm_device *dev)
10248{
10249 /* Enable VGA memory on Intel HD */
10250 if (HAS_PCH_SPLIT(dev)) {
10251 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10252 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10253 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10254 VGA_RSRC_LEGACY_MEM |
10255 VGA_RSRC_NORMAL_IO |
10256 VGA_RSRC_NORMAL_MEM);
10257 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10258 }
10259}
10260
10261void intel_modeset_init_hw(struct drm_device *dev)
10262{
10263 intel_init_power_well(dev);
10264
10265 intel_prepare_ddi(dev);
10266
10267 intel_init_clock_gating(dev);
10268
10269 mutex_lock(&dev->struct_mutex);
10270 intel_enable_gt_powersave(dev);
10271 mutex_unlock(&dev->struct_mutex);
10272}
10273
10274void intel_modeset_suspend_hw(struct drm_device *dev)
10275{
10276 intel_suspend_hw(dev);
10277}
10278
10279void intel_modeset_init(struct drm_device *dev)
10280{
10281 struct drm_i915_private *dev_priv = dev->dev_private;
10282 int i, j, ret;
10283
10284 drm_mode_config_init(dev);
10285
10286 dev->mode_config.min_width = 0;
10287 dev->mode_config.min_height = 0;
10288
10289 dev->mode_config.preferred_depth = 24;
10290 dev->mode_config.prefer_shadow = 1;
10291
10292 dev->mode_config.funcs = &intel_mode_funcs;
10293
10294 intel_init_quirks(dev);
10295
10296 intel_init_pm(dev);
10297
10298 if (INTEL_INFO(dev)->num_pipes == 0)
10299 return;
10300
10301 intel_init_display(dev);
10302
10303 if (IS_GEN2(dev)) {
10304 dev->mode_config.max_width = 2048;
10305 dev->mode_config.max_height = 2048;
10306 } else if (IS_GEN3(dev)) {
10307 dev->mode_config.max_width = 4096;
10308 dev->mode_config.max_height = 4096;
10309 } else {
10310 dev->mode_config.max_width = 8192;
10311 dev->mode_config.max_height = 8192;
10312 }
10313 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10314
10315 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10316 INTEL_INFO(dev)->num_pipes,
10317 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10318
10319 for_each_pipe(i) {
10320 intel_crtc_init(dev, i);
10321 for (j = 0; j < dev_priv->num_plane; j++) {
10322 ret = intel_plane_init(dev, i, j);
10323 if (ret)
10324 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10325 pipe_name(i), sprite_name(i, j), ret);
10326 }
10327 }
10328
10329 intel_cpu_pll_init(dev);
10330 intel_shared_dpll_init(dev);
10331
10332 /* Just disable it once at startup */
10333 i915_disable_vga(dev);
10334 intel_setup_outputs(dev);
10335
10336 /* Just in case the BIOS is doing something questionable. */
10337 intel_disable_fbc(dev);
10338}
10339
10340static void
10341intel_connector_break_all_links(struct intel_connector *connector)
10342{
10343 connector->base.dpms = DRM_MODE_DPMS_OFF;
10344 connector->base.encoder = NULL;
10345 connector->encoder->connectors_active = false;
10346 connector->encoder->base.crtc = NULL;
10347}
10348
10349static void intel_enable_pipe_a(struct drm_device *dev)
10350{
10351 struct intel_connector *connector;
10352 struct drm_connector *crt = NULL;
10353 struct intel_load_detect_pipe load_detect_temp;
10354
10355 /* We can't just switch on the pipe A, we need to set things up with a
10356 * proper mode and output configuration. As a gross hack, enable pipe A
10357 * by enabling the load detect pipe once. */
10358 list_for_each_entry(connector,
10359 &dev->mode_config.connector_list,
10360 base.head) {
10361 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10362 crt = &connector->base;
10363 break;
10364 }
10365 }
10366
10367 if (!crt)
10368 return;
10369
10370 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10371 intel_release_load_detect_pipe(crt, &load_detect_temp);
10372
10373
10374}
10375
10376static bool
10377intel_check_plane_mapping(struct intel_crtc *crtc)
10378{
10379 struct drm_device *dev = crtc->base.dev;
10380 struct drm_i915_private *dev_priv = dev->dev_private;
10381 u32 reg, val;
10382
10383 if (INTEL_INFO(dev)->num_pipes == 1)
10384 return true;
10385
10386 reg = DSPCNTR(!crtc->plane);
10387 val = I915_READ(reg);
10388
10389 if ((val & DISPLAY_PLANE_ENABLE) &&
10390 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10391 return false;
10392
10393 return true;
10394}
10395
10396static void intel_sanitize_crtc(struct intel_crtc *crtc)
10397{
10398 struct drm_device *dev = crtc->base.dev;
10399 struct drm_i915_private *dev_priv = dev->dev_private;
10400 u32 reg;
10401
10402 /* Clear any frame start delays used for debugging left by the BIOS */
10403 reg = PIPECONF(crtc->config.cpu_transcoder);
10404 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10405
10406 /* We need to sanitize the plane -> pipe mapping first because this will
10407 * disable the crtc (and hence change the state) if it is wrong. Note
10408 * that gen4+ has a fixed plane -> pipe mapping. */
10409 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10410 struct intel_connector *connector;
10411 bool plane;
10412
10413 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10414 crtc->base.base.id);
10415
10416 /* Pipe has the wrong plane attached and the plane is active.
10417 * Temporarily change the plane mapping and disable everything
10418 * ... */
10419 plane = crtc->plane;
10420 crtc->plane = !plane;
10421 dev_priv->display.crtc_disable(&crtc->base);
10422 crtc->plane = plane;
10423
10424 /* ... and break all links. */
10425 list_for_each_entry(connector, &dev->mode_config.connector_list,
10426 base.head) {
10427 if (connector->encoder->base.crtc != &crtc->base)
10428 continue;
10429
10430 intel_connector_break_all_links(connector);
10431 }
10432
10433 WARN_ON(crtc->active);
10434 crtc->base.enabled = false;
10435 }
10436
10437 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10438 crtc->pipe == PIPE_A && !crtc->active) {
10439 /* BIOS forgot to enable pipe A, this mostly happens after
10440 * resume. Force-enable the pipe to fix this, the update_dpms
10441 * call below we restore the pipe to the right state, but leave
10442 * the required bits on. */
10443 intel_enable_pipe_a(dev);
10444 }
10445
10446 /* Adjust the state of the output pipe according to whether we
10447 * have active connectors/encoders. */
10448 intel_crtc_update_dpms(&crtc->base);
10449
10450 if (crtc->active != crtc->base.enabled) {
10451 struct intel_encoder *encoder;
10452
10453 /* This can happen either due to bugs in the get_hw_state
10454 * functions or because the pipe is force-enabled due to the
10455 * pipe A quirk. */
10456 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10457 crtc->base.base.id,
10458 crtc->base.enabled ? "enabled" : "disabled",
10459 crtc->active ? "enabled" : "disabled");
10460
10461 crtc->base.enabled = crtc->active;
10462
10463 /* Because we only establish the connector -> encoder ->
10464 * crtc links if something is active, this means the
10465 * crtc is now deactivated. Break the links. connector
10466 * -> encoder links are only establish when things are
10467 * actually up, hence no need to break them. */
10468 WARN_ON(crtc->active);
10469
10470 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10471 WARN_ON(encoder->connectors_active);
10472 encoder->base.crtc = NULL;
10473 }
10474 }
10475}
10476
10477static void intel_sanitize_encoder(struct intel_encoder *encoder)
10478{
10479 struct intel_connector *connector;
10480 struct drm_device *dev = encoder->base.dev;
10481
10482 /* We need to check both for a crtc link (meaning that the
10483 * encoder is active and trying to read from a pipe) and the
10484 * pipe itself being active. */
10485 bool has_active_crtc = encoder->base.crtc &&
10486 to_intel_crtc(encoder->base.crtc)->active;
10487
10488 if (encoder->connectors_active && !has_active_crtc) {
10489 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10490 encoder->base.base.id,
10491 drm_get_encoder_name(&encoder->base));
10492
10493 /* Connector is active, but has no active pipe. This is
10494 * fallout from our resume register restoring. Disable
10495 * the encoder manually again. */
10496 if (encoder->base.crtc) {
10497 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10498 encoder->base.base.id,
10499 drm_get_encoder_name(&encoder->base));
10500 encoder->disable(encoder);
10501 }
10502
10503 /* Inconsistent output/port/pipe state happens presumably due to
10504 * a bug in one of the get_hw_state functions. Or someplace else
10505 * in our code, like the register restore mess on resume. Clamp
10506 * things to off as a safer default. */
10507 list_for_each_entry(connector,
10508 &dev->mode_config.connector_list,
10509 base.head) {
10510 if (connector->encoder != encoder)
10511 continue;
10512
10513 intel_connector_break_all_links(connector);
10514 }
10515 }
10516 /* Enabled encoders without active connectors will be fixed in
10517 * the crtc fixup. */
10518}
10519
10520void i915_redisable_vga(struct drm_device *dev)
10521{
10522 struct drm_i915_private *dev_priv = dev->dev_private;
10523 u32 vga_reg = i915_vgacntrl_reg(dev);
10524
10525 /* This function can be called both from intel_modeset_setup_hw_state or
10526 * at a very early point in our resume sequence, where the power well
10527 * structures are not yet restored. Since this function is at a very
10528 * paranoid "someone might have enabled VGA while we were not looking"
10529 * level, just check if the power well is enabled instead of trying to
10530 * follow the "don't touch the power well if we don't need it" policy
10531 * the rest of the driver uses. */
10532 if (HAS_POWER_WELL(dev) &&
10533 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10534 return;
10535
10536 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10537 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10538 i915_disable_vga(dev);
10539 }
10540}
10541
10542static void intel_modeset_readout_hw_state(struct drm_device *dev)
10543{
10544 struct drm_i915_private *dev_priv = dev->dev_private;
10545 enum pipe pipe;
10546 struct intel_crtc *crtc;
10547 struct intel_encoder *encoder;
10548 struct intel_connector *connector;
10549 int i;
10550
10551 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10552 base.head) {
10553 memset(&crtc->config, 0, sizeof(crtc->config));
10554
10555 crtc->active = dev_priv->display.get_pipe_config(crtc,
10556 &crtc->config);
10557
10558 crtc->base.enabled = crtc->active;
10559
10560 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10561 crtc->base.base.id,
10562 crtc->active ? "enabled" : "disabled");
10563 }
10564
10565 /* FIXME: Smash this into the new shared dpll infrastructure. */
10566 if (HAS_DDI(dev))
10567 intel_ddi_setup_hw_pll_state(dev);
10568
10569 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10570 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10571
10572 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10573 pll->active = 0;
10574 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10575 base.head) {
10576 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10577 pll->active++;
10578 }
10579 pll->refcount = pll->active;
10580
10581 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10582 pll->name, pll->refcount, pll->on);
10583 }
10584
10585 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10586 base.head) {
10587 pipe = 0;
10588
10589 if (encoder->get_hw_state(encoder, &pipe)) {
10590 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10591 encoder->base.crtc = &crtc->base;
10592 if (encoder->get_config)
10593 encoder->get_config(encoder, &crtc->config);
10594 } else {
10595 encoder->base.crtc = NULL;
10596 }
10597
10598 encoder->connectors_active = false;
10599 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10600 encoder->base.base.id,
10601 drm_get_encoder_name(&encoder->base),
10602 encoder->base.crtc ? "enabled" : "disabled",
10603 pipe);
10604 }
10605
10606 list_for_each_entry(connector, &dev->mode_config.connector_list,
10607 base.head) {
10608 if (connector->get_hw_state(connector)) {
10609 connector->base.dpms = DRM_MODE_DPMS_ON;
10610 connector->encoder->connectors_active = true;
10611 connector->base.encoder = &connector->encoder->base;
10612 } else {
10613 connector->base.dpms = DRM_MODE_DPMS_OFF;
10614 connector->base.encoder = NULL;
10615 }
10616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10617 connector->base.base.id,
10618 drm_get_connector_name(&connector->base),
10619 connector->base.encoder ? "enabled" : "disabled");
10620 }
10621}
10622
10623/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10624 * and i915 state tracking structures. */
10625void intel_modeset_setup_hw_state(struct drm_device *dev,
10626 bool force_restore)
10627{
10628 struct drm_i915_private *dev_priv = dev->dev_private;
10629 enum pipe pipe;
10630 struct drm_plane *plane;
10631 struct intel_crtc *crtc;
10632 struct intel_encoder *encoder;
10633 int i;
10634
10635 intel_modeset_readout_hw_state(dev);
10636
10637 /*
10638 * Now that we have the config, copy it to each CRTC struct
10639 * Note that this could go away if we move to using crtc_config
10640 * checking everywhere.
10641 */
10642 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10643 base.head) {
10644 if (crtc->active && i915_fastboot) {
10645 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10646
10647 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10648 crtc->base.base.id);
10649 drm_mode_debug_printmodeline(&crtc->base.mode);
10650 }
10651 }
10652
10653 /* HW state is read out, now we need to sanitize this mess. */
10654 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10655 base.head) {
10656 intel_sanitize_encoder(encoder);
10657 }
10658
10659 for_each_pipe(pipe) {
10660 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10661 intel_sanitize_crtc(crtc);
10662 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10663 }
10664
10665 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10666 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10667
10668 if (!pll->on || pll->active)
10669 continue;
10670
10671 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10672
10673 pll->disable(dev_priv, pll);
10674 pll->on = false;
10675 }
10676
10677 if (force_restore) {
10678 /*
10679 * We need to use raw interfaces for restoring state to avoid
10680 * checking (bogus) intermediate states.
10681 */
10682 for_each_pipe(pipe) {
10683 struct drm_crtc *crtc =
10684 dev_priv->pipe_to_crtc_mapping[pipe];
10685
10686 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10687 crtc->fb);
10688 }
10689 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10690 intel_plane_restore(plane);
10691
10692 i915_redisable_vga(dev);
10693 } else {
10694 intel_modeset_update_staged_output_state(dev);
10695 }
10696
10697 intel_modeset_check_state(dev);
10698
10699 drm_mode_config_reset(dev);
10700}
10701
10702void intel_modeset_gem_init(struct drm_device *dev)
10703{
10704 intel_modeset_init_hw(dev);
10705
10706 intel_setup_overlay(dev);
10707
10708 intel_modeset_setup_hw_state(dev, false);
10709}
10710
10711void intel_modeset_cleanup(struct drm_device *dev)
10712{
10713 struct drm_i915_private *dev_priv = dev->dev_private;
10714 struct drm_crtc *crtc;
10715
10716 /*
10717 * Interrupts and polling as the first thing to avoid creating havoc.
10718 * Too much stuff here (turning of rps, connectors, ...) would
10719 * experience fancy races otherwise.
10720 */
10721 drm_irq_uninstall(dev);
10722 cancel_work_sync(&dev_priv->hotplug_work);
10723 /*
10724 * Due to the hpd irq storm handling the hotplug work can re-arm the
10725 * poll handlers. Hence disable polling after hpd handling is shut down.
10726 */
10727 drm_kms_helper_poll_fini(dev);
10728
10729 mutex_lock(&dev->struct_mutex);
10730
10731 intel_unregister_dsm_handler();
10732
10733 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10734 /* Skip inactive CRTCs */
10735 if (!crtc->fb)
10736 continue;
10737
10738 intel_increase_pllclock(crtc);
10739 }
10740
10741 intel_disable_fbc(dev);
10742
10743 i915_enable_vga(dev);
10744
10745 intel_disable_gt_powersave(dev);
10746
10747 ironlake_teardown_rc6(dev);
10748
10749 mutex_unlock(&dev->struct_mutex);
10750
10751 /* flush any delayed tasks or pending work */
10752 flush_scheduled_work();
10753
10754 /* destroy backlight, if any, before the connectors */
10755 intel_panel_destroy_backlight(dev);
10756
10757 drm_mode_config_cleanup(dev);
10758
10759 intel_cleanup_overlay(dev);
10760}
10761
10762/*
10763 * Return which encoder is currently attached for connector.
10764 */
10765struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10766{
10767 return &intel_attached_encoder(connector)->base;
10768}
10769
10770void intel_connector_attach_encoder(struct intel_connector *connector,
10771 struct intel_encoder *encoder)
10772{
10773 connector->encoder = encoder;
10774 drm_mode_connector_attach_encoder(&connector->base,
10775 &encoder->base);
10776}
10777
10778/*
10779 * set vga decode state - true == enable VGA decode
10780 */
10781int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10782{
10783 struct drm_i915_private *dev_priv = dev->dev_private;
10784 u16 gmch_ctrl;
10785
10786 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10787 if (state)
10788 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10789 else
10790 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10791 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10792 return 0;
10793}
10794
10795struct intel_display_error_state {
10796
10797 u32 power_well_driver;
10798
10799 int num_transcoders;
10800
10801 struct intel_cursor_error_state {
10802 u32 control;
10803 u32 position;
10804 u32 base;
10805 u32 size;
10806 } cursor[I915_MAX_PIPES];
10807
10808 struct intel_pipe_error_state {
10809 u32 source;
10810 } pipe[I915_MAX_PIPES];
10811
10812 struct intel_plane_error_state {
10813 u32 control;
10814 u32 stride;
10815 u32 size;
10816 u32 pos;
10817 u32 addr;
10818 u32 surface;
10819 u32 tile_offset;
10820 } plane[I915_MAX_PIPES];
10821
10822 struct intel_transcoder_error_state {
10823 enum transcoder cpu_transcoder;
10824
10825 u32 conf;
10826
10827 u32 htotal;
10828 u32 hblank;
10829 u32 hsync;
10830 u32 vtotal;
10831 u32 vblank;
10832 u32 vsync;
10833 } transcoder[4];
10834};
10835
10836struct intel_display_error_state *
10837intel_display_capture_error_state(struct drm_device *dev)
10838{
10839 drm_i915_private_t *dev_priv = dev->dev_private;
10840 struct intel_display_error_state *error;
10841 int transcoders[] = {
10842 TRANSCODER_A,
10843 TRANSCODER_B,
10844 TRANSCODER_C,
10845 TRANSCODER_EDP,
10846 };
10847 int i;
10848
10849 if (INTEL_INFO(dev)->num_pipes == 0)
10850 return NULL;
10851
10852 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10853 if (error == NULL)
10854 return NULL;
10855
10856 if (HAS_POWER_WELL(dev))
10857 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10858
10859 for_each_pipe(i) {
10860 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10861 error->cursor[i].control = I915_READ(CURCNTR(i));
10862 error->cursor[i].position = I915_READ(CURPOS(i));
10863 error->cursor[i].base = I915_READ(CURBASE(i));
10864 } else {
10865 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10866 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10867 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10868 }
10869
10870 error->plane[i].control = I915_READ(DSPCNTR(i));
10871 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10872 if (INTEL_INFO(dev)->gen <= 3) {
10873 error->plane[i].size = I915_READ(DSPSIZE(i));
10874 error->plane[i].pos = I915_READ(DSPPOS(i));
10875 }
10876 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10877 error->plane[i].addr = I915_READ(DSPADDR(i));
10878 if (INTEL_INFO(dev)->gen >= 4) {
10879 error->plane[i].surface = I915_READ(DSPSURF(i));
10880 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10881 }
10882
10883 error->pipe[i].source = I915_READ(PIPESRC(i));
10884 }
10885
10886 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10887 if (HAS_DDI(dev_priv->dev))
10888 error->num_transcoders++; /* Account for eDP. */
10889
10890 for (i = 0; i < error->num_transcoders; i++) {
10891 enum transcoder cpu_transcoder = transcoders[i];
10892
10893 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10894
10895 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10896 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10897 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10898 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10899 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10900 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10901 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10902 }
10903
10904 /* In the code above we read the registers without checking if the power
10905 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10906 * prevent the next I915_WRITE from detecting it and printing an error
10907 * message. */
10908 intel_uncore_clear_errors(dev);
10909
10910 return error;
10911}
10912
10913#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10914
10915void
10916intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10917 struct drm_device *dev,
10918 struct intel_display_error_state *error)
10919{
10920 int i;
10921
10922 if (!error)
10923 return;
10924
10925 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10926 if (HAS_POWER_WELL(dev))
10927 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10928 error->power_well_driver);
10929 for_each_pipe(i) {
10930 err_printf(m, "Pipe [%d]:\n", i);
10931 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10932
10933 err_printf(m, "Plane [%d]:\n", i);
10934 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10935 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10936 if (INTEL_INFO(dev)->gen <= 3) {
10937 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10938 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10939 }
10940 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10941 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10942 if (INTEL_INFO(dev)->gen >= 4) {
10943 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10944 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10945 }
10946
10947 err_printf(m, "Cursor [%d]:\n", i);
10948 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10949 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10950 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10951 }
10952
10953 for (i = 0; i < error->num_transcoders; i++) {
10954 err_printf(m, " CPU transcoder: %c\n",
10955 transcoder_name(error->transcoder[i].cpu_transcoder));
10956 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10957 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10958 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10959 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10960 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10961 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10962 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10963 }
10964}
Linux kernel - Deliverables
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