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drm/i915: Remove saved_mode from __intel_set_mode()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_atomic.h>
41#include <drm/drm_atomic_helper.h>
42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
46#include <linux/dma_remapping.h>
47
48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
100static void vlv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102static void chv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
109 int num_connectors);
110static void intel_crtc_enable_planes(struct drm_crtc *crtc);
111static void intel_crtc_disable_planes(struct drm_crtc *crtc);
112
113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
121typedef struct {
122 int min, max;
123} intel_range_t;
124
125typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128} intel_p2_t;
129
130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134};
135
136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
154}
155
156static const intel_limit_t intel_limits_i8xx_dac = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
167};
168
169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
182static const intel_limit_t intel_limits_i8xx_lvds = {
183 .dot = { .min = 25000, .max = 350000 },
184 .vco = { .min = 908000, .max = 1512000 },
185 .n = { .min = 2, .max = 16 },
186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
193};
194
195static const intel_limit_t intel_limits_i9xx_sdvo = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
219};
220
221
222static const intel_limit_t intel_limits_g4x_sdvo = {
223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
234 },
235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
261 },
262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
275 },
276};
277
278static const intel_limit_t intel_limits_pineview_sdvo = {
279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
291};
292
293static const intel_limit_t intel_limits_pineview_lvds = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
304};
305
306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
311static const intel_limit_t intel_limits_ironlake_dac = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
322};
323
324static const intel_limit_t intel_limits_ironlake_single_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
348};
349
350/* LVDS 100mhz refclk limits. */
351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
375};
376
377static const intel_limit_t intel_limits_vlv = {
378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
385 .vco = { .min = 4000000, .max = 6000000 },
386 .n = { .min = 1, .max = 7 },
387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
391};
392
393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
401 .vco = { .min = 4800000, .max = 6480000 },
402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
421static void vlv_clock(int refclk, intel_clock_t *clock)
422{
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
429}
430
431/**
432 * Returns whether any output on the specified pipe is of the specified type
433 */
434bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
435{
436 struct drm_device *dev = crtc->base.dev;
437 struct intel_encoder *encoder;
438
439 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
440 if (encoder->type == type)
441 return true;
442
443 return false;
444}
445
446/**
447 * Returns whether any output on the specified pipe will have the specified
448 * type after a staged modeset is complete, i.e., the same as
449 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
450 * encoder->crtc.
451 */
452static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
453 int type)
454{
455 struct drm_atomic_state *state = crtc_state->base.state;
456 struct drm_connector *connector;
457 struct drm_connector_state *connector_state;
458 struct intel_encoder *encoder;
459 int i, num_connectors = 0;
460
461 for_each_connector_in_state(state, connector, connector_state, i) {
462 if (connector_state->crtc != crtc_state->base.crtc)
463 continue;
464
465 num_connectors++;
466
467 encoder = to_intel_encoder(connector_state->best_encoder);
468 if (encoder->type == type)
469 return true;
470 }
471
472 WARN_ON(num_connectors == 0);
473
474 return false;
475}
476
477static const intel_limit_t *
478intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
479{
480 struct drm_device *dev = crtc_state->base.crtc->dev;
481 const intel_limit_t *limit;
482
483 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
484 if (intel_is_dual_link_lvds(dev)) {
485 if (refclk == 100000)
486 limit = &intel_limits_ironlake_dual_lvds_100m;
487 else
488 limit = &intel_limits_ironlake_dual_lvds;
489 } else {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_single_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_single_lvds;
494 }
495 } else
496 limit = &intel_limits_ironlake_dac;
497
498 return limit;
499}
500
501static const intel_limit_t *
502intel_g4x_limit(struct intel_crtc_state *crtc_state)
503{
504 struct drm_device *dev = crtc_state->base.crtc->dev;
505 const intel_limit_t *limit;
506
507 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
508 if (intel_is_dual_link_lvds(dev))
509 limit = &intel_limits_g4x_dual_channel_lvds;
510 else
511 limit = &intel_limits_g4x_single_channel_lvds;
512 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
513 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
514 limit = &intel_limits_g4x_hdmi;
515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
516 limit = &intel_limits_g4x_sdvo;
517 } else /* The option is for other outputs */
518 limit = &intel_limits_i9xx_sdvo;
519
520 return limit;
521}
522
523static const intel_limit_t *
524intel_limit(struct intel_crtc_state *crtc_state, int refclk)
525{
526 struct drm_device *dev = crtc_state->base.crtc->dev;
527 const intel_limit_t *limit;
528
529 if (IS_BROXTON(dev))
530 limit = &intel_limits_bxt;
531 else if (HAS_PCH_SPLIT(dev))
532 limit = intel_ironlake_limit(crtc_state, refclk);
533 else if (IS_G4X(dev)) {
534 limit = intel_g4x_limit(crtc_state);
535 } else if (IS_PINEVIEW(dev)) {
536 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
537 limit = &intel_limits_pineview_lvds;
538 else
539 limit = &intel_limits_pineview_sdvo;
540 } else if (IS_CHERRYVIEW(dev)) {
541 limit = &intel_limits_chv;
542 } else if (IS_VALLEYVIEW(dev)) {
543 limit = &intel_limits_vlv;
544 } else if (!IS_GEN2(dev)) {
545 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
546 limit = &intel_limits_i9xx_lvds;
547 else
548 limit = &intel_limits_i9xx_sdvo;
549 } else {
550 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
551 limit = &intel_limits_i8xx_lvds;
552 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
553 limit = &intel_limits_i8xx_dvo;
554 else
555 limit = &intel_limits_i8xx_dac;
556 }
557 return limit;
558}
559
560/* m1 is reserved as 0 in Pineview, n is a ring counter */
561static void pineview_clock(int refclk, intel_clock_t *clock)
562{
563 clock->m = clock->m2 + 2;
564 clock->p = clock->p1 * clock->p2;
565 if (WARN_ON(clock->n == 0 || clock->p == 0))
566 return;
567 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
568 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
569}
570
571static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
572{
573 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
574}
575
576static void i9xx_clock(int refclk, intel_clock_t *clock)
577{
578 clock->m = i9xx_dpll_compute_m(clock);
579 clock->p = clock->p1 * clock->p2;
580 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
581 return;
582 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
583 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
584}
585
586static void chv_clock(int refclk, intel_clock_t *clock)
587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
591 return;
592 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
593 clock->n << 22);
594 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595}
596
597#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
598/**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
603static bool intel_PLL_is_valid(struct drm_device *dev,
604 const intel_limit_t *limit,
605 const intel_clock_t *clock)
606{
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
615
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
617 if (clock->m1 <= clock->m2)
618 INTELPllInvalid("m1 <= m2\n");
619
620 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
621 if (clock->p < limit->p.min || limit->p.max < clock->p)
622 INTELPllInvalid("p out of range\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 }
626
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
634
635 return true;
636}
637
638static bool
639i9xx_find_best_dpll(const intel_limit_t *limit,
640 struct intel_crtc_state *crtc_state,
641 int target, int refclk, intel_clock_t *match_clock,
642 intel_clock_t *best_clock)
643{
644 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
645 struct drm_device *dev = crtc->base.dev;
646 intel_clock_t clock;
647 int err = target;
648
649 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
650 /*
651 * For LVDS just rely on its current settings for dual-channel.
652 * We haven't figured out how to reliably set up different
653 * single/dual channel state, if we even can.
654 */
655 if (intel_is_dual_link_lvds(dev))
656 clock.p2 = limit->p2.p2_fast;
657 else
658 clock.p2 = limit->p2.p2_slow;
659 } else {
660 if (target < limit->p2.dot_limit)
661 clock.p2 = limit->p2.p2_slow;
662 else
663 clock.p2 = limit->p2.p2_fast;
664 }
665
666 memset(best_clock, 0, sizeof(*best_clock));
667
668 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
669 clock.m1++) {
670 for (clock.m2 = limit->m2.min;
671 clock.m2 <= limit->m2.max; clock.m2++) {
672 if (clock.m2 >= clock.m1)
673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
680 i9xx_clock(refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
683 continue;
684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
701static bool
702pnv_find_best_dpll(const intel_limit_t *limit,
703 struct intel_crtc_state *crtc_state,
704 int target, int refclk, intel_clock_t *match_clock,
705 intel_clock_t *best_clock)
706{
707 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
708 struct drm_device *dev = crtc->base.dev;
709 intel_clock_t clock;
710 int err = target;
711
712 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
713 /*
714 * For LVDS just rely on its current settings for dual-channel.
715 * We haven't figured out how to reliably set up different
716 * single/dual channel state, if we even can.
717 */
718 if (intel_is_dual_link_lvds(dev))
719 clock.p2 = limit->p2.p2_fast;
720 else
721 clock.p2 = limit->p2.p2_slow;
722 } else {
723 if (target < limit->p2.dot_limit)
724 clock.p2 = limit->p2.p2_slow;
725 else
726 clock.p2 = limit->p2.p2_fast;
727 }
728
729 memset(best_clock, 0, sizeof(*best_clock));
730
731 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
732 clock.m1++) {
733 for (clock.m2 = limit->m2.min;
734 clock.m2 <= limit->m2.max; clock.m2++) {
735 for (clock.n = limit->n.min;
736 clock.n <= limit->n.max; clock.n++) {
737 for (clock.p1 = limit->p1.min;
738 clock.p1 <= limit->p1.max; clock.p1++) {
739 int this_err;
740
741 pineview_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
748
749 this_err = abs(clock.dot - target);
750 if (this_err < err) {
751 *best_clock = clock;
752 err = this_err;
753 }
754 }
755 }
756 }
757 }
758
759 return (err != target);
760}
761
762static bool
763g4x_find_best_dpll(const intel_limit_t *limit,
764 struct intel_crtc_state *crtc_state,
765 int target, int refclk, intel_clock_t *match_clock,
766 intel_clock_t *best_clock)
767{
768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
769 struct drm_device *dev = crtc->base.dev;
770 intel_clock_t clock;
771 int max_n;
772 bool found;
773 /* approximately equals target * 0.00585 */
774 int err_most = (target >> 8) + (target >> 9);
775 found = false;
776
777 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
778 if (intel_is_dual_link_lvds(dev))
779 clock.p2 = limit->p2.p2_fast;
780 else
781 clock.p2 = limit->p2.p2_slow;
782 } else {
783 if (target < limit->p2.dot_limit)
784 clock.p2 = limit->p2.p2_slow;
785 else
786 clock.p2 = limit->p2.p2_fast;
787 }
788
789 memset(best_clock, 0, sizeof(*best_clock));
790 max_n = limit->n.max;
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 /* based on hardware requirement, prefere larger m1,m2 */
794 for (clock.m1 = limit->m1.max;
795 clock.m1 >= limit->m1.min; clock.m1--) {
796 for (clock.m2 = limit->m2.max;
797 clock.m2 >= limit->m2.min; clock.m2--) {
798 for (clock.p1 = limit->p1.max;
799 clock.p1 >= limit->p1.min; clock.p1--) {
800 int this_err;
801
802 i9xx_clock(refclk, &clock);
803 if (!intel_PLL_is_valid(dev, limit,
804 &clock))
805 continue;
806
807 this_err = abs(clock.dot - target);
808 if (this_err < err_most) {
809 *best_clock = clock;
810 err_most = this_err;
811 max_n = clock.n;
812 found = true;
813 }
814 }
815 }
816 }
817 }
818 return found;
819}
820
821/*
822 * Check if the calculated PLL configuration is more optimal compared to the
823 * best configuration and error found so far. Return the calculated error.
824 */
825static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
826 const intel_clock_t *calculated_clock,
827 const intel_clock_t *best_clock,
828 unsigned int best_error_ppm,
829 unsigned int *error_ppm)
830{
831 /*
832 * For CHV ignore the error and consider only the P value.
833 * Prefer a bigger P value based on HW requirements.
834 */
835 if (IS_CHERRYVIEW(dev)) {
836 *error_ppm = 0;
837
838 return calculated_clock->p > best_clock->p;
839 }
840
841 if (WARN_ON_ONCE(!target_freq))
842 return false;
843
844 *error_ppm = div_u64(1000000ULL *
845 abs(target_freq - calculated_clock->dot),
846 target_freq);
847 /*
848 * Prefer a better P value over a better (smaller) error if the error
849 * is small. Ensure this preference for future configurations too by
850 * setting the error to 0.
851 */
852 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
853 *error_ppm = 0;
854
855 return true;
856 }
857
858 return *error_ppm + 10 < best_error_ppm;
859}
860
861static bool
862vlv_find_best_dpll(const intel_limit_t *limit,
863 struct intel_crtc_state *crtc_state,
864 int target, int refclk, intel_clock_t *match_clock,
865 intel_clock_t *best_clock)
866{
867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
868 struct drm_device *dev = crtc->base.dev;
869 intel_clock_t clock;
870 unsigned int bestppm = 1000000;
871 /* min update 19.2 MHz */
872 int max_n = min(limit->n.max, refclk / 19200);
873 bool found = false;
874
875 target *= 5; /* fast clock */
876
877 memset(best_clock, 0, sizeof(*best_clock));
878
879 /* based on hardware requirement, prefer smaller n to precision */
880 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
881 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
882 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
883 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
884 clock.p = clock.p1 * clock.p2;
885 /* based on hardware requirement, prefer bigger m1,m2 values */
886 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
887 unsigned int ppm;
888
889 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
890 refclk * clock.m1);
891
892 vlv_clock(refclk, &clock);
893
894 if (!intel_PLL_is_valid(dev, limit,
895 &clock))
896 continue;
897
898 if (!vlv_PLL_is_optimal(dev, target,
899 &clock,
900 best_clock,
901 bestppm, &ppm))
902 continue;
903
904 *best_clock = clock;
905 bestppm = ppm;
906 found = true;
907 }
908 }
909 }
910 }
911
912 return found;
913}
914
915static bool
916chv_find_best_dpll(const intel_limit_t *limit,
917 struct intel_crtc_state *crtc_state,
918 int target, int refclk, intel_clock_t *match_clock,
919 intel_clock_t *best_clock)
920{
921 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
922 struct drm_device *dev = crtc->base.dev;
923 unsigned int best_error_ppm;
924 intel_clock_t clock;
925 uint64_t m2;
926 int found = false;
927
928 memset(best_clock, 0, sizeof(*best_clock));
929 best_error_ppm = 1000000;
930
931 /*
932 * Based on hardware doc, the n always set to 1, and m1 always
933 * set to 2. If requires to support 200Mhz refclk, we need to
934 * revisit this because n may not 1 anymore.
935 */
936 clock.n = 1, clock.m1 = 2;
937 target *= 5; /* fast clock */
938
939 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
940 for (clock.p2 = limit->p2.p2_fast;
941 clock.p2 >= limit->p2.p2_slow;
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
943 unsigned int error_ppm;
944
945 clock.p = clock.p1 * clock.p2;
946
947 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
948 clock.n) << 22, refclk * clock.m1);
949
950 if (m2 > INT_MAX/clock.m1)
951 continue;
952
953 clock.m2 = m2;
954
955 chv_clock(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit, &clock))
958 continue;
959
960 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
961 best_error_ppm, &error_ppm))
962 continue;
963
964 *best_clock = clock;
965 best_error_ppm = error_ppm;
966 found = true;
967 }
968 }
969
970 return found;
971}
972
973bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
974 intel_clock_t *best_clock)
975{
976 int refclk = i9xx_get_refclk(crtc_state, 0);
977
978 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
979 target_clock, refclk, NULL, best_clock);
980}
981
982bool intel_crtc_active(struct drm_crtc *crtc)
983{
984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
985
986 /* Be paranoid as we can arrive here with only partial
987 * state retrieved from the hardware during setup.
988 *
989 * We can ditch the adjusted_mode.crtc_clock check as soon
990 * as Haswell has gained clock readout/fastboot support.
991 *
992 * We can ditch the crtc->primary->fb check as soon as we can
993 * properly reconstruct framebuffers.
994 *
995 * FIXME: The intel_crtc->active here should be switched to
996 * crtc->state->active once we have proper CRTC states wired up
997 * for atomic.
998 */
999 return intel_crtc->active && crtc->primary->state->fb &&
1000 intel_crtc->config->base.adjusted_mode.crtc_clock;
1001}
1002
1003enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1004 enum pipe pipe)
1005{
1006 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008
1009 return intel_crtc->config->cpu_transcoder;
1010}
1011
1012static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1013{
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 u32 reg = PIPEDSL(pipe);
1016 u32 line1, line2;
1017 u32 line_mask;
1018
1019 if (IS_GEN2(dev))
1020 line_mask = DSL_LINEMASK_GEN2;
1021 else
1022 line_mask = DSL_LINEMASK_GEN3;
1023
1024 line1 = I915_READ(reg) & line_mask;
1025 mdelay(5);
1026 line2 = I915_READ(reg) & line_mask;
1027
1028 return line1 == line2;
1029}
1030
1031/*
1032 * intel_wait_for_pipe_off - wait for pipe to turn off
1033 * @crtc: crtc whose pipe to wait for
1034 *
1035 * After disabling a pipe, we can't wait for vblank in the usual way,
1036 * spinning on the vblank interrupt status bit, since we won't actually
1037 * see an interrupt when the pipe is disabled.
1038 *
1039 * On Gen4 and above:
1040 * wait for the pipe register state bit to turn off
1041 *
1042 * Otherwise:
1043 * wait for the display line value to settle (it usually
1044 * ends up stopping at the start of the next frame).
1045 *
1046 */
1047static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1048{
1049 struct drm_device *dev = crtc->base.dev;
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1052 enum pipe pipe = crtc->pipe;
1053
1054 if (INTEL_INFO(dev)->gen >= 4) {
1055 int reg = PIPECONF(cpu_transcoder);
1056
1057 /* Wait for the Pipe State to go off */
1058 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1059 100))
1060 WARN(1, "pipe_off wait timed out\n");
1061 } else {
1062 /* Wait for the display line to settle */
1063 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1064 WARN(1, "pipe_off wait timed out\n");
1065 }
1066}
1067
1068/*
1069 * ibx_digital_port_connected - is the specified port connected?
1070 * @dev_priv: i915 private structure
1071 * @port: the port to test
1072 *
1073 * Returns true if @port is connected, false otherwise.
1074 */
1075bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1076 struct intel_digital_port *port)
1077{
1078 u32 bit;
1079
1080 if (HAS_PCH_IBX(dev_priv->dev)) {
1081 switch (port->port) {
1082 case PORT_B:
1083 bit = SDE_PORTB_HOTPLUG;
1084 break;
1085 case PORT_C:
1086 bit = SDE_PORTC_HOTPLUG;
1087 break;
1088 case PORT_D:
1089 bit = SDE_PORTD_HOTPLUG;
1090 break;
1091 default:
1092 return true;
1093 }
1094 } else {
1095 switch (port->port) {
1096 case PORT_B:
1097 bit = SDE_PORTB_HOTPLUG_CPT;
1098 break;
1099 case PORT_C:
1100 bit = SDE_PORTC_HOTPLUG_CPT;
1101 break;
1102 case PORT_D:
1103 bit = SDE_PORTD_HOTPLUG_CPT;
1104 break;
1105 default:
1106 return true;
1107 }
1108 }
1109
1110 return I915_READ(SDEISR) & bit;
1111}
1112
1113static const char *state_string(bool enabled)
1114{
1115 return enabled ? "on" : "off";
1116}
1117
1118/* Only for pre-ILK configs */
1119void assert_pll(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = DPLL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & DPLL_VCO_ENABLE);
1129 I915_STATE_WARN(cur_state != state,
1130 "PLL state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132}
1133
1134/* XXX: the dsi pll is shared between MIPI DSI ports */
1135static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1136{
1137 u32 val;
1138 bool cur_state;
1139
1140 mutex_lock(&dev_priv->dpio_lock);
1141 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1142 mutex_unlock(&dev_priv->dpio_lock);
1143
1144 cur_state = val & DSI_PLL_VCO_EN;
1145 I915_STATE_WARN(cur_state != state,
1146 "DSI PLL state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148}
1149#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1150#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1151
1152struct intel_shared_dpll *
1153intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1154{
1155 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1156
1157 if (crtc->config->shared_dpll < 0)
1158 return NULL;
1159
1160 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1161}
1162
1163/* For ILK+ */
1164void assert_shared_dpll(struct drm_i915_private *dev_priv,
1165 struct intel_shared_dpll *pll,
1166 bool state)
1167{
1168 bool cur_state;
1169 struct intel_dpll_hw_state hw_state;
1170
1171 if (WARN (!pll,
1172 "asserting DPLL %s with no DPLL\n", state_string(state)))
1173 return;
1174
1175 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1176 I915_STATE_WARN(cur_state != state,
1177 "%s assertion failure (expected %s, current %s)\n",
1178 pll->name, state_string(state), state_string(cur_state));
1179}
1180
1181static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183{
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1188 pipe);
1189
1190 if (HAS_DDI(dev_priv->dev)) {
1191 /* DDI does not have a specific FDI_TX register */
1192 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1195 } else {
1196 reg = FDI_TX_CTL(pipe);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & FDI_TX_ENABLE);
1199 }
1200 I915_STATE_WARN(cur_state != state,
1201 "FDI TX state assertion failure (expected %s, current %s)\n",
1202 state_string(state), state_string(cur_state));
1203}
1204#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1205#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1206
1207static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1208 enum pipe pipe, bool state)
1209{
1210 int reg;
1211 u32 val;
1212 bool cur_state;
1213
1214 reg = FDI_RX_CTL(pipe);
1215 val = I915_READ(reg);
1216 cur_state = !!(val & FDI_RX_ENABLE);
1217 I915_STATE_WARN(cur_state != state,
1218 "FDI RX state assertion failure (expected %s, current %s)\n",
1219 state_string(state), state_string(cur_state));
1220}
1221#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1222#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1223
1224static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
1226{
1227 int reg;
1228 u32 val;
1229
1230 /* ILK FDI PLL is always enabled */
1231 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1232 return;
1233
1234 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1235 if (HAS_DDI(dev_priv->dev))
1236 return;
1237
1238 reg = FDI_TX_CTL(pipe);
1239 val = I915_READ(reg);
1240 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1241}
1242
1243void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1244 enum pipe pipe, bool state)
1245{
1246 int reg;
1247 u32 val;
1248 bool cur_state;
1249
1250 reg = FDI_RX_CTL(pipe);
1251 val = I915_READ(reg);
1252 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1253 I915_STATE_WARN(cur_state != state,
1254 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1255 state_string(state), state_string(cur_state));
1256}
1257
1258void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1259 enum pipe pipe)
1260{
1261 struct drm_device *dev = dev_priv->dev;
1262 int pp_reg;
1263 u32 val;
1264 enum pipe panel_pipe = PIPE_A;
1265 bool locked = true;
1266
1267 if (WARN_ON(HAS_DDI(dev)))
1268 return;
1269
1270 if (HAS_PCH_SPLIT(dev)) {
1271 u32 port_sel;
1272
1273 pp_reg = PCH_PP_CONTROL;
1274 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1275
1276 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1277 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1278 panel_pipe = PIPE_B;
1279 /* XXX: else fix for eDP */
1280 } else if (IS_VALLEYVIEW(dev)) {
1281 /* presumably write lock depends on pipe, not port select */
1282 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1283 panel_pipe = pipe;
1284 } else {
1285 pp_reg = PP_CONTROL;
1286 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1287 panel_pipe = PIPE_B;
1288 }
1289
1290 val = I915_READ(pp_reg);
1291 if (!(val & PANEL_POWER_ON) ||
1292 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1293 locked = false;
1294
1295 I915_STATE_WARN(panel_pipe == pipe && locked,
1296 "panel assertion failure, pipe %c regs locked\n",
1297 pipe_name(pipe));
1298}
1299
1300static void assert_cursor(struct drm_i915_private *dev_priv,
1301 enum pipe pipe, bool state)
1302{
1303 struct drm_device *dev = dev_priv->dev;
1304 bool cur_state;
1305
1306 if (IS_845G(dev) || IS_I865G(dev))
1307 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1308 else
1309 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1310
1311 I915_STATE_WARN(cur_state != state,
1312 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1313 pipe_name(pipe), state_string(state), state_string(cur_state));
1314}
1315#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1316#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1317
1318void assert_pipe(struct drm_i915_private *dev_priv,
1319 enum pipe pipe, bool state)
1320{
1321 int reg;
1322 u32 val;
1323 bool cur_state;
1324 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1325 pipe);
1326
1327 /* if we need the pipe quirk it must be always on */
1328 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1329 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1330 state = true;
1331
1332 if (!intel_display_power_is_enabled(dev_priv,
1333 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1334 cur_state = false;
1335 } else {
1336 reg = PIPECONF(cpu_transcoder);
1337 val = I915_READ(reg);
1338 cur_state = !!(val & PIPECONF_ENABLE);
1339 }
1340
1341 I915_STATE_WARN(cur_state != state,
1342 "pipe %c assertion failure (expected %s, current %s)\n",
1343 pipe_name(pipe), state_string(state), state_string(cur_state));
1344}
1345
1346static void assert_plane(struct drm_i915_private *dev_priv,
1347 enum plane plane, bool state)
1348{
1349 int reg;
1350 u32 val;
1351 bool cur_state;
1352
1353 reg = DSPCNTR(plane);
1354 val = I915_READ(reg);
1355 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1356 I915_STATE_WARN(cur_state != state,
1357 "plane %c assertion failure (expected %s, current %s)\n",
1358 plane_name(plane), state_string(state), state_string(cur_state));
1359}
1360
1361#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1362#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1363
1364static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366{
1367 struct drm_device *dev = dev_priv->dev;
1368 int reg, i;
1369 u32 val;
1370 int cur_pipe;
1371
1372 /* Primary planes are fixed to pipes on gen4+ */
1373 if (INTEL_INFO(dev)->gen >= 4) {
1374 reg = DSPCNTR(pipe);
1375 val = I915_READ(reg);
1376 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1377 "plane %c assertion failure, should be disabled but not\n",
1378 plane_name(pipe));
1379 return;
1380 }
1381
1382 /* Need to check both planes against the pipe */
1383 for_each_pipe(dev_priv, i) {
1384 reg = DSPCNTR(i);
1385 val = I915_READ(reg);
1386 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1387 DISPPLANE_SEL_PIPE_SHIFT;
1388 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1389 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1390 plane_name(i), pipe_name(pipe));
1391 }
1392}
1393
1394static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 struct drm_device *dev = dev_priv->dev;
1398 int reg, sprite;
1399 u32 val;
1400
1401 if (INTEL_INFO(dev)->gen >= 9) {
1402 for_each_sprite(dev_priv, pipe, sprite) {
1403 val = I915_READ(PLANE_CTL(pipe, sprite));
1404 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1405 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1406 sprite, pipe_name(pipe));
1407 }
1408 } else if (IS_VALLEYVIEW(dev)) {
1409 for_each_sprite(dev_priv, pipe, sprite) {
1410 reg = SPCNTR(pipe, sprite);
1411 val = I915_READ(reg);
1412 I915_STATE_WARN(val & SP_ENABLE,
1413 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1414 sprite_name(pipe, sprite), pipe_name(pipe));
1415 }
1416 } else if (INTEL_INFO(dev)->gen >= 7) {
1417 reg = SPRCTL(pipe);
1418 val = I915_READ(reg);
1419 I915_STATE_WARN(val & SPRITE_ENABLE,
1420 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1421 plane_name(pipe), pipe_name(pipe));
1422 } else if (INTEL_INFO(dev)->gen >= 5) {
1423 reg = DVSCNTR(pipe);
1424 val = I915_READ(reg);
1425 I915_STATE_WARN(val & DVS_ENABLE,
1426 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1427 plane_name(pipe), pipe_name(pipe));
1428 }
1429}
1430
1431static void assert_vblank_disabled(struct drm_crtc *crtc)
1432{
1433 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1434 drm_crtc_vblank_put(crtc);
1435}
1436
1437static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1438{
1439 u32 val;
1440 bool enabled;
1441
1442 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1443
1444 val = I915_READ(PCH_DREF_CONTROL);
1445 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1446 DREF_SUPERSPREAD_SOURCE_MASK));
1447 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1448}
1449
1450static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe)
1452{
1453 int reg;
1454 u32 val;
1455 bool enabled;
1456
1457 reg = PCH_TRANSCONF(pipe);
1458 val = I915_READ(reg);
1459 enabled = !!(val & TRANS_ENABLE);
1460 I915_STATE_WARN(enabled,
1461 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1462 pipe_name(pipe));
1463}
1464
1465static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1466 enum pipe pipe, u32 port_sel, u32 val)
1467{
1468 if ((val & DP_PORT_EN) == 0)
1469 return false;
1470
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1473 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1474 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1475 return false;
1476 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1477 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1478 return false;
1479 } else {
1480 if ((val & DP_PIPE_MASK) != (pipe << 30))
1481 return false;
1482 }
1483 return true;
1484}
1485
1486static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, u32 val)
1488{
1489 if ((val & SDVO_ENABLE) == 0)
1490 return false;
1491
1492 if (HAS_PCH_CPT(dev_priv->dev)) {
1493 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1494 return false;
1495 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1496 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1497 return false;
1498 } else {
1499 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1500 return false;
1501 }
1502 return true;
1503}
1504
1505static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1506 enum pipe pipe, u32 val)
1507{
1508 if ((val & LVDS_PORT_EN) == 0)
1509 return false;
1510
1511 if (HAS_PCH_CPT(dev_priv->dev)) {
1512 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1513 return false;
1514 } else {
1515 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1516 return false;
1517 }
1518 return true;
1519}
1520
1521static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1522 enum pipe pipe, u32 val)
1523{
1524 if ((val & ADPA_DAC_ENABLE) == 0)
1525 return false;
1526 if (HAS_PCH_CPT(dev_priv->dev)) {
1527 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1528 return false;
1529 } else {
1530 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1531 return false;
1532 }
1533 return true;
1534}
1535
1536static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe, int reg, u32 port_sel)
1538{
1539 u32 val = I915_READ(reg);
1540 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1541 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1542 reg, pipe_name(pipe));
1543
1544 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1545 && (val & DP_PIPEB_SELECT),
1546 "IBX PCH dp port still using transcoder B\n");
1547}
1548
1549static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1550 enum pipe pipe, int reg)
1551{
1552 u32 val = I915_READ(reg);
1553 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1554 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1555 reg, pipe_name(pipe));
1556
1557 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1558 && (val & SDVO_PIPE_B_SELECT),
1559 "IBX PCH hdmi port still using transcoder B\n");
1560}
1561
1562static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1563 enum pipe pipe)
1564{
1565 int reg;
1566 u32 val;
1567
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1570 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1571
1572 reg = PCH_ADPA;
1573 val = I915_READ(reg);
1574 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1575 "PCH VGA enabled on transcoder %c, should be disabled\n",
1576 pipe_name(pipe));
1577
1578 reg = PCH_LVDS;
1579 val = I915_READ(reg);
1580 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1581 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1582 pipe_name(pipe));
1583
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1586 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1587}
1588
1589static void intel_init_dpio(struct drm_device *dev)
1590{
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592
1593 if (!IS_VALLEYVIEW(dev))
1594 return;
1595
1596 /*
1597 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1598 * CHV x1 PHY (DP/HDMI D)
1599 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1600 */
1601 if (IS_CHERRYVIEW(dev)) {
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1604 } else {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1606 }
1607}
1608
1609static void vlv_enable_pll(struct intel_crtc *crtc,
1610 const struct intel_crtc_state *pipe_config)
1611{
1612 struct drm_device *dev = crtc->base.dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 int reg = DPLL(crtc->pipe);
1615 u32 dpll = pipe_config->dpll_hw_state.dpll;
1616
1617 assert_pipe_disabled(dev_priv, crtc->pipe);
1618
1619 /* No really, not for ILK+ */
1620 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1621
1622 /* PLL is protected by panel, make sure we can write it */
1623 if (IS_MOBILE(dev_priv->dev))
1624 assert_panel_unlocked(dev_priv, crtc->pipe);
1625
1626 I915_WRITE(reg, dpll);
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1631 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1632
1633 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1634 POSTING_READ(DPLL_MD(crtc->pipe));
1635
1636 /* We do this three times for luck */
1637 I915_WRITE(reg, dpll);
1638 POSTING_READ(reg);
1639 udelay(150); /* wait for warmup */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646}
1647
1648static void chv_enable_pll(struct intel_crtc *crtc,
1649 const struct intel_crtc_state *pipe_config)
1650{
1651 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 int pipe = crtc->pipe;
1654 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1655 u32 tmp;
1656
1657 assert_pipe_disabled(dev_priv, crtc->pipe);
1658
1659 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1660
1661 mutex_lock(&dev_priv->dpio_lock);
1662
1663 /* Enable back the 10bit clock to display controller */
1664 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1665 tmp |= DPIO_DCLKP_EN;
1666 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1667
1668 /*
1669 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1670 */
1671 udelay(1);
1672
1673 /* Enable PLL */
1674 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1675
1676 /* Check PLL is locked */
1677 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1678 DRM_ERROR("PLL %d failed to lock\n", pipe);
1679
1680 /* not sure when this should be written */
1681 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1682 POSTING_READ(DPLL_MD(pipe));
1683
1684 mutex_unlock(&dev_priv->dpio_lock);
1685}
1686
1687static int intel_num_dvo_pipes(struct drm_device *dev)
1688{
1689 struct intel_crtc *crtc;
1690 int count = 0;
1691
1692 for_each_intel_crtc(dev, crtc)
1693 count += crtc->active &&
1694 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1695
1696 return count;
1697}
1698
1699static void i9xx_enable_pll(struct intel_crtc *crtc)
1700{
1701 struct drm_device *dev = crtc->base.dev;
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 int reg = DPLL(crtc->pipe);
1704 u32 dpll = crtc->config->dpll_hw_state.dpll;
1705
1706 assert_pipe_disabled(dev_priv, crtc->pipe);
1707
1708 /* No really, not for ILK+ */
1709 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1710
1711 /* PLL is protected by panel, make sure we can write it */
1712 if (IS_MOBILE(dev) && !IS_I830(dev))
1713 assert_panel_unlocked(dev_priv, crtc->pipe);
1714
1715 /* Enable DVO 2x clock on both PLLs if necessary */
1716 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1717 /*
1718 * It appears to be important that we don't enable this
1719 * for the current pipe before otherwise configuring the
1720 * PLL. No idea how this should be handled if multiple
1721 * DVO outputs are enabled simultaneosly.
1722 */
1723 dpll |= DPLL_DVO_2X_MODE;
1724 I915_WRITE(DPLL(!crtc->pipe),
1725 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1726 }
1727
1728 /* Wait for the clocks to stabilize. */
1729 POSTING_READ(reg);
1730 udelay(150);
1731
1732 if (INTEL_INFO(dev)->gen >= 4) {
1733 I915_WRITE(DPLL_MD(crtc->pipe),
1734 crtc->config->dpll_hw_state.dpll_md);
1735 } else {
1736 /* The pixel multiplier can only be updated once the
1737 * DPLL is enabled and the clocks are stable.
1738 *
1739 * So write it again.
1740 */
1741 I915_WRITE(reg, dpll);
1742 }
1743
1744 /* We do this three times for luck */
1745 I915_WRITE(reg, dpll);
1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg, dpll);
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754}
1755
1756/**
1757 * i9xx_disable_pll - disable a PLL
1758 * @dev_priv: i915 private structure
1759 * @pipe: pipe PLL to disable
1760 *
1761 * Disable the PLL for @pipe, making sure the pipe is off first.
1762 *
1763 * Note! This is for pre-ILK only.
1764 */
1765static void i9xx_disable_pll(struct intel_crtc *crtc)
1766{
1767 struct drm_device *dev = crtc->base.dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 enum pipe pipe = crtc->pipe;
1770
1771 /* Disable DVO 2x clock on both PLLs if necessary */
1772 if (IS_I830(dev) &&
1773 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1774 intel_num_dvo_pipes(dev) == 1) {
1775 I915_WRITE(DPLL(PIPE_B),
1776 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1777 I915_WRITE(DPLL(PIPE_A),
1778 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1779 }
1780
1781 /* Don't disable pipe or pipe PLLs if needed */
1782 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1783 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1784 return;
1785
1786 /* Make sure the pipe isn't still relying on us */
1787 assert_pipe_disabled(dev_priv, pipe);
1788
1789 I915_WRITE(DPLL(pipe), 0);
1790 POSTING_READ(DPLL(pipe));
1791}
1792
1793static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1794{
1795 u32 val = 0;
1796
1797 /* Make sure the pipe isn't still relying on us */
1798 assert_pipe_disabled(dev_priv, pipe);
1799
1800 /*
1801 * Leave integrated clock source and reference clock enabled for pipe B.
1802 * The latter is needed for VGA hotplug / manual detection.
1803 */
1804 if (pipe == PIPE_B)
1805 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1806 I915_WRITE(DPLL(pipe), val);
1807 POSTING_READ(DPLL(pipe));
1808
1809}
1810
1811static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812{
1813 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1814 u32 val;
1815
1816 /* Make sure the pipe isn't still relying on us */
1817 assert_pipe_disabled(dev_priv, pipe);
1818
1819 /* Set PLL en = 0 */
1820 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1821 if (pipe != PIPE_A)
1822 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1823 I915_WRITE(DPLL(pipe), val);
1824 POSTING_READ(DPLL(pipe));
1825
1826 mutex_lock(&dev_priv->dpio_lock);
1827
1828 /* Disable 10bit clock to display controller */
1829 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1830 val &= ~DPIO_DCLKP_EN;
1831 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1832
1833 /* disable left/right clock distribution */
1834 if (pipe != PIPE_B) {
1835 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1836 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1837 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1838 } else {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1840 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1842 }
1843
1844 mutex_unlock(&dev_priv->dpio_lock);
1845}
1846
1847void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1848 struct intel_digital_port *dport)
1849{
1850 u32 port_mask;
1851 int dpll_reg;
1852
1853 switch (dport->port) {
1854 case PORT_B:
1855 port_mask = DPLL_PORTB_READY_MASK;
1856 dpll_reg = DPLL(0);
1857 break;
1858 case PORT_C:
1859 port_mask = DPLL_PORTC_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
1865 break;
1866 default:
1867 BUG();
1868 }
1869
1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1871 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1872 port_name(dport->port), I915_READ(dpll_reg));
1873}
1874
1875static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876{
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881 if (WARN_ON(pll == NULL))
1882 return;
1883
1884 WARN_ON(!pll->config.crtc_mask);
1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892}
1893
1894/**
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
1902static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903{
1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908 if (WARN_ON(pll == NULL))
1909 return;
1910
1911 if (WARN_ON(pll->config.crtc_mask == 0))
1912 return;
1913
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll->name, pll->active, pll->on,
1916 crtc->base.base.id);
1917
1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
1920 assert_shared_dpll_enabled(dev_priv, pll);
1921 return;
1922 }
1923 WARN_ON(pll->on);
1924
1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928 pll->enable(dev_priv, pll);
1929 pll->on = true;
1930}
1931
1932static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933{
1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev)->gen < 5);
1940 if (WARN_ON(pll == NULL))
1941 return;
1942
1943 if (WARN_ON(pll->config.crtc_mask == 0))
1944 return;
1945
1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll->name, pll->active, pll->on,
1948 crtc->base.base.id);
1949
1950 if (WARN_ON(pll->active == 0)) {
1951 assert_shared_dpll_disabled(dev_priv, pll);
1952 return;
1953 }
1954
1955 assert_shared_dpll_enabled(dev_priv, pll);
1956 WARN_ON(!pll->on);
1957 if (--pll->active)
1958 return;
1959
1960 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1961 pll->disable(dev_priv, pll);
1962 pll->on = false;
1963
1964 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1965}
1966
1967static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1968 enum pipe pipe)
1969{
1970 struct drm_device *dev = dev_priv->dev;
1971 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1973 uint32_t reg, val, pipeconf_val;
1974
1975 /* PCH only available on ILK+ */
1976 BUG_ON(!HAS_PCH_SPLIT(dev));
1977
1978 /* Make sure PCH DPLL is enabled */
1979 assert_shared_dpll_enabled(dev_priv,
1980 intel_crtc_to_shared_dpll(intel_crtc));
1981
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv, pipe);
1984 assert_fdi_rx_enabled(dev_priv, pipe);
1985
1986 if (HAS_PCH_CPT(dev)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg = TRANS_CHICKEN2(pipe);
1990 val = I915_READ(reg);
1991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992 I915_WRITE(reg, val);
1993 }
1994
1995 reg = PCH_TRANSCONF(pipe);
1996 val = I915_READ(reg);
1997 pipeconf_val = I915_READ(PIPECONF(pipe));
1998
1999 if (HAS_PCH_IBX(dev_priv->dev)) {
2000 /*
2001 * make the BPC in transcoder be consistent with
2002 * that in pipeconf reg.
2003 */
2004 val &= ~PIPECONF_BPC_MASK;
2005 val |= pipeconf_val & PIPECONF_BPC_MASK;
2006 }
2007
2008 val &= ~TRANS_INTERLACE_MASK;
2009 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2010 if (HAS_PCH_IBX(dev_priv->dev) &&
2011 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2012 val |= TRANS_LEGACY_INTERLACED_ILK;
2013 else
2014 val |= TRANS_INTERLACED;
2015 else
2016 val |= TRANS_PROGRESSIVE;
2017
2018 I915_WRITE(reg, val | TRANS_ENABLE);
2019 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2020 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2021}
2022
2023static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2024 enum transcoder cpu_transcoder)
2025{
2026 u32 val, pipeconf_val;
2027
2028 /* PCH only available on ILK+ */
2029 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2030
2031 /* FDI must be feeding us bits for PCH ports */
2032 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2033 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2034
2035 /* Workaround: set timing override bit. */
2036 val = I915_READ(_TRANSA_CHICKEN2);
2037 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2038 I915_WRITE(_TRANSA_CHICKEN2, val);
2039
2040 val = TRANS_ENABLE;
2041 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2042
2043 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2044 PIPECONF_INTERLACED_ILK)
2045 val |= TRANS_INTERLACED;
2046 else
2047 val |= TRANS_PROGRESSIVE;
2048
2049 I915_WRITE(LPT_TRANSCONF, val);
2050 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2051 DRM_ERROR("Failed to enable PCH transcoder\n");
2052}
2053
2054static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2055 enum pipe pipe)
2056{
2057 struct drm_device *dev = dev_priv->dev;
2058 uint32_t reg, val;
2059
2060 /* FDI relies on the transcoder */
2061 assert_fdi_tx_disabled(dev_priv, pipe);
2062 assert_fdi_rx_disabled(dev_priv, pipe);
2063
2064 /* Ports must be off as well */
2065 assert_pch_ports_disabled(dev_priv, pipe);
2066
2067 reg = PCH_TRANSCONF(pipe);
2068 val = I915_READ(reg);
2069 val &= ~TRANS_ENABLE;
2070 I915_WRITE(reg, val);
2071 /* wait for PCH transcoder off, transcoder state */
2072 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2073 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2074
2075 if (!HAS_PCH_IBX(dev)) {
2076 /* Workaround: Clear the timing override chicken bit again. */
2077 reg = TRANS_CHICKEN2(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080 I915_WRITE(reg, val);
2081 }
2082}
2083
2084static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2085{
2086 u32 val;
2087
2088 val = I915_READ(LPT_TRANSCONF);
2089 val &= ~TRANS_ENABLE;
2090 I915_WRITE(LPT_TRANSCONF, val);
2091 /* wait for PCH transcoder off, transcoder state */
2092 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2093 DRM_ERROR("Failed to disable PCH transcoder\n");
2094
2095 /* Workaround: clear timing override bit. */
2096 val = I915_READ(_TRANSA_CHICKEN2);
2097 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2098 I915_WRITE(_TRANSA_CHICKEN2, val);
2099}
2100
2101/**
2102 * intel_enable_pipe - enable a pipe, asserting requirements
2103 * @crtc: crtc responsible for the pipe
2104 *
2105 * Enable @crtc's pipe, making sure that various hardware specific requirements
2106 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2107 */
2108static void intel_enable_pipe(struct intel_crtc *crtc)
2109{
2110 struct drm_device *dev = crtc->base.dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112 enum pipe pipe = crtc->pipe;
2113 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2114 pipe);
2115 enum pipe pch_transcoder;
2116 int reg;
2117 u32 val;
2118
2119 assert_planes_disabled(dev_priv, pipe);
2120 assert_cursor_disabled(dev_priv, pipe);
2121 assert_sprites_disabled(dev_priv, pipe);
2122
2123 if (HAS_PCH_LPT(dev_priv->dev))
2124 pch_transcoder = TRANSCODER_A;
2125 else
2126 pch_transcoder = pipe;
2127
2128 /*
2129 * A pipe without a PLL won't actually be able to drive bits from
2130 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2131 * need the check.
2132 */
2133 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2134 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2135 assert_dsi_pll_enabled(dev_priv);
2136 else
2137 assert_pll_enabled(dev_priv, pipe);
2138 else {
2139 if (crtc->config->has_pch_encoder) {
2140 /* if driving the PCH, we need FDI enabled */
2141 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2142 assert_fdi_tx_pll_enabled(dev_priv,
2143 (enum pipe) cpu_transcoder);
2144 }
2145 /* FIXME: assert CPU port conditions for SNB+ */
2146 }
2147
2148 reg = PIPECONF(cpu_transcoder);
2149 val = I915_READ(reg);
2150 if (val & PIPECONF_ENABLE) {
2151 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2152 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2153 return;
2154 }
2155
2156 I915_WRITE(reg, val | PIPECONF_ENABLE);
2157 POSTING_READ(reg);
2158}
2159
2160/**
2161 * intel_disable_pipe - disable a pipe, asserting requirements
2162 * @crtc: crtc whose pipes is to be disabled
2163 *
2164 * Disable the pipe of @crtc, making sure that various hardware
2165 * specific requirements are met, if applicable, e.g. plane
2166 * disabled, panel fitter off, etc.
2167 *
2168 * Will wait until the pipe has shut down before returning.
2169 */
2170static void intel_disable_pipe(struct intel_crtc *crtc)
2171{
2172 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2173 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2174 enum pipe pipe = crtc->pipe;
2175 int reg;
2176 u32 val;
2177
2178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
2183 assert_cursor_disabled(dev_priv, pipe);
2184 assert_sprites_disabled(dev_priv, pipe);
2185
2186 reg = PIPECONF(cpu_transcoder);
2187 val = I915_READ(reg);
2188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
2191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
2195 if (crtc->config->double_wide)
2196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
2206}
2207
2208/*
2209 * Plane regs are double buffered, going from enabled->disabled needs a
2210 * trigger in order to latch. The display address reg provides this.
2211 */
2212void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2213 enum plane plane)
2214{
2215 struct drm_device *dev = dev_priv->dev;
2216 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2217
2218 I915_WRITE(reg, I915_READ(reg));
2219 POSTING_READ(reg);
2220}
2221
2222/**
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2226 *
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2228 */
2229static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
2231{
2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2238 to_intel_plane_state(plane->state)->visible = true;
2239
2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
2242}
2243
2244static bool need_vtd_wa(struct drm_device *dev)
2245{
2246#ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249#endif
2250 return false;
2251}
2252
2253unsigned int
2254intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
2256{
2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
2259
2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
2273 default:
2274 case 1:
2275 tile_height = 64;
2276 break;
2277 case 2:
2278 case 4:
2279 tile_height = 32;
2280 break;
2281 case 8:
2282 tile_height = 16;
2283 break;
2284 case 16:
2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
2296
2297 return tile_height;
2298}
2299
2300unsigned int
2301intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303{
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
2306}
2307
2308static int
2309intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311{
2312 struct intel_rotation_info *info = &view->rotation_info;
2313
2314 *view = i915_ggtt_view_normal;
2315
2316 if (!plane_state)
2317 return 0;
2318
2319 if (!intel_rotation_90_or_270(plane_state->rotation))
2320 return 0;
2321
2322 *view = i915_ggtt_view_rotated;
2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
2329 return 0;
2330}
2331
2332int
2333intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2334 struct drm_framebuffer *fb,
2335 const struct drm_plane_state *plane_state,
2336 struct intel_engine_cs *pipelined)
2337{
2338 struct drm_device *dev = fb->dev;
2339 struct drm_i915_private *dev_priv = dev->dev_private;
2340 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2341 struct i915_ggtt_view view;
2342 u32 alignment;
2343 int ret;
2344
2345 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346
2347 switch (fb->modifier[0]) {
2348 case DRM_FORMAT_MOD_NONE:
2349 if (INTEL_INFO(dev)->gen >= 9)
2350 alignment = 256 * 1024;
2351 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2352 alignment = 128 * 1024;
2353 else if (INTEL_INFO(dev)->gen >= 4)
2354 alignment = 4 * 1024;
2355 else
2356 alignment = 64 * 1024;
2357 break;
2358 case I915_FORMAT_MOD_X_TILED:
2359 if (INTEL_INFO(dev)->gen >= 9)
2360 alignment = 256 * 1024;
2361 else {
2362 /* pin() will align the object as required by fence */
2363 alignment = 0;
2364 }
2365 break;
2366 case I915_FORMAT_MOD_Y_TILED:
2367 case I915_FORMAT_MOD_Yf_TILED:
2368 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2369 "Y tiling bo slipped through, driver bug!\n"))
2370 return -EINVAL;
2371 alignment = 1 * 1024 * 1024;
2372 break;
2373 default:
2374 MISSING_CASE(fb->modifier[0]);
2375 return -EINVAL;
2376 }
2377
2378 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2379 if (ret)
2380 return ret;
2381
2382 /* Note that the w/a also requires 64 PTE of padding following the
2383 * bo. We currently fill all unused PTE with the shadow page and so
2384 * we should always have valid PTE following the scanout preventing
2385 * the VT-d warning.
2386 */
2387 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2388 alignment = 256 * 1024;
2389
2390 /*
2391 * Global gtt pte registers are special registers which actually forward
2392 * writes to a chunk of system memory. Which means that there is no risk
2393 * that the register values disappear as soon as we call
2394 * intel_runtime_pm_put(), so it is correct to wrap only the
2395 * pin/unpin/fence and not more.
2396 */
2397 intel_runtime_pm_get(dev_priv);
2398
2399 dev_priv->mm.interruptible = false;
2400 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2401 &view);
2402 if (ret)
2403 goto err_interruptible;
2404
2405 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2406 * fence, whereas 965+ only requires a fence if using
2407 * framebuffer compression. For simplicity, we always install
2408 * a fence as the cost is not that onerous.
2409 */
2410 ret = i915_gem_object_get_fence(obj);
2411 if (ret)
2412 goto err_unpin;
2413
2414 i915_gem_object_pin_fence(obj);
2415
2416 dev_priv->mm.interruptible = true;
2417 intel_runtime_pm_put(dev_priv);
2418 return 0;
2419
2420err_unpin:
2421 i915_gem_object_unpin_from_display_plane(obj, &view);
2422err_interruptible:
2423 dev_priv->mm.interruptible = true;
2424 intel_runtime_pm_put(dev_priv);
2425 return ret;
2426}
2427
2428static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429 const struct drm_plane_state *plane_state)
2430{
2431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2432 struct i915_ggtt_view view;
2433 int ret;
2434
2435 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
2437 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438 WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
2440 i915_gem_object_unpin_fence(obj);
2441 i915_gem_object_unpin_from_display_plane(obj, &view);
2442}
2443
2444/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
2446unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2447 unsigned int tiling_mode,
2448 unsigned int cpp,
2449 unsigned int pitch)
2450{
2451 if (tiling_mode != I915_TILING_NONE) {
2452 unsigned int tile_rows, tiles;
2453
2454 tile_rows = *y / 8;
2455 *y %= 8;
2456
2457 tiles = *x / (512/cpp);
2458 *x %= 512/cpp;
2459
2460 return tile_rows * pitch * 8 + tiles * 4096;
2461 } else {
2462 unsigned int offset;
2463
2464 offset = *y * pitch + *x * cpp;
2465 *y = 0;
2466 *x = (offset & 4095) / cpp;
2467 return offset & -4096;
2468 }
2469}
2470
2471static int i9xx_format_to_fourcc(int format)
2472{
2473 switch (format) {
2474 case DISPPLANE_8BPP:
2475 return DRM_FORMAT_C8;
2476 case DISPPLANE_BGRX555:
2477 return DRM_FORMAT_XRGB1555;
2478 case DISPPLANE_BGRX565:
2479 return DRM_FORMAT_RGB565;
2480 default:
2481 case DISPPLANE_BGRX888:
2482 return DRM_FORMAT_XRGB8888;
2483 case DISPPLANE_RGBX888:
2484 return DRM_FORMAT_XBGR8888;
2485 case DISPPLANE_BGRX101010:
2486 return DRM_FORMAT_XRGB2101010;
2487 case DISPPLANE_RGBX101010:
2488 return DRM_FORMAT_XBGR2101010;
2489 }
2490}
2491
2492static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493{
2494 switch (format) {
2495 case PLANE_CTL_FORMAT_RGB_565:
2496 return DRM_FORMAT_RGB565;
2497 default:
2498 case PLANE_CTL_FORMAT_XRGB_8888:
2499 if (rgb_order) {
2500 if (alpha)
2501 return DRM_FORMAT_ABGR8888;
2502 else
2503 return DRM_FORMAT_XBGR8888;
2504 } else {
2505 if (alpha)
2506 return DRM_FORMAT_ARGB8888;
2507 else
2508 return DRM_FORMAT_XRGB8888;
2509 }
2510 case PLANE_CTL_FORMAT_XRGB_2101010:
2511 if (rgb_order)
2512 return DRM_FORMAT_XBGR2101010;
2513 else
2514 return DRM_FORMAT_XRGB2101010;
2515 }
2516}
2517
2518static bool
2519intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520 struct intel_initial_plane_config *plane_config)
2521{
2522 struct drm_device *dev = crtc->base.dev;
2523 struct drm_i915_gem_object *obj = NULL;
2524 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2525 struct drm_framebuffer *fb = &plane_config->fb->base;
2526 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2527 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2528 PAGE_SIZE);
2529
2530 size_aligned -= base_aligned;
2531
2532 if (plane_config->size == 0)
2533 return false;
2534
2535 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2536 base_aligned,
2537 base_aligned,
2538 size_aligned);
2539 if (!obj)
2540 return false;
2541
2542 obj->tiling_mode = plane_config->tiling;
2543 if (obj->tiling_mode == I915_TILING_X)
2544 obj->stride = fb->pitches[0];
2545
2546 mode_cmd.pixel_format = fb->pixel_format;
2547 mode_cmd.width = fb->width;
2548 mode_cmd.height = fb->height;
2549 mode_cmd.pitches[0] = fb->pitches[0];
2550 mode_cmd.modifier[0] = fb->modifier[0];
2551 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2552
2553 mutex_lock(&dev->struct_mutex);
2554 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2555 &mode_cmd, obj)) {
2556 DRM_DEBUG_KMS("intel fb init failed\n");
2557 goto out_unref_obj;
2558 }
2559 mutex_unlock(&dev->struct_mutex);
2560
2561 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2562 return true;
2563
2564out_unref_obj:
2565 drm_gem_object_unreference(&obj->base);
2566 mutex_unlock(&dev->struct_mutex);
2567 return false;
2568}
2569
2570/* Update plane->state->fb to match plane->fb after driver-internal updates */
2571static void
2572update_state_fb(struct drm_plane *plane)
2573{
2574 if (plane->fb == plane->state->fb)
2575 return;
2576
2577 if (plane->state->fb)
2578 drm_framebuffer_unreference(plane->state->fb);
2579 plane->state->fb = plane->fb;
2580 if (plane->state->fb)
2581 drm_framebuffer_reference(plane->state->fb);
2582}
2583
2584static void
2585intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2586 struct intel_initial_plane_config *plane_config)
2587{
2588 struct drm_device *dev = intel_crtc->base.dev;
2589 struct drm_i915_private *dev_priv = dev->dev_private;
2590 struct drm_crtc *c;
2591 struct intel_crtc *i;
2592 struct drm_i915_gem_object *obj;
2593 struct drm_plane *primary = intel_crtc->base.primary;
2594 struct drm_framebuffer *fb;
2595
2596 if (!plane_config->fb)
2597 return;
2598
2599 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2600 fb = &plane_config->fb->base;
2601 goto valid_fb;
2602 }
2603
2604 kfree(plane_config->fb);
2605
2606 /*
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2609 */
2610 for_each_crtc(dev, c) {
2611 i = to_intel_crtc(c);
2612
2613 if (c == &intel_crtc->base)
2614 continue;
2615
2616 if (!i->active)
2617 continue;
2618
2619 fb = c->primary->fb;
2620 if (!fb)
2621 continue;
2622
2623 obj = intel_fb_obj(fb);
2624 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2625 drm_framebuffer_reference(fb);
2626 goto valid_fb;
2627 }
2628 }
2629
2630 return;
2631
2632valid_fb:
2633 obj = intel_fb_obj(fb);
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dev_priv->preserve_bios_swizzle = true;
2636
2637 primary->fb = fb;
2638 primary->state->crtc = &intel_crtc->base;
2639 primary->crtc = &intel_crtc->base;
2640 update_state_fb(primary);
2641 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2642}
2643
2644static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2645 struct drm_framebuffer *fb,
2646 int x, int y)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 struct drm_plane *primary = crtc->primary;
2652 bool visible = to_intel_plane_state(primary->state)->visible;
2653 struct drm_i915_gem_object *obj;
2654 int plane = intel_crtc->plane;
2655 unsigned long linear_offset;
2656 u32 dspcntr;
2657 u32 reg = DSPCNTR(plane);
2658 int pixel_size;
2659
2660 if (!visible || !fb) {
2661 I915_WRITE(reg, 0);
2662 if (INTEL_INFO(dev)->gen >= 4)
2663 I915_WRITE(DSPSURF(plane), 0);
2664 else
2665 I915_WRITE(DSPADDR(plane), 0);
2666 POSTING_READ(reg);
2667 return;
2668 }
2669
2670 obj = intel_fb_obj(fb);
2671 if (WARN_ON(obj == NULL))
2672 return;
2673
2674 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2675
2676 dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
2678 dspcntr |= DISPLAY_PLANE_ENABLE;
2679
2680 if (INTEL_INFO(dev)->gen < 4) {
2681 if (intel_crtc->pipe == PIPE_B)
2682 dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2686 */
2687 I915_WRITE(DSPSIZE(plane),
2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
2690 I915_WRITE(DSPPOS(plane), 0);
2691 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692 I915_WRITE(PRIMSIZE(plane),
2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
2695 I915_WRITE(PRIMPOS(plane), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697 }
2698
2699 switch (fb->pixel_format) {
2700 case DRM_FORMAT_C8:
2701 dspcntr |= DISPPLANE_8BPP;
2702 break;
2703 case DRM_FORMAT_XRGB1555:
2704 case DRM_FORMAT_ARGB1555:
2705 dspcntr |= DISPPLANE_BGRX555;
2706 break;
2707 case DRM_FORMAT_RGB565:
2708 dspcntr |= DISPPLANE_BGRX565;
2709 break;
2710 case DRM_FORMAT_XRGB8888:
2711 case DRM_FORMAT_ARGB8888:
2712 dspcntr |= DISPPLANE_BGRX888;
2713 break;
2714 case DRM_FORMAT_XBGR8888:
2715 case DRM_FORMAT_ABGR8888:
2716 dspcntr |= DISPPLANE_RGBX888;
2717 break;
2718 case DRM_FORMAT_XRGB2101010:
2719 case DRM_FORMAT_ARGB2101010:
2720 dspcntr |= DISPPLANE_BGRX101010;
2721 break;
2722 case DRM_FORMAT_XBGR2101010:
2723 case DRM_FORMAT_ABGR2101010:
2724 dspcntr |= DISPPLANE_RGBX101010;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
2733
2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
2738
2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742 pixel_size,
2743 fb->pitches[0]);
2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
2746 intel_crtc->dspaddr_offset = linear_offset;
2747 }
2748
2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765 if (INTEL_INFO(dev)->gen >= 4) {
2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770 } else
2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2772 POSTING_READ(reg);
2773}
2774
2775static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
2784 struct drm_i915_gem_object *obj;
2785 int plane = intel_crtc->plane;
2786 unsigned long linear_offset;
2787 u32 dspcntr;
2788 u32 reg = DSPCNTR(plane);
2789 int pixel_size;
2790
2791 if (!visible || !fb) {
2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
2806 dspcntr |= DISPLAY_PLANE_ENABLE;
2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2810
2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
2817 break;
2818 case DRM_FORMAT_XRGB8888:
2819 case DRM_FORMAT_ARGB8888:
2820 dspcntr |= DISPPLANE_BGRX888;
2821 break;
2822 case DRM_FORMAT_XBGR8888:
2823 case DRM_FORMAT_ABGR8888:
2824 dspcntr |= DISPPLANE_RGBX888;
2825 break;
2826 case DRM_FORMAT_XRGB2101010:
2827 case DRM_FORMAT_ARGB2101010:
2828 dspcntr |= DISPPLANE_BGRX101010;
2829 break;
2830 case DRM_FORMAT_XBGR2101010:
2831 case DRM_FORMAT_ABGR2101010:
2832 dspcntr |= DISPPLANE_RGBX101010;
2833 break;
2834 default:
2835 BUG();
2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2843
2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
2845 intel_crtc->dspaddr_offset =
2846 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2847 pixel_size,
2848 fb->pitches[0]);
2849 linear_offset -= intel_crtc->dspaddr_offset;
2850 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2851 dspcntr |= DISPPLANE_ROTATE_180;
2852
2853 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2854 x += (intel_crtc->config->pipe_src_w - 1);
2855 y += (intel_crtc->config->pipe_src_h - 1);
2856
2857 /* Finding the last pixel of the last line of the display
2858 data and adding to linear_offset*/
2859 linear_offset +=
2860 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2861 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2862 }
2863 }
2864
2865 I915_WRITE(reg, dspcntr);
2866
2867 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2868 I915_WRITE(DSPSURF(plane),
2869 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2870 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2871 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2872 } else {
2873 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2874 I915_WRITE(DSPLINOFF(plane), linear_offset);
2875 }
2876 POSTING_READ(reg);
2877}
2878
2879u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2880 uint32_t pixel_format)
2881{
2882 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2883
2884 /*
2885 * The stride is either expressed as a multiple of 64 bytes
2886 * chunks for linear buffers or in number of tiles for tiled
2887 * buffers.
2888 */
2889 switch (fb_modifier) {
2890 case DRM_FORMAT_MOD_NONE:
2891 return 64;
2892 case I915_FORMAT_MOD_X_TILED:
2893 if (INTEL_INFO(dev)->gen == 2)
2894 return 128;
2895 return 512;
2896 case I915_FORMAT_MOD_Y_TILED:
2897 /* No need to check for old gens and Y tiling since this is
2898 * about the display engine and those will be blocked before
2899 * we get here.
2900 */
2901 return 128;
2902 case I915_FORMAT_MOD_Yf_TILED:
2903 if (bits_per_pixel == 8)
2904 return 64;
2905 else
2906 return 128;
2907 default:
2908 MISSING_CASE(fb_modifier);
2909 return 64;
2910 }
2911}
2912
2913unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2914 struct drm_i915_gem_object *obj)
2915{
2916 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2917
2918 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2919 view = &i915_ggtt_view_rotated;
2920
2921 return i915_gem_obj_ggtt_offset_view(obj, view);
2922}
2923
2924/*
2925 * This function detaches (aka. unbinds) unused scalers in hardware
2926 */
2927void skl_detach_scalers(struct intel_crtc *intel_crtc)
2928{
2929 struct drm_device *dev;
2930 struct drm_i915_private *dev_priv;
2931 struct intel_crtc_scaler_state *scaler_state;
2932 int i;
2933
2934 if (!intel_crtc || !intel_crtc->config)
2935 return;
2936
2937 dev = intel_crtc->base.dev;
2938 dev_priv = dev->dev_private;
2939 scaler_state = &intel_crtc->config->scaler_state;
2940
2941 /* loop through and disable scalers that aren't in use */
2942 for (i = 0; i < intel_crtc->num_scalers; i++) {
2943 if (!scaler_state->scalers[i].in_use) {
2944 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2945 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2947 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2948 intel_crtc->base.base.id, intel_crtc->pipe, i);
2949 }
2950 }
2951}
2952
2953u32 skl_plane_ctl_format(uint32_t pixel_format)
2954{
2955 u32 plane_ctl_format = 0;
2956 switch (pixel_format) {
2957 case DRM_FORMAT_RGB565:
2958 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
2959 break;
2960 case DRM_FORMAT_XBGR8888:
2961 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2962 break;
2963 case DRM_FORMAT_XRGB8888:
2964 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
2965 break;
2966 /*
2967 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2968 * to be already pre-multiplied. We need to add a knob (or a different
2969 * DRM_FORMAT) for user-space to configure that.
2970 */
2971 case DRM_FORMAT_ABGR8888:
2972 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974 break;
2975 case DRM_FORMAT_ARGB8888:
2976 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2977 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2978 break;
2979 case DRM_FORMAT_XRGB2101010:
2980 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
2981 break;
2982 case DRM_FORMAT_XBGR2101010:
2983 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2984 break;
2985 case DRM_FORMAT_YUYV:
2986 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2987 break;
2988 case DRM_FORMAT_YVYU:
2989 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2990 break;
2991 case DRM_FORMAT_UYVY:
2992 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2993 break;
2994 case DRM_FORMAT_VYUY:
2995 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2996 break;
2997 default:
2998 BUG();
2999 }
3000 return plane_ctl_format;
3001}
3002
3003u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3004{
3005 u32 plane_ctl_tiling = 0;
3006 switch (fb_modifier) {
3007 case DRM_FORMAT_MOD_NONE:
3008 break;
3009 case I915_FORMAT_MOD_X_TILED:
3010 plane_ctl_tiling = PLANE_CTL_TILED_X;
3011 break;
3012 case I915_FORMAT_MOD_Y_TILED:
3013 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3014 break;
3015 case I915_FORMAT_MOD_Yf_TILED:
3016 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3017 break;
3018 default:
3019 MISSING_CASE(fb_modifier);
3020 }
3021 return plane_ctl_tiling;
3022}
3023
3024u32 skl_plane_ctl_rotation(unsigned int rotation)
3025{
3026 u32 plane_ctl_rotation = 0;
3027 switch (rotation) {
3028 case BIT(DRM_ROTATE_0):
3029 break;
3030 case BIT(DRM_ROTATE_90):
3031 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3032 break;
3033 case BIT(DRM_ROTATE_180):
3034 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3035 break;
3036 case BIT(DRM_ROTATE_270):
3037 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3038 break;
3039 default:
3040 MISSING_CASE(rotation);
3041 }
3042
3043 return plane_ctl_rotation;
3044}
3045
3046static void skylake_update_primary_plane(struct drm_crtc *crtc,
3047 struct drm_framebuffer *fb,
3048 int x, int y)
3049{
3050 struct drm_device *dev = crtc->dev;
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3053 struct drm_plane *plane = crtc->primary;
3054 bool visible = to_intel_plane_state(plane->state)->visible;
3055 struct drm_i915_gem_object *obj;
3056 int pipe = intel_crtc->pipe;
3057 u32 plane_ctl, stride_div, stride;
3058 u32 tile_height, plane_offset, plane_size;
3059 unsigned int rotation;
3060 int x_offset, y_offset;
3061 unsigned long surf_addr;
3062 struct intel_crtc_state *crtc_state = intel_crtc->config;
3063 struct intel_plane_state *plane_state;
3064 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3065 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3066 int scaler_id = -1;
3067
3068 plane_state = to_intel_plane_state(plane->state);
3069
3070 if (!visible || !fb) {
3071 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3072 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3073 POSTING_READ(PLANE_CTL(pipe, 0));
3074 return;
3075 }
3076
3077 plane_ctl = PLANE_CTL_ENABLE |
3078 PLANE_CTL_PIPE_GAMMA_ENABLE |
3079 PLANE_CTL_PIPE_CSC_ENABLE;
3080
3081 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3082 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3083 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3084
3085 rotation = plane->state->rotation;
3086 plane_ctl |= skl_plane_ctl_rotation(rotation);
3087
3088 obj = intel_fb_obj(fb);
3089 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3090 fb->pixel_format);
3091 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3092
3093 /*
3094 * FIXME: intel_plane_state->src, dst aren't set when transitional
3095 * update_plane helpers are called from legacy paths.
3096 * Once full atomic crtc is available, below check can be avoided.
3097 */
3098 if (drm_rect_width(&plane_state->src)) {
3099 scaler_id = plane_state->scaler_id;
3100 src_x = plane_state->src.x1 >> 16;
3101 src_y = plane_state->src.y1 >> 16;
3102 src_w = drm_rect_width(&plane_state->src) >> 16;
3103 src_h = drm_rect_height(&plane_state->src) >> 16;
3104 dst_x = plane_state->dst.x1;
3105 dst_y = plane_state->dst.y1;
3106 dst_w = drm_rect_width(&plane_state->dst);
3107 dst_h = drm_rect_height(&plane_state->dst);
3108
3109 WARN_ON(x != src_x || y != src_y);
3110 } else {
3111 src_w = intel_crtc->config->pipe_src_w;
3112 src_h = intel_crtc->config->pipe_src_h;
3113 }
3114
3115 if (intel_rotation_90_or_270(rotation)) {
3116 /* stride = Surface height in tiles */
3117 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3118 fb->modifier[0]);
3119 stride = DIV_ROUND_UP(fb->height, tile_height);
3120 x_offset = stride * tile_height - y - src_h;
3121 y_offset = x;
3122 plane_size = (src_w - 1) << 16 | (src_h - 1);
3123 } else {
3124 stride = fb->pitches[0] / stride_div;
3125 x_offset = x;
3126 y_offset = y;
3127 plane_size = (src_h - 1) << 16 | (src_w - 1);
3128 }
3129 plane_offset = y_offset << 16 | x_offset;
3130
3131 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3132 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3133 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3134 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3135
3136 if (scaler_id >= 0) {
3137 uint32_t ps_ctrl = 0;
3138
3139 WARN_ON(!dst_w || !dst_h);
3140 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3141 crtc_state->scaler_state.scalers[scaler_id].mode;
3142 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3143 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3144 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3145 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3146 I915_WRITE(PLANE_POS(pipe, 0), 0);
3147 } else {
3148 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3149 }
3150
3151 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3152
3153 POSTING_READ(PLANE_SURF(pipe, 0));
3154}
3155
3156/* Assume fb object is pinned & idle & fenced and just update base pointers */
3157static int
3158intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3159 int x, int y, enum mode_set_atomic state)
3160{
3161 struct drm_device *dev = crtc->dev;
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163
3164 if (dev_priv->display.disable_fbc)
3165 dev_priv->display.disable_fbc(dev);
3166
3167 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3168
3169 return 0;
3170}
3171
3172static void intel_complete_page_flips(struct drm_device *dev)
3173{
3174 struct drm_crtc *crtc;
3175
3176 for_each_crtc(dev, crtc) {
3177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3178 enum plane plane = intel_crtc->plane;
3179
3180 intel_prepare_page_flip(dev, plane);
3181 intel_finish_page_flip_plane(dev, plane);
3182 }
3183}
3184
3185static void intel_update_primary_planes(struct drm_device *dev)
3186{
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct drm_crtc *crtc;
3189
3190 for_each_crtc(dev, crtc) {
3191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3192
3193 drm_modeset_lock(&crtc->mutex, NULL);
3194 /*
3195 * FIXME: Once we have proper support for primary planes (and
3196 * disabling them without disabling the entire crtc) allow again
3197 * a NULL crtc->primary->fb.
3198 */
3199 if (intel_crtc->active && crtc->primary->fb)
3200 dev_priv->display.update_primary_plane(crtc,
3201 crtc->primary->fb,
3202 crtc->x,
3203 crtc->y);
3204 drm_modeset_unlock(&crtc->mutex);
3205 }
3206}
3207
3208void intel_crtc_reset(struct intel_crtc *crtc)
3209{
3210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3211
3212 if (!crtc->active)
3213 return;
3214
3215 intel_crtc_disable_planes(&crtc->base);
3216 dev_priv->display.crtc_disable(&crtc->base);
3217 dev_priv->display.crtc_enable(&crtc->base);
3218 intel_crtc_enable_planes(&crtc->base);
3219}
3220
3221void intel_prepare_reset(struct drm_device *dev)
3222{
3223 struct drm_i915_private *dev_priv = to_i915(dev);
3224 struct intel_crtc *crtc;
3225
3226 /* no reset support for gen2 */
3227 if (IS_GEN2(dev))
3228 return;
3229
3230 /* reset doesn't touch the display */
3231 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3232 return;
3233
3234 drm_modeset_lock_all(dev);
3235
3236 /*
3237 * Disabling the crtcs gracefully seems nicer. Also the
3238 * g33 docs say we should at least disable all the planes.
3239 */
3240 for_each_intel_crtc(dev, crtc) {
3241 if (!crtc->active)
3242 continue;
3243
3244 intel_crtc_disable_planes(&crtc->base);
3245 dev_priv->display.crtc_disable(&crtc->base);
3246 }
3247}
3248
3249void intel_finish_reset(struct drm_device *dev)
3250{
3251 struct drm_i915_private *dev_priv = to_i915(dev);
3252
3253 /*
3254 * Flips in the rings will be nuked by the reset,
3255 * so complete all pending flips so that user space
3256 * will get its events and not get stuck.
3257 */
3258 intel_complete_page_flips(dev);
3259
3260 /* no reset support for gen2 */
3261 if (IS_GEN2(dev))
3262 return;
3263
3264 /* reset doesn't touch the display */
3265 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3266 /*
3267 * Flips in the rings have been nuked by the reset,
3268 * so update the base address of all primary
3269 * planes to the the last fb to make sure we're
3270 * showing the correct fb after a reset.
3271 */
3272 intel_update_primary_planes(dev);
3273 return;
3274 }
3275
3276 /*
3277 * The display has been reset as well,
3278 * so need a full re-initialization.
3279 */
3280 intel_runtime_pm_disable_interrupts(dev_priv);
3281 intel_runtime_pm_enable_interrupts(dev_priv);
3282
3283 intel_modeset_init_hw(dev);
3284
3285 spin_lock_irq(&dev_priv->irq_lock);
3286 if (dev_priv->display.hpd_irq_setup)
3287 dev_priv->display.hpd_irq_setup(dev);
3288 spin_unlock_irq(&dev_priv->irq_lock);
3289
3290 intel_modeset_setup_hw_state(dev, true);
3291
3292 intel_hpd_init(dev_priv);
3293
3294 drm_modeset_unlock_all(dev);
3295}
3296
3297static int
3298intel_finish_fb(struct drm_framebuffer *old_fb)
3299{
3300 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3301 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3302 bool was_interruptible = dev_priv->mm.interruptible;
3303 int ret;
3304
3305 /* Big Hammer, we also need to ensure that any pending
3306 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3307 * current scanout is retired before unpinning the old
3308 * framebuffer.
3309 *
3310 * This should only fail upon a hung GPU, in which case we
3311 * can safely continue.
3312 */
3313 dev_priv->mm.interruptible = false;
3314 ret = i915_gem_object_finish_gpu(obj);
3315 dev_priv->mm.interruptible = was_interruptible;
3316
3317 return ret;
3318}
3319
3320static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3321{
3322 struct drm_device *dev = crtc->dev;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325 bool pending;
3326
3327 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3328 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3329 return false;
3330
3331 spin_lock_irq(&dev->event_lock);
3332 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3333 spin_unlock_irq(&dev->event_lock);
3334
3335 return pending;
3336}
3337
3338static void intel_update_pipe_size(struct intel_crtc *crtc)
3339{
3340 struct drm_device *dev = crtc->base.dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 const struct drm_display_mode *adjusted_mode;
3343
3344 if (!i915.fastboot)
3345 return;
3346
3347 /*
3348 * Update pipe size and adjust fitter if needed: the reason for this is
3349 * that in compute_mode_changes we check the native mode (not the pfit
3350 * mode) to see if we can flip rather than do a full mode set. In the
3351 * fastboot case, we'll flip, but if we don't update the pipesrc and
3352 * pfit state, we'll end up with a big fb scanned out into the wrong
3353 * sized surface.
3354 *
3355 * To fix this properly, we need to hoist the checks up into
3356 * compute_mode_changes (or above), check the actual pfit state and
3357 * whether the platform allows pfit disable with pipe active, and only
3358 * then update the pipesrc and pfit state, even on the flip path.
3359 */
3360
3361 adjusted_mode = &crtc->config->base.adjusted_mode;
3362
3363 I915_WRITE(PIPESRC(crtc->pipe),
3364 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3365 (adjusted_mode->crtc_vdisplay - 1));
3366 if (!crtc->config->pch_pfit.enabled &&
3367 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3369 I915_WRITE(PF_CTL(crtc->pipe), 0);
3370 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3371 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3372 }
3373 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3374 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3375}
3376
3377static void intel_fdi_normal_train(struct drm_crtc *crtc)
3378{
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 u32 reg, temp;
3384
3385 /* enable normal train */
3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
3388 if (IS_IVYBRIDGE(dev)) {
3389 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3390 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3391 } else {
3392 temp &= ~FDI_LINK_TRAIN_NONE;
3393 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3394 }
3395 I915_WRITE(reg, temp);
3396
3397 reg = FDI_RX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 if (HAS_PCH_CPT(dev)) {
3400 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3401 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3402 } else {
3403 temp &= ~FDI_LINK_TRAIN_NONE;
3404 temp |= FDI_LINK_TRAIN_NONE;
3405 }
3406 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3407
3408 /* wait one idle pattern time */
3409 POSTING_READ(reg);
3410 udelay(1000);
3411
3412 /* IVB wants error correction enabled */
3413 if (IS_IVYBRIDGE(dev))
3414 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3415 FDI_FE_ERRC_ENABLE);
3416}
3417
3418/* The FDI link training functions for ILK/Ibexpeak. */
3419static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3420{
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424 int pipe = intel_crtc->pipe;
3425 u32 reg, temp, tries;
3426
3427 /* FDI needs bits from pipe first */
3428 assert_pipe_enabled(dev_priv, pipe);
3429
3430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3431 for train result */
3432 reg = FDI_RX_IMR(pipe);
3433 temp = I915_READ(reg);
3434 temp &= ~FDI_RX_SYMBOL_LOCK;
3435 temp &= ~FDI_RX_BIT_LOCK;
3436 I915_WRITE(reg, temp);
3437 I915_READ(reg);
3438 udelay(150);
3439
3440 /* enable CPU FDI TX and PCH FDI RX */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_1;
3447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3448
3449 reg = FDI_RX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_1;
3453 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3454
3455 POSTING_READ(reg);
3456 udelay(150);
3457
3458 /* Ironlake workaround, enable clock pointer after FDI enable*/
3459 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3461 FDI_RX_PHASE_SYNC_POINTER_EN);
3462
3463 reg = FDI_RX_IIR(pipe);
3464 for (tries = 0; tries < 5; tries++) {
3465 temp = I915_READ(reg);
3466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467
3468 if ((temp & FDI_RX_BIT_LOCK)) {
3469 DRM_DEBUG_KMS("FDI train 1 done.\n");
3470 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3471 break;
3472 }
3473 }
3474 if (tries == 5)
3475 DRM_ERROR("FDI train 1 fail!\n");
3476
3477 /* Train 2 */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_2;
3482 I915_WRITE(reg, temp);
3483
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 temp &= ~FDI_LINK_TRAIN_NONE;
3487 temp |= FDI_LINK_TRAIN_PATTERN_2;
3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
3491 udelay(150);
3492
3493 reg = FDI_RX_IIR(pipe);
3494 for (tries = 0; tries < 5; tries++) {
3495 temp = I915_READ(reg);
3496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497
3498 if (temp & FDI_RX_SYMBOL_LOCK) {
3499 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3500 DRM_DEBUG_KMS("FDI train 2 done.\n");
3501 break;
3502 }
3503 }
3504 if (tries == 5)
3505 DRM_ERROR("FDI train 2 fail!\n");
3506
3507 DRM_DEBUG_KMS("FDI train done\n");
3508
3509}
3510
3511static const int snb_b_fdi_train_param[] = {
3512 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3513 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3514 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3515 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3516};
3517
3518/* The FDI link training functions for SNB/Cougarpoint. */
3519static void gen6_fdi_link_train(struct drm_crtc *crtc)
3520{
3521 struct drm_device *dev = crtc->dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524 int pipe = intel_crtc->pipe;
3525 u32 reg, temp, i, retry;
3526
3527 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3528 for train result */
3529 reg = FDI_RX_IMR(pipe);
3530 temp = I915_READ(reg);
3531 temp &= ~FDI_RX_SYMBOL_LOCK;
3532 temp &= ~FDI_RX_BIT_LOCK;
3533 I915_WRITE(reg, temp);
3534
3535 POSTING_READ(reg);
3536 udelay(150);
3537
3538 /* enable CPU FDI TX and PCH FDI RX */
3539 reg = FDI_TX_CTL(pipe);
3540 temp = I915_READ(reg);
3541 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3542 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3543 temp &= ~FDI_LINK_TRAIN_NONE;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1;
3545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546 /* SNB-B */
3547 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3548 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3549
3550 I915_WRITE(FDI_RX_MISC(pipe),
3551 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3552
3553 reg = FDI_RX_CTL(pipe);
3554 temp = I915_READ(reg);
3555 if (HAS_PCH_CPT(dev)) {
3556 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3557 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558 } else {
3559 temp &= ~FDI_LINK_TRAIN_NONE;
3560 temp |= FDI_LINK_TRAIN_PATTERN_1;
3561 }
3562 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3563
3564 POSTING_READ(reg);
3565 udelay(150);
3566
3567 for (i = 0; i < 4; i++) {
3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3571 temp |= snb_b_fdi_train_param[i];
3572 I915_WRITE(reg, temp);
3573
3574 POSTING_READ(reg);
3575 udelay(500);
3576
3577 for (retry = 0; retry < 5; retry++) {
3578 reg = FDI_RX_IIR(pipe);
3579 temp = I915_READ(reg);
3580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3581 if (temp & FDI_RX_BIT_LOCK) {
3582 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3583 DRM_DEBUG_KMS("FDI train 1 done.\n");
3584 break;
3585 }
3586 udelay(50);
3587 }
3588 if (retry < 5)
3589 break;
3590 }
3591 if (i == 4)
3592 DRM_ERROR("FDI train 1 fail!\n");
3593
3594 /* Train 2 */
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 temp &= ~FDI_LINK_TRAIN_NONE;
3598 temp |= FDI_LINK_TRAIN_PATTERN_2;
3599 if (IS_GEN6(dev)) {
3600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3601 /* SNB-B */
3602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3603 }
3604 I915_WRITE(reg, temp);
3605
3606 reg = FDI_RX_CTL(pipe);
3607 temp = I915_READ(reg);
3608 if (HAS_PCH_CPT(dev)) {
3609 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3610 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3611 } else {
3612 temp &= ~FDI_LINK_TRAIN_NONE;
3613 temp |= FDI_LINK_TRAIN_PATTERN_2;
3614 }
3615 I915_WRITE(reg, temp);
3616
3617 POSTING_READ(reg);
3618 udelay(150);
3619
3620 for (i = 0; i < 4; i++) {
3621 reg = FDI_TX_CTL(pipe);
3622 temp = I915_READ(reg);
3623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3624 temp |= snb_b_fdi_train_param[i];
3625 I915_WRITE(reg, temp);
3626
3627 POSTING_READ(reg);
3628 udelay(500);
3629
3630 for (retry = 0; retry < 5; retry++) {
3631 reg = FDI_RX_IIR(pipe);
3632 temp = I915_READ(reg);
3633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3634 if (temp & FDI_RX_SYMBOL_LOCK) {
3635 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3636 DRM_DEBUG_KMS("FDI train 2 done.\n");
3637 break;
3638 }
3639 udelay(50);
3640 }
3641 if (retry < 5)
3642 break;
3643 }
3644 if (i == 4)
3645 DRM_ERROR("FDI train 2 fail!\n");
3646
3647 DRM_DEBUG_KMS("FDI train done.\n");
3648}
3649
3650/* Manual link training for Ivy Bridge A0 parts */
3651static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3652{
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 int pipe = intel_crtc->pipe;
3657 u32 reg, temp, i, j;
3658
3659 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3660 for train result */
3661 reg = FDI_RX_IMR(pipe);
3662 temp = I915_READ(reg);
3663 temp &= ~FDI_RX_SYMBOL_LOCK;
3664 temp &= ~FDI_RX_BIT_LOCK;
3665 I915_WRITE(reg, temp);
3666
3667 POSTING_READ(reg);
3668 udelay(150);
3669
3670 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3671 I915_READ(FDI_RX_IIR(pipe)));
3672
3673 /* Try each vswing and preemphasis setting twice before moving on */
3674 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3675 /* disable first in case we need to retry */
3676 reg = FDI_TX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3679 temp &= ~FDI_TX_ENABLE;
3680 I915_WRITE(reg, temp);
3681
3682 reg = FDI_RX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 temp &= ~FDI_LINK_TRAIN_AUTO;
3685 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3686 temp &= ~FDI_RX_ENABLE;
3687 I915_WRITE(reg, temp);
3688
3689 /* enable CPU FDI TX and PCH FDI RX */
3690 reg = FDI_TX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3693 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3694 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3696 temp |= snb_b_fdi_train_param[j/2];
3697 temp |= FDI_COMPOSITE_SYNC;
3698 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3699
3700 I915_WRITE(FDI_RX_MISC(pipe),
3701 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3702
3703 reg = FDI_RX_CTL(pipe);
3704 temp = I915_READ(reg);
3705 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3706 temp |= FDI_COMPOSITE_SYNC;
3707 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3708
3709 POSTING_READ(reg);
3710 udelay(1); /* should be 0.5us */
3711
3712 for (i = 0; i < 4; i++) {
3713 reg = FDI_RX_IIR(pipe);
3714 temp = I915_READ(reg);
3715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3716
3717 if (temp & FDI_RX_BIT_LOCK ||
3718 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3719 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3720 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3721 i);
3722 break;
3723 }
3724 udelay(1); /* should be 0.5us */
3725 }
3726 if (i == 4) {
3727 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3728 continue;
3729 }
3730
3731 /* Train 2 */
3732 reg = FDI_TX_CTL(pipe);
3733 temp = I915_READ(reg);
3734 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3735 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3736 I915_WRITE(reg, temp);
3737
3738 reg = FDI_RX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3741 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3742 I915_WRITE(reg, temp);
3743
3744 POSTING_READ(reg);
3745 udelay(2); /* should be 1.5us */
3746
3747 for (i = 0; i < 4; i++) {
3748 reg = FDI_RX_IIR(pipe);
3749 temp = I915_READ(reg);
3750 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3751
3752 if (temp & FDI_RX_SYMBOL_LOCK ||
3753 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3754 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3756 i);
3757 goto train_done;
3758 }
3759 udelay(2); /* should be 1.5us */
3760 }
3761 if (i == 4)
3762 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3763 }
3764
3765train_done:
3766 DRM_DEBUG_KMS("FDI train done.\n");
3767}
3768
3769static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3770{
3771 struct drm_device *dev = intel_crtc->base.dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773 int pipe = intel_crtc->pipe;
3774 u32 reg, temp;
3775
3776
3777 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3778 reg = FDI_RX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3781 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3782 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3783 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3784
3785 POSTING_READ(reg);
3786 udelay(200);
3787
3788 /* Switch from Rawclk to PCDclk */
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp | FDI_PCDCLK);
3791
3792 POSTING_READ(reg);
3793 udelay(200);
3794
3795 /* Enable CPU FDI TX PLL, always on for Ironlake */
3796 reg = FDI_TX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3799 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3800
3801 POSTING_READ(reg);
3802 udelay(100);
3803 }
3804}
3805
3806static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3807{
3808 struct drm_device *dev = intel_crtc->base.dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 int pipe = intel_crtc->pipe;
3811 u32 reg, temp;
3812
3813 /* Switch from PCDclk to Rawclk */
3814 reg = FDI_RX_CTL(pipe);
3815 temp = I915_READ(reg);
3816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3817
3818 /* Disable CPU FDI TX PLL */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3822
3823 POSTING_READ(reg);
3824 udelay(100);
3825
3826 reg = FDI_RX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3829
3830 /* Wait for the clocks to turn off. */
3831 POSTING_READ(reg);
3832 udelay(100);
3833}
3834
3835static void ironlake_fdi_disable(struct drm_crtc *crtc)
3836{
3837 struct drm_device *dev = crtc->dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3840 int pipe = intel_crtc->pipe;
3841 u32 reg, temp;
3842
3843 /* disable CPU FDI tx and PCH FDI rx */
3844 reg = FDI_TX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3847 POSTING_READ(reg);
3848
3849 reg = FDI_RX_CTL(pipe);
3850 temp = I915_READ(reg);
3851 temp &= ~(0x7 << 16);
3852 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3853 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3854
3855 POSTING_READ(reg);
3856 udelay(100);
3857
3858 /* Ironlake workaround, disable clock pointer after downing FDI */
3859 if (HAS_PCH_IBX(dev))
3860 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3861
3862 /* still set train pattern 1 */
3863 reg = FDI_TX_CTL(pipe);
3864 temp = I915_READ(reg);
3865 temp &= ~FDI_LINK_TRAIN_NONE;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1;
3867 I915_WRITE(reg, temp);
3868
3869 reg = FDI_RX_CTL(pipe);
3870 temp = I915_READ(reg);
3871 if (HAS_PCH_CPT(dev)) {
3872 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3873 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3874 } else {
3875 temp &= ~FDI_LINK_TRAIN_NONE;
3876 temp |= FDI_LINK_TRAIN_PATTERN_1;
3877 }
3878 /* BPC in FDI rx is consistent with that in PIPECONF */
3879 temp &= ~(0x07 << 16);
3880 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3881 I915_WRITE(reg, temp);
3882
3883 POSTING_READ(reg);
3884 udelay(100);
3885}
3886
3887bool intel_has_pending_fb_unpin(struct drm_device *dev)
3888{
3889 struct intel_crtc *crtc;
3890
3891 /* Note that we don't need to be called with mode_config.lock here
3892 * as our list of CRTC objects is static for the lifetime of the
3893 * device and so cannot disappear as we iterate. Similarly, we can
3894 * happily treat the predicates as racy, atomic checks as userspace
3895 * cannot claim and pin a new fb without at least acquring the
3896 * struct_mutex and so serialising with us.
3897 */
3898 for_each_intel_crtc(dev, crtc) {
3899 if (atomic_read(&crtc->unpin_work_count) == 0)
3900 continue;
3901
3902 if (crtc->unpin_work)
3903 intel_wait_for_vblank(dev, crtc->pipe);
3904
3905 return true;
3906 }
3907
3908 return false;
3909}
3910
3911static void page_flip_completed(struct intel_crtc *intel_crtc)
3912{
3913 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3914 struct intel_unpin_work *work = intel_crtc->unpin_work;
3915
3916 /* ensure that the unpin work is consistent wrt ->pending. */
3917 smp_rmb();
3918 intel_crtc->unpin_work = NULL;
3919
3920 if (work->event)
3921 drm_send_vblank_event(intel_crtc->base.dev,
3922 intel_crtc->pipe,
3923 work->event);
3924
3925 drm_crtc_vblank_put(&intel_crtc->base);
3926
3927 wake_up_all(&dev_priv->pending_flip_queue);
3928 queue_work(dev_priv->wq, &work->work);
3929
3930 trace_i915_flip_complete(intel_crtc->plane,
3931 work->pending_flip_obj);
3932}
3933
3934void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938
3939 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3940 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3941 !intel_crtc_has_pending_flip(crtc),
3942 60*HZ) == 0)) {
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944
3945 spin_lock_irq(&dev->event_lock);
3946 if (intel_crtc->unpin_work) {
3947 WARN_ONCE(1, "Removing stuck page flip\n");
3948 page_flip_completed(intel_crtc);
3949 }
3950 spin_unlock_irq(&dev->event_lock);
3951 }
3952
3953 if (crtc->primary->fb) {
3954 mutex_lock(&dev->struct_mutex);
3955 intel_finish_fb(crtc->primary->fb);
3956 mutex_unlock(&dev->struct_mutex);
3957 }
3958}
3959
3960/* Program iCLKIP clock to the desired frequency */
3961static void lpt_program_iclkip(struct drm_crtc *crtc)
3962{
3963 struct drm_device *dev = crtc->dev;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
3965 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3966 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3967 u32 temp;
3968
3969 mutex_lock(&dev_priv->dpio_lock);
3970
3971 /* It is necessary to ungate the pixclk gate prior to programming
3972 * the divisors, and gate it back when it is done.
3973 */
3974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3975
3976 /* Disable SSCCTL */
3977 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3978 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3979 SBI_SSCCTL_DISABLE,
3980 SBI_ICLK);
3981
3982 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3983 if (clock == 20000) {
3984 auxdiv = 1;
3985 divsel = 0x41;
3986 phaseinc = 0x20;
3987 } else {
3988 /* The iCLK virtual clock root frequency is in MHz,
3989 * but the adjusted_mode->crtc_clock in in KHz. To get the
3990 * divisors, it is necessary to divide one by another, so we
3991 * convert the virtual clock precision to KHz here for higher
3992 * precision.
3993 */
3994 u32 iclk_virtual_root_freq = 172800 * 1000;
3995 u32 iclk_pi_range = 64;
3996 u32 desired_divisor, msb_divisor_value, pi_value;
3997
3998 desired_divisor = (iclk_virtual_root_freq / clock);
3999 msb_divisor_value = desired_divisor / iclk_pi_range;
4000 pi_value = desired_divisor % iclk_pi_range;
4001
4002 auxdiv = 0;
4003 divsel = msb_divisor_value - 2;
4004 phaseinc = pi_value;
4005 }
4006
4007 /* This should not happen with any sane values */
4008 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4009 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4010 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4011 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4012
4013 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4014 clock,
4015 auxdiv,
4016 divsel,
4017 phasedir,
4018 phaseinc);
4019
4020 /* Program SSCDIVINTPHASE6 */
4021 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4022 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4023 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4024 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4025 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4026 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4027 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4028 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4029
4030 /* Program SSCAUXDIV */
4031 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4032 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4034 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4035
4036 /* Enable modulator and associated divider */
4037 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4038 temp &= ~SBI_SSCCTL_DISABLE;
4039 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4040
4041 /* Wait for initialization time */
4042 udelay(24);
4043
4044 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4045
4046 mutex_unlock(&dev_priv->dpio_lock);
4047}
4048
4049static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4050 enum pipe pch_transcoder)
4051{
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4055
4056 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4057 I915_READ(HTOTAL(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4059 I915_READ(HBLANK(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4061 I915_READ(HSYNC(cpu_transcoder)));
4062
4063 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4064 I915_READ(VTOTAL(cpu_transcoder)));
4065 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4066 I915_READ(VBLANK(cpu_transcoder)));
4067 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4068 I915_READ(VSYNC(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4070 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4071}
4072
4073static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 uint32_t temp;
4077
4078 temp = I915_READ(SOUTH_CHICKEN1);
4079 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4080 return;
4081
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4084
4085 temp &= ~FDI_BC_BIFURCATION_SELECT;
4086 if (enable)
4087 temp |= FDI_BC_BIFURCATION_SELECT;
4088
4089 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4090 I915_WRITE(SOUTH_CHICKEN1, temp);
4091 POSTING_READ(SOUTH_CHICKEN1);
4092}
4093
4094static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4095{
4096 struct drm_device *dev = intel_crtc->base.dev;
4097
4098 switch (intel_crtc->pipe) {
4099 case PIPE_A:
4100 break;
4101 case PIPE_B:
4102 if (intel_crtc->config->fdi_lanes > 2)
4103 cpt_set_fdi_bc_bifurcation(dev, false);
4104 else
4105 cpt_set_fdi_bc_bifurcation(dev, true);
4106
4107 break;
4108 case PIPE_C:
4109 cpt_set_fdi_bc_bifurcation(dev, true);
4110
4111 break;
4112 default:
4113 BUG();
4114 }
4115}
4116
4117/*
4118 * Enable PCH resources required for PCH ports:
4119 * - PCH PLLs
4120 * - FDI training & RX/TX
4121 * - update transcoder timings
4122 * - DP transcoding bits
4123 * - transcoder
4124 */
4125static void ironlake_pch_enable(struct drm_crtc *crtc)
4126{
4127 struct drm_device *dev = crtc->dev;
4128 struct drm_i915_private *dev_priv = dev->dev_private;
4129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130 int pipe = intel_crtc->pipe;
4131 u32 reg, temp;
4132
4133 assert_pch_transcoder_disabled(dev_priv, pipe);
4134
4135 if (IS_IVYBRIDGE(dev))
4136 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4137
4138 /* Write the TU size bits before fdi link training, so that error
4139 * detection works. */
4140 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4141 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4142
4143 /* For PCH output, training FDI link */
4144 dev_priv->display.fdi_link_train(crtc);
4145
4146 /* We need to program the right clock selection before writing the pixel
4147 * mutliplier into the DPLL. */
4148 if (HAS_PCH_CPT(dev)) {
4149 u32 sel;
4150
4151 temp = I915_READ(PCH_DPLL_SEL);
4152 temp |= TRANS_DPLL_ENABLE(pipe);
4153 sel = TRANS_DPLLB_SEL(pipe);
4154 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4155 temp |= sel;
4156 else
4157 temp &= ~sel;
4158 I915_WRITE(PCH_DPLL_SEL, temp);
4159 }
4160
4161 /* XXX: pch pll's can be enabled any time before we enable the PCH
4162 * transcoder, and we actually should do this to not upset any PCH
4163 * transcoder that already use the clock when we share it.
4164 *
4165 * Note that enable_shared_dpll tries to do the right thing, but
4166 * get_shared_dpll unconditionally resets the pll - we need that to have
4167 * the right LVDS enable sequence. */
4168 intel_enable_shared_dpll(intel_crtc);
4169
4170 /* set transcoder timing, panel must allow it */
4171 assert_panel_unlocked(dev_priv, pipe);
4172 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4173
4174 intel_fdi_normal_train(crtc);
4175
4176 /* For PCH DP, enable TRANS_DP_CTL */
4177 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4178 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4179 reg = TRANS_DP_CTL(pipe);
4180 temp = I915_READ(reg);
4181 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4182 TRANS_DP_SYNC_MASK |
4183 TRANS_DP_BPC_MASK);
4184 temp |= (TRANS_DP_OUTPUT_ENABLE |
4185 TRANS_DP_ENH_FRAMING);
4186 temp |= bpc << 9; /* same format but at 11:9 */
4187
4188 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4189 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4190 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4191 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4192
4193 switch (intel_trans_dp_port_sel(crtc)) {
4194 case PCH_DP_B:
4195 temp |= TRANS_DP_PORT_SEL_B;
4196 break;
4197 case PCH_DP_C:
4198 temp |= TRANS_DP_PORT_SEL_C;
4199 break;
4200 case PCH_DP_D:
4201 temp |= TRANS_DP_PORT_SEL_D;
4202 break;
4203 default:
4204 BUG();
4205 }
4206
4207 I915_WRITE(reg, temp);
4208 }
4209
4210 ironlake_enable_pch_transcoder(dev_priv, pipe);
4211}
4212
4213static void lpt_pch_enable(struct drm_crtc *crtc)
4214{
4215 struct drm_device *dev = crtc->dev;
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4218 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4219
4220 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4221
4222 lpt_program_iclkip(crtc);
4223
4224 /* Set transcoder timing. */
4225 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4226
4227 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4228}
4229
4230void intel_put_shared_dpll(struct intel_crtc *crtc)
4231{
4232 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4233
4234 if (pll == NULL)
4235 return;
4236
4237 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4238 WARN(1, "bad %s crtc mask\n", pll->name);
4239 return;
4240 }
4241
4242 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4243 if (pll->config.crtc_mask == 0) {
4244 WARN_ON(pll->on);
4245 WARN_ON(pll->active);
4246 }
4247
4248 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4249}
4250
4251struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252 struct intel_crtc_state *crtc_state)
4253{
4254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4255 struct intel_shared_dpll *pll;
4256 enum intel_dpll_id i;
4257
4258 if (HAS_PCH_IBX(dev_priv->dev)) {
4259 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4260 i = (enum intel_dpll_id) crtc->pipe;
4261 pll = &dev_priv->shared_dplls[i];
4262
4263 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4264 crtc->base.base.id, pll->name);
4265
4266 WARN_ON(pll->new_config->crtc_mask);
4267
4268 goto found;
4269 }
4270
4271 if (IS_BROXTON(dev_priv->dev)) {
4272 /* PLL is attached to port in bxt */
4273 struct intel_encoder *encoder;
4274 struct intel_digital_port *intel_dig_port;
4275
4276 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4277 if (WARN_ON(!encoder))
4278 return NULL;
4279
4280 intel_dig_port = enc_to_dig_port(&encoder->base);
4281 /* 1:1 mapping between ports and PLLs */
4282 i = (enum intel_dpll_id)intel_dig_port->port;
4283 pll = &dev_priv->shared_dplls[i];
4284 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4285 crtc->base.base.id, pll->name);
4286 WARN_ON(pll->new_config->crtc_mask);
4287
4288 goto found;
4289 }
4290
4291 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4292 pll = &dev_priv->shared_dplls[i];
4293
4294 /* Only want to check enabled timings first */
4295 if (pll->new_config->crtc_mask == 0)
4296 continue;
4297
4298 if (memcmp(&crtc_state->dpll_hw_state,
4299 &pll->new_config->hw_state,
4300 sizeof(pll->new_config->hw_state)) == 0) {
4301 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4302 crtc->base.base.id, pll->name,
4303 pll->new_config->crtc_mask,
4304 pll->active);
4305 goto found;
4306 }
4307 }
4308
4309 /* Ok no matching timings, maybe there's a free one? */
4310 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4311 pll = &dev_priv->shared_dplls[i];
4312 if (pll->new_config->crtc_mask == 0) {
4313 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4314 crtc->base.base.id, pll->name);
4315 goto found;
4316 }
4317 }
4318
4319 return NULL;
4320
4321found:
4322 if (pll->new_config->crtc_mask == 0)
4323 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4324
4325 crtc_state->shared_dpll = i;
4326 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4327 pipe_name(crtc->pipe));
4328
4329 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4330
4331 return pll;
4332}
4333
4334/**
4335 * intel_shared_dpll_start_config - start a new PLL staged config
4336 * @dev_priv: DRM device
4337 * @clear_pipes: mask of pipes that will have their PLLs freed
4338 *
4339 * Starts a new PLL staged config, copying the current config but
4340 * releasing the references of pipes specified in clear_pipes.
4341 */
4342static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4343 unsigned clear_pipes)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4352 GFP_KERNEL);
4353 if (!pll->new_config)
4354 goto cleanup;
4355
4356 pll->new_config->crtc_mask &= ~clear_pipes;
4357 }
4358
4359 return 0;
4360
4361cleanup:
4362 while (--i >= 0) {
4363 pll = &dev_priv->shared_dplls[i];
4364 kfree(pll->new_config);
4365 pll->new_config = NULL;
4366 }
4367
4368 return -ENOMEM;
4369}
4370
4371static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4372{
4373 struct intel_shared_dpll *pll;
4374 enum intel_dpll_id i;
4375
4376 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4377 pll = &dev_priv->shared_dplls[i];
4378
4379 WARN_ON(pll->new_config == &pll->config);
4380
4381 pll->config = *pll->new_config;
4382 kfree(pll->new_config);
4383 pll->new_config = NULL;
4384 }
4385}
4386
4387static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4388{
4389 struct intel_shared_dpll *pll;
4390 enum intel_dpll_id i;
4391
4392 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4393 pll = &dev_priv->shared_dplls[i];
4394
4395 WARN_ON(pll->new_config == &pll->config);
4396
4397 kfree(pll->new_config);
4398 pll->new_config = NULL;
4399 }
4400}
4401
4402static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4403{
4404 struct drm_i915_private *dev_priv = dev->dev_private;
4405 int dslreg = PIPEDSL(pipe);
4406 u32 temp;
4407
4408 temp = I915_READ(dslreg);
4409 udelay(500);
4410 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4411 if (wait_for(I915_READ(dslreg) != temp, 5))
4412 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4413 }
4414}
4415
4416/**
4417 * skl_update_scaler_users - Stages update to crtc's scaler state
4418 * @intel_crtc: crtc
4419 * @crtc_state: crtc_state
4420 * @plane: plane (NULL indicates crtc is requesting update)
4421 * @plane_state: plane's state
4422 * @force_detach: request unconditional detachment of scaler
4423 *
4424 * This function updates scaler state for requested plane or crtc.
4425 * To request scaler usage update for a plane, caller shall pass plane pointer.
4426 * To request scaler usage update for crtc, caller shall pass plane pointer
4427 * as NULL.
4428 *
4429 * Return
4430 * 0 - scaler_usage updated successfully
4431 * error - requested scaling cannot be supported or other error condition
4432 */
4433int
4434skl_update_scaler_users(
4435 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4436 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4437 int force_detach)
4438{
4439 int need_scaling;
4440 int idx;
4441 int src_w, src_h, dst_w, dst_h;
4442 int *scaler_id;
4443 struct drm_framebuffer *fb;
4444 struct intel_crtc_scaler_state *scaler_state;
4445 unsigned int rotation;
4446
4447 if (!intel_crtc || !crtc_state)
4448 return 0;
4449
4450 scaler_state = &crtc_state->scaler_state;
4451
4452 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4453 fb = intel_plane ? plane_state->base.fb : NULL;
4454
4455 if (intel_plane) {
4456 src_w = drm_rect_width(&plane_state->src) >> 16;
4457 src_h = drm_rect_height(&plane_state->src) >> 16;
4458 dst_w = drm_rect_width(&plane_state->dst);
4459 dst_h = drm_rect_height(&plane_state->dst);
4460 scaler_id = &plane_state->scaler_id;
4461 rotation = plane_state->base.rotation;
4462 } else {
4463 struct drm_display_mode *adjusted_mode =
4464 &crtc_state->base.adjusted_mode;
4465 src_w = crtc_state->pipe_src_w;
4466 src_h = crtc_state->pipe_src_h;
4467 dst_w = adjusted_mode->hdisplay;
4468 dst_h = adjusted_mode->vdisplay;
4469 scaler_id = &scaler_state->scaler_id;
4470 rotation = DRM_ROTATE_0;
4471 }
4472
4473 need_scaling = intel_rotation_90_or_270(rotation) ?
4474 (src_h != dst_w || src_w != dst_h):
4475 (src_w != dst_w || src_h != dst_h);
4476
4477 /*
4478 * if plane is being disabled or scaler is no more required or force detach
4479 * - free scaler binded to this plane/crtc
4480 * - in order to do this, update crtc->scaler_usage
4481 *
4482 * Here scaler state in crtc_state is set free so that
4483 * scaler can be assigned to other user. Actual register
4484 * update to free the scaler is done in plane/panel-fit programming.
4485 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4486 */
4487 if (force_detach || !need_scaling || (intel_plane &&
4488 (!fb || !plane_state->visible))) {
4489 if (*scaler_id >= 0) {
4490 scaler_state->scaler_users &= ~(1 << idx);
4491 scaler_state->scalers[*scaler_id].in_use = 0;
4492
4493 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4494 "crtc_state = %p scaler_users = 0x%x\n",
4495 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4496 intel_plane ? intel_plane->base.base.id :
4497 intel_crtc->base.base.id, crtc_state,
4498 scaler_state->scaler_users);
4499 *scaler_id = -1;
4500 }
4501 return 0;
4502 }
4503
4504 /* range checks */
4505 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4506 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4507
4508 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4509 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4510 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4511 "size is out of scaler range\n",
4512 intel_plane ? "PLANE" : "CRTC",
4513 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4514 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4515 return -EINVAL;
4516 }
4517
4518 /* check colorkey */
4519 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4520 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4521 intel_plane->base.base.id);
4522 return -EINVAL;
4523 }
4524
4525 /* Check src format */
4526 if (intel_plane) {
4527 switch (fb->pixel_format) {
4528 case DRM_FORMAT_RGB565:
4529 case DRM_FORMAT_XBGR8888:
4530 case DRM_FORMAT_XRGB8888:
4531 case DRM_FORMAT_ABGR8888:
4532 case DRM_FORMAT_ARGB8888:
4533 case DRM_FORMAT_XRGB2101010:
4534 case DRM_FORMAT_ARGB2101010:
4535 case DRM_FORMAT_XBGR2101010:
4536 case DRM_FORMAT_ABGR2101010:
4537 case DRM_FORMAT_YUYV:
4538 case DRM_FORMAT_YVYU:
4539 case DRM_FORMAT_UYVY:
4540 case DRM_FORMAT_VYUY:
4541 break;
4542 default:
4543 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4544 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4545 return -EINVAL;
4546 }
4547 }
4548
4549 /* mark this plane as a scaler user in crtc_state */
4550 scaler_state->scaler_users |= (1 << idx);
4551 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4552 "crtc_state = %p scaler_users = 0x%x\n",
4553 intel_plane ? "PLANE" : "CRTC",
4554 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4555 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4556 return 0;
4557}
4558
4559static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4560{
4561 struct drm_device *dev = crtc->base.dev;
4562 struct drm_i915_private *dev_priv = dev->dev_private;
4563 int pipe = crtc->pipe;
4564 struct intel_crtc_scaler_state *scaler_state =
4565 &crtc->config->scaler_state;
4566
4567 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4568
4569 /* To update pfit, first update scaler state */
4570 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4571 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4572 skl_detach_scalers(crtc);
4573 if (!enable)
4574 return;
4575
4576 if (crtc->config->pch_pfit.enabled) {
4577 int id;
4578
4579 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4580 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4581 return;
4582 }
4583
4584 id = scaler_state->scaler_id;
4585 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4586 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4587 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4588 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4589
4590 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4591 }
4592}
4593
4594static void ironlake_pfit_enable(struct intel_crtc *crtc)
4595{
4596 struct drm_device *dev = crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 int pipe = crtc->pipe;
4599
4600 if (crtc->config->pch_pfit.enabled) {
4601 /* Force use of hard-coded filter coefficients
4602 * as some pre-programmed values are broken,
4603 * e.g. x201.
4604 */
4605 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4606 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4607 PF_PIPE_SEL_IVB(pipe));
4608 else
4609 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4610 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4611 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4612 }
4613}
4614
4615static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4616{
4617 struct drm_device *dev = crtc->dev;
4618 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4619 struct drm_plane *plane;
4620 struct intel_plane *intel_plane;
4621
4622 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4623 intel_plane = to_intel_plane(plane);
4624 if (intel_plane->pipe == pipe)
4625 intel_plane_restore(&intel_plane->base);
4626 }
4627}
4628
4629void hsw_enable_ips(struct intel_crtc *crtc)
4630{
4631 struct drm_device *dev = crtc->base.dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633
4634 if (!crtc->config->ips_enabled)
4635 return;
4636
4637 /* We can only enable IPS after we enable a plane and wait for a vblank */
4638 intel_wait_for_vblank(dev, crtc->pipe);
4639
4640 assert_plane_enabled(dev_priv, crtc->plane);
4641 if (IS_BROADWELL(dev)) {
4642 mutex_lock(&dev_priv->rps.hw_lock);
4643 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4644 mutex_unlock(&dev_priv->rps.hw_lock);
4645 /* Quoting Art Runyan: "its not safe to expect any particular
4646 * value in IPS_CTL bit 31 after enabling IPS through the
4647 * mailbox." Moreover, the mailbox may return a bogus state,
4648 * so we need to just enable it and continue on.
4649 */
4650 } else {
4651 I915_WRITE(IPS_CTL, IPS_ENABLE);
4652 /* The bit only becomes 1 in the next vblank, so this wait here
4653 * is essentially intel_wait_for_vblank. If we don't have this
4654 * and don't wait for vblanks until the end of crtc_enable, then
4655 * the HW state readout code will complain that the expected
4656 * IPS_CTL value is not the one we read. */
4657 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4658 DRM_ERROR("Timed out waiting for IPS enable\n");
4659 }
4660}
4661
4662void hsw_disable_ips(struct intel_crtc *crtc)
4663{
4664 struct drm_device *dev = crtc->base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666
4667 if (!crtc->config->ips_enabled)
4668 return;
4669
4670 assert_plane_enabled(dev_priv, crtc->plane);
4671 if (IS_BROADWELL(dev)) {
4672 mutex_lock(&dev_priv->rps.hw_lock);
4673 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4674 mutex_unlock(&dev_priv->rps.hw_lock);
4675 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4676 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4677 DRM_ERROR("Timed out waiting for IPS disable\n");
4678 } else {
4679 I915_WRITE(IPS_CTL, 0);
4680 POSTING_READ(IPS_CTL);
4681 }
4682
4683 /* We need to wait for a vblank before we can disable the plane. */
4684 intel_wait_for_vblank(dev, crtc->pipe);
4685}
4686
4687/** Loads the palette/gamma unit for the CRTC with the prepared values */
4688static void intel_crtc_load_lut(struct drm_crtc *crtc)
4689{
4690 struct drm_device *dev = crtc->dev;
4691 struct drm_i915_private *dev_priv = dev->dev_private;
4692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4693 enum pipe pipe = intel_crtc->pipe;
4694 int palreg = PALETTE(pipe);
4695 int i;
4696 bool reenable_ips = false;
4697
4698 /* The clocks have to be on to load the palette. */
4699 if (!crtc->state->enable || !intel_crtc->active)
4700 return;
4701
4702 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4703 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4704 assert_dsi_pll_enabled(dev_priv);
4705 else
4706 assert_pll_enabled(dev_priv, pipe);
4707 }
4708
4709 /* use legacy palette for Ironlake */
4710 if (!HAS_GMCH_DISPLAY(dev))
4711 palreg = LGC_PALETTE(pipe);
4712
4713 /* Workaround : Do not read or write the pipe palette/gamma data while
4714 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4715 */
4716 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4717 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4718 GAMMA_MODE_MODE_SPLIT)) {
4719 hsw_disable_ips(intel_crtc);
4720 reenable_ips = true;
4721 }
4722
4723 for (i = 0; i < 256; i++) {
4724 I915_WRITE(palreg + 4 * i,
4725 (intel_crtc->lut_r[i] << 16) |
4726 (intel_crtc->lut_g[i] << 8) |
4727 intel_crtc->lut_b[i]);
4728 }
4729
4730 if (reenable_ips)
4731 hsw_enable_ips(intel_crtc);
4732}
4733
4734static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4735{
4736 if (intel_crtc->overlay) {
4737 struct drm_device *dev = intel_crtc->base.dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739
4740 mutex_lock(&dev->struct_mutex);
4741 dev_priv->mm.interruptible = false;
4742 (void) intel_overlay_switch_off(intel_crtc->overlay);
4743 dev_priv->mm.interruptible = true;
4744 mutex_unlock(&dev->struct_mutex);
4745 }
4746
4747 /* Let userspace switch the overlay on again. In most cases userspace
4748 * has to recompute where to put it anyway.
4749 */
4750}
4751
4752/**
4753 * intel_post_enable_primary - Perform operations after enabling primary plane
4754 * @crtc: the CRTC whose primary plane was just enabled
4755 *
4756 * Performs potentially sleeping operations that must be done after the primary
4757 * plane is enabled, such as updating FBC and IPS. Note that this may be
4758 * called due to an explicit primary plane update, or due to an implicit
4759 * re-enable that is caused when a sprite plane is updated to no longer
4760 * completely hide the primary plane.
4761 */
4762static void
4763intel_post_enable_primary(struct drm_crtc *crtc)
4764{
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
4769
4770 /*
4771 * BDW signals flip done immediately if the plane
4772 * is disabled, even if the plane enable is already
4773 * armed to occur at the next vblank :(
4774 */
4775 if (IS_BROADWELL(dev))
4776 intel_wait_for_vblank(dev, pipe);
4777
4778 /*
4779 * FIXME IPS should be fine as long as one plane is
4780 * enabled, but in practice it seems to have problems
4781 * when going from primary only to sprite only and vice
4782 * versa.
4783 */
4784 hsw_enable_ips(intel_crtc);
4785
4786 mutex_lock(&dev->struct_mutex);
4787 intel_fbc_update(dev);
4788 mutex_unlock(&dev->struct_mutex);
4789
4790 /*
4791 * Gen2 reports pipe underruns whenever all planes are disabled.
4792 * So don't enable underrun reporting before at least some planes
4793 * are enabled.
4794 * FIXME: Need to fix the logic to work when we turn off all planes
4795 * but leave the pipe running.
4796 */
4797 if (IS_GEN2(dev))
4798 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4799
4800 /* Underruns don't raise interrupts, so check manually. */
4801 if (HAS_GMCH_DISPLAY(dev))
4802 i9xx_check_fifo_underruns(dev_priv);
4803}
4804
4805/**
4806 * intel_pre_disable_primary - Perform operations before disabling primary plane
4807 * @crtc: the CRTC whose primary plane is to be disabled
4808 *
4809 * Performs potentially sleeping operations that must be done before the
4810 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4811 * be called due to an explicit primary plane update, or due to an implicit
4812 * disable that is caused when a sprite plane completely hides the primary
4813 * plane.
4814 */
4815static void
4816intel_pre_disable_primary(struct drm_crtc *crtc)
4817{
4818 struct drm_device *dev = crtc->dev;
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4821 int pipe = intel_crtc->pipe;
4822
4823 /*
4824 * Gen2 reports pipe underruns whenever all planes are disabled.
4825 * So diasble underrun reporting before all the planes get disabled.
4826 * FIXME: Need to fix the logic to work when we turn off all planes
4827 * but leave the pipe running.
4828 */
4829 if (IS_GEN2(dev))
4830 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4831
4832 /*
4833 * Vblank time updates from the shadow to live plane control register
4834 * are blocked if the memory self-refresh mode is active at that
4835 * moment. So to make sure the plane gets truly disabled, disable
4836 * first the self-refresh mode. The self-refresh enable bit in turn
4837 * will be checked/applied by the HW only at the next frame start
4838 * event which is after the vblank start event, so we need to have a
4839 * wait-for-vblank between disabling the plane and the pipe.
4840 */
4841 if (HAS_GMCH_DISPLAY(dev))
4842 intel_set_memory_cxsr(dev_priv, false);
4843
4844 mutex_lock(&dev->struct_mutex);
4845 if (dev_priv->fbc.crtc == intel_crtc)
4846 intel_fbc_disable(dev);
4847 mutex_unlock(&dev->struct_mutex);
4848
4849 /*
4850 * FIXME IPS should be fine as long as one plane is
4851 * enabled, but in practice it seems to have problems
4852 * when going from primary only to sprite only and vice
4853 * versa.
4854 */
4855 hsw_disable_ips(intel_crtc);
4856}
4857
4858static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4859{
4860 intel_enable_primary_hw_plane(crtc->primary, crtc);
4861 intel_enable_sprite_planes(crtc);
4862 intel_crtc_update_cursor(crtc, true);
4863
4864 intel_post_enable_primary(crtc);
4865}
4866
4867static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4868{
4869 struct drm_device *dev = crtc->dev;
4870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4871 struct intel_plane *intel_plane;
4872 int pipe = intel_crtc->pipe;
4873
4874 intel_crtc_wait_for_pending_flips(crtc);
4875
4876 intel_pre_disable_primary(crtc);
4877
4878 intel_crtc_dpms_overlay_disable(intel_crtc);
4879 for_each_intel_plane(dev, intel_plane) {
4880 if (intel_plane->pipe == pipe) {
4881 struct drm_crtc *from = intel_plane->base.crtc;
4882
4883 intel_plane->disable_plane(&intel_plane->base,
4884 from ?: crtc, true);
4885 }
4886 }
4887
4888 /*
4889 * FIXME: Once we grow proper nuclear flip support out of this we need
4890 * to compute the mask of flip planes precisely. For the time being
4891 * consider this a flip to a NULL plane.
4892 */
4893 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4894}
4895
4896static void ironlake_crtc_enable(struct drm_crtc *crtc)
4897{
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901 struct intel_encoder *encoder;
4902 int pipe = intel_crtc->pipe;
4903
4904 WARN_ON(!crtc->state->enable);
4905
4906 if (intel_crtc->active)
4907 return;
4908
4909 if (intel_crtc->config->has_pch_encoder)
4910 intel_prepare_shared_dpll(intel_crtc);
4911
4912 if (intel_crtc->config->has_dp_encoder)
4913 intel_dp_set_m_n(intel_crtc, M1_N1);
4914
4915 intel_set_pipe_timings(intel_crtc);
4916
4917 if (intel_crtc->config->has_pch_encoder) {
4918 intel_cpu_transcoder_set_m_n(intel_crtc,
4919 &intel_crtc->config->fdi_m_n, NULL);
4920 }
4921
4922 ironlake_set_pipeconf(crtc);
4923
4924 intel_crtc->active = true;
4925
4926 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4927 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4928
4929 for_each_encoder_on_crtc(dev, crtc, encoder)
4930 if (encoder->pre_enable)
4931 encoder->pre_enable(encoder);
4932
4933 if (intel_crtc->config->has_pch_encoder) {
4934 /* Note: FDI PLL enabling _must_ be done before we enable the
4935 * cpu pipes, hence this is separate from all the other fdi/pch
4936 * enabling. */
4937 ironlake_fdi_pll_enable(intel_crtc);
4938 } else {
4939 assert_fdi_tx_disabled(dev_priv, pipe);
4940 assert_fdi_rx_disabled(dev_priv, pipe);
4941 }
4942
4943 ironlake_pfit_enable(intel_crtc);
4944
4945 /*
4946 * On ILK+ LUT must be loaded before the pipe is running but with
4947 * clocks enabled
4948 */
4949 intel_crtc_load_lut(crtc);
4950
4951 intel_update_watermarks(crtc);
4952 intel_enable_pipe(intel_crtc);
4953
4954 if (intel_crtc->config->has_pch_encoder)
4955 ironlake_pch_enable(crtc);
4956
4957 assert_vblank_disabled(crtc);
4958 drm_crtc_vblank_on(crtc);
4959
4960 for_each_encoder_on_crtc(dev, crtc, encoder)
4961 encoder->enable(encoder);
4962
4963 if (HAS_PCH_CPT(dev))
4964 cpt_verify_modeset(dev, intel_crtc->pipe);
4965}
4966
4967/* IPS only exists on ULT machines and is tied to pipe A. */
4968static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4969{
4970 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4971}
4972
4973/*
4974 * This implements the workaround described in the "notes" section of the mode
4975 * set sequence documentation. When going from no pipes or single pipe to
4976 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4977 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4978 */
4979static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4980{
4981 struct drm_device *dev = crtc->base.dev;
4982 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4983
4984 /* We want to get the other_active_crtc only if there's only 1 other
4985 * active crtc. */
4986 for_each_intel_crtc(dev, crtc_it) {
4987 if (!crtc_it->active || crtc_it == crtc)
4988 continue;
4989
4990 if (other_active_crtc)
4991 return;
4992
4993 other_active_crtc = crtc_it;
4994 }
4995 if (!other_active_crtc)
4996 return;
4997
4998 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4999 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5000}
5001
5002static void haswell_crtc_enable(struct drm_crtc *crtc)
5003{
5004 struct drm_device *dev = crtc->dev;
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007 struct intel_encoder *encoder;
5008 int pipe = intel_crtc->pipe;
5009
5010 WARN_ON(!crtc->state->enable);
5011
5012 if (intel_crtc->active)
5013 return;
5014
5015 if (intel_crtc_to_shared_dpll(intel_crtc))
5016 intel_enable_shared_dpll(intel_crtc);
5017
5018 if (intel_crtc->config->has_dp_encoder)
5019 intel_dp_set_m_n(intel_crtc, M1_N1);
5020
5021 intel_set_pipe_timings(intel_crtc);
5022
5023 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5024 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5025 intel_crtc->config->pixel_multiplier - 1);
5026 }
5027
5028 if (intel_crtc->config->has_pch_encoder) {
5029 intel_cpu_transcoder_set_m_n(intel_crtc,
5030 &intel_crtc->config->fdi_m_n, NULL);
5031 }
5032
5033 haswell_set_pipeconf(crtc);
5034
5035 intel_set_pipe_csc(crtc);
5036
5037 intel_crtc->active = true;
5038
5039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5040 for_each_encoder_on_crtc(dev, crtc, encoder)
5041 if (encoder->pre_enable)
5042 encoder->pre_enable(encoder);
5043
5044 if (intel_crtc->config->has_pch_encoder) {
5045 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5046 true);
5047 dev_priv->display.fdi_link_train(crtc);
5048 }
5049
5050 intel_ddi_enable_pipe_clock(intel_crtc);
5051
5052 if (INTEL_INFO(dev)->gen == 9)
5053 skylake_pfit_update(intel_crtc, 1);
5054 else if (INTEL_INFO(dev)->gen < 9)
5055 ironlake_pfit_enable(intel_crtc);
5056 else
5057 MISSING_CASE(INTEL_INFO(dev)->gen);
5058
5059 /*
5060 * On ILK+ LUT must be loaded before the pipe is running but with
5061 * clocks enabled
5062 */
5063 intel_crtc_load_lut(crtc);
5064
5065 intel_ddi_set_pipe_settings(crtc);
5066 intel_ddi_enable_transcoder_func(crtc);
5067
5068 intel_update_watermarks(crtc);
5069 intel_enable_pipe(intel_crtc);
5070
5071 if (intel_crtc->config->has_pch_encoder)
5072 lpt_pch_enable(crtc);
5073
5074 if (intel_crtc->config->dp_encoder_is_mst)
5075 intel_ddi_set_vc_payload_alloc(crtc, true);
5076
5077 assert_vblank_disabled(crtc);
5078 drm_crtc_vblank_on(crtc);
5079
5080 for_each_encoder_on_crtc(dev, crtc, encoder) {
5081 encoder->enable(encoder);
5082 intel_opregion_notify_encoder(encoder, true);
5083 }
5084
5085 /* If we change the relative order between pipe/planes enabling, we need
5086 * to change the workaround. */
5087 haswell_mode_set_planes_workaround(intel_crtc);
5088}
5089
5090static void ironlake_pfit_disable(struct intel_crtc *crtc)
5091{
5092 struct drm_device *dev = crtc->base.dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 int pipe = crtc->pipe;
5095
5096 /* To avoid upsetting the power well on haswell only disable the pfit if
5097 * it's in use. The hw state code will make sure we get this right. */
5098 if (crtc->config->pch_pfit.enabled) {
5099 I915_WRITE(PF_CTL(pipe), 0);
5100 I915_WRITE(PF_WIN_POS(pipe), 0);
5101 I915_WRITE(PF_WIN_SZ(pipe), 0);
5102 }
5103}
5104
5105static void ironlake_crtc_disable(struct drm_crtc *crtc)
5106{
5107 struct drm_device *dev = crtc->dev;
5108 struct drm_i915_private *dev_priv = dev->dev_private;
5109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5110 struct intel_encoder *encoder;
5111 int pipe = intel_crtc->pipe;
5112 u32 reg, temp;
5113
5114 if (!intel_crtc->active)
5115 return;
5116
5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 encoder->disable(encoder);
5119
5120 drm_crtc_vblank_off(crtc);
5121 assert_vblank_disabled(crtc);
5122
5123 if (intel_crtc->config->has_pch_encoder)
5124 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5125
5126 intel_disable_pipe(intel_crtc);
5127
5128 ironlake_pfit_disable(intel_crtc);
5129
5130 for_each_encoder_on_crtc(dev, crtc, encoder)
5131 if (encoder->post_disable)
5132 encoder->post_disable(encoder);
5133
5134 if (intel_crtc->config->has_pch_encoder) {
5135 ironlake_fdi_disable(crtc);
5136
5137 ironlake_disable_pch_transcoder(dev_priv, pipe);
5138
5139 if (HAS_PCH_CPT(dev)) {
5140 /* disable TRANS_DP_CTL */
5141 reg = TRANS_DP_CTL(pipe);
5142 temp = I915_READ(reg);
5143 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5144 TRANS_DP_PORT_SEL_MASK);
5145 temp |= TRANS_DP_PORT_SEL_NONE;
5146 I915_WRITE(reg, temp);
5147
5148 /* disable DPLL_SEL */
5149 temp = I915_READ(PCH_DPLL_SEL);
5150 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5151 I915_WRITE(PCH_DPLL_SEL, temp);
5152 }
5153
5154 /* disable PCH DPLL */
5155 intel_disable_shared_dpll(intel_crtc);
5156
5157 ironlake_fdi_pll_disable(intel_crtc);
5158 }
5159
5160 intel_crtc->active = false;
5161 intel_update_watermarks(crtc);
5162
5163 mutex_lock(&dev->struct_mutex);
5164 intel_fbc_update(dev);
5165 mutex_unlock(&dev->struct_mutex);
5166}
5167
5168static void haswell_crtc_disable(struct drm_crtc *crtc)
5169{
5170 struct drm_device *dev = crtc->dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 struct intel_encoder *encoder;
5174 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5175
5176 if (!intel_crtc->active)
5177 return;
5178
5179 for_each_encoder_on_crtc(dev, crtc, encoder) {
5180 intel_opregion_notify_encoder(encoder, false);
5181 encoder->disable(encoder);
5182 }
5183
5184 drm_crtc_vblank_off(crtc);
5185 assert_vblank_disabled(crtc);
5186
5187 if (intel_crtc->config->has_pch_encoder)
5188 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5189 false);
5190 intel_disable_pipe(intel_crtc);
5191
5192 if (intel_crtc->config->dp_encoder_is_mst)
5193 intel_ddi_set_vc_payload_alloc(crtc, false);
5194
5195 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5196
5197 if (INTEL_INFO(dev)->gen == 9)
5198 skylake_pfit_update(intel_crtc, 0);
5199 else if (INTEL_INFO(dev)->gen < 9)
5200 ironlake_pfit_disable(intel_crtc);
5201 else
5202 MISSING_CASE(INTEL_INFO(dev)->gen);
5203
5204 intel_ddi_disable_pipe_clock(intel_crtc);
5205
5206 if (intel_crtc->config->has_pch_encoder) {
5207 lpt_disable_pch_transcoder(dev_priv);
5208 intel_ddi_fdi_disable(crtc);
5209 }
5210
5211 for_each_encoder_on_crtc(dev, crtc, encoder)
5212 if (encoder->post_disable)
5213 encoder->post_disable(encoder);
5214
5215 intel_crtc->active = false;
5216 intel_update_watermarks(crtc);
5217
5218 mutex_lock(&dev->struct_mutex);
5219 intel_fbc_update(dev);
5220 mutex_unlock(&dev->struct_mutex);
5221
5222 if (intel_crtc_to_shared_dpll(intel_crtc))
5223 intel_disable_shared_dpll(intel_crtc);
5224}
5225
5226static void ironlake_crtc_off(struct drm_crtc *crtc)
5227{
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229 intel_put_shared_dpll(intel_crtc);
5230}
5231
5232
5233static void i9xx_pfit_enable(struct intel_crtc *crtc)
5234{
5235 struct drm_device *dev = crtc->base.dev;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 struct intel_crtc_state *pipe_config = crtc->config;
5238
5239 if (!pipe_config->gmch_pfit.control)
5240 return;
5241
5242 /*
5243 * The panel fitter should only be adjusted whilst the pipe is disabled,
5244 * according to register description and PRM.
5245 */
5246 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5247 assert_pipe_disabled(dev_priv, crtc->pipe);
5248
5249 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5250 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5251
5252 /* Border color in case we don't scale up to the full screen. Black by
5253 * default, change to something else for debugging. */
5254 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5255}
5256
5257static enum intel_display_power_domain port_to_power_domain(enum port port)
5258{
5259 switch (port) {
5260 case PORT_A:
5261 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5262 case PORT_B:
5263 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5264 case PORT_C:
5265 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5266 case PORT_D:
5267 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5268 default:
5269 WARN_ON_ONCE(1);
5270 return POWER_DOMAIN_PORT_OTHER;
5271 }
5272}
5273
5274#define for_each_power_domain(domain, mask) \
5275 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5276 if ((1 << (domain)) & (mask))
5277
5278enum intel_display_power_domain
5279intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5280{
5281 struct drm_device *dev = intel_encoder->base.dev;
5282 struct intel_digital_port *intel_dig_port;
5283
5284 switch (intel_encoder->type) {
5285 case INTEL_OUTPUT_UNKNOWN:
5286 /* Only DDI platforms should ever use this output type */
5287 WARN_ON_ONCE(!HAS_DDI(dev));
5288 case INTEL_OUTPUT_DISPLAYPORT:
5289 case INTEL_OUTPUT_HDMI:
5290 case INTEL_OUTPUT_EDP:
5291 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5292 return port_to_power_domain(intel_dig_port->port);
5293 case INTEL_OUTPUT_DP_MST:
5294 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5295 return port_to_power_domain(intel_dig_port->port);
5296 case INTEL_OUTPUT_ANALOG:
5297 return POWER_DOMAIN_PORT_CRT;
5298 case INTEL_OUTPUT_DSI:
5299 return POWER_DOMAIN_PORT_DSI;
5300 default:
5301 return POWER_DOMAIN_PORT_OTHER;
5302 }
5303}
5304
5305static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5306{
5307 struct drm_device *dev = crtc->dev;
5308 struct intel_encoder *intel_encoder;
5309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310 enum pipe pipe = intel_crtc->pipe;
5311 unsigned long mask;
5312 enum transcoder transcoder;
5313
5314 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5315
5316 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5317 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5318 if (intel_crtc->config->pch_pfit.enabled ||
5319 intel_crtc->config->pch_pfit.force_thru)
5320 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5321
5322 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5323 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5324
5325 return mask;
5326}
5327
5328static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5329{
5330 struct drm_device *dev = state->dev;
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5333 struct intel_crtc *crtc;
5334
5335 /*
5336 * First get all needed power domains, then put all unneeded, to avoid
5337 * any unnecessary toggling of the power wells.
5338 */
5339 for_each_intel_crtc(dev, crtc) {
5340 enum intel_display_power_domain domain;
5341
5342 if (!crtc->base.state->enable)
5343 continue;
5344
5345 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5346
5347 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5348 intel_display_power_get(dev_priv, domain);
5349 }
5350
5351 if (dev_priv->display.modeset_global_resources)
5352 dev_priv->display.modeset_global_resources(state);
5353
5354 for_each_intel_crtc(dev, crtc) {
5355 enum intel_display_power_domain domain;
5356
5357 for_each_power_domain(domain, crtc->enabled_power_domains)
5358 intel_display_power_put(dev_priv, domain);
5359
5360 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5361 }
5362
5363 intel_display_set_init_power(dev_priv, false);
5364}
5365
5366void broxton_set_cdclk(struct drm_device *dev, int frequency)
5367{
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5369 uint32_t divider;
5370 uint32_t ratio;
5371 uint32_t current_freq;
5372 int ret;
5373
5374 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5375 switch (frequency) {
5376 case 144000:
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5378 ratio = BXT_DE_PLL_RATIO(60);
5379 break;
5380 case 288000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5382 ratio = BXT_DE_PLL_RATIO(60);
5383 break;
5384 case 384000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 576000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 624000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(65);
5395 break;
5396 case 19200:
5397 /*
5398 * Bypass frequency with DE PLL disabled. Init ratio, divider
5399 * to suppress GCC warning.
5400 */
5401 ratio = 0;
5402 divider = 0;
5403 break;
5404 default:
5405 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5406
5407 return;
5408 }
5409
5410 mutex_lock(&dev_priv->rps.hw_lock);
5411 /* Inform power controller of upcoming frequency change */
5412 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5413 0x80000000);
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5415
5416 if (ret) {
5417 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5418 ret, frequency);
5419 return;
5420 }
5421
5422 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5423 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5424 current_freq = current_freq * 500 + 1000;
5425
5426 /*
5427 * DE PLL has to be disabled when
5428 * - setting to 19.2MHz (bypass, PLL isn't used)
5429 * - before setting to 624MHz (PLL needs toggling)
5430 * - before setting to any frequency from 624MHz (PLL needs toggling)
5431 */
5432 if (frequency == 19200 || frequency == 624000 ||
5433 current_freq == 624000) {
5434 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5437 1))
5438 DRM_ERROR("timout waiting for DE PLL unlock\n");
5439 }
5440
5441 if (frequency != 19200) {
5442 uint32_t val;
5443
5444 val = I915_READ(BXT_DE_PLL_CTL);
5445 val &= ~BXT_DE_PLL_RATIO_MASK;
5446 val |= ratio;
5447 I915_WRITE(BXT_DE_PLL_CTL, val);
5448
5449 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5450 /* Timeout 200us */
5451 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5452 DRM_ERROR("timeout waiting for DE PLL lock\n");
5453
5454 val = I915_READ(CDCLK_CTL);
5455 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5456 val |= divider;
5457 /*
5458 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5459 * enable otherwise.
5460 */
5461 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5462 if (frequency >= 500000)
5463 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5464
5465 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5466 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5467 val |= (frequency - 1000) / 500;
5468 I915_WRITE(CDCLK_CTL, val);
5469 }
5470
5471 mutex_lock(&dev_priv->rps.hw_lock);
5472 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5473 DIV_ROUND_UP(frequency, 25000));
5474 mutex_unlock(&dev_priv->rps.hw_lock);
5475
5476 if (ret) {
5477 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5478 ret, frequency);
5479 return;
5480 }
5481
5482 dev_priv->cdclk_freq = frequency;
5483}
5484
5485void broxton_init_cdclk(struct drm_device *dev)
5486{
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 uint32_t val;
5489
5490 /*
5491 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5492 * or else the reset will hang because there is no PCH to respond.
5493 * Move the handshake programming to initialization sequence.
5494 * Previously was left up to BIOS.
5495 */
5496 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5497 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5498 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5499
5500 /* Enable PG1 for cdclk */
5501 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5502
5503 /* check if cd clock is enabled */
5504 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5505 DRM_DEBUG_KMS("Display already initialized\n");
5506 return;
5507 }
5508
5509 /*
5510 * FIXME:
5511 * - The initial CDCLK needs to be read from VBT.
5512 * Need to make this change after VBT has changes for BXT.
5513 * - check if setting the max (or any) cdclk freq is really necessary
5514 * here, it belongs to modeset time
5515 */
5516 broxton_set_cdclk(dev, 624000);
5517
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5519 POSTING_READ(DBUF_CTL);
5520
5521 udelay(10);
5522
5523 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5524 DRM_ERROR("DBuf power enable timeout!\n");
5525}
5526
5527void broxton_uninit_cdclk(struct drm_device *dev)
5528{
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5530
5531 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5532 POSTING_READ(DBUF_CTL);
5533
5534 udelay(10);
5535
5536 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5537 DRM_ERROR("DBuf power disable timeout!\n");
5538
5539 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5540 broxton_set_cdclk(dev, 19200);
5541
5542 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5543}
5544
5545/* returns HPLL frequency in kHz */
5546static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5547{
5548 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5549
5550 /* Obtain SKU information */
5551 mutex_lock(&dev_priv->dpio_lock);
5552 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5553 CCK_FUSE_HPLL_FREQ_MASK;
5554 mutex_unlock(&dev_priv->dpio_lock);
5555
5556 return vco_freq[hpll_freq] * 1000;
5557}
5558
5559static void vlv_update_cdclk(struct drm_device *dev)
5560{
5561 struct drm_i915_private *dev_priv = dev->dev_private;
5562
5563 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5564 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5565 dev_priv->cdclk_freq);
5566
5567 /*
5568 * Program the gmbus_freq based on the cdclk frequency.
5569 * BSpec erroneously claims we should aim for 4MHz, but
5570 * in fact 1MHz is the correct frequency.
5571 */
5572 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5573}
5574
5575/* Adjust CDclk dividers to allow high res or save power if possible */
5576static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5577{
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579 u32 val, cmd;
5580
5581 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5582 != dev_priv->cdclk_freq);
5583
5584 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5585 cmd = 2;
5586 else if (cdclk == 266667)
5587 cmd = 1;
5588 else
5589 cmd = 0;
5590
5591 mutex_lock(&dev_priv->rps.hw_lock);
5592 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5593 val &= ~DSPFREQGUAR_MASK;
5594 val |= (cmd << DSPFREQGUAR_SHIFT);
5595 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5596 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5597 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5598 50)) {
5599 DRM_ERROR("timed out waiting for CDclk change\n");
5600 }
5601 mutex_unlock(&dev_priv->rps.hw_lock);
5602
5603 if (cdclk == 400000) {
5604 u32 divider;
5605
5606 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5607
5608 mutex_lock(&dev_priv->dpio_lock);
5609 /* adjust cdclk divider */
5610 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5611 val &= ~DISPLAY_FREQUENCY_VALUES;
5612 val |= divider;
5613 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5614
5615 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5616 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5617 50))
5618 DRM_ERROR("timed out waiting for CDclk change\n");
5619 mutex_unlock(&dev_priv->dpio_lock);
5620 }
5621
5622 mutex_lock(&dev_priv->dpio_lock);
5623 /* adjust self-refresh exit latency value */
5624 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5625 val &= ~0x7f;
5626
5627 /*
5628 * For high bandwidth configs, we set a higher latency in the bunit
5629 * so that the core display fetch happens in time to avoid underruns.
5630 */
5631 if (cdclk == 400000)
5632 val |= 4500 / 250; /* 4.5 usec */
5633 else
5634 val |= 3000 / 250; /* 3.0 usec */
5635 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5636 mutex_unlock(&dev_priv->dpio_lock);
5637
5638 vlv_update_cdclk(dev);
5639}
5640
5641static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5642{
5643 struct drm_i915_private *dev_priv = dev->dev_private;
5644 u32 val, cmd;
5645
5646 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5647 != dev_priv->cdclk_freq);
5648
5649 switch (cdclk) {
5650 case 333333:
5651 case 320000:
5652 case 266667:
5653 case 200000:
5654 break;
5655 default:
5656 MISSING_CASE(cdclk);
5657 return;
5658 }
5659
5660 /*
5661 * Specs are full of misinformation, but testing on actual
5662 * hardware has shown that we just need to write the desired
5663 * CCK divider into the Punit register.
5664 */
5665 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5666
5667 mutex_lock(&dev_priv->rps.hw_lock);
5668 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5669 val &= ~DSPFREQGUAR_MASK_CHV;
5670 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5671 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5672 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5673 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5674 50)) {
5675 DRM_ERROR("timed out waiting for CDclk change\n");
5676 }
5677 mutex_unlock(&dev_priv->rps.hw_lock);
5678
5679 vlv_update_cdclk(dev);
5680}
5681
5682static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5683 int max_pixclk)
5684{
5685 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5686 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5687
5688 /*
5689 * Really only a few cases to deal with, as only 4 CDclks are supported:
5690 * 200MHz
5691 * 267MHz
5692 * 320/333MHz (depends on HPLL freq)
5693 * 400MHz (VLV only)
5694 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5695 * of the lower bin and adjust if needed.
5696 *
5697 * We seem to get an unstable or solid color picture at 200MHz.
5698 * Not sure what's wrong. For now use 200MHz only when all pipes
5699 * are off.
5700 */
5701 if (!IS_CHERRYVIEW(dev_priv) &&
5702 max_pixclk > freq_320*limit/100)
5703 return 400000;
5704 else if (max_pixclk > 266667*limit/100)
5705 return freq_320;
5706 else if (max_pixclk > 0)
5707 return 266667;
5708 else
5709 return 200000;
5710}
5711
5712static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5713 int max_pixclk)
5714{
5715 /*
5716 * FIXME:
5717 * - remove the guardband, it's not needed on BXT
5718 * - set 19.2MHz bypass frequency if there are no active pipes
5719 */
5720 if (max_pixclk > 576000*9/10)
5721 return 624000;
5722 else if (max_pixclk > 384000*9/10)
5723 return 576000;
5724 else if (max_pixclk > 288000*9/10)
5725 return 384000;
5726 else if (max_pixclk > 144000*9/10)
5727 return 288000;
5728 else
5729 return 144000;
5730}
5731
5732/* compute the max pixel clock for new configuration */
5733static int intel_mode_max_pixclk(struct drm_atomic_state *state)
5734{
5735 struct drm_device *dev = state->dev;
5736 struct intel_crtc *intel_crtc;
5737 struct intel_crtc_state *crtc_state;
5738 int max_pixclk = 0;
5739
5740 for_each_intel_crtc(dev, intel_crtc) {
5741 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5742 if (IS_ERR(crtc_state))
5743 return PTR_ERR(crtc_state);
5744
5745 if (!crtc_state->base.enable)
5746 continue;
5747
5748 max_pixclk = max(max_pixclk,
5749 crtc_state->base.adjusted_mode.crtc_clock);
5750 }
5751
5752 return max_pixclk;
5753}
5754
5755static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5756{
5757 struct drm_i915_private *dev_priv = to_i915(state->dev);
5758 struct drm_crtc *crtc;
5759 struct drm_crtc_state *crtc_state;
5760 int max_pixclk = intel_mode_max_pixclk(state);
5761 int cdclk, i;
5762
5763 if (max_pixclk < 0)
5764 return max_pixclk;
5765
5766 if (IS_VALLEYVIEW(dev_priv))
5767 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5768 else
5769 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5770
5771 if (cdclk == dev_priv->cdclk_freq)
5772 return 0;
5773
5774 /* add all active pipes to the state */
5775 for_each_crtc(state->dev, crtc) {
5776 if (!crtc->state->enable)
5777 continue;
5778
5779 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5780 if (IS_ERR(crtc_state))
5781 return PTR_ERR(crtc_state);
5782 }
5783
5784 /* disable/enable all currently active pipes while we change cdclk */
5785 for_each_crtc_in_state(state, crtc, crtc_state, i)
5786 if (crtc_state->enable)
5787 crtc_state->mode_changed = true;
5788
5789 return 0;
5790}
5791
5792static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5793{
5794 unsigned int credits, default_credits;
5795
5796 if (IS_CHERRYVIEW(dev_priv))
5797 default_credits = PFI_CREDIT(12);
5798 else
5799 default_credits = PFI_CREDIT(8);
5800
5801 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5802 /* CHV suggested value is 31 or 63 */
5803 if (IS_CHERRYVIEW(dev_priv))
5804 credits = PFI_CREDIT_31;
5805 else
5806 credits = PFI_CREDIT(15);
5807 } else {
5808 credits = default_credits;
5809 }
5810
5811 /*
5812 * WA - write default credits before re-programming
5813 * FIXME: should we also set the resend bit here?
5814 */
5815 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5816 default_credits);
5817
5818 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5819 credits | PFI_CREDIT_RESEND);
5820
5821 /*
5822 * FIXME is this guaranteed to clear
5823 * immediately or should we poll for it?
5824 */
5825 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5826}
5827
5828static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5829{
5830 struct drm_device *dev = state->dev;
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 int max_pixclk = intel_mode_max_pixclk(state);
5833 int req_cdclk;
5834
5835 /* The only reason this can fail is if we fail to add the crtc_state
5836 * to the atomic state. But that can't happen since the call to
5837 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5838 * can't have failed otherwise the mode set would be aborted) added all
5839 * the states already. */
5840 if (WARN_ON(max_pixclk < 0))
5841 return;
5842
5843 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5844
5845 if (req_cdclk != dev_priv->cdclk_freq) {
5846 /*
5847 * FIXME: We can end up here with all power domains off, yet
5848 * with a CDCLK frequency other than the minimum. To account
5849 * for this take the PIPE-A power domain, which covers the HW
5850 * blocks needed for the following programming. This can be
5851 * removed once it's guaranteed that we get here either with
5852 * the minimum CDCLK set, or the required power domains
5853 * enabled.
5854 */
5855 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5856
5857 if (IS_CHERRYVIEW(dev))
5858 cherryview_set_cdclk(dev, req_cdclk);
5859 else
5860 valleyview_set_cdclk(dev, req_cdclk);
5861
5862 vlv_program_pfi_credits(dev_priv);
5863
5864 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5865 }
5866}
5867
5868static void valleyview_crtc_enable(struct drm_crtc *crtc)
5869{
5870 struct drm_device *dev = crtc->dev;
5871 struct drm_i915_private *dev_priv = to_i915(dev);
5872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5873 struct intel_encoder *encoder;
5874 int pipe = intel_crtc->pipe;
5875 bool is_dsi;
5876
5877 WARN_ON(!crtc->state->enable);
5878
5879 if (intel_crtc->active)
5880 return;
5881
5882 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5883
5884 if (!is_dsi) {
5885 if (IS_CHERRYVIEW(dev))
5886 chv_prepare_pll(intel_crtc, intel_crtc->config);
5887 else
5888 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5889 }
5890
5891 if (intel_crtc->config->has_dp_encoder)
5892 intel_dp_set_m_n(intel_crtc, M1_N1);
5893
5894 intel_set_pipe_timings(intel_crtc);
5895
5896 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898
5899 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5900 I915_WRITE(CHV_CANVAS(pipe), 0);
5901 }
5902
5903 i9xx_set_pipeconf(intel_crtc);
5904
5905 intel_crtc->active = true;
5906
5907 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5908
5909 for_each_encoder_on_crtc(dev, crtc, encoder)
5910 if (encoder->pre_pll_enable)
5911 encoder->pre_pll_enable(encoder);
5912
5913 if (!is_dsi) {
5914 if (IS_CHERRYVIEW(dev))
5915 chv_enable_pll(intel_crtc, intel_crtc->config);
5916 else
5917 vlv_enable_pll(intel_crtc, intel_crtc->config);
5918 }
5919
5920 for_each_encoder_on_crtc(dev, crtc, encoder)
5921 if (encoder->pre_enable)
5922 encoder->pre_enable(encoder);
5923
5924 i9xx_pfit_enable(intel_crtc);
5925
5926 intel_crtc_load_lut(crtc);
5927
5928 intel_update_watermarks(crtc);
5929 intel_enable_pipe(intel_crtc);
5930
5931 assert_vblank_disabled(crtc);
5932 drm_crtc_vblank_on(crtc);
5933
5934 for_each_encoder_on_crtc(dev, crtc, encoder)
5935 encoder->enable(encoder);
5936}
5937
5938static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5939{
5940 struct drm_device *dev = crtc->base.dev;
5941 struct drm_i915_private *dev_priv = dev->dev_private;
5942
5943 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5944 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5945}
5946
5947static void i9xx_crtc_enable(struct drm_crtc *crtc)
5948{
5949 struct drm_device *dev = crtc->dev;
5950 struct drm_i915_private *dev_priv = to_i915(dev);
5951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952 struct intel_encoder *encoder;
5953 int pipe = intel_crtc->pipe;
5954
5955 WARN_ON(!crtc->state->enable);
5956
5957 if (intel_crtc->active)
5958 return;
5959
5960 i9xx_set_pll_dividers(intel_crtc);
5961
5962 if (intel_crtc->config->has_dp_encoder)
5963 intel_dp_set_m_n(intel_crtc, M1_N1);
5964
5965 intel_set_pipe_timings(intel_crtc);
5966
5967 i9xx_set_pipeconf(intel_crtc);
5968
5969 intel_crtc->active = true;
5970
5971 if (!IS_GEN2(dev))
5972 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5973
5974 for_each_encoder_on_crtc(dev, crtc, encoder)
5975 if (encoder->pre_enable)
5976 encoder->pre_enable(encoder);
5977
5978 i9xx_enable_pll(intel_crtc);
5979
5980 i9xx_pfit_enable(intel_crtc);
5981
5982 intel_crtc_load_lut(crtc);
5983
5984 intel_update_watermarks(crtc);
5985 intel_enable_pipe(intel_crtc);
5986
5987 assert_vblank_disabled(crtc);
5988 drm_crtc_vblank_on(crtc);
5989
5990 for_each_encoder_on_crtc(dev, crtc, encoder)
5991 encoder->enable(encoder);
5992}
5993
5994static void i9xx_pfit_disable(struct intel_crtc *crtc)
5995{
5996 struct drm_device *dev = crtc->base.dev;
5997 struct drm_i915_private *dev_priv = dev->dev_private;
5998
5999 if (!crtc->config->gmch_pfit.control)
6000 return;
6001
6002 assert_pipe_disabled(dev_priv, crtc->pipe);
6003
6004 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6005 I915_READ(PFIT_CONTROL));
6006 I915_WRITE(PFIT_CONTROL, 0);
6007}
6008
6009static void i9xx_crtc_disable(struct drm_crtc *crtc)
6010{
6011 struct drm_device *dev = crtc->dev;
6012 struct drm_i915_private *dev_priv = dev->dev_private;
6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014 struct intel_encoder *encoder;
6015 int pipe = intel_crtc->pipe;
6016
6017 if (!intel_crtc->active)
6018 return;
6019
6020 /*
6021 * On gen2 planes are double buffered but the pipe isn't, so we must
6022 * wait for planes to fully turn off before disabling the pipe.
6023 * We also need to wait on all gmch platforms because of the
6024 * self-refresh mode constraint explained above.
6025 */
6026 intel_wait_for_vblank(dev, pipe);
6027
6028 for_each_encoder_on_crtc(dev, crtc, encoder)
6029 encoder->disable(encoder);
6030
6031 drm_crtc_vblank_off(crtc);
6032 assert_vblank_disabled(crtc);
6033
6034 intel_disable_pipe(intel_crtc);
6035
6036 i9xx_pfit_disable(intel_crtc);
6037
6038 for_each_encoder_on_crtc(dev, crtc, encoder)
6039 if (encoder->post_disable)
6040 encoder->post_disable(encoder);
6041
6042 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6043 if (IS_CHERRYVIEW(dev))
6044 chv_disable_pll(dev_priv, pipe);
6045 else if (IS_VALLEYVIEW(dev))
6046 vlv_disable_pll(dev_priv, pipe);
6047 else
6048 i9xx_disable_pll(intel_crtc);
6049 }
6050
6051 if (!IS_GEN2(dev))
6052 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6053
6054 intel_crtc->active = false;
6055 intel_update_watermarks(crtc);
6056
6057 mutex_lock(&dev->struct_mutex);
6058 intel_fbc_update(dev);
6059 mutex_unlock(&dev->struct_mutex);
6060}
6061
6062static void i9xx_crtc_off(struct drm_crtc *crtc)
6063{
6064}
6065
6066/* Master function to enable/disable CRTC and corresponding power wells */
6067void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6068{
6069 struct drm_device *dev = crtc->dev;
6070 struct drm_i915_private *dev_priv = dev->dev_private;
6071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072 enum intel_display_power_domain domain;
6073 unsigned long domains;
6074
6075 if (enable) {
6076 if (!intel_crtc->active) {
6077 domains = get_crtc_power_domains(crtc);
6078 for_each_power_domain(domain, domains)
6079 intel_display_power_get(dev_priv, domain);
6080 intel_crtc->enabled_power_domains = domains;
6081
6082 dev_priv->display.crtc_enable(crtc);
6083 intel_crtc_enable_planes(crtc);
6084 }
6085 } else {
6086 if (intel_crtc->active) {
6087 intel_crtc_disable_planes(crtc);
6088 dev_priv->display.crtc_disable(crtc);
6089
6090 domains = intel_crtc->enabled_power_domains;
6091 for_each_power_domain(domain, domains)
6092 intel_display_power_put(dev_priv, domain);
6093 intel_crtc->enabled_power_domains = 0;
6094 }
6095 }
6096}
6097
6098/**
6099 * Sets the power management mode of the pipe and plane.
6100 */
6101void intel_crtc_update_dpms(struct drm_crtc *crtc)
6102{
6103 struct drm_device *dev = crtc->dev;
6104 struct intel_encoder *intel_encoder;
6105 bool enable = false;
6106
6107 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6108 enable |= intel_encoder->connectors_active;
6109
6110 intel_crtc_control(crtc, enable);
6111}
6112
6113static void intel_crtc_disable(struct drm_crtc *crtc)
6114{
6115 struct drm_device *dev = crtc->dev;
6116 struct drm_connector *connector;
6117 struct drm_i915_private *dev_priv = dev->dev_private;
6118
6119 /* crtc should still be enabled when we disable it. */
6120 WARN_ON(!crtc->state->enable);
6121
6122 intel_crtc_disable_planes(crtc);
6123 dev_priv->display.crtc_disable(crtc);
6124 dev_priv->display.off(crtc);
6125
6126 drm_plane_helper_disable(crtc->primary);
6127
6128 /* Update computed state. */
6129 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6130 if (!connector->encoder || !connector->encoder->crtc)
6131 continue;
6132
6133 if (connector->encoder->crtc != crtc)
6134 continue;
6135
6136 connector->dpms = DRM_MODE_DPMS_OFF;
6137 to_intel_encoder(connector->encoder)->connectors_active = false;
6138 }
6139}
6140
6141void intel_encoder_destroy(struct drm_encoder *encoder)
6142{
6143 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6144
6145 drm_encoder_cleanup(encoder);
6146 kfree(intel_encoder);
6147}
6148
6149/* Simple dpms helper for encoders with just one connector, no cloning and only
6150 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6151 * state of the entire output pipe. */
6152static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6153{
6154 if (mode == DRM_MODE_DPMS_ON) {
6155 encoder->connectors_active = true;
6156
6157 intel_crtc_update_dpms(encoder->base.crtc);
6158 } else {
6159 encoder->connectors_active = false;
6160
6161 intel_crtc_update_dpms(encoder->base.crtc);
6162 }
6163}
6164
6165/* Cross check the actual hw state with our own modeset state tracking (and it's
6166 * internal consistency). */
6167static void intel_connector_check_state(struct intel_connector *connector)
6168{
6169 if (connector->get_hw_state(connector)) {
6170 struct intel_encoder *encoder = connector->encoder;
6171 struct drm_crtc *crtc;
6172 bool encoder_enabled;
6173 enum pipe pipe;
6174
6175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6176 connector->base.base.id,
6177 connector->base.name);
6178
6179 /* there is no real hw state for MST connectors */
6180 if (connector->mst_port)
6181 return;
6182
6183 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6184 "wrong connector dpms state\n");
6185 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6186 "active connector not linked to encoder\n");
6187
6188 if (encoder) {
6189 I915_STATE_WARN(!encoder->connectors_active,
6190 "encoder->connectors_active not set\n");
6191
6192 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6193 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6194 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6195 return;
6196
6197 crtc = encoder->base.crtc;
6198
6199 I915_STATE_WARN(!crtc->state->enable,
6200 "crtc not enabled\n");
6201 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6202 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6203 "encoder active on the wrong pipe\n");
6204 }
6205 }
6206}
6207
6208int intel_connector_init(struct intel_connector *connector)
6209{
6210 struct drm_connector_state *connector_state;
6211
6212 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6213 if (!connector_state)
6214 return -ENOMEM;
6215
6216 connector->base.state = connector_state;
6217 return 0;
6218}
6219
6220struct intel_connector *intel_connector_alloc(void)
6221{
6222 struct intel_connector *connector;
6223
6224 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6225 if (!connector)
6226 return NULL;
6227
6228 if (intel_connector_init(connector) < 0) {
6229 kfree(connector);
6230 return NULL;
6231 }
6232
6233 return connector;
6234}
6235
6236/* Even simpler default implementation, if there's really no special case to
6237 * consider. */
6238void intel_connector_dpms(struct drm_connector *connector, int mode)
6239{
6240 /* All the simple cases only support two dpms states. */
6241 if (mode != DRM_MODE_DPMS_ON)
6242 mode = DRM_MODE_DPMS_OFF;
6243
6244 if (mode == connector->dpms)
6245 return;
6246
6247 connector->dpms = mode;
6248
6249 /* Only need to change hw state when actually enabled */
6250 if (connector->encoder)
6251 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6252
6253 intel_modeset_check_state(connector->dev);
6254}
6255
6256/* Simple connector->get_hw_state implementation for encoders that support only
6257 * one connector and no cloning and hence the encoder state determines the state
6258 * of the connector. */
6259bool intel_connector_get_hw_state(struct intel_connector *connector)
6260{
6261 enum pipe pipe = 0;
6262 struct intel_encoder *encoder = connector->encoder;
6263
6264 return encoder->get_hw_state(encoder, &pipe);
6265}
6266
6267static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6268{
6269 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6270 return crtc_state->fdi_lanes;
6271
6272 return 0;
6273}
6274
6275static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6276 struct intel_crtc_state *pipe_config)
6277{
6278 struct drm_atomic_state *state = pipe_config->base.state;
6279 struct intel_crtc *other_crtc;
6280 struct intel_crtc_state *other_crtc_state;
6281
6282 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6283 pipe_name(pipe), pipe_config->fdi_lanes);
6284 if (pipe_config->fdi_lanes > 4) {
6285 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6286 pipe_name(pipe), pipe_config->fdi_lanes);
6287 return -EINVAL;
6288 }
6289
6290 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6291 if (pipe_config->fdi_lanes > 2) {
6292 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6293 pipe_config->fdi_lanes);
6294 return -EINVAL;
6295 } else {
6296 return 0;
6297 }
6298 }
6299
6300 if (INTEL_INFO(dev)->num_pipes == 2)
6301 return 0;
6302
6303 /* Ivybridge 3 pipe is really complicated */
6304 switch (pipe) {
6305 case PIPE_A:
6306 return 0;
6307 case PIPE_B:
6308 if (pipe_config->fdi_lanes <= 2)
6309 return 0;
6310
6311 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6312 other_crtc_state =
6313 intel_atomic_get_crtc_state(state, other_crtc);
6314 if (IS_ERR(other_crtc_state))
6315 return PTR_ERR(other_crtc_state);
6316
6317 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6318 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6319 pipe_name(pipe), pipe_config->fdi_lanes);
6320 return -EINVAL;
6321 }
6322 return 0;
6323 case PIPE_C:
6324 if (pipe_config->fdi_lanes > 2) {
6325 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6326 pipe_name(pipe), pipe_config->fdi_lanes);
6327 return -EINVAL;
6328 }
6329
6330 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6331 other_crtc_state =
6332 intel_atomic_get_crtc_state(state, other_crtc);
6333 if (IS_ERR(other_crtc_state))
6334 return PTR_ERR(other_crtc_state);
6335
6336 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6337 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6338 return -EINVAL;
6339 }
6340 return 0;
6341 default:
6342 BUG();
6343 }
6344}
6345
6346#define RETRY 1
6347static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6348 struct intel_crtc_state *pipe_config)
6349{
6350 struct drm_device *dev = intel_crtc->base.dev;
6351 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6352 int lane, link_bw, fdi_dotclock, ret;
6353 bool needs_recompute = false;
6354
6355retry:
6356 /* FDI is a binary signal running at ~2.7GHz, encoding
6357 * each output octet as 10 bits. The actual frequency
6358 * is stored as a divider into a 100MHz clock, and the
6359 * mode pixel clock is stored in units of 1KHz.
6360 * Hence the bw of each lane in terms of the mode signal
6361 * is:
6362 */
6363 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6364
6365 fdi_dotclock = adjusted_mode->crtc_clock;
6366
6367 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6368 pipe_config->pipe_bpp);
6369
6370 pipe_config->fdi_lanes = lane;
6371
6372 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6373 link_bw, &pipe_config->fdi_m_n);
6374
6375 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6376 intel_crtc->pipe, pipe_config);
6377 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6378 pipe_config->pipe_bpp -= 2*3;
6379 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6380 pipe_config->pipe_bpp);
6381 needs_recompute = true;
6382 pipe_config->bw_constrained = true;
6383
6384 goto retry;
6385 }
6386
6387 if (needs_recompute)
6388 return RETRY;
6389
6390 return ret;
6391}
6392
6393static void hsw_compute_ips_config(struct intel_crtc *crtc,
6394 struct intel_crtc_state *pipe_config)
6395{
6396 pipe_config->ips_enabled = i915.enable_ips &&
6397 hsw_crtc_supports_ips(crtc) &&
6398 pipe_config->pipe_bpp <= 24;
6399}
6400
6401static int intel_crtc_compute_config(struct intel_crtc *crtc,
6402 struct intel_crtc_state *pipe_config)
6403{
6404 struct drm_device *dev = crtc->base.dev;
6405 struct drm_i915_private *dev_priv = dev->dev_private;
6406 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6407 int ret;
6408
6409 /* FIXME should check pixel clock limits on all platforms */
6410 if (INTEL_INFO(dev)->gen < 4) {
6411 int clock_limit =
6412 dev_priv->display.get_display_clock_speed(dev);
6413
6414 /*
6415 * Enable pixel doubling when the dot clock
6416 * is > 90% of the (display) core speed.
6417 *
6418 * GDG double wide on either pipe,
6419 * otherwise pipe A only.
6420 */
6421 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6422 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6423 clock_limit *= 2;
6424 pipe_config->double_wide = true;
6425 }
6426
6427 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6428 return -EINVAL;
6429 }
6430
6431 /*
6432 * Pipe horizontal size must be even in:
6433 * - DVO ganged mode
6434 * - LVDS dual channel mode
6435 * - Double wide pipe
6436 */
6437 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6438 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6439 pipe_config->pipe_src_w &= ~1;
6440
6441 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6442 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6443 */
6444 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6445 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6446 return -EINVAL;
6447
6448 if (HAS_IPS(dev))
6449 hsw_compute_ips_config(crtc, pipe_config);
6450
6451 if (pipe_config->has_pch_encoder)
6452 return ironlake_fdi_compute_config(crtc, pipe_config);
6453
6454 /* FIXME: remove below call once atomic mode set is place and all crtc
6455 * related checks called from atomic_crtc_check function */
6456 ret = 0;
6457 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6458 crtc, pipe_config->base.state);
6459 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6460
6461 return ret;
6462}
6463
6464static int skylake_get_display_clock_speed(struct drm_device *dev)
6465{
6466 struct drm_i915_private *dev_priv = to_i915(dev);
6467 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6468 uint32_t cdctl = I915_READ(CDCLK_CTL);
6469 uint32_t linkrate;
6470
6471 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6472 WARN(1, "LCPLL1 not enabled\n");
6473 return 24000; /* 24MHz is the cd freq with NSSC ref */
6474 }
6475
6476 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6477 return 540000;
6478
6479 linkrate = (I915_READ(DPLL_CTRL1) &
6480 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6481
6482 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6483 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6484 /* vco 8640 */
6485 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6486 case CDCLK_FREQ_450_432:
6487 return 432000;
6488 case CDCLK_FREQ_337_308:
6489 return 308570;
6490 case CDCLK_FREQ_675_617:
6491 return 617140;
6492 default:
6493 WARN(1, "Unknown cd freq selection\n");
6494 }
6495 } else {
6496 /* vco 8100 */
6497 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6498 case CDCLK_FREQ_450_432:
6499 return 450000;
6500 case CDCLK_FREQ_337_308:
6501 return 337500;
6502 case CDCLK_FREQ_675_617:
6503 return 675000;
6504 default:
6505 WARN(1, "Unknown cd freq selection\n");
6506 }
6507 }
6508
6509 /* error case, do as if DPLL0 isn't enabled */
6510 return 24000;
6511}
6512
6513static int broadwell_get_display_clock_speed(struct drm_device *dev)
6514{
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 uint32_t lcpll = I915_READ(LCPLL_CTL);
6517 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6518
6519 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6520 return 800000;
6521 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6522 return 450000;
6523 else if (freq == LCPLL_CLK_FREQ_450)
6524 return 450000;
6525 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6526 return 540000;
6527 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6528 return 337500;
6529 else
6530 return 675000;
6531}
6532
6533static int haswell_get_display_clock_speed(struct drm_device *dev)
6534{
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 uint32_t lcpll = I915_READ(LCPLL_CTL);
6537 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6538
6539 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6540 return 800000;
6541 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6542 return 450000;
6543 else if (freq == LCPLL_CLK_FREQ_450)
6544 return 450000;
6545 else if (IS_HSW_ULT(dev))
6546 return 337500;
6547 else
6548 return 540000;
6549}
6550
6551static int valleyview_get_display_clock_speed(struct drm_device *dev)
6552{
6553 struct drm_i915_private *dev_priv = dev->dev_private;
6554 u32 val;
6555 int divider;
6556
6557 if (dev_priv->hpll_freq == 0)
6558 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6559
6560 mutex_lock(&dev_priv->dpio_lock);
6561 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6562 mutex_unlock(&dev_priv->dpio_lock);
6563
6564 divider = val & DISPLAY_FREQUENCY_VALUES;
6565
6566 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6567 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6568 "cdclk change in progress\n");
6569
6570 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6571}
6572
6573static int ilk_get_display_clock_speed(struct drm_device *dev)
6574{
6575 return 450000;
6576}
6577
6578static int i945_get_display_clock_speed(struct drm_device *dev)
6579{
6580 return 400000;
6581}
6582
6583static int i915_get_display_clock_speed(struct drm_device *dev)
6584{
6585 return 333333;
6586}
6587
6588static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6589{
6590 return 200000;
6591}
6592
6593static int pnv_get_display_clock_speed(struct drm_device *dev)
6594{
6595 u16 gcfgc = 0;
6596
6597 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6598
6599 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6600 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6601 return 266667;
6602 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6603 return 333333;
6604 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6605 return 444444;
6606 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6607 return 200000;
6608 default:
6609 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6610 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6611 return 133333;
6612 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6613 return 166667;
6614 }
6615}
6616
6617static int i915gm_get_display_clock_speed(struct drm_device *dev)
6618{
6619 u16 gcfgc = 0;
6620
6621 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6622
6623 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6624 return 133333;
6625 else {
6626 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6627 case GC_DISPLAY_CLOCK_333_MHZ:
6628 return 333333;
6629 default:
6630 case GC_DISPLAY_CLOCK_190_200_MHZ:
6631 return 190000;
6632 }
6633 }
6634}
6635
6636static int i865_get_display_clock_speed(struct drm_device *dev)
6637{
6638 return 266667;
6639}
6640
6641static int i855_get_display_clock_speed(struct drm_device *dev)
6642{
6643 u16 hpllcc = 0;
6644 /* Assume that the hardware is in the high speed state. This
6645 * should be the default.
6646 */
6647 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6648 case GC_CLOCK_133_200:
6649 case GC_CLOCK_100_200:
6650 return 200000;
6651 case GC_CLOCK_166_250:
6652 return 250000;
6653 case GC_CLOCK_100_133:
6654 return 133333;
6655 }
6656
6657 /* Shouldn't happen */
6658 return 0;
6659}
6660
6661static int i830_get_display_clock_speed(struct drm_device *dev)
6662{
6663 return 133333;
6664}
6665
6666static void
6667intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6668{
6669 while (*num > DATA_LINK_M_N_MASK ||
6670 *den > DATA_LINK_M_N_MASK) {
6671 *num >>= 1;
6672 *den >>= 1;
6673 }
6674}
6675
6676static void compute_m_n(unsigned int m, unsigned int n,
6677 uint32_t *ret_m, uint32_t *ret_n)
6678{
6679 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6680 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6681 intel_reduce_m_n_ratio(ret_m, ret_n);
6682}
6683
6684void
6685intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6686 int pixel_clock, int link_clock,
6687 struct intel_link_m_n *m_n)
6688{
6689 m_n->tu = 64;
6690
6691 compute_m_n(bits_per_pixel * pixel_clock,
6692 link_clock * nlanes * 8,
6693 &m_n->gmch_m, &m_n->gmch_n);
6694
6695 compute_m_n(pixel_clock, link_clock,
6696 &m_n->link_m, &m_n->link_n);
6697}
6698
6699static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6700{
6701 if (i915.panel_use_ssc >= 0)
6702 return i915.panel_use_ssc != 0;
6703 return dev_priv->vbt.lvds_use_ssc
6704 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6705}
6706
6707static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6708 int num_connectors)
6709{
6710 struct drm_device *dev = crtc_state->base.crtc->dev;
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 int refclk;
6713
6714 WARN_ON(!crtc_state->base.state);
6715
6716 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6717 refclk = 100000;
6718 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6719 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6720 refclk = dev_priv->vbt.lvds_ssc_freq;
6721 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6722 } else if (!IS_GEN2(dev)) {
6723 refclk = 96000;
6724 } else {
6725 refclk = 48000;
6726 }
6727
6728 return refclk;
6729}
6730
6731static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6732{
6733 return (1 << dpll->n) << 16 | dpll->m2;
6734}
6735
6736static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6737{
6738 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6739}
6740
6741static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6742 struct intel_crtc_state *crtc_state,
6743 intel_clock_t *reduced_clock)
6744{
6745 struct drm_device *dev = crtc->base.dev;
6746 u32 fp, fp2 = 0;
6747
6748 if (IS_PINEVIEW(dev)) {
6749 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6750 if (reduced_clock)
6751 fp2 = pnv_dpll_compute_fp(reduced_clock);
6752 } else {
6753 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6754 if (reduced_clock)
6755 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6756 }
6757
6758 crtc_state->dpll_hw_state.fp0 = fp;
6759
6760 crtc->lowfreq_avail = false;
6761 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6762 reduced_clock) {
6763 crtc_state->dpll_hw_state.fp1 = fp2;
6764 crtc->lowfreq_avail = true;
6765 } else {
6766 crtc_state->dpll_hw_state.fp1 = fp;
6767 }
6768}
6769
6770static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6771 pipe)
6772{
6773 u32 reg_val;
6774
6775 /*
6776 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6777 * and set it to a reasonable value instead.
6778 */
6779 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6780 reg_val &= 0xffffff00;
6781 reg_val |= 0x00000030;
6782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6783
6784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6785 reg_val &= 0x8cffffff;
6786 reg_val = 0x8c000000;
6787 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6788
6789 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6790 reg_val &= 0xffffff00;
6791 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6792
6793 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6794 reg_val &= 0x00ffffff;
6795 reg_val |= 0xb0000000;
6796 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6797}
6798
6799static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6800 struct intel_link_m_n *m_n)
6801{
6802 struct drm_device *dev = crtc->base.dev;
6803 struct drm_i915_private *dev_priv = dev->dev_private;
6804 int pipe = crtc->pipe;
6805
6806 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6807 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6808 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6809 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6810}
6811
6812static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6813 struct intel_link_m_n *m_n,
6814 struct intel_link_m_n *m2_n2)
6815{
6816 struct drm_device *dev = crtc->base.dev;
6817 struct drm_i915_private *dev_priv = dev->dev_private;
6818 int pipe = crtc->pipe;
6819 enum transcoder transcoder = crtc->config->cpu_transcoder;
6820
6821 if (INTEL_INFO(dev)->gen >= 5) {
6822 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6823 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6824 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6825 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6826 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6827 * for gen < 8) and if DRRS is supported (to make sure the
6828 * registers are not unnecessarily accessed).
6829 */
6830 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6831 crtc->config->has_drrs) {
6832 I915_WRITE(PIPE_DATA_M2(transcoder),
6833 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6834 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6835 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6836 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6837 }
6838 } else {
6839 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6840 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6841 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6842 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6843 }
6844}
6845
6846void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6847{
6848 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6849
6850 if (m_n == M1_N1) {
6851 dp_m_n = &crtc->config->dp_m_n;
6852 dp_m2_n2 = &crtc->config->dp_m2_n2;
6853 } else if (m_n == M2_N2) {
6854
6855 /*
6856 * M2_N2 registers are not supported. Hence m2_n2 divider value
6857 * needs to be programmed into M1_N1.
6858 */
6859 dp_m_n = &crtc->config->dp_m2_n2;
6860 } else {
6861 DRM_ERROR("Unsupported divider value\n");
6862 return;
6863 }
6864
6865 if (crtc->config->has_pch_encoder)
6866 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6867 else
6868 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6869}
6870
6871static void vlv_update_pll(struct intel_crtc *crtc,
6872 struct intel_crtc_state *pipe_config)
6873{
6874 u32 dpll, dpll_md;
6875
6876 /*
6877 * Enable DPIO clock input. We should never disable the reference
6878 * clock for pipe B, since VGA hotplug / manual detection depends
6879 * on it.
6880 */
6881 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6882 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6883 /* We should never disable this, set it here for state tracking */
6884 if (crtc->pipe == PIPE_B)
6885 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6886 dpll |= DPLL_VCO_ENABLE;
6887 pipe_config->dpll_hw_state.dpll = dpll;
6888
6889 dpll_md = (pipe_config->pixel_multiplier - 1)
6890 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6891 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6892}
6893
6894static void vlv_prepare_pll(struct intel_crtc *crtc,
6895 const struct intel_crtc_state *pipe_config)
6896{
6897 struct drm_device *dev = crtc->base.dev;
6898 struct drm_i915_private *dev_priv = dev->dev_private;
6899 int pipe = crtc->pipe;
6900 u32 mdiv;
6901 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6902 u32 coreclk, reg_val;
6903
6904 mutex_lock(&dev_priv->dpio_lock);
6905
6906 bestn = pipe_config->dpll.n;
6907 bestm1 = pipe_config->dpll.m1;
6908 bestm2 = pipe_config->dpll.m2;
6909 bestp1 = pipe_config->dpll.p1;
6910 bestp2 = pipe_config->dpll.p2;
6911
6912 /* See eDP HDMI DPIO driver vbios notes doc */
6913
6914 /* PLL B needs special handling */
6915 if (pipe == PIPE_B)
6916 vlv_pllb_recal_opamp(dev_priv, pipe);
6917
6918 /* Set up Tx target for periodic Rcomp update */
6919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6920
6921 /* Disable target IRef on PLL */
6922 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6923 reg_val &= 0x00ffffff;
6924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6925
6926 /* Disable fast lock */
6927 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6928
6929 /* Set idtafcrecal before PLL is enabled */
6930 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6931 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6932 mdiv |= ((bestn << DPIO_N_SHIFT));
6933 mdiv |= (1 << DPIO_K_SHIFT);
6934
6935 /*
6936 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6937 * but we don't support that).
6938 * Note: don't use the DAC post divider as it seems unstable.
6939 */
6940 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6942
6943 mdiv |= DPIO_ENABLE_CALIBRATION;
6944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6945
6946 /* Set HBR and RBR LPF coefficients */
6947 if (pipe_config->port_clock == 162000 ||
6948 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6949 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6951 0x009f0003);
6952 else
6953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6954 0x00d0000f);
6955
6956 if (pipe_config->has_dp_encoder) {
6957 /* Use SSC source */
6958 if (pipe == PIPE_A)
6959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6960 0x0df40000);
6961 else
6962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6963 0x0df70000);
6964 } else { /* HDMI or VGA */
6965 /* Use bend source */
6966 if (pipe == PIPE_A)
6967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6968 0x0df70000);
6969 else
6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6971 0x0df40000);
6972 }
6973
6974 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6975 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6976 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6977 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6978 coreclk |= 0x01000000;
6979 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6980
6981 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6982 mutex_unlock(&dev_priv->dpio_lock);
6983}
6984
6985static void chv_update_pll(struct intel_crtc *crtc,
6986 struct intel_crtc_state *pipe_config)
6987{
6988 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6989 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6990 DPLL_VCO_ENABLE;
6991 if (crtc->pipe != PIPE_A)
6992 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6993
6994 pipe_config->dpll_hw_state.dpll_md =
6995 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6996}
6997
6998static void chv_prepare_pll(struct intel_crtc *crtc,
6999 const struct intel_crtc_state *pipe_config)
7000{
7001 struct drm_device *dev = crtc->base.dev;
7002 struct drm_i915_private *dev_priv = dev->dev_private;
7003 int pipe = crtc->pipe;
7004 int dpll_reg = DPLL(crtc->pipe);
7005 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7006 u32 loopfilter, tribuf_calcntr;
7007 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7008 u32 dpio_val;
7009 int vco;
7010
7011 bestn = pipe_config->dpll.n;
7012 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7013 bestm1 = pipe_config->dpll.m1;
7014 bestm2 = pipe_config->dpll.m2 >> 22;
7015 bestp1 = pipe_config->dpll.p1;
7016 bestp2 = pipe_config->dpll.p2;
7017 vco = pipe_config->dpll.vco;
7018 dpio_val = 0;
7019 loopfilter = 0;
7020
7021 /*
7022 * Enable Refclk and SSC
7023 */
7024 I915_WRITE(dpll_reg,
7025 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7026
7027 mutex_lock(&dev_priv->dpio_lock);
7028
7029 /* p1 and p2 divider */
7030 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7031 5 << DPIO_CHV_S1_DIV_SHIFT |
7032 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7033 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7034 1 << DPIO_CHV_K_DIV_SHIFT);
7035
7036 /* Feedback post-divider - m2 */
7037 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7038
7039 /* Feedback refclk divider - n and m1 */
7040 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7041 DPIO_CHV_M1_DIV_BY_2 |
7042 1 << DPIO_CHV_N_DIV_SHIFT);
7043
7044 /* M2 fraction division */
7045 if (bestm2_frac)
7046 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7047
7048 /* M2 fraction division enable */
7049 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7050 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7051 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7052 if (bestm2_frac)
7053 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7054 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7055
7056 /* Program digital lock detect threshold */
7057 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7058 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7059 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7060 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7061 if (!bestm2_frac)
7062 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7063 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7064
7065 /* Loop filter */
7066 if (vco == 5400000) {
7067 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7068 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7069 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7070 tribuf_calcntr = 0x9;
7071 } else if (vco <= 6200000) {
7072 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7073 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7074 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7075 tribuf_calcntr = 0x9;
7076 } else if (vco <= 6480000) {
7077 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7078 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7079 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7080 tribuf_calcntr = 0x8;
7081 } else {
7082 /* Not supported. Apply the same limits as in the max case */
7083 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7084 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7085 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7086 tribuf_calcntr = 0;
7087 }
7088 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7089
7090 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7091 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7092 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7093 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7094
7095 /* AFC Recal */
7096 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7097 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7098 DPIO_AFC_RECAL);
7099
7100 mutex_unlock(&dev_priv->dpio_lock);
7101}
7102
7103/**
7104 * vlv_force_pll_on - forcibly enable just the PLL
7105 * @dev_priv: i915 private structure
7106 * @pipe: pipe PLL to enable
7107 * @dpll: PLL configuration
7108 *
7109 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7110 * in cases where we need the PLL enabled even when @pipe is not going to
7111 * be enabled.
7112 */
7113void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7114 const struct dpll *dpll)
7115{
7116 struct intel_crtc *crtc =
7117 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7118 struct intel_crtc_state pipe_config = {
7119 .base.crtc = &crtc->base,
7120 .pixel_multiplier = 1,
7121 .dpll = *dpll,
7122 };
7123
7124 if (IS_CHERRYVIEW(dev)) {
7125 chv_update_pll(crtc, &pipe_config);
7126 chv_prepare_pll(crtc, &pipe_config);
7127 chv_enable_pll(crtc, &pipe_config);
7128 } else {
7129 vlv_update_pll(crtc, &pipe_config);
7130 vlv_prepare_pll(crtc, &pipe_config);
7131 vlv_enable_pll(crtc, &pipe_config);
7132 }
7133}
7134
7135/**
7136 * vlv_force_pll_off - forcibly disable just the PLL
7137 * @dev_priv: i915 private structure
7138 * @pipe: pipe PLL to disable
7139 *
7140 * Disable the PLL for @pipe. To be used in cases where we need
7141 * the PLL enabled even when @pipe is not going to be enabled.
7142 */
7143void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7144{
7145 if (IS_CHERRYVIEW(dev))
7146 chv_disable_pll(to_i915(dev), pipe);
7147 else
7148 vlv_disable_pll(to_i915(dev), pipe);
7149}
7150
7151static void i9xx_update_pll(struct intel_crtc *crtc,
7152 struct intel_crtc_state *crtc_state,
7153 intel_clock_t *reduced_clock,
7154 int num_connectors)
7155{
7156 struct drm_device *dev = crtc->base.dev;
7157 struct drm_i915_private *dev_priv = dev->dev_private;
7158 u32 dpll;
7159 bool is_sdvo;
7160 struct dpll *clock = &crtc_state->dpll;
7161
7162 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7163
7164 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7165 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7166
7167 dpll = DPLL_VGA_MODE_DIS;
7168
7169 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7170 dpll |= DPLLB_MODE_LVDS;
7171 else
7172 dpll |= DPLLB_MODE_DAC_SERIAL;
7173
7174 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7175 dpll |= (crtc_state->pixel_multiplier - 1)
7176 << SDVO_MULTIPLIER_SHIFT_HIRES;
7177 }
7178
7179 if (is_sdvo)
7180 dpll |= DPLL_SDVO_HIGH_SPEED;
7181
7182 if (crtc_state->has_dp_encoder)
7183 dpll |= DPLL_SDVO_HIGH_SPEED;
7184
7185 /* compute bitmask from p1 value */
7186 if (IS_PINEVIEW(dev))
7187 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7188 else {
7189 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7190 if (IS_G4X(dev) && reduced_clock)
7191 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7192 }
7193 switch (clock->p2) {
7194 case 5:
7195 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7196 break;
7197 case 7:
7198 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7199 break;
7200 case 10:
7201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7202 break;
7203 case 14:
7204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7205 break;
7206 }
7207 if (INTEL_INFO(dev)->gen >= 4)
7208 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7209
7210 if (crtc_state->sdvo_tv_clock)
7211 dpll |= PLL_REF_INPUT_TVCLKINBC;
7212 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7213 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7214 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7215 else
7216 dpll |= PLL_REF_INPUT_DREFCLK;
7217
7218 dpll |= DPLL_VCO_ENABLE;
7219 crtc_state->dpll_hw_state.dpll = dpll;
7220
7221 if (INTEL_INFO(dev)->gen >= 4) {
7222 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7223 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7224 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7225 }
7226}
7227
7228static void i8xx_update_pll(struct intel_crtc *crtc,
7229 struct intel_crtc_state *crtc_state,
7230 intel_clock_t *reduced_clock,
7231 int num_connectors)
7232{
7233 struct drm_device *dev = crtc->base.dev;
7234 struct drm_i915_private *dev_priv = dev->dev_private;
7235 u32 dpll;
7236 struct dpll *clock = &crtc_state->dpll;
7237
7238 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7239
7240 dpll = DPLL_VGA_MODE_DIS;
7241
7242 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7243 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7244 } else {
7245 if (clock->p1 == 2)
7246 dpll |= PLL_P1_DIVIDE_BY_TWO;
7247 else
7248 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7249 if (clock->p2 == 4)
7250 dpll |= PLL_P2_DIVIDE_BY_4;
7251 }
7252
7253 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7254 dpll |= DPLL_DVO_2X_MODE;
7255
7256 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7257 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7258 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7259 else
7260 dpll |= PLL_REF_INPUT_DREFCLK;
7261
7262 dpll |= DPLL_VCO_ENABLE;
7263 crtc_state->dpll_hw_state.dpll = dpll;
7264}
7265
7266static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7267{
7268 struct drm_device *dev = intel_crtc->base.dev;
7269 struct drm_i915_private *dev_priv = dev->dev_private;
7270 enum pipe pipe = intel_crtc->pipe;
7271 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7272 struct drm_display_mode *adjusted_mode =
7273 &intel_crtc->config->base.adjusted_mode;
7274 uint32_t crtc_vtotal, crtc_vblank_end;
7275 int vsyncshift = 0;
7276
7277 /* We need to be careful not to changed the adjusted mode, for otherwise
7278 * the hw state checker will get angry at the mismatch. */
7279 crtc_vtotal = adjusted_mode->crtc_vtotal;
7280 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7281
7282 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7283 /* the chip adds 2 halflines automatically */
7284 crtc_vtotal -= 1;
7285 crtc_vblank_end -= 1;
7286
7287 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7288 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7289 else
7290 vsyncshift = adjusted_mode->crtc_hsync_start -
7291 adjusted_mode->crtc_htotal / 2;
7292 if (vsyncshift < 0)
7293 vsyncshift += adjusted_mode->crtc_htotal;
7294 }
7295
7296 if (INTEL_INFO(dev)->gen > 3)
7297 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7298
7299 I915_WRITE(HTOTAL(cpu_transcoder),
7300 (adjusted_mode->crtc_hdisplay - 1) |
7301 ((adjusted_mode->crtc_htotal - 1) << 16));
7302 I915_WRITE(HBLANK(cpu_transcoder),
7303 (adjusted_mode->crtc_hblank_start - 1) |
7304 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7305 I915_WRITE(HSYNC(cpu_transcoder),
7306 (adjusted_mode->crtc_hsync_start - 1) |
7307 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7308
7309 I915_WRITE(VTOTAL(cpu_transcoder),
7310 (adjusted_mode->crtc_vdisplay - 1) |
7311 ((crtc_vtotal - 1) << 16));
7312 I915_WRITE(VBLANK(cpu_transcoder),
7313 (adjusted_mode->crtc_vblank_start - 1) |
7314 ((crtc_vblank_end - 1) << 16));
7315 I915_WRITE(VSYNC(cpu_transcoder),
7316 (adjusted_mode->crtc_vsync_start - 1) |
7317 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7318
7319 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7320 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7321 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7322 * bits. */
7323 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7324 (pipe == PIPE_B || pipe == PIPE_C))
7325 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7326
7327 /* pipesrc controls the size that is scaled from, which should
7328 * always be the user's requested size.
7329 */
7330 I915_WRITE(PIPESRC(pipe),
7331 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7332 (intel_crtc->config->pipe_src_h - 1));
7333}
7334
7335static void intel_get_pipe_timings(struct intel_crtc *crtc,
7336 struct intel_crtc_state *pipe_config)
7337{
7338 struct drm_device *dev = crtc->base.dev;
7339 struct drm_i915_private *dev_priv = dev->dev_private;
7340 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7341 uint32_t tmp;
7342
7343 tmp = I915_READ(HTOTAL(cpu_transcoder));
7344 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7345 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7346 tmp = I915_READ(HBLANK(cpu_transcoder));
7347 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7348 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7349 tmp = I915_READ(HSYNC(cpu_transcoder));
7350 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7351 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7352
7353 tmp = I915_READ(VTOTAL(cpu_transcoder));
7354 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7355 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7356 tmp = I915_READ(VBLANK(cpu_transcoder));
7357 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7358 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7359 tmp = I915_READ(VSYNC(cpu_transcoder));
7360 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7361 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7362
7363 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7364 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7365 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7366 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7367 }
7368
7369 tmp = I915_READ(PIPESRC(crtc->pipe));
7370 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7371 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7372
7373 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7374 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7375}
7376
7377void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7378 struct intel_crtc_state *pipe_config)
7379{
7380 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7381 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7382 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7383 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7384
7385 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7386 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7387 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7388 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7389
7390 mode->flags = pipe_config->base.adjusted_mode.flags;
7391
7392 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7393 mode->flags |= pipe_config->base.adjusted_mode.flags;
7394}
7395
7396static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7397{
7398 struct drm_device *dev = intel_crtc->base.dev;
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 uint32_t pipeconf;
7401
7402 pipeconf = 0;
7403
7404 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7405 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7406 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7407
7408 if (intel_crtc->config->double_wide)
7409 pipeconf |= PIPECONF_DOUBLE_WIDE;
7410
7411 /* only g4x and later have fancy bpc/dither controls */
7412 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7413 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7414 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7415 pipeconf |= PIPECONF_DITHER_EN |
7416 PIPECONF_DITHER_TYPE_SP;
7417
7418 switch (intel_crtc->config->pipe_bpp) {
7419 case 18:
7420 pipeconf |= PIPECONF_6BPC;
7421 break;
7422 case 24:
7423 pipeconf |= PIPECONF_8BPC;
7424 break;
7425 case 30:
7426 pipeconf |= PIPECONF_10BPC;
7427 break;
7428 default:
7429 /* Case prevented by intel_choose_pipe_bpp_dither. */
7430 BUG();
7431 }
7432 }
7433
7434 if (HAS_PIPE_CXSR(dev)) {
7435 if (intel_crtc->lowfreq_avail) {
7436 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7437 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7438 } else {
7439 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7440 }
7441 }
7442
7443 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7444 if (INTEL_INFO(dev)->gen < 4 ||
7445 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7446 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7447 else
7448 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7449 } else
7450 pipeconf |= PIPECONF_PROGRESSIVE;
7451
7452 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7453 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7454
7455 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7456 POSTING_READ(PIPECONF(intel_crtc->pipe));
7457}
7458
7459static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7460 struct intel_crtc_state *crtc_state)
7461{
7462 struct drm_device *dev = crtc->base.dev;
7463 struct drm_i915_private *dev_priv = dev->dev_private;
7464 int refclk, num_connectors = 0;
7465 intel_clock_t clock, reduced_clock;
7466 bool ok, has_reduced_clock = false;
7467 bool is_lvds = false, is_dsi = false;
7468 struct intel_encoder *encoder;
7469 const intel_limit_t *limit;
7470 struct drm_atomic_state *state = crtc_state->base.state;
7471 struct drm_connector *connector;
7472 struct drm_connector_state *connector_state;
7473 int i;
7474
7475 for_each_connector_in_state(state, connector, connector_state, i) {
7476 if (connector_state->crtc != &crtc->base)
7477 continue;
7478
7479 encoder = to_intel_encoder(connector_state->best_encoder);
7480
7481 switch (encoder->type) {
7482 case INTEL_OUTPUT_LVDS:
7483 is_lvds = true;
7484 break;
7485 case INTEL_OUTPUT_DSI:
7486 is_dsi = true;
7487 break;
7488 default:
7489 break;
7490 }
7491
7492 num_connectors++;
7493 }
7494
7495 if (is_dsi)
7496 return 0;
7497
7498 if (!crtc_state->clock_set) {
7499 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7500
7501 /*
7502 * Returns a set of divisors for the desired target clock with
7503 * the given refclk, or FALSE. The returned values represent
7504 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7505 * 2) / p1 / p2.
7506 */
7507 limit = intel_limit(crtc_state, refclk);
7508 ok = dev_priv->display.find_dpll(limit, crtc_state,
7509 crtc_state->port_clock,
7510 refclk, NULL, &clock);
7511 if (!ok) {
7512 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7513 return -EINVAL;
7514 }
7515
7516 if (is_lvds && dev_priv->lvds_downclock_avail) {
7517 /*
7518 * Ensure we match the reduced clock's P to the target
7519 * clock. If the clocks don't match, we can't switch
7520 * the display clock by using the FP0/FP1. In such case
7521 * we will disable the LVDS downclock feature.
7522 */
7523 has_reduced_clock =
7524 dev_priv->display.find_dpll(limit, crtc_state,
7525 dev_priv->lvds_downclock,
7526 refclk, &clock,
7527 &reduced_clock);
7528 }
7529 /* Compat-code for transition, will disappear. */
7530 crtc_state->dpll.n = clock.n;
7531 crtc_state->dpll.m1 = clock.m1;
7532 crtc_state->dpll.m2 = clock.m2;
7533 crtc_state->dpll.p1 = clock.p1;
7534 crtc_state->dpll.p2 = clock.p2;
7535 }
7536
7537 if (IS_GEN2(dev)) {
7538 i8xx_update_pll(crtc, crtc_state,
7539 has_reduced_clock ? &reduced_clock : NULL,
7540 num_connectors);
7541 } else if (IS_CHERRYVIEW(dev)) {
7542 chv_update_pll(crtc, crtc_state);
7543 } else if (IS_VALLEYVIEW(dev)) {
7544 vlv_update_pll(crtc, crtc_state);
7545 } else {
7546 i9xx_update_pll(crtc, crtc_state,
7547 has_reduced_clock ? &reduced_clock : NULL,
7548 num_connectors);
7549 }
7550
7551 return 0;
7552}
7553
7554static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7555 struct intel_crtc_state *pipe_config)
7556{
7557 struct drm_device *dev = crtc->base.dev;
7558 struct drm_i915_private *dev_priv = dev->dev_private;
7559 uint32_t tmp;
7560
7561 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7562 return;
7563
7564 tmp = I915_READ(PFIT_CONTROL);
7565 if (!(tmp & PFIT_ENABLE))
7566 return;
7567
7568 /* Check whether the pfit is attached to our pipe. */
7569 if (INTEL_INFO(dev)->gen < 4) {
7570 if (crtc->pipe != PIPE_B)
7571 return;
7572 } else {
7573 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7574 return;
7575 }
7576
7577 pipe_config->gmch_pfit.control = tmp;
7578 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7579 if (INTEL_INFO(dev)->gen < 5)
7580 pipe_config->gmch_pfit.lvds_border_bits =
7581 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7582}
7583
7584static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7585 struct intel_crtc_state *pipe_config)
7586{
7587 struct drm_device *dev = crtc->base.dev;
7588 struct drm_i915_private *dev_priv = dev->dev_private;
7589 int pipe = pipe_config->cpu_transcoder;
7590 intel_clock_t clock;
7591 u32 mdiv;
7592 int refclk = 100000;
7593
7594 /* In case of MIPI DPLL will not even be used */
7595 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7596 return;
7597
7598 mutex_lock(&dev_priv->dpio_lock);
7599 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7600 mutex_unlock(&dev_priv->dpio_lock);
7601
7602 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7603 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7604 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7605 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7606 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7607
7608 vlv_clock(refclk, &clock);
7609
7610 /* clock.dot is the fast clock */
7611 pipe_config->port_clock = clock.dot / 5;
7612}
7613
7614static void
7615i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7616 struct intel_initial_plane_config *plane_config)
7617{
7618 struct drm_device *dev = crtc->base.dev;
7619 struct drm_i915_private *dev_priv = dev->dev_private;
7620 u32 val, base, offset;
7621 int pipe = crtc->pipe, plane = crtc->plane;
7622 int fourcc, pixel_format;
7623 unsigned int aligned_height;
7624 struct drm_framebuffer *fb;
7625 struct intel_framebuffer *intel_fb;
7626
7627 val = I915_READ(DSPCNTR(plane));
7628 if (!(val & DISPLAY_PLANE_ENABLE))
7629 return;
7630
7631 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7632 if (!intel_fb) {
7633 DRM_DEBUG_KMS("failed to alloc fb\n");
7634 return;
7635 }
7636
7637 fb = &intel_fb->base;
7638
7639 if (INTEL_INFO(dev)->gen >= 4) {
7640 if (val & DISPPLANE_TILED) {
7641 plane_config->tiling = I915_TILING_X;
7642 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7643 }
7644 }
7645
7646 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7647 fourcc = i9xx_format_to_fourcc(pixel_format);
7648 fb->pixel_format = fourcc;
7649 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7650
7651 if (INTEL_INFO(dev)->gen >= 4) {
7652 if (plane_config->tiling)
7653 offset = I915_READ(DSPTILEOFF(plane));
7654 else
7655 offset = I915_READ(DSPLINOFF(plane));
7656 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7657 } else {
7658 base = I915_READ(DSPADDR(plane));
7659 }
7660 plane_config->base = base;
7661
7662 val = I915_READ(PIPESRC(pipe));
7663 fb->width = ((val >> 16) & 0xfff) + 1;
7664 fb->height = ((val >> 0) & 0xfff) + 1;
7665
7666 val = I915_READ(DSPSTRIDE(pipe));
7667 fb->pitches[0] = val & 0xffffffc0;
7668
7669 aligned_height = intel_fb_align_height(dev, fb->height,
7670 fb->pixel_format,
7671 fb->modifier[0]);
7672
7673 plane_config->size = fb->pitches[0] * aligned_height;
7674
7675 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7676 pipe_name(pipe), plane, fb->width, fb->height,
7677 fb->bits_per_pixel, base, fb->pitches[0],
7678 plane_config->size);
7679
7680 plane_config->fb = intel_fb;
7681}
7682
7683static void chv_crtc_clock_get(struct intel_crtc *crtc,
7684 struct intel_crtc_state *pipe_config)
7685{
7686 struct drm_device *dev = crtc->base.dev;
7687 struct drm_i915_private *dev_priv = dev->dev_private;
7688 int pipe = pipe_config->cpu_transcoder;
7689 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7690 intel_clock_t clock;
7691 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7692 int refclk = 100000;
7693
7694 mutex_lock(&dev_priv->dpio_lock);
7695 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7696 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7697 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7698 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7699 mutex_unlock(&dev_priv->dpio_lock);
7700
7701 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7702 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7703 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7704 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7705 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7706
7707 chv_clock(refclk, &clock);
7708
7709 /* clock.dot is the fast clock */
7710 pipe_config->port_clock = clock.dot / 5;
7711}
7712
7713static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7714 struct intel_crtc_state *pipe_config)
7715{
7716 struct drm_device *dev = crtc->base.dev;
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7718 uint32_t tmp;
7719
7720 if (!intel_display_power_is_enabled(dev_priv,
7721 POWER_DOMAIN_PIPE(crtc->pipe)))
7722 return false;
7723
7724 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7725 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7726
7727 tmp = I915_READ(PIPECONF(crtc->pipe));
7728 if (!(tmp & PIPECONF_ENABLE))
7729 return false;
7730
7731 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7732 switch (tmp & PIPECONF_BPC_MASK) {
7733 case PIPECONF_6BPC:
7734 pipe_config->pipe_bpp = 18;
7735 break;
7736 case PIPECONF_8BPC:
7737 pipe_config->pipe_bpp = 24;
7738 break;
7739 case PIPECONF_10BPC:
7740 pipe_config->pipe_bpp = 30;
7741 break;
7742 default:
7743 break;
7744 }
7745 }
7746
7747 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7748 pipe_config->limited_color_range = true;
7749
7750 if (INTEL_INFO(dev)->gen < 4)
7751 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7752
7753 intel_get_pipe_timings(crtc, pipe_config);
7754
7755 i9xx_get_pfit_config(crtc, pipe_config);
7756
7757 if (INTEL_INFO(dev)->gen >= 4) {
7758 tmp = I915_READ(DPLL_MD(crtc->pipe));
7759 pipe_config->pixel_multiplier =
7760 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7761 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7762 pipe_config->dpll_hw_state.dpll_md = tmp;
7763 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7764 tmp = I915_READ(DPLL(crtc->pipe));
7765 pipe_config->pixel_multiplier =
7766 ((tmp & SDVO_MULTIPLIER_MASK)
7767 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7768 } else {
7769 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7770 * port and will be fixed up in the encoder->get_config
7771 * function. */
7772 pipe_config->pixel_multiplier = 1;
7773 }
7774 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7775 if (!IS_VALLEYVIEW(dev)) {
7776 /*
7777 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7778 * on 830. Filter it out here so that we don't
7779 * report errors due to that.
7780 */
7781 if (IS_I830(dev))
7782 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7783
7784 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7785 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7786 } else {
7787 /* Mask out read-only status bits. */
7788 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7789 DPLL_PORTC_READY_MASK |
7790 DPLL_PORTB_READY_MASK);
7791 }
7792
7793 if (IS_CHERRYVIEW(dev))
7794 chv_crtc_clock_get(crtc, pipe_config);
7795 else if (IS_VALLEYVIEW(dev))
7796 vlv_crtc_clock_get(crtc, pipe_config);
7797 else
7798 i9xx_crtc_clock_get(crtc, pipe_config);
7799
7800 return true;
7801}
7802
7803static void ironlake_init_pch_refclk(struct drm_device *dev)
7804{
7805 struct drm_i915_private *dev_priv = dev->dev_private;
7806 struct intel_encoder *encoder;
7807 u32 val, final;
7808 bool has_lvds = false;
7809 bool has_cpu_edp = false;
7810 bool has_panel = false;
7811 bool has_ck505 = false;
7812 bool can_ssc = false;
7813
7814 /* We need to take the global config into account */
7815 for_each_intel_encoder(dev, encoder) {
7816 switch (encoder->type) {
7817 case INTEL_OUTPUT_LVDS:
7818 has_panel = true;
7819 has_lvds = true;
7820 break;
7821 case INTEL_OUTPUT_EDP:
7822 has_panel = true;
7823 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7824 has_cpu_edp = true;
7825 break;
7826 default:
7827 break;
7828 }
7829 }
7830
7831 if (HAS_PCH_IBX(dev)) {
7832 has_ck505 = dev_priv->vbt.display_clock_mode;
7833 can_ssc = has_ck505;
7834 } else {
7835 has_ck505 = false;
7836 can_ssc = true;
7837 }
7838
7839 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7840 has_panel, has_lvds, has_ck505);
7841
7842 /* Ironlake: try to setup display ref clock before DPLL
7843 * enabling. This is only under driver's control after
7844 * PCH B stepping, previous chipset stepping should be
7845 * ignoring this setting.
7846 */
7847 val = I915_READ(PCH_DREF_CONTROL);
7848
7849 /* As we must carefully and slowly disable/enable each source in turn,
7850 * compute the final state we want first and check if we need to
7851 * make any changes at all.
7852 */
7853 final = val;
7854 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7855 if (has_ck505)
7856 final |= DREF_NONSPREAD_CK505_ENABLE;
7857 else
7858 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7859
7860 final &= ~DREF_SSC_SOURCE_MASK;
7861 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7862 final &= ~DREF_SSC1_ENABLE;
7863
7864 if (has_panel) {
7865 final |= DREF_SSC_SOURCE_ENABLE;
7866
7867 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7868 final |= DREF_SSC1_ENABLE;
7869
7870 if (has_cpu_edp) {
7871 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7872 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7873 else
7874 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7875 } else
7876 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7877 } else {
7878 final |= DREF_SSC_SOURCE_DISABLE;
7879 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7880 }
7881
7882 if (final == val)
7883 return;
7884
7885 /* Always enable nonspread source */
7886 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7887
7888 if (has_ck505)
7889 val |= DREF_NONSPREAD_CK505_ENABLE;
7890 else
7891 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7892
7893 if (has_panel) {
7894 val &= ~DREF_SSC_SOURCE_MASK;
7895 val |= DREF_SSC_SOURCE_ENABLE;
7896
7897 /* SSC must be turned on before enabling the CPU output */
7898 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7899 DRM_DEBUG_KMS("Using SSC on panel\n");
7900 val |= DREF_SSC1_ENABLE;
7901 } else
7902 val &= ~DREF_SSC1_ENABLE;
7903
7904 /* Get SSC going before enabling the outputs */
7905 I915_WRITE(PCH_DREF_CONTROL, val);
7906 POSTING_READ(PCH_DREF_CONTROL);
7907 udelay(200);
7908
7909 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7910
7911 /* Enable CPU source on CPU attached eDP */
7912 if (has_cpu_edp) {
7913 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7914 DRM_DEBUG_KMS("Using SSC on eDP\n");
7915 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7916 } else
7917 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7918 } else
7919 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7920
7921 I915_WRITE(PCH_DREF_CONTROL, val);
7922 POSTING_READ(PCH_DREF_CONTROL);
7923 udelay(200);
7924 } else {
7925 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7926
7927 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7928
7929 /* Turn off CPU output */
7930 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7931
7932 I915_WRITE(PCH_DREF_CONTROL, val);
7933 POSTING_READ(PCH_DREF_CONTROL);
7934 udelay(200);
7935
7936 /* Turn off the SSC source */
7937 val &= ~DREF_SSC_SOURCE_MASK;
7938 val |= DREF_SSC_SOURCE_DISABLE;
7939
7940 /* Turn off SSC1 */
7941 val &= ~DREF_SSC1_ENABLE;
7942
7943 I915_WRITE(PCH_DREF_CONTROL, val);
7944 POSTING_READ(PCH_DREF_CONTROL);
7945 udelay(200);
7946 }
7947
7948 BUG_ON(val != final);
7949}
7950
7951static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7952{
7953 uint32_t tmp;
7954
7955 tmp = I915_READ(SOUTH_CHICKEN2);
7956 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7957 I915_WRITE(SOUTH_CHICKEN2, tmp);
7958
7959 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7960 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7961 DRM_ERROR("FDI mPHY reset assert timeout\n");
7962
7963 tmp = I915_READ(SOUTH_CHICKEN2);
7964 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7965 I915_WRITE(SOUTH_CHICKEN2, tmp);
7966
7967 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7968 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7969 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7970}
7971
7972/* WaMPhyProgramming:hsw */
7973static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7974{
7975 uint32_t tmp;
7976
7977 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7978 tmp &= ~(0xFF << 24);
7979 tmp |= (0x12 << 24);
7980 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7981
7982 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7983 tmp |= (1 << 11);
7984 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7985
7986 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7987 tmp |= (1 << 11);
7988 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7989
7990 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7991 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7992 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7993
7994 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7995 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7996 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7997
7998 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7999 tmp &= ~(7 << 13);
8000 tmp |= (5 << 13);
8001 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8002
8003 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8004 tmp &= ~(7 << 13);
8005 tmp |= (5 << 13);
8006 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8007
8008 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8009 tmp &= ~0xFF;
8010 tmp |= 0x1C;
8011 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8012
8013 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8014 tmp &= ~0xFF;
8015 tmp |= 0x1C;
8016 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8017
8018 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8019 tmp &= ~(0xFF << 16);
8020 tmp |= (0x1C << 16);
8021 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8022
8023 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8024 tmp &= ~(0xFF << 16);
8025 tmp |= (0x1C << 16);
8026 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8027
8028 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8029 tmp |= (1 << 27);
8030 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8031
8032 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8033 tmp |= (1 << 27);
8034 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8035
8036 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8037 tmp &= ~(0xF << 28);
8038 tmp |= (4 << 28);
8039 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8040
8041 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8042 tmp &= ~(0xF << 28);
8043 tmp |= (4 << 28);
8044 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8045}
8046
8047/* Implements 3 different sequences from BSpec chapter "Display iCLK
8048 * Programming" based on the parameters passed:
8049 * - Sequence to enable CLKOUT_DP
8050 * - Sequence to enable CLKOUT_DP without spread
8051 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8052 */
8053static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8054 bool with_fdi)
8055{
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 uint32_t reg, tmp;
8058
8059 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8060 with_spread = true;
8061 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8062 with_fdi, "LP PCH doesn't have FDI\n"))
8063 with_fdi = false;
8064
8065 mutex_lock(&dev_priv->dpio_lock);
8066
8067 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8068 tmp &= ~SBI_SSCCTL_DISABLE;
8069 tmp |= SBI_SSCCTL_PATHALT;
8070 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8071
8072 udelay(24);
8073
8074 if (with_spread) {
8075 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8076 tmp &= ~SBI_SSCCTL_PATHALT;
8077 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8078
8079 if (with_fdi) {
8080 lpt_reset_fdi_mphy(dev_priv);
8081 lpt_program_fdi_mphy(dev_priv);
8082 }
8083 }
8084
8085 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8086 SBI_GEN0 : SBI_DBUFF0;
8087 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8088 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8089 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8090
8091 mutex_unlock(&dev_priv->dpio_lock);
8092}
8093
8094/* Sequence to disable CLKOUT_DP */
8095static void lpt_disable_clkout_dp(struct drm_device *dev)
8096{
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 uint32_t reg, tmp;
8099
8100 mutex_lock(&dev_priv->dpio_lock);
8101
8102 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8103 SBI_GEN0 : SBI_DBUFF0;
8104 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8105 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8106 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8107
8108 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8109 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8110 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8111 tmp |= SBI_SSCCTL_PATHALT;
8112 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8113 udelay(32);
8114 }
8115 tmp |= SBI_SSCCTL_DISABLE;
8116 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8117 }
8118
8119 mutex_unlock(&dev_priv->dpio_lock);
8120}
8121
8122static void lpt_init_pch_refclk(struct drm_device *dev)
8123{
8124 struct intel_encoder *encoder;
8125 bool has_vga = false;
8126
8127 for_each_intel_encoder(dev, encoder) {
8128 switch (encoder->type) {
8129 case INTEL_OUTPUT_ANALOG:
8130 has_vga = true;
8131 break;
8132 default:
8133 break;
8134 }
8135 }
8136
8137 if (has_vga)
8138 lpt_enable_clkout_dp(dev, true, true);
8139 else
8140 lpt_disable_clkout_dp(dev);
8141}
8142
8143/*
8144 * Initialize reference clocks when the driver loads
8145 */
8146void intel_init_pch_refclk(struct drm_device *dev)
8147{
8148 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8149 ironlake_init_pch_refclk(dev);
8150 else if (HAS_PCH_LPT(dev))
8151 lpt_init_pch_refclk(dev);
8152}
8153
8154static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8155{
8156 struct drm_device *dev = crtc_state->base.crtc->dev;
8157 struct drm_i915_private *dev_priv = dev->dev_private;
8158 struct drm_atomic_state *state = crtc_state->base.state;
8159 struct drm_connector *connector;
8160 struct drm_connector_state *connector_state;
8161 struct intel_encoder *encoder;
8162 int num_connectors = 0, i;
8163 bool is_lvds = false;
8164
8165 for_each_connector_in_state(state, connector, connector_state, i) {
8166 if (connector_state->crtc != crtc_state->base.crtc)
8167 continue;
8168
8169 encoder = to_intel_encoder(connector_state->best_encoder);
8170
8171 switch (encoder->type) {
8172 case INTEL_OUTPUT_LVDS:
8173 is_lvds = true;
8174 break;
8175 default:
8176 break;
8177 }
8178 num_connectors++;
8179 }
8180
8181 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8182 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8183 dev_priv->vbt.lvds_ssc_freq);
8184 return dev_priv->vbt.lvds_ssc_freq;
8185 }
8186
8187 return 120000;
8188}
8189
8190static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8191{
8192 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8194 int pipe = intel_crtc->pipe;
8195 uint32_t val;
8196
8197 val = 0;
8198
8199 switch (intel_crtc->config->pipe_bpp) {
8200 case 18:
8201 val |= PIPECONF_6BPC;
8202 break;
8203 case 24:
8204 val |= PIPECONF_8BPC;
8205 break;
8206 case 30:
8207 val |= PIPECONF_10BPC;
8208 break;
8209 case 36:
8210 val |= PIPECONF_12BPC;
8211 break;
8212 default:
8213 /* Case prevented by intel_choose_pipe_bpp_dither. */
8214 BUG();
8215 }
8216
8217 if (intel_crtc->config->dither)
8218 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8219
8220 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8221 val |= PIPECONF_INTERLACED_ILK;
8222 else
8223 val |= PIPECONF_PROGRESSIVE;
8224
8225 if (intel_crtc->config->limited_color_range)
8226 val |= PIPECONF_COLOR_RANGE_SELECT;
8227
8228 I915_WRITE(PIPECONF(pipe), val);
8229 POSTING_READ(PIPECONF(pipe));
8230}
8231
8232/*
8233 * Set up the pipe CSC unit.
8234 *
8235 * Currently only full range RGB to limited range RGB conversion
8236 * is supported, but eventually this should handle various
8237 * RGB<->YCbCr scenarios as well.
8238 */
8239static void intel_set_pipe_csc(struct drm_crtc *crtc)
8240{
8241 struct drm_device *dev = crtc->dev;
8242 struct drm_i915_private *dev_priv = dev->dev_private;
8243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8244 int pipe = intel_crtc->pipe;
8245 uint16_t coeff = 0x7800; /* 1.0 */
8246
8247 /*
8248 * TODO: Check what kind of values actually come out of the pipe
8249 * with these coeff/postoff values and adjust to get the best
8250 * accuracy. Perhaps we even need to take the bpc value into
8251 * consideration.
8252 */
8253
8254 if (intel_crtc->config->limited_color_range)
8255 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8256
8257 /*
8258 * GY/GU and RY/RU should be the other way around according
8259 * to BSpec, but reality doesn't agree. Just set them up in
8260 * a way that results in the correct picture.
8261 */
8262 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8263 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8264
8265 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8266 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8267
8268 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8269 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8270
8271 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8272 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8273 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8274
8275 if (INTEL_INFO(dev)->gen > 6) {
8276 uint16_t postoff = 0;
8277
8278 if (intel_crtc->config->limited_color_range)
8279 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8280
8281 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8282 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8283 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8284
8285 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8286 } else {
8287 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8288
8289 if (intel_crtc->config->limited_color_range)
8290 mode |= CSC_BLACK_SCREEN_OFFSET;
8291
8292 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8293 }
8294}
8295
8296static void haswell_set_pipeconf(struct drm_crtc *crtc)
8297{
8298 struct drm_device *dev = crtc->dev;
8299 struct drm_i915_private *dev_priv = dev->dev_private;
8300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8301 enum pipe pipe = intel_crtc->pipe;
8302 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8303 uint32_t val;
8304
8305 val = 0;
8306
8307 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8308 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8309
8310 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8311 val |= PIPECONF_INTERLACED_ILK;
8312 else
8313 val |= PIPECONF_PROGRESSIVE;
8314
8315 I915_WRITE(PIPECONF(cpu_transcoder), val);
8316 POSTING_READ(PIPECONF(cpu_transcoder));
8317
8318 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8319 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8320
8321 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8322 val = 0;
8323
8324 switch (intel_crtc->config->pipe_bpp) {
8325 case 18:
8326 val |= PIPEMISC_DITHER_6_BPC;
8327 break;
8328 case 24:
8329 val |= PIPEMISC_DITHER_8_BPC;
8330 break;
8331 case 30:
8332 val |= PIPEMISC_DITHER_10_BPC;
8333 break;
8334 case 36:
8335 val |= PIPEMISC_DITHER_12_BPC;
8336 break;
8337 default:
8338 /* Case prevented by pipe_config_set_bpp. */
8339 BUG();
8340 }
8341
8342 if (intel_crtc->config->dither)
8343 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8344
8345 I915_WRITE(PIPEMISC(pipe), val);
8346 }
8347}
8348
8349static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8350 struct intel_crtc_state *crtc_state,
8351 intel_clock_t *clock,
8352 bool *has_reduced_clock,
8353 intel_clock_t *reduced_clock)
8354{
8355 struct drm_device *dev = crtc->dev;
8356 struct drm_i915_private *dev_priv = dev->dev_private;
8357 int refclk;
8358 const intel_limit_t *limit;
8359 bool ret, is_lvds = false;
8360
8361 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8362
8363 refclk = ironlake_get_refclk(crtc_state);
8364
8365 /*
8366 * Returns a set of divisors for the desired target clock with the given
8367 * refclk, or FALSE. The returned values represent the clock equation:
8368 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8369 */
8370 limit = intel_limit(crtc_state, refclk);
8371 ret = dev_priv->display.find_dpll(limit, crtc_state,
8372 crtc_state->port_clock,
8373 refclk, NULL, clock);
8374 if (!ret)
8375 return false;
8376
8377 if (is_lvds && dev_priv->lvds_downclock_avail) {
8378 /*
8379 * Ensure we match the reduced clock's P to the target clock.
8380 * If the clocks don't match, we can't switch the display clock
8381 * by using the FP0/FP1. In such case we will disable the LVDS
8382 * downclock feature.
8383 */
8384 *has_reduced_clock =
8385 dev_priv->display.find_dpll(limit, crtc_state,
8386 dev_priv->lvds_downclock,
8387 refclk, clock,
8388 reduced_clock);
8389 }
8390
8391 return true;
8392}
8393
8394int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8395{
8396 /*
8397 * Account for spread spectrum to avoid
8398 * oversubscribing the link. Max center spread
8399 * is 2.5%; use 5% for safety's sake.
8400 */
8401 u32 bps = target_clock * bpp * 21 / 20;
8402 return DIV_ROUND_UP(bps, link_bw * 8);
8403}
8404
8405static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8406{
8407 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8408}
8409
8410static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8411 struct intel_crtc_state *crtc_state,
8412 u32 *fp,
8413 intel_clock_t *reduced_clock, u32 *fp2)
8414{
8415 struct drm_crtc *crtc = &intel_crtc->base;
8416 struct drm_device *dev = crtc->dev;
8417 struct drm_i915_private *dev_priv = dev->dev_private;
8418 struct drm_atomic_state *state = crtc_state->base.state;
8419 struct drm_connector *connector;
8420 struct drm_connector_state *connector_state;
8421 struct intel_encoder *encoder;
8422 uint32_t dpll;
8423 int factor, num_connectors = 0, i;
8424 bool is_lvds = false, is_sdvo = false;
8425
8426 for_each_connector_in_state(state, connector, connector_state, i) {
8427 if (connector_state->crtc != crtc_state->base.crtc)
8428 continue;
8429
8430 encoder = to_intel_encoder(connector_state->best_encoder);
8431
8432 switch (encoder->type) {
8433 case INTEL_OUTPUT_LVDS:
8434 is_lvds = true;
8435 break;
8436 case INTEL_OUTPUT_SDVO:
8437 case INTEL_OUTPUT_HDMI:
8438 is_sdvo = true;
8439 break;
8440 default:
8441 break;
8442 }
8443
8444 num_connectors++;
8445 }
8446
8447 /* Enable autotuning of the PLL clock (if permissible) */
8448 factor = 21;
8449 if (is_lvds) {
8450 if ((intel_panel_use_ssc(dev_priv) &&
8451 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8452 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8453 factor = 25;
8454 } else if (crtc_state->sdvo_tv_clock)
8455 factor = 20;
8456
8457 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8458 *fp |= FP_CB_TUNE;
8459
8460 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8461 *fp2 |= FP_CB_TUNE;
8462
8463 dpll = 0;
8464
8465 if (is_lvds)
8466 dpll |= DPLLB_MODE_LVDS;
8467 else
8468 dpll |= DPLLB_MODE_DAC_SERIAL;
8469
8470 dpll |= (crtc_state->pixel_multiplier - 1)
8471 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8472
8473 if (is_sdvo)
8474 dpll |= DPLL_SDVO_HIGH_SPEED;
8475 if (crtc_state->has_dp_encoder)
8476 dpll |= DPLL_SDVO_HIGH_SPEED;
8477
8478 /* compute bitmask from p1 value */
8479 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8480 /* also FPA1 */
8481 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8482
8483 switch (crtc_state->dpll.p2) {
8484 case 5:
8485 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8486 break;
8487 case 7:
8488 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8489 break;
8490 case 10:
8491 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8492 break;
8493 case 14:
8494 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8495 break;
8496 }
8497
8498 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8499 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8500 else
8501 dpll |= PLL_REF_INPUT_DREFCLK;
8502
8503 return dpll | DPLL_VCO_ENABLE;
8504}
8505
8506static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8507 struct intel_crtc_state *crtc_state)
8508{
8509 struct drm_device *dev = crtc->base.dev;
8510 intel_clock_t clock, reduced_clock;
8511 u32 dpll = 0, fp = 0, fp2 = 0;
8512 bool ok, has_reduced_clock = false;
8513 bool is_lvds = false;
8514 struct intel_shared_dpll *pll;
8515
8516 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8517
8518 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8519 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8520
8521 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8522 &has_reduced_clock, &reduced_clock);
8523 if (!ok && !crtc_state->clock_set) {
8524 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8525 return -EINVAL;
8526 }
8527 /* Compat-code for transition, will disappear. */
8528 if (!crtc_state->clock_set) {
8529 crtc_state->dpll.n = clock.n;
8530 crtc_state->dpll.m1 = clock.m1;
8531 crtc_state->dpll.m2 = clock.m2;
8532 crtc_state->dpll.p1 = clock.p1;
8533 crtc_state->dpll.p2 = clock.p2;
8534 }
8535
8536 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8537 if (crtc_state->has_pch_encoder) {
8538 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8539 if (has_reduced_clock)
8540 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8541
8542 dpll = ironlake_compute_dpll(crtc, crtc_state,
8543 &fp, &reduced_clock,
8544 has_reduced_clock ? &fp2 : NULL);
8545
8546 crtc_state->dpll_hw_state.dpll = dpll;
8547 crtc_state->dpll_hw_state.fp0 = fp;
8548 if (has_reduced_clock)
8549 crtc_state->dpll_hw_state.fp1 = fp2;
8550 else
8551 crtc_state->dpll_hw_state.fp1 = fp;
8552
8553 pll = intel_get_shared_dpll(crtc, crtc_state);
8554 if (pll == NULL) {
8555 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8556 pipe_name(crtc->pipe));
8557 return -EINVAL;
8558 }
8559 }
8560
8561 if (is_lvds && has_reduced_clock)
8562 crtc->lowfreq_avail = true;
8563 else
8564 crtc->lowfreq_avail = false;
8565
8566 return 0;
8567}
8568
8569static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8570 struct intel_link_m_n *m_n)
8571{
8572 struct drm_device *dev = crtc->base.dev;
8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574 enum pipe pipe = crtc->pipe;
8575
8576 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8577 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8578 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8579 & ~TU_SIZE_MASK;
8580 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8581 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8582 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8583}
8584
8585static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8586 enum transcoder transcoder,
8587 struct intel_link_m_n *m_n,
8588 struct intel_link_m_n *m2_n2)
8589{
8590 struct drm_device *dev = crtc->base.dev;
8591 struct drm_i915_private *dev_priv = dev->dev_private;
8592 enum pipe pipe = crtc->pipe;
8593
8594 if (INTEL_INFO(dev)->gen >= 5) {
8595 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8596 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8597 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8598 & ~TU_SIZE_MASK;
8599 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8600 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8601 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8602 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8603 * gen < 8) and if DRRS is supported (to make sure the
8604 * registers are not unnecessarily read).
8605 */
8606 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8607 crtc->config->has_drrs) {
8608 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8609 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8610 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8611 & ~TU_SIZE_MASK;
8612 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8613 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8614 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8615 }
8616 } else {
8617 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8618 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8619 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8620 & ~TU_SIZE_MASK;
8621 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8622 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8623 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8624 }
8625}
8626
8627void intel_dp_get_m_n(struct intel_crtc *crtc,
8628 struct intel_crtc_state *pipe_config)
8629{
8630 if (pipe_config->has_pch_encoder)
8631 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8632 else
8633 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8634 &pipe_config->dp_m_n,
8635 &pipe_config->dp_m2_n2);
8636}
8637
8638static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8639 struct intel_crtc_state *pipe_config)
8640{
8641 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8642 &pipe_config->fdi_m_n, NULL);
8643}
8644
8645static void skylake_get_pfit_config(struct intel_crtc *crtc,
8646 struct intel_crtc_state *pipe_config)
8647{
8648 struct drm_device *dev = crtc->base.dev;
8649 struct drm_i915_private *dev_priv = dev->dev_private;
8650 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8651 uint32_t ps_ctrl = 0;
8652 int id = -1;
8653 int i;
8654
8655 /* find scaler attached to this pipe */
8656 for (i = 0; i < crtc->num_scalers; i++) {
8657 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8658 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8659 id = i;
8660 pipe_config->pch_pfit.enabled = true;
8661 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8662 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8663 break;
8664 }
8665 }
8666
8667 scaler_state->scaler_id = id;
8668 if (id >= 0) {
8669 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8670 } else {
8671 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8672 }
8673}
8674
8675static void
8676skylake_get_initial_plane_config(struct intel_crtc *crtc,
8677 struct intel_initial_plane_config *plane_config)
8678{
8679 struct drm_device *dev = crtc->base.dev;
8680 struct drm_i915_private *dev_priv = dev->dev_private;
8681 u32 val, base, offset, stride_mult, tiling;
8682 int pipe = crtc->pipe;
8683 int fourcc, pixel_format;
8684 unsigned int aligned_height;
8685 struct drm_framebuffer *fb;
8686 struct intel_framebuffer *intel_fb;
8687
8688 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8689 if (!intel_fb) {
8690 DRM_DEBUG_KMS("failed to alloc fb\n");
8691 return;
8692 }
8693
8694 fb = &intel_fb->base;
8695
8696 val = I915_READ(PLANE_CTL(pipe, 0));
8697 if (!(val & PLANE_CTL_ENABLE))
8698 goto error;
8699
8700 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8701 fourcc = skl_format_to_fourcc(pixel_format,
8702 val & PLANE_CTL_ORDER_RGBX,
8703 val & PLANE_CTL_ALPHA_MASK);
8704 fb->pixel_format = fourcc;
8705 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8706
8707 tiling = val & PLANE_CTL_TILED_MASK;
8708 switch (tiling) {
8709 case PLANE_CTL_TILED_LINEAR:
8710 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8711 break;
8712 case PLANE_CTL_TILED_X:
8713 plane_config->tiling = I915_TILING_X;
8714 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8715 break;
8716 case PLANE_CTL_TILED_Y:
8717 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8718 break;
8719 case PLANE_CTL_TILED_YF:
8720 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8721 break;
8722 default:
8723 MISSING_CASE(tiling);
8724 goto error;
8725 }
8726
8727 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8728 plane_config->base = base;
8729
8730 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8731
8732 val = I915_READ(PLANE_SIZE(pipe, 0));
8733 fb->height = ((val >> 16) & 0xfff) + 1;
8734 fb->width = ((val >> 0) & 0x1fff) + 1;
8735
8736 val = I915_READ(PLANE_STRIDE(pipe, 0));
8737 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8738 fb->pixel_format);
8739 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8740
8741 aligned_height = intel_fb_align_height(dev, fb->height,
8742 fb->pixel_format,
8743 fb->modifier[0]);
8744
8745 plane_config->size = fb->pitches[0] * aligned_height;
8746
8747 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8748 pipe_name(pipe), fb->width, fb->height,
8749 fb->bits_per_pixel, base, fb->pitches[0],
8750 plane_config->size);
8751
8752 plane_config->fb = intel_fb;
8753 return;
8754
8755error:
8756 kfree(fb);
8757}
8758
8759static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8760 struct intel_crtc_state *pipe_config)
8761{
8762 struct drm_device *dev = crtc->base.dev;
8763 struct drm_i915_private *dev_priv = dev->dev_private;
8764 uint32_t tmp;
8765
8766 tmp = I915_READ(PF_CTL(crtc->pipe));
8767
8768 if (tmp & PF_ENABLE) {
8769 pipe_config->pch_pfit.enabled = true;
8770 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8771 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8772
8773 /* We currently do not free assignements of panel fitters on
8774 * ivb/hsw (since we don't use the higher upscaling modes which
8775 * differentiates them) so just WARN about this case for now. */
8776 if (IS_GEN7(dev)) {
8777 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8778 PF_PIPE_SEL_IVB(crtc->pipe));
8779 }
8780 }
8781}
8782
8783static void
8784ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8785 struct intel_initial_plane_config *plane_config)
8786{
8787 struct drm_device *dev = crtc->base.dev;
8788 struct drm_i915_private *dev_priv = dev->dev_private;
8789 u32 val, base, offset;
8790 int pipe = crtc->pipe;
8791 int fourcc, pixel_format;
8792 unsigned int aligned_height;
8793 struct drm_framebuffer *fb;
8794 struct intel_framebuffer *intel_fb;
8795
8796 val = I915_READ(DSPCNTR(pipe));
8797 if (!(val & DISPLAY_PLANE_ENABLE))
8798 return;
8799
8800 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8801 if (!intel_fb) {
8802 DRM_DEBUG_KMS("failed to alloc fb\n");
8803 return;
8804 }
8805
8806 fb = &intel_fb->base;
8807
8808 if (INTEL_INFO(dev)->gen >= 4) {
8809 if (val & DISPPLANE_TILED) {
8810 plane_config->tiling = I915_TILING_X;
8811 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8812 }
8813 }
8814
8815 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8816 fourcc = i9xx_format_to_fourcc(pixel_format);
8817 fb->pixel_format = fourcc;
8818 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8819
8820 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8821 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8822 offset = I915_READ(DSPOFFSET(pipe));
8823 } else {
8824 if (plane_config->tiling)
8825 offset = I915_READ(DSPTILEOFF(pipe));
8826 else
8827 offset = I915_READ(DSPLINOFF(pipe));
8828 }
8829 plane_config->base = base;
8830
8831 val = I915_READ(PIPESRC(pipe));
8832 fb->width = ((val >> 16) & 0xfff) + 1;
8833 fb->height = ((val >> 0) & 0xfff) + 1;
8834
8835 val = I915_READ(DSPSTRIDE(pipe));
8836 fb->pitches[0] = val & 0xffffffc0;
8837
8838 aligned_height = intel_fb_align_height(dev, fb->height,
8839 fb->pixel_format,
8840 fb->modifier[0]);
8841
8842 plane_config->size = fb->pitches[0] * aligned_height;
8843
8844 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8845 pipe_name(pipe), fb->width, fb->height,
8846 fb->bits_per_pixel, base, fb->pitches[0],
8847 plane_config->size);
8848
8849 plane_config->fb = intel_fb;
8850}
8851
8852static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8853 struct intel_crtc_state *pipe_config)
8854{
8855 struct drm_device *dev = crtc->base.dev;
8856 struct drm_i915_private *dev_priv = dev->dev_private;
8857 uint32_t tmp;
8858
8859 if (!intel_display_power_is_enabled(dev_priv,
8860 POWER_DOMAIN_PIPE(crtc->pipe)))
8861 return false;
8862
8863 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8864 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8865
8866 tmp = I915_READ(PIPECONF(crtc->pipe));
8867 if (!(tmp & PIPECONF_ENABLE))
8868 return false;
8869
8870 switch (tmp & PIPECONF_BPC_MASK) {
8871 case PIPECONF_6BPC:
8872 pipe_config->pipe_bpp = 18;
8873 break;
8874 case PIPECONF_8BPC:
8875 pipe_config->pipe_bpp = 24;
8876 break;
8877 case PIPECONF_10BPC:
8878 pipe_config->pipe_bpp = 30;
8879 break;
8880 case PIPECONF_12BPC:
8881 pipe_config->pipe_bpp = 36;
8882 break;
8883 default:
8884 break;
8885 }
8886
8887 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8888 pipe_config->limited_color_range = true;
8889
8890 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8891 struct intel_shared_dpll *pll;
8892
8893 pipe_config->has_pch_encoder = true;
8894
8895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8896 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8897 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8898
8899 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8900
8901 if (HAS_PCH_IBX(dev_priv->dev)) {
8902 pipe_config->shared_dpll =
8903 (enum intel_dpll_id) crtc->pipe;
8904 } else {
8905 tmp = I915_READ(PCH_DPLL_SEL);
8906 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8907 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8908 else
8909 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8910 }
8911
8912 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8913
8914 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8915 &pipe_config->dpll_hw_state));
8916
8917 tmp = pipe_config->dpll_hw_state.dpll;
8918 pipe_config->pixel_multiplier =
8919 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8920 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8921
8922 ironlake_pch_clock_get(crtc, pipe_config);
8923 } else {
8924 pipe_config->pixel_multiplier = 1;
8925 }
8926
8927 intel_get_pipe_timings(crtc, pipe_config);
8928
8929 ironlake_get_pfit_config(crtc, pipe_config);
8930
8931 return true;
8932}
8933
8934static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8935{
8936 struct drm_device *dev = dev_priv->dev;
8937 struct intel_crtc *crtc;
8938
8939 for_each_intel_crtc(dev, crtc)
8940 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8941 pipe_name(crtc->pipe));
8942
8943 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8944 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8945 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8946 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8947 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8948 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8949 "CPU PWM1 enabled\n");
8950 if (IS_HASWELL(dev))
8951 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8952 "CPU PWM2 enabled\n");
8953 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8954 "PCH PWM1 enabled\n");
8955 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8956 "Utility pin enabled\n");
8957 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8958
8959 /*
8960 * In theory we can still leave IRQs enabled, as long as only the HPD
8961 * interrupts remain enabled. We used to check for that, but since it's
8962 * gen-specific and since we only disable LCPLL after we fully disable
8963 * the interrupts, the check below should be enough.
8964 */
8965 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8966}
8967
8968static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8969{
8970 struct drm_device *dev = dev_priv->dev;
8971
8972 if (IS_HASWELL(dev))
8973 return I915_READ(D_COMP_HSW);
8974 else
8975 return I915_READ(D_COMP_BDW);
8976}
8977
8978static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8979{
8980 struct drm_device *dev = dev_priv->dev;
8981
8982 if (IS_HASWELL(dev)) {
8983 mutex_lock(&dev_priv->rps.hw_lock);
8984 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8985 val))
8986 DRM_ERROR("Failed to write to D_COMP\n");
8987 mutex_unlock(&dev_priv->rps.hw_lock);
8988 } else {
8989 I915_WRITE(D_COMP_BDW, val);
8990 POSTING_READ(D_COMP_BDW);
8991 }
8992}
8993
8994/*
8995 * This function implements pieces of two sequences from BSpec:
8996 * - Sequence for display software to disable LCPLL
8997 * - Sequence for display software to allow package C8+
8998 * The steps implemented here are just the steps that actually touch the LCPLL
8999 * register. Callers should take care of disabling all the display engine
9000 * functions, doing the mode unset, fixing interrupts, etc.
9001 */
9002static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9003 bool switch_to_fclk, bool allow_power_down)
9004{
9005 uint32_t val;
9006
9007 assert_can_disable_lcpll(dev_priv);
9008
9009 val = I915_READ(LCPLL_CTL);
9010
9011 if (switch_to_fclk) {
9012 val |= LCPLL_CD_SOURCE_FCLK;
9013 I915_WRITE(LCPLL_CTL, val);
9014
9015 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9016 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9017 DRM_ERROR("Switching to FCLK failed\n");
9018
9019 val = I915_READ(LCPLL_CTL);
9020 }
9021
9022 val |= LCPLL_PLL_DISABLE;
9023 I915_WRITE(LCPLL_CTL, val);
9024 POSTING_READ(LCPLL_CTL);
9025
9026 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9027 DRM_ERROR("LCPLL still locked\n");
9028
9029 val = hsw_read_dcomp(dev_priv);
9030 val |= D_COMP_COMP_DISABLE;
9031 hsw_write_dcomp(dev_priv, val);
9032 ndelay(100);
9033
9034 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9035 1))
9036 DRM_ERROR("D_COMP RCOMP still in progress\n");
9037
9038 if (allow_power_down) {
9039 val = I915_READ(LCPLL_CTL);
9040 val |= LCPLL_POWER_DOWN_ALLOW;
9041 I915_WRITE(LCPLL_CTL, val);
9042 POSTING_READ(LCPLL_CTL);
9043 }
9044}
9045
9046/*
9047 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9048 * source.
9049 */
9050static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9051{
9052 uint32_t val;
9053
9054 val = I915_READ(LCPLL_CTL);
9055
9056 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9057 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9058 return;
9059
9060 /*
9061 * Make sure we're not on PC8 state before disabling PC8, otherwise
9062 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9063 */
9064 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9065
9066 if (val & LCPLL_POWER_DOWN_ALLOW) {
9067 val &= ~LCPLL_POWER_DOWN_ALLOW;
9068 I915_WRITE(LCPLL_CTL, val);
9069 POSTING_READ(LCPLL_CTL);
9070 }
9071
9072 val = hsw_read_dcomp(dev_priv);
9073 val |= D_COMP_COMP_FORCE;
9074 val &= ~D_COMP_COMP_DISABLE;
9075 hsw_write_dcomp(dev_priv, val);
9076
9077 val = I915_READ(LCPLL_CTL);
9078 val &= ~LCPLL_PLL_DISABLE;
9079 I915_WRITE(LCPLL_CTL, val);
9080
9081 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9082 DRM_ERROR("LCPLL not locked yet\n");
9083
9084 if (val & LCPLL_CD_SOURCE_FCLK) {
9085 val = I915_READ(LCPLL_CTL);
9086 val &= ~LCPLL_CD_SOURCE_FCLK;
9087 I915_WRITE(LCPLL_CTL, val);
9088
9089 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9090 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9091 DRM_ERROR("Switching back to LCPLL failed\n");
9092 }
9093
9094 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9095}
9096
9097/*
9098 * Package states C8 and deeper are really deep PC states that can only be
9099 * reached when all the devices on the system allow it, so even if the graphics
9100 * device allows PC8+, it doesn't mean the system will actually get to these
9101 * states. Our driver only allows PC8+ when going into runtime PM.
9102 *
9103 * The requirements for PC8+ are that all the outputs are disabled, the power
9104 * well is disabled and most interrupts are disabled, and these are also
9105 * requirements for runtime PM. When these conditions are met, we manually do
9106 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9107 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9108 * hang the machine.
9109 *
9110 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9111 * the state of some registers, so when we come back from PC8+ we need to
9112 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9113 * need to take care of the registers kept by RC6. Notice that this happens even
9114 * if we don't put the device in PCI D3 state (which is what currently happens
9115 * because of the runtime PM support).
9116 *
9117 * For more, read "Display Sequences for Package C8" on the hardware
9118 * documentation.
9119 */
9120void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9121{
9122 struct drm_device *dev = dev_priv->dev;
9123 uint32_t val;
9124
9125 DRM_DEBUG_KMS("Enabling package C8+\n");
9126
9127 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9128 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9129 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9130 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9131 }
9132
9133 lpt_disable_clkout_dp(dev);
9134 hsw_disable_lcpll(dev_priv, true, true);
9135}
9136
9137void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9138{
9139 struct drm_device *dev = dev_priv->dev;
9140 uint32_t val;
9141
9142 DRM_DEBUG_KMS("Disabling package C8+\n");
9143
9144 hsw_restore_lcpll(dev_priv);
9145 lpt_init_pch_refclk(dev);
9146
9147 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9148 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9149 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9150 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9151 }
9152
9153 intel_prepare_ddi(dev);
9154}
9155
9156static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9157{
9158 struct drm_device *dev = state->dev;
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 int max_pixclk = intel_mode_max_pixclk(state);
9161 int req_cdclk;
9162
9163 /* see the comment in valleyview_modeset_global_resources */
9164 if (WARN_ON(max_pixclk < 0))
9165 return;
9166
9167 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9168
9169 if (req_cdclk != dev_priv->cdclk_freq)
9170 broxton_set_cdclk(dev, req_cdclk);
9171}
9172
9173static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9174 struct intel_crtc_state *crtc_state)
9175{
9176 if (!intel_ddi_pll_select(crtc, crtc_state))
9177 return -EINVAL;
9178
9179 crtc->lowfreq_avail = false;
9180
9181 return 0;
9182}
9183
9184static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9185 enum port port,
9186 struct intel_crtc_state *pipe_config)
9187{
9188 switch (port) {
9189 case PORT_A:
9190 pipe_config->ddi_pll_sel = SKL_DPLL0;
9191 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9192 break;
9193 case PORT_B:
9194 pipe_config->ddi_pll_sel = SKL_DPLL1;
9195 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9196 break;
9197 case PORT_C:
9198 pipe_config->ddi_pll_sel = SKL_DPLL2;
9199 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9200 break;
9201 default:
9202 DRM_ERROR("Incorrect port type\n");
9203 }
9204}
9205
9206static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9207 enum port port,
9208 struct intel_crtc_state *pipe_config)
9209{
9210 u32 temp, dpll_ctl1;
9211
9212 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9213 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9214
9215 switch (pipe_config->ddi_pll_sel) {
9216 case SKL_DPLL0:
9217 /*
9218 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9219 * of the shared DPLL framework and thus needs to be read out
9220 * separately
9221 */
9222 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9223 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9224 break;
9225 case SKL_DPLL1:
9226 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9227 break;
9228 case SKL_DPLL2:
9229 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9230 break;
9231 case SKL_DPLL3:
9232 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9233 break;
9234 }
9235}
9236
9237static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9238 enum port port,
9239 struct intel_crtc_state *pipe_config)
9240{
9241 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9242
9243 switch (pipe_config->ddi_pll_sel) {
9244 case PORT_CLK_SEL_WRPLL1:
9245 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9246 break;
9247 case PORT_CLK_SEL_WRPLL2:
9248 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9249 break;
9250 }
9251}
9252
9253static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9254 struct intel_crtc_state *pipe_config)
9255{
9256 struct drm_device *dev = crtc->base.dev;
9257 struct drm_i915_private *dev_priv = dev->dev_private;
9258 struct intel_shared_dpll *pll;
9259 enum port port;
9260 uint32_t tmp;
9261
9262 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9263
9264 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9265
9266 if (IS_SKYLAKE(dev))
9267 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9268 else if (IS_BROXTON(dev))
9269 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9270 else
9271 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9272
9273 if (pipe_config->shared_dpll >= 0) {
9274 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9275
9276 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9277 &pipe_config->dpll_hw_state));
9278 }
9279
9280 /*
9281 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9282 * DDI E. So just check whether this pipe is wired to DDI E and whether
9283 * the PCH transcoder is on.
9284 */
9285 if (INTEL_INFO(dev)->gen < 9 &&
9286 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9287 pipe_config->has_pch_encoder = true;
9288
9289 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9290 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9291 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9292
9293 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9294 }
9295}
9296
9297static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9298 struct intel_crtc_state *pipe_config)
9299{
9300 struct drm_device *dev = crtc->base.dev;
9301 struct drm_i915_private *dev_priv = dev->dev_private;
9302 enum intel_display_power_domain pfit_domain;
9303 uint32_t tmp;
9304
9305 if (!intel_display_power_is_enabled(dev_priv,
9306 POWER_DOMAIN_PIPE(crtc->pipe)))
9307 return false;
9308
9309 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9310 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9311
9312 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9313 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9314 enum pipe trans_edp_pipe;
9315 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9316 default:
9317 WARN(1, "unknown pipe linked to edp transcoder\n");
9318 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9319 case TRANS_DDI_EDP_INPUT_A_ON:
9320 trans_edp_pipe = PIPE_A;
9321 break;
9322 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9323 trans_edp_pipe = PIPE_B;
9324 break;
9325 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9326 trans_edp_pipe = PIPE_C;
9327 break;
9328 }
9329
9330 if (trans_edp_pipe == crtc->pipe)
9331 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9332 }
9333
9334 if (!intel_display_power_is_enabled(dev_priv,
9335 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9336 return false;
9337
9338 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9339 if (!(tmp & PIPECONF_ENABLE))
9340 return false;
9341
9342 haswell_get_ddi_port_state(crtc, pipe_config);
9343
9344 intel_get_pipe_timings(crtc, pipe_config);
9345
9346 if (INTEL_INFO(dev)->gen >= 9) {
9347 skl_init_scalers(dev, crtc, pipe_config);
9348 }
9349
9350 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9351 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9352 if (INTEL_INFO(dev)->gen == 9)
9353 skylake_get_pfit_config(crtc, pipe_config);
9354 else if (INTEL_INFO(dev)->gen < 9)
9355 ironlake_get_pfit_config(crtc, pipe_config);
9356 else
9357 MISSING_CASE(INTEL_INFO(dev)->gen);
9358
9359 } else {
9360 pipe_config->scaler_state.scaler_id = -1;
9361 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9362 }
9363
9364 if (IS_HASWELL(dev))
9365 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9366 (I915_READ(IPS_CTL) & IPS_ENABLE);
9367
9368 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9369 pipe_config->pixel_multiplier =
9370 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9371 } else {
9372 pipe_config->pixel_multiplier = 1;
9373 }
9374
9375 return true;
9376}
9377
9378static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9379{
9380 struct drm_device *dev = crtc->dev;
9381 struct drm_i915_private *dev_priv = dev->dev_private;
9382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9383 uint32_t cntl = 0, size = 0;
9384
9385 if (base) {
9386 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9387 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9388 unsigned int stride = roundup_pow_of_two(width) * 4;
9389
9390 switch (stride) {
9391 default:
9392 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9393 width, stride);
9394 stride = 256;
9395 /* fallthrough */
9396 case 256:
9397 case 512:
9398 case 1024:
9399 case 2048:
9400 break;
9401 }
9402
9403 cntl |= CURSOR_ENABLE |
9404 CURSOR_GAMMA_ENABLE |
9405 CURSOR_FORMAT_ARGB |
9406 CURSOR_STRIDE(stride);
9407
9408 size = (height << 12) | width;
9409 }
9410
9411 if (intel_crtc->cursor_cntl != 0 &&
9412 (intel_crtc->cursor_base != base ||
9413 intel_crtc->cursor_size != size ||
9414 intel_crtc->cursor_cntl != cntl)) {
9415 /* On these chipsets we can only modify the base/size/stride
9416 * whilst the cursor is disabled.
9417 */
9418 I915_WRITE(_CURACNTR, 0);
9419 POSTING_READ(_CURACNTR);
9420 intel_crtc->cursor_cntl = 0;
9421 }
9422
9423 if (intel_crtc->cursor_base != base) {
9424 I915_WRITE(_CURABASE, base);
9425 intel_crtc->cursor_base = base;
9426 }
9427
9428 if (intel_crtc->cursor_size != size) {
9429 I915_WRITE(CURSIZE, size);
9430 intel_crtc->cursor_size = size;
9431 }
9432
9433 if (intel_crtc->cursor_cntl != cntl) {
9434 I915_WRITE(_CURACNTR, cntl);
9435 POSTING_READ(_CURACNTR);
9436 intel_crtc->cursor_cntl = cntl;
9437 }
9438}
9439
9440static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9441{
9442 struct drm_device *dev = crtc->dev;
9443 struct drm_i915_private *dev_priv = dev->dev_private;
9444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9445 int pipe = intel_crtc->pipe;
9446 uint32_t cntl;
9447
9448 cntl = 0;
9449 if (base) {
9450 cntl = MCURSOR_GAMMA_ENABLE;
9451 switch (intel_crtc->base.cursor->state->crtc_w) {
9452 case 64:
9453 cntl |= CURSOR_MODE_64_ARGB_AX;
9454 break;
9455 case 128:
9456 cntl |= CURSOR_MODE_128_ARGB_AX;
9457 break;
9458 case 256:
9459 cntl |= CURSOR_MODE_256_ARGB_AX;
9460 break;
9461 default:
9462 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9463 return;
9464 }
9465 cntl |= pipe << 28; /* Connect to correct pipe */
9466
9467 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9468 cntl |= CURSOR_PIPE_CSC_ENABLE;
9469 }
9470
9471 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9472 cntl |= CURSOR_ROTATE_180;
9473
9474 if (intel_crtc->cursor_cntl != cntl) {
9475 I915_WRITE(CURCNTR(pipe), cntl);
9476 POSTING_READ(CURCNTR(pipe));
9477 intel_crtc->cursor_cntl = cntl;
9478 }
9479
9480 /* and commit changes on next vblank */
9481 I915_WRITE(CURBASE(pipe), base);
9482 POSTING_READ(CURBASE(pipe));
9483
9484 intel_crtc->cursor_base = base;
9485}
9486
9487/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9488static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9489 bool on)
9490{
9491 struct drm_device *dev = crtc->dev;
9492 struct drm_i915_private *dev_priv = dev->dev_private;
9493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9494 int pipe = intel_crtc->pipe;
9495 int x = crtc->cursor_x;
9496 int y = crtc->cursor_y;
9497 u32 base = 0, pos = 0;
9498
9499 if (on)
9500 base = intel_crtc->cursor_addr;
9501
9502 if (x >= intel_crtc->config->pipe_src_w)
9503 base = 0;
9504
9505 if (y >= intel_crtc->config->pipe_src_h)
9506 base = 0;
9507
9508 if (x < 0) {
9509 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9510 base = 0;
9511
9512 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9513 x = -x;
9514 }
9515 pos |= x << CURSOR_X_SHIFT;
9516
9517 if (y < 0) {
9518 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9519 base = 0;
9520
9521 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9522 y = -y;
9523 }
9524 pos |= y << CURSOR_Y_SHIFT;
9525
9526 if (base == 0 && intel_crtc->cursor_base == 0)
9527 return;
9528
9529 I915_WRITE(CURPOS(pipe), pos);
9530
9531 /* ILK+ do this automagically */
9532 if (HAS_GMCH_DISPLAY(dev) &&
9533 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9534 base += (intel_crtc->base.cursor->state->crtc_h *
9535 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9536 }
9537
9538 if (IS_845G(dev) || IS_I865G(dev))
9539 i845_update_cursor(crtc, base);
9540 else
9541 i9xx_update_cursor(crtc, base);
9542}
9543
9544static bool cursor_size_ok(struct drm_device *dev,
9545 uint32_t width, uint32_t height)
9546{
9547 if (width == 0 || height == 0)
9548 return false;
9549
9550 /*
9551 * 845g/865g are special in that they are only limited by
9552 * the width of their cursors, the height is arbitrary up to
9553 * the precision of the register. Everything else requires
9554 * square cursors, limited to a few power-of-two sizes.
9555 */
9556 if (IS_845G(dev) || IS_I865G(dev)) {
9557 if ((width & 63) != 0)
9558 return false;
9559
9560 if (width > (IS_845G(dev) ? 64 : 512))
9561 return false;
9562
9563 if (height > 1023)
9564 return false;
9565 } else {
9566 switch (width | height) {
9567 case 256:
9568 case 128:
9569 if (IS_GEN2(dev))
9570 return false;
9571 case 64:
9572 break;
9573 default:
9574 return false;
9575 }
9576 }
9577
9578 return true;
9579}
9580
9581static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9582 u16 *blue, uint32_t start, uint32_t size)
9583{
9584 int end = (start + size > 256) ? 256 : start + size, i;
9585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9586
9587 for (i = start; i < end; i++) {
9588 intel_crtc->lut_r[i] = red[i] >> 8;
9589 intel_crtc->lut_g[i] = green[i] >> 8;
9590 intel_crtc->lut_b[i] = blue[i] >> 8;
9591 }
9592
9593 intel_crtc_load_lut(crtc);
9594}
9595
9596/* VESA 640x480x72Hz mode to set on the pipe */
9597static struct drm_display_mode load_detect_mode = {
9598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9600};
9601
9602struct drm_framebuffer *
9603__intel_framebuffer_create(struct drm_device *dev,
9604 struct drm_mode_fb_cmd2 *mode_cmd,
9605 struct drm_i915_gem_object *obj)
9606{
9607 struct intel_framebuffer *intel_fb;
9608 int ret;
9609
9610 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9611 if (!intel_fb) {
9612 drm_gem_object_unreference(&obj->base);
9613 return ERR_PTR(-ENOMEM);
9614 }
9615
9616 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9617 if (ret)
9618 goto err;
9619
9620 return &intel_fb->base;
9621err:
9622 drm_gem_object_unreference(&obj->base);
9623 kfree(intel_fb);
9624
9625 return ERR_PTR(ret);
9626}
9627
9628static struct drm_framebuffer *
9629intel_framebuffer_create(struct drm_device *dev,
9630 struct drm_mode_fb_cmd2 *mode_cmd,
9631 struct drm_i915_gem_object *obj)
9632{
9633 struct drm_framebuffer *fb;
9634 int ret;
9635
9636 ret = i915_mutex_lock_interruptible(dev);
9637 if (ret)
9638 return ERR_PTR(ret);
9639 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9640 mutex_unlock(&dev->struct_mutex);
9641
9642 return fb;
9643}
9644
9645static u32
9646intel_framebuffer_pitch_for_width(int width, int bpp)
9647{
9648 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9649 return ALIGN(pitch, 64);
9650}
9651
9652static u32
9653intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9654{
9655 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9656 return PAGE_ALIGN(pitch * mode->vdisplay);
9657}
9658
9659static struct drm_framebuffer *
9660intel_framebuffer_create_for_mode(struct drm_device *dev,
9661 struct drm_display_mode *mode,
9662 int depth, int bpp)
9663{
9664 struct drm_i915_gem_object *obj;
9665 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9666
9667 obj = i915_gem_alloc_object(dev,
9668 intel_framebuffer_size_for_mode(mode, bpp));
9669 if (obj == NULL)
9670 return ERR_PTR(-ENOMEM);
9671
9672 mode_cmd.width = mode->hdisplay;
9673 mode_cmd.height = mode->vdisplay;
9674 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9675 bpp);
9676 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9677
9678 return intel_framebuffer_create(dev, &mode_cmd, obj);
9679}
9680
9681static struct drm_framebuffer *
9682mode_fits_in_fbdev(struct drm_device *dev,
9683 struct drm_display_mode *mode)
9684{
9685#ifdef CONFIG_DRM_I915_FBDEV
9686 struct drm_i915_private *dev_priv = dev->dev_private;
9687 struct drm_i915_gem_object *obj;
9688 struct drm_framebuffer *fb;
9689
9690 if (!dev_priv->fbdev)
9691 return NULL;
9692
9693 if (!dev_priv->fbdev->fb)
9694 return NULL;
9695
9696 obj = dev_priv->fbdev->fb->obj;
9697 BUG_ON(!obj);
9698
9699 fb = &dev_priv->fbdev->fb->base;
9700 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9701 fb->bits_per_pixel))
9702 return NULL;
9703
9704 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9705 return NULL;
9706
9707 return fb;
9708#else
9709 return NULL;
9710#endif
9711}
9712
9713bool intel_get_load_detect_pipe(struct drm_connector *connector,
9714 struct drm_display_mode *mode,
9715 struct intel_load_detect_pipe *old,
9716 struct drm_modeset_acquire_ctx *ctx)
9717{
9718 struct intel_crtc *intel_crtc;
9719 struct intel_encoder *intel_encoder =
9720 intel_attached_encoder(connector);
9721 struct drm_crtc *possible_crtc;
9722 struct drm_encoder *encoder = &intel_encoder->base;
9723 struct drm_crtc *crtc = NULL;
9724 struct drm_device *dev = encoder->dev;
9725 struct drm_framebuffer *fb;
9726 struct drm_mode_config *config = &dev->mode_config;
9727 struct drm_atomic_state *state = NULL;
9728 struct drm_connector_state *connector_state;
9729 struct intel_crtc_state *crtc_state;
9730 int ret, i = -1;
9731
9732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9733 connector->base.id, connector->name,
9734 encoder->base.id, encoder->name);
9735
9736retry:
9737 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9738 if (ret)
9739 goto fail_unlock;
9740
9741 /*
9742 * Algorithm gets a little messy:
9743 *
9744 * - if the connector already has an assigned crtc, use it (but make
9745 * sure it's on first)
9746 *
9747 * - try to find the first unused crtc that can drive this connector,
9748 * and use that if we find one
9749 */
9750
9751 /* See if we already have a CRTC for this connector */
9752 if (encoder->crtc) {
9753 crtc = encoder->crtc;
9754
9755 ret = drm_modeset_lock(&crtc->mutex, ctx);
9756 if (ret)
9757 goto fail_unlock;
9758 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9759 if (ret)
9760 goto fail_unlock;
9761
9762 old->dpms_mode = connector->dpms;
9763 old->load_detect_temp = false;
9764
9765 /* Make sure the crtc and connector are running */
9766 if (connector->dpms != DRM_MODE_DPMS_ON)
9767 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9768
9769 return true;
9770 }
9771
9772 /* Find an unused one (if possible) */
9773 for_each_crtc(dev, possible_crtc) {
9774 i++;
9775 if (!(encoder->possible_crtcs & (1 << i)))
9776 continue;
9777 if (possible_crtc->state->enable)
9778 continue;
9779 /* This can occur when applying the pipe A quirk on resume. */
9780 if (to_intel_crtc(possible_crtc)->new_enabled)
9781 continue;
9782
9783 crtc = possible_crtc;
9784 break;
9785 }
9786
9787 /*
9788 * If we didn't find an unused CRTC, don't use any.
9789 */
9790 if (!crtc) {
9791 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9792 goto fail_unlock;
9793 }
9794
9795 ret = drm_modeset_lock(&crtc->mutex, ctx);
9796 if (ret)
9797 goto fail_unlock;
9798 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9799 if (ret)
9800 goto fail_unlock;
9801 intel_encoder->new_crtc = to_intel_crtc(crtc);
9802 to_intel_connector(connector)->new_encoder = intel_encoder;
9803
9804 intel_crtc = to_intel_crtc(crtc);
9805 intel_crtc->new_enabled = true;
9806 old->dpms_mode = connector->dpms;
9807 old->load_detect_temp = true;
9808 old->release_fb = NULL;
9809
9810 state = drm_atomic_state_alloc(dev);
9811 if (!state)
9812 return false;
9813
9814 state->acquire_ctx = ctx;
9815
9816 connector_state = drm_atomic_get_connector_state(state, connector);
9817 if (IS_ERR(connector_state)) {
9818 ret = PTR_ERR(connector_state);
9819 goto fail;
9820 }
9821
9822 connector_state->crtc = crtc;
9823 connector_state->best_encoder = &intel_encoder->base;
9824
9825 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9826 if (IS_ERR(crtc_state)) {
9827 ret = PTR_ERR(crtc_state);
9828 goto fail;
9829 }
9830
9831 crtc_state->base.enable = true;
9832
9833 if (!mode)
9834 mode = &load_detect_mode;
9835
9836 /* We need a framebuffer large enough to accommodate all accesses
9837 * that the plane may generate whilst we perform load detection.
9838 * We can not rely on the fbcon either being present (we get called
9839 * during its initialisation to detect all boot displays, or it may
9840 * not even exist) or that it is large enough to satisfy the
9841 * requested mode.
9842 */
9843 fb = mode_fits_in_fbdev(dev, mode);
9844 if (fb == NULL) {
9845 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9846 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9847 old->release_fb = fb;
9848 } else
9849 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9850 if (IS_ERR(fb)) {
9851 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9852 goto fail;
9853 }
9854
9855 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
9856 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9857 if (old->release_fb)
9858 old->release_fb->funcs->destroy(old->release_fb);
9859 goto fail;
9860 }
9861 crtc->primary->crtc = crtc;
9862
9863 /* let the connector get through one full cycle before testing */
9864 intel_wait_for_vblank(dev, intel_crtc->pipe);
9865 return true;
9866
9867 fail:
9868 intel_crtc->new_enabled = crtc->state->enable;
9869fail_unlock:
9870 drm_atomic_state_free(state);
9871 state = NULL;
9872
9873 if (ret == -EDEADLK) {
9874 drm_modeset_backoff(ctx);
9875 goto retry;
9876 }
9877
9878 return false;
9879}
9880
9881void intel_release_load_detect_pipe(struct drm_connector *connector,
9882 struct intel_load_detect_pipe *old,
9883 struct drm_modeset_acquire_ctx *ctx)
9884{
9885 struct drm_device *dev = connector->dev;
9886 struct intel_encoder *intel_encoder =
9887 intel_attached_encoder(connector);
9888 struct drm_encoder *encoder = &intel_encoder->base;
9889 struct drm_crtc *crtc = encoder->crtc;
9890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9891 struct drm_atomic_state *state;
9892 struct drm_connector_state *connector_state;
9893 struct intel_crtc_state *crtc_state;
9894
9895 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9896 connector->base.id, connector->name,
9897 encoder->base.id, encoder->name);
9898
9899 if (old->load_detect_temp) {
9900 state = drm_atomic_state_alloc(dev);
9901 if (!state)
9902 goto fail;
9903
9904 state->acquire_ctx = ctx;
9905
9906 connector_state = drm_atomic_get_connector_state(state, connector);
9907 if (IS_ERR(connector_state))
9908 goto fail;
9909
9910 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9911 if (IS_ERR(crtc_state))
9912 goto fail;
9913
9914 to_intel_connector(connector)->new_encoder = NULL;
9915 intel_encoder->new_crtc = NULL;
9916 intel_crtc->new_enabled = false;
9917
9918 connector_state->best_encoder = NULL;
9919 connector_state->crtc = NULL;
9920
9921 crtc_state->base.enable = false;
9922
9923 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9924
9925 drm_atomic_state_free(state);
9926
9927 if (old->release_fb) {
9928 drm_framebuffer_unregister_private(old->release_fb);
9929 drm_framebuffer_unreference(old->release_fb);
9930 }
9931
9932 return;
9933 }
9934
9935 /* Switch crtc and encoder back off if necessary */
9936 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9937 connector->funcs->dpms(connector, old->dpms_mode);
9938
9939 return;
9940fail:
9941 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9942 drm_atomic_state_free(state);
9943}
9944
9945static int i9xx_pll_refclk(struct drm_device *dev,
9946 const struct intel_crtc_state *pipe_config)
9947{
9948 struct drm_i915_private *dev_priv = dev->dev_private;
9949 u32 dpll = pipe_config->dpll_hw_state.dpll;
9950
9951 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9952 return dev_priv->vbt.lvds_ssc_freq;
9953 else if (HAS_PCH_SPLIT(dev))
9954 return 120000;
9955 else if (!IS_GEN2(dev))
9956 return 96000;
9957 else
9958 return 48000;
9959}
9960
9961/* Returns the clock of the currently programmed mode of the given pipe. */
9962static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9963 struct intel_crtc_state *pipe_config)
9964{
9965 struct drm_device *dev = crtc->base.dev;
9966 struct drm_i915_private *dev_priv = dev->dev_private;
9967 int pipe = pipe_config->cpu_transcoder;
9968 u32 dpll = pipe_config->dpll_hw_state.dpll;
9969 u32 fp;
9970 intel_clock_t clock;
9971 int refclk = i9xx_pll_refclk(dev, pipe_config);
9972
9973 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9974 fp = pipe_config->dpll_hw_state.fp0;
9975 else
9976 fp = pipe_config->dpll_hw_state.fp1;
9977
9978 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9979 if (IS_PINEVIEW(dev)) {
9980 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9981 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9982 } else {
9983 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9984 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9985 }
9986
9987 if (!IS_GEN2(dev)) {
9988 if (IS_PINEVIEW(dev))
9989 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9990 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9991 else
9992 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9993 DPLL_FPA01_P1_POST_DIV_SHIFT);
9994
9995 switch (dpll & DPLL_MODE_MASK) {
9996 case DPLLB_MODE_DAC_SERIAL:
9997 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9998 5 : 10;
9999 break;
10000 case DPLLB_MODE_LVDS:
10001 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10002 7 : 14;
10003 break;
10004 default:
10005 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10006 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10007 return;
10008 }
10009
10010 if (IS_PINEVIEW(dev))
10011 pineview_clock(refclk, &clock);
10012 else
10013 i9xx_clock(refclk, &clock);
10014 } else {
10015 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10016 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10017
10018 if (is_lvds) {
10019 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10020 DPLL_FPA01_P1_POST_DIV_SHIFT);
10021
10022 if (lvds & LVDS_CLKB_POWER_UP)
10023 clock.p2 = 7;
10024 else
10025 clock.p2 = 14;
10026 } else {
10027 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10028 clock.p1 = 2;
10029 else {
10030 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10031 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10032 }
10033 if (dpll & PLL_P2_DIVIDE_BY_4)
10034 clock.p2 = 4;
10035 else
10036 clock.p2 = 2;
10037 }
10038
10039 i9xx_clock(refclk, &clock);
10040 }
10041
10042 /*
10043 * This value includes pixel_multiplier. We will use
10044 * port_clock to compute adjusted_mode.crtc_clock in the
10045 * encoder's get_config() function.
10046 */
10047 pipe_config->port_clock = clock.dot;
10048}
10049
10050int intel_dotclock_calculate(int link_freq,
10051 const struct intel_link_m_n *m_n)
10052{
10053 /*
10054 * The calculation for the data clock is:
10055 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10056 * But we want to avoid losing precison if possible, so:
10057 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10058 *
10059 * and the link clock is simpler:
10060 * link_clock = (m * link_clock) / n
10061 */
10062
10063 if (!m_n->link_n)
10064 return 0;
10065
10066 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10067}
10068
10069static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10070 struct intel_crtc_state *pipe_config)
10071{
10072 struct drm_device *dev = crtc->base.dev;
10073
10074 /* read out port_clock from the DPLL */
10075 i9xx_crtc_clock_get(crtc, pipe_config);
10076
10077 /*
10078 * This value does not include pixel_multiplier.
10079 * We will check that port_clock and adjusted_mode.crtc_clock
10080 * agree once we know their relationship in the encoder's
10081 * get_config() function.
10082 */
10083 pipe_config->base.adjusted_mode.crtc_clock =
10084 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10085 &pipe_config->fdi_m_n);
10086}
10087
10088/** Returns the currently programmed mode of the given pipe. */
10089struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10090 struct drm_crtc *crtc)
10091{
10092 struct drm_i915_private *dev_priv = dev->dev_private;
10093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10094 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10095 struct drm_display_mode *mode;
10096 struct intel_crtc_state pipe_config;
10097 int htot = I915_READ(HTOTAL(cpu_transcoder));
10098 int hsync = I915_READ(HSYNC(cpu_transcoder));
10099 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10100 int vsync = I915_READ(VSYNC(cpu_transcoder));
10101 enum pipe pipe = intel_crtc->pipe;
10102
10103 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10104 if (!mode)
10105 return NULL;
10106
10107 /*
10108 * Construct a pipe_config sufficient for getting the clock info
10109 * back out of crtc_clock_get.
10110 *
10111 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10112 * to use a real value here instead.
10113 */
10114 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10115 pipe_config.pixel_multiplier = 1;
10116 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10117 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10118 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10119 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10120
10121 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10122 mode->hdisplay = (htot & 0xffff) + 1;
10123 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10124 mode->hsync_start = (hsync & 0xffff) + 1;
10125 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10126 mode->vdisplay = (vtot & 0xffff) + 1;
10127 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10128 mode->vsync_start = (vsync & 0xffff) + 1;
10129 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10130
10131 drm_mode_set_name(mode);
10132
10133 return mode;
10134}
10135
10136static void intel_decrease_pllclock(struct drm_crtc *crtc)
10137{
10138 struct drm_device *dev = crtc->dev;
10139 struct drm_i915_private *dev_priv = dev->dev_private;
10140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10141
10142 if (!HAS_GMCH_DISPLAY(dev))
10143 return;
10144
10145 if (!dev_priv->lvds_downclock_avail)
10146 return;
10147
10148 /*
10149 * Since this is called by a timer, we should never get here in
10150 * the manual case.
10151 */
10152 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10153 int pipe = intel_crtc->pipe;
10154 int dpll_reg = DPLL(pipe);
10155 int dpll;
10156
10157 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10158
10159 assert_panel_unlocked(dev_priv, pipe);
10160
10161 dpll = I915_READ(dpll_reg);
10162 dpll |= DISPLAY_RATE_SELECT_FPA1;
10163 I915_WRITE(dpll_reg, dpll);
10164 intel_wait_for_vblank(dev, pipe);
10165 dpll = I915_READ(dpll_reg);
10166 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10167 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10168 }
10169
10170}
10171
10172void intel_mark_busy(struct drm_device *dev)
10173{
10174 struct drm_i915_private *dev_priv = dev->dev_private;
10175
10176 if (dev_priv->mm.busy)
10177 return;
10178
10179 intel_runtime_pm_get(dev_priv);
10180 i915_update_gfx_val(dev_priv);
10181 if (INTEL_INFO(dev)->gen >= 6)
10182 gen6_rps_busy(dev_priv);
10183 dev_priv->mm.busy = true;
10184}
10185
10186void intel_mark_idle(struct drm_device *dev)
10187{
10188 struct drm_i915_private *dev_priv = dev->dev_private;
10189 struct drm_crtc *crtc;
10190
10191 if (!dev_priv->mm.busy)
10192 return;
10193
10194 dev_priv->mm.busy = false;
10195
10196 for_each_crtc(dev, crtc) {
10197 if (!crtc->primary->fb)
10198 continue;
10199
10200 intel_decrease_pllclock(crtc);
10201 }
10202
10203 if (INTEL_INFO(dev)->gen >= 6)
10204 gen6_rps_idle(dev->dev_private);
10205
10206 intel_runtime_pm_put(dev_priv);
10207}
10208
10209static void intel_crtc_set_state(struct intel_crtc *crtc,
10210 struct intel_crtc_state *crtc_state)
10211{
10212 kfree(crtc->config);
10213 crtc->config = crtc_state;
10214 crtc->base.state = &crtc_state->base;
10215}
10216
10217static void intel_crtc_destroy(struct drm_crtc *crtc)
10218{
10219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10220 struct drm_device *dev = crtc->dev;
10221 struct intel_unpin_work *work;
10222
10223 spin_lock_irq(&dev->event_lock);
10224 work = intel_crtc->unpin_work;
10225 intel_crtc->unpin_work = NULL;
10226 spin_unlock_irq(&dev->event_lock);
10227
10228 if (work) {
10229 cancel_work_sync(&work->work);
10230 kfree(work);
10231 }
10232
10233 intel_crtc_set_state(intel_crtc, NULL);
10234 drm_crtc_cleanup(crtc);
10235
10236 kfree(intel_crtc);
10237}
10238
10239static void intel_unpin_work_fn(struct work_struct *__work)
10240{
10241 struct intel_unpin_work *work =
10242 container_of(__work, struct intel_unpin_work, work);
10243 struct drm_device *dev = work->crtc->dev;
10244 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10245
10246 mutex_lock(&dev->struct_mutex);
10247 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10248 drm_gem_object_unreference(&work->pending_flip_obj->base);
10249
10250 intel_fbc_update(dev);
10251
10252 if (work->flip_queued_req)
10253 i915_gem_request_assign(&work->flip_queued_req, NULL);
10254 mutex_unlock(&dev->struct_mutex);
10255
10256 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10257 drm_framebuffer_unreference(work->old_fb);
10258
10259 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10260 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10261
10262 kfree(work);
10263}
10264
10265static void do_intel_finish_page_flip(struct drm_device *dev,
10266 struct drm_crtc *crtc)
10267{
10268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10269 struct intel_unpin_work *work;
10270 unsigned long flags;
10271
10272 /* Ignore early vblank irqs */
10273 if (intel_crtc == NULL)
10274 return;
10275
10276 /*
10277 * This is called both by irq handlers and the reset code (to complete
10278 * lost pageflips) so needs the full irqsave spinlocks.
10279 */
10280 spin_lock_irqsave(&dev->event_lock, flags);
10281 work = intel_crtc->unpin_work;
10282
10283 /* Ensure we don't miss a work->pending update ... */
10284 smp_rmb();
10285
10286 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10287 spin_unlock_irqrestore(&dev->event_lock, flags);
10288 return;
10289 }
10290
10291 page_flip_completed(intel_crtc);
10292
10293 spin_unlock_irqrestore(&dev->event_lock, flags);
10294}
10295
10296void intel_finish_page_flip(struct drm_device *dev, int pipe)
10297{
10298 struct drm_i915_private *dev_priv = dev->dev_private;
10299 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10300
10301 do_intel_finish_page_flip(dev, crtc);
10302}
10303
10304void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10305{
10306 struct drm_i915_private *dev_priv = dev->dev_private;
10307 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10308
10309 do_intel_finish_page_flip(dev, crtc);
10310}
10311
10312/* Is 'a' after or equal to 'b'? */
10313static bool g4x_flip_count_after_eq(u32 a, u32 b)
10314{
10315 return !((a - b) & 0x80000000);
10316}
10317
10318static bool page_flip_finished(struct intel_crtc *crtc)
10319{
10320 struct drm_device *dev = crtc->base.dev;
10321 struct drm_i915_private *dev_priv = dev->dev_private;
10322
10323 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10324 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10325 return true;
10326
10327 /*
10328 * The relevant registers doen't exist on pre-ctg.
10329 * As the flip done interrupt doesn't trigger for mmio
10330 * flips on gmch platforms, a flip count check isn't
10331 * really needed there. But since ctg has the registers,
10332 * include it in the check anyway.
10333 */
10334 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10335 return true;
10336
10337 /*
10338 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10339 * used the same base address. In that case the mmio flip might
10340 * have completed, but the CS hasn't even executed the flip yet.
10341 *
10342 * A flip count check isn't enough as the CS might have updated
10343 * the base address just after start of vblank, but before we
10344 * managed to process the interrupt. This means we'd complete the
10345 * CS flip too soon.
10346 *
10347 * Combining both checks should get us a good enough result. It may
10348 * still happen that the CS flip has been executed, but has not
10349 * yet actually completed. But in case the base address is the same
10350 * anyway, we don't really care.
10351 */
10352 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10353 crtc->unpin_work->gtt_offset &&
10354 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10355 crtc->unpin_work->flip_count);
10356}
10357
10358void intel_prepare_page_flip(struct drm_device *dev, int plane)
10359{
10360 struct drm_i915_private *dev_priv = dev->dev_private;
10361 struct intel_crtc *intel_crtc =
10362 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10363 unsigned long flags;
10364
10365
10366 /*
10367 * This is called both by irq handlers and the reset code (to complete
10368 * lost pageflips) so needs the full irqsave spinlocks.
10369 *
10370 * NB: An MMIO update of the plane base pointer will also
10371 * generate a page-flip completion irq, i.e. every modeset
10372 * is also accompanied by a spurious intel_prepare_page_flip().
10373 */
10374 spin_lock_irqsave(&dev->event_lock, flags);
10375 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10376 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10377 spin_unlock_irqrestore(&dev->event_lock, flags);
10378}
10379
10380static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10381{
10382 /* Ensure that the work item is consistent when activating it ... */
10383 smp_wmb();
10384 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10385 /* and that it is marked active as soon as the irq could fire. */
10386 smp_wmb();
10387}
10388
10389static int intel_gen2_queue_flip(struct drm_device *dev,
10390 struct drm_crtc *crtc,
10391 struct drm_framebuffer *fb,
10392 struct drm_i915_gem_object *obj,
10393 struct intel_engine_cs *ring,
10394 uint32_t flags)
10395{
10396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10397 u32 flip_mask;
10398 int ret;
10399
10400 ret = intel_ring_begin(ring, 6);
10401 if (ret)
10402 return ret;
10403
10404 /* Can't queue multiple flips, so wait for the previous
10405 * one to finish before executing the next.
10406 */
10407 if (intel_crtc->plane)
10408 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10409 else
10410 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10411 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10412 intel_ring_emit(ring, MI_NOOP);
10413 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10414 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10415 intel_ring_emit(ring, fb->pitches[0]);
10416 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10417 intel_ring_emit(ring, 0); /* aux display base address, unused */
10418
10419 intel_mark_page_flip_active(intel_crtc);
10420 __intel_ring_advance(ring);
10421 return 0;
10422}
10423
10424static int intel_gen3_queue_flip(struct drm_device *dev,
10425 struct drm_crtc *crtc,
10426 struct drm_framebuffer *fb,
10427 struct drm_i915_gem_object *obj,
10428 struct intel_engine_cs *ring,
10429 uint32_t flags)
10430{
10431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10432 u32 flip_mask;
10433 int ret;
10434
10435 ret = intel_ring_begin(ring, 6);
10436 if (ret)
10437 return ret;
10438
10439 if (intel_crtc->plane)
10440 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10441 else
10442 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10443 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10444 intel_ring_emit(ring, MI_NOOP);
10445 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10446 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10447 intel_ring_emit(ring, fb->pitches[0]);
10448 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10449 intel_ring_emit(ring, MI_NOOP);
10450
10451 intel_mark_page_flip_active(intel_crtc);
10452 __intel_ring_advance(ring);
10453 return 0;
10454}
10455
10456static int intel_gen4_queue_flip(struct drm_device *dev,
10457 struct drm_crtc *crtc,
10458 struct drm_framebuffer *fb,
10459 struct drm_i915_gem_object *obj,
10460 struct intel_engine_cs *ring,
10461 uint32_t flags)
10462{
10463 struct drm_i915_private *dev_priv = dev->dev_private;
10464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10465 uint32_t pf, pipesrc;
10466 int ret;
10467
10468 ret = intel_ring_begin(ring, 4);
10469 if (ret)
10470 return ret;
10471
10472 /* i965+ uses the linear or tiled offsets from the
10473 * Display Registers (which do not change across a page-flip)
10474 * so we need only reprogram the base address.
10475 */
10476 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10477 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10478 intel_ring_emit(ring, fb->pitches[0]);
10479 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10480 obj->tiling_mode);
10481
10482 /* XXX Enabling the panel-fitter across page-flip is so far
10483 * untested on non-native modes, so ignore it for now.
10484 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10485 */
10486 pf = 0;
10487 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10488 intel_ring_emit(ring, pf | pipesrc);
10489
10490 intel_mark_page_flip_active(intel_crtc);
10491 __intel_ring_advance(ring);
10492 return 0;
10493}
10494
10495static int intel_gen6_queue_flip(struct drm_device *dev,
10496 struct drm_crtc *crtc,
10497 struct drm_framebuffer *fb,
10498 struct drm_i915_gem_object *obj,
10499 struct intel_engine_cs *ring,
10500 uint32_t flags)
10501{
10502 struct drm_i915_private *dev_priv = dev->dev_private;
10503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10504 uint32_t pf, pipesrc;
10505 int ret;
10506
10507 ret = intel_ring_begin(ring, 4);
10508 if (ret)
10509 return ret;
10510
10511 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10512 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10513 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10514 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10515
10516 /* Contrary to the suggestions in the documentation,
10517 * "Enable Panel Fitter" does not seem to be required when page
10518 * flipping with a non-native mode, and worse causes a normal
10519 * modeset to fail.
10520 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10521 */
10522 pf = 0;
10523 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10524 intel_ring_emit(ring, pf | pipesrc);
10525
10526 intel_mark_page_flip_active(intel_crtc);
10527 __intel_ring_advance(ring);
10528 return 0;
10529}
10530
10531static int intel_gen7_queue_flip(struct drm_device *dev,
10532 struct drm_crtc *crtc,
10533 struct drm_framebuffer *fb,
10534 struct drm_i915_gem_object *obj,
10535 struct intel_engine_cs *ring,
10536 uint32_t flags)
10537{
10538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10539 uint32_t plane_bit = 0;
10540 int len, ret;
10541
10542 switch (intel_crtc->plane) {
10543 case PLANE_A:
10544 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10545 break;
10546 case PLANE_B:
10547 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10548 break;
10549 case PLANE_C:
10550 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10551 break;
10552 default:
10553 WARN_ONCE(1, "unknown plane in flip command\n");
10554 return -ENODEV;
10555 }
10556
10557 len = 4;
10558 if (ring->id == RCS) {
10559 len += 6;
10560 /*
10561 * On Gen 8, SRM is now taking an extra dword to accommodate
10562 * 48bits addresses, and we need a NOOP for the batch size to
10563 * stay even.
10564 */
10565 if (IS_GEN8(dev))
10566 len += 2;
10567 }
10568
10569 /*
10570 * BSpec MI_DISPLAY_FLIP for IVB:
10571 * "The full packet must be contained within the same cache line."
10572 *
10573 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10574 * cacheline, if we ever start emitting more commands before
10575 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10576 * then do the cacheline alignment, and finally emit the
10577 * MI_DISPLAY_FLIP.
10578 */
10579 ret = intel_ring_cacheline_align(ring);
10580 if (ret)
10581 return ret;
10582
10583 ret = intel_ring_begin(ring, len);
10584 if (ret)
10585 return ret;
10586
10587 /* Unmask the flip-done completion message. Note that the bspec says that
10588 * we should do this for both the BCS and RCS, and that we must not unmask
10589 * more than one flip event at any time (or ensure that one flip message
10590 * can be sent by waiting for flip-done prior to queueing new flips).
10591 * Experimentation says that BCS works despite DERRMR masking all
10592 * flip-done completion events and that unmasking all planes at once
10593 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10594 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10595 */
10596 if (ring->id == RCS) {
10597 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10598 intel_ring_emit(ring, DERRMR);
10599 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10600 DERRMR_PIPEB_PRI_FLIP_DONE |
10601 DERRMR_PIPEC_PRI_FLIP_DONE));
10602 if (IS_GEN8(dev))
10603 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10604 MI_SRM_LRM_GLOBAL_GTT);
10605 else
10606 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10607 MI_SRM_LRM_GLOBAL_GTT);
10608 intel_ring_emit(ring, DERRMR);
10609 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10610 if (IS_GEN8(dev)) {
10611 intel_ring_emit(ring, 0);
10612 intel_ring_emit(ring, MI_NOOP);
10613 }
10614 }
10615
10616 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10617 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10618 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10619 intel_ring_emit(ring, (MI_NOOP));
10620
10621 intel_mark_page_flip_active(intel_crtc);
10622 __intel_ring_advance(ring);
10623 return 0;
10624}
10625
10626static bool use_mmio_flip(struct intel_engine_cs *ring,
10627 struct drm_i915_gem_object *obj)
10628{
10629 /*
10630 * This is not being used for older platforms, because
10631 * non-availability of flip done interrupt forces us to use
10632 * CS flips. Older platforms derive flip done using some clever
10633 * tricks involving the flip_pending status bits and vblank irqs.
10634 * So using MMIO flips there would disrupt this mechanism.
10635 */
10636
10637 if (ring == NULL)
10638 return true;
10639
10640 if (INTEL_INFO(ring->dev)->gen < 5)
10641 return false;
10642
10643 if (i915.use_mmio_flip < 0)
10644 return false;
10645 else if (i915.use_mmio_flip > 0)
10646 return true;
10647 else if (i915.enable_execlists)
10648 return true;
10649 else
10650 return ring != i915_gem_request_get_ring(obj->last_read_req);
10651}
10652
10653static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10654{
10655 struct drm_device *dev = intel_crtc->base.dev;
10656 struct drm_i915_private *dev_priv = dev->dev_private;
10657 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10658 const enum pipe pipe = intel_crtc->pipe;
10659 u32 ctl, stride;
10660
10661 ctl = I915_READ(PLANE_CTL(pipe, 0));
10662 ctl &= ~PLANE_CTL_TILED_MASK;
10663 switch (fb->modifier[0]) {
10664 case DRM_FORMAT_MOD_NONE:
10665 break;
10666 case I915_FORMAT_MOD_X_TILED:
10667 ctl |= PLANE_CTL_TILED_X;
10668 break;
10669 case I915_FORMAT_MOD_Y_TILED:
10670 ctl |= PLANE_CTL_TILED_Y;
10671 break;
10672 case I915_FORMAT_MOD_Yf_TILED:
10673 ctl |= PLANE_CTL_TILED_YF;
10674 break;
10675 default:
10676 MISSING_CASE(fb->modifier[0]);
10677 }
10678
10679 /*
10680 * The stride is either expressed as a multiple of 64 bytes chunks for
10681 * linear buffers or in number of tiles for tiled buffers.
10682 */
10683 stride = fb->pitches[0] /
10684 intel_fb_stride_alignment(dev, fb->modifier[0],
10685 fb->pixel_format);
10686
10687 /*
10688 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10689 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10690 */
10691 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10692 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10693
10694 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10695 POSTING_READ(PLANE_SURF(pipe, 0));
10696}
10697
10698static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10699{
10700 struct drm_device *dev = intel_crtc->base.dev;
10701 struct drm_i915_private *dev_priv = dev->dev_private;
10702 struct intel_framebuffer *intel_fb =
10703 to_intel_framebuffer(intel_crtc->base.primary->fb);
10704 struct drm_i915_gem_object *obj = intel_fb->obj;
10705 u32 dspcntr;
10706 u32 reg;
10707
10708 reg = DSPCNTR(intel_crtc->plane);
10709 dspcntr = I915_READ(reg);
10710
10711 if (obj->tiling_mode != I915_TILING_NONE)
10712 dspcntr |= DISPPLANE_TILED;
10713 else
10714 dspcntr &= ~DISPPLANE_TILED;
10715
10716 I915_WRITE(reg, dspcntr);
10717
10718 I915_WRITE(DSPSURF(intel_crtc->plane),
10719 intel_crtc->unpin_work->gtt_offset);
10720 POSTING_READ(DSPSURF(intel_crtc->plane));
10721
10722}
10723
10724/*
10725 * XXX: This is the temporary way to update the plane registers until we get
10726 * around to using the usual plane update functions for MMIO flips
10727 */
10728static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10729{
10730 struct drm_device *dev = intel_crtc->base.dev;
10731 bool atomic_update;
10732 u32 start_vbl_count;
10733
10734 intel_mark_page_flip_active(intel_crtc);
10735
10736 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10737
10738 if (INTEL_INFO(dev)->gen >= 9)
10739 skl_do_mmio_flip(intel_crtc);
10740 else
10741 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10742 ilk_do_mmio_flip(intel_crtc);
10743
10744 if (atomic_update)
10745 intel_pipe_update_end(intel_crtc, start_vbl_count);
10746}
10747
10748static void intel_mmio_flip_work_func(struct work_struct *work)
10749{
10750 struct intel_crtc *crtc =
10751 container_of(work, struct intel_crtc, mmio_flip.work);
10752 struct intel_mmio_flip *mmio_flip;
10753
10754 mmio_flip = &crtc->mmio_flip;
10755 if (mmio_flip->req)
10756 WARN_ON(__i915_wait_request(mmio_flip->req,
10757 crtc->reset_counter,
10758 false, NULL, NULL) != 0);
10759
10760 intel_do_mmio_flip(crtc);
10761 if (mmio_flip->req) {
10762 mutex_lock(&crtc->base.dev->struct_mutex);
10763 i915_gem_request_assign(&mmio_flip->req, NULL);
10764 mutex_unlock(&crtc->base.dev->struct_mutex);
10765 }
10766}
10767
10768static int intel_queue_mmio_flip(struct drm_device *dev,
10769 struct drm_crtc *crtc,
10770 struct drm_framebuffer *fb,
10771 struct drm_i915_gem_object *obj,
10772 struct intel_engine_cs *ring,
10773 uint32_t flags)
10774{
10775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10776
10777 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10778 obj->last_write_req);
10779
10780 schedule_work(&intel_crtc->mmio_flip.work);
10781
10782 return 0;
10783}
10784
10785static int intel_default_queue_flip(struct drm_device *dev,
10786 struct drm_crtc *crtc,
10787 struct drm_framebuffer *fb,
10788 struct drm_i915_gem_object *obj,
10789 struct intel_engine_cs *ring,
10790 uint32_t flags)
10791{
10792 return -ENODEV;
10793}
10794
10795static bool __intel_pageflip_stall_check(struct drm_device *dev,
10796 struct drm_crtc *crtc)
10797{
10798 struct drm_i915_private *dev_priv = dev->dev_private;
10799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10800 struct intel_unpin_work *work = intel_crtc->unpin_work;
10801 u32 addr;
10802
10803 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10804 return true;
10805
10806 if (!work->enable_stall_check)
10807 return false;
10808
10809 if (work->flip_ready_vblank == 0) {
10810 if (work->flip_queued_req &&
10811 !i915_gem_request_completed(work->flip_queued_req, true))
10812 return false;
10813
10814 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10815 }
10816
10817 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10818 return false;
10819
10820 /* Potential stall - if we see that the flip has happened,
10821 * assume a missed interrupt. */
10822 if (INTEL_INFO(dev)->gen >= 4)
10823 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10824 else
10825 addr = I915_READ(DSPADDR(intel_crtc->plane));
10826
10827 /* There is a potential issue here with a false positive after a flip
10828 * to the same address. We could address this by checking for a
10829 * non-incrementing frame counter.
10830 */
10831 return addr == work->gtt_offset;
10832}
10833
10834void intel_check_page_flip(struct drm_device *dev, int pipe)
10835{
10836 struct drm_i915_private *dev_priv = dev->dev_private;
10837 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10839 struct intel_unpin_work *work;
10840
10841 WARN_ON(!in_interrupt());
10842
10843 if (crtc == NULL)
10844 return;
10845
10846 spin_lock(&dev->event_lock);
10847 work = intel_crtc->unpin_work;
10848 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10849 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10850 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10851 page_flip_completed(intel_crtc);
10852 work = NULL;
10853 }
10854 if (work != NULL &&
10855 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10856 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10857 spin_unlock(&dev->event_lock);
10858}
10859
10860static int intel_crtc_page_flip(struct drm_crtc *crtc,
10861 struct drm_framebuffer *fb,
10862 struct drm_pending_vblank_event *event,
10863 uint32_t page_flip_flags)
10864{
10865 struct drm_device *dev = crtc->dev;
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10867 struct drm_framebuffer *old_fb = crtc->primary->fb;
10868 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10870 struct drm_plane *primary = crtc->primary;
10871 enum pipe pipe = intel_crtc->pipe;
10872 struct intel_unpin_work *work;
10873 struct intel_engine_cs *ring;
10874 bool mmio_flip;
10875 int ret;
10876
10877 /*
10878 * drm_mode_page_flip_ioctl() should already catch this, but double
10879 * check to be safe. In the future we may enable pageflipping from
10880 * a disabled primary plane.
10881 */
10882 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10883 return -EBUSY;
10884
10885 /* Can't change pixel format via MI display flips. */
10886 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10887 return -EINVAL;
10888
10889 /*
10890 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10891 * Note that pitch changes could also affect these register.
10892 */
10893 if (INTEL_INFO(dev)->gen > 3 &&
10894 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10895 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10896 return -EINVAL;
10897
10898 if (i915_terminally_wedged(&dev_priv->gpu_error))
10899 goto out_hang;
10900
10901 work = kzalloc(sizeof(*work), GFP_KERNEL);
10902 if (work == NULL)
10903 return -ENOMEM;
10904
10905 work->event = event;
10906 work->crtc = crtc;
10907 work->old_fb = old_fb;
10908 INIT_WORK(&work->work, intel_unpin_work_fn);
10909
10910 ret = drm_crtc_vblank_get(crtc);
10911 if (ret)
10912 goto free_work;
10913
10914 /* We borrow the event spin lock for protecting unpin_work */
10915 spin_lock_irq(&dev->event_lock);
10916 if (intel_crtc->unpin_work) {
10917 /* Before declaring the flip queue wedged, check if
10918 * the hardware completed the operation behind our backs.
10919 */
10920 if (__intel_pageflip_stall_check(dev, crtc)) {
10921 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10922 page_flip_completed(intel_crtc);
10923 } else {
10924 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10925 spin_unlock_irq(&dev->event_lock);
10926
10927 drm_crtc_vblank_put(crtc);
10928 kfree(work);
10929 return -EBUSY;
10930 }
10931 }
10932 intel_crtc->unpin_work = work;
10933 spin_unlock_irq(&dev->event_lock);
10934
10935 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10936 flush_workqueue(dev_priv->wq);
10937
10938 /* Reference the objects for the scheduled work. */
10939 drm_framebuffer_reference(work->old_fb);
10940 drm_gem_object_reference(&obj->base);
10941
10942 crtc->primary->fb = fb;
10943 update_state_fb(crtc->primary);
10944
10945 work->pending_flip_obj = obj;
10946
10947 ret = i915_mutex_lock_interruptible(dev);
10948 if (ret)
10949 goto cleanup;
10950
10951 atomic_inc(&intel_crtc->unpin_work_count);
10952 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10953
10954 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10955 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10956
10957 if (IS_VALLEYVIEW(dev)) {
10958 ring = &dev_priv->ring[BCS];
10959 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10960 /* vlv: DISPLAY_FLIP fails to change tiling */
10961 ring = NULL;
10962 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10963 ring = &dev_priv->ring[BCS];
10964 } else if (INTEL_INFO(dev)->gen >= 7) {
10965 ring = i915_gem_request_get_ring(obj->last_read_req);
10966 if (ring == NULL || ring->id != RCS)
10967 ring = &dev_priv->ring[BCS];
10968 } else {
10969 ring = &dev_priv->ring[RCS];
10970 }
10971
10972 mmio_flip = use_mmio_flip(ring, obj);
10973
10974 /* When using CS flips, we want to emit semaphores between rings.
10975 * However, when using mmio flips we will create a task to do the
10976 * synchronisation, so all we want here is to pin the framebuffer
10977 * into the display plane and skip any waits.
10978 */
10979 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10980 crtc->primary->state,
10981 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
10982 if (ret)
10983 goto cleanup_pending;
10984
10985 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10986 + intel_crtc->dspaddr_offset;
10987
10988 if (mmio_flip) {
10989 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10990 page_flip_flags);
10991 if (ret)
10992 goto cleanup_unpin;
10993
10994 i915_gem_request_assign(&work->flip_queued_req,
10995 obj->last_write_req);
10996 } else {
10997 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10998 page_flip_flags);
10999 if (ret)
11000 goto cleanup_unpin;
11001
11002 i915_gem_request_assign(&work->flip_queued_req,
11003 intel_ring_get_request(ring));
11004 }
11005
11006 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11007 work->enable_stall_check = true;
11008
11009 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11010 INTEL_FRONTBUFFER_PRIMARY(pipe));
11011
11012 intel_fbc_disable(dev);
11013 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11014 mutex_unlock(&dev->struct_mutex);
11015
11016 trace_i915_flip_request(intel_crtc->plane, obj);
11017
11018 return 0;
11019
11020cleanup_unpin:
11021 intel_unpin_fb_obj(fb, crtc->primary->state);
11022cleanup_pending:
11023 atomic_dec(&intel_crtc->unpin_work_count);
11024 mutex_unlock(&dev->struct_mutex);
11025cleanup:
11026 crtc->primary->fb = old_fb;
11027 update_state_fb(crtc->primary);
11028
11029 drm_gem_object_unreference_unlocked(&obj->base);
11030 drm_framebuffer_unreference(work->old_fb);
11031
11032 spin_lock_irq(&dev->event_lock);
11033 intel_crtc->unpin_work = NULL;
11034 spin_unlock_irq(&dev->event_lock);
11035
11036 drm_crtc_vblank_put(crtc);
11037free_work:
11038 kfree(work);
11039
11040 if (ret == -EIO) {
11041out_hang:
11042 ret = intel_plane_restore(primary);
11043 if (ret == 0 && event) {
11044 spin_lock_irq(&dev->event_lock);
11045 drm_send_vblank_event(dev, pipe, event);
11046 spin_unlock_irq(&dev->event_lock);
11047 }
11048 }
11049 return ret;
11050}
11051
11052static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11053 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11054 .load_lut = intel_crtc_load_lut,
11055 .atomic_begin = intel_begin_crtc_commit,
11056 .atomic_flush = intel_finish_crtc_commit,
11057};
11058
11059/**
11060 * intel_modeset_update_staged_output_state
11061 *
11062 * Updates the staged output configuration state, e.g. after we've read out the
11063 * current hw state.
11064 */
11065static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11066{
11067 struct intel_crtc *crtc;
11068 struct intel_encoder *encoder;
11069 struct intel_connector *connector;
11070
11071 for_each_intel_connector(dev, connector) {
11072 connector->new_encoder =
11073 to_intel_encoder(connector->base.encoder);
11074 }
11075
11076 for_each_intel_encoder(dev, encoder) {
11077 encoder->new_crtc =
11078 to_intel_crtc(encoder->base.crtc);
11079 }
11080
11081 for_each_intel_crtc(dev, crtc) {
11082 crtc->new_enabled = crtc->base.state->enable;
11083 }
11084}
11085
11086/* Transitional helper to copy current connector/encoder state to
11087 * connector->state. This is needed so that code that is partially
11088 * converted to atomic does the right thing.
11089 */
11090static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11091{
11092 struct intel_connector *connector;
11093
11094 for_each_intel_connector(dev, connector) {
11095 if (connector->base.encoder) {
11096 connector->base.state->best_encoder =
11097 connector->base.encoder;
11098 connector->base.state->crtc =
11099 connector->base.encoder->crtc;
11100 } else {
11101 connector->base.state->best_encoder = NULL;
11102 connector->base.state->crtc = NULL;
11103 }
11104 }
11105}
11106
11107/**
11108 * intel_modeset_commit_output_state
11109 *
11110 * This function copies the stage display pipe configuration to the real one.
11111 */
11112static void intel_modeset_commit_output_state(struct drm_device *dev)
11113{
11114 struct intel_crtc *crtc;
11115 struct intel_encoder *encoder;
11116 struct intel_connector *connector;
11117
11118 for_each_intel_connector(dev, connector) {
11119 connector->base.encoder = &connector->new_encoder->base;
11120 }
11121
11122 for_each_intel_encoder(dev, encoder) {
11123 encoder->base.crtc = &encoder->new_crtc->base;
11124 }
11125
11126 for_each_intel_crtc(dev, crtc) {
11127 crtc->base.state->enable = crtc->new_enabled;
11128 crtc->base.enabled = crtc->new_enabled;
11129 }
11130
11131 intel_modeset_update_connector_atomic_state(dev);
11132}
11133
11134static void
11135connected_sink_compute_bpp(struct intel_connector *connector,
11136 struct intel_crtc_state *pipe_config)
11137{
11138 int bpp = pipe_config->pipe_bpp;
11139
11140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11141 connector->base.base.id,
11142 connector->base.name);
11143
11144 /* Don't use an invalid EDID bpc value */
11145 if (connector->base.display_info.bpc &&
11146 connector->base.display_info.bpc * 3 < bpp) {
11147 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11148 bpp, connector->base.display_info.bpc*3);
11149 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11150 }
11151
11152 /* Clamp bpp to 8 on screens without EDID 1.4 */
11153 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11154 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11155 bpp);
11156 pipe_config->pipe_bpp = 24;
11157 }
11158}
11159
11160static int
11161compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11162 struct intel_crtc_state *pipe_config)
11163{
11164 struct drm_device *dev = crtc->base.dev;
11165 struct drm_atomic_state *state;
11166 struct drm_connector *connector;
11167 struct drm_connector_state *connector_state;
11168 int bpp, i;
11169
11170 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11171 bpp = 10*3;
11172 else if (INTEL_INFO(dev)->gen >= 5)
11173 bpp = 12*3;
11174 else
11175 bpp = 8*3;
11176
11177
11178 pipe_config->pipe_bpp = bpp;
11179
11180 state = pipe_config->base.state;
11181
11182 /* Clamp display bpp to EDID value */
11183 for_each_connector_in_state(state, connector, connector_state, i) {
11184 if (connector_state->crtc != &crtc->base)
11185 continue;
11186
11187 connected_sink_compute_bpp(to_intel_connector(connector),
11188 pipe_config);
11189 }
11190
11191 return bpp;
11192}
11193
11194static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11195{
11196 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11197 "type: 0x%x flags: 0x%x\n",
11198 mode->crtc_clock,
11199 mode->crtc_hdisplay, mode->crtc_hsync_start,
11200 mode->crtc_hsync_end, mode->crtc_htotal,
11201 mode->crtc_vdisplay, mode->crtc_vsync_start,
11202 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11203}
11204
11205static void intel_dump_pipe_config(struct intel_crtc *crtc,
11206 struct intel_crtc_state *pipe_config,
11207 const char *context)
11208{
11209 struct drm_device *dev = crtc->base.dev;
11210 struct drm_plane *plane;
11211 struct intel_plane *intel_plane;
11212 struct intel_plane_state *state;
11213 struct drm_framebuffer *fb;
11214
11215 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11216 context, pipe_config, pipe_name(crtc->pipe));
11217
11218 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11219 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11220 pipe_config->pipe_bpp, pipe_config->dither);
11221 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11222 pipe_config->has_pch_encoder,
11223 pipe_config->fdi_lanes,
11224 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11225 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11226 pipe_config->fdi_m_n.tu);
11227 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11228 pipe_config->has_dp_encoder,
11229 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11230 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11231 pipe_config->dp_m_n.tu);
11232
11233 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11234 pipe_config->has_dp_encoder,
11235 pipe_config->dp_m2_n2.gmch_m,
11236 pipe_config->dp_m2_n2.gmch_n,
11237 pipe_config->dp_m2_n2.link_m,
11238 pipe_config->dp_m2_n2.link_n,
11239 pipe_config->dp_m2_n2.tu);
11240
11241 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11242 pipe_config->has_audio,
11243 pipe_config->has_infoframe);
11244
11245 DRM_DEBUG_KMS("requested mode:\n");
11246 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11247 DRM_DEBUG_KMS("adjusted mode:\n");
11248 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11249 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11250 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11251 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11252 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11253 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11254 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11255 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
11256 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11257 pipe_config->gmch_pfit.control,
11258 pipe_config->gmch_pfit.pgm_ratios,
11259 pipe_config->gmch_pfit.lvds_border_bits);
11260 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11261 pipe_config->pch_pfit.pos,
11262 pipe_config->pch_pfit.size,
11263 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11264 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11265 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11266
11267 DRM_DEBUG_KMS("planes on this crtc\n");
11268 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11269 intel_plane = to_intel_plane(plane);
11270 if (intel_plane->pipe != crtc->pipe)
11271 continue;
11272
11273 state = to_intel_plane_state(plane->state);
11274 fb = state->base.fb;
11275 if (!fb) {
11276 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11277 "disabled, scaler_id = %d\n",
11278 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11279 plane->base.id, intel_plane->pipe,
11280 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11281 drm_plane_index(plane), state->scaler_id);
11282 continue;
11283 }
11284
11285 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11286 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11287 plane->base.id, intel_plane->pipe,
11288 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11289 drm_plane_index(plane));
11290 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11291 fb->base.id, fb->width, fb->height, fb->pixel_format);
11292 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11293 state->scaler_id,
11294 state->src.x1 >> 16, state->src.y1 >> 16,
11295 drm_rect_width(&state->src) >> 16,
11296 drm_rect_height(&state->src) >> 16,
11297 state->dst.x1, state->dst.y1,
11298 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11299 }
11300}
11301
11302static bool encoders_cloneable(const struct intel_encoder *a,
11303 const struct intel_encoder *b)
11304{
11305 /* masks could be asymmetric, so check both ways */
11306 return a == b || (a->cloneable & (1 << b->type) &&
11307 b->cloneable & (1 << a->type));
11308}
11309
11310static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11311 struct intel_crtc *crtc,
11312 struct intel_encoder *encoder)
11313{
11314 struct intel_encoder *source_encoder;
11315 struct drm_connector *connector;
11316 struct drm_connector_state *connector_state;
11317 int i;
11318
11319 for_each_connector_in_state(state, connector, connector_state, i) {
11320 if (connector_state->crtc != &crtc->base)
11321 continue;
11322
11323 source_encoder =
11324 to_intel_encoder(connector_state->best_encoder);
11325 if (!encoders_cloneable(encoder, source_encoder))
11326 return false;
11327 }
11328
11329 return true;
11330}
11331
11332static bool check_encoder_cloning(struct drm_atomic_state *state,
11333 struct intel_crtc *crtc)
11334{
11335 struct intel_encoder *encoder;
11336 struct drm_connector *connector;
11337 struct drm_connector_state *connector_state;
11338 int i;
11339
11340 for_each_connector_in_state(state, connector, connector_state, i) {
11341 if (connector_state->crtc != &crtc->base)
11342 continue;
11343
11344 encoder = to_intel_encoder(connector_state->best_encoder);
11345 if (!check_single_encoder_cloning(state, crtc, encoder))
11346 return false;
11347 }
11348
11349 return true;
11350}
11351
11352static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11353{
11354 struct drm_device *dev = state->dev;
11355 struct intel_encoder *encoder;
11356 struct drm_connector *connector;
11357 struct drm_connector_state *connector_state;
11358 unsigned int used_ports = 0;
11359 int i;
11360
11361 /*
11362 * Walk the connector list instead of the encoder
11363 * list to detect the problem on ddi platforms
11364 * where there's just one encoder per digital port.
11365 */
11366 for_each_connector_in_state(state, connector, connector_state, i) {
11367 if (!connector_state->best_encoder)
11368 continue;
11369
11370 encoder = to_intel_encoder(connector_state->best_encoder);
11371
11372 WARN_ON(!connector_state->crtc);
11373
11374 switch (encoder->type) {
11375 unsigned int port_mask;
11376 case INTEL_OUTPUT_UNKNOWN:
11377 if (WARN_ON(!HAS_DDI(dev)))
11378 break;
11379 case INTEL_OUTPUT_DISPLAYPORT:
11380 case INTEL_OUTPUT_HDMI:
11381 case INTEL_OUTPUT_EDP:
11382 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11383
11384 /* the same port mustn't appear more than once */
11385 if (used_ports & port_mask)
11386 return false;
11387
11388 used_ports |= port_mask;
11389 default:
11390 break;
11391 }
11392 }
11393
11394 return true;
11395}
11396
11397static void
11398clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11399{
11400 struct drm_crtc_state tmp_state;
11401 struct intel_crtc_scaler_state scaler_state;
11402
11403 /* Clear only the intel specific part of the crtc state excluding scalers */
11404 tmp_state = crtc_state->base;
11405 scaler_state = crtc_state->scaler_state;
11406 memset(crtc_state, 0, sizeof *crtc_state);
11407 crtc_state->base = tmp_state;
11408 crtc_state->scaler_state = scaler_state;
11409}
11410
11411static int
11412intel_modeset_pipe_config(struct drm_crtc *crtc,
11413 struct drm_display_mode *mode,
11414 struct drm_atomic_state *state,
11415 struct intel_crtc_state *pipe_config)
11416{
11417 struct intel_encoder *encoder;
11418 struct drm_connector *connector;
11419 struct drm_connector_state *connector_state;
11420 int base_bpp, ret = -EINVAL;
11421 int i;
11422 bool retry = true;
11423
11424 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11425 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11426 return -EINVAL;
11427 }
11428
11429 if (!check_digital_port_conflicts(state)) {
11430 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11431 return -EINVAL;
11432 }
11433
11434 clear_intel_crtc_state(pipe_config);
11435
11436 pipe_config->base.crtc = crtc;
11437 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11438 drm_mode_copy(&pipe_config->base.mode, mode);
11439
11440 pipe_config->cpu_transcoder =
11441 (enum transcoder) to_intel_crtc(crtc)->pipe;
11442 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
11443
11444 /*
11445 * Sanitize sync polarity flags based on requested ones. If neither
11446 * positive or negative polarity is requested, treat this as meaning
11447 * negative polarity.
11448 */
11449 if (!(pipe_config->base.adjusted_mode.flags &
11450 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11451 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11452
11453 if (!(pipe_config->base.adjusted_mode.flags &
11454 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11455 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11456
11457 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11458 * plane pixel format and any sink constraints into account. Returns the
11459 * source plane bpp so that dithering can be selected on mismatches
11460 * after encoders and crtc also have had their say. */
11461 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11462 pipe_config);
11463 if (base_bpp < 0)
11464 goto fail;
11465
11466 /*
11467 * Determine the real pipe dimensions. Note that stereo modes can
11468 * increase the actual pipe size due to the frame doubling and
11469 * insertion of additional space for blanks between the frame. This
11470 * is stored in the crtc timings. We use the requested mode to do this
11471 * computation to clearly distinguish it from the adjusted mode, which
11472 * can be changed by the connectors in the below retry loop.
11473 */
11474 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11475 &pipe_config->pipe_src_w,
11476 &pipe_config->pipe_src_h);
11477
11478encoder_retry:
11479 /* Ensure the port clock defaults are reset when retrying. */
11480 pipe_config->port_clock = 0;
11481 pipe_config->pixel_multiplier = 1;
11482
11483 /* Fill in default crtc timings, allow encoders to overwrite them. */
11484 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11485 CRTC_STEREO_DOUBLE);
11486
11487 /* Pass our mode to the connectors and the CRTC to give them a chance to
11488 * adjust it according to limitations or connector properties, and also
11489 * a chance to reject the mode entirely.
11490 */
11491 for_each_connector_in_state(state, connector, connector_state, i) {
11492 if (connector_state->crtc != crtc)
11493 continue;
11494
11495 encoder = to_intel_encoder(connector_state->best_encoder);
11496
11497 if (!(encoder->compute_config(encoder, pipe_config))) {
11498 DRM_DEBUG_KMS("Encoder config failure\n");
11499 goto fail;
11500 }
11501 }
11502
11503 /* Set default port clock if not overwritten by the encoder. Needs to be
11504 * done afterwards in case the encoder adjusts the mode. */
11505 if (!pipe_config->port_clock)
11506 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11507 * pipe_config->pixel_multiplier;
11508
11509 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11510 if (ret < 0) {
11511 DRM_DEBUG_KMS("CRTC fixup failed\n");
11512 goto fail;
11513 }
11514
11515 if (ret == RETRY) {
11516 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11517 ret = -EINVAL;
11518 goto fail;
11519 }
11520
11521 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11522 retry = false;
11523 goto encoder_retry;
11524 }
11525
11526 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11527 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11528 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11529
11530 return 0;
11531fail:
11532 return ret;
11533}
11534
11535static bool intel_crtc_in_use(struct drm_crtc *crtc)
11536{
11537 struct drm_encoder *encoder;
11538 struct drm_device *dev = crtc->dev;
11539
11540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11541 if (encoder->crtc == crtc)
11542 return true;
11543
11544 return false;
11545}
11546
11547static bool
11548needs_modeset(struct drm_crtc_state *state)
11549{
11550 return state->mode_changed || state->active_changed;
11551}
11552
11553static void
11554intel_modeset_update_state(struct drm_atomic_state *state)
11555{
11556 struct drm_device *dev = state->dev;
11557 struct drm_i915_private *dev_priv = dev->dev_private;
11558 struct intel_encoder *intel_encoder;
11559 struct drm_crtc *crtc;
11560 struct drm_crtc_state *crtc_state;
11561 struct drm_connector *connector;
11562 int i;
11563
11564 intel_shared_dpll_commit(dev_priv);
11565
11566 for_each_intel_encoder(dev, intel_encoder) {
11567 if (!intel_encoder->base.crtc)
11568 continue;
11569
11570 for_each_crtc_in_state(state, crtc, crtc_state, i)
11571 if (crtc == intel_encoder->base.crtc)
11572 break;
11573
11574 if (crtc != intel_encoder->base.crtc)
11575 continue;
11576
11577 if (crtc_state->enable && needs_modeset(crtc_state))
11578 intel_encoder->connectors_active = false;
11579 }
11580
11581 intel_modeset_commit_output_state(dev);
11582
11583 /* Double check state. */
11584 for_each_crtc(dev, crtc) {
11585 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11586 }
11587
11588 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11589 if (!connector->encoder || !connector->encoder->crtc)
11590 continue;
11591
11592 for_each_crtc_in_state(state, crtc, crtc_state, i)
11593 if (crtc == connector->encoder->crtc)
11594 break;
11595
11596 if (crtc != connector->encoder->crtc)
11597 continue;
11598
11599 if (crtc_state->enable && needs_modeset(crtc_state)) {
11600 struct drm_property *dpms_property =
11601 dev->mode_config.dpms_property;
11602
11603 connector->dpms = DRM_MODE_DPMS_ON;
11604 drm_object_property_set_value(&connector->base,
11605 dpms_property,
11606 DRM_MODE_DPMS_ON);
11607
11608 intel_encoder = to_intel_encoder(connector->encoder);
11609 intel_encoder->connectors_active = true;
11610 }
11611 }
11612
11613}
11614
11615static bool intel_fuzzy_clock_check(int clock1, int clock2)
11616{
11617 int diff;
11618
11619 if (clock1 == clock2)
11620 return true;
11621
11622 if (!clock1 || !clock2)
11623 return false;
11624
11625 diff = abs(clock1 - clock2);
11626
11627 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11628 return true;
11629
11630 return false;
11631}
11632
11633#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11634 list_for_each_entry((intel_crtc), \
11635 &(dev)->mode_config.crtc_list, \
11636 base.head) \
11637 if (mask & (1 <<(intel_crtc)->pipe))
11638
11639static bool
11640intel_pipe_config_compare(struct drm_device *dev,
11641 struct intel_crtc_state *current_config,
11642 struct intel_crtc_state *pipe_config)
11643{
11644#define PIPE_CONF_CHECK_X(name) \
11645 if (current_config->name != pipe_config->name) { \
11646 DRM_ERROR("mismatch in " #name " " \
11647 "(expected 0x%08x, found 0x%08x)\n", \
11648 current_config->name, \
11649 pipe_config->name); \
11650 return false; \
11651 }
11652
11653#define PIPE_CONF_CHECK_I(name) \
11654 if (current_config->name != pipe_config->name) { \
11655 DRM_ERROR("mismatch in " #name " " \
11656 "(expected %i, found %i)\n", \
11657 current_config->name, \
11658 pipe_config->name); \
11659 return false; \
11660 }
11661
11662/* This is required for BDW+ where there is only one set of registers for
11663 * switching between high and low RR.
11664 * This macro can be used whenever a comparison has to be made between one
11665 * hw state and multiple sw state variables.
11666 */
11667#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11668 if ((current_config->name != pipe_config->name) && \
11669 (current_config->alt_name != pipe_config->name)) { \
11670 DRM_ERROR("mismatch in " #name " " \
11671 "(expected %i or %i, found %i)\n", \
11672 current_config->name, \
11673 current_config->alt_name, \
11674 pipe_config->name); \
11675 return false; \
11676 }
11677
11678#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11679 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11680 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11681 "(expected %i, found %i)\n", \
11682 current_config->name & (mask), \
11683 pipe_config->name & (mask)); \
11684 return false; \
11685 }
11686
11687#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11688 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11689 DRM_ERROR("mismatch in " #name " " \
11690 "(expected %i, found %i)\n", \
11691 current_config->name, \
11692 pipe_config->name); \
11693 return false; \
11694 }
11695
11696#define PIPE_CONF_QUIRK(quirk) \
11697 ((current_config->quirks | pipe_config->quirks) & (quirk))
11698
11699 PIPE_CONF_CHECK_I(cpu_transcoder);
11700
11701 PIPE_CONF_CHECK_I(has_pch_encoder);
11702 PIPE_CONF_CHECK_I(fdi_lanes);
11703 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11704 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11705 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11706 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11707 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11708
11709 PIPE_CONF_CHECK_I(has_dp_encoder);
11710
11711 if (INTEL_INFO(dev)->gen < 8) {
11712 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11713 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11714 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11715 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11716 PIPE_CONF_CHECK_I(dp_m_n.tu);
11717
11718 if (current_config->has_drrs) {
11719 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11720 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11721 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11722 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11723 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11724 }
11725 } else {
11726 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11727 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11728 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11729 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11730 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11731 }
11732
11733 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11734 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11735 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11736 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11737 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11738 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11739
11740 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11741 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11742 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11743 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11744 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11745 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11746
11747 PIPE_CONF_CHECK_I(pixel_multiplier);
11748 PIPE_CONF_CHECK_I(has_hdmi_sink);
11749 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11750 IS_VALLEYVIEW(dev))
11751 PIPE_CONF_CHECK_I(limited_color_range);
11752 PIPE_CONF_CHECK_I(has_infoframe);
11753
11754 PIPE_CONF_CHECK_I(has_audio);
11755
11756 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11757 DRM_MODE_FLAG_INTERLACE);
11758
11759 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11760 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11761 DRM_MODE_FLAG_PHSYNC);
11762 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11763 DRM_MODE_FLAG_NHSYNC);
11764 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11765 DRM_MODE_FLAG_PVSYNC);
11766 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11767 DRM_MODE_FLAG_NVSYNC);
11768 }
11769
11770 PIPE_CONF_CHECK_I(pipe_src_w);
11771 PIPE_CONF_CHECK_I(pipe_src_h);
11772
11773 /*
11774 * FIXME: BIOS likes to set up a cloned config with lvds+external
11775 * screen. Since we don't yet re-compute the pipe config when moving
11776 * just the lvds port away to another pipe the sw tracking won't match.
11777 *
11778 * Proper atomic modesets with recomputed global state will fix this.
11779 * Until then just don't check gmch state for inherited modes.
11780 */
11781 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11782 PIPE_CONF_CHECK_I(gmch_pfit.control);
11783 /* pfit ratios are autocomputed by the hw on gen4+ */
11784 if (INTEL_INFO(dev)->gen < 4)
11785 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11786 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11787 }
11788
11789 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11790 if (current_config->pch_pfit.enabled) {
11791 PIPE_CONF_CHECK_I(pch_pfit.pos);
11792 PIPE_CONF_CHECK_I(pch_pfit.size);
11793 }
11794
11795 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11796
11797 /* BDW+ don't expose a synchronous way to read the state */
11798 if (IS_HASWELL(dev))
11799 PIPE_CONF_CHECK_I(ips_enabled);
11800
11801 PIPE_CONF_CHECK_I(double_wide);
11802
11803 PIPE_CONF_CHECK_X(ddi_pll_sel);
11804
11805 PIPE_CONF_CHECK_I(shared_dpll);
11806 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11807 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11808 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11809 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11810 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11811 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11812 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11813 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11814
11815 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11816 PIPE_CONF_CHECK_I(pipe_bpp);
11817
11818 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11819 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11820
11821#undef PIPE_CONF_CHECK_X
11822#undef PIPE_CONF_CHECK_I
11823#undef PIPE_CONF_CHECK_I_ALT
11824#undef PIPE_CONF_CHECK_FLAGS
11825#undef PIPE_CONF_CHECK_CLOCK_FUZZY
11826#undef PIPE_CONF_QUIRK
11827
11828 return true;
11829}
11830
11831static void check_wm_state(struct drm_device *dev)
11832{
11833 struct drm_i915_private *dev_priv = dev->dev_private;
11834 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11835 struct intel_crtc *intel_crtc;
11836 int plane;
11837
11838 if (INTEL_INFO(dev)->gen < 9)
11839 return;
11840
11841 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11842 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11843
11844 for_each_intel_crtc(dev, intel_crtc) {
11845 struct skl_ddb_entry *hw_entry, *sw_entry;
11846 const enum pipe pipe = intel_crtc->pipe;
11847
11848 if (!intel_crtc->active)
11849 continue;
11850
11851 /* planes */
11852 for_each_plane(dev_priv, pipe, plane) {
11853 hw_entry = &hw_ddb.plane[pipe][plane];
11854 sw_entry = &sw_ddb->plane[pipe][plane];
11855
11856 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11857 continue;
11858
11859 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11860 "(expected (%u,%u), found (%u,%u))\n",
11861 pipe_name(pipe), plane + 1,
11862 sw_entry->start, sw_entry->end,
11863 hw_entry->start, hw_entry->end);
11864 }
11865
11866 /* cursor */
11867 hw_entry = &hw_ddb.cursor[pipe];
11868 sw_entry = &sw_ddb->cursor[pipe];
11869
11870 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11871 continue;
11872
11873 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11874 "(expected (%u,%u), found (%u,%u))\n",
11875 pipe_name(pipe),
11876 sw_entry->start, sw_entry->end,
11877 hw_entry->start, hw_entry->end);
11878 }
11879}
11880
11881static void
11882check_connector_state(struct drm_device *dev)
11883{
11884 struct intel_connector *connector;
11885
11886 for_each_intel_connector(dev, connector) {
11887 /* This also checks the encoder/connector hw state with the
11888 * ->get_hw_state callbacks. */
11889 intel_connector_check_state(connector);
11890
11891 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11892 "connector's staged encoder doesn't match current encoder\n");
11893 }
11894}
11895
11896static void
11897check_encoder_state(struct drm_device *dev)
11898{
11899 struct intel_encoder *encoder;
11900 struct intel_connector *connector;
11901
11902 for_each_intel_encoder(dev, encoder) {
11903 bool enabled = false;
11904 bool active = false;
11905 enum pipe pipe, tracked_pipe;
11906
11907 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11908 encoder->base.base.id,
11909 encoder->base.name);
11910
11911 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11912 "encoder's stage crtc doesn't match current crtc\n");
11913 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11914 "encoder's active_connectors set, but no crtc\n");
11915
11916 for_each_intel_connector(dev, connector) {
11917 if (connector->base.encoder != &encoder->base)
11918 continue;
11919 enabled = true;
11920 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11921 active = true;
11922 }
11923 /*
11924 * for MST connectors if we unplug the connector is gone
11925 * away but the encoder is still connected to a crtc
11926 * until a modeset happens in response to the hotplug.
11927 */
11928 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11929 continue;
11930
11931 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11932 "encoder's enabled state mismatch "
11933 "(expected %i, found %i)\n",
11934 !!encoder->base.crtc, enabled);
11935 I915_STATE_WARN(active && !encoder->base.crtc,
11936 "active encoder with no crtc\n");
11937
11938 I915_STATE_WARN(encoder->connectors_active != active,
11939 "encoder's computed active state doesn't match tracked active state "
11940 "(expected %i, found %i)\n", active, encoder->connectors_active);
11941
11942 active = encoder->get_hw_state(encoder, &pipe);
11943 I915_STATE_WARN(active != encoder->connectors_active,
11944 "encoder's hw state doesn't match sw tracking "
11945 "(expected %i, found %i)\n",
11946 encoder->connectors_active, active);
11947
11948 if (!encoder->base.crtc)
11949 continue;
11950
11951 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11952 I915_STATE_WARN(active && pipe != tracked_pipe,
11953 "active encoder's pipe doesn't match"
11954 "(expected %i, found %i)\n",
11955 tracked_pipe, pipe);
11956
11957 }
11958}
11959
11960static void
11961check_crtc_state(struct drm_device *dev)
11962{
11963 struct drm_i915_private *dev_priv = dev->dev_private;
11964 struct intel_crtc *crtc;
11965 struct intel_encoder *encoder;
11966 struct intel_crtc_state pipe_config;
11967
11968 for_each_intel_crtc(dev, crtc) {
11969 bool enabled = false;
11970 bool active = false;
11971
11972 memset(&pipe_config, 0, sizeof(pipe_config));
11973
11974 DRM_DEBUG_KMS("[CRTC:%d]\n",
11975 crtc->base.base.id);
11976
11977 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11978 "active crtc, but not enabled in sw tracking\n");
11979
11980 for_each_intel_encoder(dev, encoder) {
11981 if (encoder->base.crtc != &crtc->base)
11982 continue;
11983 enabled = true;
11984 if (encoder->connectors_active)
11985 active = true;
11986 }
11987
11988 I915_STATE_WARN(active != crtc->active,
11989 "crtc's computed active state doesn't match tracked active state "
11990 "(expected %i, found %i)\n", active, crtc->active);
11991 I915_STATE_WARN(enabled != crtc->base.state->enable,
11992 "crtc's computed enabled state doesn't match tracked enabled state "
11993 "(expected %i, found %i)\n", enabled,
11994 crtc->base.state->enable);
11995
11996 active = dev_priv->display.get_pipe_config(crtc,
11997 &pipe_config);
11998
11999 /* hw state is inconsistent with the pipe quirk */
12000 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12001 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12002 active = crtc->active;
12003
12004 for_each_intel_encoder(dev, encoder) {
12005 enum pipe pipe;
12006 if (encoder->base.crtc != &crtc->base)
12007 continue;
12008 if (encoder->get_hw_state(encoder, &pipe))
12009 encoder->get_config(encoder, &pipe_config);
12010 }
12011
12012 I915_STATE_WARN(crtc->active != active,
12013 "crtc active state doesn't match with hw state "
12014 "(expected %i, found %i)\n", crtc->active, active);
12015
12016 if (active &&
12017 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12018 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12019 intel_dump_pipe_config(crtc, &pipe_config,
12020 "[hw state]");
12021 intel_dump_pipe_config(crtc, crtc->config,
12022 "[sw state]");
12023 }
12024 }
12025}
12026
12027static void
12028check_shared_dpll_state(struct drm_device *dev)
12029{
12030 struct drm_i915_private *dev_priv = dev->dev_private;
12031 struct intel_crtc *crtc;
12032 struct intel_dpll_hw_state dpll_hw_state;
12033 int i;
12034
12035 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12036 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12037 int enabled_crtcs = 0, active_crtcs = 0;
12038 bool active;
12039
12040 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12041
12042 DRM_DEBUG_KMS("%s\n", pll->name);
12043
12044 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12045
12046 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12047 "more active pll users than references: %i vs %i\n",
12048 pll->active, hweight32(pll->config.crtc_mask));
12049 I915_STATE_WARN(pll->active && !pll->on,
12050 "pll in active use but not on in sw tracking\n");
12051 I915_STATE_WARN(pll->on && !pll->active,
12052 "pll in on but not on in use in sw tracking\n");
12053 I915_STATE_WARN(pll->on != active,
12054 "pll on state mismatch (expected %i, found %i)\n",
12055 pll->on, active);
12056
12057 for_each_intel_crtc(dev, crtc) {
12058 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12059 enabled_crtcs++;
12060 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12061 active_crtcs++;
12062 }
12063 I915_STATE_WARN(pll->active != active_crtcs,
12064 "pll active crtcs mismatch (expected %i, found %i)\n",
12065 pll->active, active_crtcs);
12066 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12067 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12068 hweight32(pll->config.crtc_mask), enabled_crtcs);
12069
12070 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12071 sizeof(dpll_hw_state)),
12072 "pll hw state mismatch\n");
12073 }
12074}
12075
12076void
12077intel_modeset_check_state(struct drm_device *dev)
12078{
12079 check_wm_state(dev);
12080 check_connector_state(dev);
12081 check_encoder_state(dev);
12082 check_crtc_state(dev);
12083 check_shared_dpll_state(dev);
12084}
12085
12086void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12087 int dotclock)
12088{
12089 /*
12090 * FDI already provided one idea for the dotclock.
12091 * Yell if the encoder disagrees.
12092 */
12093 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12094 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12095 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12096}
12097
12098static void update_scanline_offset(struct intel_crtc *crtc)
12099{
12100 struct drm_device *dev = crtc->base.dev;
12101
12102 /*
12103 * The scanline counter increments at the leading edge of hsync.
12104 *
12105 * On most platforms it starts counting from vtotal-1 on the
12106 * first active line. That means the scanline counter value is
12107 * always one less than what we would expect. Ie. just after
12108 * start of vblank, which also occurs at start of hsync (on the
12109 * last active line), the scanline counter will read vblank_start-1.
12110 *
12111 * On gen2 the scanline counter starts counting from 1 instead
12112 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12113 * to keep the value positive), instead of adding one.
12114 *
12115 * On HSW+ the behaviour of the scanline counter depends on the output
12116 * type. For DP ports it behaves like most other platforms, but on HDMI
12117 * there's an extra 1 line difference. So we need to add two instead of
12118 * one to the value.
12119 */
12120 if (IS_GEN2(dev)) {
12121 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12122 int vtotal;
12123
12124 vtotal = mode->crtc_vtotal;
12125 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12126 vtotal /= 2;
12127
12128 crtc->scanline_offset = vtotal - 1;
12129 } else if (HAS_DDI(dev) &&
12130 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12131 crtc->scanline_offset = 2;
12132 } else
12133 crtc->scanline_offset = 1;
12134}
12135
12136static void
12137intel_atomic_modeset_compute_changed_flags(struct drm_atomic_state *state,
12138 struct drm_crtc *modeset_crtc)
12139{
12140 struct drm_crtc_state *crtc_state;
12141 struct drm_crtc *crtc;
12142 int i;
12143
12144 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12145 if (crtc_state->enable != crtc->state->enable)
12146 crtc_state->mode_changed = true;
12147
12148 /* FIXME: Do we need to always set mode_changed for
12149 * modeset_crtc if it is enabled? modeset_affect_pipes()
12150 * did that. */
12151 }
12152}
12153
12154static struct intel_crtc_state *
12155intel_modeset_compute_config(struct drm_crtc *crtc,
12156 struct drm_display_mode *mode,
12157 struct drm_atomic_state *state)
12158{
12159 struct intel_crtc_state *pipe_config;
12160 int ret = 0;
12161
12162 ret = drm_atomic_add_affected_connectors(state, crtc);
12163 if (ret)
12164 return ERR_PTR(ret);
12165
12166 intel_atomic_modeset_compute_changed_flags(state, crtc);
12167
12168 /*
12169 * Note this needs changes when we start tracking multiple modes
12170 * and crtcs. At that point we'll need to compute the whole config
12171 * (i.e. one pipe_config for each crtc) rather than just the one
12172 * for this crtc.
12173 */
12174 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12175 if (IS_ERR(pipe_config))
12176 return pipe_config;
12177
12178 if (!pipe_config->base.enable)
12179 return pipe_config;
12180
12181 ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config);
12182 if (ret)
12183 return ERR_PTR(ret);
12184
12185 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12186
12187 return pipe_config;
12188}
12189
12190static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12191{
12192 struct drm_device *dev = state->dev;
12193 struct drm_i915_private *dev_priv = to_i915(dev);
12194 unsigned clear_pipes = 0;
12195 struct intel_crtc *intel_crtc;
12196 struct intel_crtc_state *intel_crtc_state;
12197 struct drm_crtc *crtc;
12198 struct drm_crtc_state *crtc_state;
12199 int ret = 0;
12200 int i;
12201
12202 if (!dev_priv->display.crtc_compute_clock)
12203 return 0;
12204
12205 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12206 intel_crtc = to_intel_crtc(crtc);
12207
12208 if (needs_modeset(crtc_state))
12209 clear_pipes |= 1 << intel_crtc->pipe;
12210 }
12211
12212 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12213 if (ret)
12214 goto done;
12215
12216 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12217 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12218 continue;
12219
12220 intel_crtc = to_intel_crtc(crtc);
12221 intel_crtc_state = to_intel_crtc_state(crtc_state);
12222
12223 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12224 intel_crtc_state);
12225 if (ret) {
12226 intel_shared_dpll_abort_config(dev_priv);
12227 goto done;
12228 }
12229 }
12230
12231done:
12232 return ret;
12233}
12234
12235static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12236 struct drm_display_mode *mode,
12237 int x, int y, struct drm_framebuffer *fb,
12238 struct intel_crtc_state *pipe_config)
12239{
12240 struct drm_device *dev = modeset_crtc->dev;
12241 struct drm_i915_private *dev_priv = dev->dev_private;
12242 struct drm_atomic_state *state = pipe_config->base.state;
12243 struct intel_crtc_state *crtc_state_copy = NULL;
12244 struct intel_crtc *intel_crtc;
12245 struct drm_crtc *crtc;
12246 struct drm_crtc_state *crtc_state;
12247 int ret = 0;
12248 int i;
12249
12250 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12251 if (!crtc_state_copy) {
12252 ret = -ENOMEM;
12253 goto done;
12254 }
12255
12256 /*
12257 * See if the config requires any additional preparation, e.g.
12258 * to adjust global state with pipes off. We need to do this
12259 * here so we can get the modeset_pipe updated config for the new
12260 * mode set on this crtc. For other crtcs we need to use the
12261 * adjusted_mode bits in the crtc directly.
12262 */
12263 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12264 ret = valleyview_modeset_global_pipes(state);
12265 if (ret)
12266 goto done;
12267 }
12268
12269 ret = __intel_set_mode_setup_plls(state);
12270 if (ret)
12271 goto done;
12272
12273 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12274 if (!needs_modeset(crtc_state))
12275 continue;
12276
12277 if (!crtc_state->enable) {
12278 intel_crtc_disable(crtc);
12279 } else if (crtc->state->enable) {
12280 intel_crtc_disable_planes(crtc);
12281 dev_priv->display.crtc_disable(crtc);
12282 }
12283 }
12284
12285 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12286 * to set it here already despite that we pass it down the callchain.
12287 *
12288 * Note we'll need to fix this up when we start tracking multiple
12289 * pipes; here we assume a single modeset_pipe and only track the
12290 * single crtc and mode.
12291 */
12292 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12293 modeset_crtc->mode = *mode;
12294 /* mode_set/enable/disable functions rely on a correct pipe
12295 * config. */
12296 intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config);
12297
12298 /*
12299 * Calculate and store various constants which
12300 * are later needed by vblank and swap-completion
12301 * timestamping. They are derived from true hwmode.
12302 */
12303 drm_calc_timestamping_constants(modeset_crtc,
12304 &pipe_config->base.adjusted_mode);
12305 }
12306
12307 /* Only after disabling all output pipelines that will be changed can we
12308 * update the the output configuration. */
12309 intel_modeset_update_state(state);
12310
12311 modeset_update_crtc_power_domains(state);
12312
12313 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12314 struct drm_plane *primary;
12315 int vdisplay, hdisplay;
12316
12317 intel_crtc = to_intel_crtc(modeset_crtc);
12318 primary = intel_crtc->base.primary;
12319
12320 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
12321
12322 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12323 fb, 0, 0,
12324 hdisplay, vdisplay,
12325 x << 16, y << 16,
12326 hdisplay << 16, vdisplay << 16);
12327 }
12328
12329 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12330 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12331 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12332 continue;
12333
12334 update_scanline_offset(to_intel_crtc(crtc));
12335
12336 dev_priv->display.crtc_enable(crtc);
12337 intel_crtc_enable_planes(crtc);
12338 }
12339
12340 /* FIXME: add subpixel order */
12341done:
12342 if (ret == 0 && pipe_config) {
12343 struct intel_crtc *intel_crtc = to_intel_crtc(modeset_crtc);
12344
12345 /* The pipe_config will be freed with the atomic state, so
12346 * make a copy. */
12347 memcpy(crtc_state_copy, intel_crtc->config,
12348 sizeof *crtc_state_copy);
12349 intel_crtc->config = crtc_state_copy;
12350 intel_crtc->base.state = &crtc_state_copy->base;
12351 } else {
12352 kfree(crtc_state_copy);
12353 }
12354
12355 return ret;
12356}
12357
12358static int intel_set_mode_with_config(struct drm_crtc *crtc,
12359 struct drm_display_mode *mode,
12360 int x, int y, struct drm_framebuffer *fb,
12361 struct intel_crtc_state *pipe_config)
12362{
12363 int ret;
12364
12365 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config);
12366
12367 if (ret == 0)
12368 intel_modeset_check_state(crtc->dev);
12369
12370 return ret;
12371}
12372
12373static int intel_set_mode(struct drm_crtc *crtc,
12374 struct drm_display_mode *mode,
12375 int x, int y, struct drm_framebuffer *fb,
12376 struct drm_atomic_state *state)
12377{
12378 struct intel_crtc_state *pipe_config;
12379 int ret = 0;
12380
12381 pipe_config = intel_modeset_compute_config(crtc, mode, state);
12382 if (IS_ERR(pipe_config)) {
12383 ret = PTR_ERR(pipe_config);
12384 goto out;
12385 }
12386
12387 ret = intel_set_mode_with_config(crtc, mode, x, y, fb, pipe_config);
12388 if (ret)
12389 goto out;
12390
12391out:
12392 return ret;
12393}
12394
12395void intel_crtc_restore_mode(struct drm_crtc *crtc)
12396{
12397 struct drm_device *dev = crtc->dev;
12398 struct drm_atomic_state *state;
12399 struct intel_crtc *intel_crtc;
12400 struct intel_encoder *encoder;
12401 struct intel_connector *connector;
12402 struct drm_connector_state *connector_state;
12403 struct intel_crtc_state *crtc_state;
12404
12405 state = drm_atomic_state_alloc(dev);
12406 if (!state) {
12407 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12408 crtc->base.id);
12409 return;
12410 }
12411
12412 state->acquire_ctx = dev->mode_config.acquire_ctx;
12413
12414 /* The force restore path in the HW readout code relies on the staged
12415 * config still keeping the user requested config while the actual
12416 * state has been overwritten by the configuration read from HW. We
12417 * need to copy the staged config to the atomic state, otherwise the
12418 * mode set will just reapply the state the HW is already in. */
12419 for_each_intel_encoder(dev, encoder) {
12420 if (&encoder->new_crtc->base != crtc)
12421 continue;
12422
12423 for_each_intel_connector(dev, connector) {
12424 if (connector->new_encoder != encoder)
12425 continue;
12426
12427 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12428 if (IS_ERR(connector_state)) {
12429 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12430 connector->base.base.id,
12431 connector->base.name,
12432 PTR_ERR(connector_state));
12433 continue;
12434 }
12435
12436 connector_state->crtc = crtc;
12437 connector_state->best_encoder = &encoder->base;
12438 }
12439 }
12440
12441 for_each_intel_crtc(dev, intel_crtc) {
12442 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12443 continue;
12444
12445 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12446 if (IS_ERR(crtc_state)) {
12447 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12448 intel_crtc->base.base.id,
12449 PTR_ERR(crtc_state));
12450 continue;
12451 }
12452
12453 crtc_state->base.enable = intel_crtc->new_enabled;
12454 }
12455
12456 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12457 state);
12458
12459 drm_atomic_state_free(state);
12460}
12461
12462#undef for_each_intel_crtc_masked
12463
12464static void intel_set_config_free(struct intel_set_config *config)
12465{
12466 if (!config)
12467 return;
12468
12469 kfree(config->save_connector_encoders);
12470 kfree(config->save_encoder_crtcs);
12471 kfree(config->save_crtc_enabled);
12472 kfree(config);
12473}
12474
12475static int intel_set_config_save_state(struct drm_device *dev,
12476 struct intel_set_config *config)
12477{
12478 struct drm_crtc *crtc;
12479 struct drm_encoder *encoder;
12480 struct drm_connector *connector;
12481 int count;
12482
12483 config->save_crtc_enabled =
12484 kcalloc(dev->mode_config.num_crtc,
12485 sizeof(bool), GFP_KERNEL);
12486 if (!config->save_crtc_enabled)
12487 return -ENOMEM;
12488
12489 config->save_encoder_crtcs =
12490 kcalloc(dev->mode_config.num_encoder,
12491 sizeof(struct drm_crtc *), GFP_KERNEL);
12492 if (!config->save_encoder_crtcs)
12493 return -ENOMEM;
12494
12495 config->save_connector_encoders =
12496 kcalloc(dev->mode_config.num_connector,
12497 sizeof(struct drm_encoder *), GFP_KERNEL);
12498 if (!config->save_connector_encoders)
12499 return -ENOMEM;
12500
12501 /* Copy data. Note that driver private data is not affected.
12502 * Should anything bad happen only the expected state is
12503 * restored, not the drivers personal bookkeeping.
12504 */
12505 count = 0;
12506 for_each_crtc(dev, crtc) {
12507 config->save_crtc_enabled[count++] = crtc->state->enable;
12508 }
12509
12510 count = 0;
12511 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
12512 config->save_encoder_crtcs[count++] = encoder->crtc;
12513 }
12514
12515 count = 0;
12516 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12517 config->save_connector_encoders[count++] = connector->encoder;
12518 }
12519
12520 return 0;
12521}
12522
12523static void intel_set_config_restore_state(struct drm_device *dev,
12524 struct intel_set_config *config)
12525{
12526 struct intel_crtc *crtc;
12527 struct intel_encoder *encoder;
12528 struct intel_connector *connector;
12529 int count;
12530
12531 count = 0;
12532 for_each_intel_crtc(dev, crtc) {
12533 crtc->new_enabled = config->save_crtc_enabled[count++];
12534 }
12535
12536 count = 0;
12537 for_each_intel_encoder(dev, encoder) {
12538 encoder->new_crtc =
12539 to_intel_crtc(config->save_encoder_crtcs[count++]);
12540 }
12541
12542 count = 0;
12543 for_each_intel_connector(dev, connector) {
12544 connector->new_encoder =
12545 to_intel_encoder(config->save_connector_encoders[count++]);
12546 }
12547}
12548
12549static bool
12550is_crtc_connector_off(struct drm_mode_set *set)
12551{
12552 int i;
12553
12554 if (set->num_connectors == 0)
12555 return false;
12556
12557 if (WARN_ON(set->connectors == NULL))
12558 return false;
12559
12560 for (i = 0; i < set->num_connectors; i++)
12561 if (set->connectors[i]->encoder &&
12562 set->connectors[i]->encoder->crtc == set->crtc &&
12563 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
12564 return true;
12565
12566 return false;
12567}
12568
12569static void
12570intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12571 struct intel_set_config *config)
12572{
12573 struct drm_device *dev = set->crtc->dev;
12574 struct intel_connector *connector;
12575 struct intel_encoder *encoder;
12576 struct intel_crtc *crtc;
12577
12578 /* We should be able to check here if the fb has the same properties
12579 * and then just flip_or_move it */
12580 if (is_crtc_connector_off(set)) {
12581 config->mode_changed = true;
12582 } else if (set->crtc->primary->fb != set->fb) {
12583 /*
12584 * If we have no fb, we can only flip as long as the crtc is
12585 * active, otherwise we need a full mode set. The crtc may
12586 * be active if we've only disabled the primary plane, or
12587 * in fastboot situations.
12588 */
12589 if (set->crtc->primary->fb == NULL) {
12590 struct intel_crtc *intel_crtc =
12591 to_intel_crtc(set->crtc);
12592
12593 if (intel_crtc->active) {
12594 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12595 config->fb_changed = true;
12596 } else {
12597 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12598 config->mode_changed = true;
12599 }
12600 } else if (set->fb == NULL) {
12601 config->mode_changed = true;
12602 } else if (set->fb->pixel_format !=
12603 set->crtc->primary->fb->pixel_format) {
12604 config->mode_changed = true;
12605 } else {
12606 config->fb_changed = true;
12607 }
12608 }
12609
12610 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
12611 config->fb_changed = true;
12612
12613 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12614 DRM_DEBUG_KMS("modes are different, full mode set\n");
12615 drm_mode_debug_printmodeline(&set->crtc->mode);
12616 drm_mode_debug_printmodeline(set->mode);
12617 config->mode_changed = true;
12618 }
12619
12620 for_each_intel_connector(dev, connector) {
12621 if (&connector->new_encoder->base == connector->base.encoder)
12622 continue;
12623
12624 config->mode_changed = true;
12625 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12626 connector->base.base.id,
12627 connector->base.name);
12628 }
12629
12630 for_each_intel_encoder(dev, encoder) {
12631 if (&encoder->new_crtc->base == encoder->base.crtc)
12632 continue;
12633
12634 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12635 encoder->base.base.id,
12636 encoder->base.name);
12637 config->mode_changed = true;
12638 }
12639
12640 for_each_intel_crtc(dev, crtc) {
12641 if (crtc->new_enabled == crtc->base.state->enable)
12642 continue;
12643
12644 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12645 crtc->base.base.id,
12646 crtc->new_enabled ? "en" : "dis");
12647 config->mode_changed = true;
12648 }
12649
12650 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12651 set->crtc->base.id, config->mode_changed, config->fb_changed);
12652}
12653
12654static int
12655intel_modeset_stage_output_state(struct drm_device *dev,
12656 struct drm_mode_set *set,
12657 struct drm_atomic_state *state)
12658{
12659 struct intel_connector *connector;
12660 struct drm_connector_state *connector_state;
12661 struct intel_encoder *encoder;
12662 struct intel_crtc *crtc;
12663 struct intel_crtc_state *crtc_state;
12664 int ro;
12665
12666 /* The upper layers ensure that we either disable a crtc or have a list
12667 * of connectors. For paranoia, double-check this. */
12668 WARN_ON(!set->fb && (set->num_connectors != 0));
12669 WARN_ON(set->fb && (set->num_connectors == 0));
12670
12671 for_each_intel_connector(dev, connector) {
12672 /* Otherwise traverse passed in connector list and get encoders
12673 * for them. */
12674 for (ro = 0; ro < set->num_connectors; ro++) {
12675 if (set->connectors[ro] == &connector->base) {
12676 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
12677 break;
12678 }
12679 }
12680
12681 /* If we disable the crtc, disable all its connectors. Also, if
12682 * the connector is on the changing crtc but not on the new
12683 * connector list, disable it. */
12684 if ((!set->fb || ro == set->num_connectors) &&
12685 connector->base.encoder &&
12686 connector->base.encoder->crtc == set->crtc) {
12687 connector->new_encoder = NULL;
12688
12689 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12690 connector->base.base.id,
12691 connector->base.name);
12692 }
12693 }
12694 /* connector->new_encoder is now updated for all connectors. */
12695
12696 /* Update crtc of enabled connectors. */
12697 for_each_intel_connector(dev, connector) {
12698 struct drm_crtc *new_crtc;
12699
12700 if (!connector->new_encoder)
12701 continue;
12702
12703 new_crtc = connector->new_encoder->base.crtc;
12704
12705 for (ro = 0; ro < set->num_connectors; ro++) {
12706 if (set->connectors[ro] == &connector->base)
12707 new_crtc = set->crtc;
12708 }
12709
12710 /* Make sure the new CRTC will work with the encoder */
12711 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12712 new_crtc)) {
12713 return -EINVAL;
12714 }
12715 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
12716
12717 connector_state =
12718 drm_atomic_get_connector_state(state, &connector->base);
12719 if (IS_ERR(connector_state))
12720 return PTR_ERR(connector_state);
12721
12722 connector_state->crtc = new_crtc;
12723 connector_state->best_encoder = &connector->new_encoder->base;
12724
12725 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12726 connector->base.base.id,
12727 connector->base.name,
12728 new_crtc->base.id);
12729 }
12730
12731 /* Check for any encoders that needs to be disabled. */
12732 for_each_intel_encoder(dev, encoder) {
12733 int num_connectors = 0;
12734 for_each_intel_connector(dev, connector) {
12735 if (connector->new_encoder == encoder) {
12736 WARN_ON(!connector->new_encoder->new_crtc);
12737 num_connectors++;
12738 }
12739 }
12740
12741 if (num_connectors == 0)
12742 encoder->new_crtc = NULL;
12743 else if (num_connectors > 1)
12744 return -EINVAL;
12745 }
12746 /* Now we've also updated encoder->new_crtc for all encoders. */
12747 for_each_intel_connector(dev, connector) {
12748 connector_state =
12749 drm_atomic_get_connector_state(state, &connector->base);
12750 if (IS_ERR(connector_state))
12751 return PTR_ERR(connector_state);
12752
12753 if (connector->new_encoder) {
12754 if (connector->new_encoder != connector->encoder)
12755 connector->encoder = connector->new_encoder;
12756 } else {
12757 connector_state->crtc = NULL;
12758 connector_state->best_encoder = NULL;
12759 }
12760 }
12761 for_each_intel_crtc(dev, crtc) {
12762 crtc->new_enabled = false;
12763
12764 for_each_intel_encoder(dev, encoder) {
12765 if (encoder->new_crtc == crtc) {
12766 crtc->new_enabled = true;
12767 break;
12768 }
12769 }
12770
12771 if (crtc->new_enabled != crtc->base.state->enable) {
12772 crtc_state = intel_atomic_get_crtc_state(state, crtc);
12773 if (IS_ERR(crtc_state))
12774 return PTR_ERR(crtc_state);
12775
12776 crtc_state->base.enable = crtc->new_enabled;
12777 }
12778 }
12779
12780 return 0;
12781}
12782
12783static void disable_crtc_nofb(struct intel_crtc *crtc)
12784{
12785 struct drm_device *dev = crtc->base.dev;
12786 struct intel_encoder *encoder;
12787 struct intel_connector *connector;
12788
12789 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12790 pipe_name(crtc->pipe));
12791
12792 for_each_intel_connector(dev, connector) {
12793 if (connector->new_encoder &&
12794 connector->new_encoder->new_crtc == crtc)
12795 connector->new_encoder = NULL;
12796 }
12797
12798 for_each_intel_encoder(dev, encoder) {
12799 if (encoder->new_crtc == crtc)
12800 encoder->new_crtc = NULL;
12801 }
12802
12803 crtc->new_enabled = false;
12804}
12805
12806static int intel_crtc_set_config(struct drm_mode_set *set)
12807{
12808 struct drm_device *dev;
12809 struct drm_mode_set save_set;
12810 struct drm_atomic_state *state = NULL;
12811 struct intel_set_config *config;
12812 struct intel_crtc_state *pipe_config;
12813 int ret;
12814
12815 BUG_ON(!set);
12816 BUG_ON(!set->crtc);
12817 BUG_ON(!set->crtc->helper_private);
12818
12819 /* Enforce sane interface api - has been abused by the fb helper. */
12820 BUG_ON(!set->mode && set->fb);
12821 BUG_ON(set->fb && set->num_connectors == 0);
12822
12823 if (set->fb) {
12824 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12825 set->crtc->base.id, set->fb->base.id,
12826 (int)set->num_connectors, set->x, set->y);
12827 } else {
12828 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12829 }
12830
12831 dev = set->crtc->dev;
12832
12833 ret = -ENOMEM;
12834 config = kzalloc(sizeof(*config), GFP_KERNEL);
12835 if (!config)
12836 goto out_config;
12837
12838 ret = intel_set_config_save_state(dev, config);
12839 if (ret)
12840 goto out_config;
12841
12842 save_set.crtc = set->crtc;
12843 save_set.mode = &set->crtc->mode;
12844 save_set.x = set->crtc->x;
12845 save_set.y = set->crtc->y;
12846 save_set.fb = set->crtc->primary->fb;
12847
12848 state = drm_atomic_state_alloc(dev);
12849 if (!state) {
12850 ret = -ENOMEM;
12851 goto out_config;
12852 }
12853
12854 state->acquire_ctx = dev->mode_config.acquire_ctx;
12855
12856 ret = intel_modeset_stage_output_state(dev, set, state);
12857 if (ret)
12858 goto fail;
12859
12860 /* Compute whether we need a full modeset, only an fb base update or no
12861 * change at all. In the future we might also check whether only the
12862 * mode changed, e.g. for LVDS where we only change the panel fitter in
12863 * such cases. */
12864 intel_set_config_compute_mode_changes(set, config);
12865
12866 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12867 state);
12868 if (IS_ERR(pipe_config)) {
12869 ret = PTR_ERR(pipe_config);
12870 goto fail;
12871 } else if (pipe_config) {
12872 if (pipe_config->has_audio !=
12873 to_intel_crtc(set->crtc)->config->has_audio)
12874 config->mode_changed = true;
12875
12876 /*
12877 * Note we have an issue here with infoframes: current code
12878 * only updates them on the full mode set path per hw
12879 * requirements. So here we should be checking for any
12880 * required changes and forcing a mode set.
12881 */
12882 }
12883
12884 intel_update_pipe_size(to_intel_crtc(set->crtc));
12885
12886 if (config->mode_changed) {
12887 ret = intel_set_mode_with_config(set->crtc, set->mode,
12888 set->x, set->y, set->fb,
12889 pipe_config);
12890 } else if (config->fb_changed) {
12891 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12892 struct drm_plane *primary = set->crtc->primary;
12893 struct intel_plane_state *plane_state =
12894 to_intel_plane_state(primary->state);
12895 bool was_visible = plane_state->visible;
12896 int vdisplay, hdisplay;
12897
12898 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12899 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12900 0, 0, hdisplay, vdisplay,
12901 set->x << 16, set->y << 16,
12902 hdisplay << 16, vdisplay << 16);
12903
12904 /*
12905 * We need to make sure the primary plane is re-enabled if it
12906 * has previously been turned off.
12907 */
12908 plane_state = to_intel_plane_state(primary->state);
12909 if (ret == 0 && !was_visible && plane_state->visible) {
12910 WARN_ON(!intel_crtc->active);
12911 intel_post_enable_primary(set->crtc);
12912 }
12913
12914 /*
12915 * In the fastboot case this may be our only check of the
12916 * state after boot. It would be better to only do it on
12917 * the first update, but we don't have a nice way of doing that
12918 * (and really, set_config isn't used much for high freq page
12919 * flipping, so increasing its cost here shouldn't be a big
12920 * deal).
12921 */
12922 if (i915.fastboot && ret == 0)
12923 intel_modeset_check_state(set->crtc->dev);
12924 }
12925
12926 if (ret) {
12927 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12928 set->crtc->base.id, ret);
12929fail:
12930 intel_set_config_restore_state(dev, config);
12931
12932 drm_atomic_state_clear(state);
12933
12934 /*
12935 * HACK: if the pipe was on, but we didn't have a framebuffer,
12936 * force the pipe off to avoid oopsing in the modeset code
12937 * due to fb==NULL. This should only happen during boot since
12938 * we don't yet reconstruct the FB from the hardware state.
12939 */
12940 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12941 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12942
12943 /* Try to restore the config */
12944 if (config->mode_changed &&
12945 intel_set_mode(save_set.crtc, save_set.mode,
12946 save_set.x, save_set.y, save_set.fb,
12947 state))
12948 DRM_ERROR("failed to restore config after modeset failure\n");
12949 }
12950
12951out_config:
12952 drm_atomic_state_free(state);
12953
12954 intel_set_config_free(config);
12955 return ret;
12956}
12957
12958static const struct drm_crtc_funcs intel_crtc_funcs = {
12959 .gamma_set = intel_crtc_gamma_set,
12960 .set_config = intel_crtc_set_config,
12961 .destroy = intel_crtc_destroy,
12962 .page_flip = intel_crtc_page_flip,
12963 .atomic_duplicate_state = intel_crtc_duplicate_state,
12964 .atomic_destroy_state = intel_crtc_destroy_state,
12965};
12966
12967static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12968 struct intel_shared_dpll *pll,
12969 struct intel_dpll_hw_state *hw_state)
12970{
12971 uint32_t val;
12972
12973 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12974 return false;
12975
12976 val = I915_READ(PCH_DPLL(pll->id));
12977 hw_state->dpll = val;
12978 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12979 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12980
12981 return val & DPLL_VCO_ENABLE;
12982}
12983
12984static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12985 struct intel_shared_dpll *pll)
12986{
12987 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12988 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12989}
12990
12991static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12992 struct intel_shared_dpll *pll)
12993{
12994 /* PCH refclock must be enabled first */
12995 ibx_assert_pch_refclk_enabled(dev_priv);
12996
12997 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12998
12999 /* Wait for the clocks to stabilize. */
13000 POSTING_READ(PCH_DPLL(pll->id));
13001 udelay(150);
13002
13003 /* The pixel multiplier can only be updated once the
13004 * DPLL is enabled and the clocks are stable.
13005 *
13006 * So write it again.
13007 */
13008 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13009 POSTING_READ(PCH_DPLL(pll->id));
13010 udelay(200);
13011}
13012
13013static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13014 struct intel_shared_dpll *pll)
13015{
13016 struct drm_device *dev = dev_priv->dev;
13017 struct intel_crtc *crtc;
13018
13019 /* Make sure no transcoder isn't still depending on us. */
13020 for_each_intel_crtc(dev, crtc) {
13021 if (intel_crtc_to_shared_dpll(crtc) == pll)
13022 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13023 }
13024
13025 I915_WRITE(PCH_DPLL(pll->id), 0);
13026 POSTING_READ(PCH_DPLL(pll->id));
13027 udelay(200);
13028}
13029
13030static char *ibx_pch_dpll_names[] = {
13031 "PCH DPLL A",
13032 "PCH DPLL B",
13033};
13034
13035static void ibx_pch_dpll_init(struct drm_device *dev)
13036{
13037 struct drm_i915_private *dev_priv = dev->dev_private;
13038 int i;
13039
13040 dev_priv->num_shared_dpll = 2;
13041
13042 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13043 dev_priv->shared_dplls[i].id = i;
13044 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13045 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13046 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13047 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13048 dev_priv->shared_dplls[i].get_hw_state =
13049 ibx_pch_dpll_get_hw_state;
13050 }
13051}
13052
13053static void intel_shared_dpll_init(struct drm_device *dev)
13054{
13055 struct drm_i915_private *dev_priv = dev->dev_private;
13056
13057 if (HAS_DDI(dev))
13058 intel_ddi_pll_init(dev);
13059 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13060 ibx_pch_dpll_init(dev);
13061 else
13062 dev_priv->num_shared_dpll = 0;
13063
13064 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13065}
13066
13067/**
13068 * intel_wm_need_update - Check whether watermarks need updating
13069 * @plane: drm plane
13070 * @state: new plane state
13071 *
13072 * Check current plane state versus the new one to determine whether
13073 * watermarks need to be recalculated.
13074 *
13075 * Returns true or false.
13076 */
13077bool intel_wm_need_update(struct drm_plane *plane,
13078 struct drm_plane_state *state)
13079{
13080 /* Update watermarks on tiling changes. */
13081 if (!plane->state->fb || !state->fb ||
13082 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13083 plane->state->rotation != state->rotation)
13084 return true;
13085
13086 return false;
13087}
13088
13089/**
13090 * intel_prepare_plane_fb - Prepare fb for usage on plane
13091 * @plane: drm plane to prepare for
13092 * @fb: framebuffer to prepare for presentation
13093 *
13094 * Prepares a framebuffer for usage on a display plane. Generally this
13095 * involves pinning the underlying object and updating the frontbuffer tracking
13096 * bits. Some older platforms need special physical address handling for
13097 * cursor planes.
13098 *
13099 * Returns 0 on success, negative error code on failure.
13100 */
13101int
13102intel_prepare_plane_fb(struct drm_plane *plane,
13103 struct drm_framebuffer *fb,
13104 const struct drm_plane_state *new_state)
13105{
13106 struct drm_device *dev = plane->dev;
13107 struct intel_plane *intel_plane = to_intel_plane(plane);
13108 enum pipe pipe = intel_plane->pipe;
13109 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13110 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13111 unsigned frontbuffer_bits = 0;
13112 int ret = 0;
13113
13114 if (!obj)
13115 return 0;
13116
13117 switch (plane->type) {
13118 case DRM_PLANE_TYPE_PRIMARY:
13119 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13120 break;
13121 case DRM_PLANE_TYPE_CURSOR:
13122 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13123 break;
13124 case DRM_PLANE_TYPE_OVERLAY:
13125 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13126 break;
13127 }
13128
13129 mutex_lock(&dev->struct_mutex);
13130
13131 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13132 INTEL_INFO(dev)->cursor_needs_physical) {
13133 int align = IS_I830(dev) ? 16 * 1024 : 256;
13134 ret = i915_gem_object_attach_phys(obj, align);
13135 if (ret)
13136 DRM_DEBUG_KMS("failed to attach phys object\n");
13137 } else {
13138 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13139 }
13140
13141 if (ret == 0)
13142 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13143
13144 mutex_unlock(&dev->struct_mutex);
13145
13146 return ret;
13147}
13148
13149/**
13150 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13151 * @plane: drm plane to clean up for
13152 * @fb: old framebuffer that was on plane
13153 *
13154 * Cleans up a framebuffer that has just been removed from a plane.
13155 */
13156void
13157intel_cleanup_plane_fb(struct drm_plane *plane,
13158 struct drm_framebuffer *fb,
13159 const struct drm_plane_state *old_state)
13160{
13161 struct drm_device *dev = plane->dev;
13162 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13163
13164 if (WARN_ON(!obj))
13165 return;
13166
13167 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13168 !INTEL_INFO(dev)->cursor_needs_physical) {
13169 mutex_lock(&dev->struct_mutex);
13170 intel_unpin_fb_obj(fb, old_state);
13171 mutex_unlock(&dev->struct_mutex);
13172 }
13173}
13174
13175int
13176skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13177{
13178 int max_scale;
13179 struct drm_device *dev;
13180 struct drm_i915_private *dev_priv;
13181 int crtc_clock, cdclk;
13182
13183 if (!intel_crtc || !crtc_state)
13184 return DRM_PLANE_HELPER_NO_SCALING;
13185
13186 dev = intel_crtc->base.dev;
13187 dev_priv = dev->dev_private;
13188 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13189 cdclk = dev_priv->display.get_display_clock_speed(dev);
13190
13191 if (!crtc_clock || !cdclk)
13192 return DRM_PLANE_HELPER_NO_SCALING;
13193
13194 /*
13195 * skl max scale is lower of:
13196 * close to 3 but not 3, -1 is for that purpose
13197 * or
13198 * cdclk/crtc_clock
13199 */
13200 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13201
13202 return max_scale;
13203}
13204
13205static int
13206intel_check_primary_plane(struct drm_plane *plane,
13207 struct intel_plane_state *state)
13208{
13209 struct drm_device *dev = plane->dev;
13210 struct drm_i915_private *dev_priv = dev->dev_private;
13211 struct drm_crtc *crtc = state->base.crtc;
13212 struct intel_crtc *intel_crtc;
13213 struct intel_crtc_state *crtc_state;
13214 struct drm_framebuffer *fb = state->base.fb;
13215 struct drm_rect *dest = &state->dst;
13216 struct drm_rect *src = &state->src;
13217 const struct drm_rect *clip = &state->clip;
13218 bool can_position = false;
13219 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13220 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13221 int ret;
13222
13223 crtc = crtc ? crtc : plane->crtc;
13224 intel_crtc = to_intel_crtc(crtc);
13225 crtc_state = state->base.state ?
13226 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13227
13228 if (INTEL_INFO(dev)->gen >= 9) {
13229 min_scale = 1;
13230 max_scale = skl_max_scale(intel_crtc, crtc_state);
13231 can_position = true;
13232 }
13233
13234 ret = drm_plane_helper_check_update(plane, crtc, fb,
13235 src, dest, clip,
13236 min_scale,
13237 max_scale,
13238 can_position, true,
13239 &state->visible);
13240 if (ret)
13241 return ret;
13242
13243 if (intel_crtc->active) {
13244 struct intel_plane_state *old_state =
13245 to_intel_plane_state(plane->state);
13246
13247 intel_crtc->atomic.wait_for_flips = true;
13248
13249 /*
13250 * FBC does not work on some platforms for rotated
13251 * planes, so disable it when rotation is not 0 and
13252 * update it when rotation is set back to 0.
13253 *
13254 * FIXME: This is redundant with the fbc update done in
13255 * the primary plane enable function except that that
13256 * one is done too late. We eventually need to unify
13257 * this.
13258 */
13259 if (state->visible &&
13260 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13261 dev_priv->fbc.crtc == intel_crtc &&
13262 state->base.rotation != BIT(DRM_ROTATE_0)) {
13263 intel_crtc->atomic.disable_fbc = true;
13264 }
13265
13266 if (state->visible && !old_state->visible) {
13267 /*
13268 * BDW signals flip done immediately if the plane
13269 * is disabled, even if the plane enable is already
13270 * armed to occur at the next vblank :(
13271 */
13272 if (IS_BROADWELL(dev))
13273 intel_crtc->atomic.wait_vblank = true;
13274 }
13275
13276 intel_crtc->atomic.fb_bits |=
13277 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13278
13279 intel_crtc->atomic.update_fbc = true;
13280
13281 if (intel_wm_need_update(plane, &state->base))
13282 intel_crtc->atomic.update_wm = true;
13283 }
13284
13285 if (INTEL_INFO(dev)->gen >= 9) {
13286 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13287 to_intel_plane(plane), state, 0);
13288 if (ret)
13289 return ret;
13290 }
13291
13292 return 0;
13293}
13294
13295static void
13296intel_commit_primary_plane(struct drm_plane *plane,
13297 struct intel_plane_state *state)
13298{
13299 struct drm_crtc *crtc = state->base.crtc;
13300 struct drm_framebuffer *fb = state->base.fb;
13301 struct drm_device *dev = plane->dev;
13302 struct drm_i915_private *dev_priv = dev->dev_private;
13303 struct intel_crtc *intel_crtc;
13304 struct drm_rect *src = &state->src;
13305
13306 crtc = crtc ? crtc : plane->crtc;
13307 intel_crtc = to_intel_crtc(crtc);
13308
13309 plane->fb = fb;
13310 crtc->x = src->x1 >> 16;
13311 crtc->y = src->y1 >> 16;
13312
13313 if (intel_crtc->active) {
13314 if (state->visible)
13315 /* FIXME: kill this fastboot hack */
13316 intel_update_pipe_size(intel_crtc);
13317
13318 dev_priv->display.update_primary_plane(crtc, plane->fb,
13319 crtc->x, crtc->y);
13320 }
13321}
13322
13323static void
13324intel_disable_primary_plane(struct drm_plane *plane,
13325 struct drm_crtc *crtc,
13326 bool force)
13327{
13328 struct drm_device *dev = plane->dev;
13329 struct drm_i915_private *dev_priv = dev->dev_private;
13330
13331 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13332}
13333
13334static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13335{
13336 struct drm_device *dev = crtc->dev;
13337 struct drm_i915_private *dev_priv = dev->dev_private;
13338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13339 struct intel_plane *intel_plane;
13340 struct drm_plane *p;
13341 unsigned fb_bits = 0;
13342
13343 /* Track fb's for any planes being disabled */
13344 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13345 intel_plane = to_intel_plane(p);
13346
13347 if (intel_crtc->atomic.disabled_planes &
13348 (1 << drm_plane_index(p))) {
13349 switch (p->type) {
13350 case DRM_PLANE_TYPE_PRIMARY:
13351 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13352 break;
13353 case DRM_PLANE_TYPE_CURSOR:
13354 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13355 break;
13356 case DRM_PLANE_TYPE_OVERLAY:
13357 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13358 break;
13359 }
13360
13361 mutex_lock(&dev->struct_mutex);
13362 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13363 mutex_unlock(&dev->struct_mutex);
13364 }
13365 }
13366
13367 if (intel_crtc->atomic.wait_for_flips)
13368 intel_crtc_wait_for_pending_flips(crtc);
13369
13370 if (intel_crtc->atomic.disable_fbc)
13371 intel_fbc_disable(dev);
13372
13373 if (intel_crtc->atomic.pre_disable_primary)
13374 intel_pre_disable_primary(crtc);
13375
13376 if (intel_crtc->atomic.update_wm)
13377 intel_update_watermarks(crtc);
13378
13379 intel_runtime_pm_get(dev_priv);
13380
13381 /* Perform vblank evasion around commit operation */
13382 if (intel_crtc->active)
13383 intel_crtc->atomic.evade =
13384 intel_pipe_update_start(intel_crtc,
13385 &intel_crtc->atomic.start_vbl_count);
13386}
13387
13388static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13389{
13390 struct drm_device *dev = crtc->dev;
13391 struct drm_i915_private *dev_priv = dev->dev_private;
13392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13393 struct drm_plane *p;
13394
13395 if (intel_crtc->atomic.evade)
13396 intel_pipe_update_end(intel_crtc,
13397 intel_crtc->atomic.start_vbl_count);
13398
13399 intel_runtime_pm_put(dev_priv);
13400
13401 if (intel_crtc->atomic.wait_vblank)
13402 intel_wait_for_vblank(dev, intel_crtc->pipe);
13403
13404 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13405
13406 if (intel_crtc->atomic.update_fbc) {
13407 mutex_lock(&dev->struct_mutex);
13408 intel_fbc_update(dev);
13409 mutex_unlock(&dev->struct_mutex);
13410 }
13411
13412 if (intel_crtc->atomic.post_enable_primary)
13413 intel_post_enable_primary(crtc);
13414
13415 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13416 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13417 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13418 false, false);
13419
13420 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13421}
13422
13423/**
13424 * intel_plane_destroy - destroy a plane
13425 * @plane: plane to destroy
13426 *
13427 * Common destruction function for all types of planes (primary, cursor,
13428 * sprite).
13429 */
13430void intel_plane_destroy(struct drm_plane *plane)
13431{
13432 struct intel_plane *intel_plane = to_intel_plane(plane);
13433 drm_plane_cleanup(plane);
13434 kfree(intel_plane);
13435}
13436
13437const struct drm_plane_funcs intel_plane_funcs = {
13438 .update_plane = drm_atomic_helper_update_plane,
13439 .disable_plane = drm_atomic_helper_disable_plane,
13440 .destroy = intel_plane_destroy,
13441 .set_property = drm_atomic_helper_plane_set_property,
13442 .atomic_get_property = intel_plane_atomic_get_property,
13443 .atomic_set_property = intel_plane_atomic_set_property,
13444 .atomic_duplicate_state = intel_plane_duplicate_state,
13445 .atomic_destroy_state = intel_plane_destroy_state,
13446
13447};
13448
13449static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13450 int pipe)
13451{
13452 struct intel_plane *primary;
13453 struct intel_plane_state *state;
13454 const uint32_t *intel_primary_formats;
13455 int num_formats;
13456
13457 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13458 if (primary == NULL)
13459 return NULL;
13460
13461 state = intel_create_plane_state(&primary->base);
13462 if (!state) {
13463 kfree(primary);
13464 return NULL;
13465 }
13466 primary->base.state = &state->base;
13467
13468 primary->can_scale = false;
13469 primary->max_downscale = 1;
13470 if (INTEL_INFO(dev)->gen >= 9) {
13471 primary->can_scale = true;
13472 }
13473 state->scaler_id = -1;
13474 primary->pipe = pipe;
13475 primary->plane = pipe;
13476 primary->check_plane = intel_check_primary_plane;
13477 primary->commit_plane = intel_commit_primary_plane;
13478 primary->disable_plane = intel_disable_primary_plane;
13479 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13480 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13481 primary->plane = !pipe;
13482
13483 if (INTEL_INFO(dev)->gen <= 3) {
13484 intel_primary_formats = intel_primary_formats_gen2;
13485 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13486 } else {
13487 intel_primary_formats = intel_primary_formats_gen4;
13488 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13489 }
13490
13491 drm_universal_plane_init(dev, &primary->base, 0,
13492 &intel_plane_funcs,
13493 intel_primary_formats, num_formats,
13494 DRM_PLANE_TYPE_PRIMARY);
13495
13496 if (INTEL_INFO(dev)->gen >= 4)
13497 intel_create_rotation_property(dev, primary);
13498
13499 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13500
13501 return &primary->base;
13502}
13503
13504void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13505{
13506 if (!dev->mode_config.rotation_property) {
13507 unsigned long flags = BIT(DRM_ROTATE_0) |
13508 BIT(DRM_ROTATE_180);
13509
13510 if (INTEL_INFO(dev)->gen >= 9)
13511 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13512
13513 dev->mode_config.rotation_property =
13514 drm_mode_create_rotation_property(dev, flags);
13515 }
13516 if (dev->mode_config.rotation_property)
13517 drm_object_attach_property(&plane->base.base,
13518 dev->mode_config.rotation_property,
13519 plane->base.state->rotation);
13520}
13521
13522static int
13523intel_check_cursor_plane(struct drm_plane *plane,
13524 struct intel_plane_state *state)
13525{
13526 struct drm_crtc *crtc = state->base.crtc;
13527 struct drm_device *dev = plane->dev;
13528 struct drm_framebuffer *fb = state->base.fb;
13529 struct drm_rect *dest = &state->dst;
13530 struct drm_rect *src = &state->src;
13531 const struct drm_rect *clip = &state->clip;
13532 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13533 struct intel_crtc *intel_crtc;
13534 unsigned stride;
13535 int ret;
13536
13537 crtc = crtc ? crtc : plane->crtc;
13538 intel_crtc = to_intel_crtc(crtc);
13539
13540 ret = drm_plane_helper_check_update(plane, crtc, fb,
13541 src, dest, clip,
13542 DRM_PLANE_HELPER_NO_SCALING,
13543 DRM_PLANE_HELPER_NO_SCALING,
13544 true, true, &state->visible);
13545 if (ret)
13546 return ret;
13547
13548
13549 /* if we want to turn off the cursor ignore width and height */
13550 if (!obj)
13551 goto finish;
13552
13553 /* Check for which cursor types we support */
13554 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13555 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13556 state->base.crtc_w, state->base.crtc_h);
13557 return -EINVAL;
13558 }
13559
13560 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13561 if (obj->base.size < stride * state->base.crtc_h) {
13562 DRM_DEBUG_KMS("buffer is too small\n");
13563 return -ENOMEM;
13564 }
13565
13566 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13567 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13568 ret = -EINVAL;
13569 }
13570
13571finish:
13572 if (intel_crtc->active) {
13573 if (plane->state->crtc_w != state->base.crtc_w)
13574 intel_crtc->atomic.update_wm = true;
13575
13576 intel_crtc->atomic.fb_bits |=
13577 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13578 }
13579
13580 return ret;
13581}
13582
13583static void
13584intel_disable_cursor_plane(struct drm_plane *plane,
13585 struct drm_crtc *crtc,
13586 bool force)
13587{
13588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13589
13590 if (!force) {
13591 plane->fb = NULL;
13592 intel_crtc->cursor_bo = NULL;
13593 intel_crtc->cursor_addr = 0;
13594 }
13595
13596 intel_crtc_update_cursor(crtc, false);
13597}
13598
13599static void
13600intel_commit_cursor_plane(struct drm_plane *plane,
13601 struct intel_plane_state *state)
13602{
13603 struct drm_crtc *crtc = state->base.crtc;
13604 struct drm_device *dev = plane->dev;
13605 struct intel_crtc *intel_crtc;
13606 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13607 uint32_t addr;
13608
13609 crtc = crtc ? crtc : plane->crtc;
13610 intel_crtc = to_intel_crtc(crtc);
13611
13612 plane->fb = state->base.fb;
13613 crtc->cursor_x = state->base.crtc_x;
13614 crtc->cursor_y = state->base.crtc_y;
13615
13616 if (intel_crtc->cursor_bo == obj)
13617 goto update;
13618
13619 if (!obj)
13620 addr = 0;
13621 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13622 addr = i915_gem_obj_ggtt_offset(obj);
13623 else
13624 addr = obj->phys_handle->busaddr;
13625
13626 intel_crtc->cursor_addr = addr;
13627 intel_crtc->cursor_bo = obj;
13628update:
13629
13630 if (intel_crtc->active)
13631 intel_crtc_update_cursor(crtc, state->visible);
13632}
13633
13634static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13635 int pipe)
13636{
13637 struct intel_plane *cursor;
13638 struct intel_plane_state *state;
13639
13640 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13641 if (cursor == NULL)
13642 return NULL;
13643
13644 state = intel_create_plane_state(&cursor->base);
13645 if (!state) {
13646 kfree(cursor);
13647 return NULL;
13648 }
13649 cursor->base.state = &state->base;
13650
13651 cursor->can_scale = false;
13652 cursor->max_downscale = 1;
13653 cursor->pipe = pipe;
13654 cursor->plane = pipe;
13655 state->scaler_id = -1;
13656 cursor->check_plane = intel_check_cursor_plane;
13657 cursor->commit_plane = intel_commit_cursor_plane;
13658 cursor->disable_plane = intel_disable_cursor_plane;
13659
13660 drm_universal_plane_init(dev, &cursor->base, 0,
13661 &intel_plane_funcs,
13662 intel_cursor_formats,
13663 ARRAY_SIZE(intel_cursor_formats),
13664 DRM_PLANE_TYPE_CURSOR);
13665
13666 if (INTEL_INFO(dev)->gen >= 4) {
13667 if (!dev->mode_config.rotation_property)
13668 dev->mode_config.rotation_property =
13669 drm_mode_create_rotation_property(dev,
13670 BIT(DRM_ROTATE_0) |
13671 BIT(DRM_ROTATE_180));
13672 if (dev->mode_config.rotation_property)
13673 drm_object_attach_property(&cursor->base.base,
13674 dev->mode_config.rotation_property,
13675 state->base.rotation);
13676 }
13677
13678 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13679
13680 return &cursor->base;
13681}
13682
13683static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13684 struct intel_crtc_state *crtc_state)
13685{
13686 int i;
13687 struct intel_scaler *intel_scaler;
13688 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13689
13690 for (i = 0; i < intel_crtc->num_scalers; i++) {
13691 intel_scaler = &scaler_state->scalers[i];
13692 intel_scaler->in_use = 0;
13693 intel_scaler->id = i;
13694
13695 intel_scaler->mode = PS_SCALER_MODE_DYN;
13696 }
13697
13698 scaler_state->scaler_id = -1;
13699}
13700
13701static void intel_crtc_init(struct drm_device *dev, int pipe)
13702{
13703 struct drm_i915_private *dev_priv = dev->dev_private;
13704 struct intel_crtc *intel_crtc;
13705 struct intel_crtc_state *crtc_state = NULL;
13706 struct drm_plane *primary = NULL;
13707 struct drm_plane *cursor = NULL;
13708 int i, ret;
13709
13710 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13711 if (intel_crtc == NULL)
13712 return;
13713
13714 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13715 if (!crtc_state)
13716 goto fail;
13717 intel_crtc_set_state(intel_crtc, crtc_state);
13718 crtc_state->base.crtc = &intel_crtc->base;
13719
13720 /* initialize shared scalers */
13721 if (INTEL_INFO(dev)->gen >= 9) {
13722 if (pipe == PIPE_C)
13723 intel_crtc->num_scalers = 1;
13724 else
13725 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13726
13727 skl_init_scalers(dev, intel_crtc, crtc_state);
13728 }
13729
13730 primary = intel_primary_plane_create(dev, pipe);
13731 if (!primary)
13732 goto fail;
13733
13734 cursor = intel_cursor_plane_create(dev, pipe);
13735 if (!cursor)
13736 goto fail;
13737
13738 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13739 cursor, &intel_crtc_funcs);
13740 if (ret)
13741 goto fail;
13742
13743 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13744 for (i = 0; i < 256; i++) {
13745 intel_crtc->lut_r[i] = i;
13746 intel_crtc->lut_g[i] = i;
13747 intel_crtc->lut_b[i] = i;
13748 }
13749
13750 /*
13751 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13752 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13753 */
13754 intel_crtc->pipe = pipe;
13755 intel_crtc->plane = pipe;
13756 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13757 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13758 intel_crtc->plane = !pipe;
13759 }
13760
13761 intel_crtc->cursor_base = ~0;
13762 intel_crtc->cursor_cntl = ~0;
13763 intel_crtc->cursor_size = ~0;
13764
13765 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13766 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13767 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13768 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13769
13770 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13771
13772 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13773
13774 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13775 return;
13776
13777fail:
13778 if (primary)
13779 drm_plane_cleanup(primary);
13780 if (cursor)
13781 drm_plane_cleanup(cursor);
13782 kfree(crtc_state);
13783 kfree(intel_crtc);
13784}
13785
13786enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13787{
13788 struct drm_encoder *encoder = connector->base.encoder;
13789 struct drm_device *dev = connector->base.dev;
13790
13791 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13792
13793 if (!encoder || WARN_ON(!encoder->crtc))
13794 return INVALID_PIPE;
13795
13796 return to_intel_crtc(encoder->crtc)->pipe;
13797}
13798
13799int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13800 struct drm_file *file)
13801{
13802 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13803 struct drm_crtc *drmmode_crtc;
13804 struct intel_crtc *crtc;
13805
13806 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13807
13808 if (!drmmode_crtc) {
13809 DRM_ERROR("no such CRTC id\n");
13810 return -ENOENT;
13811 }
13812
13813 crtc = to_intel_crtc(drmmode_crtc);
13814 pipe_from_crtc_id->pipe = crtc->pipe;
13815
13816 return 0;
13817}
13818
13819static int intel_encoder_clones(struct intel_encoder *encoder)
13820{
13821 struct drm_device *dev = encoder->base.dev;
13822 struct intel_encoder *source_encoder;
13823 int index_mask = 0;
13824 int entry = 0;
13825
13826 for_each_intel_encoder(dev, source_encoder) {
13827 if (encoders_cloneable(encoder, source_encoder))
13828 index_mask |= (1 << entry);
13829
13830 entry++;
13831 }
13832
13833 return index_mask;
13834}
13835
13836static bool has_edp_a(struct drm_device *dev)
13837{
13838 struct drm_i915_private *dev_priv = dev->dev_private;
13839
13840 if (!IS_MOBILE(dev))
13841 return false;
13842
13843 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13844 return false;
13845
13846 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13847 return false;
13848
13849 return true;
13850}
13851
13852static bool intel_crt_present(struct drm_device *dev)
13853{
13854 struct drm_i915_private *dev_priv = dev->dev_private;
13855
13856 if (INTEL_INFO(dev)->gen >= 9)
13857 return false;
13858
13859 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13860 return false;
13861
13862 if (IS_CHERRYVIEW(dev))
13863 return false;
13864
13865 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13866 return false;
13867
13868 return true;
13869}
13870
13871static void intel_setup_outputs(struct drm_device *dev)
13872{
13873 struct drm_i915_private *dev_priv = dev->dev_private;
13874 struct intel_encoder *encoder;
13875 bool dpd_is_edp = false;
13876
13877 intel_lvds_init(dev);
13878
13879 if (intel_crt_present(dev))
13880 intel_crt_init(dev);
13881
13882 if (IS_BROXTON(dev)) {
13883 /*
13884 * FIXME: Broxton doesn't support port detection via the
13885 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13886 * detect the ports.
13887 */
13888 intel_ddi_init(dev, PORT_A);
13889 intel_ddi_init(dev, PORT_B);
13890 intel_ddi_init(dev, PORT_C);
13891 } else if (HAS_DDI(dev)) {
13892 int found;
13893
13894 /*
13895 * Haswell uses DDI functions to detect digital outputs.
13896 * On SKL pre-D0 the strap isn't connected, so we assume
13897 * it's there.
13898 */
13899 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13900 /* WaIgnoreDDIAStrap: skl */
13901 if (found ||
13902 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13903 intel_ddi_init(dev, PORT_A);
13904
13905 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13906 * register */
13907 found = I915_READ(SFUSE_STRAP);
13908
13909 if (found & SFUSE_STRAP_DDIB_DETECTED)
13910 intel_ddi_init(dev, PORT_B);
13911 if (found & SFUSE_STRAP_DDIC_DETECTED)
13912 intel_ddi_init(dev, PORT_C);
13913 if (found & SFUSE_STRAP_DDID_DETECTED)
13914 intel_ddi_init(dev, PORT_D);
13915 } else if (HAS_PCH_SPLIT(dev)) {
13916 int found;
13917 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13918
13919 if (has_edp_a(dev))
13920 intel_dp_init(dev, DP_A, PORT_A);
13921
13922 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13923 /* PCH SDVOB multiplex with HDMIB */
13924 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13925 if (!found)
13926 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13927 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13928 intel_dp_init(dev, PCH_DP_B, PORT_B);
13929 }
13930
13931 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13932 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13933
13934 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13935 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13936
13937 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13938 intel_dp_init(dev, PCH_DP_C, PORT_C);
13939
13940 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13941 intel_dp_init(dev, PCH_DP_D, PORT_D);
13942 } else if (IS_VALLEYVIEW(dev)) {
13943 /*
13944 * The DP_DETECTED bit is the latched state of the DDC
13945 * SDA pin at boot. However since eDP doesn't require DDC
13946 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13947 * eDP ports may have been muxed to an alternate function.
13948 * Thus we can't rely on the DP_DETECTED bit alone to detect
13949 * eDP ports. Consult the VBT as well as DP_DETECTED to
13950 * detect eDP ports.
13951 */
13952 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13953 !intel_dp_is_edp(dev, PORT_B))
13954 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13955 PORT_B);
13956 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13957 intel_dp_is_edp(dev, PORT_B))
13958 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13959
13960 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13961 !intel_dp_is_edp(dev, PORT_C))
13962 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13963 PORT_C);
13964 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13965 intel_dp_is_edp(dev, PORT_C))
13966 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13967
13968 if (IS_CHERRYVIEW(dev)) {
13969 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13970 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13971 PORT_D);
13972 /* eDP not supported on port D, so don't check VBT */
13973 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13974 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13975 }
13976
13977 intel_dsi_init(dev);
13978 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13979 bool found = false;
13980
13981 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13982 DRM_DEBUG_KMS("probing SDVOB\n");
13983 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13984 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13985 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13986 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13987 }
13988
13989 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13990 intel_dp_init(dev, DP_B, PORT_B);
13991 }
13992
13993 /* Before G4X SDVOC doesn't have its own detect register */
13994
13995 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13996 DRM_DEBUG_KMS("probing SDVOC\n");
13997 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13998 }
13999
14000 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14001
14002 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14003 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14004 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14005 }
14006 if (SUPPORTS_INTEGRATED_DP(dev))
14007 intel_dp_init(dev, DP_C, PORT_C);
14008 }
14009
14010 if (SUPPORTS_INTEGRATED_DP(dev) &&
14011 (I915_READ(DP_D) & DP_DETECTED))
14012 intel_dp_init(dev, DP_D, PORT_D);
14013 } else if (IS_GEN2(dev))
14014 intel_dvo_init(dev);
14015
14016 if (SUPPORTS_TV(dev))
14017 intel_tv_init(dev);
14018
14019 intel_psr_init(dev);
14020
14021 for_each_intel_encoder(dev, encoder) {
14022 encoder->base.possible_crtcs = encoder->crtc_mask;
14023 encoder->base.possible_clones =
14024 intel_encoder_clones(encoder);
14025 }
14026
14027 intel_init_pch_refclk(dev);
14028
14029 drm_helper_move_panel_connectors_to_head(dev);
14030}
14031
14032static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14033{
14034 struct drm_device *dev = fb->dev;
14035 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14036
14037 drm_framebuffer_cleanup(fb);
14038 mutex_lock(&dev->struct_mutex);
14039 WARN_ON(!intel_fb->obj->framebuffer_references--);
14040 drm_gem_object_unreference(&intel_fb->obj->base);
14041 mutex_unlock(&dev->struct_mutex);
14042 kfree(intel_fb);
14043}
14044
14045static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14046 struct drm_file *file,
14047 unsigned int *handle)
14048{
14049 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14050 struct drm_i915_gem_object *obj = intel_fb->obj;
14051
14052 return drm_gem_handle_create(file, &obj->base, handle);
14053}
14054
14055static const struct drm_framebuffer_funcs intel_fb_funcs = {
14056 .destroy = intel_user_framebuffer_destroy,
14057 .create_handle = intel_user_framebuffer_create_handle,
14058};
14059
14060static
14061u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14062 uint32_t pixel_format)
14063{
14064 u32 gen = INTEL_INFO(dev)->gen;
14065
14066 if (gen >= 9) {
14067 /* "The stride in bytes must not exceed the of the size of 8K
14068 * pixels and 32K bytes."
14069 */
14070 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14071 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14072 return 32*1024;
14073 } else if (gen >= 4) {
14074 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14075 return 16*1024;
14076 else
14077 return 32*1024;
14078 } else if (gen >= 3) {
14079 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14080 return 8*1024;
14081 else
14082 return 16*1024;
14083 } else {
14084 /* XXX DSPC is limited to 4k tiled */
14085 return 8*1024;
14086 }
14087}
14088
14089static int intel_framebuffer_init(struct drm_device *dev,
14090 struct intel_framebuffer *intel_fb,
14091 struct drm_mode_fb_cmd2 *mode_cmd,
14092 struct drm_i915_gem_object *obj)
14093{
14094 unsigned int aligned_height;
14095 int ret;
14096 u32 pitch_limit, stride_alignment;
14097
14098 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14099
14100 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14101 /* Enforce that fb modifier and tiling mode match, but only for
14102 * X-tiled. This is needed for FBC. */
14103 if (!!(obj->tiling_mode == I915_TILING_X) !=
14104 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14105 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14106 return -EINVAL;
14107 }
14108 } else {
14109 if (obj->tiling_mode == I915_TILING_X)
14110 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14111 else if (obj->tiling_mode == I915_TILING_Y) {
14112 DRM_DEBUG("No Y tiling for legacy addfb\n");
14113 return -EINVAL;
14114 }
14115 }
14116
14117 /* Passed in modifier sanity checking. */
14118 switch (mode_cmd->modifier[0]) {
14119 case I915_FORMAT_MOD_Y_TILED:
14120 case I915_FORMAT_MOD_Yf_TILED:
14121 if (INTEL_INFO(dev)->gen < 9) {
14122 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14123 mode_cmd->modifier[0]);
14124 return -EINVAL;
14125 }
14126 case DRM_FORMAT_MOD_NONE:
14127 case I915_FORMAT_MOD_X_TILED:
14128 break;
14129 default:
14130 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14131 mode_cmd->modifier[0]);
14132 return -EINVAL;
14133 }
14134
14135 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14136 mode_cmd->pixel_format);
14137 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14138 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14139 mode_cmd->pitches[0], stride_alignment);
14140 return -EINVAL;
14141 }
14142
14143 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14144 mode_cmd->pixel_format);
14145 if (mode_cmd->pitches[0] > pitch_limit) {
14146 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14147 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14148 "tiled" : "linear",
14149 mode_cmd->pitches[0], pitch_limit);
14150 return -EINVAL;
14151 }
14152
14153 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14154 mode_cmd->pitches[0] != obj->stride) {
14155 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14156 mode_cmd->pitches[0], obj->stride);
14157 return -EINVAL;
14158 }
14159
14160 /* Reject formats not supported by any plane early. */
14161 switch (mode_cmd->pixel_format) {
14162 case DRM_FORMAT_C8:
14163 case DRM_FORMAT_RGB565:
14164 case DRM_FORMAT_XRGB8888:
14165 case DRM_FORMAT_ARGB8888:
14166 break;
14167 case DRM_FORMAT_XRGB1555:
14168 case DRM_FORMAT_ARGB1555:
14169 if (INTEL_INFO(dev)->gen > 3) {
14170 DRM_DEBUG("unsupported pixel format: %s\n",
14171 drm_get_format_name(mode_cmd->pixel_format));
14172 return -EINVAL;
14173 }
14174 break;
14175 case DRM_FORMAT_XBGR8888:
14176 case DRM_FORMAT_ABGR8888:
14177 case DRM_FORMAT_XRGB2101010:
14178 case DRM_FORMAT_ARGB2101010:
14179 case DRM_FORMAT_XBGR2101010:
14180 case DRM_FORMAT_ABGR2101010:
14181 if (INTEL_INFO(dev)->gen < 4) {
14182 DRM_DEBUG("unsupported pixel format: %s\n",
14183 drm_get_format_name(mode_cmd->pixel_format));
14184 return -EINVAL;
14185 }
14186 break;
14187 case DRM_FORMAT_YUYV:
14188 case DRM_FORMAT_UYVY:
14189 case DRM_FORMAT_YVYU:
14190 case DRM_FORMAT_VYUY:
14191 if (INTEL_INFO(dev)->gen < 5) {
14192 DRM_DEBUG("unsupported pixel format: %s\n",
14193 drm_get_format_name(mode_cmd->pixel_format));
14194 return -EINVAL;
14195 }
14196 break;
14197 default:
14198 DRM_DEBUG("unsupported pixel format: %s\n",
14199 drm_get_format_name(mode_cmd->pixel_format));
14200 return -EINVAL;
14201 }
14202
14203 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14204 if (mode_cmd->offsets[0] != 0)
14205 return -EINVAL;
14206
14207 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14208 mode_cmd->pixel_format,
14209 mode_cmd->modifier[0]);
14210 /* FIXME drm helper for size checks (especially planar formats)? */
14211 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14212 return -EINVAL;
14213
14214 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14215 intel_fb->obj = obj;
14216 intel_fb->obj->framebuffer_references++;
14217
14218 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14219 if (ret) {
14220 DRM_ERROR("framebuffer init failed %d\n", ret);
14221 return ret;
14222 }
14223
14224 return 0;
14225}
14226
14227static struct drm_framebuffer *
14228intel_user_framebuffer_create(struct drm_device *dev,
14229 struct drm_file *filp,
14230 struct drm_mode_fb_cmd2 *mode_cmd)
14231{
14232 struct drm_i915_gem_object *obj;
14233
14234 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14235 mode_cmd->handles[0]));
14236 if (&obj->base == NULL)
14237 return ERR_PTR(-ENOENT);
14238
14239 return intel_framebuffer_create(dev, mode_cmd, obj);
14240}
14241
14242#ifndef CONFIG_DRM_I915_FBDEV
14243static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14244{
14245}
14246#endif
14247
14248static const struct drm_mode_config_funcs intel_mode_funcs = {
14249 .fb_create = intel_user_framebuffer_create,
14250 .output_poll_changed = intel_fbdev_output_poll_changed,
14251 .atomic_check = intel_atomic_check,
14252 .atomic_commit = intel_atomic_commit,
14253};
14254
14255/* Set up chip specific display functions */
14256static void intel_init_display(struct drm_device *dev)
14257{
14258 struct drm_i915_private *dev_priv = dev->dev_private;
14259
14260 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14261 dev_priv->display.find_dpll = g4x_find_best_dpll;
14262 else if (IS_CHERRYVIEW(dev))
14263 dev_priv->display.find_dpll = chv_find_best_dpll;
14264 else if (IS_VALLEYVIEW(dev))
14265 dev_priv->display.find_dpll = vlv_find_best_dpll;
14266 else if (IS_PINEVIEW(dev))
14267 dev_priv->display.find_dpll = pnv_find_best_dpll;
14268 else
14269 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14270
14271 if (INTEL_INFO(dev)->gen >= 9) {
14272 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14273 dev_priv->display.get_initial_plane_config =
14274 skylake_get_initial_plane_config;
14275 dev_priv->display.crtc_compute_clock =
14276 haswell_crtc_compute_clock;
14277 dev_priv->display.crtc_enable = haswell_crtc_enable;
14278 dev_priv->display.crtc_disable = haswell_crtc_disable;
14279 dev_priv->display.off = ironlake_crtc_off;
14280 dev_priv->display.update_primary_plane =
14281 skylake_update_primary_plane;
14282 } else if (HAS_DDI(dev)) {
14283 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14284 dev_priv->display.get_initial_plane_config =
14285 ironlake_get_initial_plane_config;
14286 dev_priv->display.crtc_compute_clock =
14287 haswell_crtc_compute_clock;
14288 dev_priv->display.crtc_enable = haswell_crtc_enable;
14289 dev_priv->display.crtc_disable = haswell_crtc_disable;
14290 dev_priv->display.off = ironlake_crtc_off;
14291 dev_priv->display.update_primary_plane =
14292 ironlake_update_primary_plane;
14293 } else if (HAS_PCH_SPLIT(dev)) {
14294 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14295 dev_priv->display.get_initial_plane_config =
14296 ironlake_get_initial_plane_config;
14297 dev_priv->display.crtc_compute_clock =
14298 ironlake_crtc_compute_clock;
14299 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14300 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14301 dev_priv->display.off = ironlake_crtc_off;
14302 dev_priv->display.update_primary_plane =
14303 ironlake_update_primary_plane;
14304 } else if (IS_VALLEYVIEW(dev)) {
14305 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14306 dev_priv->display.get_initial_plane_config =
14307 i9xx_get_initial_plane_config;
14308 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14309 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14310 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14311 dev_priv->display.off = i9xx_crtc_off;
14312 dev_priv->display.update_primary_plane =
14313 i9xx_update_primary_plane;
14314 } else {
14315 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14316 dev_priv->display.get_initial_plane_config =
14317 i9xx_get_initial_plane_config;
14318 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14319 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14320 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14321 dev_priv->display.off = i9xx_crtc_off;
14322 dev_priv->display.update_primary_plane =
14323 i9xx_update_primary_plane;
14324 }
14325
14326 /* Returns the core display clock speed */
14327 if (IS_SKYLAKE(dev))
14328 dev_priv->display.get_display_clock_speed =
14329 skylake_get_display_clock_speed;
14330 else if (IS_BROADWELL(dev))
14331 dev_priv->display.get_display_clock_speed =
14332 broadwell_get_display_clock_speed;
14333 else if (IS_HASWELL(dev))
14334 dev_priv->display.get_display_clock_speed =
14335 haswell_get_display_clock_speed;
14336 else if (IS_VALLEYVIEW(dev))
14337 dev_priv->display.get_display_clock_speed =
14338 valleyview_get_display_clock_speed;
14339 else if (IS_GEN5(dev))
14340 dev_priv->display.get_display_clock_speed =
14341 ilk_get_display_clock_speed;
14342 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14343 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14344 dev_priv->display.get_display_clock_speed =
14345 i945_get_display_clock_speed;
14346 else if (IS_I915G(dev))
14347 dev_priv->display.get_display_clock_speed =
14348 i915_get_display_clock_speed;
14349 else if (IS_I945GM(dev) || IS_845G(dev))
14350 dev_priv->display.get_display_clock_speed =
14351 i9xx_misc_get_display_clock_speed;
14352 else if (IS_PINEVIEW(dev))
14353 dev_priv->display.get_display_clock_speed =
14354 pnv_get_display_clock_speed;
14355 else if (IS_I915GM(dev))
14356 dev_priv->display.get_display_clock_speed =
14357 i915gm_get_display_clock_speed;
14358 else if (IS_I865G(dev))
14359 dev_priv->display.get_display_clock_speed =
14360 i865_get_display_clock_speed;
14361 else if (IS_I85X(dev))
14362 dev_priv->display.get_display_clock_speed =
14363 i855_get_display_clock_speed;
14364 else /* 852, 830 */
14365 dev_priv->display.get_display_clock_speed =
14366 i830_get_display_clock_speed;
14367
14368 if (IS_GEN5(dev)) {
14369 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14370 } else if (IS_GEN6(dev)) {
14371 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14372 } else if (IS_IVYBRIDGE(dev)) {
14373 /* FIXME: detect B0+ stepping and use auto training */
14374 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14375 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14376 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14377 } else if (IS_VALLEYVIEW(dev)) {
14378 dev_priv->display.modeset_global_resources =
14379 valleyview_modeset_global_resources;
14380 } else if (IS_BROXTON(dev)) {
14381 dev_priv->display.modeset_global_resources =
14382 broxton_modeset_global_resources;
14383 }
14384
14385 switch (INTEL_INFO(dev)->gen) {
14386 case 2:
14387 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14388 break;
14389
14390 case 3:
14391 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14392 break;
14393
14394 case 4:
14395 case 5:
14396 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14397 break;
14398
14399 case 6:
14400 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14401 break;
14402 case 7:
14403 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14404 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14405 break;
14406 case 9:
14407 /* Drop through - unsupported since execlist only. */
14408 default:
14409 /* Default just returns -ENODEV to indicate unsupported */
14410 dev_priv->display.queue_flip = intel_default_queue_flip;
14411 }
14412
14413 intel_panel_init_backlight_funcs(dev);
14414
14415 mutex_init(&dev_priv->pps_mutex);
14416}
14417
14418/*
14419 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14420 * resume, or other times. This quirk makes sure that's the case for
14421 * affected systems.
14422 */
14423static void quirk_pipea_force(struct drm_device *dev)
14424{
14425 struct drm_i915_private *dev_priv = dev->dev_private;
14426
14427 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14428 DRM_INFO("applying pipe a force quirk\n");
14429}
14430
14431static void quirk_pipeb_force(struct drm_device *dev)
14432{
14433 struct drm_i915_private *dev_priv = dev->dev_private;
14434
14435 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14436 DRM_INFO("applying pipe b force quirk\n");
14437}
14438
14439/*
14440 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14441 */
14442static void quirk_ssc_force_disable(struct drm_device *dev)
14443{
14444 struct drm_i915_private *dev_priv = dev->dev_private;
14445 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14446 DRM_INFO("applying lvds SSC disable quirk\n");
14447}
14448
14449/*
14450 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14451 * brightness value
14452 */
14453static void quirk_invert_brightness(struct drm_device *dev)
14454{
14455 struct drm_i915_private *dev_priv = dev->dev_private;
14456 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14457 DRM_INFO("applying inverted panel brightness quirk\n");
14458}
14459
14460/* Some VBT's incorrectly indicate no backlight is present */
14461static void quirk_backlight_present(struct drm_device *dev)
14462{
14463 struct drm_i915_private *dev_priv = dev->dev_private;
14464 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14465 DRM_INFO("applying backlight present quirk\n");
14466}
14467
14468struct intel_quirk {
14469 int device;
14470 int subsystem_vendor;
14471 int subsystem_device;
14472 void (*hook)(struct drm_device *dev);
14473};
14474
14475/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14476struct intel_dmi_quirk {
14477 void (*hook)(struct drm_device *dev);
14478 const struct dmi_system_id (*dmi_id_list)[];
14479};
14480
14481static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14482{
14483 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14484 return 1;
14485}
14486
14487static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14488 {
14489 .dmi_id_list = &(const struct dmi_system_id[]) {
14490 {
14491 .callback = intel_dmi_reverse_brightness,
14492 .ident = "NCR Corporation",
14493 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14494 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14495 },
14496 },
14497 { } /* terminating entry */
14498 },
14499 .hook = quirk_invert_brightness,
14500 },
14501};
14502
14503static struct intel_quirk intel_quirks[] = {
14504 /* HP Mini needs pipe A force quirk (LP: #322104) */
14505 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
14506
14507 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14508 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14509
14510 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14511 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14512
14513 /* 830 needs to leave pipe A & dpll A up */
14514 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14515
14516 /* 830 needs to leave pipe B & dpll B up */
14517 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14518
14519 /* Lenovo U160 cannot use SSC on LVDS */
14520 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14521
14522 /* Sony Vaio Y cannot use SSC on LVDS */
14523 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14524
14525 /* Acer Aspire 5734Z must invert backlight brightness */
14526 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14527
14528 /* Acer/eMachines G725 */
14529 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14530
14531 /* Acer/eMachines e725 */
14532 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14533
14534 /* Acer/Packard Bell NCL20 */
14535 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14536
14537 /* Acer Aspire 4736Z */
14538 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14539
14540 /* Acer Aspire 5336 */
14541 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14542
14543 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14544 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14545
14546 /* Acer C720 Chromebook (Core i3 4005U) */
14547 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14548
14549 /* Apple Macbook 2,1 (Core 2 T7400) */
14550 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14551
14552 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14553 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14554
14555 /* HP Chromebook 14 (Celeron 2955U) */
14556 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14557
14558 /* Dell Chromebook 11 */
14559 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14560};
14561
14562static void intel_init_quirks(struct drm_device *dev)
14563{
14564 struct pci_dev *d = dev->pdev;
14565 int i;
14566
14567 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14568 struct intel_quirk *q = &intel_quirks[i];
14569
14570 if (d->device == q->device &&
14571 (d->subsystem_vendor == q->subsystem_vendor ||
14572 q->subsystem_vendor == PCI_ANY_ID) &&
14573 (d->subsystem_device == q->subsystem_device ||
14574 q->subsystem_device == PCI_ANY_ID))
14575 q->hook(dev);
14576 }
14577 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14578 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14579 intel_dmi_quirks[i].hook(dev);
14580 }
14581}
14582
14583/* Disable the VGA plane that we never use */
14584static void i915_disable_vga(struct drm_device *dev)
14585{
14586 struct drm_i915_private *dev_priv = dev->dev_private;
14587 u8 sr1;
14588 u32 vga_reg = i915_vgacntrl_reg(dev);
14589
14590 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14591 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14592 outb(SR01, VGA_SR_INDEX);
14593 sr1 = inb(VGA_SR_DATA);
14594 outb(sr1 | 1<<5, VGA_SR_DATA);
14595 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14596 udelay(300);
14597
14598 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14599 POSTING_READ(vga_reg);
14600}
14601
14602void intel_modeset_init_hw(struct drm_device *dev)
14603{
14604 intel_prepare_ddi(dev);
14605
14606 if (IS_VALLEYVIEW(dev))
14607 vlv_update_cdclk(dev);
14608
14609 intel_init_clock_gating(dev);
14610
14611 intel_enable_gt_powersave(dev);
14612}
14613
14614void intel_modeset_init(struct drm_device *dev)
14615{
14616 struct drm_i915_private *dev_priv = dev->dev_private;
14617 int sprite, ret;
14618 enum pipe pipe;
14619 struct intel_crtc *crtc;
14620
14621 drm_mode_config_init(dev);
14622
14623 dev->mode_config.min_width = 0;
14624 dev->mode_config.min_height = 0;
14625
14626 dev->mode_config.preferred_depth = 24;
14627 dev->mode_config.prefer_shadow = 1;
14628
14629 dev->mode_config.allow_fb_modifiers = true;
14630
14631 dev->mode_config.funcs = &intel_mode_funcs;
14632
14633 intel_init_quirks(dev);
14634
14635 intel_init_pm(dev);
14636
14637 if (INTEL_INFO(dev)->num_pipes == 0)
14638 return;
14639
14640 intel_init_display(dev);
14641 intel_init_audio(dev);
14642
14643 if (IS_GEN2(dev)) {
14644 dev->mode_config.max_width = 2048;
14645 dev->mode_config.max_height = 2048;
14646 } else if (IS_GEN3(dev)) {
14647 dev->mode_config.max_width = 4096;
14648 dev->mode_config.max_height = 4096;
14649 } else {
14650 dev->mode_config.max_width = 8192;
14651 dev->mode_config.max_height = 8192;
14652 }
14653
14654 if (IS_845G(dev) || IS_I865G(dev)) {
14655 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14656 dev->mode_config.cursor_height = 1023;
14657 } else if (IS_GEN2(dev)) {
14658 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14659 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14660 } else {
14661 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14662 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14663 }
14664
14665 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14666
14667 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14668 INTEL_INFO(dev)->num_pipes,
14669 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14670
14671 for_each_pipe(dev_priv, pipe) {
14672 intel_crtc_init(dev, pipe);
14673 for_each_sprite(dev_priv, pipe, sprite) {
14674 ret = intel_plane_init(dev, pipe, sprite);
14675 if (ret)
14676 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14677 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14678 }
14679 }
14680
14681 intel_init_dpio(dev);
14682
14683 intel_shared_dpll_init(dev);
14684
14685 /* Just disable it once at startup */
14686 i915_disable_vga(dev);
14687 intel_setup_outputs(dev);
14688
14689 /* Just in case the BIOS is doing something questionable. */
14690 intel_fbc_disable(dev);
14691
14692 drm_modeset_lock_all(dev);
14693 intel_modeset_setup_hw_state(dev, false);
14694 drm_modeset_unlock_all(dev);
14695
14696 for_each_intel_crtc(dev, crtc) {
14697 if (!crtc->active)
14698 continue;
14699
14700 /*
14701 * Note that reserving the BIOS fb up front prevents us
14702 * from stuffing other stolen allocations like the ring
14703 * on top. This prevents some ugliness at boot time, and
14704 * can even allow for smooth boot transitions if the BIOS
14705 * fb is large enough for the active pipe configuration.
14706 */
14707 if (dev_priv->display.get_initial_plane_config) {
14708 dev_priv->display.get_initial_plane_config(crtc,
14709 &crtc->plane_config);
14710 /*
14711 * If the fb is shared between multiple heads, we'll
14712 * just get the first one.
14713 */
14714 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14715 }
14716 }
14717}
14718
14719static void intel_enable_pipe_a(struct drm_device *dev)
14720{
14721 struct intel_connector *connector;
14722 struct drm_connector *crt = NULL;
14723 struct intel_load_detect_pipe load_detect_temp;
14724 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14725
14726 /* We can't just switch on the pipe A, we need to set things up with a
14727 * proper mode and output configuration. As a gross hack, enable pipe A
14728 * by enabling the load detect pipe once. */
14729 for_each_intel_connector(dev, connector) {
14730 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14731 crt = &connector->base;
14732 break;
14733 }
14734 }
14735
14736 if (!crt)
14737 return;
14738
14739 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14740 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14741}
14742
14743static bool
14744intel_check_plane_mapping(struct intel_crtc *crtc)
14745{
14746 struct drm_device *dev = crtc->base.dev;
14747 struct drm_i915_private *dev_priv = dev->dev_private;
14748 u32 reg, val;
14749
14750 if (INTEL_INFO(dev)->num_pipes == 1)
14751 return true;
14752
14753 reg = DSPCNTR(!crtc->plane);
14754 val = I915_READ(reg);
14755
14756 if ((val & DISPLAY_PLANE_ENABLE) &&
14757 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14758 return false;
14759
14760 return true;
14761}
14762
14763static void intel_sanitize_crtc(struct intel_crtc *crtc)
14764{
14765 struct drm_device *dev = crtc->base.dev;
14766 struct drm_i915_private *dev_priv = dev->dev_private;
14767 u32 reg;
14768
14769 /* Clear any frame start delays used for debugging left by the BIOS */
14770 reg = PIPECONF(crtc->config->cpu_transcoder);
14771 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14772
14773 /* restore vblank interrupts to correct state */
14774 drm_crtc_vblank_reset(&crtc->base);
14775 if (crtc->active) {
14776 update_scanline_offset(crtc);
14777 drm_crtc_vblank_on(&crtc->base);
14778 }
14779
14780 /* We need to sanitize the plane -> pipe mapping first because this will
14781 * disable the crtc (and hence change the state) if it is wrong. Note
14782 * that gen4+ has a fixed plane -> pipe mapping. */
14783 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14784 struct intel_connector *connector;
14785 bool plane;
14786
14787 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14788 crtc->base.base.id);
14789
14790 /* Pipe has the wrong plane attached and the plane is active.
14791 * Temporarily change the plane mapping and disable everything
14792 * ... */
14793 plane = crtc->plane;
14794 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14795 crtc->plane = !plane;
14796 intel_crtc_disable_planes(&crtc->base);
14797 dev_priv->display.crtc_disable(&crtc->base);
14798 crtc->plane = plane;
14799
14800 /* ... and break all links. */
14801 for_each_intel_connector(dev, connector) {
14802 if (connector->encoder->base.crtc != &crtc->base)
14803 continue;
14804
14805 connector->base.dpms = DRM_MODE_DPMS_OFF;
14806 connector->base.encoder = NULL;
14807 }
14808 /* multiple connectors may have the same encoder:
14809 * handle them and break crtc link separately */
14810 for_each_intel_connector(dev, connector)
14811 if (connector->encoder->base.crtc == &crtc->base) {
14812 connector->encoder->base.crtc = NULL;
14813 connector->encoder->connectors_active = false;
14814 }
14815
14816 WARN_ON(crtc->active);
14817 crtc->base.state->enable = false;
14818 crtc->base.enabled = false;
14819 }
14820
14821 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14822 crtc->pipe == PIPE_A && !crtc->active) {
14823 /* BIOS forgot to enable pipe A, this mostly happens after
14824 * resume. Force-enable the pipe to fix this, the update_dpms
14825 * call below we restore the pipe to the right state, but leave
14826 * the required bits on. */
14827 intel_enable_pipe_a(dev);
14828 }
14829
14830 /* Adjust the state of the output pipe according to whether we
14831 * have active connectors/encoders. */
14832 intel_crtc_update_dpms(&crtc->base);
14833
14834 if (crtc->active != crtc->base.state->enable) {
14835 struct intel_encoder *encoder;
14836
14837 /* This can happen either due to bugs in the get_hw_state
14838 * functions or because the pipe is force-enabled due to the
14839 * pipe A quirk. */
14840 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14841 crtc->base.base.id,
14842 crtc->base.state->enable ? "enabled" : "disabled",
14843 crtc->active ? "enabled" : "disabled");
14844
14845 crtc->base.state->enable = crtc->active;
14846 crtc->base.enabled = crtc->active;
14847
14848 /* Because we only establish the connector -> encoder ->
14849 * crtc links if something is active, this means the
14850 * crtc is now deactivated. Break the links. connector
14851 * -> encoder links are only establish when things are
14852 * actually up, hence no need to break them. */
14853 WARN_ON(crtc->active);
14854
14855 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14856 WARN_ON(encoder->connectors_active);
14857 encoder->base.crtc = NULL;
14858 }
14859 }
14860
14861 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14862 /*
14863 * We start out with underrun reporting disabled to avoid races.
14864 * For correct bookkeeping mark this on active crtcs.
14865 *
14866 * Also on gmch platforms we dont have any hardware bits to
14867 * disable the underrun reporting. Which means we need to start
14868 * out with underrun reporting disabled also on inactive pipes,
14869 * since otherwise we'll complain about the garbage we read when
14870 * e.g. coming up after runtime pm.
14871 *
14872 * No protection against concurrent access is required - at
14873 * worst a fifo underrun happens which also sets this to false.
14874 */
14875 crtc->cpu_fifo_underrun_disabled = true;
14876 crtc->pch_fifo_underrun_disabled = true;
14877 }
14878}
14879
14880static void intel_sanitize_encoder(struct intel_encoder *encoder)
14881{
14882 struct intel_connector *connector;
14883 struct drm_device *dev = encoder->base.dev;
14884
14885 /* We need to check both for a crtc link (meaning that the
14886 * encoder is active and trying to read from a pipe) and the
14887 * pipe itself being active. */
14888 bool has_active_crtc = encoder->base.crtc &&
14889 to_intel_crtc(encoder->base.crtc)->active;
14890
14891 if (encoder->connectors_active && !has_active_crtc) {
14892 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14893 encoder->base.base.id,
14894 encoder->base.name);
14895
14896 /* Connector is active, but has no active pipe. This is
14897 * fallout from our resume register restoring. Disable
14898 * the encoder manually again. */
14899 if (encoder->base.crtc) {
14900 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14901 encoder->base.base.id,
14902 encoder->base.name);
14903 encoder->disable(encoder);
14904 if (encoder->post_disable)
14905 encoder->post_disable(encoder);
14906 }
14907 encoder->base.crtc = NULL;
14908 encoder->connectors_active = false;
14909
14910 /* Inconsistent output/port/pipe state happens presumably due to
14911 * a bug in one of the get_hw_state functions. Or someplace else
14912 * in our code, like the register restore mess on resume. Clamp
14913 * things to off as a safer default. */
14914 for_each_intel_connector(dev, connector) {
14915 if (connector->encoder != encoder)
14916 continue;
14917 connector->base.dpms = DRM_MODE_DPMS_OFF;
14918 connector->base.encoder = NULL;
14919 }
14920 }
14921 /* Enabled encoders without active connectors will be fixed in
14922 * the crtc fixup. */
14923}
14924
14925void i915_redisable_vga_power_on(struct drm_device *dev)
14926{
14927 struct drm_i915_private *dev_priv = dev->dev_private;
14928 u32 vga_reg = i915_vgacntrl_reg(dev);
14929
14930 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14931 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14932 i915_disable_vga(dev);
14933 }
14934}
14935
14936void i915_redisable_vga(struct drm_device *dev)
14937{
14938 struct drm_i915_private *dev_priv = dev->dev_private;
14939
14940 /* This function can be called both from intel_modeset_setup_hw_state or
14941 * at a very early point in our resume sequence, where the power well
14942 * structures are not yet restored. Since this function is at a very
14943 * paranoid "someone might have enabled VGA while we were not looking"
14944 * level, just check if the power well is enabled instead of trying to
14945 * follow the "don't touch the power well if we don't need it" policy
14946 * the rest of the driver uses. */
14947 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14948 return;
14949
14950 i915_redisable_vga_power_on(dev);
14951}
14952
14953static bool primary_get_hw_state(struct intel_crtc *crtc)
14954{
14955 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14956
14957 if (!crtc->active)
14958 return false;
14959
14960 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14961}
14962
14963static void intel_modeset_readout_hw_state(struct drm_device *dev)
14964{
14965 struct drm_i915_private *dev_priv = dev->dev_private;
14966 enum pipe pipe;
14967 struct intel_crtc *crtc;
14968 struct intel_encoder *encoder;
14969 struct intel_connector *connector;
14970 int i;
14971
14972 for_each_intel_crtc(dev, crtc) {
14973 struct drm_plane *primary = crtc->base.primary;
14974 struct intel_plane_state *plane_state;
14975
14976 memset(crtc->config, 0, sizeof(*crtc->config));
14977
14978 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14979
14980 crtc->active = dev_priv->display.get_pipe_config(crtc,
14981 crtc->config);
14982
14983 crtc->base.state->enable = crtc->active;
14984 crtc->base.enabled = crtc->active;
14985
14986 plane_state = to_intel_plane_state(primary->state);
14987 plane_state->visible = primary_get_hw_state(crtc);
14988
14989 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14990 crtc->base.base.id,
14991 crtc->active ? "enabled" : "disabled");
14992 }
14993
14994 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14995 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14996
14997 pll->on = pll->get_hw_state(dev_priv, pll,
14998 &pll->config.hw_state);
14999 pll->active = 0;
15000 pll->config.crtc_mask = 0;
15001 for_each_intel_crtc(dev, crtc) {
15002 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15003 pll->active++;
15004 pll->config.crtc_mask |= 1 << crtc->pipe;
15005 }
15006 }
15007
15008 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15009 pll->name, pll->config.crtc_mask, pll->on);
15010
15011 if (pll->config.crtc_mask)
15012 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15013 }
15014
15015 for_each_intel_encoder(dev, encoder) {
15016 pipe = 0;
15017
15018 if (encoder->get_hw_state(encoder, &pipe)) {
15019 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15020 encoder->base.crtc = &crtc->base;
15021 encoder->get_config(encoder, crtc->config);
15022 } else {
15023 encoder->base.crtc = NULL;
15024 }
15025
15026 encoder->connectors_active = false;
15027 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15028 encoder->base.base.id,
15029 encoder->base.name,
15030 encoder->base.crtc ? "enabled" : "disabled",
15031 pipe_name(pipe));
15032 }
15033
15034 for_each_intel_connector(dev, connector) {
15035 if (connector->get_hw_state(connector)) {
15036 connector->base.dpms = DRM_MODE_DPMS_ON;
15037 connector->encoder->connectors_active = true;
15038 connector->base.encoder = &connector->encoder->base;
15039 } else {
15040 connector->base.dpms = DRM_MODE_DPMS_OFF;
15041 connector->base.encoder = NULL;
15042 }
15043 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15044 connector->base.base.id,
15045 connector->base.name,
15046 connector->base.encoder ? "enabled" : "disabled");
15047 }
15048}
15049
15050/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15051 * and i915 state tracking structures. */
15052void intel_modeset_setup_hw_state(struct drm_device *dev,
15053 bool force_restore)
15054{
15055 struct drm_i915_private *dev_priv = dev->dev_private;
15056 enum pipe pipe;
15057 struct intel_crtc *crtc;
15058 struct intel_encoder *encoder;
15059 int i;
15060
15061 intel_modeset_readout_hw_state(dev);
15062
15063 /*
15064 * Now that we have the config, copy it to each CRTC struct
15065 * Note that this could go away if we move to using crtc_config
15066 * checking everywhere.
15067 */
15068 for_each_intel_crtc(dev, crtc) {
15069 if (crtc->active && i915.fastboot) {
15070 intel_mode_from_pipe_config(&crtc->base.mode,
15071 crtc->config);
15072 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15073 crtc->base.base.id);
15074 drm_mode_debug_printmodeline(&crtc->base.mode);
15075 }
15076 }
15077
15078 /* HW state is read out, now we need to sanitize this mess. */
15079 for_each_intel_encoder(dev, encoder) {
15080 intel_sanitize_encoder(encoder);
15081 }
15082
15083 for_each_pipe(dev_priv, pipe) {
15084 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15085 intel_sanitize_crtc(crtc);
15086 intel_dump_pipe_config(crtc, crtc->config,
15087 "[setup_hw_state]");
15088 }
15089
15090 intel_modeset_update_connector_atomic_state(dev);
15091
15092 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15093 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15094
15095 if (!pll->on || pll->active)
15096 continue;
15097
15098 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15099
15100 pll->disable(dev_priv, pll);
15101 pll->on = false;
15102 }
15103
15104 if (IS_GEN9(dev))
15105 skl_wm_get_hw_state(dev);
15106 else if (HAS_PCH_SPLIT(dev))
15107 ilk_wm_get_hw_state(dev);
15108
15109 if (force_restore) {
15110 i915_redisable_vga(dev);
15111
15112 /*
15113 * We need to use raw interfaces for restoring state to avoid
15114 * checking (bogus) intermediate states.
15115 */
15116 for_each_pipe(dev_priv, pipe) {
15117 struct drm_crtc *crtc =
15118 dev_priv->pipe_to_crtc_mapping[pipe];
15119
15120 intel_crtc_restore_mode(crtc);
15121 }
15122 } else {
15123 intel_modeset_update_staged_output_state(dev);
15124 }
15125
15126 intel_modeset_check_state(dev);
15127}
15128
15129void intel_modeset_gem_init(struct drm_device *dev)
15130{
15131 struct drm_i915_private *dev_priv = dev->dev_private;
15132 struct drm_crtc *c;
15133 struct drm_i915_gem_object *obj;
15134 int ret;
15135
15136 mutex_lock(&dev->struct_mutex);
15137 intel_init_gt_powersave(dev);
15138 mutex_unlock(&dev->struct_mutex);
15139
15140 /*
15141 * There may be no VBT; and if the BIOS enabled SSC we can
15142 * just keep using it to avoid unnecessary flicker. Whereas if the
15143 * BIOS isn't using it, don't assume it will work even if the VBT
15144 * indicates as much.
15145 */
15146 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15147 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15148 DREF_SSC1_ENABLE);
15149
15150 intel_modeset_init_hw(dev);
15151
15152 intel_setup_overlay(dev);
15153
15154 /*
15155 * Make sure any fbs we allocated at startup are properly
15156 * pinned & fenced. When we do the allocation it's too early
15157 * for this.
15158 */
15159 for_each_crtc(dev, c) {
15160 obj = intel_fb_obj(c->primary->fb);
15161 if (obj == NULL)
15162 continue;
15163
15164 mutex_lock(&dev->struct_mutex);
15165 ret = intel_pin_and_fence_fb_obj(c->primary,
15166 c->primary->fb,
15167 c->primary->state,
15168 NULL);
15169 mutex_unlock(&dev->struct_mutex);
15170 if (ret) {
15171 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15172 to_intel_crtc(c)->pipe);
15173 drm_framebuffer_unreference(c->primary->fb);
15174 c->primary->fb = NULL;
15175 update_state_fb(c->primary);
15176 }
15177 }
15178
15179 intel_backlight_register(dev);
15180}
15181
15182void intel_connector_unregister(struct intel_connector *intel_connector)
15183{
15184 struct drm_connector *connector = &intel_connector->base;
15185
15186 intel_panel_destroy_backlight(connector);
15187 drm_connector_unregister(connector);
15188}
15189
15190void intel_modeset_cleanup(struct drm_device *dev)
15191{
15192 struct drm_i915_private *dev_priv = dev->dev_private;
15193 struct drm_connector *connector;
15194
15195 intel_disable_gt_powersave(dev);
15196
15197 intel_backlight_unregister(dev);
15198
15199 /*
15200 * Interrupts and polling as the first thing to avoid creating havoc.
15201 * Too much stuff here (turning of connectors, ...) would
15202 * experience fancy races otherwise.
15203 */
15204 intel_irq_uninstall(dev_priv);
15205
15206 /*
15207 * Due to the hpd irq storm handling the hotplug work can re-arm the
15208 * poll handlers. Hence disable polling after hpd handling is shut down.
15209 */
15210 drm_kms_helper_poll_fini(dev);
15211
15212 mutex_lock(&dev->struct_mutex);
15213
15214 intel_unregister_dsm_handler();
15215
15216 intel_fbc_disable(dev);
15217
15218 mutex_unlock(&dev->struct_mutex);
15219
15220 /* flush any delayed tasks or pending work */
15221 flush_scheduled_work();
15222
15223 /* destroy the backlight and sysfs files before encoders/connectors */
15224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15225 struct intel_connector *intel_connector;
15226
15227 intel_connector = to_intel_connector(connector);
15228 intel_connector->unregister(intel_connector);
15229 }
15230
15231 drm_mode_config_cleanup(dev);
15232
15233 intel_cleanup_overlay(dev);
15234
15235 mutex_lock(&dev->struct_mutex);
15236 intel_cleanup_gt_powersave(dev);
15237 mutex_unlock(&dev->struct_mutex);
15238}
15239
15240/*
15241 * Return which encoder is currently attached for connector.
15242 */
15243struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15244{
15245 return &intel_attached_encoder(connector)->base;
15246}
15247
15248void intel_connector_attach_encoder(struct intel_connector *connector,
15249 struct intel_encoder *encoder)
15250{
15251 connector->encoder = encoder;
15252 drm_mode_connector_attach_encoder(&connector->base,
15253 &encoder->base);
15254}
15255
15256/*
15257 * set vga decode state - true == enable VGA decode
15258 */
15259int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15260{
15261 struct drm_i915_private *dev_priv = dev->dev_private;
15262 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15263 u16 gmch_ctrl;
15264
15265 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15266 DRM_ERROR("failed to read control word\n");
15267 return -EIO;
15268 }
15269
15270 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15271 return 0;
15272
15273 if (state)
15274 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15275 else
15276 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15277
15278 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15279 DRM_ERROR("failed to write control word\n");
15280 return -EIO;
15281 }
15282
15283 return 0;
15284}
15285
15286struct intel_display_error_state {
15287
15288 u32 power_well_driver;
15289
15290 int num_transcoders;
15291
15292 struct intel_cursor_error_state {
15293 u32 control;
15294 u32 position;
15295 u32 base;
15296 u32 size;
15297 } cursor[I915_MAX_PIPES];
15298
15299 struct intel_pipe_error_state {
15300 bool power_domain_on;
15301 u32 source;
15302 u32 stat;
15303 } pipe[I915_MAX_PIPES];
15304
15305 struct intel_plane_error_state {
15306 u32 control;
15307 u32 stride;
15308 u32 size;
15309 u32 pos;
15310 u32 addr;
15311 u32 surface;
15312 u32 tile_offset;
15313 } plane[I915_MAX_PIPES];
15314
15315 struct intel_transcoder_error_state {
15316 bool power_domain_on;
15317 enum transcoder cpu_transcoder;
15318
15319 u32 conf;
15320
15321 u32 htotal;
15322 u32 hblank;
15323 u32 hsync;
15324 u32 vtotal;
15325 u32 vblank;
15326 u32 vsync;
15327 } transcoder[4];
15328};
15329
15330struct intel_display_error_state *
15331intel_display_capture_error_state(struct drm_device *dev)
15332{
15333 struct drm_i915_private *dev_priv = dev->dev_private;
15334 struct intel_display_error_state *error;
15335 int transcoders[] = {
15336 TRANSCODER_A,
15337 TRANSCODER_B,
15338 TRANSCODER_C,
15339 TRANSCODER_EDP,
15340 };
15341 int i;
15342
15343 if (INTEL_INFO(dev)->num_pipes == 0)
15344 return NULL;
15345
15346 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15347 if (error == NULL)
15348 return NULL;
15349
15350 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15351 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15352
15353 for_each_pipe(dev_priv, i) {
15354 error->pipe[i].power_domain_on =
15355 __intel_display_power_is_enabled(dev_priv,
15356 POWER_DOMAIN_PIPE(i));
15357 if (!error->pipe[i].power_domain_on)
15358 continue;
15359
15360 error->cursor[i].control = I915_READ(CURCNTR(i));
15361 error->cursor[i].position = I915_READ(CURPOS(i));
15362 error->cursor[i].base = I915_READ(CURBASE(i));
15363
15364 error->plane[i].control = I915_READ(DSPCNTR(i));
15365 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15366 if (INTEL_INFO(dev)->gen <= 3) {
15367 error->plane[i].size = I915_READ(DSPSIZE(i));
15368 error->plane[i].pos = I915_READ(DSPPOS(i));
15369 }
15370 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15371 error->plane[i].addr = I915_READ(DSPADDR(i));
15372 if (INTEL_INFO(dev)->gen >= 4) {
15373 error->plane[i].surface = I915_READ(DSPSURF(i));
15374 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15375 }
15376
15377 error->pipe[i].source = I915_READ(PIPESRC(i));
15378
15379 if (HAS_GMCH_DISPLAY(dev))
15380 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15381 }
15382
15383 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15384 if (HAS_DDI(dev_priv->dev))
15385 error->num_transcoders++; /* Account for eDP. */
15386
15387 for (i = 0; i < error->num_transcoders; i++) {
15388 enum transcoder cpu_transcoder = transcoders[i];
15389
15390 error->transcoder[i].power_domain_on =
15391 __intel_display_power_is_enabled(dev_priv,
15392 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15393 if (!error->transcoder[i].power_domain_on)
15394 continue;
15395
15396 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15397
15398 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15399 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15400 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15401 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15402 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15403 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15404 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15405 }
15406
15407 return error;
15408}
15409
15410#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15411
15412void
15413intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15414 struct drm_device *dev,
15415 struct intel_display_error_state *error)
15416{
15417 struct drm_i915_private *dev_priv = dev->dev_private;
15418 int i;
15419
15420 if (!error)
15421 return;
15422
15423 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15424 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15425 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15426 error->power_well_driver);
15427 for_each_pipe(dev_priv, i) {
15428 err_printf(m, "Pipe [%d]:\n", i);
15429 err_printf(m, " Power: %s\n",
15430 error->pipe[i].power_domain_on ? "on" : "off");
15431 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15432 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15433
15434 err_printf(m, "Plane [%d]:\n", i);
15435 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15436 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15437 if (INTEL_INFO(dev)->gen <= 3) {
15438 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15439 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15440 }
15441 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15442 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15443 if (INTEL_INFO(dev)->gen >= 4) {
15444 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15445 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15446 }
15447
15448 err_printf(m, "Cursor [%d]:\n", i);
15449 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15450 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15451 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15452 }
15453
15454 for (i = 0; i < error->num_transcoders; i++) {
15455 err_printf(m, "CPU transcoder: %c\n",
15456 transcoder_name(error->transcoder[i].cpu_transcoder));
15457 err_printf(m, " Power: %s\n",
15458 error->transcoder[i].power_domain_on ? "on" : "off");
15459 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15460 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15461 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15462 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15463 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15464 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15465 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15466 }
15467}
15468
15469void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15470{
15471 struct intel_crtc *crtc;
15472
15473 for_each_intel_crtc(dev, crtc) {
15474 struct intel_unpin_work *work;
15475
15476 spin_lock_irq(&dev->event_lock);
15477
15478 work = crtc->unpin_work;
15479
15480 if (work && work->event &&
15481 work->event->base.file_priv == file) {
15482 kfree(work->event);
15483 work->event = NULL;
15484 }
15485
15486 spin_unlock_irq(&dev->event_lock);
15487 }
15488}
Linux kernel - Deliverables
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