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drm/i915: Helper function to determine GGTT view from plane state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/module.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/slab.h>
33#include <linux/vgaarb.h>
34#include <drm/drm_edid.h>
35#include <drm/drmP.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39#include "i915_trace.h"
40#include <drm/drm_atomic.h>
41#include <drm/drm_atomic_helper.h>
42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
46#include <linux/dma_remapping.h>
47
48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97static void haswell_set_pipeconf(struct drm_crtc *crtc);
98static void intel_set_pipe_csc(struct drm_crtc *crtc);
99static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107{
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112}
113
114typedef struct {
115 int min, max;
116} intel_range_t;
117
118typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121} intel_p2_t;
122
123typedef struct intel_limit intel_limit_t;
124struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127};
128
129int
130intel_pch_rawclk(struct drm_device *dev)
131{
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137}
138
139static inline u32 /* units of 100MHz */
140intel_fdi_link_freq(struct drm_device *dev)
141{
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147}
148
149static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160};
161
162static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173};
174
175static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186};
187
188static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199};
200
201static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212};
213
214
215static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228};
229
230static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241};
242
243static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255};
256
257static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269};
270
271static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284};
285
286static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297};
298
299/* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315};
316
317static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341};
342
343/* LVDS 100mhz refclk limits. */
344static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355};
356
357static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368};
369
370static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384};
385
386static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400};
401
402static void vlv_clock(int refclk, intel_clock_t *clock)
403{
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410}
411
412/**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416{
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425}
426
427/**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434{
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443}
444
445static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447{
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467}
468
469static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470{
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488}
489
490static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491{
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522}
523
524/* m1 is reserved as 0 in Pineview, n is a ring counter */
525static void pineview_clock(int refclk, intel_clock_t *clock)
526{
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533}
534
535static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536{
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538}
539
540static void i9xx_clock(int refclk, intel_clock_t *clock)
541{
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548}
549
550static void chv_clock(int refclk, intel_clock_t *clock)
551{
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559}
560
561#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562/**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570{
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600}
601
602static bool
603i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606{
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661}
662
663static bool
664pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667{
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720}
721
722static bool
723g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726{
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777}
778
779/*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788{
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(dev)) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817}
818
819static bool
820vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
821 int target, int refclk, intel_clock_t *match_clock,
822 intel_clock_t *best_clock)
823{
824 struct drm_device *dev = crtc->base.dev;
825 intel_clock_t clock;
826 unsigned int bestppm = 1000000;
827 /* min update 19.2 MHz */
828 int max_n = min(limit->n.max, refclk / 19200);
829 bool found = false;
830
831 target *= 5; /* fast clock */
832
833 memset(best_clock, 0, sizeof(*best_clock));
834
835 /* based on hardware requirement, prefer smaller n to precision */
836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
840 clock.p = clock.p1 * clock.p2;
841 /* based on hardware requirement, prefer bigger m1,m2 values */
842 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
843 unsigned int ppm;
844
845 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
846 refclk * clock.m1);
847
848 vlv_clock(refclk, &clock);
849
850 if (!intel_PLL_is_valid(dev, limit,
851 &clock))
852 continue;
853
854 if (!vlv_PLL_is_optimal(dev, target,
855 &clock,
856 best_clock,
857 bestppm, &ppm))
858 continue;
859
860 *best_clock = clock;
861 bestppm = ppm;
862 found = true;
863 }
864 }
865 }
866 }
867
868 return found;
869}
870
871static bool
872chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 struct drm_device *dev = crtc->base.dev;
877 unsigned int best_error_ppm;
878 intel_clock_t clock;
879 uint64_t m2;
880 int found = false;
881
882 memset(best_clock, 0, sizeof(*best_clock));
883 best_error_ppm = 1000000;
884
885 /*
886 * Based on hardware doc, the n always set to 1, and m1 always
887 * set to 2. If requires to support 200Mhz refclk, we need to
888 * revisit this because n may not 1 anymore.
889 */
890 clock.n = 1, clock.m1 = 2;
891 target *= 5; /* fast clock */
892
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast;
895 clock.p2 >= limit->p2.p2_slow;
896 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
897 unsigned int error_ppm;
898
899 clock.p = clock.p1 * clock.p2;
900
901 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
902 clock.n) << 22, refclk * clock.m1);
903
904 if (m2 > INT_MAX/clock.m1)
905 continue;
906
907 clock.m2 = m2;
908
909 chv_clock(refclk, &clock);
910
911 if (!intel_PLL_is_valid(dev, limit, &clock))
912 continue;
913
914 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
915 best_error_ppm, &error_ppm))
916 continue;
917
918 *best_clock = clock;
919 best_error_ppm = error_ppm;
920 found = true;
921 }
922 }
923
924 return found;
925}
926
927bool intel_crtc_active(struct drm_crtc *crtc)
928{
929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
930
931 /* Be paranoid as we can arrive here with only partial
932 * state retrieved from the hardware during setup.
933 *
934 * We can ditch the adjusted_mode.crtc_clock check as soon
935 * as Haswell has gained clock readout/fastboot support.
936 *
937 * We can ditch the crtc->primary->fb check as soon as we can
938 * properly reconstruct framebuffers.
939 *
940 * FIXME: The intel_crtc->active here should be switched to
941 * crtc->state->active once we have proper CRTC states wired up
942 * for atomic.
943 */
944 return intel_crtc->active && crtc->primary->state->fb &&
945 intel_crtc->config->base.adjusted_mode.crtc_clock;
946}
947
948enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
953
954 return intel_crtc->config->cpu_transcoder;
955}
956
957static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
958{
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 reg = PIPEDSL(pipe);
961 u32 line1, line2;
962 u32 line_mask;
963
964 if (IS_GEN2(dev))
965 line_mask = DSL_LINEMASK_GEN2;
966 else
967 line_mask = DSL_LINEMASK_GEN3;
968
969 line1 = I915_READ(reg) & line_mask;
970 mdelay(5);
971 line2 = I915_READ(reg) & line_mask;
972
973 return line1 == line2;
974}
975
976/*
977 * intel_wait_for_pipe_off - wait for pipe to turn off
978 * @crtc: crtc whose pipe to wait for
979 *
980 * After disabling a pipe, we can't wait for vblank in the usual way,
981 * spinning on the vblank interrupt status bit, since we won't actually
982 * see an interrupt when the pipe is disabled.
983 *
984 * On Gen4 and above:
985 * wait for the pipe register state bit to turn off
986 *
987 * Otherwise:
988 * wait for the display line value to settle (it usually
989 * ends up stopping at the start of the next frame).
990 *
991 */
992static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
993{
994 struct drm_device *dev = crtc->base.dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
997 enum pipe pipe = crtc->pipe;
998
999 if (INTEL_INFO(dev)->gen >= 4) {
1000 int reg = PIPECONF(cpu_transcoder);
1001
1002 /* Wait for the Pipe State to go off */
1003 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004 100))
1005 WARN(1, "pipe_off wait timed out\n");
1006 } else {
1007 /* Wait for the display line to settle */
1008 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1009 WARN(1, "pipe_off wait timed out\n");
1010 }
1011}
1012
1013/*
1014 * ibx_digital_port_connected - is the specified port connected?
1015 * @dev_priv: i915 private structure
1016 * @port: the port to test
1017 *
1018 * Returns true if @port is connected, false otherwise.
1019 */
1020bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021 struct intel_digital_port *port)
1022{
1023 u32 bit;
1024
1025 if (HAS_PCH_IBX(dev_priv->dev)) {
1026 switch (port->port) {
1027 case PORT_B:
1028 bit = SDE_PORTB_HOTPLUG;
1029 break;
1030 case PORT_C:
1031 bit = SDE_PORTC_HOTPLUG;
1032 break;
1033 case PORT_D:
1034 bit = SDE_PORTD_HOTPLUG;
1035 break;
1036 default:
1037 return true;
1038 }
1039 } else {
1040 switch (port->port) {
1041 case PORT_B:
1042 bit = SDE_PORTB_HOTPLUG_CPT;
1043 break;
1044 case PORT_C:
1045 bit = SDE_PORTC_HOTPLUG_CPT;
1046 break;
1047 case PORT_D:
1048 bit = SDE_PORTD_HOTPLUG_CPT;
1049 break;
1050 default:
1051 return true;
1052 }
1053 }
1054
1055 return I915_READ(SDEISR) & bit;
1056}
1057
1058static const char *state_string(bool enabled)
1059{
1060 return enabled ? "on" : "off";
1061}
1062
1063/* Only for pre-ILK configs */
1064void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
1066{
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070
1071 reg = DPLL(pipe);
1072 val = I915_READ(reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 I915_STATE_WARN(cur_state != state,
1075 "PLL state assertion failure (expected %s, current %s)\n",
1076 state_string(state), state_string(cur_state));
1077}
1078
1079/* XXX: the dsi pll is shared between MIPI DSI ports */
1080static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081{
1082 u32 val;
1083 bool cur_state;
1084
1085 mutex_lock(&dev_priv->dpio_lock);
1086 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087 mutex_unlock(&dev_priv->dpio_lock);
1088
1089 cur_state = val & DSI_PLL_VCO_EN;
1090 I915_STATE_WARN(cur_state != state,
1091 "DSI PLL state assertion failure (expected %s, current %s)\n",
1092 state_string(state), state_string(cur_state));
1093}
1094#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
1097struct intel_shared_dpll *
1098intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099{
1100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
1102 if (crtc->config->shared_dpll < 0)
1103 return NULL;
1104
1105 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1106}
1107
1108/* For ILK+ */
1109void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110 struct intel_shared_dpll *pll,
1111 bool state)
1112{
1113 bool cur_state;
1114 struct intel_dpll_hw_state hw_state;
1115
1116 if (WARN (!pll,
1117 "asserting DPLL %s with no DPLL\n", state_string(state)))
1118 return;
1119
1120 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1121 I915_STATE_WARN(cur_state != state,
1122 "%s assertion failure (expected %s, current %s)\n",
1123 pll->name, state_string(state), state_string(cur_state));
1124}
1125
1126static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128{
1129 int reg;
1130 u32 val;
1131 bool cur_state;
1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133 pipe);
1134
1135 if (HAS_DDI(dev_priv->dev)) {
1136 /* DDI does not have a specific FDI_TX register */
1137 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1138 val = I915_READ(reg);
1139 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1140 } else {
1141 reg = FDI_TX_CTL(pipe);
1142 val = I915_READ(reg);
1143 cur_state = !!(val & FDI_TX_ENABLE);
1144 }
1145 I915_STATE_WARN(cur_state != state,
1146 "FDI TX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148}
1149#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153 enum pipe pipe, bool state)
1154{
1155 int reg;
1156 u32 val;
1157 bool cur_state;
1158
1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 cur_state = !!(val & FDI_RX_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1177 return;
1178
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (HAS_DDI(dev_priv->dev))
1181 return;
1182
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
1190{
1191 int reg;
1192 u32 val;
1193 bool cur_state;
1194
1195 reg = FDI_RX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1198 I915_STATE_WARN(cur_state != state,
1199 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
1201}
1202
1203void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 struct drm_device *dev = dev_priv->dev;
1207 int pp_reg;
1208 u32 val;
1209 enum pipe panel_pipe = PIPE_A;
1210 bool locked = true;
1211
1212 if (WARN_ON(HAS_DDI(dev)))
1213 return;
1214
1215 if (HAS_PCH_SPLIT(dev)) {
1216 u32 port_sel;
1217
1218 pp_reg = PCH_PP_CONTROL;
1219 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224 /* XXX: else fix for eDP */
1225 } else if (IS_VALLEYVIEW(dev)) {
1226 /* presumably write lock depends on pipe, not port select */
1227 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228 panel_pipe = pipe;
1229 } else {
1230 pp_reg = PP_CONTROL;
1231 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232 panel_pipe = PIPE_B;
1233 }
1234
1235 val = I915_READ(pp_reg);
1236 if (!(val & PANEL_POWER_ON) ||
1237 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1238 locked = false;
1239
1240 I915_STATE_WARN(panel_pipe == pipe && locked,
1241 "panel assertion failure, pipe %c regs locked\n",
1242 pipe_name(pipe));
1243}
1244
1245static void assert_cursor(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247{
1248 struct drm_device *dev = dev_priv->dev;
1249 bool cur_state;
1250
1251 if (IS_845G(dev) || IS_I865G(dev))
1252 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1253 else
1254 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1255
1256 I915_STATE_WARN(cur_state != state,
1257 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258 pipe_name(pipe), state_string(state), state_string(cur_state));
1259}
1260#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
1263void assert_pipe(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, bool state)
1265{
1266 int reg;
1267 u32 val;
1268 bool cur_state;
1269 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270 pipe);
1271
1272 /* if we need the pipe quirk it must be always on */
1273 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1275 state = true;
1276
1277 if (!intel_display_power_is_enabled(dev_priv,
1278 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1279 cur_state = false;
1280 } else {
1281 reg = PIPECONF(cpu_transcoder);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & PIPECONF_ENABLE);
1284 }
1285
1286 I915_STATE_WARN(cur_state != state,
1287 "pipe %c assertion failure (expected %s, current %s)\n",
1288 pipe_name(pipe), state_string(state), state_string(cur_state));
1289}
1290
1291static void assert_plane(struct drm_i915_private *dev_priv,
1292 enum plane plane, bool state)
1293{
1294 int reg;
1295 u32 val;
1296 bool cur_state;
1297
1298 reg = DSPCNTR(plane);
1299 val = I915_READ(reg);
1300 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1301 I915_STATE_WARN(cur_state != state,
1302 "plane %c assertion failure (expected %s, current %s)\n",
1303 plane_name(plane), state_string(state), state_string(cur_state));
1304}
1305
1306#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
1309static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311{
1312 struct drm_device *dev = dev_priv->dev;
1313 int reg, i;
1314 u32 val;
1315 int cur_pipe;
1316
1317 /* Primary planes are fixed to pipes on gen4+ */
1318 if (INTEL_INFO(dev)->gen >= 4) {
1319 reg = DSPCNTR(pipe);
1320 val = I915_READ(reg);
1321 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1322 "plane %c assertion failure, should be disabled but not\n",
1323 plane_name(pipe));
1324 return;
1325 }
1326
1327 /* Need to check both planes against the pipe */
1328 for_each_pipe(dev_priv, i) {
1329 reg = DSPCNTR(i);
1330 val = I915_READ(reg);
1331 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332 DISPPLANE_SEL_PIPE_SHIFT;
1333 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1334 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(i), pipe_name(pipe));
1336 }
1337}
1338
1339static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
1342 struct drm_device *dev = dev_priv->dev;
1343 int reg, sprite;
1344 u32 val;
1345
1346 if (INTEL_INFO(dev)->gen >= 9) {
1347 for_each_sprite(dev_priv, pipe, sprite) {
1348 val = I915_READ(PLANE_CTL(pipe, sprite));
1349 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1350 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351 sprite, pipe_name(pipe));
1352 }
1353 } else if (IS_VALLEYVIEW(dev)) {
1354 for_each_sprite(dev_priv, pipe, sprite) {
1355 reg = SPCNTR(pipe, sprite);
1356 val = I915_READ(reg);
1357 I915_STATE_WARN(val & SP_ENABLE,
1358 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1359 sprite_name(pipe, sprite), pipe_name(pipe));
1360 }
1361 } else if (INTEL_INFO(dev)->gen >= 7) {
1362 reg = SPRCTL(pipe);
1363 val = I915_READ(reg);
1364 I915_STATE_WARN(val & SPRITE_ENABLE,
1365 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(pipe), pipe_name(pipe));
1367 } else if (INTEL_INFO(dev)->gen >= 5) {
1368 reg = DVSCNTR(pipe);
1369 val = I915_READ(reg);
1370 I915_STATE_WARN(val & DVS_ENABLE,
1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1372 plane_name(pipe), pipe_name(pipe));
1373 }
1374}
1375
1376static void assert_vblank_disabled(struct drm_crtc *crtc)
1377{
1378 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1379 drm_crtc_vblank_put(crtc);
1380}
1381
1382static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1383{
1384 u32 val;
1385 bool enabled;
1386
1387 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1388
1389 val = I915_READ(PCH_DREF_CONTROL);
1390 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391 DREF_SUPERSPREAD_SOURCE_MASK));
1392 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1393}
1394
1395static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
1400 bool enabled;
1401
1402 reg = PCH_TRANSCONF(pipe);
1403 val = I915_READ(reg);
1404 enabled = !!(val & TRANS_ENABLE);
1405 I915_STATE_WARN(enabled,
1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407 pipe_name(pipe));
1408}
1409
1410static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
1412{
1413 if ((val & DP_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
1421 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429}
1430
1431static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433{
1434 if ((val & SDVO_ENABLE) == 0)
1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv->dev)) {
1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439 return false;
1440 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1443 } else {
1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445 return false;
1446 }
1447 return true;
1448}
1449
1450static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452{
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464}
1465
1466static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468{
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479}
1480
1481static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg, u32 port_sel)
1483{
1484 u32 val = I915_READ(reg);
1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1487 reg, pipe_name(pipe));
1488
1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1490 && (val & DP_PIPEB_SELECT),
1491 "IBX PCH dp port still using transcoder B\n");
1492}
1493
1494static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, int reg)
1496{
1497 u32 val = I915_READ(reg);
1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1500 reg, pipe_name(pipe));
1501
1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1503 && (val & SDVO_PIPE_B_SELECT),
1504 "IBX PCH hdmi port still using transcoder B\n");
1505}
1506
1507static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508 enum pipe pipe)
1509{
1510 int reg;
1511 u32 val;
1512
1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517 reg = PCH_ADPA;
1518 val = I915_READ(reg);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 reg = PCH_LVDS;
1524 val = I915_READ(reg);
1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1527 pipe_name(pipe));
1528
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1532}
1533
1534static void intel_init_dpio(struct drm_device *dev)
1535{
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 if (!IS_VALLEYVIEW(dev))
1539 return;
1540
1541 /*
1542 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543 * CHV x1 PHY (DP/HDMI D)
1544 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545 */
1546 if (IS_CHERRYVIEW(dev)) {
1547 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549 } else {
1550 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551 }
1552}
1553
1554static void vlv_enable_pll(struct intel_crtc *crtc,
1555 const struct intel_crtc_state *pipe_config)
1556{
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int reg = DPLL(crtc->pipe);
1560 u32 dpll = pipe_config->dpll_hw_state.dpll;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 /* No really, not for ILK+ */
1565 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567 /* PLL is protected by panel, make sure we can write it */
1568 if (IS_MOBILE(dev_priv->dev))
1569 assert_panel_unlocked(dev_priv, crtc->pipe);
1570
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150);
1574
1575 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
1578 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1579 POSTING_READ(DPLL_MD(crtc->pipe));
1580
1581 /* We do this three times for luck */
1582 I915_WRITE(reg, dpll);
1583 POSTING_READ(reg);
1584 udelay(150); /* wait for warmup */
1585 I915_WRITE(reg, dpll);
1586 POSTING_READ(reg);
1587 udelay(150); /* wait for warmup */
1588 I915_WRITE(reg, dpll);
1589 POSTING_READ(reg);
1590 udelay(150); /* wait for warmup */
1591}
1592
1593static void chv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595{
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 int pipe = crtc->pipe;
1599 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1600 u32 tmp;
1601
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606 mutex_lock(&dev_priv->dpio_lock);
1607
1608 /* Enable back the 10bit clock to display controller */
1609 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 tmp |= DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613 /*
1614 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615 */
1616 udelay(1);
1617
1618 /* Enable PLL */
1619 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1620
1621 /* Check PLL is locked */
1622 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1623 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
1625 /* not sure when this should be written */
1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1627 POSTING_READ(DPLL_MD(pipe));
1628
1629 mutex_unlock(&dev_priv->dpio_lock);
1630}
1631
1632static int intel_num_dvo_pipes(struct drm_device *dev)
1633{
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->active &&
1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641 return count;
1642}
1643
1644static void i9xx_enable_pll(struct intel_crtc *crtc)
1645{
1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int reg = DPLL(crtc->pipe);
1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651 assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653 /* No really, not for ILK+ */
1654 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1655
1656 /* PLL is protected by panel, make sure we can write it */
1657 if (IS_MOBILE(dev) && !IS_I830(dev))
1658 assert_panel_unlocked(dev_priv, crtc->pipe);
1659
1660 /* Enable DVO 2x clock on both PLLs if necessary */
1661 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662 /*
1663 * It appears to be important that we don't enable this
1664 * for the current pipe before otherwise configuring the
1665 * PLL. No idea how this should be handled if multiple
1666 * DVO outputs are enabled simultaneosly.
1667 */
1668 dpll |= DPLL_DVO_2X_MODE;
1669 I915_WRITE(DPLL(!crtc->pipe),
1670 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671 }
1672
1673 /* Wait for the clocks to stabilize. */
1674 POSTING_READ(reg);
1675 udelay(150);
1676
1677 if (INTEL_INFO(dev)->gen >= 4) {
1678 I915_WRITE(DPLL_MD(crtc->pipe),
1679 crtc->config->dpll_hw_state.dpll_md);
1680 } else {
1681 /* The pixel multiplier can only be updated once the
1682 * DPLL is enabled and the clocks are stable.
1683 *
1684 * So write it again.
1685 */
1686 I915_WRITE(reg, dpll);
1687 }
1688
1689 /* We do this three times for luck */
1690 I915_WRITE(reg, dpll);
1691 POSTING_READ(reg);
1692 udelay(150); /* wait for warmup */
1693 I915_WRITE(reg, dpll);
1694 POSTING_READ(reg);
1695 udelay(150); /* wait for warmup */
1696 I915_WRITE(reg, dpll);
1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699}
1700
1701/**
1702 * i9xx_disable_pll - disable a PLL
1703 * @dev_priv: i915 private structure
1704 * @pipe: pipe PLL to disable
1705 *
1706 * Disable the PLL for @pipe, making sure the pipe is off first.
1707 *
1708 * Note! This is for pre-ILK only.
1709 */
1710static void i9xx_disable_pll(struct intel_crtc *crtc)
1711{
1712 struct drm_device *dev = crtc->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 enum pipe pipe = crtc->pipe;
1715
1716 /* Disable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) &&
1718 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1719 intel_num_dvo_pipes(dev) == 1) {
1720 I915_WRITE(DPLL(PIPE_B),
1721 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722 I915_WRITE(DPLL(PIPE_A),
1723 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724 }
1725
1726 /* Don't disable pipe or pipe PLLs if needed */
1727 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1729 return;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
1734 I915_WRITE(DPLL(pipe), 0);
1735 POSTING_READ(DPLL(pipe));
1736}
1737
1738static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739{
1740 u32 val = 0;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 /*
1746 * Leave integrated clock source and reference clock enabled for pipe B.
1747 * The latter is needed for VGA hotplug / manual detection.
1748 */
1749 if (pipe == PIPE_B)
1750 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1753
1754}
1755
1756static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757{
1758 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1759 u32 val;
1760
1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
1763
1764 /* Set PLL en = 0 */
1765 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1766 if (pipe != PIPE_A)
1767 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
1770
1771 mutex_lock(&dev_priv->dpio_lock);
1772
1773 /* Disable 10bit clock to display controller */
1774 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775 val &= ~DPIO_DCLKP_EN;
1776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
1778 /* disable left/right clock distribution */
1779 if (pipe != PIPE_B) {
1780 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783 } else {
1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787 }
1788
1789 mutex_unlock(&dev_priv->dpio_lock);
1790}
1791
1792void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793 struct intel_digital_port *dport)
1794{
1795 u32 port_mask;
1796 int dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 break;
1807 case PORT_D:
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
1810 break;
1811 default:
1812 BUG();
1813 }
1814
1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1816 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1817 port_name(dport->port), I915_READ(dpll_reg));
1818}
1819
1820static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821{
1822 struct drm_device *dev = crtc->base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
1826 if (WARN_ON(pll == NULL))
1827 return;
1828
1829 WARN_ON(!pll->config.crtc_mask);
1830 if (pll->active == 0) {
1831 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832 WARN_ON(pll->on);
1833 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835 pll->mode_set(dev_priv, pll);
1836 }
1837}
1838
1839/**
1840 * intel_enable_shared_dpll - enable PCH PLL
1841 * @dev_priv: i915 private structure
1842 * @pipe: pipe PLL to enable
1843 *
1844 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845 * drives the transcoder clock.
1846 */
1847static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1848{
1849 struct drm_device *dev = crtc->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1852
1853 if (WARN_ON(pll == NULL))
1854 return;
1855
1856 if (WARN_ON(pll->config.crtc_mask == 0))
1857 return;
1858
1859 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1860 pll->name, pll->active, pll->on,
1861 crtc->base.base.id);
1862
1863 if (pll->active++) {
1864 WARN_ON(!pll->on);
1865 assert_shared_dpll_enabled(dev_priv, pll);
1866 return;
1867 }
1868 WARN_ON(pll->on);
1869
1870 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
1872 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1873 pll->enable(dev_priv, pll);
1874 pll->on = true;
1875}
1876
1877static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1878{
1879 struct drm_device *dev = crtc->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1882
1883 /* PCH only available on ILK+ */
1884 BUG_ON(INTEL_INFO(dev)->gen < 5);
1885 if (WARN_ON(pll == NULL))
1886 return;
1887
1888 if (WARN_ON(pll->config.crtc_mask == 0))
1889 return;
1890
1891 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892 pll->name, pll->active, pll->on,
1893 crtc->base.base.id);
1894
1895 if (WARN_ON(pll->active == 0)) {
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897 return;
1898 }
1899
1900 assert_shared_dpll_enabled(dev_priv, pll);
1901 WARN_ON(!pll->on);
1902 if (--pll->active)
1903 return;
1904
1905 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1906 pll->disable(dev_priv, pll);
1907 pll->on = false;
1908
1909 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1910}
1911
1912static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913 enum pipe pipe)
1914{
1915 struct drm_device *dev = dev_priv->dev;
1916 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1918 uint32_t reg, val, pipeconf_val;
1919
1920 /* PCH only available on ILK+ */
1921 BUG_ON(!HAS_PCH_SPLIT(dev));
1922
1923 /* Make sure PCH DPLL is enabled */
1924 assert_shared_dpll_enabled(dev_priv,
1925 intel_crtc_to_shared_dpll(intel_crtc));
1926
1927 /* FDI must be feeding us bits for PCH ports */
1928 assert_fdi_tx_enabled(dev_priv, pipe);
1929 assert_fdi_rx_enabled(dev_priv, pipe);
1930
1931 if (HAS_PCH_CPT(dev)) {
1932 /* Workaround: Set the timing override bit before enabling the
1933 * pch transcoder. */
1934 reg = TRANS_CHICKEN2(pipe);
1935 val = I915_READ(reg);
1936 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937 I915_WRITE(reg, val);
1938 }
1939
1940 reg = PCH_TRANSCONF(pipe);
1941 val = I915_READ(reg);
1942 pipeconf_val = I915_READ(PIPECONF(pipe));
1943
1944 if (HAS_PCH_IBX(dev_priv->dev)) {
1945 /*
1946 * make the BPC in transcoder be consistent with
1947 * that in pipeconf reg.
1948 */
1949 val &= ~PIPECONF_BPC_MASK;
1950 val |= pipeconf_val & PIPECONF_BPC_MASK;
1951 }
1952
1953 val &= ~TRANS_INTERLACE_MASK;
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1955 if (HAS_PCH_IBX(dev_priv->dev) &&
1956 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1957 val |= TRANS_LEGACY_INTERLACED_ILK;
1958 else
1959 val |= TRANS_INTERLACED;
1960 else
1961 val |= TRANS_PROGRESSIVE;
1962
1963 I915_WRITE(reg, val | TRANS_ENABLE);
1964 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1965 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1966}
1967
1968static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum transcoder cpu_transcoder)
1970{
1971 u32 val, pipeconf_val;
1972
1973 /* PCH only available on ILK+ */
1974 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1975
1976 /* FDI must be feeding us bits for PCH ports */
1977 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1978 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1979
1980 /* Workaround: set timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1984
1985 val = TRANS_ENABLE;
1986 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1987
1988 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989 PIPECONF_INTERLACED_ILK)
1990 val |= TRANS_INTERLACED;
1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
1994 I915_WRITE(LPT_TRANSCONF, val);
1995 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1996 DRM_ERROR("Failed to enable PCH transcoder\n");
1997}
1998
1999static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000 enum pipe pipe)
2001{
2002 struct drm_device *dev = dev_priv->dev;
2003 uint32_t reg, val;
2004
2005 /* FDI relies on the transcoder */
2006 assert_fdi_tx_disabled(dev_priv, pipe);
2007 assert_fdi_rx_disabled(dev_priv, pipe);
2008
2009 /* Ports must be off as well */
2010 assert_pch_ports_disabled(dev_priv, pipe);
2011
2012 reg = PCH_TRANSCONF(pipe);
2013 val = I915_READ(reg);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(reg, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2018 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2019
2020 if (!HAS_PCH_IBX(dev)) {
2021 /* Workaround: Clear the timing override chicken bit again. */
2022 reg = TRANS_CHICKEN2(pipe);
2023 val = I915_READ(reg);
2024 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(reg, val);
2026 }
2027}
2028
2029static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2030{
2031 u32 val;
2032
2033 val = I915_READ(LPT_TRANSCONF);
2034 val &= ~TRANS_ENABLE;
2035 I915_WRITE(LPT_TRANSCONF, val);
2036 /* wait for PCH transcoder off, transcoder state */
2037 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2038 DRM_ERROR("Failed to disable PCH transcoder\n");
2039
2040 /* Workaround: clear timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044}
2045
2046/**
2047 * intel_enable_pipe - enable a pipe, asserting requirements
2048 * @crtc: crtc responsible for the pipe
2049 *
2050 * Enable @crtc's pipe, making sure that various hardware specific requirements
2051 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2052 */
2053static void intel_enable_pipe(struct intel_crtc *crtc)
2054{
2055 struct drm_device *dev = crtc->base.dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe = crtc->pipe;
2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
2060 enum pipe pch_transcoder;
2061 int reg;
2062 u32 val;
2063
2064 assert_planes_disabled(dev_priv, pipe);
2065 assert_cursor_disabled(dev_priv, pipe);
2066 assert_sprites_disabled(dev_priv, pipe);
2067
2068 if (HAS_PCH_LPT(dev_priv->dev))
2069 pch_transcoder = TRANSCODER_A;
2070 else
2071 pch_transcoder = pipe;
2072
2073 /*
2074 * A pipe without a PLL won't actually be able to drive bits from
2075 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2076 * need the check.
2077 */
2078 if (!HAS_PCH_SPLIT(dev_priv->dev))
2079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2080 assert_dsi_pll_enabled(dev_priv);
2081 else
2082 assert_pll_enabled(dev_priv, pipe);
2083 else {
2084 if (crtc->config->has_pch_encoder) {
2085 /* if driving the PCH, we need FDI enabled */
2086 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2087 assert_fdi_tx_pll_enabled(dev_priv,
2088 (enum pipe) cpu_transcoder);
2089 }
2090 /* FIXME: assert CPU port conditions for SNB+ */
2091 }
2092
2093 reg = PIPECONF(cpu_transcoder);
2094 val = I915_READ(reg);
2095 if (val & PIPECONF_ENABLE) {
2096 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2098 return;
2099 }
2100
2101 I915_WRITE(reg, val | PIPECONF_ENABLE);
2102 POSTING_READ(reg);
2103}
2104
2105/**
2106 * intel_disable_pipe - disable a pipe, asserting requirements
2107 * @crtc: crtc whose pipes is to be disabled
2108 *
2109 * Disable the pipe of @crtc, making sure that various hardware
2110 * specific requirements are met, if applicable, e.g. plane
2111 * disabled, panel fitter off, etc.
2112 *
2113 * Will wait until the pipe has shut down before returning.
2114 */
2115static void intel_disable_pipe(struct intel_crtc *crtc)
2116{
2117 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2118 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2119 enum pipe pipe = crtc->pipe;
2120 int reg;
2121 u32 val;
2122
2123 /*
2124 * Make sure planes won't keep trying to pump pixels to us,
2125 * or we might hang the display.
2126 */
2127 assert_planes_disabled(dev_priv, pipe);
2128 assert_cursor_disabled(dev_priv, pipe);
2129 assert_sprites_disabled(dev_priv, pipe);
2130
2131 reg = PIPECONF(cpu_transcoder);
2132 val = I915_READ(reg);
2133 if ((val & PIPECONF_ENABLE) == 0)
2134 return;
2135
2136 /*
2137 * Double wide has implications for planes
2138 * so best keep it disabled when not needed.
2139 */
2140 if (crtc->config->double_wide)
2141 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143 /* Don't disable pipe or pipe PLLs if needed */
2144 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2146 val &= ~PIPECONF_ENABLE;
2147
2148 I915_WRITE(reg, val);
2149 if ((val & PIPECONF_ENABLE) == 0)
2150 intel_wait_for_pipe_off(crtc);
2151}
2152
2153/*
2154 * Plane regs are double buffered, going from enabled->disabled needs a
2155 * trigger in order to latch. The display address reg provides this.
2156 */
2157void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158 enum plane plane)
2159{
2160 struct drm_device *dev = dev_priv->dev;
2161 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2162
2163 I915_WRITE(reg, I915_READ(reg));
2164 POSTING_READ(reg);
2165}
2166
2167/**
2168 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2169 * @plane: plane to be enabled
2170 * @crtc: crtc for the plane
2171 *
2172 * Enable @plane on @crtc, making sure that the pipe is running first.
2173 */
2174static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175 struct drm_crtc *crtc)
2176{
2177 struct drm_device *dev = plane->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2182 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2183
2184 if (intel_crtc->primary_enabled)
2185 return;
2186
2187 intel_crtc->primary_enabled = true;
2188
2189 dev_priv->display.update_primary_plane(crtc, plane->fb,
2190 crtc->x, crtc->y);
2191
2192 /*
2193 * BDW signals flip done immediately if the plane
2194 * is disabled, even if the plane enable is already
2195 * armed to occur at the next vblank :(
2196 */
2197 if (IS_BROADWELL(dev))
2198 intel_wait_for_vblank(dev, intel_crtc->pipe);
2199}
2200
2201/**
2202 * intel_disable_primary_hw_plane - disable the primary hardware plane
2203 * @plane: plane to be disabled
2204 * @crtc: crtc for the plane
2205 *
2206 * Disable @plane on @crtc, making sure that the pipe is running first.
2207 */
2208static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209 struct drm_crtc *crtc)
2210{
2211 struct drm_device *dev = plane->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
2215 if (WARN_ON(!intel_crtc->active))
2216 return;
2217
2218 if (!intel_crtc->primary_enabled)
2219 return;
2220
2221 intel_crtc->primary_enabled = false;
2222
2223 dev_priv->display.update_primary_plane(crtc, plane->fb,
2224 crtc->x, crtc->y);
2225}
2226
2227static bool need_vtd_wa(struct drm_device *dev)
2228{
2229#ifdef CONFIG_INTEL_IOMMU
2230 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231 return true;
2232#endif
2233 return false;
2234}
2235
2236static unsigned int
2237intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238 uint64_t fb_format_modifier)
2239{
2240 unsigned int tile_height;
2241 uint32_t pixel_bytes;
2242
2243 switch (fb_format_modifier) {
2244 case DRM_FORMAT_MOD_NONE:
2245 tile_height = 1;
2246 break;
2247 case I915_FORMAT_MOD_X_TILED:
2248 tile_height = IS_GEN2(dev) ? 16 : 8;
2249 break;
2250 case I915_FORMAT_MOD_Y_TILED:
2251 tile_height = 32;
2252 break;
2253 case I915_FORMAT_MOD_Yf_TILED:
2254 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255 switch (pixel_bytes) {
2256 default:
2257 case 1:
2258 tile_height = 64;
2259 break;
2260 case 2:
2261 case 4:
2262 tile_height = 32;
2263 break;
2264 case 8:
2265 tile_height = 16;
2266 break;
2267 case 16:
2268 WARN_ONCE(1,
2269 "128-bit pixels are not supported for display!");
2270 tile_height = 16;
2271 break;
2272 }
2273 break;
2274 default:
2275 MISSING_CASE(fb_format_modifier);
2276 tile_height = 1;
2277 break;
2278 }
2279
2280 return tile_height;
2281}
2282
2283unsigned int
2284intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285 uint32_t pixel_format, uint64_t fb_format_modifier)
2286{
2287 return ALIGN(height, intel_tile_height(dev, pixel_format,
2288 fb_format_modifier));
2289}
2290
2291static int
2292intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2293 const struct drm_plane_state *plane_state)
2294{
2295 *view = i915_ggtt_view_normal;
2296
2297 return 0;
2298}
2299
2300int
2301intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2302 struct drm_framebuffer *fb,
2303 const struct drm_plane_state *plane_state,
2304 struct intel_engine_cs *pipelined)
2305{
2306 struct drm_device *dev = fb->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2309 struct i915_ggtt_view view;
2310 u32 alignment;
2311 int ret;
2312
2313 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2314
2315 switch (fb->modifier[0]) {
2316 case DRM_FORMAT_MOD_NONE:
2317 if (INTEL_INFO(dev)->gen >= 9)
2318 alignment = 256 * 1024;
2319 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2320 alignment = 128 * 1024;
2321 else if (INTEL_INFO(dev)->gen >= 4)
2322 alignment = 4 * 1024;
2323 else
2324 alignment = 64 * 1024;
2325 break;
2326 case I915_FORMAT_MOD_X_TILED:
2327 if (INTEL_INFO(dev)->gen >= 9)
2328 alignment = 256 * 1024;
2329 else {
2330 /* pin() will align the object as required by fence */
2331 alignment = 0;
2332 }
2333 break;
2334 case I915_FORMAT_MOD_Y_TILED:
2335 case I915_FORMAT_MOD_Yf_TILED:
2336 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2337 "Y tiling bo slipped through, driver bug!\n"))
2338 return -EINVAL;
2339 alignment = 1 * 1024 * 1024;
2340 break;
2341 default:
2342 MISSING_CASE(fb->modifier[0]);
2343 return -EINVAL;
2344 }
2345
2346 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2347 if (ret)
2348 return ret;
2349
2350 /* Note that the w/a also requires 64 PTE of padding following the
2351 * bo. We currently fill all unused PTE with the shadow page and so
2352 * we should always have valid PTE following the scanout preventing
2353 * the VT-d warning.
2354 */
2355 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2356 alignment = 256 * 1024;
2357
2358 /*
2359 * Global gtt pte registers are special registers which actually forward
2360 * writes to a chunk of system memory. Which means that there is no risk
2361 * that the register values disappear as soon as we call
2362 * intel_runtime_pm_put(), so it is correct to wrap only the
2363 * pin/unpin/fence and not more.
2364 */
2365 intel_runtime_pm_get(dev_priv);
2366
2367 dev_priv->mm.interruptible = false;
2368 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2369 &view);
2370 if (ret)
2371 goto err_interruptible;
2372
2373 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2374 * fence, whereas 965+ only requires a fence if using
2375 * framebuffer compression. For simplicity, we always install
2376 * a fence as the cost is not that onerous.
2377 */
2378 ret = i915_gem_object_get_fence(obj);
2379 if (ret)
2380 goto err_unpin;
2381
2382 i915_gem_object_pin_fence(obj);
2383
2384 dev_priv->mm.interruptible = true;
2385 intel_runtime_pm_put(dev_priv);
2386 return 0;
2387
2388err_unpin:
2389 i915_gem_object_unpin_from_display_plane(obj, &view);
2390err_interruptible:
2391 dev_priv->mm.interruptible = true;
2392 intel_runtime_pm_put(dev_priv);
2393 return ret;
2394}
2395
2396static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2397 const struct drm_plane_state *plane_state)
2398{
2399 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2400 struct i915_ggtt_view view;
2401 int ret;
2402
2403 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2404
2405 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2406 WARN_ONCE(ret, "Couldn't get view from plane state!");
2407
2408 i915_gem_object_unpin_fence(obj);
2409 i915_gem_object_unpin_from_display_plane(obj, &view);
2410}
2411
2412/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2413 * is assumed to be a power-of-two. */
2414unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2415 unsigned int tiling_mode,
2416 unsigned int cpp,
2417 unsigned int pitch)
2418{
2419 if (tiling_mode != I915_TILING_NONE) {
2420 unsigned int tile_rows, tiles;
2421
2422 tile_rows = *y / 8;
2423 *y %= 8;
2424
2425 tiles = *x / (512/cpp);
2426 *x %= 512/cpp;
2427
2428 return tile_rows * pitch * 8 + tiles * 4096;
2429 } else {
2430 unsigned int offset;
2431
2432 offset = *y * pitch + *x * cpp;
2433 *y = 0;
2434 *x = (offset & 4095) / cpp;
2435 return offset & -4096;
2436 }
2437}
2438
2439static int i9xx_format_to_fourcc(int format)
2440{
2441 switch (format) {
2442 case DISPPLANE_8BPP:
2443 return DRM_FORMAT_C8;
2444 case DISPPLANE_BGRX555:
2445 return DRM_FORMAT_XRGB1555;
2446 case DISPPLANE_BGRX565:
2447 return DRM_FORMAT_RGB565;
2448 default:
2449 case DISPPLANE_BGRX888:
2450 return DRM_FORMAT_XRGB8888;
2451 case DISPPLANE_RGBX888:
2452 return DRM_FORMAT_XBGR8888;
2453 case DISPPLANE_BGRX101010:
2454 return DRM_FORMAT_XRGB2101010;
2455 case DISPPLANE_RGBX101010:
2456 return DRM_FORMAT_XBGR2101010;
2457 }
2458}
2459
2460static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2461{
2462 switch (format) {
2463 case PLANE_CTL_FORMAT_RGB_565:
2464 return DRM_FORMAT_RGB565;
2465 default:
2466 case PLANE_CTL_FORMAT_XRGB_8888:
2467 if (rgb_order) {
2468 if (alpha)
2469 return DRM_FORMAT_ABGR8888;
2470 else
2471 return DRM_FORMAT_XBGR8888;
2472 } else {
2473 if (alpha)
2474 return DRM_FORMAT_ARGB8888;
2475 else
2476 return DRM_FORMAT_XRGB8888;
2477 }
2478 case PLANE_CTL_FORMAT_XRGB_2101010:
2479 if (rgb_order)
2480 return DRM_FORMAT_XBGR2101010;
2481 else
2482 return DRM_FORMAT_XRGB2101010;
2483 }
2484}
2485
2486static bool
2487intel_alloc_plane_obj(struct intel_crtc *crtc,
2488 struct intel_initial_plane_config *plane_config)
2489{
2490 struct drm_device *dev = crtc->base.dev;
2491 struct drm_i915_gem_object *obj = NULL;
2492 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2493 struct drm_framebuffer *fb = &plane_config->fb->base;
2494 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2495 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2496 PAGE_SIZE);
2497
2498 size_aligned -= base_aligned;
2499
2500 if (plane_config->size == 0)
2501 return false;
2502
2503 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2504 base_aligned,
2505 base_aligned,
2506 size_aligned);
2507 if (!obj)
2508 return false;
2509
2510 obj->tiling_mode = plane_config->tiling;
2511 if (obj->tiling_mode == I915_TILING_X)
2512 obj->stride = fb->pitches[0];
2513
2514 mode_cmd.pixel_format = fb->pixel_format;
2515 mode_cmd.width = fb->width;
2516 mode_cmd.height = fb->height;
2517 mode_cmd.pitches[0] = fb->pitches[0];
2518 mode_cmd.modifier[0] = fb->modifier[0];
2519 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2520
2521 mutex_lock(&dev->struct_mutex);
2522
2523 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2524 &mode_cmd, obj)) {
2525 DRM_DEBUG_KMS("intel fb init failed\n");
2526 goto out_unref_obj;
2527 }
2528
2529 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2530 mutex_unlock(&dev->struct_mutex);
2531
2532 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2533 return true;
2534
2535out_unref_obj:
2536 drm_gem_object_unreference(&obj->base);
2537 mutex_unlock(&dev->struct_mutex);
2538 return false;
2539}
2540
2541/* Update plane->state->fb to match plane->fb after driver-internal updates */
2542static void
2543update_state_fb(struct drm_plane *plane)
2544{
2545 if (plane->fb == plane->state->fb)
2546 return;
2547
2548 if (plane->state->fb)
2549 drm_framebuffer_unreference(plane->state->fb);
2550 plane->state->fb = plane->fb;
2551 if (plane->state->fb)
2552 drm_framebuffer_reference(plane->state->fb);
2553}
2554
2555static void
2556intel_find_plane_obj(struct intel_crtc *intel_crtc,
2557 struct intel_initial_plane_config *plane_config)
2558{
2559 struct drm_device *dev = intel_crtc->base.dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct drm_crtc *c;
2562 struct intel_crtc *i;
2563 struct drm_i915_gem_object *obj;
2564
2565 if (!plane_config->fb)
2566 return;
2567
2568 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2569 struct drm_plane *primary = intel_crtc->base.primary;
2570
2571 primary->fb = &plane_config->fb->base;
2572 primary->state->crtc = &intel_crtc->base;
2573 update_state_fb(primary);
2574
2575 return;
2576 }
2577
2578 kfree(plane_config->fb);
2579
2580 /*
2581 * Failed to alloc the obj, check to see if we should share
2582 * an fb with another CRTC instead
2583 */
2584 for_each_crtc(dev, c) {
2585 i = to_intel_crtc(c);
2586
2587 if (c == &intel_crtc->base)
2588 continue;
2589
2590 if (!i->active)
2591 continue;
2592
2593 obj = intel_fb_obj(c->primary->fb);
2594 if (obj == NULL)
2595 continue;
2596
2597 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2598 struct drm_plane *primary = intel_crtc->base.primary;
2599
2600 if (obj->tiling_mode != I915_TILING_NONE)
2601 dev_priv->preserve_bios_swizzle = true;
2602
2603 drm_framebuffer_reference(c->primary->fb);
2604 primary->fb = c->primary->fb;
2605 primary->state->crtc = &intel_crtc->base;
2606 update_state_fb(intel_crtc->base.primary);
2607 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2608 break;
2609 }
2610 }
2611}
2612
2613static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2614 struct drm_framebuffer *fb,
2615 int x, int y)
2616{
2617 struct drm_device *dev = crtc->dev;
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620 struct drm_i915_gem_object *obj;
2621 int plane = intel_crtc->plane;
2622 unsigned long linear_offset;
2623 u32 dspcntr;
2624 u32 reg = DSPCNTR(plane);
2625 int pixel_size;
2626
2627 if (!intel_crtc->primary_enabled) {
2628 I915_WRITE(reg, 0);
2629 if (INTEL_INFO(dev)->gen >= 4)
2630 I915_WRITE(DSPSURF(plane), 0);
2631 else
2632 I915_WRITE(DSPADDR(plane), 0);
2633 POSTING_READ(reg);
2634 return;
2635 }
2636
2637 obj = intel_fb_obj(fb);
2638 if (WARN_ON(obj == NULL))
2639 return;
2640
2641 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2642
2643 dspcntr = DISPPLANE_GAMMA_ENABLE;
2644
2645 dspcntr |= DISPLAY_PLANE_ENABLE;
2646
2647 if (INTEL_INFO(dev)->gen < 4) {
2648 if (intel_crtc->pipe == PIPE_B)
2649 dspcntr |= DISPPLANE_SEL_PIPE_B;
2650
2651 /* pipesrc and dspsize control the size that is scaled from,
2652 * which should always be the user's requested size.
2653 */
2654 I915_WRITE(DSPSIZE(plane),
2655 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2656 (intel_crtc->config->pipe_src_w - 1));
2657 I915_WRITE(DSPPOS(plane), 0);
2658 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2659 I915_WRITE(PRIMSIZE(plane),
2660 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2661 (intel_crtc->config->pipe_src_w - 1));
2662 I915_WRITE(PRIMPOS(plane), 0);
2663 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2664 }
2665
2666 switch (fb->pixel_format) {
2667 case DRM_FORMAT_C8:
2668 dspcntr |= DISPPLANE_8BPP;
2669 break;
2670 case DRM_FORMAT_XRGB1555:
2671 case DRM_FORMAT_ARGB1555:
2672 dspcntr |= DISPPLANE_BGRX555;
2673 break;
2674 case DRM_FORMAT_RGB565:
2675 dspcntr |= DISPPLANE_BGRX565;
2676 break;
2677 case DRM_FORMAT_XRGB8888:
2678 case DRM_FORMAT_ARGB8888:
2679 dspcntr |= DISPPLANE_BGRX888;
2680 break;
2681 case DRM_FORMAT_XBGR8888:
2682 case DRM_FORMAT_ABGR8888:
2683 dspcntr |= DISPPLANE_RGBX888;
2684 break;
2685 case DRM_FORMAT_XRGB2101010:
2686 case DRM_FORMAT_ARGB2101010:
2687 dspcntr |= DISPPLANE_BGRX101010;
2688 break;
2689 case DRM_FORMAT_XBGR2101010:
2690 case DRM_FORMAT_ABGR2101010:
2691 dspcntr |= DISPPLANE_RGBX101010;
2692 break;
2693 default:
2694 BUG();
2695 }
2696
2697 if (INTEL_INFO(dev)->gen >= 4 &&
2698 obj->tiling_mode != I915_TILING_NONE)
2699 dspcntr |= DISPPLANE_TILED;
2700
2701 if (IS_G4X(dev))
2702 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2703
2704 linear_offset = y * fb->pitches[0] + x * pixel_size;
2705
2706 if (INTEL_INFO(dev)->gen >= 4) {
2707 intel_crtc->dspaddr_offset =
2708 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2709 pixel_size,
2710 fb->pitches[0]);
2711 linear_offset -= intel_crtc->dspaddr_offset;
2712 } else {
2713 intel_crtc->dspaddr_offset = linear_offset;
2714 }
2715
2716 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2717 dspcntr |= DISPPLANE_ROTATE_180;
2718
2719 x += (intel_crtc->config->pipe_src_w - 1);
2720 y += (intel_crtc->config->pipe_src_h - 1);
2721
2722 /* Finding the last pixel of the last line of the display
2723 data and adding to linear_offset*/
2724 linear_offset +=
2725 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2726 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2727 }
2728
2729 I915_WRITE(reg, dspcntr);
2730
2731 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2732 if (INTEL_INFO(dev)->gen >= 4) {
2733 I915_WRITE(DSPSURF(plane),
2734 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2735 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2736 I915_WRITE(DSPLINOFF(plane), linear_offset);
2737 } else
2738 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2739 POSTING_READ(reg);
2740}
2741
2742static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2743 struct drm_framebuffer *fb,
2744 int x, int y)
2745{
2746 struct drm_device *dev = crtc->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2749 struct drm_i915_gem_object *obj;
2750 int plane = intel_crtc->plane;
2751 unsigned long linear_offset;
2752 u32 dspcntr;
2753 u32 reg = DSPCNTR(plane);
2754 int pixel_size;
2755
2756 if (!intel_crtc->primary_enabled) {
2757 I915_WRITE(reg, 0);
2758 I915_WRITE(DSPSURF(plane), 0);
2759 POSTING_READ(reg);
2760 return;
2761 }
2762
2763 obj = intel_fb_obj(fb);
2764 if (WARN_ON(obj == NULL))
2765 return;
2766
2767 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2768
2769 dspcntr = DISPPLANE_GAMMA_ENABLE;
2770
2771 dspcntr |= DISPLAY_PLANE_ENABLE;
2772
2773 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2774 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2775
2776 switch (fb->pixel_format) {
2777 case DRM_FORMAT_C8:
2778 dspcntr |= DISPPLANE_8BPP;
2779 break;
2780 case DRM_FORMAT_RGB565:
2781 dspcntr |= DISPPLANE_BGRX565;
2782 break;
2783 case DRM_FORMAT_XRGB8888:
2784 case DRM_FORMAT_ARGB8888:
2785 dspcntr |= DISPPLANE_BGRX888;
2786 break;
2787 case DRM_FORMAT_XBGR8888:
2788 case DRM_FORMAT_ABGR8888:
2789 dspcntr |= DISPPLANE_RGBX888;
2790 break;
2791 case DRM_FORMAT_XRGB2101010:
2792 case DRM_FORMAT_ARGB2101010:
2793 dspcntr |= DISPPLANE_BGRX101010;
2794 break;
2795 case DRM_FORMAT_XBGR2101010:
2796 case DRM_FORMAT_ABGR2101010:
2797 dspcntr |= DISPPLANE_RGBX101010;
2798 break;
2799 default:
2800 BUG();
2801 }
2802
2803 if (obj->tiling_mode != I915_TILING_NONE)
2804 dspcntr |= DISPPLANE_TILED;
2805
2806 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2807 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2808
2809 linear_offset = y * fb->pitches[0] + x * pixel_size;
2810 intel_crtc->dspaddr_offset =
2811 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2812 pixel_size,
2813 fb->pitches[0]);
2814 linear_offset -= intel_crtc->dspaddr_offset;
2815 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2816 dspcntr |= DISPPLANE_ROTATE_180;
2817
2818 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2819 x += (intel_crtc->config->pipe_src_w - 1);
2820 y += (intel_crtc->config->pipe_src_h - 1);
2821
2822 /* Finding the last pixel of the last line of the display
2823 data and adding to linear_offset*/
2824 linear_offset +=
2825 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2826 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2827 }
2828 }
2829
2830 I915_WRITE(reg, dspcntr);
2831
2832 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2833 I915_WRITE(DSPSURF(plane),
2834 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2835 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2836 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2837 } else {
2838 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2839 I915_WRITE(DSPLINOFF(plane), linear_offset);
2840 }
2841 POSTING_READ(reg);
2842}
2843
2844u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2845 uint32_t pixel_format)
2846{
2847 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2848
2849 /*
2850 * The stride is either expressed as a multiple of 64 bytes
2851 * chunks for linear buffers or in number of tiles for tiled
2852 * buffers.
2853 */
2854 switch (fb_modifier) {
2855 case DRM_FORMAT_MOD_NONE:
2856 return 64;
2857 case I915_FORMAT_MOD_X_TILED:
2858 if (INTEL_INFO(dev)->gen == 2)
2859 return 128;
2860 return 512;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 /* No need to check for old gens and Y tiling since this is
2863 * about the display engine and those will be blocked before
2864 * we get here.
2865 */
2866 return 128;
2867 case I915_FORMAT_MOD_Yf_TILED:
2868 if (bits_per_pixel == 8)
2869 return 64;
2870 else
2871 return 128;
2872 default:
2873 MISSING_CASE(fb_modifier);
2874 return 64;
2875 }
2876}
2877
2878static void skylake_update_primary_plane(struct drm_crtc *crtc,
2879 struct drm_framebuffer *fb,
2880 int x, int y)
2881{
2882 struct drm_device *dev = crtc->dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2885 struct drm_i915_gem_object *obj;
2886 int pipe = intel_crtc->pipe;
2887 u32 plane_ctl, stride_div;
2888
2889 if (!intel_crtc->primary_enabled) {
2890 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2891 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2892 POSTING_READ(PLANE_CTL(pipe, 0));
2893 return;
2894 }
2895
2896 plane_ctl = PLANE_CTL_ENABLE |
2897 PLANE_CTL_PIPE_GAMMA_ENABLE |
2898 PLANE_CTL_PIPE_CSC_ENABLE;
2899
2900 switch (fb->pixel_format) {
2901 case DRM_FORMAT_RGB565:
2902 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2903 break;
2904 case DRM_FORMAT_XRGB8888:
2905 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2906 break;
2907 case DRM_FORMAT_ARGB8888:
2908 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2909 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2910 break;
2911 case DRM_FORMAT_XBGR8888:
2912 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2913 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2914 break;
2915 case DRM_FORMAT_ABGR8888:
2916 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2917 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2918 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2919 break;
2920 case DRM_FORMAT_XRGB2101010:
2921 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2922 break;
2923 case DRM_FORMAT_XBGR2101010:
2924 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2925 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2926 break;
2927 default:
2928 BUG();
2929 }
2930
2931 switch (fb->modifier[0]) {
2932 case DRM_FORMAT_MOD_NONE:
2933 break;
2934 case I915_FORMAT_MOD_X_TILED:
2935 plane_ctl |= PLANE_CTL_TILED_X;
2936 break;
2937 case I915_FORMAT_MOD_Y_TILED:
2938 plane_ctl |= PLANE_CTL_TILED_Y;
2939 break;
2940 case I915_FORMAT_MOD_Yf_TILED:
2941 plane_ctl |= PLANE_CTL_TILED_YF;
2942 break;
2943 default:
2944 MISSING_CASE(fb->modifier[0]);
2945 }
2946
2947 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2948 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2949 plane_ctl |= PLANE_CTL_ROTATE_180;
2950
2951 obj = intel_fb_obj(fb);
2952 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2953 fb->pixel_format);
2954
2955 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2956
2957 I915_WRITE(PLANE_POS(pipe, 0), 0);
2958 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2959 I915_WRITE(PLANE_SIZE(pipe, 0),
2960 (intel_crtc->config->pipe_src_h - 1) << 16 |
2961 (intel_crtc->config->pipe_src_w - 1));
2962 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2963 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2964
2965 POSTING_READ(PLANE_SURF(pipe, 0));
2966}
2967
2968/* Assume fb object is pinned & idle & fenced and just update base pointers */
2969static int
2970intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2971 int x, int y, enum mode_set_atomic state)
2972{
2973 struct drm_device *dev = crtc->dev;
2974 struct drm_i915_private *dev_priv = dev->dev_private;
2975
2976 if (dev_priv->display.disable_fbc)
2977 dev_priv->display.disable_fbc(dev);
2978
2979 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2980
2981 return 0;
2982}
2983
2984static void intel_complete_page_flips(struct drm_device *dev)
2985{
2986 struct drm_crtc *crtc;
2987
2988 for_each_crtc(dev, crtc) {
2989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2990 enum plane plane = intel_crtc->plane;
2991
2992 intel_prepare_page_flip(dev, plane);
2993 intel_finish_page_flip_plane(dev, plane);
2994 }
2995}
2996
2997static void intel_update_primary_planes(struct drm_device *dev)
2998{
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct drm_crtc *crtc;
3001
3002 for_each_crtc(dev, crtc) {
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004
3005 drm_modeset_lock(&crtc->mutex, NULL);
3006 /*
3007 * FIXME: Once we have proper support for primary planes (and
3008 * disabling them without disabling the entire crtc) allow again
3009 * a NULL crtc->primary->fb.
3010 */
3011 if (intel_crtc->active && crtc->primary->fb)
3012 dev_priv->display.update_primary_plane(crtc,
3013 crtc->primary->fb,
3014 crtc->x,
3015 crtc->y);
3016 drm_modeset_unlock(&crtc->mutex);
3017 }
3018}
3019
3020void intel_prepare_reset(struct drm_device *dev)
3021{
3022 struct drm_i915_private *dev_priv = to_i915(dev);
3023 struct intel_crtc *crtc;
3024
3025 /* no reset support for gen2 */
3026 if (IS_GEN2(dev))
3027 return;
3028
3029 /* reset doesn't touch the display */
3030 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3031 return;
3032
3033 drm_modeset_lock_all(dev);
3034
3035 /*
3036 * Disabling the crtcs gracefully seems nicer. Also the
3037 * g33 docs say we should at least disable all the planes.
3038 */
3039 for_each_intel_crtc(dev, crtc) {
3040 if (crtc->active)
3041 dev_priv->display.crtc_disable(&crtc->base);
3042 }
3043}
3044
3045void intel_finish_reset(struct drm_device *dev)
3046{
3047 struct drm_i915_private *dev_priv = to_i915(dev);
3048
3049 /*
3050 * Flips in the rings will be nuked by the reset,
3051 * so complete all pending flips so that user space
3052 * will get its events and not get stuck.
3053 */
3054 intel_complete_page_flips(dev);
3055
3056 /* no reset support for gen2 */
3057 if (IS_GEN2(dev))
3058 return;
3059
3060 /* reset doesn't touch the display */
3061 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3062 /*
3063 * Flips in the rings have been nuked by the reset,
3064 * so update the base address of all primary
3065 * planes to the the last fb to make sure we're
3066 * showing the correct fb after a reset.
3067 */
3068 intel_update_primary_planes(dev);
3069 return;
3070 }
3071
3072 /*
3073 * The display has been reset as well,
3074 * so need a full re-initialization.
3075 */
3076 intel_runtime_pm_disable_interrupts(dev_priv);
3077 intel_runtime_pm_enable_interrupts(dev_priv);
3078
3079 intel_modeset_init_hw(dev);
3080
3081 spin_lock_irq(&dev_priv->irq_lock);
3082 if (dev_priv->display.hpd_irq_setup)
3083 dev_priv->display.hpd_irq_setup(dev);
3084 spin_unlock_irq(&dev_priv->irq_lock);
3085
3086 intel_modeset_setup_hw_state(dev, true);
3087
3088 intel_hpd_init(dev_priv);
3089
3090 drm_modeset_unlock_all(dev);
3091}
3092
3093static int
3094intel_finish_fb(struct drm_framebuffer *old_fb)
3095{
3096 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3097 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3098 bool was_interruptible = dev_priv->mm.interruptible;
3099 int ret;
3100
3101 /* Big Hammer, we also need to ensure that any pending
3102 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3103 * current scanout is retired before unpinning the old
3104 * framebuffer.
3105 *
3106 * This should only fail upon a hung GPU, in which case we
3107 * can safely continue.
3108 */
3109 dev_priv->mm.interruptible = false;
3110 ret = i915_gem_object_finish_gpu(obj);
3111 dev_priv->mm.interruptible = was_interruptible;
3112
3113 return ret;
3114}
3115
3116static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3117{
3118 struct drm_device *dev = crtc->dev;
3119 struct drm_i915_private *dev_priv = dev->dev_private;
3120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3121 bool pending;
3122
3123 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3124 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3125 return false;
3126
3127 spin_lock_irq(&dev->event_lock);
3128 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3129 spin_unlock_irq(&dev->event_lock);
3130
3131 return pending;
3132}
3133
3134static void intel_update_pipe_size(struct intel_crtc *crtc)
3135{
3136 struct drm_device *dev = crtc->base.dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 const struct drm_display_mode *adjusted_mode;
3139
3140 if (!i915.fastboot)
3141 return;
3142
3143 /*
3144 * Update pipe size and adjust fitter if needed: the reason for this is
3145 * that in compute_mode_changes we check the native mode (not the pfit
3146 * mode) to see if we can flip rather than do a full mode set. In the
3147 * fastboot case, we'll flip, but if we don't update the pipesrc and
3148 * pfit state, we'll end up with a big fb scanned out into the wrong
3149 * sized surface.
3150 *
3151 * To fix this properly, we need to hoist the checks up into
3152 * compute_mode_changes (or above), check the actual pfit state and
3153 * whether the platform allows pfit disable with pipe active, and only
3154 * then update the pipesrc and pfit state, even on the flip path.
3155 */
3156
3157 adjusted_mode = &crtc->config->base.adjusted_mode;
3158
3159 I915_WRITE(PIPESRC(crtc->pipe),
3160 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3161 (adjusted_mode->crtc_vdisplay - 1));
3162 if (!crtc->config->pch_pfit.enabled &&
3163 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3164 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3165 I915_WRITE(PF_CTL(crtc->pipe), 0);
3166 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3167 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3168 }
3169 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3170 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3171}
3172
3173static void intel_fdi_normal_train(struct drm_crtc *crtc)
3174{
3175 struct drm_device *dev = crtc->dev;
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3178 int pipe = intel_crtc->pipe;
3179 u32 reg, temp;
3180
3181 /* enable normal train */
3182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 if (IS_IVYBRIDGE(dev)) {
3185 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3186 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3187 } else {
3188 temp &= ~FDI_LINK_TRAIN_NONE;
3189 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3190 }
3191 I915_WRITE(reg, temp);
3192
3193 reg = FDI_RX_CTL(pipe);
3194 temp = I915_READ(reg);
3195 if (HAS_PCH_CPT(dev)) {
3196 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3197 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3198 } else {
3199 temp &= ~FDI_LINK_TRAIN_NONE;
3200 temp |= FDI_LINK_TRAIN_NONE;
3201 }
3202 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3203
3204 /* wait one idle pattern time */
3205 POSTING_READ(reg);
3206 udelay(1000);
3207
3208 /* IVB wants error correction enabled */
3209 if (IS_IVYBRIDGE(dev))
3210 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3211 FDI_FE_ERRC_ENABLE);
3212}
3213
3214/* The FDI link training functions for ILK/Ibexpeak. */
3215static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3220 int pipe = intel_crtc->pipe;
3221 u32 reg, temp, tries;
3222
3223 /* FDI needs bits from pipe first */
3224 assert_pipe_enabled(dev_priv, pipe);
3225
3226 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3227 for train result */
3228 reg = FDI_RX_IMR(pipe);
3229 temp = I915_READ(reg);
3230 temp &= ~FDI_RX_SYMBOL_LOCK;
3231 temp &= ~FDI_RX_BIT_LOCK;
3232 I915_WRITE(reg, temp);
3233 I915_READ(reg);
3234 udelay(150);
3235
3236 /* enable CPU FDI TX and PCH FDI RX */
3237 reg = FDI_TX_CTL(pipe);
3238 temp = I915_READ(reg);
3239 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3240 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3241 temp &= ~FDI_LINK_TRAIN_NONE;
3242 temp |= FDI_LINK_TRAIN_PATTERN_1;
3243 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3244
3245 reg = FDI_RX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 temp &= ~FDI_LINK_TRAIN_NONE;
3248 temp |= FDI_LINK_TRAIN_PATTERN_1;
3249 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3250
3251 POSTING_READ(reg);
3252 udelay(150);
3253
3254 /* Ironlake workaround, enable clock pointer after FDI enable*/
3255 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3256 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3257 FDI_RX_PHASE_SYNC_POINTER_EN);
3258
3259 reg = FDI_RX_IIR(pipe);
3260 for (tries = 0; tries < 5; tries++) {
3261 temp = I915_READ(reg);
3262 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3263
3264 if ((temp & FDI_RX_BIT_LOCK)) {
3265 DRM_DEBUG_KMS("FDI train 1 done.\n");
3266 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3267 break;
3268 }
3269 }
3270 if (tries == 5)
3271 DRM_ERROR("FDI train 1 fail!\n");
3272
3273 /* Train 2 */
3274 reg = FDI_TX_CTL(pipe);
3275 temp = I915_READ(reg);
3276 temp &= ~FDI_LINK_TRAIN_NONE;
3277 temp |= FDI_LINK_TRAIN_PATTERN_2;
3278 I915_WRITE(reg, temp);
3279
3280 reg = FDI_RX_CTL(pipe);
3281 temp = I915_READ(reg);
3282 temp &= ~FDI_LINK_TRAIN_NONE;
3283 temp |= FDI_LINK_TRAIN_PATTERN_2;
3284 I915_WRITE(reg, temp);
3285
3286 POSTING_READ(reg);
3287 udelay(150);
3288
3289 reg = FDI_RX_IIR(pipe);
3290 for (tries = 0; tries < 5; tries++) {
3291 temp = I915_READ(reg);
3292 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3293
3294 if (temp & FDI_RX_SYMBOL_LOCK) {
3295 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3296 DRM_DEBUG_KMS("FDI train 2 done.\n");
3297 break;
3298 }
3299 }
3300 if (tries == 5)
3301 DRM_ERROR("FDI train 2 fail!\n");
3302
3303 DRM_DEBUG_KMS("FDI train done\n");
3304
3305}
3306
3307static const int snb_b_fdi_train_param[] = {
3308 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3309 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3310 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3311 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3312};
3313
3314/* The FDI link training functions for SNB/Cougarpoint. */
3315static void gen6_fdi_link_train(struct drm_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe;
3321 u32 reg, temp, i, retry;
3322
3323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3324 for train result */
3325 reg = FDI_RX_IMR(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~FDI_RX_SYMBOL_LOCK;
3328 temp &= ~FDI_RX_BIT_LOCK;
3329 I915_WRITE(reg, temp);
3330
3331 POSTING_READ(reg);
3332 udelay(150);
3333
3334 /* enable CPU FDI TX and PCH FDI RX */
3335 reg = FDI_TX_CTL(pipe);
3336 temp = I915_READ(reg);
3337 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3338 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3339 temp &= ~FDI_LINK_TRAIN_NONE;
3340 temp |= FDI_LINK_TRAIN_PATTERN_1;
3341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3342 /* SNB-B */
3343 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3344 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3345
3346 I915_WRITE(FDI_RX_MISC(pipe),
3347 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3348
3349 reg = FDI_RX_CTL(pipe);
3350 temp = I915_READ(reg);
3351 if (HAS_PCH_CPT(dev)) {
3352 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3353 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3354 } else {
3355 temp &= ~FDI_LINK_TRAIN_NONE;
3356 temp |= FDI_LINK_TRAIN_PATTERN_1;
3357 }
3358 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3359
3360 POSTING_READ(reg);
3361 udelay(150);
3362
3363 for (i = 0; i < 4; i++) {
3364 reg = FDI_TX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3367 temp |= snb_b_fdi_train_param[i];
3368 I915_WRITE(reg, temp);
3369
3370 POSTING_READ(reg);
3371 udelay(500);
3372
3373 for (retry = 0; retry < 5; retry++) {
3374 reg = FDI_RX_IIR(pipe);
3375 temp = I915_READ(reg);
3376 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3377 if (temp & FDI_RX_BIT_LOCK) {
3378 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3379 DRM_DEBUG_KMS("FDI train 1 done.\n");
3380 break;
3381 }
3382 udelay(50);
3383 }
3384 if (retry < 5)
3385 break;
3386 }
3387 if (i == 4)
3388 DRM_ERROR("FDI train 1 fail!\n");
3389
3390 /* Train 2 */
3391 reg = FDI_TX_CTL(pipe);
3392 temp = I915_READ(reg);
3393 temp &= ~FDI_LINK_TRAIN_NONE;
3394 temp |= FDI_LINK_TRAIN_PATTERN_2;
3395 if (IS_GEN6(dev)) {
3396 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3397 /* SNB-B */
3398 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3399 }
3400 I915_WRITE(reg, temp);
3401
3402 reg = FDI_RX_CTL(pipe);
3403 temp = I915_READ(reg);
3404 if (HAS_PCH_CPT(dev)) {
3405 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3406 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3407 } else {
3408 temp &= ~FDI_LINK_TRAIN_NONE;
3409 temp |= FDI_LINK_TRAIN_PATTERN_2;
3410 }
3411 I915_WRITE(reg, temp);
3412
3413 POSTING_READ(reg);
3414 udelay(150);
3415
3416 for (i = 0; i < 4; i++) {
3417 reg = FDI_TX_CTL(pipe);
3418 temp = I915_READ(reg);
3419 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3420 temp |= snb_b_fdi_train_param[i];
3421 I915_WRITE(reg, temp);
3422
3423 POSTING_READ(reg);
3424 udelay(500);
3425
3426 for (retry = 0; retry < 5; retry++) {
3427 reg = FDI_RX_IIR(pipe);
3428 temp = I915_READ(reg);
3429 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3430 if (temp & FDI_RX_SYMBOL_LOCK) {
3431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432 DRM_DEBUG_KMS("FDI train 2 done.\n");
3433 break;
3434 }
3435 udelay(50);
3436 }
3437 if (retry < 5)
3438 break;
3439 }
3440 if (i == 4)
3441 DRM_ERROR("FDI train 2 fail!\n");
3442
3443 DRM_DEBUG_KMS("FDI train done.\n");
3444}
3445
3446/* Manual link training for Ivy Bridge A0 parts */
3447static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3448{
3449 struct drm_device *dev = crtc->dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3452 int pipe = intel_crtc->pipe;
3453 u32 reg, temp, i, j;
3454
3455 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3456 for train result */
3457 reg = FDI_RX_IMR(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_RX_SYMBOL_LOCK;
3460 temp &= ~FDI_RX_BIT_LOCK;
3461 I915_WRITE(reg, temp);
3462
3463 POSTING_READ(reg);
3464 udelay(150);
3465
3466 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3467 I915_READ(FDI_RX_IIR(pipe)));
3468
3469 /* Try each vswing and preemphasis setting twice before moving on */
3470 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3471 /* disable first in case we need to retry */
3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3475 temp &= ~FDI_TX_ENABLE;
3476 I915_WRITE(reg, temp);
3477
3478 reg = FDI_RX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_AUTO;
3481 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3482 temp &= ~FDI_RX_ENABLE;
3483 I915_WRITE(reg, temp);
3484
3485 /* enable CPU FDI TX and PCH FDI RX */
3486 reg = FDI_TX_CTL(pipe);
3487 temp = I915_READ(reg);
3488 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3489 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3490 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3492 temp |= snb_b_fdi_train_param[j/2];
3493 temp |= FDI_COMPOSITE_SYNC;
3494 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3495
3496 I915_WRITE(FDI_RX_MISC(pipe),
3497 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3498
3499 reg = FDI_RX_CTL(pipe);
3500 temp = I915_READ(reg);
3501 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3502 temp |= FDI_COMPOSITE_SYNC;
3503 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3504
3505 POSTING_READ(reg);
3506 udelay(1); /* should be 0.5us */
3507
3508 for (i = 0; i < 4; i++) {
3509 reg = FDI_RX_IIR(pipe);
3510 temp = I915_READ(reg);
3511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3512
3513 if (temp & FDI_RX_BIT_LOCK ||
3514 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3515 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3516 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3517 i);
3518 break;
3519 }
3520 udelay(1); /* should be 0.5us */
3521 }
3522 if (i == 4) {
3523 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3524 continue;
3525 }
3526
3527 /* Train 2 */
3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3531 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3532 I915_WRITE(reg, temp);
3533
3534 reg = FDI_RX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3537 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3538 I915_WRITE(reg, temp);
3539
3540 POSTING_READ(reg);
3541 udelay(2); /* should be 1.5us */
3542
3543 for (i = 0; i < 4; i++) {
3544 reg = FDI_RX_IIR(pipe);
3545 temp = I915_READ(reg);
3546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3547
3548 if (temp & FDI_RX_SYMBOL_LOCK ||
3549 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3550 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3551 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3552 i);
3553 goto train_done;
3554 }
3555 udelay(2); /* should be 1.5us */
3556 }
3557 if (i == 4)
3558 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3559 }
3560
3561train_done:
3562 DRM_DEBUG_KMS("FDI train done.\n");
3563}
3564
3565static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3566{
3567 struct drm_device *dev = intel_crtc->base.dev;
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 int pipe = intel_crtc->pipe;
3570 u32 reg, temp;
3571
3572
3573 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3574 reg = FDI_RX_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3577 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3578 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3579 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3580
3581 POSTING_READ(reg);
3582 udelay(200);
3583
3584 /* Switch from Rawclk to PCDclk */
3585 temp = I915_READ(reg);
3586 I915_WRITE(reg, temp | FDI_PCDCLK);
3587
3588 POSTING_READ(reg);
3589 udelay(200);
3590
3591 /* Enable CPU FDI TX PLL, always on for Ironlake */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3595 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3596
3597 POSTING_READ(reg);
3598 udelay(100);
3599 }
3600}
3601
3602static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3603{
3604 struct drm_device *dev = intel_crtc->base.dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 int pipe = intel_crtc->pipe;
3607 u32 reg, temp;
3608
3609 /* Switch from PCDclk to Rawclk */
3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
3612 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3613
3614 /* Disable CPU FDI TX PLL */
3615 reg = FDI_TX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3618
3619 POSTING_READ(reg);
3620 udelay(100);
3621
3622 reg = FDI_RX_CTL(pipe);
3623 temp = I915_READ(reg);
3624 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3625
3626 /* Wait for the clocks to turn off. */
3627 POSTING_READ(reg);
3628 udelay(100);
3629}
3630
3631static void ironlake_fdi_disable(struct drm_crtc *crtc)
3632{
3633 struct drm_device *dev = crtc->dev;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3636 int pipe = intel_crtc->pipe;
3637 u32 reg, temp;
3638
3639 /* disable CPU FDI tx and PCH FDI rx */
3640 reg = FDI_TX_CTL(pipe);
3641 temp = I915_READ(reg);
3642 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3643 POSTING_READ(reg);
3644
3645 reg = FDI_RX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~(0x7 << 16);
3648 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3649 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3650
3651 POSTING_READ(reg);
3652 udelay(100);
3653
3654 /* Ironlake workaround, disable clock pointer after downing FDI */
3655 if (HAS_PCH_IBX(dev))
3656 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3657
3658 /* still set train pattern 1 */
3659 reg = FDI_TX_CTL(pipe);
3660 temp = I915_READ(reg);
3661 temp &= ~FDI_LINK_TRAIN_NONE;
3662 temp |= FDI_LINK_TRAIN_PATTERN_1;
3663 I915_WRITE(reg, temp);
3664
3665 reg = FDI_RX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 if (HAS_PCH_CPT(dev)) {
3668 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3669 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3670 } else {
3671 temp &= ~FDI_LINK_TRAIN_NONE;
3672 temp |= FDI_LINK_TRAIN_PATTERN_1;
3673 }
3674 /* BPC in FDI rx is consistent with that in PIPECONF */
3675 temp &= ~(0x07 << 16);
3676 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3677 I915_WRITE(reg, temp);
3678
3679 POSTING_READ(reg);
3680 udelay(100);
3681}
3682
3683bool intel_has_pending_fb_unpin(struct drm_device *dev)
3684{
3685 struct intel_crtc *crtc;
3686
3687 /* Note that we don't need to be called with mode_config.lock here
3688 * as our list of CRTC objects is static for the lifetime of the
3689 * device and so cannot disappear as we iterate. Similarly, we can
3690 * happily treat the predicates as racy, atomic checks as userspace
3691 * cannot claim and pin a new fb without at least acquring the
3692 * struct_mutex and so serialising with us.
3693 */
3694 for_each_intel_crtc(dev, crtc) {
3695 if (atomic_read(&crtc->unpin_work_count) == 0)
3696 continue;
3697
3698 if (crtc->unpin_work)
3699 intel_wait_for_vblank(dev, crtc->pipe);
3700
3701 return true;
3702 }
3703
3704 return false;
3705}
3706
3707static void page_flip_completed(struct intel_crtc *intel_crtc)
3708{
3709 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3710 struct intel_unpin_work *work = intel_crtc->unpin_work;
3711
3712 /* ensure that the unpin work is consistent wrt ->pending. */
3713 smp_rmb();
3714 intel_crtc->unpin_work = NULL;
3715
3716 if (work->event)
3717 drm_send_vblank_event(intel_crtc->base.dev,
3718 intel_crtc->pipe,
3719 work->event);
3720
3721 drm_crtc_vblank_put(&intel_crtc->base);
3722
3723 wake_up_all(&dev_priv->pending_flip_queue);
3724 queue_work(dev_priv->wq, &work->work);
3725
3726 trace_i915_flip_complete(intel_crtc->plane,
3727 work->pending_flip_obj);
3728}
3729
3730void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3731{
3732 struct drm_device *dev = crtc->dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734
3735 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3736 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3737 !intel_crtc_has_pending_flip(crtc),
3738 60*HZ) == 0)) {
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740
3741 spin_lock_irq(&dev->event_lock);
3742 if (intel_crtc->unpin_work) {
3743 WARN_ONCE(1, "Removing stuck page flip\n");
3744 page_flip_completed(intel_crtc);
3745 }
3746 spin_unlock_irq(&dev->event_lock);
3747 }
3748
3749 if (crtc->primary->fb) {
3750 mutex_lock(&dev->struct_mutex);
3751 intel_finish_fb(crtc->primary->fb);
3752 mutex_unlock(&dev->struct_mutex);
3753 }
3754}
3755
3756/* Program iCLKIP clock to the desired frequency */
3757static void lpt_program_iclkip(struct drm_crtc *crtc)
3758{
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3762 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3763 u32 temp;
3764
3765 mutex_lock(&dev_priv->dpio_lock);
3766
3767 /* It is necessary to ungate the pixclk gate prior to programming
3768 * the divisors, and gate it back when it is done.
3769 */
3770 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3771
3772 /* Disable SSCCTL */
3773 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3774 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3775 SBI_SSCCTL_DISABLE,
3776 SBI_ICLK);
3777
3778 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3779 if (clock == 20000) {
3780 auxdiv = 1;
3781 divsel = 0x41;
3782 phaseinc = 0x20;
3783 } else {
3784 /* The iCLK virtual clock root frequency is in MHz,
3785 * but the adjusted_mode->crtc_clock in in KHz. To get the
3786 * divisors, it is necessary to divide one by another, so we
3787 * convert the virtual clock precision to KHz here for higher
3788 * precision.
3789 */
3790 u32 iclk_virtual_root_freq = 172800 * 1000;
3791 u32 iclk_pi_range = 64;
3792 u32 desired_divisor, msb_divisor_value, pi_value;
3793
3794 desired_divisor = (iclk_virtual_root_freq / clock);
3795 msb_divisor_value = desired_divisor / iclk_pi_range;
3796 pi_value = desired_divisor % iclk_pi_range;
3797
3798 auxdiv = 0;
3799 divsel = msb_divisor_value - 2;
3800 phaseinc = pi_value;
3801 }
3802
3803 /* This should not happen with any sane values */
3804 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3805 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3806 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3807 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3808
3809 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3810 clock,
3811 auxdiv,
3812 divsel,
3813 phasedir,
3814 phaseinc);
3815
3816 /* Program SSCDIVINTPHASE6 */
3817 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3818 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3819 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3820 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3821 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3822 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3823 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3824 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3825
3826 /* Program SSCAUXDIV */
3827 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3828 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3829 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3830 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3831
3832 /* Enable modulator and associated divider */
3833 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3834 temp &= ~SBI_SSCCTL_DISABLE;
3835 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3836
3837 /* Wait for initialization time */
3838 udelay(24);
3839
3840 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3841
3842 mutex_unlock(&dev_priv->dpio_lock);
3843}
3844
3845static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3846 enum pipe pch_transcoder)
3847{
3848 struct drm_device *dev = crtc->base.dev;
3849 struct drm_i915_private *dev_priv = dev->dev_private;
3850 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3851
3852 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3853 I915_READ(HTOTAL(cpu_transcoder)));
3854 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3855 I915_READ(HBLANK(cpu_transcoder)));
3856 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3857 I915_READ(HSYNC(cpu_transcoder)));
3858
3859 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3860 I915_READ(VTOTAL(cpu_transcoder)));
3861 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3862 I915_READ(VBLANK(cpu_transcoder)));
3863 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3864 I915_READ(VSYNC(cpu_transcoder)));
3865 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3866 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3867}
3868
3869static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3870{
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 uint32_t temp;
3873
3874 temp = I915_READ(SOUTH_CHICKEN1);
3875 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3876 return;
3877
3878 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3879 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3880
3881 temp &= ~FDI_BC_BIFURCATION_SELECT;
3882 if (enable)
3883 temp |= FDI_BC_BIFURCATION_SELECT;
3884
3885 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3886 I915_WRITE(SOUTH_CHICKEN1, temp);
3887 POSTING_READ(SOUTH_CHICKEN1);
3888}
3889
3890static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3891{
3892 struct drm_device *dev = intel_crtc->base.dev;
3893
3894 switch (intel_crtc->pipe) {
3895 case PIPE_A:
3896 break;
3897 case PIPE_B:
3898 if (intel_crtc->config->fdi_lanes > 2)
3899 cpt_set_fdi_bc_bifurcation(dev, false);
3900 else
3901 cpt_set_fdi_bc_bifurcation(dev, true);
3902
3903 break;
3904 case PIPE_C:
3905 cpt_set_fdi_bc_bifurcation(dev, true);
3906
3907 break;
3908 default:
3909 BUG();
3910 }
3911}
3912
3913/*
3914 * Enable PCH resources required for PCH ports:
3915 * - PCH PLLs
3916 * - FDI training & RX/TX
3917 * - update transcoder timings
3918 * - DP transcoding bits
3919 * - transcoder
3920 */
3921static void ironlake_pch_enable(struct drm_crtc *crtc)
3922{
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3926 int pipe = intel_crtc->pipe;
3927 u32 reg, temp;
3928
3929 assert_pch_transcoder_disabled(dev_priv, pipe);
3930
3931 if (IS_IVYBRIDGE(dev))
3932 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3933
3934 /* Write the TU size bits before fdi link training, so that error
3935 * detection works. */
3936 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3937 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3938
3939 /* For PCH output, training FDI link */
3940 dev_priv->display.fdi_link_train(crtc);
3941
3942 /* We need to program the right clock selection before writing the pixel
3943 * mutliplier into the DPLL. */
3944 if (HAS_PCH_CPT(dev)) {
3945 u32 sel;
3946
3947 temp = I915_READ(PCH_DPLL_SEL);
3948 temp |= TRANS_DPLL_ENABLE(pipe);
3949 sel = TRANS_DPLLB_SEL(pipe);
3950 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3951 temp |= sel;
3952 else
3953 temp &= ~sel;
3954 I915_WRITE(PCH_DPLL_SEL, temp);
3955 }
3956
3957 /* XXX: pch pll's can be enabled any time before we enable the PCH
3958 * transcoder, and we actually should do this to not upset any PCH
3959 * transcoder that already use the clock when we share it.
3960 *
3961 * Note that enable_shared_dpll tries to do the right thing, but
3962 * get_shared_dpll unconditionally resets the pll - we need that to have
3963 * the right LVDS enable sequence. */
3964 intel_enable_shared_dpll(intel_crtc);
3965
3966 /* set transcoder timing, panel must allow it */
3967 assert_panel_unlocked(dev_priv, pipe);
3968 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3969
3970 intel_fdi_normal_train(crtc);
3971
3972 /* For PCH DP, enable TRANS_DP_CTL */
3973 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3974 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3975 reg = TRANS_DP_CTL(pipe);
3976 temp = I915_READ(reg);
3977 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3978 TRANS_DP_SYNC_MASK |
3979 TRANS_DP_BPC_MASK);
3980 temp |= (TRANS_DP_OUTPUT_ENABLE |
3981 TRANS_DP_ENH_FRAMING);
3982 temp |= bpc << 9; /* same format but at 11:9 */
3983
3984 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3985 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3986 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3987 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3988
3989 switch (intel_trans_dp_port_sel(crtc)) {
3990 case PCH_DP_B:
3991 temp |= TRANS_DP_PORT_SEL_B;
3992 break;
3993 case PCH_DP_C:
3994 temp |= TRANS_DP_PORT_SEL_C;
3995 break;
3996 case PCH_DP_D:
3997 temp |= TRANS_DP_PORT_SEL_D;
3998 break;
3999 default:
4000 BUG();
4001 }
4002
4003 I915_WRITE(reg, temp);
4004 }
4005
4006 ironlake_enable_pch_transcoder(dev_priv, pipe);
4007}
4008
4009static void lpt_pch_enable(struct drm_crtc *crtc)
4010{
4011 struct drm_device *dev = crtc->dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4014 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4015
4016 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4017
4018 lpt_program_iclkip(crtc);
4019
4020 /* Set transcoder timing. */
4021 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4022
4023 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4024}
4025
4026void intel_put_shared_dpll(struct intel_crtc *crtc)
4027{
4028 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4029
4030 if (pll == NULL)
4031 return;
4032
4033 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4034 WARN(1, "bad %s crtc mask\n", pll->name);
4035 return;
4036 }
4037
4038 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4039 if (pll->config.crtc_mask == 0) {
4040 WARN_ON(pll->on);
4041 WARN_ON(pll->active);
4042 }
4043
4044 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4045}
4046
4047struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4048 struct intel_crtc_state *crtc_state)
4049{
4050 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4051 struct intel_shared_dpll *pll;
4052 enum intel_dpll_id i;
4053
4054 if (HAS_PCH_IBX(dev_priv->dev)) {
4055 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4056 i = (enum intel_dpll_id) crtc->pipe;
4057 pll = &dev_priv->shared_dplls[i];
4058
4059 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4060 crtc->base.base.id, pll->name);
4061
4062 WARN_ON(pll->new_config->crtc_mask);
4063
4064 goto found;
4065 }
4066
4067 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4068 pll = &dev_priv->shared_dplls[i];
4069
4070 /* Only want to check enabled timings first */
4071 if (pll->new_config->crtc_mask == 0)
4072 continue;
4073
4074 if (memcmp(&crtc_state->dpll_hw_state,
4075 &pll->new_config->hw_state,
4076 sizeof(pll->new_config->hw_state)) == 0) {
4077 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4078 crtc->base.base.id, pll->name,
4079 pll->new_config->crtc_mask,
4080 pll->active);
4081 goto found;
4082 }
4083 }
4084
4085 /* Ok no matching timings, maybe there's a free one? */
4086 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4087 pll = &dev_priv->shared_dplls[i];
4088 if (pll->new_config->crtc_mask == 0) {
4089 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4090 crtc->base.base.id, pll->name);
4091 goto found;
4092 }
4093 }
4094
4095 return NULL;
4096
4097found:
4098 if (pll->new_config->crtc_mask == 0)
4099 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4100
4101 crtc_state->shared_dpll = i;
4102 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4103 pipe_name(crtc->pipe));
4104
4105 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4106
4107 return pll;
4108}
4109
4110/**
4111 * intel_shared_dpll_start_config - start a new PLL staged config
4112 * @dev_priv: DRM device
4113 * @clear_pipes: mask of pipes that will have their PLLs freed
4114 *
4115 * Starts a new PLL staged config, copying the current config but
4116 * releasing the references of pipes specified in clear_pipes.
4117 */
4118static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4119 unsigned clear_pipes)
4120{
4121 struct intel_shared_dpll *pll;
4122 enum intel_dpll_id i;
4123
4124 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4125 pll = &dev_priv->shared_dplls[i];
4126
4127 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4128 GFP_KERNEL);
4129 if (!pll->new_config)
4130 goto cleanup;
4131
4132 pll->new_config->crtc_mask &= ~clear_pipes;
4133 }
4134
4135 return 0;
4136
4137cleanup:
4138 while (--i >= 0) {
4139 pll = &dev_priv->shared_dplls[i];
4140 kfree(pll->new_config);
4141 pll->new_config = NULL;
4142 }
4143
4144 return -ENOMEM;
4145}
4146
4147static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4148{
4149 struct intel_shared_dpll *pll;
4150 enum intel_dpll_id i;
4151
4152 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4153 pll = &dev_priv->shared_dplls[i];
4154
4155 WARN_ON(pll->new_config == &pll->config);
4156
4157 pll->config = *pll->new_config;
4158 kfree(pll->new_config);
4159 pll->new_config = NULL;
4160 }
4161}
4162
4163static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4164{
4165 struct intel_shared_dpll *pll;
4166 enum intel_dpll_id i;
4167
4168 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4169 pll = &dev_priv->shared_dplls[i];
4170
4171 WARN_ON(pll->new_config == &pll->config);
4172
4173 kfree(pll->new_config);
4174 pll->new_config = NULL;
4175 }
4176}
4177
4178static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4179{
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 int dslreg = PIPEDSL(pipe);
4182 u32 temp;
4183
4184 temp = I915_READ(dslreg);
4185 udelay(500);
4186 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4187 if (wait_for(I915_READ(dslreg) != temp, 5))
4188 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4189 }
4190}
4191
4192static void skylake_pfit_enable(struct intel_crtc *crtc)
4193{
4194 struct drm_device *dev = crtc->base.dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 int pipe = crtc->pipe;
4197
4198 if (crtc->config->pch_pfit.enabled) {
4199 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4200 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4201 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4202 }
4203}
4204
4205static void ironlake_pfit_enable(struct intel_crtc *crtc)
4206{
4207 struct drm_device *dev = crtc->base.dev;
4208 struct drm_i915_private *dev_priv = dev->dev_private;
4209 int pipe = crtc->pipe;
4210
4211 if (crtc->config->pch_pfit.enabled) {
4212 /* Force use of hard-coded filter coefficients
4213 * as some pre-programmed values are broken,
4214 * e.g. x201.
4215 */
4216 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4217 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4218 PF_PIPE_SEL_IVB(pipe));
4219 else
4220 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4221 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4222 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4223 }
4224}
4225
4226static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4227{
4228 struct drm_device *dev = crtc->dev;
4229 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4230 struct drm_plane *plane;
4231 struct intel_plane *intel_plane;
4232
4233 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4234 intel_plane = to_intel_plane(plane);
4235 if (intel_plane->pipe == pipe)
4236 intel_plane_restore(&intel_plane->base);
4237 }
4238}
4239
4240/*
4241 * Disable a plane internally without actually modifying the plane's state.
4242 * This will allow us to easily restore the plane later by just reprogramming
4243 * its state.
4244 */
4245static void disable_plane_internal(struct drm_plane *plane)
4246{
4247 struct intel_plane *intel_plane = to_intel_plane(plane);
4248 struct drm_plane_state *state =
4249 plane->funcs->atomic_duplicate_state(plane);
4250 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4251
4252 intel_state->visible = false;
4253 intel_plane->commit_plane(plane, intel_state);
4254
4255 intel_plane_destroy_state(plane, state);
4256}
4257
4258static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4259{
4260 struct drm_device *dev = crtc->dev;
4261 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4262 struct drm_plane *plane;
4263 struct intel_plane *intel_plane;
4264
4265 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4266 intel_plane = to_intel_plane(plane);
4267 if (plane->fb && intel_plane->pipe == pipe)
4268 disable_plane_internal(plane);
4269 }
4270}
4271
4272void hsw_enable_ips(struct intel_crtc *crtc)
4273{
4274 struct drm_device *dev = crtc->base.dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276
4277 if (!crtc->config->ips_enabled)
4278 return;
4279
4280 /* We can only enable IPS after we enable a plane and wait for a vblank */
4281 intel_wait_for_vblank(dev, crtc->pipe);
4282
4283 assert_plane_enabled(dev_priv, crtc->plane);
4284 if (IS_BROADWELL(dev)) {
4285 mutex_lock(&dev_priv->rps.hw_lock);
4286 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4287 mutex_unlock(&dev_priv->rps.hw_lock);
4288 /* Quoting Art Runyan: "its not safe to expect any particular
4289 * value in IPS_CTL bit 31 after enabling IPS through the
4290 * mailbox." Moreover, the mailbox may return a bogus state,
4291 * so we need to just enable it and continue on.
4292 */
4293 } else {
4294 I915_WRITE(IPS_CTL, IPS_ENABLE);
4295 /* The bit only becomes 1 in the next vblank, so this wait here
4296 * is essentially intel_wait_for_vblank. If we don't have this
4297 * and don't wait for vblanks until the end of crtc_enable, then
4298 * the HW state readout code will complain that the expected
4299 * IPS_CTL value is not the one we read. */
4300 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4301 DRM_ERROR("Timed out waiting for IPS enable\n");
4302 }
4303}
4304
4305void hsw_disable_ips(struct intel_crtc *crtc)
4306{
4307 struct drm_device *dev = crtc->base.dev;
4308 struct drm_i915_private *dev_priv = dev->dev_private;
4309
4310 if (!crtc->config->ips_enabled)
4311 return;
4312
4313 assert_plane_enabled(dev_priv, crtc->plane);
4314 if (IS_BROADWELL(dev)) {
4315 mutex_lock(&dev_priv->rps.hw_lock);
4316 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4317 mutex_unlock(&dev_priv->rps.hw_lock);
4318 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4319 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4320 DRM_ERROR("Timed out waiting for IPS disable\n");
4321 } else {
4322 I915_WRITE(IPS_CTL, 0);
4323 POSTING_READ(IPS_CTL);
4324 }
4325
4326 /* We need to wait for a vblank before we can disable the plane. */
4327 intel_wait_for_vblank(dev, crtc->pipe);
4328}
4329
4330/** Loads the palette/gamma unit for the CRTC with the prepared values */
4331static void intel_crtc_load_lut(struct drm_crtc *crtc)
4332{
4333 struct drm_device *dev = crtc->dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4336 enum pipe pipe = intel_crtc->pipe;
4337 int palreg = PALETTE(pipe);
4338 int i;
4339 bool reenable_ips = false;
4340
4341 /* The clocks have to be on to load the palette. */
4342 if (!crtc->state->enable || !intel_crtc->active)
4343 return;
4344
4345 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4346 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4347 assert_dsi_pll_enabled(dev_priv);
4348 else
4349 assert_pll_enabled(dev_priv, pipe);
4350 }
4351
4352 /* use legacy palette for Ironlake */
4353 if (!HAS_GMCH_DISPLAY(dev))
4354 palreg = LGC_PALETTE(pipe);
4355
4356 /* Workaround : Do not read or write the pipe palette/gamma data while
4357 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4358 */
4359 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4360 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4361 GAMMA_MODE_MODE_SPLIT)) {
4362 hsw_disable_ips(intel_crtc);
4363 reenable_ips = true;
4364 }
4365
4366 for (i = 0; i < 256; i++) {
4367 I915_WRITE(palreg + 4 * i,
4368 (intel_crtc->lut_r[i] << 16) |
4369 (intel_crtc->lut_g[i] << 8) |
4370 intel_crtc->lut_b[i]);
4371 }
4372
4373 if (reenable_ips)
4374 hsw_enable_ips(intel_crtc);
4375}
4376
4377static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4378{
4379 if (!enable && intel_crtc->overlay) {
4380 struct drm_device *dev = intel_crtc->base.dev;
4381 struct drm_i915_private *dev_priv = dev->dev_private;
4382
4383 mutex_lock(&dev->struct_mutex);
4384 dev_priv->mm.interruptible = false;
4385 (void) intel_overlay_switch_off(intel_crtc->overlay);
4386 dev_priv->mm.interruptible = true;
4387 mutex_unlock(&dev->struct_mutex);
4388 }
4389
4390 /* Let userspace switch the overlay on again. In most cases userspace
4391 * has to recompute where to put it anyway.
4392 */
4393}
4394
4395static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4396{
4397 struct drm_device *dev = crtc->dev;
4398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4399 int pipe = intel_crtc->pipe;
4400
4401 intel_enable_primary_hw_plane(crtc->primary, crtc);
4402 intel_enable_sprite_planes(crtc);
4403 intel_crtc_update_cursor(crtc, true);
4404 intel_crtc_dpms_overlay(intel_crtc, true);
4405
4406 hsw_enable_ips(intel_crtc);
4407
4408 mutex_lock(&dev->struct_mutex);
4409 intel_fbc_update(dev);
4410 mutex_unlock(&dev->struct_mutex);
4411
4412 /*
4413 * FIXME: Once we grow proper nuclear flip support out of this we need
4414 * to compute the mask of flip planes precisely. For the time being
4415 * consider this a flip from a NULL plane.
4416 */
4417 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4418}
4419
4420static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4421{
4422 struct drm_device *dev = crtc->dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4425 int pipe = intel_crtc->pipe;
4426
4427 intel_crtc_wait_for_pending_flips(crtc);
4428
4429 if (dev_priv->fbc.crtc == intel_crtc)
4430 intel_fbc_disable(dev);
4431
4432 hsw_disable_ips(intel_crtc);
4433
4434 intel_crtc_dpms_overlay(intel_crtc, false);
4435 intel_crtc_update_cursor(crtc, false);
4436 intel_disable_sprite_planes(crtc);
4437 intel_disable_primary_hw_plane(crtc->primary, crtc);
4438
4439 /*
4440 * FIXME: Once we grow proper nuclear flip support out of this we need
4441 * to compute the mask of flip planes precisely. For the time being
4442 * consider this a flip to a NULL plane.
4443 */
4444 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4445}
4446
4447static void ironlake_crtc_enable(struct drm_crtc *crtc)
4448{
4449 struct drm_device *dev = crtc->dev;
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4452 struct intel_encoder *encoder;
4453 int pipe = intel_crtc->pipe;
4454
4455 WARN_ON(!crtc->state->enable);
4456
4457 if (intel_crtc->active)
4458 return;
4459
4460 if (intel_crtc->config->has_pch_encoder)
4461 intel_prepare_shared_dpll(intel_crtc);
4462
4463 if (intel_crtc->config->has_dp_encoder)
4464 intel_dp_set_m_n(intel_crtc, M1_N1);
4465
4466 intel_set_pipe_timings(intel_crtc);
4467
4468 if (intel_crtc->config->has_pch_encoder) {
4469 intel_cpu_transcoder_set_m_n(intel_crtc,
4470 &intel_crtc->config->fdi_m_n, NULL);
4471 }
4472
4473 ironlake_set_pipeconf(crtc);
4474
4475 intel_crtc->active = true;
4476
4477 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4478 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4479
4480 for_each_encoder_on_crtc(dev, crtc, encoder)
4481 if (encoder->pre_enable)
4482 encoder->pre_enable(encoder);
4483
4484 if (intel_crtc->config->has_pch_encoder) {
4485 /* Note: FDI PLL enabling _must_ be done before we enable the
4486 * cpu pipes, hence this is separate from all the other fdi/pch
4487 * enabling. */
4488 ironlake_fdi_pll_enable(intel_crtc);
4489 } else {
4490 assert_fdi_tx_disabled(dev_priv, pipe);
4491 assert_fdi_rx_disabled(dev_priv, pipe);
4492 }
4493
4494 ironlake_pfit_enable(intel_crtc);
4495
4496 /*
4497 * On ILK+ LUT must be loaded before the pipe is running but with
4498 * clocks enabled
4499 */
4500 intel_crtc_load_lut(crtc);
4501
4502 intel_update_watermarks(crtc);
4503 intel_enable_pipe(intel_crtc);
4504
4505 if (intel_crtc->config->has_pch_encoder)
4506 ironlake_pch_enable(crtc);
4507
4508 assert_vblank_disabled(crtc);
4509 drm_crtc_vblank_on(crtc);
4510
4511 for_each_encoder_on_crtc(dev, crtc, encoder)
4512 encoder->enable(encoder);
4513
4514 if (HAS_PCH_CPT(dev))
4515 cpt_verify_modeset(dev, intel_crtc->pipe);
4516
4517 intel_crtc_enable_planes(crtc);
4518}
4519
4520/* IPS only exists on ULT machines and is tied to pipe A. */
4521static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4522{
4523 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4524}
4525
4526/*
4527 * This implements the workaround described in the "notes" section of the mode
4528 * set sequence documentation. When going from no pipes or single pipe to
4529 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4530 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4531 */
4532static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4533{
4534 struct drm_device *dev = crtc->base.dev;
4535 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4536
4537 /* We want to get the other_active_crtc only if there's only 1 other
4538 * active crtc. */
4539 for_each_intel_crtc(dev, crtc_it) {
4540 if (!crtc_it->active || crtc_it == crtc)
4541 continue;
4542
4543 if (other_active_crtc)
4544 return;
4545
4546 other_active_crtc = crtc_it;
4547 }
4548 if (!other_active_crtc)
4549 return;
4550
4551 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4552 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4553}
4554
4555static void haswell_crtc_enable(struct drm_crtc *crtc)
4556{
4557 struct drm_device *dev = crtc->dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4560 struct intel_encoder *encoder;
4561 int pipe = intel_crtc->pipe;
4562
4563 WARN_ON(!crtc->state->enable);
4564
4565 if (intel_crtc->active)
4566 return;
4567
4568 if (intel_crtc_to_shared_dpll(intel_crtc))
4569 intel_enable_shared_dpll(intel_crtc);
4570
4571 if (intel_crtc->config->has_dp_encoder)
4572 intel_dp_set_m_n(intel_crtc, M1_N1);
4573
4574 intel_set_pipe_timings(intel_crtc);
4575
4576 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4577 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4578 intel_crtc->config->pixel_multiplier - 1);
4579 }
4580
4581 if (intel_crtc->config->has_pch_encoder) {
4582 intel_cpu_transcoder_set_m_n(intel_crtc,
4583 &intel_crtc->config->fdi_m_n, NULL);
4584 }
4585
4586 haswell_set_pipeconf(crtc);
4587
4588 intel_set_pipe_csc(crtc);
4589
4590 intel_crtc->active = true;
4591
4592 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4593 for_each_encoder_on_crtc(dev, crtc, encoder)
4594 if (encoder->pre_enable)
4595 encoder->pre_enable(encoder);
4596
4597 if (intel_crtc->config->has_pch_encoder) {
4598 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4599 true);
4600 dev_priv->display.fdi_link_train(crtc);
4601 }
4602
4603 intel_ddi_enable_pipe_clock(intel_crtc);
4604
4605 if (IS_SKYLAKE(dev))
4606 skylake_pfit_enable(intel_crtc);
4607 else
4608 ironlake_pfit_enable(intel_crtc);
4609
4610 /*
4611 * On ILK+ LUT must be loaded before the pipe is running but with
4612 * clocks enabled
4613 */
4614 intel_crtc_load_lut(crtc);
4615
4616 intel_ddi_set_pipe_settings(crtc);
4617 intel_ddi_enable_transcoder_func(crtc);
4618
4619 intel_update_watermarks(crtc);
4620 intel_enable_pipe(intel_crtc);
4621
4622 if (intel_crtc->config->has_pch_encoder)
4623 lpt_pch_enable(crtc);
4624
4625 if (intel_crtc->config->dp_encoder_is_mst)
4626 intel_ddi_set_vc_payload_alloc(crtc, true);
4627
4628 assert_vblank_disabled(crtc);
4629 drm_crtc_vblank_on(crtc);
4630
4631 for_each_encoder_on_crtc(dev, crtc, encoder) {
4632 encoder->enable(encoder);
4633 intel_opregion_notify_encoder(encoder, true);
4634 }
4635
4636 /* If we change the relative order between pipe/planes enabling, we need
4637 * to change the workaround. */
4638 haswell_mode_set_planes_workaround(intel_crtc);
4639 intel_crtc_enable_planes(crtc);
4640}
4641
4642static void skylake_pfit_disable(struct intel_crtc *crtc)
4643{
4644 struct drm_device *dev = crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 int pipe = crtc->pipe;
4647
4648 /* To avoid upsetting the power well on haswell only disable the pfit if
4649 * it's in use. The hw state code will make sure we get this right. */
4650 if (crtc->config->pch_pfit.enabled) {
4651 I915_WRITE(PS_CTL(pipe), 0);
4652 I915_WRITE(PS_WIN_POS(pipe), 0);
4653 I915_WRITE(PS_WIN_SZ(pipe), 0);
4654 }
4655}
4656
4657static void ironlake_pfit_disable(struct intel_crtc *crtc)
4658{
4659 struct drm_device *dev = crtc->base.dev;
4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661 int pipe = crtc->pipe;
4662
4663 /* To avoid upsetting the power well on haswell only disable the pfit if
4664 * it's in use. The hw state code will make sure we get this right. */
4665 if (crtc->config->pch_pfit.enabled) {
4666 I915_WRITE(PF_CTL(pipe), 0);
4667 I915_WRITE(PF_WIN_POS(pipe), 0);
4668 I915_WRITE(PF_WIN_SZ(pipe), 0);
4669 }
4670}
4671
4672static void ironlake_crtc_disable(struct drm_crtc *crtc)
4673{
4674 struct drm_device *dev = crtc->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4677 struct intel_encoder *encoder;
4678 int pipe = intel_crtc->pipe;
4679 u32 reg, temp;
4680
4681 if (!intel_crtc->active)
4682 return;
4683
4684 intel_crtc_disable_planes(crtc);
4685
4686 for_each_encoder_on_crtc(dev, crtc, encoder)
4687 encoder->disable(encoder);
4688
4689 drm_crtc_vblank_off(crtc);
4690 assert_vblank_disabled(crtc);
4691
4692 if (intel_crtc->config->has_pch_encoder)
4693 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4694
4695 intel_disable_pipe(intel_crtc);
4696
4697 ironlake_pfit_disable(intel_crtc);
4698
4699 for_each_encoder_on_crtc(dev, crtc, encoder)
4700 if (encoder->post_disable)
4701 encoder->post_disable(encoder);
4702
4703 if (intel_crtc->config->has_pch_encoder) {
4704 ironlake_fdi_disable(crtc);
4705
4706 ironlake_disable_pch_transcoder(dev_priv, pipe);
4707
4708 if (HAS_PCH_CPT(dev)) {
4709 /* disable TRANS_DP_CTL */
4710 reg = TRANS_DP_CTL(pipe);
4711 temp = I915_READ(reg);
4712 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4713 TRANS_DP_PORT_SEL_MASK);
4714 temp |= TRANS_DP_PORT_SEL_NONE;
4715 I915_WRITE(reg, temp);
4716
4717 /* disable DPLL_SEL */
4718 temp = I915_READ(PCH_DPLL_SEL);
4719 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4720 I915_WRITE(PCH_DPLL_SEL, temp);
4721 }
4722
4723 /* disable PCH DPLL */
4724 intel_disable_shared_dpll(intel_crtc);
4725
4726 ironlake_fdi_pll_disable(intel_crtc);
4727 }
4728
4729 intel_crtc->active = false;
4730 intel_update_watermarks(crtc);
4731
4732 mutex_lock(&dev->struct_mutex);
4733 intel_fbc_update(dev);
4734 mutex_unlock(&dev->struct_mutex);
4735}
4736
4737static void haswell_crtc_disable(struct drm_crtc *crtc)
4738{
4739 struct drm_device *dev = crtc->dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4742 struct intel_encoder *encoder;
4743 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4744
4745 if (!intel_crtc->active)
4746 return;
4747
4748 intel_crtc_disable_planes(crtc);
4749
4750 for_each_encoder_on_crtc(dev, crtc, encoder) {
4751 intel_opregion_notify_encoder(encoder, false);
4752 encoder->disable(encoder);
4753 }
4754
4755 drm_crtc_vblank_off(crtc);
4756 assert_vblank_disabled(crtc);
4757
4758 if (intel_crtc->config->has_pch_encoder)
4759 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4760 false);
4761 intel_disable_pipe(intel_crtc);
4762
4763 if (intel_crtc->config->dp_encoder_is_mst)
4764 intel_ddi_set_vc_payload_alloc(crtc, false);
4765
4766 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4767
4768 if (IS_SKYLAKE(dev))
4769 skylake_pfit_disable(intel_crtc);
4770 else
4771 ironlake_pfit_disable(intel_crtc);
4772
4773 intel_ddi_disable_pipe_clock(intel_crtc);
4774
4775 if (intel_crtc->config->has_pch_encoder) {
4776 lpt_disable_pch_transcoder(dev_priv);
4777 intel_ddi_fdi_disable(crtc);
4778 }
4779
4780 for_each_encoder_on_crtc(dev, crtc, encoder)
4781 if (encoder->post_disable)
4782 encoder->post_disable(encoder);
4783
4784 intel_crtc->active = false;
4785 intel_update_watermarks(crtc);
4786
4787 mutex_lock(&dev->struct_mutex);
4788 intel_fbc_update(dev);
4789 mutex_unlock(&dev->struct_mutex);
4790
4791 if (intel_crtc_to_shared_dpll(intel_crtc))
4792 intel_disable_shared_dpll(intel_crtc);
4793}
4794
4795static void ironlake_crtc_off(struct drm_crtc *crtc)
4796{
4797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4798 intel_put_shared_dpll(intel_crtc);
4799}
4800
4801
4802static void i9xx_pfit_enable(struct intel_crtc *crtc)
4803{
4804 struct drm_device *dev = crtc->base.dev;
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 struct intel_crtc_state *pipe_config = crtc->config;
4807
4808 if (!pipe_config->gmch_pfit.control)
4809 return;
4810
4811 /*
4812 * The panel fitter should only be adjusted whilst the pipe is disabled,
4813 * according to register description and PRM.
4814 */
4815 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4816 assert_pipe_disabled(dev_priv, crtc->pipe);
4817
4818 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4819 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4820
4821 /* Border color in case we don't scale up to the full screen. Black by
4822 * default, change to something else for debugging. */
4823 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4824}
4825
4826static enum intel_display_power_domain port_to_power_domain(enum port port)
4827{
4828 switch (port) {
4829 case PORT_A:
4830 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4831 case PORT_B:
4832 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4833 case PORT_C:
4834 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4835 case PORT_D:
4836 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4837 default:
4838 WARN_ON_ONCE(1);
4839 return POWER_DOMAIN_PORT_OTHER;
4840 }
4841}
4842
4843#define for_each_power_domain(domain, mask) \
4844 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4845 if ((1 << (domain)) & (mask))
4846
4847enum intel_display_power_domain
4848intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4849{
4850 struct drm_device *dev = intel_encoder->base.dev;
4851 struct intel_digital_port *intel_dig_port;
4852
4853 switch (intel_encoder->type) {
4854 case INTEL_OUTPUT_UNKNOWN:
4855 /* Only DDI platforms should ever use this output type */
4856 WARN_ON_ONCE(!HAS_DDI(dev));
4857 case INTEL_OUTPUT_DISPLAYPORT:
4858 case INTEL_OUTPUT_HDMI:
4859 case INTEL_OUTPUT_EDP:
4860 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4861 return port_to_power_domain(intel_dig_port->port);
4862 case INTEL_OUTPUT_DP_MST:
4863 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4864 return port_to_power_domain(intel_dig_port->port);
4865 case INTEL_OUTPUT_ANALOG:
4866 return POWER_DOMAIN_PORT_CRT;
4867 case INTEL_OUTPUT_DSI:
4868 return POWER_DOMAIN_PORT_DSI;
4869 default:
4870 return POWER_DOMAIN_PORT_OTHER;
4871 }
4872}
4873
4874static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4875{
4876 struct drm_device *dev = crtc->dev;
4877 struct intel_encoder *intel_encoder;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 enum pipe pipe = intel_crtc->pipe;
4880 unsigned long mask;
4881 enum transcoder transcoder;
4882
4883 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4884
4885 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4886 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4887 if (intel_crtc->config->pch_pfit.enabled ||
4888 intel_crtc->config->pch_pfit.force_thru)
4889 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4890
4891 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4892 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4893
4894 return mask;
4895}
4896
4897static void modeset_update_crtc_power_domains(struct drm_device *dev)
4898{
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4901 struct intel_crtc *crtc;
4902
4903 /*
4904 * First get all needed power domains, then put all unneeded, to avoid
4905 * any unnecessary toggling of the power wells.
4906 */
4907 for_each_intel_crtc(dev, crtc) {
4908 enum intel_display_power_domain domain;
4909
4910 if (!crtc->base.state->enable)
4911 continue;
4912
4913 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4914
4915 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4916 intel_display_power_get(dev_priv, domain);
4917 }
4918
4919 if (dev_priv->display.modeset_global_resources)
4920 dev_priv->display.modeset_global_resources(dev);
4921
4922 for_each_intel_crtc(dev, crtc) {
4923 enum intel_display_power_domain domain;
4924
4925 for_each_power_domain(domain, crtc->enabled_power_domains)
4926 intel_display_power_put(dev_priv, domain);
4927
4928 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4929 }
4930
4931 intel_display_set_init_power(dev_priv, false);
4932}
4933
4934/* returns HPLL frequency in kHz */
4935static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4936{
4937 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4938
4939 /* Obtain SKU information */
4940 mutex_lock(&dev_priv->dpio_lock);
4941 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4942 CCK_FUSE_HPLL_FREQ_MASK;
4943 mutex_unlock(&dev_priv->dpio_lock);
4944
4945 return vco_freq[hpll_freq] * 1000;
4946}
4947
4948static void vlv_update_cdclk(struct drm_device *dev)
4949{
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4951
4952 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4953 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4954 dev_priv->vlv_cdclk_freq);
4955
4956 /*
4957 * Program the gmbus_freq based on the cdclk frequency.
4958 * BSpec erroneously claims we should aim for 4MHz, but
4959 * in fact 1MHz is the correct frequency.
4960 */
4961 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4962}
4963
4964/* Adjust CDclk dividers to allow high res or save power if possible */
4965static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4966{
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 u32 val, cmd;
4969
4970 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4971
4972 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4973 cmd = 2;
4974 else if (cdclk == 266667)
4975 cmd = 1;
4976 else
4977 cmd = 0;
4978
4979 mutex_lock(&dev_priv->rps.hw_lock);
4980 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4981 val &= ~DSPFREQGUAR_MASK;
4982 val |= (cmd << DSPFREQGUAR_SHIFT);
4983 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4984 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4985 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4986 50)) {
4987 DRM_ERROR("timed out waiting for CDclk change\n");
4988 }
4989 mutex_unlock(&dev_priv->rps.hw_lock);
4990
4991 if (cdclk == 400000) {
4992 u32 divider;
4993
4994 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4995
4996 mutex_lock(&dev_priv->dpio_lock);
4997 /* adjust cdclk divider */
4998 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4999 val &= ~DISPLAY_FREQUENCY_VALUES;
5000 val |= divider;
5001 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5002
5003 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5004 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5005 50))
5006 DRM_ERROR("timed out waiting for CDclk change\n");
5007 mutex_unlock(&dev_priv->dpio_lock);
5008 }
5009
5010 mutex_lock(&dev_priv->dpio_lock);
5011 /* adjust self-refresh exit latency value */
5012 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5013 val &= ~0x7f;
5014
5015 /*
5016 * For high bandwidth configs, we set a higher latency in the bunit
5017 * so that the core display fetch happens in time to avoid underruns.
5018 */
5019 if (cdclk == 400000)
5020 val |= 4500 / 250; /* 4.5 usec */
5021 else
5022 val |= 3000 / 250; /* 3.0 usec */
5023 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5024 mutex_unlock(&dev_priv->dpio_lock);
5025
5026 vlv_update_cdclk(dev);
5027}
5028
5029static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5030{
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 u32 val, cmd;
5033
5034 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5035
5036 switch (cdclk) {
5037 case 333333:
5038 case 320000:
5039 case 266667:
5040 case 200000:
5041 break;
5042 default:
5043 MISSING_CASE(cdclk);
5044 return;
5045 }
5046
5047 /*
5048 * Specs are full of misinformation, but testing on actual
5049 * hardware has shown that we just need to write the desired
5050 * CCK divider into the Punit register.
5051 */
5052 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5053
5054 mutex_lock(&dev_priv->rps.hw_lock);
5055 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5056 val &= ~DSPFREQGUAR_MASK_CHV;
5057 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5058 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5059 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5060 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5061 50)) {
5062 DRM_ERROR("timed out waiting for CDclk change\n");
5063 }
5064 mutex_unlock(&dev_priv->rps.hw_lock);
5065
5066 vlv_update_cdclk(dev);
5067}
5068
5069static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5070 int max_pixclk)
5071{
5072 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5073 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5074
5075 /*
5076 * Really only a few cases to deal with, as only 4 CDclks are supported:
5077 * 200MHz
5078 * 267MHz
5079 * 320/333MHz (depends on HPLL freq)
5080 * 400MHz (VLV only)
5081 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5082 * of the lower bin and adjust if needed.
5083 *
5084 * We seem to get an unstable or solid color picture at 200MHz.
5085 * Not sure what's wrong. For now use 200MHz only when all pipes
5086 * are off.
5087 */
5088 if (!IS_CHERRYVIEW(dev_priv) &&
5089 max_pixclk > freq_320*limit/100)
5090 return 400000;
5091 else if (max_pixclk > 266667*limit/100)
5092 return freq_320;
5093 else if (max_pixclk > 0)
5094 return 266667;
5095 else
5096 return 200000;
5097}
5098
5099/* compute the max pixel clock for new configuration */
5100static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5101{
5102 struct drm_device *dev = dev_priv->dev;
5103 struct intel_crtc *intel_crtc;
5104 int max_pixclk = 0;
5105
5106 for_each_intel_crtc(dev, intel_crtc) {
5107 if (intel_crtc->new_enabled)
5108 max_pixclk = max(max_pixclk,
5109 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5110 }
5111
5112 return max_pixclk;
5113}
5114
5115static void valleyview_modeset_global_pipes(struct drm_device *dev,
5116 unsigned *prepare_pipes)
5117{
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct intel_crtc *intel_crtc;
5120 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5121
5122 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5123 dev_priv->vlv_cdclk_freq)
5124 return;
5125
5126 /* disable/enable all currently active pipes while we change cdclk */
5127 for_each_intel_crtc(dev, intel_crtc)
5128 if (intel_crtc->base.state->enable)
5129 *prepare_pipes |= (1 << intel_crtc->pipe);
5130}
5131
5132static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5133{
5134 unsigned int credits, default_credits;
5135
5136 if (IS_CHERRYVIEW(dev_priv))
5137 default_credits = PFI_CREDIT(12);
5138 else
5139 default_credits = PFI_CREDIT(8);
5140
5141 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5142 /* CHV suggested value is 31 or 63 */
5143 if (IS_CHERRYVIEW(dev_priv))
5144 credits = PFI_CREDIT_31;
5145 else
5146 credits = PFI_CREDIT(15);
5147 } else {
5148 credits = default_credits;
5149 }
5150
5151 /*
5152 * WA - write default credits before re-programming
5153 * FIXME: should we also set the resend bit here?
5154 */
5155 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5156 default_credits);
5157
5158 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5159 credits | PFI_CREDIT_RESEND);
5160
5161 /*
5162 * FIXME is this guaranteed to clear
5163 * immediately or should we poll for it?
5164 */
5165 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5166}
5167
5168static void valleyview_modeset_global_resources(struct drm_device *dev)
5169{
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5172 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5173
5174 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5175 /*
5176 * FIXME: We can end up here with all power domains off, yet
5177 * with a CDCLK frequency other than the minimum. To account
5178 * for this take the PIPE-A power domain, which covers the HW
5179 * blocks needed for the following programming. This can be
5180 * removed once it's guaranteed that we get here either with
5181 * the minimum CDCLK set, or the required power domains
5182 * enabled.
5183 */
5184 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5185
5186 if (IS_CHERRYVIEW(dev))
5187 cherryview_set_cdclk(dev, req_cdclk);
5188 else
5189 valleyview_set_cdclk(dev, req_cdclk);
5190
5191 vlv_program_pfi_credits(dev_priv);
5192
5193 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5194 }
5195}
5196
5197static void valleyview_crtc_enable(struct drm_crtc *crtc)
5198{
5199 struct drm_device *dev = crtc->dev;
5200 struct drm_i915_private *dev_priv = to_i915(dev);
5201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202 struct intel_encoder *encoder;
5203 int pipe = intel_crtc->pipe;
5204 bool is_dsi;
5205
5206 WARN_ON(!crtc->state->enable);
5207
5208 if (intel_crtc->active)
5209 return;
5210
5211 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5212
5213 if (!is_dsi) {
5214 if (IS_CHERRYVIEW(dev))
5215 chv_prepare_pll(intel_crtc, intel_crtc->config);
5216 else
5217 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5218 }
5219
5220 if (intel_crtc->config->has_dp_encoder)
5221 intel_dp_set_m_n(intel_crtc, M1_N1);
5222
5223 intel_set_pipe_timings(intel_crtc);
5224
5225 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227
5228 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5229 I915_WRITE(CHV_CANVAS(pipe), 0);
5230 }
5231
5232 i9xx_set_pipeconf(intel_crtc);
5233
5234 intel_crtc->active = true;
5235
5236 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5237
5238 for_each_encoder_on_crtc(dev, crtc, encoder)
5239 if (encoder->pre_pll_enable)
5240 encoder->pre_pll_enable(encoder);
5241
5242 if (!is_dsi) {
5243 if (IS_CHERRYVIEW(dev))
5244 chv_enable_pll(intel_crtc, intel_crtc->config);
5245 else
5246 vlv_enable_pll(intel_crtc, intel_crtc->config);
5247 }
5248
5249 for_each_encoder_on_crtc(dev, crtc, encoder)
5250 if (encoder->pre_enable)
5251 encoder->pre_enable(encoder);
5252
5253 i9xx_pfit_enable(intel_crtc);
5254
5255 intel_crtc_load_lut(crtc);
5256
5257 intel_update_watermarks(crtc);
5258 intel_enable_pipe(intel_crtc);
5259
5260 assert_vblank_disabled(crtc);
5261 drm_crtc_vblank_on(crtc);
5262
5263 for_each_encoder_on_crtc(dev, crtc, encoder)
5264 encoder->enable(encoder);
5265
5266 intel_crtc_enable_planes(crtc);
5267
5268 /* Underruns don't raise interrupts, so check manually. */
5269 i9xx_check_fifo_underruns(dev_priv);
5270}
5271
5272static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5273{
5274 struct drm_device *dev = crtc->base.dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276
5277 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5278 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5279}
5280
5281static void i9xx_crtc_enable(struct drm_crtc *crtc)
5282{
5283 struct drm_device *dev = crtc->dev;
5284 struct drm_i915_private *dev_priv = to_i915(dev);
5285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5286 struct intel_encoder *encoder;
5287 int pipe = intel_crtc->pipe;
5288
5289 WARN_ON(!crtc->state->enable);
5290
5291 if (intel_crtc->active)
5292 return;
5293
5294 i9xx_set_pll_dividers(intel_crtc);
5295
5296 if (intel_crtc->config->has_dp_encoder)
5297 intel_dp_set_m_n(intel_crtc, M1_N1);
5298
5299 intel_set_pipe_timings(intel_crtc);
5300
5301 i9xx_set_pipeconf(intel_crtc);
5302
5303 intel_crtc->active = true;
5304
5305 if (!IS_GEN2(dev))
5306 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5307
5308 for_each_encoder_on_crtc(dev, crtc, encoder)
5309 if (encoder->pre_enable)
5310 encoder->pre_enable(encoder);
5311
5312 i9xx_enable_pll(intel_crtc);
5313
5314 i9xx_pfit_enable(intel_crtc);
5315
5316 intel_crtc_load_lut(crtc);
5317
5318 intel_update_watermarks(crtc);
5319 intel_enable_pipe(intel_crtc);
5320
5321 assert_vblank_disabled(crtc);
5322 drm_crtc_vblank_on(crtc);
5323
5324 for_each_encoder_on_crtc(dev, crtc, encoder)
5325 encoder->enable(encoder);
5326
5327 intel_crtc_enable_planes(crtc);
5328
5329 /*
5330 * Gen2 reports pipe underruns whenever all planes are disabled.
5331 * So don't enable underrun reporting before at least some planes
5332 * are enabled.
5333 * FIXME: Need to fix the logic to work when we turn off all planes
5334 * but leave the pipe running.
5335 */
5336 if (IS_GEN2(dev))
5337 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5338
5339 /* Underruns don't raise interrupts, so check manually. */
5340 i9xx_check_fifo_underruns(dev_priv);
5341}
5342
5343static void i9xx_pfit_disable(struct intel_crtc *crtc)
5344{
5345 struct drm_device *dev = crtc->base.dev;
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347
5348 if (!crtc->config->gmch_pfit.control)
5349 return;
5350
5351 assert_pipe_disabled(dev_priv, crtc->pipe);
5352
5353 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5354 I915_READ(PFIT_CONTROL));
5355 I915_WRITE(PFIT_CONTROL, 0);
5356}
5357
5358static void i9xx_crtc_disable(struct drm_crtc *crtc)
5359{
5360 struct drm_device *dev = crtc->dev;
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363 struct intel_encoder *encoder;
5364 int pipe = intel_crtc->pipe;
5365
5366 if (!intel_crtc->active)
5367 return;
5368
5369 /*
5370 * Gen2 reports pipe underruns whenever all planes are disabled.
5371 * So diasble underrun reporting before all the planes get disabled.
5372 * FIXME: Need to fix the logic to work when we turn off all planes
5373 * but leave the pipe running.
5374 */
5375 if (IS_GEN2(dev))
5376 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5377
5378 /*
5379 * Vblank time updates from the shadow to live plane control register
5380 * are blocked if the memory self-refresh mode is active at that
5381 * moment. So to make sure the plane gets truly disabled, disable
5382 * first the self-refresh mode. The self-refresh enable bit in turn
5383 * will be checked/applied by the HW only at the next frame start
5384 * event which is after the vblank start event, so we need to have a
5385 * wait-for-vblank between disabling the plane and the pipe.
5386 */
5387 intel_set_memory_cxsr(dev_priv, false);
5388 intel_crtc_disable_planes(crtc);
5389
5390 /*
5391 * On gen2 planes are double buffered but the pipe isn't, so we must
5392 * wait for planes to fully turn off before disabling the pipe.
5393 * We also need to wait on all gmch platforms because of the
5394 * self-refresh mode constraint explained above.
5395 */
5396 intel_wait_for_vblank(dev, pipe);
5397
5398 for_each_encoder_on_crtc(dev, crtc, encoder)
5399 encoder->disable(encoder);
5400
5401 drm_crtc_vblank_off(crtc);
5402 assert_vblank_disabled(crtc);
5403
5404 intel_disable_pipe(intel_crtc);
5405
5406 i9xx_pfit_disable(intel_crtc);
5407
5408 for_each_encoder_on_crtc(dev, crtc, encoder)
5409 if (encoder->post_disable)
5410 encoder->post_disable(encoder);
5411
5412 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5413 if (IS_CHERRYVIEW(dev))
5414 chv_disable_pll(dev_priv, pipe);
5415 else if (IS_VALLEYVIEW(dev))
5416 vlv_disable_pll(dev_priv, pipe);
5417 else
5418 i9xx_disable_pll(intel_crtc);
5419 }
5420
5421 if (!IS_GEN2(dev))
5422 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5423
5424 intel_crtc->active = false;
5425 intel_update_watermarks(crtc);
5426
5427 mutex_lock(&dev->struct_mutex);
5428 intel_fbc_update(dev);
5429 mutex_unlock(&dev->struct_mutex);
5430}
5431
5432static void i9xx_crtc_off(struct drm_crtc *crtc)
5433{
5434}
5435
5436/* Master function to enable/disable CRTC and corresponding power wells */
5437void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5438{
5439 struct drm_device *dev = crtc->dev;
5440 struct drm_i915_private *dev_priv = dev->dev_private;
5441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5442 enum intel_display_power_domain domain;
5443 unsigned long domains;
5444
5445 if (enable) {
5446 if (!intel_crtc->active) {
5447 domains = get_crtc_power_domains(crtc);
5448 for_each_power_domain(domain, domains)
5449 intel_display_power_get(dev_priv, domain);
5450 intel_crtc->enabled_power_domains = domains;
5451
5452 dev_priv->display.crtc_enable(crtc);
5453 }
5454 } else {
5455 if (intel_crtc->active) {
5456 dev_priv->display.crtc_disable(crtc);
5457
5458 domains = intel_crtc->enabled_power_domains;
5459 for_each_power_domain(domain, domains)
5460 intel_display_power_put(dev_priv, domain);
5461 intel_crtc->enabled_power_domains = 0;
5462 }
5463 }
5464}
5465
5466/**
5467 * Sets the power management mode of the pipe and plane.
5468 */
5469void intel_crtc_update_dpms(struct drm_crtc *crtc)
5470{
5471 struct drm_device *dev = crtc->dev;
5472 struct intel_encoder *intel_encoder;
5473 bool enable = false;
5474
5475 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5476 enable |= intel_encoder->connectors_active;
5477
5478 intel_crtc_control(crtc, enable);
5479}
5480
5481static void intel_crtc_disable(struct drm_crtc *crtc)
5482{
5483 struct drm_device *dev = crtc->dev;
5484 struct drm_connector *connector;
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486
5487 /* crtc should still be enabled when we disable it. */
5488 WARN_ON(!crtc->state->enable);
5489
5490 dev_priv->display.crtc_disable(crtc);
5491 dev_priv->display.off(crtc);
5492
5493 crtc->primary->funcs->disable_plane(crtc->primary);
5494
5495 /* Update computed state. */
5496 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5497 if (!connector->encoder || !connector->encoder->crtc)
5498 continue;
5499
5500 if (connector->encoder->crtc != crtc)
5501 continue;
5502
5503 connector->dpms = DRM_MODE_DPMS_OFF;
5504 to_intel_encoder(connector->encoder)->connectors_active = false;
5505 }
5506}
5507
5508void intel_encoder_destroy(struct drm_encoder *encoder)
5509{
5510 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5511
5512 drm_encoder_cleanup(encoder);
5513 kfree(intel_encoder);
5514}
5515
5516/* Simple dpms helper for encoders with just one connector, no cloning and only
5517 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5518 * state of the entire output pipe. */
5519static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5520{
5521 if (mode == DRM_MODE_DPMS_ON) {
5522 encoder->connectors_active = true;
5523
5524 intel_crtc_update_dpms(encoder->base.crtc);
5525 } else {
5526 encoder->connectors_active = false;
5527
5528 intel_crtc_update_dpms(encoder->base.crtc);
5529 }
5530}
5531
5532/* Cross check the actual hw state with our own modeset state tracking (and it's
5533 * internal consistency). */
5534static void intel_connector_check_state(struct intel_connector *connector)
5535{
5536 if (connector->get_hw_state(connector)) {
5537 struct intel_encoder *encoder = connector->encoder;
5538 struct drm_crtc *crtc;
5539 bool encoder_enabled;
5540 enum pipe pipe;
5541
5542 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5543 connector->base.base.id,
5544 connector->base.name);
5545
5546 /* there is no real hw state for MST connectors */
5547 if (connector->mst_port)
5548 return;
5549
5550 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5551 "wrong connector dpms state\n");
5552 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5553 "active connector not linked to encoder\n");
5554
5555 if (encoder) {
5556 I915_STATE_WARN(!encoder->connectors_active,
5557 "encoder->connectors_active not set\n");
5558
5559 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5560 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5561 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5562 return;
5563
5564 crtc = encoder->base.crtc;
5565
5566 I915_STATE_WARN(!crtc->state->enable,
5567 "crtc not enabled\n");
5568 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5569 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5570 "encoder active on the wrong pipe\n");
5571 }
5572 }
5573}
5574
5575/* Even simpler default implementation, if there's really no special case to
5576 * consider. */
5577void intel_connector_dpms(struct drm_connector *connector, int mode)
5578{
5579 /* All the simple cases only support two dpms states. */
5580 if (mode != DRM_MODE_DPMS_ON)
5581 mode = DRM_MODE_DPMS_OFF;
5582
5583 if (mode == connector->dpms)
5584 return;
5585
5586 connector->dpms = mode;
5587
5588 /* Only need to change hw state when actually enabled */
5589 if (connector->encoder)
5590 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5591
5592 intel_modeset_check_state(connector->dev);
5593}
5594
5595/* Simple connector->get_hw_state implementation for encoders that support only
5596 * one connector and no cloning and hence the encoder state determines the state
5597 * of the connector. */
5598bool intel_connector_get_hw_state(struct intel_connector *connector)
5599{
5600 enum pipe pipe = 0;
5601 struct intel_encoder *encoder = connector->encoder;
5602
5603 return encoder->get_hw_state(encoder, &pipe);
5604}
5605
5606static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5607{
5608 struct intel_crtc *crtc =
5609 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5610
5611 if (crtc->base.state->enable &&
5612 crtc->config->has_pch_encoder)
5613 return crtc->config->fdi_lanes;
5614
5615 return 0;
5616}
5617
5618static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5619 struct intel_crtc_state *pipe_config)
5620{
5621 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5622 pipe_name(pipe), pipe_config->fdi_lanes);
5623 if (pipe_config->fdi_lanes > 4) {
5624 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5625 pipe_name(pipe), pipe_config->fdi_lanes);
5626 return false;
5627 }
5628
5629 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5630 if (pipe_config->fdi_lanes > 2) {
5631 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5632 pipe_config->fdi_lanes);
5633 return false;
5634 } else {
5635 return true;
5636 }
5637 }
5638
5639 if (INTEL_INFO(dev)->num_pipes == 2)
5640 return true;
5641
5642 /* Ivybridge 3 pipe is really complicated */
5643 switch (pipe) {
5644 case PIPE_A:
5645 return true;
5646 case PIPE_B:
5647 if (pipe_config->fdi_lanes > 2 &&
5648 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5649 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5650 pipe_name(pipe), pipe_config->fdi_lanes);
5651 return false;
5652 }
5653 return true;
5654 case PIPE_C:
5655 if (pipe_config->fdi_lanes > 2) {
5656 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5657 pipe_name(pipe), pipe_config->fdi_lanes);
5658 return false;
5659 }
5660 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5661 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5662 return false;
5663 }
5664 return true;
5665 default:
5666 BUG();
5667 }
5668}
5669
5670#define RETRY 1
5671static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5672 struct intel_crtc_state *pipe_config)
5673{
5674 struct drm_device *dev = intel_crtc->base.dev;
5675 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5676 int lane, link_bw, fdi_dotclock;
5677 bool setup_ok, needs_recompute = false;
5678
5679retry:
5680 /* FDI is a binary signal running at ~2.7GHz, encoding
5681 * each output octet as 10 bits. The actual frequency
5682 * is stored as a divider into a 100MHz clock, and the
5683 * mode pixel clock is stored in units of 1KHz.
5684 * Hence the bw of each lane in terms of the mode signal
5685 * is:
5686 */
5687 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5688
5689 fdi_dotclock = adjusted_mode->crtc_clock;
5690
5691 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5692 pipe_config->pipe_bpp);
5693
5694 pipe_config->fdi_lanes = lane;
5695
5696 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5697 link_bw, &pipe_config->fdi_m_n);
5698
5699 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5700 intel_crtc->pipe, pipe_config);
5701 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5702 pipe_config->pipe_bpp -= 2*3;
5703 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5704 pipe_config->pipe_bpp);
5705 needs_recompute = true;
5706 pipe_config->bw_constrained = true;
5707
5708 goto retry;
5709 }
5710
5711 if (needs_recompute)
5712 return RETRY;
5713
5714 return setup_ok ? 0 : -EINVAL;
5715}
5716
5717static void hsw_compute_ips_config(struct intel_crtc *crtc,
5718 struct intel_crtc_state *pipe_config)
5719{
5720 pipe_config->ips_enabled = i915.enable_ips &&
5721 hsw_crtc_supports_ips(crtc) &&
5722 pipe_config->pipe_bpp <= 24;
5723}
5724
5725static int intel_crtc_compute_config(struct intel_crtc *crtc,
5726 struct intel_crtc_state *pipe_config)
5727{
5728 struct drm_device *dev = crtc->base.dev;
5729 struct drm_i915_private *dev_priv = dev->dev_private;
5730 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5731
5732 /* FIXME should check pixel clock limits on all platforms */
5733 if (INTEL_INFO(dev)->gen < 4) {
5734 int clock_limit =
5735 dev_priv->display.get_display_clock_speed(dev);
5736
5737 /*
5738 * Enable pixel doubling when the dot clock
5739 * is > 90% of the (display) core speed.
5740 *
5741 * GDG double wide on either pipe,
5742 * otherwise pipe A only.
5743 */
5744 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5745 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5746 clock_limit *= 2;
5747 pipe_config->double_wide = true;
5748 }
5749
5750 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5751 return -EINVAL;
5752 }
5753
5754 /*
5755 * Pipe horizontal size must be even in:
5756 * - DVO ganged mode
5757 * - LVDS dual channel mode
5758 * - Double wide pipe
5759 */
5760 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5761 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5762 pipe_config->pipe_src_w &= ~1;
5763
5764 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5765 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5766 */
5767 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5768 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5769 return -EINVAL;
5770
5771 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5772 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5773 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5774 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5775 * for lvds. */
5776 pipe_config->pipe_bpp = 8*3;
5777 }
5778
5779 if (HAS_IPS(dev))
5780 hsw_compute_ips_config(crtc, pipe_config);
5781
5782 if (pipe_config->has_pch_encoder)
5783 return ironlake_fdi_compute_config(crtc, pipe_config);
5784
5785 return 0;
5786}
5787
5788static int valleyview_get_display_clock_speed(struct drm_device *dev)
5789{
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 u32 val;
5792 int divider;
5793
5794 if (dev_priv->hpll_freq == 0)
5795 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5796
5797 mutex_lock(&dev_priv->dpio_lock);
5798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5799 mutex_unlock(&dev_priv->dpio_lock);
5800
5801 divider = val & DISPLAY_FREQUENCY_VALUES;
5802
5803 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5804 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5805 "cdclk change in progress\n");
5806
5807 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5808}
5809
5810static int i945_get_display_clock_speed(struct drm_device *dev)
5811{
5812 return 400000;
5813}
5814
5815static int i915_get_display_clock_speed(struct drm_device *dev)
5816{
5817 return 333000;
5818}
5819
5820static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5821{
5822 return 200000;
5823}
5824
5825static int pnv_get_display_clock_speed(struct drm_device *dev)
5826{
5827 u16 gcfgc = 0;
5828
5829 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5830
5831 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5832 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5833 return 267000;
5834 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5835 return 333000;
5836 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5837 return 444000;
5838 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5839 return 200000;
5840 default:
5841 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5842 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5843 return 133000;
5844 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5845 return 167000;
5846 }
5847}
5848
5849static int i915gm_get_display_clock_speed(struct drm_device *dev)
5850{
5851 u16 gcfgc = 0;
5852
5853 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5854
5855 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5856 return 133000;
5857 else {
5858 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5859 case GC_DISPLAY_CLOCK_333_MHZ:
5860 return 333000;
5861 default:
5862 case GC_DISPLAY_CLOCK_190_200_MHZ:
5863 return 190000;
5864 }
5865 }
5866}
5867
5868static int i865_get_display_clock_speed(struct drm_device *dev)
5869{
5870 return 266000;
5871}
5872
5873static int i855_get_display_clock_speed(struct drm_device *dev)
5874{
5875 u16 hpllcc = 0;
5876 /* Assume that the hardware is in the high speed state. This
5877 * should be the default.
5878 */
5879 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5880 case GC_CLOCK_133_200:
5881 case GC_CLOCK_100_200:
5882 return 200000;
5883 case GC_CLOCK_166_250:
5884 return 250000;
5885 case GC_CLOCK_100_133:
5886 return 133000;
5887 }
5888
5889 /* Shouldn't happen */
5890 return 0;
5891}
5892
5893static int i830_get_display_clock_speed(struct drm_device *dev)
5894{
5895 return 133000;
5896}
5897
5898static void
5899intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5900{
5901 while (*num > DATA_LINK_M_N_MASK ||
5902 *den > DATA_LINK_M_N_MASK) {
5903 *num >>= 1;
5904 *den >>= 1;
5905 }
5906}
5907
5908static void compute_m_n(unsigned int m, unsigned int n,
5909 uint32_t *ret_m, uint32_t *ret_n)
5910{
5911 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5912 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5913 intel_reduce_m_n_ratio(ret_m, ret_n);
5914}
5915
5916void
5917intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5918 int pixel_clock, int link_clock,
5919 struct intel_link_m_n *m_n)
5920{
5921 m_n->tu = 64;
5922
5923 compute_m_n(bits_per_pixel * pixel_clock,
5924 link_clock * nlanes * 8,
5925 &m_n->gmch_m, &m_n->gmch_n);
5926
5927 compute_m_n(pixel_clock, link_clock,
5928 &m_n->link_m, &m_n->link_n);
5929}
5930
5931static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5932{
5933 if (i915.panel_use_ssc >= 0)
5934 return i915.panel_use_ssc != 0;
5935 return dev_priv->vbt.lvds_use_ssc
5936 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5937}
5938
5939static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5940{
5941 struct drm_device *dev = crtc->base.dev;
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 int refclk;
5944
5945 if (IS_VALLEYVIEW(dev)) {
5946 refclk = 100000;
5947 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5948 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5949 refclk = dev_priv->vbt.lvds_ssc_freq;
5950 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5951 } else if (!IS_GEN2(dev)) {
5952 refclk = 96000;
5953 } else {
5954 refclk = 48000;
5955 }
5956
5957 return refclk;
5958}
5959
5960static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5961{
5962 return (1 << dpll->n) << 16 | dpll->m2;
5963}
5964
5965static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5966{
5967 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5968}
5969
5970static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5971 struct intel_crtc_state *crtc_state,
5972 intel_clock_t *reduced_clock)
5973{
5974 struct drm_device *dev = crtc->base.dev;
5975 u32 fp, fp2 = 0;
5976
5977 if (IS_PINEVIEW(dev)) {
5978 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5979 if (reduced_clock)
5980 fp2 = pnv_dpll_compute_fp(reduced_clock);
5981 } else {
5982 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5983 if (reduced_clock)
5984 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5985 }
5986
5987 crtc_state->dpll_hw_state.fp0 = fp;
5988
5989 crtc->lowfreq_avail = false;
5990 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5991 reduced_clock && i915.powersave) {
5992 crtc_state->dpll_hw_state.fp1 = fp2;
5993 crtc->lowfreq_avail = true;
5994 } else {
5995 crtc_state->dpll_hw_state.fp1 = fp;
5996 }
5997}
5998
5999static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6000 pipe)
6001{
6002 u32 reg_val;
6003
6004 /*
6005 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6006 * and set it to a reasonable value instead.
6007 */
6008 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6009 reg_val &= 0xffffff00;
6010 reg_val |= 0x00000030;
6011 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6012
6013 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6014 reg_val &= 0x8cffffff;
6015 reg_val = 0x8c000000;
6016 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6017
6018 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6019 reg_val &= 0xffffff00;
6020 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6021
6022 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6023 reg_val &= 0x00ffffff;
6024 reg_val |= 0xb0000000;
6025 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6026}
6027
6028static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6029 struct intel_link_m_n *m_n)
6030{
6031 struct drm_device *dev = crtc->base.dev;
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033 int pipe = crtc->pipe;
6034
6035 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6036 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6037 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6038 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6039}
6040
6041static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6042 struct intel_link_m_n *m_n,
6043 struct intel_link_m_n *m2_n2)
6044{
6045 struct drm_device *dev = crtc->base.dev;
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6047 int pipe = crtc->pipe;
6048 enum transcoder transcoder = crtc->config->cpu_transcoder;
6049
6050 if (INTEL_INFO(dev)->gen >= 5) {
6051 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6052 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6053 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6054 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6055 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6056 * for gen < 8) and if DRRS is supported (to make sure the
6057 * registers are not unnecessarily accessed).
6058 */
6059 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6060 crtc->config->has_drrs) {
6061 I915_WRITE(PIPE_DATA_M2(transcoder),
6062 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6063 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6064 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6065 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6066 }
6067 } else {
6068 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6069 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6070 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6071 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6072 }
6073}
6074
6075void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6076{
6077 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6078
6079 if (m_n == M1_N1) {
6080 dp_m_n = &crtc->config->dp_m_n;
6081 dp_m2_n2 = &crtc->config->dp_m2_n2;
6082 } else if (m_n == M2_N2) {
6083
6084 /*
6085 * M2_N2 registers are not supported. Hence m2_n2 divider value
6086 * needs to be programmed into M1_N1.
6087 */
6088 dp_m_n = &crtc->config->dp_m2_n2;
6089 } else {
6090 DRM_ERROR("Unsupported divider value\n");
6091 return;
6092 }
6093
6094 if (crtc->config->has_pch_encoder)
6095 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6096 else
6097 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6098}
6099
6100static void vlv_update_pll(struct intel_crtc *crtc,
6101 struct intel_crtc_state *pipe_config)
6102{
6103 u32 dpll, dpll_md;
6104
6105 /*
6106 * Enable DPIO clock input. We should never disable the reference
6107 * clock for pipe B, since VGA hotplug / manual detection depends
6108 * on it.
6109 */
6110 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6111 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6112 /* We should never disable this, set it here for state tracking */
6113 if (crtc->pipe == PIPE_B)
6114 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6115 dpll |= DPLL_VCO_ENABLE;
6116 pipe_config->dpll_hw_state.dpll = dpll;
6117
6118 dpll_md = (pipe_config->pixel_multiplier - 1)
6119 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6120 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6121}
6122
6123static void vlv_prepare_pll(struct intel_crtc *crtc,
6124 const struct intel_crtc_state *pipe_config)
6125{
6126 struct drm_device *dev = crtc->base.dev;
6127 struct drm_i915_private *dev_priv = dev->dev_private;
6128 int pipe = crtc->pipe;
6129 u32 mdiv;
6130 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6131 u32 coreclk, reg_val;
6132
6133 mutex_lock(&dev_priv->dpio_lock);
6134
6135 bestn = pipe_config->dpll.n;
6136 bestm1 = pipe_config->dpll.m1;
6137 bestm2 = pipe_config->dpll.m2;
6138 bestp1 = pipe_config->dpll.p1;
6139 bestp2 = pipe_config->dpll.p2;
6140
6141 /* See eDP HDMI DPIO driver vbios notes doc */
6142
6143 /* PLL B needs special handling */
6144 if (pipe == PIPE_B)
6145 vlv_pllb_recal_opamp(dev_priv, pipe);
6146
6147 /* Set up Tx target for periodic Rcomp update */
6148 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6149
6150 /* Disable target IRef on PLL */
6151 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6152 reg_val &= 0x00ffffff;
6153 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6154
6155 /* Disable fast lock */
6156 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6157
6158 /* Set idtafcrecal before PLL is enabled */
6159 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6160 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6161 mdiv |= ((bestn << DPIO_N_SHIFT));
6162 mdiv |= (1 << DPIO_K_SHIFT);
6163
6164 /*
6165 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6166 * but we don't support that).
6167 * Note: don't use the DAC post divider as it seems unstable.
6168 */
6169 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6170 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6171
6172 mdiv |= DPIO_ENABLE_CALIBRATION;
6173 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6174
6175 /* Set HBR and RBR LPF coefficients */
6176 if (pipe_config->port_clock == 162000 ||
6177 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6178 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6179 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6180 0x009f0003);
6181 else
6182 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6183 0x00d0000f);
6184
6185 if (pipe_config->has_dp_encoder) {
6186 /* Use SSC source */
6187 if (pipe == PIPE_A)
6188 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6189 0x0df40000);
6190 else
6191 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6192 0x0df70000);
6193 } else { /* HDMI or VGA */
6194 /* Use bend source */
6195 if (pipe == PIPE_A)
6196 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6197 0x0df70000);
6198 else
6199 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6200 0x0df40000);
6201 }
6202
6203 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6204 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6206 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6207 coreclk |= 0x01000000;
6208 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6209
6210 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6211 mutex_unlock(&dev_priv->dpio_lock);
6212}
6213
6214static void chv_update_pll(struct intel_crtc *crtc,
6215 struct intel_crtc_state *pipe_config)
6216{
6217 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6218 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6219 DPLL_VCO_ENABLE;
6220 if (crtc->pipe != PIPE_A)
6221 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6222
6223 pipe_config->dpll_hw_state.dpll_md =
6224 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6225}
6226
6227static void chv_prepare_pll(struct intel_crtc *crtc,
6228 const struct intel_crtc_state *pipe_config)
6229{
6230 struct drm_device *dev = crtc->base.dev;
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 int pipe = crtc->pipe;
6233 int dpll_reg = DPLL(crtc->pipe);
6234 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6235 u32 loopfilter, tribuf_calcntr;
6236 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6237 u32 dpio_val;
6238 int vco;
6239
6240 bestn = pipe_config->dpll.n;
6241 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6242 bestm1 = pipe_config->dpll.m1;
6243 bestm2 = pipe_config->dpll.m2 >> 22;
6244 bestp1 = pipe_config->dpll.p1;
6245 bestp2 = pipe_config->dpll.p2;
6246 vco = pipe_config->dpll.vco;
6247 dpio_val = 0;
6248 loopfilter = 0;
6249
6250 /*
6251 * Enable Refclk and SSC
6252 */
6253 I915_WRITE(dpll_reg,
6254 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6255
6256 mutex_lock(&dev_priv->dpio_lock);
6257
6258 /* p1 and p2 divider */
6259 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6260 5 << DPIO_CHV_S1_DIV_SHIFT |
6261 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6262 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6263 1 << DPIO_CHV_K_DIV_SHIFT);
6264
6265 /* Feedback post-divider - m2 */
6266 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6267
6268 /* Feedback refclk divider - n and m1 */
6269 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6270 DPIO_CHV_M1_DIV_BY_2 |
6271 1 << DPIO_CHV_N_DIV_SHIFT);
6272
6273 /* M2 fraction division */
6274 if (bestm2_frac)
6275 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6276
6277 /* M2 fraction division enable */
6278 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6279 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6280 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6281 if (bestm2_frac)
6282 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6283 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6284
6285 /* Program digital lock detect threshold */
6286 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6287 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6288 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6289 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6290 if (!bestm2_frac)
6291 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6292 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6293
6294 /* Loop filter */
6295 if (vco == 5400000) {
6296 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6297 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6298 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6299 tribuf_calcntr = 0x9;
6300 } else if (vco <= 6200000) {
6301 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6302 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6303 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6304 tribuf_calcntr = 0x9;
6305 } else if (vco <= 6480000) {
6306 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6307 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6308 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6309 tribuf_calcntr = 0x8;
6310 } else {
6311 /* Not supported. Apply the same limits as in the max case */
6312 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6313 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6314 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6315 tribuf_calcntr = 0;
6316 }
6317 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6318
6319 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6320 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6321 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6322 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6323
6324 /* AFC Recal */
6325 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6326 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6327 DPIO_AFC_RECAL);
6328
6329 mutex_unlock(&dev_priv->dpio_lock);
6330}
6331
6332/**
6333 * vlv_force_pll_on - forcibly enable just the PLL
6334 * @dev_priv: i915 private structure
6335 * @pipe: pipe PLL to enable
6336 * @dpll: PLL configuration
6337 *
6338 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6339 * in cases where we need the PLL enabled even when @pipe is not going to
6340 * be enabled.
6341 */
6342void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6343 const struct dpll *dpll)
6344{
6345 struct intel_crtc *crtc =
6346 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6347 struct intel_crtc_state pipe_config = {
6348 .pixel_multiplier = 1,
6349 .dpll = *dpll,
6350 };
6351
6352 if (IS_CHERRYVIEW(dev)) {
6353 chv_update_pll(crtc, &pipe_config);
6354 chv_prepare_pll(crtc, &pipe_config);
6355 chv_enable_pll(crtc, &pipe_config);
6356 } else {
6357 vlv_update_pll(crtc, &pipe_config);
6358 vlv_prepare_pll(crtc, &pipe_config);
6359 vlv_enable_pll(crtc, &pipe_config);
6360 }
6361}
6362
6363/**
6364 * vlv_force_pll_off - forcibly disable just the PLL
6365 * @dev_priv: i915 private structure
6366 * @pipe: pipe PLL to disable
6367 *
6368 * Disable the PLL for @pipe. To be used in cases where we need
6369 * the PLL enabled even when @pipe is not going to be enabled.
6370 */
6371void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6372{
6373 if (IS_CHERRYVIEW(dev))
6374 chv_disable_pll(to_i915(dev), pipe);
6375 else
6376 vlv_disable_pll(to_i915(dev), pipe);
6377}
6378
6379static void i9xx_update_pll(struct intel_crtc *crtc,
6380 struct intel_crtc_state *crtc_state,
6381 intel_clock_t *reduced_clock,
6382 int num_connectors)
6383{
6384 struct drm_device *dev = crtc->base.dev;
6385 struct drm_i915_private *dev_priv = dev->dev_private;
6386 u32 dpll;
6387 bool is_sdvo;
6388 struct dpll *clock = &crtc_state->dpll;
6389
6390 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6391
6392 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6393 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6394
6395 dpll = DPLL_VGA_MODE_DIS;
6396
6397 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6398 dpll |= DPLLB_MODE_LVDS;
6399 else
6400 dpll |= DPLLB_MODE_DAC_SERIAL;
6401
6402 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6403 dpll |= (crtc_state->pixel_multiplier - 1)
6404 << SDVO_MULTIPLIER_SHIFT_HIRES;
6405 }
6406
6407 if (is_sdvo)
6408 dpll |= DPLL_SDVO_HIGH_SPEED;
6409
6410 if (crtc_state->has_dp_encoder)
6411 dpll |= DPLL_SDVO_HIGH_SPEED;
6412
6413 /* compute bitmask from p1 value */
6414 if (IS_PINEVIEW(dev))
6415 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6416 else {
6417 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6418 if (IS_G4X(dev) && reduced_clock)
6419 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6420 }
6421 switch (clock->p2) {
6422 case 5:
6423 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6424 break;
6425 case 7:
6426 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6427 break;
6428 case 10:
6429 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6430 break;
6431 case 14:
6432 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6433 break;
6434 }
6435 if (INTEL_INFO(dev)->gen >= 4)
6436 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6437
6438 if (crtc_state->sdvo_tv_clock)
6439 dpll |= PLL_REF_INPUT_TVCLKINBC;
6440 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6441 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6442 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6443 else
6444 dpll |= PLL_REF_INPUT_DREFCLK;
6445
6446 dpll |= DPLL_VCO_ENABLE;
6447 crtc_state->dpll_hw_state.dpll = dpll;
6448
6449 if (INTEL_INFO(dev)->gen >= 4) {
6450 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6451 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6452 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6453 }
6454}
6455
6456static void i8xx_update_pll(struct intel_crtc *crtc,
6457 struct intel_crtc_state *crtc_state,
6458 intel_clock_t *reduced_clock,
6459 int num_connectors)
6460{
6461 struct drm_device *dev = crtc->base.dev;
6462 struct drm_i915_private *dev_priv = dev->dev_private;
6463 u32 dpll;
6464 struct dpll *clock = &crtc_state->dpll;
6465
6466 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6467
6468 dpll = DPLL_VGA_MODE_DIS;
6469
6470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6471 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6472 } else {
6473 if (clock->p1 == 2)
6474 dpll |= PLL_P1_DIVIDE_BY_TWO;
6475 else
6476 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6477 if (clock->p2 == 4)
6478 dpll |= PLL_P2_DIVIDE_BY_4;
6479 }
6480
6481 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6482 dpll |= DPLL_DVO_2X_MODE;
6483
6484 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6485 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6486 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6487 else
6488 dpll |= PLL_REF_INPUT_DREFCLK;
6489
6490 dpll |= DPLL_VCO_ENABLE;
6491 crtc_state->dpll_hw_state.dpll = dpll;
6492}
6493
6494static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6495{
6496 struct drm_device *dev = intel_crtc->base.dev;
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498 enum pipe pipe = intel_crtc->pipe;
6499 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6500 struct drm_display_mode *adjusted_mode =
6501 &intel_crtc->config->base.adjusted_mode;
6502 uint32_t crtc_vtotal, crtc_vblank_end;
6503 int vsyncshift = 0;
6504
6505 /* We need to be careful not to changed the adjusted mode, for otherwise
6506 * the hw state checker will get angry at the mismatch. */
6507 crtc_vtotal = adjusted_mode->crtc_vtotal;
6508 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6509
6510 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6511 /* the chip adds 2 halflines automatically */
6512 crtc_vtotal -= 1;
6513 crtc_vblank_end -= 1;
6514
6515 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6516 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6517 else
6518 vsyncshift = adjusted_mode->crtc_hsync_start -
6519 adjusted_mode->crtc_htotal / 2;
6520 if (vsyncshift < 0)
6521 vsyncshift += adjusted_mode->crtc_htotal;
6522 }
6523
6524 if (INTEL_INFO(dev)->gen > 3)
6525 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6526
6527 I915_WRITE(HTOTAL(cpu_transcoder),
6528 (adjusted_mode->crtc_hdisplay - 1) |
6529 ((adjusted_mode->crtc_htotal - 1) << 16));
6530 I915_WRITE(HBLANK(cpu_transcoder),
6531 (adjusted_mode->crtc_hblank_start - 1) |
6532 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6533 I915_WRITE(HSYNC(cpu_transcoder),
6534 (adjusted_mode->crtc_hsync_start - 1) |
6535 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6536
6537 I915_WRITE(VTOTAL(cpu_transcoder),
6538 (adjusted_mode->crtc_vdisplay - 1) |
6539 ((crtc_vtotal - 1) << 16));
6540 I915_WRITE(VBLANK(cpu_transcoder),
6541 (adjusted_mode->crtc_vblank_start - 1) |
6542 ((crtc_vblank_end - 1) << 16));
6543 I915_WRITE(VSYNC(cpu_transcoder),
6544 (adjusted_mode->crtc_vsync_start - 1) |
6545 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6546
6547 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6548 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6549 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6550 * bits. */
6551 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6552 (pipe == PIPE_B || pipe == PIPE_C))
6553 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6554
6555 /* pipesrc controls the size that is scaled from, which should
6556 * always be the user's requested size.
6557 */
6558 I915_WRITE(PIPESRC(pipe),
6559 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6560 (intel_crtc->config->pipe_src_h - 1));
6561}
6562
6563static void intel_get_pipe_timings(struct intel_crtc *crtc,
6564 struct intel_crtc_state *pipe_config)
6565{
6566 struct drm_device *dev = crtc->base.dev;
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6569 uint32_t tmp;
6570
6571 tmp = I915_READ(HTOTAL(cpu_transcoder));
6572 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6573 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6574 tmp = I915_READ(HBLANK(cpu_transcoder));
6575 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6576 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6577 tmp = I915_READ(HSYNC(cpu_transcoder));
6578 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6579 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6580
6581 tmp = I915_READ(VTOTAL(cpu_transcoder));
6582 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6583 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6584 tmp = I915_READ(VBLANK(cpu_transcoder));
6585 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6586 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6587 tmp = I915_READ(VSYNC(cpu_transcoder));
6588 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6589 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6590
6591 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6592 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6593 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6594 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6595 }
6596
6597 tmp = I915_READ(PIPESRC(crtc->pipe));
6598 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6599 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6600
6601 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6602 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6603}
6604
6605void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6606 struct intel_crtc_state *pipe_config)
6607{
6608 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6609 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6610 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6611 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6612
6613 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6614 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6615 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6616 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6617
6618 mode->flags = pipe_config->base.adjusted_mode.flags;
6619
6620 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6621 mode->flags |= pipe_config->base.adjusted_mode.flags;
6622}
6623
6624static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6625{
6626 struct drm_device *dev = intel_crtc->base.dev;
6627 struct drm_i915_private *dev_priv = dev->dev_private;
6628 uint32_t pipeconf;
6629
6630 pipeconf = 0;
6631
6632 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6633 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6634 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6635
6636 if (intel_crtc->config->double_wide)
6637 pipeconf |= PIPECONF_DOUBLE_WIDE;
6638
6639 /* only g4x and later have fancy bpc/dither controls */
6640 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6641 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6642 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6643 pipeconf |= PIPECONF_DITHER_EN |
6644 PIPECONF_DITHER_TYPE_SP;
6645
6646 switch (intel_crtc->config->pipe_bpp) {
6647 case 18:
6648 pipeconf |= PIPECONF_6BPC;
6649 break;
6650 case 24:
6651 pipeconf |= PIPECONF_8BPC;
6652 break;
6653 case 30:
6654 pipeconf |= PIPECONF_10BPC;
6655 break;
6656 default:
6657 /* Case prevented by intel_choose_pipe_bpp_dither. */
6658 BUG();
6659 }
6660 }
6661
6662 if (HAS_PIPE_CXSR(dev)) {
6663 if (intel_crtc->lowfreq_avail) {
6664 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6665 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6666 } else {
6667 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6668 }
6669 }
6670
6671 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6672 if (INTEL_INFO(dev)->gen < 4 ||
6673 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6674 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6675 else
6676 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6677 } else
6678 pipeconf |= PIPECONF_PROGRESSIVE;
6679
6680 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6681 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6682
6683 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6684 POSTING_READ(PIPECONF(intel_crtc->pipe));
6685}
6686
6687static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6688 struct intel_crtc_state *crtc_state)
6689{
6690 struct drm_device *dev = crtc->base.dev;
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 int refclk, num_connectors = 0;
6693 intel_clock_t clock, reduced_clock;
6694 bool ok, has_reduced_clock = false;
6695 bool is_lvds = false, is_dsi = false;
6696 struct intel_encoder *encoder;
6697 const intel_limit_t *limit;
6698
6699 for_each_intel_encoder(dev, encoder) {
6700 if (encoder->new_crtc != crtc)
6701 continue;
6702
6703 switch (encoder->type) {
6704 case INTEL_OUTPUT_LVDS:
6705 is_lvds = true;
6706 break;
6707 case INTEL_OUTPUT_DSI:
6708 is_dsi = true;
6709 break;
6710 default:
6711 break;
6712 }
6713
6714 num_connectors++;
6715 }
6716
6717 if (is_dsi)
6718 return 0;
6719
6720 if (!crtc_state->clock_set) {
6721 refclk = i9xx_get_refclk(crtc, num_connectors);
6722
6723 /*
6724 * Returns a set of divisors for the desired target clock with
6725 * the given refclk, or FALSE. The returned values represent
6726 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6727 * 2) / p1 / p2.
6728 */
6729 limit = intel_limit(crtc, refclk);
6730 ok = dev_priv->display.find_dpll(limit, crtc,
6731 crtc_state->port_clock,
6732 refclk, NULL, &clock);
6733 if (!ok) {
6734 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6735 return -EINVAL;
6736 }
6737
6738 if (is_lvds && dev_priv->lvds_downclock_avail) {
6739 /*
6740 * Ensure we match the reduced clock's P to the target
6741 * clock. If the clocks don't match, we can't switch
6742 * the display clock by using the FP0/FP1. In such case
6743 * we will disable the LVDS downclock feature.
6744 */
6745 has_reduced_clock =
6746 dev_priv->display.find_dpll(limit, crtc,
6747 dev_priv->lvds_downclock,
6748 refclk, &clock,
6749 &reduced_clock);
6750 }
6751 /* Compat-code for transition, will disappear. */
6752 crtc_state->dpll.n = clock.n;
6753 crtc_state->dpll.m1 = clock.m1;
6754 crtc_state->dpll.m2 = clock.m2;
6755 crtc_state->dpll.p1 = clock.p1;
6756 crtc_state->dpll.p2 = clock.p2;
6757 }
6758
6759 if (IS_GEN2(dev)) {
6760 i8xx_update_pll(crtc, crtc_state,
6761 has_reduced_clock ? &reduced_clock : NULL,
6762 num_connectors);
6763 } else if (IS_CHERRYVIEW(dev)) {
6764 chv_update_pll(crtc, crtc_state);
6765 } else if (IS_VALLEYVIEW(dev)) {
6766 vlv_update_pll(crtc, crtc_state);
6767 } else {
6768 i9xx_update_pll(crtc, crtc_state,
6769 has_reduced_clock ? &reduced_clock : NULL,
6770 num_connectors);
6771 }
6772
6773 return 0;
6774}
6775
6776static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6777 struct intel_crtc_state *pipe_config)
6778{
6779 struct drm_device *dev = crtc->base.dev;
6780 struct drm_i915_private *dev_priv = dev->dev_private;
6781 uint32_t tmp;
6782
6783 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6784 return;
6785
6786 tmp = I915_READ(PFIT_CONTROL);
6787 if (!(tmp & PFIT_ENABLE))
6788 return;
6789
6790 /* Check whether the pfit is attached to our pipe. */
6791 if (INTEL_INFO(dev)->gen < 4) {
6792 if (crtc->pipe != PIPE_B)
6793 return;
6794 } else {
6795 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6796 return;
6797 }
6798
6799 pipe_config->gmch_pfit.control = tmp;
6800 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6801 if (INTEL_INFO(dev)->gen < 5)
6802 pipe_config->gmch_pfit.lvds_border_bits =
6803 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6804}
6805
6806static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6807 struct intel_crtc_state *pipe_config)
6808{
6809 struct drm_device *dev = crtc->base.dev;
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6811 int pipe = pipe_config->cpu_transcoder;
6812 intel_clock_t clock;
6813 u32 mdiv;
6814 int refclk = 100000;
6815
6816 /* In case of MIPI DPLL will not even be used */
6817 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6818 return;
6819
6820 mutex_lock(&dev_priv->dpio_lock);
6821 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6822 mutex_unlock(&dev_priv->dpio_lock);
6823
6824 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6825 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6826 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6827 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6828 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6829
6830 vlv_clock(refclk, &clock);
6831
6832 /* clock.dot is the fast clock */
6833 pipe_config->port_clock = clock.dot / 5;
6834}
6835
6836static void
6837i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6838 struct intel_initial_plane_config *plane_config)
6839{
6840 struct drm_device *dev = crtc->base.dev;
6841 struct drm_i915_private *dev_priv = dev->dev_private;
6842 u32 val, base, offset;
6843 int pipe = crtc->pipe, plane = crtc->plane;
6844 int fourcc, pixel_format;
6845 unsigned int aligned_height;
6846 struct drm_framebuffer *fb;
6847 struct intel_framebuffer *intel_fb;
6848
6849 val = I915_READ(DSPCNTR(plane));
6850 if (!(val & DISPLAY_PLANE_ENABLE))
6851 return;
6852
6853 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6854 if (!intel_fb) {
6855 DRM_DEBUG_KMS("failed to alloc fb\n");
6856 return;
6857 }
6858
6859 fb = &intel_fb->base;
6860
6861 if (INTEL_INFO(dev)->gen >= 4) {
6862 if (val & DISPPLANE_TILED) {
6863 plane_config->tiling = I915_TILING_X;
6864 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6865 }
6866 }
6867
6868 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6869 fourcc = i9xx_format_to_fourcc(pixel_format);
6870 fb->pixel_format = fourcc;
6871 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6872
6873 if (INTEL_INFO(dev)->gen >= 4) {
6874 if (plane_config->tiling)
6875 offset = I915_READ(DSPTILEOFF(plane));
6876 else
6877 offset = I915_READ(DSPLINOFF(plane));
6878 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6879 } else {
6880 base = I915_READ(DSPADDR(plane));
6881 }
6882 plane_config->base = base;
6883
6884 val = I915_READ(PIPESRC(pipe));
6885 fb->width = ((val >> 16) & 0xfff) + 1;
6886 fb->height = ((val >> 0) & 0xfff) + 1;
6887
6888 val = I915_READ(DSPSTRIDE(pipe));
6889 fb->pitches[0] = val & 0xffffffc0;
6890
6891 aligned_height = intel_fb_align_height(dev, fb->height,
6892 fb->pixel_format,
6893 fb->modifier[0]);
6894
6895 plane_config->size = fb->pitches[0] * aligned_height;
6896
6897 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6898 pipe_name(pipe), plane, fb->width, fb->height,
6899 fb->bits_per_pixel, base, fb->pitches[0],
6900 plane_config->size);
6901
6902 plane_config->fb = intel_fb;
6903}
6904
6905static void chv_crtc_clock_get(struct intel_crtc *crtc,
6906 struct intel_crtc_state *pipe_config)
6907{
6908 struct drm_device *dev = crtc->base.dev;
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910 int pipe = pipe_config->cpu_transcoder;
6911 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6912 intel_clock_t clock;
6913 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6914 int refclk = 100000;
6915
6916 mutex_lock(&dev_priv->dpio_lock);
6917 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6918 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6919 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6920 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6921 mutex_unlock(&dev_priv->dpio_lock);
6922
6923 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6924 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6925 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6926 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6927 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6928
6929 chv_clock(refclk, &clock);
6930
6931 /* clock.dot is the fast clock */
6932 pipe_config->port_clock = clock.dot / 5;
6933}
6934
6935static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6936 struct intel_crtc_state *pipe_config)
6937{
6938 struct drm_device *dev = crtc->base.dev;
6939 struct drm_i915_private *dev_priv = dev->dev_private;
6940 uint32_t tmp;
6941
6942 if (!intel_display_power_is_enabled(dev_priv,
6943 POWER_DOMAIN_PIPE(crtc->pipe)))
6944 return false;
6945
6946 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6947 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6948
6949 tmp = I915_READ(PIPECONF(crtc->pipe));
6950 if (!(tmp & PIPECONF_ENABLE))
6951 return false;
6952
6953 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6954 switch (tmp & PIPECONF_BPC_MASK) {
6955 case PIPECONF_6BPC:
6956 pipe_config->pipe_bpp = 18;
6957 break;
6958 case PIPECONF_8BPC:
6959 pipe_config->pipe_bpp = 24;
6960 break;
6961 case PIPECONF_10BPC:
6962 pipe_config->pipe_bpp = 30;
6963 break;
6964 default:
6965 break;
6966 }
6967 }
6968
6969 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6970 pipe_config->limited_color_range = true;
6971
6972 if (INTEL_INFO(dev)->gen < 4)
6973 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6974
6975 intel_get_pipe_timings(crtc, pipe_config);
6976
6977 i9xx_get_pfit_config(crtc, pipe_config);
6978
6979 if (INTEL_INFO(dev)->gen >= 4) {
6980 tmp = I915_READ(DPLL_MD(crtc->pipe));
6981 pipe_config->pixel_multiplier =
6982 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6983 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6984 pipe_config->dpll_hw_state.dpll_md = tmp;
6985 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6986 tmp = I915_READ(DPLL(crtc->pipe));
6987 pipe_config->pixel_multiplier =
6988 ((tmp & SDVO_MULTIPLIER_MASK)
6989 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6990 } else {
6991 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6992 * port and will be fixed up in the encoder->get_config
6993 * function. */
6994 pipe_config->pixel_multiplier = 1;
6995 }
6996 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6997 if (!IS_VALLEYVIEW(dev)) {
6998 /*
6999 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7000 * on 830. Filter it out here so that we don't
7001 * report errors due to that.
7002 */
7003 if (IS_I830(dev))
7004 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7005
7006 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7007 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7008 } else {
7009 /* Mask out read-only status bits. */
7010 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7011 DPLL_PORTC_READY_MASK |
7012 DPLL_PORTB_READY_MASK);
7013 }
7014
7015 if (IS_CHERRYVIEW(dev))
7016 chv_crtc_clock_get(crtc, pipe_config);
7017 else if (IS_VALLEYVIEW(dev))
7018 vlv_crtc_clock_get(crtc, pipe_config);
7019 else
7020 i9xx_crtc_clock_get(crtc, pipe_config);
7021
7022 return true;
7023}
7024
7025static void ironlake_init_pch_refclk(struct drm_device *dev)
7026{
7027 struct drm_i915_private *dev_priv = dev->dev_private;
7028 struct intel_encoder *encoder;
7029 u32 val, final;
7030 bool has_lvds = false;
7031 bool has_cpu_edp = false;
7032 bool has_panel = false;
7033 bool has_ck505 = false;
7034 bool can_ssc = false;
7035
7036 /* We need to take the global config into account */
7037 for_each_intel_encoder(dev, encoder) {
7038 switch (encoder->type) {
7039 case INTEL_OUTPUT_LVDS:
7040 has_panel = true;
7041 has_lvds = true;
7042 break;
7043 case INTEL_OUTPUT_EDP:
7044 has_panel = true;
7045 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7046 has_cpu_edp = true;
7047 break;
7048 default:
7049 break;
7050 }
7051 }
7052
7053 if (HAS_PCH_IBX(dev)) {
7054 has_ck505 = dev_priv->vbt.display_clock_mode;
7055 can_ssc = has_ck505;
7056 } else {
7057 has_ck505 = false;
7058 can_ssc = true;
7059 }
7060
7061 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7062 has_panel, has_lvds, has_ck505);
7063
7064 /* Ironlake: try to setup display ref clock before DPLL
7065 * enabling. This is only under driver's control after
7066 * PCH B stepping, previous chipset stepping should be
7067 * ignoring this setting.
7068 */
7069 val = I915_READ(PCH_DREF_CONTROL);
7070
7071 /* As we must carefully and slowly disable/enable each source in turn,
7072 * compute the final state we want first and check if we need to
7073 * make any changes at all.
7074 */
7075 final = val;
7076 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7077 if (has_ck505)
7078 final |= DREF_NONSPREAD_CK505_ENABLE;
7079 else
7080 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7081
7082 final &= ~DREF_SSC_SOURCE_MASK;
7083 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7084 final &= ~DREF_SSC1_ENABLE;
7085
7086 if (has_panel) {
7087 final |= DREF_SSC_SOURCE_ENABLE;
7088
7089 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7090 final |= DREF_SSC1_ENABLE;
7091
7092 if (has_cpu_edp) {
7093 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7094 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7095 else
7096 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7097 } else
7098 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7099 } else {
7100 final |= DREF_SSC_SOURCE_DISABLE;
7101 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7102 }
7103
7104 if (final == val)
7105 return;
7106
7107 /* Always enable nonspread source */
7108 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7109
7110 if (has_ck505)
7111 val |= DREF_NONSPREAD_CK505_ENABLE;
7112 else
7113 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7114
7115 if (has_panel) {
7116 val &= ~DREF_SSC_SOURCE_MASK;
7117 val |= DREF_SSC_SOURCE_ENABLE;
7118
7119 /* SSC must be turned on before enabling the CPU output */
7120 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7121 DRM_DEBUG_KMS("Using SSC on panel\n");
7122 val |= DREF_SSC1_ENABLE;
7123 } else
7124 val &= ~DREF_SSC1_ENABLE;
7125
7126 /* Get SSC going before enabling the outputs */
7127 I915_WRITE(PCH_DREF_CONTROL, val);
7128 POSTING_READ(PCH_DREF_CONTROL);
7129 udelay(200);
7130
7131 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7132
7133 /* Enable CPU source on CPU attached eDP */
7134 if (has_cpu_edp) {
7135 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7136 DRM_DEBUG_KMS("Using SSC on eDP\n");
7137 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7138 } else
7139 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7140 } else
7141 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7142
7143 I915_WRITE(PCH_DREF_CONTROL, val);
7144 POSTING_READ(PCH_DREF_CONTROL);
7145 udelay(200);
7146 } else {
7147 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7148
7149 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7150
7151 /* Turn off CPU output */
7152 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7153
7154 I915_WRITE(PCH_DREF_CONTROL, val);
7155 POSTING_READ(PCH_DREF_CONTROL);
7156 udelay(200);
7157
7158 /* Turn off the SSC source */
7159 val &= ~DREF_SSC_SOURCE_MASK;
7160 val |= DREF_SSC_SOURCE_DISABLE;
7161
7162 /* Turn off SSC1 */
7163 val &= ~DREF_SSC1_ENABLE;
7164
7165 I915_WRITE(PCH_DREF_CONTROL, val);
7166 POSTING_READ(PCH_DREF_CONTROL);
7167 udelay(200);
7168 }
7169
7170 BUG_ON(val != final);
7171}
7172
7173static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7174{
7175 uint32_t tmp;
7176
7177 tmp = I915_READ(SOUTH_CHICKEN2);
7178 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7179 I915_WRITE(SOUTH_CHICKEN2, tmp);
7180
7181 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7182 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7183 DRM_ERROR("FDI mPHY reset assert timeout\n");
7184
7185 tmp = I915_READ(SOUTH_CHICKEN2);
7186 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7187 I915_WRITE(SOUTH_CHICKEN2, tmp);
7188
7189 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7190 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7191 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7192}
7193
7194/* WaMPhyProgramming:hsw */
7195static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7196{
7197 uint32_t tmp;
7198
7199 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7200 tmp &= ~(0xFF << 24);
7201 tmp |= (0x12 << 24);
7202 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7203
7204 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7205 tmp |= (1 << 11);
7206 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7207
7208 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7209 tmp |= (1 << 11);
7210 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7211
7212 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7213 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7214 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7215
7216 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7217 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7218 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7219
7220 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7221 tmp &= ~(7 << 13);
7222 tmp |= (5 << 13);
7223 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7224
7225 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7226 tmp &= ~(7 << 13);
7227 tmp |= (5 << 13);
7228 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7229
7230 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7231 tmp &= ~0xFF;
7232 tmp |= 0x1C;
7233 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7234
7235 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7236 tmp &= ~0xFF;
7237 tmp |= 0x1C;
7238 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7239
7240 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7241 tmp &= ~(0xFF << 16);
7242 tmp |= (0x1C << 16);
7243 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7244
7245 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7246 tmp &= ~(0xFF << 16);
7247 tmp |= (0x1C << 16);
7248 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7249
7250 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7251 tmp |= (1 << 27);
7252 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7253
7254 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7255 tmp |= (1 << 27);
7256 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7257
7258 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7259 tmp &= ~(0xF << 28);
7260 tmp |= (4 << 28);
7261 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7262
7263 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7264 tmp &= ~(0xF << 28);
7265 tmp |= (4 << 28);
7266 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7267}
7268
7269/* Implements 3 different sequences from BSpec chapter "Display iCLK
7270 * Programming" based on the parameters passed:
7271 * - Sequence to enable CLKOUT_DP
7272 * - Sequence to enable CLKOUT_DP without spread
7273 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7274 */
7275static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7276 bool with_fdi)
7277{
7278 struct drm_i915_private *dev_priv = dev->dev_private;
7279 uint32_t reg, tmp;
7280
7281 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7282 with_spread = true;
7283 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7284 with_fdi, "LP PCH doesn't have FDI\n"))
7285 with_fdi = false;
7286
7287 mutex_lock(&dev_priv->dpio_lock);
7288
7289 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7290 tmp &= ~SBI_SSCCTL_DISABLE;
7291 tmp |= SBI_SSCCTL_PATHALT;
7292 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7293
7294 udelay(24);
7295
7296 if (with_spread) {
7297 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7298 tmp &= ~SBI_SSCCTL_PATHALT;
7299 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7300
7301 if (with_fdi) {
7302 lpt_reset_fdi_mphy(dev_priv);
7303 lpt_program_fdi_mphy(dev_priv);
7304 }
7305 }
7306
7307 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7308 SBI_GEN0 : SBI_DBUFF0;
7309 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7310 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7311 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7312
7313 mutex_unlock(&dev_priv->dpio_lock);
7314}
7315
7316/* Sequence to disable CLKOUT_DP */
7317static void lpt_disable_clkout_dp(struct drm_device *dev)
7318{
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7320 uint32_t reg, tmp;
7321
7322 mutex_lock(&dev_priv->dpio_lock);
7323
7324 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7325 SBI_GEN0 : SBI_DBUFF0;
7326 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7327 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7328 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7329
7330 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7331 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7332 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7333 tmp |= SBI_SSCCTL_PATHALT;
7334 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7335 udelay(32);
7336 }
7337 tmp |= SBI_SSCCTL_DISABLE;
7338 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7339 }
7340
7341 mutex_unlock(&dev_priv->dpio_lock);
7342}
7343
7344static void lpt_init_pch_refclk(struct drm_device *dev)
7345{
7346 struct intel_encoder *encoder;
7347 bool has_vga = false;
7348
7349 for_each_intel_encoder(dev, encoder) {
7350 switch (encoder->type) {
7351 case INTEL_OUTPUT_ANALOG:
7352 has_vga = true;
7353 break;
7354 default:
7355 break;
7356 }
7357 }
7358
7359 if (has_vga)
7360 lpt_enable_clkout_dp(dev, true, true);
7361 else
7362 lpt_disable_clkout_dp(dev);
7363}
7364
7365/*
7366 * Initialize reference clocks when the driver loads
7367 */
7368void intel_init_pch_refclk(struct drm_device *dev)
7369{
7370 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7371 ironlake_init_pch_refclk(dev);
7372 else if (HAS_PCH_LPT(dev))
7373 lpt_init_pch_refclk(dev);
7374}
7375
7376static int ironlake_get_refclk(struct drm_crtc *crtc)
7377{
7378 struct drm_device *dev = crtc->dev;
7379 struct drm_i915_private *dev_priv = dev->dev_private;
7380 struct intel_encoder *encoder;
7381 int num_connectors = 0;
7382 bool is_lvds = false;
7383
7384 for_each_intel_encoder(dev, encoder) {
7385 if (encoder->new_crtc != to_intel_crtc(crtc))
7386 continue;
7387
7388 switch (encoder->type) {
7389 case INTEL_OUTPUT_LVDS:
7390 is_lvds = true;
7391 break;
7392 default:
7393 break;
7394 }
7395 num_connectors++;
7396 }
7397
7398 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7399 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7400 dev_priv->vbt.lvds_ssc_freq);
7401 return dev_priv->vbt.lvds_ssc_freq;
7402 }
7403
7404 return 120000;
7405}
7406
7407static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7408{
7409 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7411 int pipe = intel_crtc->pipe;
7412 uint32_t val;
7413
7414 val = 0;
7415
7416 switch (intel_crtc->config->pipe_bpp) {
7417 case 18:
7418 val |= PIPECONF_6BPC;
7419 break;
7420 case 24:
7421 val |= PIPECONF_8BPC;
7422 break;
7423 case 30:
7424 val |= PIPECONF_10BPC;
7425 break;
7426 case 36:
7427 val |= PIPECONF_12BPC;
7428 break;
7429 default:
7430 /* Case prevented by intel_choose_pipe_bpp_dither. */
7431 BUG();
7432 }
7433
7434 if (intel_crtc->config->dither)
7435 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7436
7437 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7438 val |= PIPECONF_INTERLACED_ILK;
7439 else
7440 val |= PIPECONF_PROGRESSIVE;
7441
7442 if (intel_crtc->config->limited_color_range)
7443 val |= PIPECONF_COLOR_RANGE_SELECT;
7444
7445 I915_WRITE(PIPECONF(pipe), val);
7446 POSTING_READ(PIPECONF(pipe));
7447}
7448
7449/*
7450 * Set up the pipe CSC unit.
7451 *
7452 * Currently only full range RGB to limited range RGB conversion
7453 * is supported, but eventually this should handle various
7454 * RGB<->YCbCr scenarios as well.
7455 */
7456static void intel_set_pipe_csc(struct drm_crtc *crtc)
7457{
7458 struct drm_device *dev = crtc->dev;
7459 struct drm_i915_private *dev_priv = dev->dev_private;
7460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7461 int pipe = intel_crtc->pipe;
7462 uint16_t coeff = 0x7800; /* 1.0 */
7463
7464 /*
7465 * TODO: Check what kind of values actually come out of the pipe
7466 * with these coeff/postoff values and adjust to get the best
7467 * accuracy. Perhaps we even need to take the bpc value into
7468 * consideration.
7469 */
7470
7471 if (intel_crtc->config->limited_color_range)
7472 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7473
7474 /*
7475 * GY/GU and RY/RU should be the other way around according
7476 * to BSpec, but reality doesn't agree. Just set them up in
7477 * a way that results in the correct picture.
7478 */
7479 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7480 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7481
7482 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7483 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7484
7485 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7486 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7487
7488 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7489 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7490 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7491
7492 if (INTEL_INFO(dev)->gen > 6) {
7493 uint16_t postoff = 0;
7494
7495 if (intel_crtc->config->limited_color_range)
7496 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7497
7498 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7499 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7500 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7501
7502 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7503 } else {
7504 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7505
7506 if (intel_crtc->config->limited_color_range)
7507 mode |= CSC_BLACK_SCREEN_OFFSET;
7508
7509 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7510 }
7511}
7512
7513static void haswell_set_pipeconf(struct drm_crtc *crtc)
7514{
7515 struct drm_device *dev = crtc->dev;
7516 struct drm_i915_private *dev_priv = dev->dev_private;
7517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7518 enum pipe pipe = intel_crtc->pipe;
7519 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7520 uint32_t val;
7521
7522 val = 0;
7523
7524 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7525 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7526
7527 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7528 val |= PIPECONF_INTERLACED_ILK;
7529 else
7530 val |= PIPECONF_PROGRESSIVE;
7531
7532 I915_WRITE(PIPECONF(cpu_transcoder), val);
7533 POSTING_READ(PIPECONF(cpu_transcoder));
7534
7535 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7536 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7537
7538 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7539 val = 0;
7540
7541 switch (intel_crtc->config->pipe_bpp) {
7542 case 18:
7543 val |= PIPEMISC_DITHER_6_BPC;
7544 break;
7545 case 24:
7546 val |= PIPEMISC_DITHER_8_BPC;
7547 break;
7548 case 30:
7549 val |= PIPEMISC_DITHER_10_BPC;
7550 break;
7551 case 36:
7552 val |= PIPEMISC_DITHER_12_BPC;
7553 break;
7554 default:
7555 /* Case prevented by pipe_config_set_bpp. */
7556 BUG();
7557 }
7558
7559 if (intel_crtc->config->dither)
7560 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7561
7562 I915_WRITE(PIPEMISC(pipe), val);
7563 }
7564}
7565
7566static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7567 struct intel_crtc_state *crtc_state,
7568 intel_clock_t *clock,
7569 bool *has_reduced_clock,
7570 intel_clock_t *reduced_clock)
7571{
7572 struct drm_device *dev = crtc->dev;
7573 struct drm_i915_private *dev_priv = dev->dev_private;
7574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7575 int refclk;
7576 const intel_limit_t *limit;
7577 bool ret, is_lvds = false;
7578
7579 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7580
7581 refclk = ironlake_get_refclk(crtc);
7582
7583 /*
7584 * Returns a set of divisors for the desired target clock with the given
7585 * refclk, or FALSE. The returned values represent the clock equation:
7586 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7587 */
7588 limit = intel_limit(intel_crtc, refclk);
7589 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7590 crtc_state->port_clock,
7591 refclk, NULL, clock);
7592 if (!ret)
7593 return false;
7594
7595 if (is_lvds && dev_priv->lvds_downclock_avail) {
7596 /*
7597 * Ensure we match the reduced clock's P to the target clock.
7598 * If the clocks don't match, we can't switch the display clock
7599 * by using the FP0/FP1. In such case we will disable the LVDS
7600 * downclock feature.
7601 */
7602 *has_reduced_clock =
7603 dev_priv->display.find_dpll(limit, intel_crtc,
7604 dev_priv->lvds_downclock,
7605 refclk, clock,
7606 reduced_clock);
7607 }
7608
7609 return true;
7610}
7611
7612int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7613{
7614 /*
7615 * Account for spread spectrum to avoid
7616 * oversubscribing the link. Max center spread
7617 * is 2.5%; use 5% for safety's sake.
7618 */
7619 u32 bps = target_clock * bpp * 21 / 20;
7620 return DIV_ROUND_UP(bps, link_bw * 8);
7621}
7622
7623static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7624{
7625 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7626}
7627
7628static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7629 struct intel_crtc_state *crtc_state,
7630 u32 *fp,
7631 intel_clock_t *reduced_clock, u32 *fp2)
7632{
7633 struct drm_crtc *crtc = &intel_crtc->base;
7634 struct drm_device *dev = crtc->dev;
7635 struct drm_i915_private *dev_priv = dev->dev_private;
7636 struct intel_encoder *intel_encoder;
7637 uint32_t dpll;
7638 int factor, num_connectors = 0;
7639 bool is_lvds = false, is_sdvo = false;
7640
7641 for_each_intel_encoder(dev, intel_encoder) {
7642 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7643 continue;
7644
7645 switch (intel_encoder->type) {
7646 case INTEL_OUTPUT_LVDS:
7647 is_lvds = true;
7648 break;
7649 case INTEL_OUTPUT_SDVO:
7650 case INTEL_OUTPUT_HDMI:
7651 is_sdvo = true;
7652 break;
7653 default:
7654 break;
7655 }
7656
7657 num_connectors++;
7658 }
7659
7660 /* Enable autotuning of the PLL clock (if permissible) */
7661 factor = 21;
7662 if (is_lvds) {
7663 if ((intel_panel_use_ssc(dev_priv) &&
7664 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7665 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7666 factor = 25;
7667 } else if (crtc_state->sdvo_tv_clock)
7668 factor = 20;
7669
7670 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7671 *fp |= FP_CB_TUNE;
7672
7673 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7674 *fp2 |= FP_CB_TUNE;
7675
7676 dpll = 0;
7677
7678 if (is_lvds)
7679 dpll |= DPLLB_MODE_LVDS;
7680 else
7681 dpll |= DPLLB_MODE_DAC_SERIAL;
7682
7683 dpll |= (crtc_state->pixel_multiplier - 1)
7684 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7685
7686 if (is_sdvo)
7687 dpll |= DPLL_SDVO_HIGH_SPEED;
7688 if (crtc_state->has_dp_encoder)
7689 dpll |= DPLL_SDVO_HIGH_SPEED;
7690
7691 /* compute bitmask from p1 value */
7692 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7693 /* also FPA1 */
7694 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7695
7696 switch (crtc_state->dpll.p2) {
7697 case 5:
7698 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7699 break;
7700 case 7:
7701 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7702 break;
7703 case 10:
7704 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7705 break;
7706 case 14:
7707 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7708 break;
7709 }
7710
7711 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7712 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7713 else
7714 dpll |= PLL_REF_INPUT_DREFCLK;
7715
7716 return dpll | DPLL_VCO_ENABLE;
7717}
7718
7719static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7720 struct intel_crtc_state *crtc_state)
7721{
7722 struct drm_device *dev = crtc->base.dev;
7723 intel_clock_t clock, reduced_clock;
7724 u32 dpll = 0, fp = 0, fp2 = 0;
7725 bool ok, has_reduced_clock = false;
7726 bool is_lvds = false;
7727 struct intel_shared_dpll *pll;
7728
7729 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7730
7731 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7732 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7733
7734 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7735 &has_reduced_clock, &reduced_clock);
7736 if (!ok && !crtc_state->clock_set) {
7737 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7738 return -EINVAL;
7739 }
7740 /* Compat-code for transition, will disappear. */
7741 if (!crtc_state->clock_set) {
7742 crtc_state->dpll.n = clock.n;
7743 crtc_state->dpll.m1 = clock.m1;
7744 crtc_state->dpll.m2 = clock.m2;
7745 crtc_state->dpll.p1 = clock.p1;
7746 crtc_state->dpll.p2 = clock.p2;
7747 }
7748
7749 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7750 if (crtc_state->has_pch_encoder) {
7751 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7752 if (has_reduced_clock)
7753 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7754
7755 dpll = ironlake_compute_dpll(crtc, crtc_state,
7756 &fp, &reduced_clock,
7757 has_reduced_clock ? &fp2 : NULL);
7758
7759 crtc_state->dpll_hw_state.dpll = dpll;
7760 crtc_state->dpll_hw_state.fp0 = fp;
7761 if (has_reduced_clock)
7762 crtc_state->dpll_hw_state.fp1 = fp2;
7763 else
7764 crtc_state->dpll_hw_state.fp1 = fp;
7765
7766 pll = intel_get_shared_dpll(crtc, crtc_state);
7767 if (pll == NULL) {
7768 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7769 pipe_name(crtc->pipe));
7770 return -EINVAL;
7771 }
7772 }
7773
7774 if (is_lvds && has_reduced_clock && i915.powersave)
7775 crtc->lowfreq_avail = true;
7776 else
7777 crtc->lowfreq_avail = false;
7778
7779 return 0;
7780}
7781
7782static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7783 struct intel_link_m_n *m_n)
7784{
7785 struct drm_device *dev = crtc->base.dev;
7786 struct drm_i915_private *dev_priv = dev->dev_private;
7787 enum pipe pipe = crtc->pipe;
7788
7789 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7790 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7791 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7792 & ~TU_SIZE_MASK;
7793 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7794 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7795 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7796}
7797
7798static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7799 enum transcoder transcoder,
7800 struct intel_link_m_n *m_n,
7801 struct intel_link_m_n *m2_n2)
7802{
7803 struct drm_device *dev = crtc->base.dev;
7804 struct drm_i915_private *dev_priv = dev->dev_private;
7805 enum pipe pipe = crtc->pipe;
7806
7807 if (INTEL_INFO(dev)->gen >= 5) {
7808 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7809 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7810 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7811 & ~TU_SIZE_MASK;
7812 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7813 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7814 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7815 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7816 * gen < 8) and if DRRS is supported (to make sure the
7817 * registers are not unnecessarily read).
7818 */
7819 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7820 crtc->config->has_drrs) {
7821 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7822 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7823 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7824 & ~TU_SIZE_MASK;
7825 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7826 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7827 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7828 }
7829 } else {
7830 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7831 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7832 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7833 & ~TU_SIZE_MASK;
7834 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7835 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7836 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7837 }
7838}
7839
7840void intel_dp_get_m_n(struct intel_crtc *crtc,
7841 struct intel_crtc_state *pipe_config)
7842{
7843 if (pipe_config->has_pch_encoder)
7844 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7845 else
7846 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7847 &pipe_config->dp_m_n,
7848 &pipe_config->dp_m2_n2);
7849}
7850
7851static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7852 struct intel_crtc_state *pipe_config)
7853{
7854 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7855 &pipe_config->fdi_m_n, NULL);
7856}
7857
7858static void skylake_get_pfit_config(struct intel_crtc *crtc,
7859 struct intel_crtc_state *pipe_config)
7860{
7861 struct drm_device *dev = crtc->base.dev;
7862 struct drm_i915_private *dev_priv = dev->dev_private;
7863 uint32_t tmp;
7864
7865 tmp = I915_READ(PS_CTL(crtc->pipe));
7866
7867 if (tmp & PS_ENABLE) {
7868 pipe_config->pch_pfit.enabled = true;
7869 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7870 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7871 }
7872}
7873
7874static void
7875skylake_get_initial_plane_config(struct intel_crtc *crtc,
7876 struct intel_initial_plane_config *plane_config)
7877{
7878 struct drm_device *dev = crtc->base.dev;
7879 struct drm_i915_private *dev_priv = dev->dev_private;
7880 u32 val, base, offset, stride_mult, tiling;
7881 int pipe = crtc->pipe;
7882 int fourcc, pixel_format;
7883 unsigned int aligned_height;
7884 struct drm_framebuffer *fb;
7885 struct intel_framebuffer *intel_fb;
7886
7887 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7888 if (!intel_fb) {
7889 DRM_DEBUG_KMS("failed to alloc fb\n");
7890 return;
7891 }
7892
7893 fb = &intel_fb->base;
7894
7895 val = I915_READ(PLANE_CTL(pipe, 0));
7896 if (!(val & PLANE_CTL_ENABLE))
7897 goto error;
7898
7899 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7900 fourcc = skl_format_to_fourcc(pixel_format,
7901 val & PLANE_CTL_ORDER_RGBX,
7902 val & PLANE_CTL_ALPHA_MASK);
7903 fb->pixel_format = fourcc;
7904 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7905
7906 tiling = val & PLANE_CTL_TILED_MASK;
7907 switch (tiling) {
7908 case PLANE_CTL_TILED_LINEAR:
7909 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7910 break;
7911 case PLANE_CTL_TILED_X:
7912 plane_config->tiling = I915_TILING_X;
7913 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7914 break;
7915 case PLANE_CTL_TILED_Y:
7916 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7917 break;
7918 case PLANE_CTL_TILED_YF:
7919 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7920 break;
7921 default:
7922 MISSING_CASE(tiling);
7923 goto error;
7924 }
7925
7926 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7927 plane_config->base = base;
7928
7929 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7930
7931 val = I915_READ(PLANE_SIZE(pipe, 0));
7932 fb->height = ((val >> 16) & 0xfff) + 1;
7933 fb->width = ((val >> 0) & 0x1fff) + 1;
7934
7935 val = I915_READ(PLANE_STRIDE(pipe, 0));
7936 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7937 fb->pixel_format);
7938 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7939
7940 aligned_height = intel_fb_align_height(dev, fb->height,
7941 fb->pixel_format,
7942 fb->modifier[0]);
7943
7944 plane_config->size = fb->pitches[0] * aligned_height;
7945
7946 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7947 pipe_name(pipe), fb->width, fb->height,
7948 fb->bits_per_pixel, base, fb->pitches[0],
7949 plane_config->size);
7950
7951 plane_config->fb = intel_fb;
7952 return;
7953
7954error:
7955 kfree(fb);
7956}
7957
7958static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7959 struct intel_crtc_state *pipe_config)
7960{
7961 struct drm_device *dev = crtc->base.dev;
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7963 uint32_t tmp;
7964
7965 tmp = I915_READ(PF_CTL(crtc->pipe));
7966
7967 if (tmp & PF_ENABLE) {
7968 pipe_config->pch_pfit.enabled = true;
7969 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7970 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7971
7972 /* We currently do not free assignements of panel fitters on
7973 * ivb/hsw (since we don't use the higher upscaling modes which
7974 * differentiates them) so just WARN about this case for now. */
7975 if (IS_GEN7(dev)) {
7976 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7977 PF_PIPE_SEL_IVB(crtc->pipe));
7978 }
7979 }
7980}
7981
7982static void
7983ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7984 struct intel_initial_plane_config *plane_config)
7985{
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 u32 val, base, offset;
7989 int pipe = crtc->pipe;
7990 int fourcc, pixel_format;
7991 unsigned int aligned_height;
7992 struct drm_framebuffer *fb;
7993 struct intel_framebuffer *intel_fb;
7994
7995 val = I915_READ(DSPCNTR(pipe));
7996 if (!(val & DISPLAY_PLANE_ENABLE))
7997 return;
7998
7999 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8000 if (!intel_fb) {
8001 DRM_DEBUG_KMS("failed to alloc fb\n");
8002 return;
8003 }
8004
8005 fb = &intel_fb->base;
8006
8007 if (INTEL_INFO(dev)->gen >= 4) {
8008 if (val & DISPPLANE_TILED) {
8009 plane_config->tiling = I915_TILING_X;
8010 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8011 }
8012 }
8013
8014 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8015 fourcc = i9xx_format_to_fourcc(pixel_format);
8016 fb->pixel_format = fourcc;
8017 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8018
8019 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8020 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8021 offset = I915_READ(DSPOFFSET(pipe));
8022 } else {
8023 if (plane_config->tiling)
8024 offset = I915_READ(DSPTILEOFF(pipe));
8025 else
8026 offset = I915_READ(DSPLINOFF(pipe));
8027 }
8028 plane_config->base = base;
8029
8030 val = I915_READ(PIPESRC(pipe));
8031 fb->width = ((val >> 16) & 0xfff) + 1;
8032 fb->height = ((val >> 0) & 0xfff) + 1;
8033
8034 val = I915_READ(DSPSTRIDE(pipe));
8035 fb->pitches[0] = val & 0xffffffc0;
8036
8037 aligned_height = intel_fb_align_height(dev, fb->height,
8038 fb->pixel_format,
8039 fb->modifier[0]);
8040
8041 plane_config->size = fb->pitches[0] * aligned_height;
8042
8043 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8044 pipe_name(pipe), fb->width, fb->height,
8045 fb->bits_per_pixel, base, fb->pitches[0],
8046 plane_config->size);
8047
8048 plane_config->fb = intel_fb;
8049}
8050
8051static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8052 struct intel_crtc_state *pipe_config)
8053{
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 uint32_t tmp;
8057
8058 if (!intel_display_power_is_enabled(dev_priv,
8059 POWER_DOMAIN_PIPE(crtc->pipe)))
8060 return false;
8061
8062 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8063 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8064
8065 tmp = I915_READ(PIPECONF(crtc->pipe));
8066 if (!(tmp & PIPECONF_ENABLE))
8067 return false;
8068
8069 switch (tmp & PIPECONF_BPC_MASK) {
8070 case PIPECONF_6BPC:
8071 pipe_config->pipe_bpp = 18;
8072 break;
8073 case PIPECONF_8BPC:
8074 pipe_config->pipe_bpp = 24;
8075 break;
8076 case PIPECONF_10BPC:
8077 pipe_config->pipe_bpp = 30;
8078 break;
8079 case PIPECONF_12BPC:
8080 pipe_config->pipe_bpp = 36;
8081 break;
8082 default:
8083 break;
8084 }
8085
8086 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8087 pipe_config->limited_color_range = true;
8088
8089 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8090 struct intel_shared_dpll *pll;
8091
8092 pipe_config->has_pch_encoder = true;
8093
8094 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8095 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8096 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8097
8098 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8099
8100 if (HAS_PCH_IBX(dev_priv->dev)) {
8101 pipe_config->shared_dpll =
8102 (enum intel_dpll_id) crtc->pipe;
8103 } else {
8104 tmp = I915_READ(PCH_DPLL_SEL);
8105 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8106 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8107 else
8108 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8109 }
8110
8111 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8112
8113 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8114 &pipe_config->dpll_hw_state));
8115
8116 tmp = pipe_config->dpll_hw_state.dpll;
8117 pipe_config->pixel_multiplier =
8118 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8119 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8120
8121 ironlake_pch_clock_get(crtc, pipe_config);
8122 } else {
8123 pipe_config->pixel_multiplier = 1;
8124 }
8125
8126 intel_get_pipe_timings(crtc, pipe_config);
8127
8128 ironlake_get_pfit_config(crtc, pipe_config);
8129
8130 return true;
8131}
8132
8133static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8134{
8135 struct drm_device *dev = dev_priv->dev;
8136 struct intel_crtc *crtc;
8137
8138 for_each_intel_crtc(dev, crtc)
8139 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8140 pipe_name(crtc->pipe));
8141
8142 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8143 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8144 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8145 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8146 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8147 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8148 "CPU PWM1 enabled\n");
8149 if (IS_HASWELL(dev))
8150 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8151 "CPU PWM2 enabled\n");
8152 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8153 "PCH PWM1 enabled\n");
8154 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8155 "Utility pin enabled\n");
8156 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8157
8158 /*
8159 * In theory we can still leave IRQs enabled, as long as only the HPD
8160 * interrupts remain enabled. We used to check for that, but since it's
8161 * gen-specific and since we only disable LCPLL after we fully disable
8162 * the interrupts, the check below should be enough.
8163 */
8164 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8165}
8166
8167static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8168{
8169 struct drm_device *dev = dev_priv->dev;
8170
8171 if (IS_HASWELL(dev))
8172 return I915_READ(D_COMP_HSW);
8173 else
8174 return I915_READ(D_COMP_BDW);
8175}
8176
8177static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8178{
8179 struct drm_device *dev = dev_priv->dev;
8180
8181 if (IS_HASWELL(dev)) {
8182 mutex_lock(&dev_priv->rps.hw_lock);
8183 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8184 val))
8185 DRM_ERROR("Failed to write to D_COMP\n");
8186 mutex_unlock(&dev_priv->rps.hw_lock);
8187 } else {
8188 I915_WRITE(D_COMP_BDW, val);
8189 POSTING_READ(D_COMP_BDW);
8190 }
8191}
8192
8193/*
8194 * This function implements pieces of two sequences from BSpec:
8195 * - Sequence for display software to disable LCPLL
8196 * - Sequence for display software to allow package C8+
8197 * The steps implemented here are just the steps that actually touch the LCPLL
8198 * register. Callers should take care of disabling all the display engine
8199 * functions, doing the mode unset, fixing interrupts, etc.
8200 */
8201static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8202 bool switch_to_fclk, bool allow_power_down)
8203{
8204 uint32_t val;
8205
8206 assert_can_disable_lcpll(dev_priv);
8207
8208 val = I915_READ(LCPLL_CTL);
8209
8210 if (switch_to_fclk) {
8211 val |= LCPLL_CD_SOURCE_FCLK;
8212 I915_WRITE(LCPLL_CTL, val);
8213
8214 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8215 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8216 DRM_ERROR("Switching to FCLK failed\n");
8217
8218 val = I915_READ(LCPLL_CTL);
8219 }
8220
8221 val |= LCPLL_PLL_DISABLE;
8222 I915_WRITE(LCPLL_CTL, val);
8223 POSTING_READ(LCPLL_CTL);
8224
8225 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8226 DRM_ERROR("LCPLL still locked\n");
8227
8228 val = hsw_read_dcomp(dev_priv);
8229 val |= D_COMP_COMP_DISABLE;
8230 hsw_write_dcomp(dev_priv, val);
8231 ndelay(100);
8232
8233 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8234 1))
8235 DRM_ERROR("D_COMP RCOMP still in progress\n");
8236
8237 if (allow_power_down) {
8238 val = I915_READ(LCPLL_CTL);
8239 val |= LCPLL_POWER_DOWN_ALLOW;
8240 I915_WRITE(LCPLL_CTL, val);
8241 POSTING_READ(LCPLL_CTL);
8242 }
8243}
8244
8245/*
8246 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8247 * source.
8248 */
8249static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8250{
8251 uint32_t val;
8252
8253 val = I915_READ(LCPLL_CTL);
8254
8255 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8256 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8257 return;
8258
8259 /*
8260 * Make sure we're not on PC8 state before disabling PC8, otherwise
8261 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8262 */
8263 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8264
8265 if (val & LCPLL_POWER_DOWN_ALLOW) {
8266 val &= ~LCPLL_POWER_DOWN_ALLOW;
8267 I915_WRITE(LCPLL_CTL, val);
8268 POSTING_READ(LCPLL_CTL);
8269 }
8270
8271 val = hsw_read_dcomp(dev_priv);
8272 val |= D_COMP_COMP_FORCE;
8273 val &= ~D_COMP_COMP_DISABLE;
8274 hsw_write_dcomp(dev_priv, val);
8275
8276 val = I915_READ(LCPLL_CTL);
8277 val &= ~LCPLL_PLL_DISABLE;
8278 I915_WRITE(LCPLL_CTL, val);
8279
8280 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8281 DRM_ERROR("LCPLL not locked yet\n");
8282
8283 if (val & LCPLL_CD_SOURCE_FCLK) {
8284 val = I915_READ(LCPLL_CTL);
8285 val &= ~LCPLL_CD_SOURCE_FCLK;
8286 I915_WRITE(LCPLL_CTL, val);
8287
8288 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8289 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8290 DRM_ERROR("Switching back to LCPLL failed\n");
8291 }
8292
8293 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8294}
8295
8296/*
8297 * Package states C8 and deeper are really deep PC states that can only be
8298 * reached when all the devices on the system allow it, so even if the graphics
8299 * device allows PC8+, it doesn't mean the system will actually get to these
8300 * states. Our driver only allows PC8+ when going into runtime PM.
8301 *
8302 * The requirements for PC8+ are that all the outputs are disabled, the power
8303 * well is disabled and most interrupts are disabled, and these are also
8304 * requirements for runtime PM. When these conditions are met, we manually do
8305 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8306 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8307 * hang the machine.
8308 *
8309 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8310 * the state of some registers, so when we come back from PC8+ we need to
8311 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8312 * need to take care of the registers kept by RC6. Notice that this happens even
8313 * if we don't put the device in PCI D3 state (which is what currently happens
8314 * because of the runtime PM support).
8315 *
8316 * For more, read "Display Sequences for Package C8" on the hardware
8317 * documentation.
8318 */
8319void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8320{
8321 struct drm_device *dev = dev_priv->dev;
8322 uint32_t val;
8323
8324 DRM_DEBUG_KMS("Enabling package C8+\n");
8325
8326 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8327 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8328 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8329 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8330 }
8331
8332 lpt_disable_clkout_dp(dev);
8333 hsw_disable_lcpll(dev_priv, true, true);
8334}
8335
8336void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8337{
8338 struct drm_device *dev = dev_priv->dev;
8339 uint32_t val;
8340
8341 DRM_DEBUG_KMS("Disabling package C8+\n");
8342
8343 hsw_restore_lcpll(dev_priv);
8344 lpt_init_pch_refclk(dev);
8345
8346 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8347 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8348 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8349 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8350 }
8351
8352 intel_prepare_ddi(dev);
8353}
8354
8355static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8356 struct intel_crtc_state *crtc_state)
8357{
8358 if (!intel_ddi_pll_select(crtc, crtc_state))
8359 return -EINVAL;
8360
8361 crtc->lowfreq_avail = false;
8362
8363 return 0;
8364}
8365
8366static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8367 enum port port,
8368 struct intel_crtc_state *pipe_config)
8369{
8370 u32 temp, dpll_ctl1;
8371
8372 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8373 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8374
8375 switch (pipe_config->ddi_pll_sel) {
8376 case SKL_DPLL0:
8377 /*
8378 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8379 * of the shared DPLL framework and thus needs to be read out
8380 * separately
8381 */
8382 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8383 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8384 break;
8385 case SKL_DPLL1:
8386 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8387 break;
8388 case SKL_DPLL2:
8389 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8390 break;
8391 case SKL_DPLL3:
8392 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8393 break;
8394 }
8395}
8396
8397static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8398 enum port port,
8399 struct intel_crtc_state *pipe_config)
8400{
8401 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8402
8403 switch (pipe_config->ddi_pll_sel) {
8404 case PORT_CLK_SEL_WRPLL1:
8405 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8406 break;
8407 case PORT_CLK_SEL_WRPLL2:
8408 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8409 break;
8410 }
8411}
8412
8413static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8414 struct intel_crtc_state *pipe_config)
8415{
8416 struct drm_device *dev = crtc->base.dev;
8417 struct drm_i915_private *dev_priv = dev->dev_private;
8418 struct intel_shared_dpll *pll;
8419 enum port port;
8420 uint32_t tmp;
8421
8422 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8423
8424 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8425
8426 if (IS_SKYLAKE(dev))
8427 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8428 else
8429 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8430
8431 if (pipe_config->shared_dpll >= 0) {
8432 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8433
8434 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8435 &pipe_config->dpll_hw_state));
8436 }
8437
8438 /*
8439 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8440 * DDI E. So just check whether this pipe is wired to DDI E and whether
8441 * the PCH transcoder is on.
8442 */
8443 if (INTEL_INFO(dev)->gen < 9 &&
8444 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8445 pipe_config->has_pch_encoder = true;
8446
8447 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8448 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8449 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8450
8451 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8452 }
8453}
8454
8455static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8456 struct intel_crtc_state *pipe_config)
8457{
8458 struct drm_device *dev = crtc->base.dev;
8459 struct drm_i915_private *dev_priv = dev->dev_private;
8460 enum intel_display_power_domain pfit_domain;
8461 uint32_t tmp;
8462
8463 if (!intel_display_power_is_enabled(dev_priv,
8464 POWER_DOMAIN_PIPE(crtc->pipe)))
8465 return false;
8466
8467 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8468 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8469
8470 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8471 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8472 enum pipe trans_edp_pipe;
8473 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8474 default:
8475 WARN(1, "unknown pipe linked to edp transcoder\n");
8476 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8477 case TRANS_DDI_EDP_INPUT_A_ON:
8478 trans_edp_pipe = PIPE_A;
8479 break;
8480 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8481 trans_edp_pipe = PIPE_B;
8482 break;
8483 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8484 trans_edp_pipe = PIPE_C;
8485 break;
8486 }
8487
8488 if (trans_edp_pipe == crtc->pipe)
8489 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8490 }
8491
8492 if (!intel_display_power_is_enabled(dev_priv,
8493 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8494 return false;
8495
8496 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8497 if (!(tmp & PIPECONF_ENABLE))
8498 return false;
8499
8500 haswell_get_ddi_port_state(crtc, pipe_config);
8501
8502 intel_get_pipe_timings(crtc, pipe_config);
8503
8504 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8505 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8506 if (IS_SKYLAKE(dev))
8507 skylake_get_pfit_config(crtc, pipe_config);
8508 else
8509 ironlake_get_pfit_config(crtc, pipe_config);
8510 }
8511
8512 if (IS_HASWELL(dev))
8513 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8514 (I915_READ(IPS_CTL) & IPS_ENABLE);
8515
8516 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8517 pipe_config->pixel_multiplier =
8518 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8519 } else {
8520 pipe_config->pixel_multiplier = 1;
8521 }
8522
8523 return true;
8524}
8525
8526static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8527{
8528 struct drm_device *dev = crtc->dev;
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8531 uint32_t cntl = 0, size = 0;
8532
8533 if (base) {
8534 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8535 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8536 unsigned int stride = roundup_pow_of_two(width) * 4;
8537
8538 switch (stride) {
8539 default:
8540 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8541 width, stride);
8542 stride = 256;
8543 /* fallthrough */
8544 case 256:
8545 case 512:
8546 case 1024:
8547 case 2048:
8548 break;
8549 }
8550
8551 cntl |= CURSOR_ENABLE |
8552 CURSOR_GAMMA_ENABLE |
8553 CURSOR_FORMAT_ARGB |
8554 CURSOR_STRIDE(stride);
8555
8556 size = (height << 12) | width;
8557 }
8558
8559 if (intel_crtc->cursor_cntl != 0 &&
8560 (intel_crtc->cursor_base != base ||
8561 intel_crtc->cursor_size != size ||
8562 intel_crtc->cursor_cntl != cntl)) {
8563 /* On these chipsets we can only modify the base/size/stride
8564 * whilst the cursor is disabled.
8565 */
8566 I915_WRITE(_CURACNTR, 0);
8567 POSTING_READ(_CURACNTR);
8568 intel_crtc->cursor_cntl = 0;
8569 }
8570
8571 if (intel_crtc->cursor_base != base) {
8572 I915_WRITE(_CURABASE, base);
8573 intel_crtc->cursor_base = base;
8574 }
8575
8576 if (intel_crtc->cursor_size != size) {
8577 I915_WRITE(CURSIZE, size);
8578 intel_crtc->cursor_size = size;
8579 }
8580
8581 if (intel_crtc->cursor_cntl != cntl) {
8582 I915_WRITE(_CURACNTR, cntl);
8583 POSTING_READ(_CURACNTR);
8584 intel_crtc->cursor_cntl = cntl;
8585 }
8586}
8587
8588static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8589{
8590 struct drm_device *dev = crtc->dev;
8591 struct drm_i915_private *dev_priv = dev->dev_private;
8592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8593 int pipe = intel_crtc->pipe;
8594 uint32_t cntl;
8595
8596 cntl = 0;
8597 if (base) {
8598 cntl = MCURSOR_GAMMA_ENABLE;
8599 switch (intel_crtc->base.cursor->state->crtc_w) {
8600 case 64:
8601 cntl |= CURSOR_MODE_64_ARGB_AX;
8602 break;
8603 case 128:
8604 cntl |= CURSOR_MODE_128_ARGB_AX;
8605 break;
8606 case 256:
8607 cntl |= CURSOR_MODE_256_ARGB_AX;
8608 break;
8609 default:
8610 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8611 return;
8612 }
8613 cntl |= pipe << 28; /* Connect to correct pipe */
8614
8615 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8616 cntl |= CURSOR_PIPE_CSC_ENABLE;
8617 }
8618
8619 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8620 cntl |= CURSOR_ROTATE_180;
8621
8622 if (intel_crtc->cursor_cntl != cntl) {
8623 I915_WRITE(CURCNTR(pipe), cntl);
8624 POSTING_READ(CURCNTR(pipe));
8625 intel_crtc->cursor_cntl = cntl;
8626 }
8627
8628 /* and commit changes on next vblank */
8629 I915_WRITE(CURBASE(pipe), base);
8630 POSTING_READ(CURBASE(pipe));
8631
8632 intel_crtc->cursor_base = base;
8633}
8634
8635/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8636static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8637 bool on)
8638{
8639 struct drm_device *dev = crtc->dev;
8640 struct drm_i915_private *dev_priv = dev->dev_private;
8641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8642 int pipe = intel_crtc->pipe;
8643 int x = crtc->cursor_x;
8644 int y = crtc->cursor_y;
8645 u32 base = 0, pos = 0;
8646
8647 if (on)
8648 base = intel_crtc->cursor_addr;
8649
8650 if (x >= intel_crtc->config->pipe_src_w)
8651 base = 0;
8652
8653 if (y >= intel_crtc->config->pipe_src_h)
8654 base = 0;
8655
8656 if (x < 0) {
8657 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8658 base = 0;
8659
8660 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8661 x = -x;
8662 }
8663 pos |= x << CURSOR_X_SHIFT;
8664
8665 if (y < 0) {
8666 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8667 base = 0;
8668
8669 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8670 y = -y;
8671 }
8672 pos |= y << CURSOR_Y_SHIFT;
8673
8674 if (base == 0 && intel_crtc->cursor_base == 0)
8675 return;
8676
8677 I915_WRITE(CURPOS(pipe), pos);
8678
8679 /* ILK+ do this automagically */
8680 if (HAS_GMCH_DISPLAY(dev) &&
8681 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8682 base += (intel_crtc->base.cursor->state->crtc_h *
8683 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8684 }
8685
8686 if (IS_845G(dev) || IS_I865G(dev))
8687 i845_update_cursor(crtc, base);
8688 else
8689 i9xx_update_cursor(crtc, base);
8690}
8691
8692static bool cursor_size_ok(struct drm_device *dev,
8693 uint32_t width, uint32_t height)
8694{
8695 if (width == 0 || height == 0)
8696 return false;
8697
8698 /*
8699 * 845g/865g are special in that they are only limited by
8700 * the width of their cursors, the height is arbitrary up to
8701 * the precision of the register. Everything else requires
8702 * square cursors, limited to a few power-of-two sizes.
8703 */
8704 if (IS_845G(dev) || IS_I865G(dev)) {
8705 if ((width & 63) != 0)
8706 return false;
8707
8708 if (width > (IS_845G(dev) ? 64 : 512))
8709 return false;
8710
8711 if (height > 1023)
8712 return false;
8713 } else {
8714 switch (width | height) {
8715 case 256:
8716 case 128:
8717 if (IS_GEN2(dev))
8718 return false;
8719 case 64:
8720 break;
8721 default:
8722 return false;
8723 }
8724 }
8725
8726 return true;
8727}
8728
8729static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8730 u16 *blue, uint32_t start, uint32_t size)
8731{
8732 int end = (start + size > 256) ? 256 : start + size, i;
8733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8734
8735 for (i = start; i < end; i++) {
8736 intel_crtc->lut_r[i] = red[i] >> 8;
8737 intel_crtc->lut_g[i] = green[i] >> 8;
8738 intel_crtc->lut_b[i] = blue[i] >> 8;
8739 }
8740
8741 intel_crtc_load_lut(crtc);
8742}
8743
8744/* VESA 640x480x72Hz mode to set on the pipe */
8745static struct drm_display_mode load_detect_mode = {
8746 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8747 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8748};
8749
8750struct drm_framebuffer *
8751__intel_framebuffer_create(struct drm_device *dev,
8752 struct drm_mode_fb_cmd2 *mode_cmd,
8753 struct drm_i915_gem_object *obj)
8754{
8755 struct intel_framebuffer *intel_fb;
8756 int ret;
8757
8758 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8759 if (!intel_fb) {
8760 drm_gem_object_unreference(&obj->base);
8761 return ERR_PTR(-ENOMEM);
8762 }
8763
8764 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8765 if (ret)
8766 goto err;
8767
8768 return &intel_fb->base;
8769err:
8770 drm_gem_object_unreference(&obj->base);
8771 kfree(intel_fb);
8772
8773 return ERR_PTR(ret);
8774}
8775
8776static struct drm_framebuffer *
8777intel_framebuffer_create(struct drm_device *dev,
8778 struct drm_mode_fb_cmd2 *mode_cmd,
8779 struct drm_i915_gem_object *obj)
8780{
8781 struct drm_framebuffer *fb;
8782 int ret;
8783
8784 ret = i915_mutex_lock_interruptible(dev);
8785 if (ret)
8786 return ERR_PTR(ret);
8787 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8788 mutex_unlock(&dev->struct_mutex);
8789
8790 return fb;
8791}
8792
8793static u32
8794intel_framebuffer_pitch_for_width(int width, int bpp)
8795{
8796 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8797 return ALIGN(pitch, 64);
8798}
8799
8800static u32
8801intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8802{
8803 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8804 return PAGE_ALIGN(pitch * mode->vdisplay);
8805}
8806
8807static struct drm_framebuffer *
8808intel_framebuffer_create_for_mode(struct drm_device *dev,
8809 struct drm_display_mode *mode,
8810 int depth, int bpp)
8811{
8812 struct drm_i915_gem_object *obj;
8813 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8814
8815 obj = i915_gem_alloc_object(dev,
8816 intel_framebuffer_size_for_mode(mode, bpp));
8817 if (obj == NULL)
8818 return ERR_PTR(-ENOMEM);
8819
8820 mode_cmd.width = mode->hdisplay;
8821 mode_cmd.height = mode->vdisplay;
8822 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8823 bpp);
8824 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8825
8826 return intel_framebuffer_create(dev, &mode_cmd, obj);
8827}
8828
8829static struct drm_framebuffer *
8830mode_fits_in_fbdev(struct drm_device *dev,
8831 struct drm_display_mode *mode)
8832{
8833#ifdef CONFIG_DRM_I915_FBDEV
8834 struct drm_i915_private *dev_priv = dev->dev_private;
8835 struct drm_i915_gem_object *obj;
8836 struct drm_framebuffer *fb;
8837
8838 if (!dev_priv->fbdev)
8839 return NULL;
8840
8841 if (!dev_priv->fbdev->fb)
8842 return NULL;
8843
8844 obj = dev_priv->fbdev->fb->obj;
8845 BUG_ON(!obj);
8846
8847 fb = &dev_priv->fbdev->fb->base;
8848 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8849 fb->bits_per_pixel))
8850 return NULL;
8851
8852 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8853 return NULL;
8854
8855 return fb;
8856#else
8857 return NULL;
8858#endif
8859}
8860
8861bool intel_get_load_detect_pipe(struct drm_connector *connector,
8862 struct drm_display_mode *mode,
8863 struct intel_load_detect_pipe *old,
8864 struct drm_modeset_acquire_ctx *ctx)
8865{
8866 struct intel_crtc *intel_crtc;
8867 struct intel_encoder *intel_encoder =
8868 intel_attached_encoder(connector);
8869 struct drm_crtc *possible_crtc;
8870 struct drm_encoder *encoder = &intel_encoder->base;
8871 struct drm_crtc *crtc = NULL;
8872 struct drm_device *dev = encoder->dev;
8873 struct drm_framebuffer *fb;
8874 struct drm_mode_config *config = &dev->mode_config;
8875 int ret, i = -1;
8876
8877 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8878 connector->base.id, connector->name,
8879 encoder->base.id, encoder->name);
8880
8881retry:
8882 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8883 if (ret)
8884 goto fail_unlock;
8885
8886 /*
8887 * Algorithm gets a little messy:
8888 *
8889 * - if the connector already has an assigned crtc, use it (but make
8890 * sure it's on first)
8891 *
8892 * - try to find the first unused crtc that can drive this connector,
8893 * and use that if we find one
8894 */
8895
8896 /* See if we already have a CRTC for this connector */
8897 if (encoder->crtc) {
8898 crtc = encoder->crtc;
8899
8900 ret = drm_modeset_lock(&crtc->mutex, ctx);
8901 if (ret)
8902 goto fail_unlock;
8903 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8904 if (ret)
8905 goto fail_unlock;
8906
8907 old->dpms_mode = connector->dpms;
8908 old->load_detect_temp = false;
8909
8910 /* Make sure the crtc and connector are running */
8911 if (connector->dpms != DRM_MODE_DPMS_ON)
8912 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8913
8914 return true;
8915 }
8916
8917 /* Find an unused one (if possible) */
8918 for_each_crtc(dev, possible_crtc) {
8919 i++;
8920 if (!(encoder->possible_crtcs & (1 << i)))
8921 continue;
8922 if (possible_crtc->state->enable)
8923 continue;
8924 /* This can occur when applying the pipe A quirk on resume. */
8925 if (to_intel_crtc(possible_crtc)->new_enabled)
8926 continue;
8927
8928 crtc = possible_crtc;
8929 break;
8930 }
8931
8932 /*
8933 * If we didn't find an unused CRTC, don't use any.
8934 */
8935 if (!crtc) {
8936 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8937 goto fail_unlock;
8938 }
8939
8940 ret = drm_modeset_lock(&crtc->mutex, ctx);
8941 if (ret)
8942 goto fail_unlock;
8943 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8944 if (ret)
8945 goto fail_unlock;
8946 intel_encoder->new_crtc = to_intel_crtc(crtc);
8947 to_intel_connector(connector)->new_encoder = intel_encoder;
8948
8949 intel_crtc = to_intel_crtc(crtc);
8950 intel_crtc->new_enabled = true;
8951 intel_crtc->new_config = intel_crtc->config;
8952 old->dpms_mode = connector->dpms;
8953 old->load_detect_temp = true;
8954 old->release_fb = NULL;
8955
8956 if (!mode)
8957 mode = &load_detect_mode;
8958
8959 /* We need a framebuffer large enough to accommodate all accesses
8960 * that the plane may generate whilst we perform load detection.
8961 * We can not rely on the fbcon either being present (we get called
8962 * during its initialisation to detect all boot displays, or it may
8963 * not even exist) or that it is large enough to satisfy the
8964 * requested mode.
8965 */
8966 fb = mode_fits_in_fbdev(dev, mode);
8967 if (fb == NULL) {
8968 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8969 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8970 old->release_fb = fb;
8971 } else
8972 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8973 if (IS_ERR(fb)) {
8974 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8975 goto fail;
8976 }
8977
8978 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8979 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8980 if (old->release_fb)
8981 old->release_fb->funcs->destroy(old->release_fb);
8982 goto fail;
8983 }
8984 crtc->primary->crtc = crtc;
8985
8986 /* let the connector get through one full cycle before testing */
8987 intel_wait_for_vblank(dev, intel_crtc->pipe);
8988 return true;
8989
8990 fail:
8991 intel_crtc->new_enabled = crtc->state->enable;
8992 if (intel_crtc->new_enabled)
8993 intel_crtc->new_config = intel_crtc->config;
8994 else
8995 intel_crtc->new_config = NULL;
8996fail_unlock:
8997 if (ret == -EDEADLK) {
8998 drm_modeset_backoff(ctx);
8999 goto retry;
9000 }
9001
9002 return false;
9003}
9004
9005void intel_release_load_detect_pipe(struct drm_connector *connector,
9006 struct intel_load_detect_pipe *old)
9007{
9008 struct intel_encoder *intel_encoder =
9009 intel_attached_encoder(connector);
9010 struct drm_encoder *encoder = &intel_encoder->base;
9011 struct drm_crtc *crtc = encoder->crtc;
9012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9013
9014 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9015 connector->base.id, connector->name,
9016 encoder->base.id, encoder->name);
9017
9018 if (old->load_detect_temp) {
9019 to_intel_connector(connector)->new_encoder = NULL;
9020 intel_encoder->new_crtc = NULL;
9021 intel_crtc->new_enabled = false;
9022 intel_crtc->new_config = NULL;
9023 intel_set_mode(crtc, NULL, 0, 0, NULL);
9024
9025 if (old->release_fb) {
9026 drm_framebuffer_unregister_private(old->release_fb);
9027 drm_framebuffer_unreference(old->release_fb);
9028 }
9029
9030 return;
9031 }
9032
9033 /* Switch crtc and encoder back off if necessary */
9034 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9035 connector->funcs->dpms(connector, old->dpms_mode);
9036}
9037
9038static int i9xx_pll_refclk(struct drm_device *dev,
9039 const struct intel_crtc_state *pipe_config)
9040{
9041 struct drm_i915_private *dev_priv = dev->dev_private;
9042 u32 dpll = pipe_config->dpll_hw_state.dpll;
9043
9044 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9045 return dev_priv->vbt.lvds_ssc_freq;
9046 else if (HAS_PCH_SPLIT(dev))
9047 return 120000;
9048 else if (!IS_GEN2(dev))
9049 return 96000;
9050 else
9051 return 48000;
9052}
9053
9054/* Returns the clock of the currently programmed mode of the given pipe. */
9055static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9056 struct intel_crtc_state *pipe_config)
9057{
9058 struct drm_device *dev = crtc->base.dev;
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060 int pipe = pipe_config->cpu_transcoder;
9061 u32 dpll = pipe_config->dpll_hw_state.dpll;
9062 u32 fp;
9063 intel_clock_t clock;
9064 int refclk = i9xx_pll_refclk(dev, pipe_config);
9065
9066 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9067 fp = pipe_config->dpll_hw_state.fp0;
9068 else
9069 fp = pipe_config->dpll_hw_state.fp1;
9070
9071 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9072 if (IS_PINEVIEW(dev)) {
9073 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9074 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9075 } else {
9076 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9077 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9078 }
9079
9080 if (!IS_GEN2(dev)) {
9081 if (IS_PINEVIEW(dev))
9082 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9083 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9084 else
9085 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9086 DPLL_FPA01_P1_POST_DIV_SHIFT);
9087
9088 switch (dpll & DPLL_MODE_MASK) {
9089 case DPLLB_MODE_DAC_SERIAL:
9090 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9091 5 : 10;
9092 break;
9093 case DPLLB_MODE_LVDS:
9094 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9095 7 : 14;
9096 break;
9097 default:
9098 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9099 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9100 return;
9101 }
9102
9103 if (IS_PINEVIEW(dev))
9104 pineview_clock(refclk, &clock);
9105 else
9106 i9xx_clock(refclk, &clock);
9107 } else {
9108 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9109 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9110
9111 if (is_lvds) {
9112 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9113 DPLL_FPA01_P1_POST_DIV_SHIFT);
9114
9115 if (lvds & LVDS_CLKB_POWER_UP)
9116 clock.p2 = 7;
9117 else
9118 clock.p2 = 14;
9119 } else {
9120 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9121 clock.p1 = 2;
9122 else {
9123 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9124 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9125 }
9126 if (dpll & PLL_P2_DIVIDE_BY_4)
9127 clock.p2 = 4;
9128 else
9129 clock.p2 = 2;
9130 }
9131
9132 i9xx_clock(refclk, &clock);
9133 }
9134
9135 /*
9136 * This value includes pixel_multiplier. We will use
9137 * port_clock to compute adjusted_mode.crtc_clock in the
9138 * encoder's get_config() function.
9139 */
9140 pipe_config->port_clock = clock.dot;
9141}
9142
9143int intel_dotclock_calculate(int link_freq,
9144 const struct intel_link_m_n *m_n)
9145{
9146 /*
9147 * The calculation for the data clock is:
9148 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9149 * But we want to avoid losing precison if possible, so:
9150 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9151 *
9152 * and the link clock is simpler:
9153 * link_clock = (m * link_clock) / n
9154 */
9155
9156 if (!m_n->link_n)
9157 return 0;
9158
9159 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9160}
9161
9162static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9163 struct intel_crtc_state *pipe_config)
9164{
9165 struct drm_device *dev = crtc->base.dev;
9166
9167 /* read out port_clock from the DPLL */
9168 i9xx_crtc_clock_get(crtc, pipe_config);
9169
9170 /*
9171 * This value does not include pixel_multiplier.
9172 * We will check that port_clock and adjusted_mode.crtc_clock
9173 * agree once we know their relationship in the encoder's
9174 * get_config() function.
9175 */
9176 pipe_config->base.adjusted_mode.crtc_clock =
9177 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9178 &pipe_config->fdi_m_n);
9179}
9180
9181/** Returns the currently programmed mode of the given pipe. */
9182struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9183 struct drm_crtc *crtc)
9184{
9185 struct drm_i915_private *dev_priv = dev->dev_private;
9186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9187 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9188 struct drm_display_mode *mode;
9189 struct intel_crtc_state pipe_config;
9190 int htot = I915_READ(HTOTAL(cpu_transcoder));
9191 int hsync = I915_READ(HSYNC(cpu_transcoder));
9192 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9193 int vsync = I915_READ(VSYNC(cpu_transcoder));
9194 enum pipe pipe = intel_crtc->pipe;
9195
9196 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9197 if (!mode)
9198 return NULL;
9199
9200 /*
9201 * Construct a pipe_config sufficient for getting the clock info
9202 * back out of crtc_clock_get.
9203 *
9204 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9205 * to use a real value here instead.
9206 */
9207 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9208 pipe_config.pixel_multiplier = 1;
9209 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9210 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9211 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9212 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9213
9214 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9215 mode->hdisplay = (htot & 0xffff) + 1;
9216 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9217 mode->hsync_start = (hsync & 0xffff) + 1;
9218 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9219 mode->vdisplay = (vtot & 0xffff) + 1;
9220 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9221 mode->vsync_start = (vsync & 0xffff) + 1;
9222 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9223
9224 drm_mode_set_name(mode);
9225
9226 return mode;
9227}
9228
9229static void intel_decrease_pllclock(struct drm_crtc *crtc)
9230{
9231 struct drm_device *dev = crtc->dev;
9232 struct drm_i915_private *dev_priv = dev->dev_private;
9233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9234
9235 if (!HAS_GMCH_DISPLAY(dev))
9236 return;
9237
9238 if (!dev_priv->lvds_downclock_avail)
9239 return;
9240
9241 /*
9242 * Since this is called by a timer, we should never get here in
9243 * the manual case.
9244 */
9245 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9246 int pipe = intel_crtc->pipe;
9247 int dpll_reg = DPLL(pipe);
9248 int dpll;
9249
9250 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9251
9252 assert_panel_unlocked(dev_priv, pipe);
9253
9254 dpll = I915_READ(dpll_reg);
9255 dpll |= DISPLAY_RATE_SELECT_FPA1;
9256 I915_WRITE(dpll_reg, dpll);
9257 intel_wait_for_vblank(dev, pipe);
9258 dpll = I915_READ(dpll_reg);
9259 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9260 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9261 }
9262
9263}
9264
9265void intel_mark_busy(struct drm_device *dev)
9266{
9267 struct drm_i915_private *dev_priv = dev->dev_private;
9268
9269 if (dev_priv->mm.busy)
9270 return;
9271
9272 intel_runtime_pm_get(dev_priv);
9273 i915_update_gfx_val(dev_priv);
9274 if (INTEL_INFO(dev)->gen >= 6)
9275 gen6_rps_busy(dev_priv);
9276 dev_priv->mm.busy = true;
9277}
9278
9279void intel_mark_idle(struct drm_device *dev)
9280{
9281 struct drm_i915_private *dev_priv = dev->dev_private;
9282 struct drm_crtc *crtc;
9283
9284 if (!dev_priv->mm.busy)
9285 return;
9286
9287 dev_priv->mm.busy = false;
9288
9289 if (!i915.powersave)
9290 goto out;
9291
9292 for_each_crtc(dev, crtc) {
9293 if (!crtc->primary->fb)
9294 continue;
9295
9296 intel_decrease_pllclock(crtc);
9297 }
9298
9299 if (INTEL_INFO(dev)->gen >= 6)
9300 gen6_rps_idle(dev->dev_private);
9301
9302out:
9303 intel_runtime_pm_put(dev_priv);
9304}
9305
9306static void intel_crtc_set_state(struct intel_crtc *crtc,
9307 struct intel_crtc_state *crtc_state)
9308{
9309 kfree(crtc->config);
9310 crtc->config = crtc_state;
9311 crtc->base.state = &crtc_state->base;
9312}
9313
9314static void intel_crtc_destroy(struct drm_crtc *crtc)
9315{
9316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9317 struct drm_device *dev = crtc->dev;
9318 struct intel_unpin_work *work;
9319
9320 spin_lock_irq(&dev->event_lock);
9321 work = intel_crtc->unpin_work;
9322 intel_crtc->unpin_work = NULL;
9323 spin_unlock_irq(&dev->event_lock);
9324
9325 if (work) {
9326 cancel_work_sync(&work->work);
9327 kfree(work);
9328 }
9329
9330 intel_crtc_set_state(intel_crtc, NULL);
9331 drm_crtc_cleanup(crtc);
9332
9333 kfree(intel_crtc);
9334}
9335
9336static void intel_unpin_work_fn(struct work_struct *__work)
9337{
9338 struct intel_unpin_work *work =
9339 container_of(__work, struct intel_unpin_work, work);
9340 struct drm_device *dev = work->crtc->dev;
9341 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9342
9343 mutex_lock(&dev->struct_mutex);
9344 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9345 drm_gem_object_unreference(&work->pending_flip_obj->base);
9346
9347 intel_fbc_update(dev);
9348
9349 if (work->flip_queued_req)
9350 i915_gem_request_assign(&work->flip_queued_req, NULL);
9351 mutex_unlock(&dev->struct_mutex);
9352
9353 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9354 drm_framebuffer_unreference(work->old_fb);
9355
9356 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9357 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9358
9359 kfree(work);
9360}
9361
9362static void do_intel_finish_page_flip(struct drm_device *dev,
9363 struct drm_crtc *crtc)
9364{
9365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9366 struct intel_unpin_work *work;
9367 unsigned long flags;
9368
9369 /* Ignore early vblank irqs */
9370 if (intel_crtc == NULL)
9371 return;
9372
9373 /*
9374 * This is called both by irq handlers and the reset code (to complete
9375 * lost pageflips) so needs the full irqsave spinlocks.
9376 */
9377 spin_lock_irqsave(&dev->event_lock, flags);
9378 work = intel_crtc->unpin_work;
9379
9380 /* Ensure we don't miss a work->pending update ... */
9381 smp_rmb();
9382
9383 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9384 spin_unlock_irqrestore(&dev->event_lock, flags);
9385 return;
9386 }
9387
9388 page_flip_completed(intel_crtc);
9389
9390 spin_unlock_irqrestore(&dev->event_lock, flags);
9391}
9392
9393void intel_finish_page_flip(struct drm_device *dev, int pipe)
9394{
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9396 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9397
9398 do_intel_finish_page_flip(dev, crtc);
9399}
9400
9401void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9402{
9403 struct drm_i915_private *dev_priv = dev->dev_private;
9404 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9405
9406 do_intel_finish_page_flip(dev, crtc);
9407}
9408
9409/* Is 'a' after or equal to 'b'? */
9410static bool g4x_flip_count_after_eq(u32 a, u32 b)
9411{
9412 return !((a - b) & 0x80000000);
9413}
9414
9415static bool page_flip_finished(struct intel_crtc *crtc)
9416{
9417 struct drm_device *dev = crtc->base.dev;
9418 struct drm_i915_private *dev_priv = dev->dev_private;
9419
9420 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9421 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9422 return true;
9423
9424 /*
9425 * The relevant registers doen't exist on pre-ctg.
9426 * As the flip done interrupt doesn't trigger for mmio
9427 * flips on gmch platforms, a flip count check isn't
9428 * really needed there. But since ctg has the registers,
9429 * include it in the check anyway.
9430 */
9431 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9432 return true;
9433
9434 /*
9435 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9436 * used the same base address. In that case the mmio flip might
9437 * have completed, but the CS hasn't even executed the flip yet.
9438 *
9439 * A flip count check isn't enough as the CS might have updated
9440 * the base address just after start of vblank, but before we
9441 * managed to process the interrupt. This means we'd complete the
9442 * CS flip too soon.
9443 *
9444 * Combining both checks should get us a good enough result. It may
9445 * still happen that the CS flip has been executed, but has not
9446 * yet actually completed. But in case the base address is the same
9447 * anyway, we don't really care.
9448 */
9449 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9450 crtc->unpin_work->gtt_offset &&
9451 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9452 crtc->unpin_work->flip_count);
9453}
9454
9455void intel_prepare_page_flip(struct drm_device *dev, int plane)
9456{
9457 struct drm_i915_private *dev_priv = dev->dev_private;
9458 struct intel_crtc *intel_crtc =
9459 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9460 unsigned long flags;
9461
9462
9463 /*
9464 * This is called both by irq handlers and the reset code (to complete
9465 * lost pageflips) so needs the full irqsave spinlocks.
9466 *
9467 * NB: An MMIO update of the plane base pointer will also
9468 * generate a page-flip completion irq, i.e. every modeset
9469 * is also accompanied by a spurious intel_prepare_page_flip().
9470 */
9471 spin_lock_irqsave(&dev->event_lock, flags);
9472 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9473 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9474 spin_unlock_irqrestore(&dev->event_lock, flags);
9475}
9476
9477static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9478{
9479 /* Ensure that the work item is consistent when activating it ... */
9480 smp_wmb();
9481 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9482 /* and that it is marked active as soon as the irq could fire. */
9483 smp_wmb();
9484}
9485
9486static int intel_gen2_queue_flip(struct drm_device *dev,
9487 struct drm_crtc *crtc,
9488 struct drm_framebuffer *fb,
9489 struct drm_i915_gem_object *obj,
9490 struct intel_engine_cs *ring,
9491 uint32_t flags)
9492{
9493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9494 u32 flip_mask;
9495 int ret;
9496
9497 ret = intel_ring_begin(ring, 6);
9498 if (ret)
9499 return ret;
9500
9501 /* Can't queue multiple flips, so wait for the previous
9502 * one to finish before executing the next.
9503 */
9504 if (intel_crtc->plane)
9505 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9506 else
9507 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9508 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9509 intel_ring_emit(ring, MI_NOOP);
9510 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9511 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9512 intel_ring_emit(ring, fb->pitches[0]);
9513 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9514 intel_ring_emit(ring, 0); /* aux display base address, unused */
9515
9516 intel_mark_page_flip_active(intel_crtc);
9517 __intel_ring_advance(ring);
9518 return 0;
9519}
9520
9521static int intel_gen3_queue_flip(struct drm_device *dev,
9522 struct drm_crtc *crtc,
9523 struct drm_framebuffer *fb,
9524 struct drm_i915_gem_object *obj,
9525 struct intel_engine_cs *ring,
9526 uint32_t flags)
9527{
9528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9529 u32 flip_mask;
9530 int ret;
9531
9532 ret = intel_ring_begin(ring, 6);
9533 if (ret)
9534 return ret;
9535
9536 if (intel_crtc->plane)
9537 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9538 else
9539 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9540 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9541 intel_ring_emit(ring, MI_NOOP);
9542 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9543 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9544 intel_ring_emit(ring, fb->pitches[0]);
9545 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9546 intel_ring_emit(ring, MI_NOOP);
9547
9548 intel_mark_page_flip_active(intel_crtc);
9549 __intel_ring_advance(ring);
9550 return 0;
9551}
9552
9553static int intel_gen4_queue_flip(struct drm_device *dev,
9554 struct drm_crtc *crtc,
9555 struct drm_framebuffer *fb,
9556 struct drm_i915_gem_object *obj,
9557 struct intel_engine_cs *ring,
9558 uint32_t flags)
9559{
9560 struct drm_i915_private *dev_priv = dev->dev_private;
9561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9562 uint32_t pf, pipesrc;
9563 int ret;
9564
9565 ret = intel_ring_begin(ring, 4);
9566 if (ret)
9567 return ret;
9568
9569 /* i965+ uses the linear or tiled offsets from the
9570 * Display Registers (which do not change across a page-flip)
9571 * so we need only reprogram the base address.
9572 */
9573 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9574 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9575 intel_ring_emit(ring, fb->pitches[0]);
9576 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9577 obj->tiling_mode);
9578
9579 /* XXX Enabling the panel-fitter across page-flip is so far
9580 * untested on non-native modes, so ignore it for now.
9581 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9582 */
9583 pf = 0;
9584 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9585 intel_ring_emit(ring, pf | pipesrc);
9586
9587 intel_mark_page_flip_active(intel_crtc);
9588 __intel_ring_advance(ring);
9589 return 0;
9590}
9591
9592static int intel_gen6_queue_flip(struct drm_device *dev,
9593 struct drm_crtc *crtc,
9594 struct drm_framebuffer *fb,
9595 struct drm_i915_gem_object *obj,
9596 struct intel_engine_cs *ring,
9597 uint32_t flags)
9598{
9599 struct drm_i915_private *dev_priv = dev->dev_private;
9600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9601 uint32_t pf, pipesrc;
9602 int ret;
9603
9604 ret = intel_ring_begin(ring, 4);
9605 if (ret)
9606 return ret;
9607
9608 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9609 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9610 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9611 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9612
9613 /* Contrary to the suggestions in the documentation,
9614 * "Enable Panel Fitter" does not seem to be required when page
9615 * flipping with a non-native mode, and worse causes a normal
9616 * modeset to fail.
9617 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9618 */
9619 pf = 0;
9620 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9621 intel_ring_emit(ring, pf | pipesrc);
9622
9623 intel_mark_page_flip_active(intel_crtc);
9624 __intel_ring_advance(ring);
9625 return 0;
9626}
9627
9628static int intel_gen7_queue_flip(struct drm_device *dev,
9629 struct drm_crtc *crtc,
9630 struct drm_framebuffer *fb,
9631 struct drm_i915_gem_object *obj,
9632 struct intel_engine_cs *ring,
9633 uint32_t flags)
9634{
9635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9636 uint32_t plane_bit = 0;
9637 int len, ret;
9638
9639 switch (intel_crtc->plane) {
9640 case PLANE_A:
9641 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9642 break;
9643 case PLANE_B:
9644 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9645 break;
9646 case PLANE_C:
9647 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9648 break;
9649 default:
9650 WARN_ONCE(1, "unknown plane in flip command\n");
9651 return -ENODEV;
9652 }
9653
9654 len = 4;
9655 if (ring->id == RCS) {
9656 len += 6;
9657 /*
9658 * On Gen 8, SRM is now taking an extra dword to accommodate
9659 * 48bits addresses, and we need a NOOP for the batch size to
9660 * stay even.
9661 */
9662 if (IS_GEN8(dev))
9663 len += 2;
9664 }
9665
9666 /*
9667 * BSpec MI_DISPLAY_FLIP for IVB:
9668 * "The full packet must be contained within the same cache line."
9669 *
9670 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9671 * cacheline, if we ever start emitting more commands before
9672 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9673 * then do the cacheline alignment, and finally emit the
9674 * MI_DISPLAY_FLIP.
9675 */
9676 ret = intel_ring_cacheline_align(ring);
9677 if (ret)
9678 return ret;
9679
9680 ret = intel_ring_begin(ring, len);
9681 if (ret)
9682 return ret;
9683
9684 /* Unmask the flip-done completion message. Note that the bspec says that
9685 * we should do this for both the BCS and RCS, and that we must not unmask
9686 * more than one flip event at any time (or ensure that one flip message
9687 * can be sent by waiting for flip-done prior to queueing new flips).
9688 * Experimentation says that BCS works despite DERRMR masking all
9689 * flip-done completion events and that unmasking all planes at once
9690 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9691 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9692 */
9693 if (ring->id == RCS) {
9694 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9695 intel_ring_emit(ring, DERRMR);
9696 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9697 DERRMR_PIPEB_PRI_FLIP_DONE |
9698 DERRMR_PIPEC_PRI_FLIP_DONE));
9699 if (IS_GEN8(dev))
9700 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9701 MI_SRM_LRM_GLOBAL_GTT);
9702 else
9703 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9704 MI_SRM_LRM_GLOBAL_GTT);
9705 intel_ring_emit(ring, DERRMR);
9706 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9707 if (IS_GEN8(dev)) {
9708 intel_ring_emit(ring, 0);
9709 intel_ring_emit(ring, MI_NOOP);
9710 }
9711 }
9712
9713 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9714 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9715 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9716 intel_ring_emit(ring, (MI_NOOP));
9717
9718 intel_mark_page_flip_active(intel_crtc);
9719 __intel_ring_advance(ring);
9720 return 0;
9721}
9722
9723static bool use_mmio_flip(struct intel_engine_cs *ring,
9724 struct drm_i915_gem_object *obj)
9725{
9726 /*
9727 * This is not being used for older platforms, because
9728 * non-availability of flip done interrupt forces us to use
9729 * CS flips. Older platforms derive flip done using some clever
9730 * tricks involving the flip_pending status bits and vblank irqs.
9731 * So using MMIO flips there would disrupt this mechanism.
9732 */
9733
9734 if (ring == NULL)
9735 return true;
9736
9737 if (INTEL_INFO(ring->dev)->gen < 5)
9738 return false;
9739
9740 if (i915.use_mmio_flip < 0)
9741 return false;
9742 else if (i915.use_mmio_flip > 0)
9743 return true;
9744 else if (i915.enable_execlists)
9745 return true;
9746 else
9747 return ring != i915_gem_request_get_ring(obj->last_read_req);
9748}
9749
9750static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9751{
9752 struct drm_device *dev = intel_crtc->base.dev;
9753 struct drm_i915_private *dev_priv = dev->dev_private;
9754 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9755 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9756 struct drm_i915_gem_object *obj = intel_fb->obj;
9757 const enum pipe pipe = intel_crtc->pipe;
9758 u32 ctl, stride;
9759
9760 ctl = I915_READ(PLANE_CTL(pipe, 0));
9761 ctl &= ~PLANE_CTL_TILED_MASK;
9762 if (obj->tiling_mode == I915_TILING_X)
9763 ctl |= PLANE_CTL_TILED_X;
9764
9765 /*
9766 * The stride is either expressed as a multiple of 64 bytes chunks for
9767 * linear buffers or in number of tiles for tiled buffers.
9768 */
9769 stride = fb->pitches[0] >> 6;
9770 if (obj->tiling_mode == I915_TILING_X)
9771 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9772
9773 /*
9774 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9775 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9776 */
9777 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9778 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9779
9780 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9781 POSTING_READ(PLANE_SURF(pipe, 0));
9782}
9783
9784static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9785{
9786 struct drm_device *dev = intel_crtc->base.dev;
9787 struct drm_i915_private *dev_priv = dev->dev_private;
9788 struct intel_framebuffer *intel_fb =
9789 to_intel_framebuffer(intel_crtc->base.primary->fb);
9790 struct drm_i915_gem_object *obj = intel_fb->obj;
9791 u32 dspcntr;
9792 u32 reg;
9793
9794 reg = DSPCNTR(intel_crtc->plane);
9795 dspcntr = I915_READ(reg);
9796
9797 if (obj->tiling_mode != I915_TILING_NONE)
9798 dspcntr |= DISPPLANE_TILED;
9799 else
9800 dspcntr &= ~DISPPLANE_TILED;
9801
9802 I915_WRITE(reg, dspcntr);
9803
9804 I915_WRITE(DSPSURF(intel_crtc->plane),
9805 intel_crtc->unpin_work->gtt_offset);
9806 POSTING_READ(DSPSURF(intel_crtc->plane));
9807
9808}
9809
9810/*
9811 * XXX: This is the temporary way to update the plane registers until we get
9812 * around to using the usual plane update functions for MMIO flips
9813 */
9814static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9815{
9816 struct drm_device *dev = intel_crtc->base.dev;
9817 bool atomic_update;
9818 u32 start_vbl_count;
9819
9820 intel_mark_page_flip_active(intel_crtc);
9821
9822 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9823
9824 if (INTEL_INFO(dev)->gen >= 9)
9825 skl_do_mmio_flip(intel_crtc);
9826 else
9827 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9828 ilk_do_mmio_flip(intel_crtc);
9829
9830 if (atomic_update)
9831 intel_pipe_update_end(intel_crtc, start_vbl_count);
9832}
9833
9834static void intel_mmio_flip_work_func(struct work_struct *work)
9835{
9836 struct intel_crtc *crtc =
9837 container_of(work, struct intel_crtc, mmio_flip.work);
9838 struct intel_mmio_flip *mmio_flip;
9839
9840 mmio_flip = &crtc->mmio_flip;
9841 if (mmio_flip->req)
9842 WARN_ON(__i915_wait_request(mmio_flip->req,
9843 crtc->reset_counter,
9844 false, NULL, NULL) != 0);
9845
9846 intel_do_mmio_flip(crtc);
9847 if (mmio_flip->req) {
9848 mutex_lock(&crtc->base.dev->struct_mutex);
9849 i915_gem_request_assign(&mmio_flip->req, NULL);
9850 mutex_unlock(&crtc->base.dev->struct_mutex);
9851 }
9852}
9853
9854static int intel_queue_mmio_flip(struct drm_device *dev,
9855 struct drm_crtc *crtc,
9856 struct drm_framebuffer *fb,
9857 struct drm_i915_gem_object *obj,
9858 struct intel_engine_cs *ring,
9859 uint32_t flags)
9860{
9861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9862
9863 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9864 obj->last_write_req);
9865
9866 schedule_work(&intel_crtc->mmio_flip.work);
9867
9868 return 0;
9869}
9870
9871static int intel_default_queue_flip(struct drm_device *dev,
9872 struct drm_crtc *crtc,
9873 struct drm_framebuffer *fb,
9874 struct drm_i915_gem_object *obj,
9875 struct intel_engine_cs *ring,
9876 uint32_t flags)
9877{
9878 return -ENODEV;
9879}
9880
9881static bool __intel_pageflip_stall_check(struct drm_device *dev,
9882 struct drm_crtc *crtc)
9883{
9884 struct drm_i915_private *dev_priv = dev->dev_private;
9885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9886 struct intel_unpin_work *work = intel_crtc->unpin_work;
9887 u32 addr;
9888
9889 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9890 return true;
9891
9892 if (!work->enable_stall_check)
9893 return false;
9894
9895 if (work->flip_ready_vblank == 0) {
9896 if (work->flip_queued_req &&
9897 !i915_gem_request_completed(work->flip_queued_req, true))
9898 return false;
9899
9900 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9901 }
9902
9903 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9904 return false;
9905
9906 /* Potential stall - if we see that the flip has happened,
9907 * assume a missed interrupt. */
9908 if (INTEL_INFO(dev)->gen >= 4)
9909 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9910 else
9911 addr = I915_READ(DSPADDR(intel_crtc->plane));
9912
9913 /* There is a potential issue here with a false positive after a flip
9914 * to the same address. We could address this by checking for a
9915 * non-incrementing frame counter.
9916 */
9917 return addr == work->gtt_offset;
9918}
9919
9920void intel_check_page_flip(struct drm_device *dev, int pipe)
9921{
9922 struct drm_i915_private *dev_priv = dev->dev_private;
9923 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9925
9926 WARN_ON(!in_interrupt());
9927
9928 if (crtc == NULL)
9929 return;
9930
9931 spin_lock(&dev->event_lock);
9932 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9933 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9934 intel_crtc->unpin_work->flip_queued_vblank,
9935 drm_vblank_count(dev, pipe));
9936 page_flip_completed(intel_crtc);
9937 }
9938 spin_unlock(&dev->event_lock);
9939}
9940
9941static int intel_crtc_page_flip(struct drm_crtc *crtc,
9942 struct drm_framebuffer *fb,
9943 struct drm_pending_vblank_event *event,
9944 uint32_t page_flip_flags)
9945{
9946 struct drm_device *dev = crtc->dev;
9947 struct drm_i915_private *dev_priv = dev->dev_private;
9948 struct drm_framebuffer *old_fb = crtc->primary->fb;
9949 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9951 struct drm_plane *primary = crtc->primary;
9952 enum pipe pipe = intel_crtc->pipe;
9953 struct intel_unpin_work *work;
9954 struct intel_engine_cs *ring;
9955 int ret;
9956
9957 /*
9958 * drm_mode_page_flip_ioctl() should already catch this, but double
9959 * check to be safe. In the future we may enable pageflipping from
9960 * a disabled primary plane.
9961 */
9962 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9963 return -EBUSY;
9964
9965 /* Can't change pixel format via MI display flips. */
9966 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9967 return -EINVAL;
9968
9969 /*
9970 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9971 * Note that pitch changes could also affect these register.
9972 */
9973 if (INTEL_INFO(dev)->gen > 3 &&
9974 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9975 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9976 return -EINVAL;
9977
9978 if (i915_terminally_wedged(&dev_priv->gpu_error))
9979 goto out_hang;
9980
9981 work = kzalloc(sizeof(*work), GFP_KERNEL);
9982 if (work == NULL)
9983 return -ENOMEM;
9984
9985 work->event = event;
9986 work->crtc = crtc;
9987 work->old_fb = old_fb;
9988 INIT_WORK(&work->work, intel_unpin_work_fn);
9989
9990 ret = drm_crtc_vblank_get(crtc);
9991 if (ret)
9992 goto free_work;
9993
9994 /* We borrow the event spin lock for protecting unpin_work */
9995 spin_lock_irq(&dev->event_lock);
9996 if (intel_crtc->unpin_work) {
9997 /* Before declaring the flip queue wedged, check if
9998 * the hardware completed the operation behind our backs.
9999 */
10000 if (__intel_pageflip_stall_check(dev, crtc)) {
10001 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10002 page_flip_completed(intel_crtc);
10003 } else {
10004 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10005 spin_unlock_irq(&dev->event_lock);
10006
10007 drm_crtc_vblank_put(crtc);
10008 kfree(work);
10009 return -EBUSY;
10010 }
10011 }
10012 intel_crtc->unpin_work = work;
10013 spin_unlock_irq(&dev->event_lock);
10014
10015 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10016 flush_workqueue(dev_priv->wq);
10017
10018 /* Reference the objects for the scheduled work. */
10019 drm_framebuffer_reference(work->old_fb);
10020 drm_gem_object_reference(&obj->base);
10021
10022 crtc->primary->fb = fb;
10023 update_state_fb(crtc->primary);
10024
10025 work->pending_flip_obj = obj;
10026
10027 ret = i915_mutex_lock_interruptible(dev);
10028 if (ret)
10029 goto cleanup;
10030
10031 atomic_inc(&intel_crtc->unpin_work_count);
10032 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10033
10034 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10035 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10036
10037 if (IS_VALLEYVIEW(dev)) {
10038 ring = &dev_priv->ring[BCS];
10039 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10040 /* vlv: DISPLAY_FLIP fails to change tiling */
10041 ring = NULL;
10042 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10043 ring = &dev_priv->ring[BCS];
10044 } else if (INTEL_INFO(dev)->gen >= 7) {
10045 ring = i915_gem_request_get_ring(obj->last_read_req);
10046 if (ring == NULL || ring->id != RCS)
10047 ring = &dev_priv->ring[BCS];
10048 } else {
10049 ring = &dev_priv->ring[RCS];
10050 }
10051
10052 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10053 crtc->primary->state, ring);
10054 if (ret)
10055 goto cleanup_pending;
10056
10057 work->gtt_offset =
10058 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10059
10060 if (use_mmio_flip(ring, obj)) {
10061 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10062 page_flip_flags);
10063 if (ret)
10064 goto cleanup_unpin;
10065
10066 i915_gem_request_assign(&work->flip_queued_req,
10067 obj->last_write_req);
10068 } else {
10069 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10070 page_flip_flags);
10071 if (ret)
10072 goto cleanup_unpin;
10073
10074 i915_gem_request_assign(&work->flip_queued_req,
10075 intel_ring_get_request(ring));
10076 }
10077
10078 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10079 work->enable_stall_check = true;
10080
10081 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10082 INTEL_FRONTBUFFER_PRIMARY(pipe));
10083
10084 intel_fbc_disable(dev);
10085 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10086 mutex_unlock(&dev->struct_mutex);
10087
10088 trace_i915_flip_request(intel_crtc->plane, obj);
10089
10090 return 0;
10091
10092cleanup_unpin:
10093 intel_unpin_fb_obj(fb, crtc->primary->state);
10094cleanup_pending:
10095 atomic_dec(&intel_crtc->unpin_work_count);
10096 mutex_unlock(&dev->struct_mutex);
10097cleanup:
10098 crtc->primary->fb = old_fb;
10099 update_state_fb(crtc->primary);
10100
10101 drm_gem_object_unreference_unlocked(&obj->base);
10102 drm_framebuffer_unreference(work->old_fb);
10103
10104 spin_lock_irq(&dev->event_lock);
10105 intel_crtc->unpin_work = NULL;
10106 spin_unlock_irq(&dev->event_lock);
10107
10108 drm_crtc_vblank_put(crtc);
10109free_work:
10110 kfree(work);
10111
10112 if (ret == -EIO) {
10113out_hang:
10114 ret = intel_plane_restore(primary);
10115 if (ret == 0 && event) {
10116 spin_lock_irq(&dev->event_lock);
10117 drm_send_vblank_event(dev, pipe, event);
10118 spin_unlock_irq(&dev->event_lock);
10119 }
10120 }
10121 return ret;
10122}
10123
10124static struct drm_crtc_helper_funcs intel_helper_funcs = {
10125 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10126 .load_lut = intel_crtc_load_lut,
10127 .atomic_begin = intel_begin_crtc_commit,
10128 .atomic_flush = intel_finish_crtc_commit,
10129};
10130
10131/**
10132 * intel_modeset_update_staged_output_state
10133 *
10134 * Updates the staged output configuration state, e.g. after we've read out the
10135 * current hw state.
10136 */
10137static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10138{
10139 struct intel_crtc *crtc;
10140 struct intel_encoder *encoder;
10141 struct intel_connector *connector;
10142
10143 for_each_intel_connector(dev, connector) {
10144 connector->new_encoder =
10145 to_intel_encoder(connector->base.encoder);
10146 }
10147
10148 for_each_intel_encoder(dev, encoder) {
10149 encoder->new_crtc =
10150 to_intel_crtc(encoder->base.crtc);
10151 }
10152
10153 for_each_intel_crtc(dev, crtc) {
10154 crtc->new_enabled = crtc->base.state->enable;
10155
10156 if (crtc->new_enabled)
10157 crtc->new_config = crtc->config;
10158 else
10159 crtc->new_config = NULL;
10160 }
10161}
10162
10163/**
10164 * intel_modeset_commit_output_state
10165 *
10166 * This function copies the stage display pipe configuration to the real one.
10167 */
10168static void intel_modeset_commit_output_state(struct drm_device *dev)
10169{
10170 struct intel_crtc *crtc;
10171 struct intel_encoder *encoder;
10172 struct intel_connector *connector;
10173
10174 for_each_intel_connector(dev, connector) {
10175 connector->base.encoder = &connector->new_encoder->base;
10176 }
10177
10178 for_each_intel_encoder(dev, encoder) {
10179 encoder->base.crtc = &encoder->new_crtc->base;
10180 }
10181
10182 for_each_intel_crtc(dev, crtc) {
10183 crtc->base.state->enable = crtc->new_enabled;
10184 crtc->base.enabled = crtc->new_enabled;
10185 }
10186}
10187
10188static void
10189connected_sink_compute_bpp(struct intel_connector *connector,
10190 struct intel_crtc_state *pipe_config)
10191{
10192 int bpp = pipe_config->pipe_bpp;
10193
10194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10195 connector->base.base.id,
10196 connector->base.name);
10197
10198 /* Don't use an invalid EDID bpc value */
10199 if (connector->base.display_info.bpc &&
10200 connector->base.display_info.bpc * 3 < bpp) {
10201 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10202 bpp, connector->base.display_info.bpc*3);
10203 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10204 }
10205
10206 /* Clamp bpp to 8 on screens without EDID 1.4 */
10207 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10208 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10209 bpp);
10210 pipe_config->pipe_bpp = 24;
10211 }
10212}
10213
10214static int
10215compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10216 struct drm_framebuffer *fb,
10217 struct intel_crtc_state *pipe_config)
10218{
10219 struct drm_device *dev = crtc->base.dev;
10220 struct intel_connector *connector;
10221 int bpp;
10222
10223 switch (fb->pixel_format) {
10224 case DRM_FORMAT_C8:
10225 bpp = 8*3; /* since we go through a colormap */
10226 break;
10227 case DRM_FORMAT_XRGB1555:
10228 case DRM_FORMAT_ARGB1555:
10229 /* checked in intel_framebuffer_init already */
10230 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10231 return -EINVAL;
10232 case DRM_FORMAT_RGB565:
10233 bpp = 6*3; /* min is 18bpp */
10234 break;
10235 case DRM_FORMAT_XBGR8888:
10236 case DRM_FORMAT_ABGR8888:
10237 /* checked in intel_framebuffer_init already */
10238 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10239 return -EINVAL;
10240 case DRM_FORMAT_XRGB8888:
10241 case DRM_FORMAT_ARGB8888:
10242 bpp = 8*3;
10243 break;
10244 case DRM_FORMAT_XRGB2101010:
10245 case DRM_FORMAT_ARGB2101010:
10246 case DRM_FORMAT_XBGR2101010:
10247 case DRM_FORMAT_ABGR2101010:
10248 /* checked in intel_framebuffer_init already */
10249 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10250 return -EINVAL;
10251 bpp = 10*3;
10252 break;
10253 /* TODO: gen4+ supports 16 bpc floating point, too. */
10254 default:
10255 DRM_DEBUG_KMS("unsupported depth\n");
10256 return -EINVAL;
10257 }
10258
10259 pipe_config->pipe_bpp = bpp;
10260
10261 /* Clamp display bpp to EDID value */
10262 for_each_intel_connector(dev, connector) {
10263 if (!connector->new_encoder ||
10264 connector->new_encoder->new_crtc != crtc)
10265 continue;
10266
10267 connected_sink_compute_bpp(connector, pipe_config);
10268 }
10269
10270 return bpp;
10271}
10272
10273static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10274{
10275 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10276 "type: 0x%x flags: 0x%x\n",
10277 mode->crtc_clock,
10278 mode->crtc_hdisplay, mode->crtc_hsync_start,
10279 mode->crtc_hsync_end, mode->crtc_htotal,
10280 mode->crtc_vdisplay, mode->crtc_vsync_start,
10281 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10282}
10283
10284static void intel_dump_pipe_config(struct intel_crtc *crtc,
10285 struct intel_crtc_state *pipe_config,
10286 const char *context)
10287{
10288 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10289 context, pipe_name(crtc->pipe));
10290
10291 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10292 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10293 pipe_config->pipe_bpp, pipe_config->dither);
10294 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10295 pipe_config->has_pch_encoder,
10296 pipe_config->fdi_lanes,
10297 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10298 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10299 pipe_config->fdi_m_n.tu);
10300 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10301 pipe_config->has_dp_encoder,
10302 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10303 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10304 pipe_config->dp_m_n.tu);
10305
10306 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10307 pipe_config->has_dp_encoder,
10308 pipe_config->dp_m2_n2.gmch_m,
10309 pipe_config->dp_m2_n2.gmch_n,
10310 pipe_config->dp_m2_n2.link_m,
10311 pipe_config->dp_m2_n2.link_n,
10312 pipe_config->dp_m2_n2.tu);
10313
10314 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10315 pipe_config->has_audio,
10316 pipe_config->has_infoframe);
10317
10318 DRM_DEBUG_KMS("requested mode:\n");
10319 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10320 DRM_DEBUG_KMS("adjusted mode:\n");
10321 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10322 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10323 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10324 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10325 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10326 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10327 pipe_config->gmch_pfit.control,
10328 pipe_config->gmch_pfit.pgm_ratios,
10329 pipe_config->gmch_pfit.lvds_border_bits);
10330 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10331 pipe_config->pch_pfit.pos,
10332 pipe_config->pch_pfit.size,
10333 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10334 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10335 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10336}
10337
10338static bool encoders_cloneable(const struct intel_encoder *a,
10339 const struct intel_encoder *b)
10340{
10341 /* masks could be asymmetric, so check both ways */
10342 return a == b || (a->cloneable & (1 << b->type) &&
10343 b->cloneable & (1 << a->type));
10344}
10345
10346static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10347 struct intel_encoder *encoder)
10348{
10349 struct drm_device *dev = crtc->base.dev;
10350 struct intel_encoder *source_encoder;
10351
10352 for_each_intel_encoder(dev, source_encoder) {
10353 if (source_encoder->new_crtc != crtc)
10354 continue;
10355
10356 if (!encoders_cloneable(encoder, source_encoder))
10357 return false;
10358 }
10359
10360 return true;
10361}
10362
10363static bool check_encoder_cloning(struct intel_crtc *crtc)
10364{
10365 struct drm_device *dev = crtc->base.dev;
10366 struct intel_encoder *encoder;
10367
10368 for_each_intel_encoder(dev, encoder) {
10369 if (encoder->new_crtc != crtc)
10370 continue;
10371
10372 if (!check_single_encoder_cloning(crtc, encoder))
10373 return false;
10374 }
10375
10376 return true;
10377}
10378
10379static bool check_digital_port_conflicts(struct drm_device *dev)
10380{
10381 struct intel_connector *connector;
10382 unsigned int used_ports = 0;
10383
10384 /*
10385 * Walk the connector list instead of the encoder
10386 * list to detect the problem on ddi platforms
10387 * where there's just one encoder per digital port.
10388 */
10389 for_each_intel_connector(dev, connector) {
10390 struct intel_encoder *encoder = connector->new_encoder;
10391
10392 if (!encoder)
10393 continue;
10394
10395 WARN_ON(!encoder->new_crtc);
10396
10397 switch (encoder->type) {
10398 unsigned int port_mask;
10399 case INTEL_OUTPUT_UNKNOWN:
10400 if (WARN_ON(!HAS_DDI(dev)))
10401 break;
10402 case INTEL_OUTPUT_DISPLAYPORT:
10403 case INTEL_OUTPUT_HDMI:
10404 case INTEL_OUTPUT_EDP:
10405 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10406
10407 /* the same port mustn't appear more than once */
10408 if (used_ports & port_mask)
10409 return false;
10410
10411 used_ports |= port_mask;
10412 default:
10413 break;
10414 }
10415 }
10416
10417 return true;
10418}
10419
10420static struct intel_crtc_state *
10421intel_modeset_pipe_config(struct drm_crtc *crtc,
10422 struct drm_framebuffer *fb,
10423 struct drm_display_mode *mode)
10424{
10425 struct drm_device *dev = crtc->dev;
10426 struct intel_encoder *encoder;
10427 struct intel_crtc_state *pipe_config;
10428 int plane_bpp, ret = -EINVAL;
10429 bool retry = true;
10430
10431 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10432 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10433 return ERR_PTR(-EINVAL);
10434 }
10435
10436 if (!check_digital_port_conflicts(dev)) {
10437 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10438 return ERR_PTR(-EINVAL);
10439 }
10440
10441 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10442 if (!pipe_config)
10443 return ERR_PTR(-ENOMEM);
10444
10445 pipe_config->base.crtc = crtc;
10446 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10447 drm_mode_copy(&pipe_config->base.mode, mode);
10448
10449 pipe_config->cpu_transcoder =
10450 (enum transcoder) to_intel_crtc(crtc)->pipe;
10451 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10452
10453 /*
10454 * Sanitize sync polarity flags based on requested ones. If neither
10455 * positive or negative polarity is requested, treat this as meaning
10456 * negative polarity.
10457 */
10458 if (!(pipe_config->base.adjusted_mode.flags &
10459 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10460 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10461
10462 if (!(pipe_config->base.adjusted_mode.flags &
10463 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10464 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10465
10466 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10467 * plane pixel format and any sink constraints into account. Returns the
10468 * source plane bpp so that dithering can be selected on mismatches
10469 * after encoders and crtc also have had their say. */
10470 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10471 fb, pipe_config);
10472 if (plane_bpp < 0)
10473 goto fail;
10474
10475 /*
10476 * Determine the real pipe dimensions. Note that stereo modes can
10477 * increase the actual pipe size due to the frame doubling and
10478 * insertion of additional space for blanks between the frame. This
10479 * is stored in the crtc timings. We use the requested mode to do this
10480 * computation to clearly distinguish it from the adjusted mode, which
10481 * can be changed by the connectors in the below retry loop.
10482 */
10483 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10484 &pipe_config->pipe_src_w,
10485 &pipe_config->pipe_src_h);
10486
10487encoder_retry:
10488 /* Ensure the port clock defaults are reset when retrying. */
10489 pipe_config->port_clock = 0;
10490 pipe_config->pixel_multiplier = 1;
10491
10492 /* Fill in default crtc timings, allow encoders to overwrite them. */
10493 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10494 CRTC_STEREO_DOUBLE);
10495
10496 /* Pass our mode to the connectors and the CRTC to give them a chance to
10497 * adjust it according to limitations or connector properties, and also
10498 * a chance to reject the mode entirely.
10499 */
10500 for_each_intel_encoder(dev, encoder) {
10501
10502 if (&encoder->new_crtc->base != crtc)
10503 continue;
10504
10505 if (!(encoder->compute_config(encoder, pipe_config))) {
10506 DRM_DEBUG_KMS("Encoder config failure\n");
10507 goto fail;
10508 }
10509 }
10510
10511 /* Set default port clock if not overwritten by the encoder. Needs to be
10512 * done afterwards in case the encoder adjusts the mode. */
10513 if (!pipe_config->port_clock)
10514 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10515 * pipe_config->pixel_multiplier;
10516
10517 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10518 if (ret < 0) {
10519 DRM_DEBUG_KMS("CRTC fixup failed\n");
10520 goto fail;
10521 }
10522
10523 if (ret == RETRY) {
10524 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10525 ret = -EINVAL;
10526 goto fail;
10527 }
10528
10529 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10530 retry = false;
10531 goto encoder_retry;
10532 }
10533
10534 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10535 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10536 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10537
10538 return pipe_config;
10539fail:
10540 kfree(pipe_config);
10541 return ERR_PTR(ret);
10542}
10543
10544/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10545 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10546static void
10547intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10548 unsigned *prepare_pipes, unsigned *disable_pipes)
10549{
10550 struct intel_crtc *intel_crtc;
10551 struct drm_device *dev = crtc->dev;
10552 struct intel_encoder *encoder;
10553 struct intel_connector *connector;
10554 struct drm_crtc *tmp_crtc;
10555
10556 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10557
10558 /* Check which crtcs have changed outputs connected to them, these need
10559 * to be part of the prepare_pipes mask. We don't (yet) support global
10560 * modeset across multiple crtcs, so modeset_pipes will only have one
10561 * bit set at most. */
10562 for_each_intel_connector(dev, connector) {
10563 if (connector->base.encoder == &connector->new_encoder->base)
10564 continue;
10565
10566 if (connector->base.encoder) {
10567 tmp_crtc = connector->base.encoder->crtc;
10568
10569 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10570 }
10571
10572 if (connector->new_encoder)
10573 *prepare_pipes |=
10574 1 << connector->new_encoder->new_crtc->pipe;
10575 }
10576
10577 for_each_intel_encoder(dev, encoder) {
10578 if (encoder->base.crtc == &encoder->new_crtc->base)
10579 continue;
10580
10581 if (encoder->base.crtc) {
10582 tmp_crtc = encoder->base.crtc;
10583
10584 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10585 }
10586
10587 if (encoder->new_crtc)
10588 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10589 }
10590
10591 /* Check for pipes that will be enabled/disabled ... */
10592 for_each_intel_crtc(dev, intel_crtc) {
10593 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10594 continue;
10595
10596 if (!intel_crtc->new_enabled)
10597 *disable_pipes |= 1 << intel_crtc->pipe;
10598 else
10599 *prepare_pipes |= 1 << intel_crtc->pipe;
10600 }
10601
10602
10603 /* set_mode is also used to update properties on life display pipes. */
10604 intel_crtc = to_intel_crtc(crtc);
10605 if (intel_crtc->new_enabled)
10606 *prepare_pipes |= 1 << intel_crtc->pipe;
10607
10608 /*
10609 * For simplicity do a full modeset on any pipe where the output routing
10610 * changed. We could be more clever, but that would require us to be
10611 * more careful with calling the relevant encoder->mode_set functions.
10612 */
10613 if (*prepare_pipes)
10614 *modeset_pipes = *prepare_pipes;
10615
10616 /* ... and mask these out. */
10617 *modeset_pipes &= ~(*disable_pipes);
10618 *prepare_pipes &= ~(*disable_pipes);
10619
10620 /*
10621 * HACK: We don't (yet) fully support global modesets. intel_set_config
10622 * obies this rule, but the modeset restore mode of
10623 * intel_modeset_setup_hw_state does not.
10624 */
10625 *modeset_pipes &= 1 << intel_crtc->pipe;
10626 *prepare_pipes &= 1 << intel_crtc->pipe;
10627
10628 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10629 *modeset_pipes, *prepare_pipes, *disable_pipes);
10630}
10631
10632static bool intel_crtc_in_use(struct drm_crtc *crtc)
10633{
10634 struct drm_encoder *encoder;
10635 struct drm_device *dev = crtc->dev;
10636
10637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10638 if (encoder->crtc == crtc)
10639 return true;
10640
10641 return false;
10642}
10643
10644static void
10645intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10646{
10647 struct drm_i915_private *dev_priv = dev->dev_private;
10648 struct intel_encoder *intel_encoder;
10649 struct intel_crtc *intel_crtc;
10650 struct drm_connector *connector;
10651
10652 intel_shared_dpll_commit(dev_priv);
10653
10654 for_each_intel_encoder(dev, intel_encoder) {
10655 if (!intel_encoder->base.crtc)
10656 continue;
10657
10658 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10659
10660 if (prepare_pipes & (1 << intel_crtc->pipe))
10661 intel_encoder->connectors_active = false;
10662 }
10663
10664 intel_modeset_commit_output_state(dev);
10665
10666 /* Double check state. */
10667 for_each_intel_crtc(dev, intel_crtc) {
10668 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10669 WARN_ON(intel_crtc->new_config &&
10670 intel_crtc->new_config != intel_crtc->config);
10671 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10672 }
10673
10674 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10675 if (!connector->encoder || !connector->encoder->crtc)
10676 continue;
10677
10678 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10679
10680 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10681 struct drm_property *dpms_property =
10682 dev->mode_config.dpms_property;
10683
10684 connector->dpms = DRM_MODE_DPMS_ON;
10685 drm_object_property_set_value(&connector->base,
10686 dpms_property,
10687 DRM_MODE_DPMS_ON);
10688
10689 intel_encoder = to_intel_encoder(connector->encoder);
10690 intel_encoder->connectors_active = true;
10691 }
10692 }
10693
10694}
10695
10696static bool intel_fuzzy_clock_check(int clock1, int clock2)
10697{
10698 int diff;
10699
10700 if (clock1 == clock2)
10701 return true;
10702
10703 if (!clock1 || !clock2)
10704 return false;
10705
10706 diff = abs(clock1 - clock2);
10707
10708 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10709 return true;
10710
10711 return false;
10712}
10713
10714#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10715 list_for_each_entry((intel_crtc), \
10716 &(dev)->mode_config.crtc_list, \
10717 base.head) \
10718 if (mask & (1 <<(intel_crtc)->pipe))
10719
10720static bool
10721intel_pipe_config_compare(struct drm_device *dev,
10722 struct intel_crtc_state *current_config,
10723 struct intel_crtc_state *pipe_config)
10724{
10725#define PIPE_CONF_CHECK_X(name) \
10726 if (current_config->name != pipe_config->name) { \
10727 DRM_ERROR("mismatch in " #name " " \
10728 "(expected 0x%08x, found 0x%08x)\n", \
10729 current_config->name, \
10730 pipe_config->name); \
10731 return false; \
10732 }
10733
10734#define PIPE_CONF_CHECK_I(name) \
10735 if (current_config->name != pipe_config->name) { \
10736 DRM_ERROR("mismatch in " #name " " \
10737 "(expected %i, found %i)\n", \
10738 current_config->name, \
10739 pipe_config->name); \
10740 return false; \
10741 }
10742
10743/* This is required for BDW+ where there is only one set of registers for
10744 * switching between high and low RR.
10745 * This macro can be used whenever a comparison has to be made between one
10746 * hw state and multiple sw state variables.
10747 */
10748#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10749 if ((current_config->name != pipe_config->name) && \
10750 (current_config->alt_name != pipe_config->name)) { \
10751 DRM_ERROR("mismatch in " #name " " \
10752 "(expected %i or %i, found %i)\n", \
10753 current_config->name, \
10754 current_config->alt_name, \
10755 pipe_config->name); \
10756 return false; \
10757 }
10758
10759#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10760 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10761 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10762 "(expected %i, found %i)\n", \
10763 current_config->name & (mask), \
10764 pipe_config->name & (mask)); \
10765 return false; \
10766 }
10767
10768#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10769 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10770 DRM_ERROR("mismatch in " #name " " \
10771 "(expected %i, found %i)\n", \
10772 current_config->name, \
10773 pipe_config->name); \
10774 return false; \
10775 }
10776
10777#define PIPE_CONF_QUIRK(quirk) \
10778 ((current_config->quirks | pipe_config->quirks) & (quirk))
10779
10780 PIPE_CONF_CHECK_I(cpu_transcoder);
10781
10782 PIPE_CONF_CHECK_I(has_pch_encoder);
10783 PIPE_CONF_CHECK_I(fdi_lanes);
10784 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10785 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10786 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10787 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10788 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10789
10790 PIPE_CONF_CHECK_I(has_dp_encoder);
10791
10792 if (INTEL_INFO(dev)->gen < 8) {
10793 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10794 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10795 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10796 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10797 PIPE_CONF_CHECK_I(dp_m_n.tu);
10798
10799 if (current_config->has_drrs) {
10800 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10801 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10802 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10803 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10804 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10805 }
10806 } else {
10807 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10808 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10809 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10810 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10811 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10812 }
10813
10814 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10815 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10816 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10817 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10818 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10819 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10820
10821 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10822 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10823 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10824 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10825 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10826 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10827
10828 PIPE_CONF_CHECK_I(pixel_multiplier);
10829 PIPE_CONF_CHECK_I(has_hdmi_sink);
10830 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10831 IS_VALLEYVIEW(dev))
10832 PIPE_CONF_CHECK_I(limited_color_range);
10833 PIPE_CONF_CHECK_I(has_infoframe);
10834
10835 PIPE_CONF_CHECK_I(has_audio);
10836
10837 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10838 DRM_MODE_FLAG_INTERLACE);
10839
10840 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10841 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10842 DRM_MODE_FLAG_PHSYNC);
10843 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10844 DRM_MODE_FLAG_NHSYNC);
10845 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10846 DRM_MODE_FLAG_PVSYNC);
10847 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10848 DRM_MODE_FLAG_NVSYNC);
10849 }
10850
10851 PIPE_CONF_CHECK_I(pipe_src_w);
10852 PIPE_CONF_CHECK_I(pipe_src_h);
10853
10854 /*
10855 * FIXME: BIOS likes to set up a cloned config with lvds+external
10856 * screen. Since we don't yet re-compute the pipe config when moving
10857 * just the lvds port away to another pipe the sw tracking won't match.
10858 *
10859 * Proper atomic modesets with recomputed global state will fix this.
10860 * Until then just don't check gmch state for inherited modes.
10861 */
10862 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10863 PIPE_CONF_CHECK_I(gmch_pfit.control);
10864 /* pfit ratios are autocomputed by the hw on gen4+ */
10865 if (INTEL_INFO(dev)->gen < 4)
10866 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10867 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10868 }
10869
10870 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10871 if (current_config->pch_pfit.enabled) {
10872 PIPE_CONF_CHECK_I(pch_pfit.pos);
10873 PIPE_CONF_CHECK_I(pch_pfit.size);
10874 }
10875
10876 /* BDW+ don't expose a synchronous way to read the state */
10877 if (IS_HASWELL(dev))
10878 PIPE_CONF_CHECK_I(ips_enabled);
10879
10880 PIPE_CONF_CHECK_I(double_wide);
10881
10882 PIPE_CONF_CHECK_X(ddi_pll_sel);
10883
10884 PIPE_CONF_CHECK_I(shared_dpll);
10885 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10886 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10887 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10888 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10889 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10890 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10891 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10892 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10893
10894 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10895 PIPE_CONF_CHECK_I(pipe_bpp);
10896
10897 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10898 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10899
10900#undef PIPE_CONF_CHECK_X
10901#undef PIPE_CONF_CHECK_I
10902#undef PIPE_CONF_CHECK_I_ALT
10903#undef PIPE_CONF_CHECK_FLAGS
10904#undef PIPE_CONF_CHECK_CLOCK_FUZZY
10905#undef PIPE_CONF_QUIRK
10906
10907 return true;
10908}
10909
10910static void check_wm_state(struct drm_device *dev)
10911{
10912 struct drm_i915_private *dev_priv = dev->dev_private;
10913 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10914 struct intel_crtc *intel_crtc;
10915 int plane;
10916
10917 if (INTEL_INFO(dev)->gen < 9)
10918 return;
10919
10920 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10921 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10922
10923 for_each_intel_crtc(dev, intel_crtc) {
10924 struct skl_ddb_entry *hw_entry, *sw_entry;
10925 const enum pipe pipe = intel_crtc->pipe;
10926
10927 if (!intel_crtc->active)
10928 continue;
10929
10930 /* planes */
10931 for_each_plane(dev_priv, pipe, plane) {
10932 hw_entry = &hw_ddb.plane[pipe][plane];
10933 sw_entry = &sw_ddb->plane[pipe][plane];
10934
10935 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10936 continue;
10937
10938 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10939 "(expected (%u,%u), found (%u,%u))\n",
10940 pipe_name(pipe), plane + 1,
10941 sw_entry->start, sw_entry->end,
10942 hw_entry->start, hw_entry->end);
10943 }
10944
10945 /* cursor */
10946 hw_entry = &hw_ddb.cursor[pipe];
10947 sw_entry = &sw_ddb->cursor[pipe];
10948
10949 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10950 continue;
10951
10952 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10953 "(expected (%u,%u), found (%u,%u))\n",
10954 pipe_name(pipe),
10955 sw_entry->start, sw_entry->end,
10956 hw_entry->start, hw_entry->end);
10957 }
10958}
10959
10960static void
10961check_connector_state(struct drm_device *dev)
10962{
10963 struct intel_connector *connector;
10964
10965 for_each_intel_connector(dev, connector) {
10966 /* This also checks the encoder/connector hw state with the
10967 * ->get_hw_state callbacks. */
10968 intel_connector_check_state(connector);
10969
10970 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10971 "connector's staged encoder doesn't match current encoder\n");
10972 }
10973}
10974
10975static void
10976check_encoder_state(struct drm_device *dev)
10977{
10978 struct intel_encoder *encoder;
10979 struct intel_connector *connector;
10980
10981 for_each_intel_encoder(dev, encoder) {
10982 bool enabled = false;
10983 bool active = false;
10984 enum pipe pipe, tracked_pipe;
10985
10986 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10987 encoder->base.base.id,
10988 encoder->base.name);
10989
10990 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10991 "encoder's stage crtc doesn't match current crtc\n");
10992 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10993 "encoder's active_connectors set, but no crtc\n");
10994
10995 for_each_intel_connector(dev, connector) {
10996 if (connector->base.encoder != &encoder->base)
10997 continue;
10998 enabled = true;
10999 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11000 active = true;
11001 }
11002 /*
11003 * for MST connectors if we unplug the connector is gone
11004 * away but the encoder is still connected to a crtc
11005 * until a modeset happens in response to the hotplug.
11006 */
11007 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11008 continue;
11009
11010 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11011 "encoder's enabled state mismatch "
11012 "(expected %i, found %i)\n",
11013 !!encoder->base.crtc, enabled);
11014 I915_STATE_WARN(active && !encoder->base.crtc,
11015 "active encoder with no crtc\n");
11016
11017 I915_STATE_WARN(encoder->connectors_active != active,
11018 "encoder's computed active state doesn't match tracked active state "
11019 "(expected %i, found %i)\n", active, encoder->connectors_active);
11020
11021 active = encoder->get_hw_state(encoder, &pipe);
11022 I915_STATE_WARN(active != encoder->connectors_active,
11023 "encoder's hw state doesn't match sw tracking "
11024 "(expected %i, found %i)\n",
11025 encoder->connectors_active, active);
11026
11027 if (!encoder->base.crtc)
11028 continue;
11029
11030 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11031 I915_STATE_WARN(active && pipe != tracked_pipe,
11032 "active encoder's pipe doesn't match"
11033 "(expected %i, found %i)\n",
11034 tracked_pipe, pipe);
11035
11036 }
11037}
11038
11039static void
11040check_crtc_state(struct drm_device *dev)
11041{
11042 struct drm_i915_private *dev_priv = dev->dev_private;
11043 struct intel_crtc *crtc;
11044 struct intel_encoder *encoder;
11045 struct intel_crtc_state pipe_config;
11046
11047 for_each_intel_crtc(dev, crtc) {
11048 bool enabled = false;
11049 bool active = false;
11050
11051 memset(&pipe_config, 0, sizeof(pipe_config));
11052
11053 DRM_DEBUG_KMS("[CRTC:%d]\n",
11054 crtc->base.base.id);
11055
11056 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11057 "active crtc, but not enabled in sw tracking\n");
11058
11059 for_each_intel_encoder(dev, encoder) {
11060 if (encoder->base.crtc != &crtc->base)
11061 continue;
11062 enabled = true;
11063 if (encoder->connectors_active)
11064 active = true;
11065 }
11066
11067 I915_STATE_WARN(active != crtc->active,
11068 "crtc's computed active state doesn't match tracked active state "
11069 "(expected %i, found %i)\n", active, crtc->active);
11070 I915_STATE_WARN(enabled != crtc->base.state->enable,
11071 "crtc's computed enabled state doesn't match tracked enabled state "
11072 "(expected %i, found %i)\n", enabled,
11073 crtc->base.state->enable);
11074
11075 active = dev_priv->display.get_pipe_config(crtc,
11076 &pipe_config);
11077
11078 /* hw state is inconsistent with the pipe quirk */
11079 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11080 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11081 active = crtc->active;
11082
11083 for_each_intel_encoder(dev, encoder) {
11084 enum pipe pipe;
11085 if (encoder->base.crtc != &crtc->base)
11086 continue;
11087 if (encoder->get_hw_state(encoder, &pipe))
11088 encoder->get_config(encoder, &pipe_config);
11089 }
11090
11091 I915_STATE_WARN(crtc->active != active,
11092 "crtc active state doesn't match with hw state "
11093 "(expected %i, found %i)\n", crtc->active, active);
11094
11095 if (active &&
11096 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11097 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11098 intel_dump_pipe_config(crtc, &pipe_config,
11099 "[hw state]");
11100 intel_dump_pipe_config(crtc, crtc->config,
11101 "[sw state]");
11102 }
11103 }
11104}
11105
11106static void
11107check_shared_dpll_state(struct drm_device *dev)
11108{
11109 struct drm_i915_private *dev_priv = dev->dev_private;
11110 struct intel_crtc *crtc;
11111 struct intel_dpll_hw_state dpll_hw_state;
11112 int i;
11113
11114 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11115 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11116 int enabled_crtcs = 0, active_crtcs = 0;
11117 bool active;
11118
11119 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11120
11121 DRM_DEBUG_KMS("%s\n", pll->name);
11122
11123 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11124
11125 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11126 "more active pll users than references: %i vs %i\n",
11127 pll->active, hweight32(pll->config.crtc_mask));
11128 I915_STATE_WARN(pll->active && !pll->on,
11129 "pll in active use but not on in sw tracking\n");
11130 I915_STATE_WARN(pll->on && !pll->active,
11131 "pll in on but not on in use in sw tracking\n");
11132 I915_STATE_WARN(pll->on != active,
11133 "pll on state mismatch (expected %i, found %i)\n",
11134 pll->on, active);
11135
11136 for_each_intel_crtc(dev, crtc) {
11137 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11138 enabled_crtcs++;
11139 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11140 active_crtcs++;
11141 }
11142 I915_STATE_WARN(pll->active != active_crtcs,
11143 "pll active crtcs mismatch (expected %i, found %i)\n",
11144 pll->active, active_crtcs);
11145 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11146 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11147 hweight32(pll->config.crtc_mask), enabled_crtcs);
11148
11149 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11150 sizeof(dpll_hw_state)),
11151 "pll hw state mismatch\n");
11152 }
11153}
11154
11155void
11156intel_modeset_check_state(struct drm_device *dev)
11157{
11158 check_wm_state(dev);
11159 check_connector_state(dev);
11160 check_encoder_state(dev);
11161 check_crtc_state(dev);
11162 check_shared_dpll_state(dev);
11163}
11164
11165void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11166 int dotclock)
11167{
11168 /*
11169 * FDI already provided one idea for the dotclock.
11170 * Yell if the encoder disagrees.
11171 */
11172 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11173 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11174 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11175}
11176
11177static void update_scanline_offset(struct intel_crtc *crtc)
11178{
11179 struct drm_device *dev = crtc->base.dev;
11180
11181 /*
11182 * The scanline counter increments at the leading edge of hsync.
11183 *
11184 * On most platforms it starts counting from vtotal-1 on the
11185 * first active line. That means the scanline counter value is
11186 * always one less than what we would expect. Ie. just after
11187 * start of vblank, which also occurs at start of hsync (on the
11188 * last active line), the scanline counter will read vblank_start-1.
11189 *
11190 * On gen2 the scanline counter starts counting from 1 instead
11191 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11192 * to keep the value positive), instead of adding one.
11193 *
11194 * On HSW+ the behaviour of the scanline counter depends on the output
11195 * type. For DP ports it behaves like most other platforms, but on HDMI
11196 * there's an extra 1 line difference. So we need to add two instead of
11197 * one to the value.
11198 */
11199 if (IS_GEN2(dev)) {
11200 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11201 int vtotal;
11202
11203 vtotal = mode->crtc_vtotal;
11204 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11205 vtotal /= 2;
11206
11207 crtc->scanline_offset = vtotal - 1;
11208 } else if (HAS_DDI(dev) &&
11209 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11210 crtc->scanline_offset = 2;
11211 } else
11212 crtc->scanline_offset = 1;
11213}
11214
11215static struct intel_crtc_state *
11216intel_modeset_compute_config(struct drm_crtc *crtc,
11217 struct drm_display_mode *mode,
11218 struct drm_framebuffer *fb,
11219 unsigned *modeset_pipes,
11220 unsigned *prepare_pipes,
11221 unsigned *disable_pipes)
11222{
11223 struct intel_crtc_state *pipe_config = NULL;
11224
11225 intel_modeset_affected_pipes(crtc, modeset_pipes,
11226 prepare_pipes, disable_pipes);
11227
11228 if ((*modeset_pipes) == 0)
11229 goto out;
11230
11231 /*
11232 * Note this needs changes when we start tracking multiple modes
11233 * and crtcs. At that point we'll need to compute the whole config
11234 * (i.e. one pipe_config for each crtc) rather than just the one
11235 * for this crtc.
11236 */
11237 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11238 if (IS_ERR(pipe_config)) {
11239 goto out;
11240 }
11241 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11242 "[modeset]");
11243
11244out:
11245 return pipe_config;
11246}
11247
11248static int __intel_set_mode_setup_plls(struct drm_device *dev,
11249 unsigned modeset_pipes,
11250 unsigned disable_pipes)
11251{
11252 struct drm_i915_private *dev_priv = to_i915(dev);
11253 unsigned clear_pipes = modeset_pipes | disable_pipes;
11254 struct intel_crtc *intel_crtc;
11255 int ret = 0;
11256
11257 if (!dev_priv->display.crtc_compute_clock)
11258 return 0;
11259
11260 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11261 if (ret)
11262 goto done;
11263
11264 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11265 struct intel_crtc_state *state = intel_crtc->new_config;
11266 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11267 state);
11268 if (ret) {
11269 intel_shared_dpll_abort_config(dev_priv);
11270 goto done;
11271 }
11272 }
11273
11274done:
11275 return ret;
11276}
11277
11278static int __intel_set_mode(struct drm_crtc *crtc,
11279 struct drm_display_mode *mode,
11280 int x, int y, struct drm_framebuffer *fb,
11281 struct intel_crtc_state *pipe_config,
11282 unsigned modeset_pipes,
11283 unsigned prepare_pipes,
11284 unsigned disable_pipes)
11285{
11286 struct drm_device *dev = crtc->dev;
11287 struct drm_i915_private *dev_priv = dev->dev_private;
11288 struct drm_display_mode *saved_mode;
11289 struct intel_crtc *intel_crtc;
11290 int ret = 0;
11291
11292 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11293 if (!saved_mode)
11294 return -ENOMEM;
11295
11296 *saved_mode = crtc->mode;
11297
11298 if (modeset_pipes)
11299 to_intel_crtc(crtc)->new_config = pipe_config;
11300
11301 /*
11302 * See if the config requires any additional preparation, e.g.
11303 * to adjust global state with pipes off. We need to do this
11304 * here so we can get the modeset_pipe updated config for the new
11305 * mode set on this crtc. For other crtcs we need to use the
11306 * adjusted_mode bits in the crtc directly.
11307 */
11308 if (IS_VALLEYVIEW(dev)) {
11309 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11310
11311 /* may have added more to prepare_pipes than we should */
11312 prepare_pipes &= ~disable_pipes;
11313 }
11314
11315 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11316 if (ret)
11317 goto done;
11318
11319 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11320 intel_crtc_disable(&intel_crtc->base);
11321
11322 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11323 if (intel_crtc->base.state->enable)
11324 dev_priv->display.crtc_disable(&intel_crtc->base);
11325 }
11326
11327 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11328 * to set it here already despite that we pass it down the callchain.
11329 *
11330 * Note we'll need to fix this up when we start tracking multiple
11331 * pipes; here we assume a single modeset_pipe and only track the
11332 * single crtc and mode.
11333 */
11334 if (modeset_pipes) {
11335 crtc->mode = *mode;
11336 /* mode_set/enable/disable functions rely on a correct pipe
11337 * config. */
11338 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11339
11340 /*
11341 * Calculate and store various constants which
11342 * are later needed by vblank and swap-completion
11343 * timestamping. They are derived from true hwmode.
11344 */
11345 drm_calc_timestamping_constants(crtc,
11346 &pipe_config->base.adjusted_mode);
11347 }
11348
11349 /* Only after disabling all output pipelines that will be changed can we
11350 * update the the output configuration. */
11351 intel_modeset_update_state(dev, prepare_pipes);
11352
11353 modeset_update_crtc_power_domains(dev);
11354
11355 /* Set up the DPLL and any encoders state that needs to adjust or depend
11356 * on the DPLL.
11357 */
11358 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11359 struct drm_plane *primary = intel_crtc->base.primary;
11360 int vdisplay, hdisplay;
11361
11362 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11363 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11364 fb, 0, 0,
11365 hdisplay, vdisplay,
11366 x << 16, y << 16,
11367 hdisplay << 16, vdisplay << 16);
11368 }
11369
11370 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11371 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11372 update_scanline_offset(intel_crtc);
11373
11374 dev_priv->display.crtc_enable(&intel_crtc->base);
11375 }
11376
11377 /* FIXME: add subpixel order */
11378done:
11379 if (ret && crtc->state->enable)
11380 crtc->mode = *saved_mode;
11381
11382 kfree(saved_mode);
11383 return ret;
11384}
11385
11386static int intel_set_mode_pipes(struct drm_crtc *crtc,
11387 struct drm_display_mode *mode,
11388 int x, int y, struct drm_framebuffer *fb,
11389 struct intel_crtc_state *pipe_config,
11390 unsigned modeset_pipes,
11391 unsigned prepare_pipes,
11392 unsigned disable_pipes)
11393{
11394 int ret;
11395
11396 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11397 prepare_pipes, disable_pipes);
11398
11399 if (ret == 0)
11400 intel_modeset_check_state(crtc->dev);
11401
11402 return ret;
11403}
11404
11405static int intel_set_mode(struct drm_crtc *crtc,
11406 struct drm_display_mode *mode,
11407 int x, int y, struct drm_framebuffer *fb)
11408{
11409 struct intel_crtc_state *pipe_config;
11410 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11411
11412 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11413 &modeset_pipes,
11414 &prepare_pipes,
11415 &disable_pipes);
11416
11417 if (IS_ERR(pipe_config))
11418 return PTR_ERR(pipe_config);
11419
11420 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11421 modeset_pipes, prepare_pipes,
11422 disable_pipes);
11423}
11424
11425void intel_crtc_restore_mode(struct drm_crtc *crtc)
11426{
11427 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11428}
11429
11430#undef for_each_intel_crtc_masked
11431
11432static void intel_set_config_free(struct intel_set_config *config)
11433{
11434 if (!config)
11435 return;
11436
11437 kfree(config->save_connector_encoders);
11438 kfree(config->save_encoder_crtcs);
11439 kfree(config->save_crtc_enabled);
11440 kfree(config);
11441}
11442
11443static int intel_set_config_save_state(struct drm_device *dev,
11444 struct intel_set_config *config)
11445{
11446 struct drm_crtc *crtc;
11447 struct drm_encoder *encoder;
11448 struct drm_connector *connector;
11449 int count;
11450
11451 config->save_crtc_enabled =
11452 kcalloc(dev->mode_config.num_crtc,
11453 sizeof(bool), GFP_KERNEL);
11454 if (!config->save_crtc_enabled)
11455 return -ENOMEM;
11456
11457 config->save_encoder_crtcs =
11458 kcalloc(dev->mode_config.num_encoder,
11459 sizeof(struct drm_crtc *), GFP_KERNEL);
11460 if (!config->save_encoder_crtcs)
11461 return -ENOMEM;
11462
11463 config->save_connector_encoders =
11464 kcalloc(dev->mode_config.num_connector,
11465 sizeof(struct drm_encoder *), GFP_KERNEL);
11466 if (!config->save_connector_encoders)
11467 return -ENOMEM;
11468
11469 /* Copy data. Note that driver private data is not affected.
11470 * Should anything bad happen only the expected state is
11471 * restored, not the drivers personal bookkeeping.
11472 */
11473 count = 0;
11474 for_each_crtc(dev, crtc) {
11475 config->save_crtc_enabled[count++] = crtc->state->enable;
11476 }
11477
11478 count = 0;
11479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11480 config->save_encoder_crtcs[count++] = encoder->crtc;
11481 }
11482
11483 count = 0;
11484 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11485 config->save_connector_encoders[count++] = connector->encoder;
11486 }
11487
11488 return 0;
11489}
11490
11491static void intel_set_config_restore_state(struct drm_device *dev,
11492 struct intel_set_config *config)
11493{
11494 struct intel_crtc *crtc;
11495 struct intel_encoder *encoder;
11496 struct intel_connector *connector;
11497 int count;
11498
11499 count = 0;
11500 for_each_intel_crtc(dev, crtc) {
11501 crtc->new_enabled = config->save_crtc_enabled[count++];
11502
11503 if (crtc->new_enabled)
11504 crtc->new_config = crtc->config;
11505 else
11506 crtc->new_config = NULL;
11507 }
11508
11509 count = 0;
11510 for_each_intel_encoder(dev, encoder) {
11511 encoder->new_crtc =
11512 to_intel_crtc(config->save_encoder_crtcs[count++]);
11513 }
11514
11515 count = 0;
11516 for_each_intel_connector(dev, connector) {
11517 connector->new_encoder =
11518 to_intel_encoder(config->save_connector_encoders[count++]);
11519 }
11520}
11521
11522static bool
11523is_crtc_connector_off(struct drm_mode_set *set)
11524{
11525 int i;
11526
11527 if (set->num_connectors == 0)
11528 return false;
11529
11530 if (WARN_ON(set->connectors == NULL))
11531 return false;
11532
11533 for (i = 0; i < set->num_connectors; i++)
11534 if (set->connectors[i]->encoder &&
11535 set->connectors[i]->encoder->crtc == set->crtc &&
11536 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11537 return true;
11538
11539 return false;
11540}
11541
11542static void
11543intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11544 struct intel_set_config *config)
11545{
11546
11547 /* We should be able to check here if the fb has the same properties
11548 * and then just flip_or_move it */
11549 if (is_crtc_connector_off(set)) {
11550 config->mode_changed = true;
11551 } else if (set->crtc->primary->fb != set->fb) {
11552 /*
11553 * If we have no fb, we can only flip as long as the crtc is
11554 * active, otherwise we need a full mode set. The crtc may
11555 * be active if we've only disabled the primary plane, or
11556 * in fastboot situations.
11557 */
11558 if (set->crtc->primary->fb == NULL) {
11559 struct intel_crtc *intel_crtc =
11560 to_intel_crtc(set->crtc);
11561
11562 if (intel_crtc->active) {
11563 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11564 config->fb_changed = true;
11565 } else {
11566 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11567 config->mode_changed = true;
11568 }
11569 } else if (set->fb == NULL) {
11570 config->mode_changed = true;
11571 } else if (set->fb->pixel_format !=
11572 set->crtc->primary->fb->pixel_format) {
11573 config->mode_changed = true;
11574 } else {
11575 config->fb_changed = true;
11576 }
11577 }
11578
11579 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11580 config->fb_changed = true;
11581
11582 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11583 DRM_DEBUG_KMS("modes are different, full mode set\n");
11584 drm_mode_debug_printmodeline(&set->crtc->mode);
11585 drm_mode_debug_printmodeline(set->mode);
11586 config->mode_changed = true;
11587 }
11588
11589 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11590 set->crtc->base.id, config->mode_changed, config->fb_changed);
11591}
11592
11593static int
11594intel_modeset_stage_output_state(struct drm_device *dev,
11595 struct drm_mode_set *set,
11596 struct intel_set_config *config)
11597{
11598 struct intel_connector *connector;
11599 struct intel_encoder *encoder;
11600 struct intel_crtc *crtc;
11601 int ro;
11602
11603 /* The upper layers ensure that we either disable a crtc or have a list
11604 * of connectors. For paranoia, double-check this. */
11605 WARN_ON(!set->fb && (set->num_connectors != 0));
11606 WARN_ON(set->fb && (set->num_connectors == 0));
11607
11608 for_each_intel_connector(dev, connector) {
11609 /* Otherwise traverse passed in connector list and get encoders
11610 * for them. */
11611 for (ro = 0; ro < set->num_connectors; ro++) {
11612 if (set->connectors[ro] == &connector->base) {
11613 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11614 break;
11615 }
11616 }
11617
11618 /* If we disable the crtc, disable all its connectors. Also, if
11619 * the connector is on the changing crtc but not on the new
11620 * connector list, disable it. */
11621 if ((!set->fb || ro == set->num_connectors) &&
11622 connector->base.encoder &&
11623 connector->base.encoder->crtc == set->crtc) {
11624 connector->new_encoder = NULL;
11625
11626 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11627 connector->base.base.id,
11628 connector->base.name);
11629 }
11630
11631
11632 if (&connector->new_encoder->base != connector->base.encoder) {
11633 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11634 connector->base.base.id,
11635 connector->base.name);
11636 config->mode_changed = true;
11637 }
11638 }
11639 /* connector->new_encoder is now updated for all connectors. */
11640
11641 /* Update crtc of enabled connectors. */
11642 for_each_intel_connector(dev, connector) {
11643 struct drm_crtc *new_crtc;
11644
11645 if (!connector->new_encoder)
11646 continue;
11647
11648 new_crtc = connector->new_encoder->base.crtc;
11649
11650 for (ro = 0; ro < set->num_connectors; ro++) {
11651 if (set->connectors[ro] == &connector->base)
11652 new_crtc = set->crtc;
11653 }
11654
11655 /* Make sure the new CRTC will work with the encoder */
11656 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11657 new_crtc)) {
11658 return -EINVAL;
11659 }
11660 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11661
11662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11663 connector->base.base.id,
11664 connector->base.name,
11665 new_crtc->base.id);
11666 }
11667
11668 /* Check for any encoders that needs to be disabled. */
11669 for_each_intel_encoder(dev, encoder) {
11670 int num_connectors = 0;
11671 for_each_intel_connector(dev, connector) {
11672 if (connector->new_encoder == encoder) {
11673 WARN_ON(!connector->new_encoder->new_crtc);
11674 num_connectors++;
11675 }
11676 }
11677
11678 if (num_connectors == 0)
11679 encoder->new_crtc = NULL;
11680 else if (num_connectors > 1)
11681 return -EINVAL;
11682
11683 /* Only now check for crtc changes so we don't miss encoders
11684 * that will be disabled. */
11685 if (&encoder->new_crtc->base != encoder->base.crtc) {
11686 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11687 encoder->base.base.id,
11688 encoder->base.name);
11689 config->mode_changed = true;
11690 }
11691 }
11692 /* Now we've also updated encoder->new_crtc for all encoders. */
11693 for_each_intel_connector(dev, connector) {
11694 if (connector->new_encoder)
11695 if (connector->new_encoder != connector->encoder)
11696 connector->encoder = connector->new_encoder;
11697 }
11698 for_each_intel_crtc(dev, crtc) {
11699 crtc->new_enabled = false;
11700
11701 for_each_intel_encoder(dev, encoder) {
11702 if (encoder->new_crtc == crtc) {
11703 crtc->new_enabled = true;
11704 break;
11705 }
11706 }
11707
11708 if (crtc->new_enabled != crtc->base.state->enable) {
11709 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11710 crtc->base.base.id,
11711 crtc->new_enabled ? "en" : "dis");
11712 config->mode_changed = true;
11713 }
11714
11715 if (crtc->new_enabled)
11716 crtc->new_config = crtc->config;
11717 else
11718 crtc->new_config = NULL;
11719 }
11720
11721 return 0;
11722}
11723
11724static void disable_crtc_nofb(struct intel_crtc *crtc)
11725{
11726 struct drm_device *dev = crtc->base.dev;
11727 struct intel_encoder *encoder;
11728 struct intel_connector *connector;
11729
11730 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11731 pipe_name(crtc->pipe));
11732
11733 for_each_intel_connector(dev, connector) {
11734 if (connector->new_encoder &&
11735 connector->new_encoder->new_crtc == crtc)
11736 connector->new_encoder = NULL;
11737 }
11738
11739 for_each_intel_encoder(dev, encoder) {
11740 if (encoder->new_crtc == crtc)
11741 encoder->new_crtc = NULL;
11742 }
11743
11744 crtc->new_enabled = false;
11745 crtc->new_config = NULL;
11746}
11747
11748static int intel_crtc_set_config(struct drm_mode_set *set)
11749{
11750 struct drm_device *dev;
11751 struct drm_mode_set save_set;
11752 struct intel_set_config *config;
11753 struct intel_crtc_state *pipe_config;
11754 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11755 int ret;
11756
11757 BUG_ON(!set);
11758 BUG_ON(!set->crtc);
11759 BUG_ON(!set->crtc->helper_private);
11760
11761 /* Enforce sane interface api - has been abused by the fb helper. */
11762 BUG_ON(!set->mode && set->fb);
11763 BUG_ON(set->fb && set->num_connectors == 0);
11764
11765 if (set->fb) {
11766 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11767 set->crtc->base.id, set->fb->base.id,
11768 (int)set->num_connectors, set->x, set->y);
11769 } else {
11770 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11771 }
11772
11773 dev = set->crtc->dev;
11774
11775 ret = -ENOMEM;
11776 config = kzalloc(sizeof(*config), GFP_KERNEL);
11777 if (!config)
11778 goto out_config;
11779
11780 ret = intel_set_config_save_state(dev, config);
11781 if (ret)
11782 goto out_config;
11783
11784 save_set.crtc = set->crtc;
11785 save_set.mode = &set->crtc->mode;
11786 save_set.x = set->crtc->x;
11787 save_set.y = set->crtc->y;
11788 save_set.fb = set->crtc->primary->fb;
11789
11790 /* Compute whether we need a full modeset, only an fb base update or no
11791 * change at all. In the future we might also check whether only the
11792 * mode changed, e.g. for LVDS where we only change the panel fitter in
11793 * such cases. */
11794 intel_set_config_compute_mode_changes(set, config);
11795
11796 ret = intel_modeset_stage_output_state(dev, set, config);
11797 if (ret)
11798 goto fail;
11799
11800 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11801 set->fb,
11802 &modeset_pipes,
11803 &prepare_pipes,
11804 &disable_pipes);
11805 if (IS_ERR(pipe_config)) {
11806 ret = PTR_ERR(pipe_config);
11807 goto fail;
11808 } else if (pipe_config) {
11809 if (pipe_config->has_audio !=
11810 to_intel_crtc(set->crtc)->config->has_audio)
11811 config->mode_changed = true;
11812
11813 /*
11814 * Note we have an issue here with infoframes: current code
11815 * only updates them on the full mode set path per hw
11816 * requirements. So here we should be checking for any
11817 * required changes and forcing a mode set.
11818 */
11819 }
11820
11821 /* set_mode will free it in the mode_changed case */
11822 if (!config->mode_changed)
11823 kfree(pipe_config);
11824
11825 intel_update_pipe_size(to_intel_crtc(set->crtc));
11826
11827 if (config->mode_changed) {
11828 ret = intel_set_mode_pipes(set->crtc, set->mode,
11829 set->x, set->y, set->fb, pipe_config,
11830 modeset_pipes, prepare_pipes,
11831 disable_pipes);
11832 } else if (config->fb_changed) {
11833 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11834 struct drm_plane *primary = set->crtc->primary;
11835 int vdisplay, hdisplay;
11836
11837 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11838 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11839 0, 0, hdisplay, vdisplay,
11840 set->x << 16, set->y << 16,
11841 hdisplay << 16, vdisplay << 16);
11842
11843 /*
11844 * We need to make sure the primary plane is re-enabled if it
11845 * has previously been turned off.
11846 */
11847 if (!intel_crtc->primary_enabled && ret == 0) {
11848 WARN_ON(!intel_crtc->active);
11849 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11850 }
11851
11852 /*
11853 * In the fastboot case this may be our only check of the
11854 * state after boot. It would be better to only do it on
11855 * the first update, but we don't have a nice way of doing that
11856 * (and really, set_config isn't used much for high freq page
11857 * flipping, so increasing its cost here shouldn't be a big
11858 * deal).
11859 */
11860 if (i915.fastboot && ret == 0)
11861 intel_modeset_check_state(set->crtc->dev);
11862 }
11863
11864 if (ret) {
11865 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11866 set->crtc->base.id, ret);
11867fail:
11868 intel_set_config_restore_state(dev, config);
11869
11870 /*
11871 * HACK: if the pipe was on, but we didn't have a framebuffer,
11872 * force the pipe off to avoid oopsing in the modeset code
11873 * due to fb==NULL. This should only happen during boot since
11874 * we don't yet reconstruct the FB from the hardware state.
11875 */
11876 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11877 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11878
11879 /* Try to restore the config */
11880 if (config->mode_changed &&
11881 intel_set_mode(save_set.crtc, save_set.mode,
11882 save_set.x, save_set.y, save_set.fb))
11883 DRM_ERROR("failed to restore config after modeset failure\n");
11884 }
11885
11886out_config:
11887 intel_set_config_free(config);
11888 return ret;
11889}
11890
11891static const struct drm_crtc_funcs intel_crtc_funcs = {
11892 .gamma_set = intel_crtc_gamma_set,
11893 .set_config = intel_crtc_set_config,
11894 .destroy = intel_crtc_destroy,
11895 .page_flip = intel_crtc_page_flip,
11896 .atomic_duplicate_state = intel_crtc_duplicate_state,
11897 .atomic_destroy_state = intel_crtc_destroy_state,
11898};
11899
11900static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11901 struct intel_shared_dpll *pll,
11902 struct intel_dpll_hw_state *hw_state)
11903{
11904 uint32_t val;
11905
11906 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11907 return false;
11908
11909 val = I915_READ(PCH_DPLL(pll->id));
11910 hw_state->dpll = val;
11911 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11912 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11913
11914 return val & DPLL_VCO_ENABLE;
11915}
11916
11917static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11918 struct intel_shared_dpll *pll)
11919{
11920 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11921 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11922}
11923
11924static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11925 struct intel_shared_dpll *pll)
11926{
11927 /* PCH refclock must be enabled first */
11928 ibx_assert_pch_refclk_enabled(dev_priv);
11929
11930 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11931
11932 /* Wait for the clocks to stabilize. */
11933 POSTING_READ(PCH_DPLL(pll->id));
11934 udelay(150);
11935
11936 /* The pixel multiplier can only be updated once the
11937 * DPLL is enabled and the clocks are stable.
11938 *
11939 * So write it again.
11940 */
11941 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11942 POSTING_READ(PCH_DPLL(pll->id));
11943 udelay(200);
11944}
11945
11946static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11947 struct intel_shared_dpll *pll)
11948{
11949 struct drm_device *dev = dev_priv->dev;
11950 struct intel_crtc *crtc;
11951
11952 /* Make sure no transcoder isn't still depending on us. */
11953 for_each_intel_crtc(dev, crtc) {
11954 if (intel_crtc_to_shared_dpll(crtc) == pll)
11955 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11956 }
11957
11958 I915_WRITE(PCH_DPLL(pll->id), 0);
11959 POSTING_READ(PCH_DPLL(pll->id));
11960 udelay(200);
11961}
11962
11963static char *ibx_pch_dpll_names[] = {
11964 "PCH DPLL A",
11965 "PCH DPLL B",
11966};
11967
11968static void ibx_pch_dpll_init(struct drm_device *dev)
11969{
11970 struct drm_i915_private *dev_priv = dev->dev_private;
11971 int i;
11972
11973 dev_priv->num_shared_dpll = 2;
11974
11975 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11976 dev_priv->shared_dplls[i].id = i;
11977 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11978 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11979 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11980 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11981 dev_priv->shared_dplls[i].get_hw_state =
11982 ibx_pch_dpll_get_hw_state;
11983 }
11984}
11985
11986static void intel_shared_dpll_init(struct drm_device *dev)
11987{
11988 struct drm_i915_private *dev_priv = dev->dev_private;
11989
11990 if (HAS_DDI(dev))
11991 intel_ddi_pll_init(dev);
11992 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11993 ibx_pch_dpll_init(dev);
11994 else
11995 dev_priv->num_shared_dpll = 0;
11996
11997 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11998}
11999
12000/**
12001 * intel_prepare_plane_fb - Prepare fb for usage on plane
12002 * @plane: drm plane to prepare for
12003 * @fb: framebuffer to prepare for presentation
12004 *
12005 * Prepares a framebuffer for usage on a display plane. Generally this
12006 * involves pinning the underlying object and updating the frontbuffer tracking
12007 * bits. Some older platforms need special physical address handling for
12008 * cursor planes.
12009 *
12010 * Returns 0 on success, negative error code on failure.
12011 */
12012int
12013intel_prepare_plane_fb(struct drm_plane *plane,
12014 struct drm_framebuffer *fb,
12015 const struct drm_plane_state *new_state)
12016{
12017 struct drm_device *dev = plane->dev;
12018 struct intel_plane *intel_plane = to_intel_plane(plane);
12019 enum pipe pipe = intel_plane->pipe;
12020 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12021 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12022 unsigned frontbuffer_bits = 0;
12023 int ret = 0;
12024
12025 if (!obj)
12026 return 0;
12027
12028 switch (plane->type) {
12029 case DRM_PLANE_TYPE_PRIMARY:
12030 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12031 break;
12032 case DRM_PLANE_TYPE_CURSOR:
12033 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12034 break;
12035 case DRM_PLANE_TYPE_OVERLAY:
12036 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12037 break;
12038 }
12039
12040 mutex_lock(&dev->struct_mutex);
12041
12042 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12043 INTEL_INFO(dev)->cursor_needs_physical) {
12044 int align = IS_I830(dev) ? 16 * 1024 : 256;
12045 ret = i915_gem_object_attach_phys(obj, align);
12046 if (ret)
12047 DRM_DEBUG_KMS("failed to attach phys object\n");
12048 } else {
12049 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12050 }
12051
12052 if (ret == 0)
12053 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12054
12055 mutex_unlock(&dev->struct_mutex);
12056
12057 return ret;
12058}
12059
12060/**
12061 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12062 * @plane: drm plane to clean up for
12063 * @fb: old framebuffer that was on plane
12064 *
12065 * Cleans up a framebuffer that has just been removed from a plane.
12066 */
12067void
12068intel_cleanup_plane_fb(struct drm_plane *plane,
12069 struct drm_framebuffer *fb,
12070 const struct drm_plane_state *old_state)
12071{
12072 struct drm_device *dev = plane->dev;
12073 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12074
12075 if (WARN_ON(!obj))
12076 return;
12077
12078 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12079 !INTEL_INFO(dev)->cursor_needs_physical) {
12080 mutex_lock(&dev->struct_mutex);
12081 intel_unpin_fb_obj(fb, old_state);
12082 mutex_unlock(&dev->struct_mutex);
12083 }
12084}
12085
12086static int
12087intel_check_primary_plane(struct drm_plane *plane,
12088 struct intel_plane_state *state)
12089{
12090 struct drm_device *dev = plane->dev;
12091 struct drm_i915_private *dev_priv = dev->dev_private;
12092 struct drm_crtc *crtc = state->base.crtc;
12093 struct intel_crtc *intel_crtc;
12094 struct drm_framebuffer *fb = state->base.fb;
12095 struct drm_rect *dest = &state->dst;
12096 struct drm_rect *src = &state->src;
12097 const struct drm_rect *clip = &state->clip;
12098 int ret;
12099
12100 crtc = crtc ? crtc : plane->crtc;
12101 intel_crtc = to_intel_crtc(crtc);
12102
12103 ret = drm_plane_helper_check_update(plane, crtc, fb,
12104 src, dest, clip,
12105 DRM_PLANE_HELPER_NO_SCALING,
12106 DRM_PLANE_HELPER_NO_SCALING,
12107 false, true, &state->visible);
12108 if (ret)
12109 return ret;
12110
12111 if (intel_crtc->active) {
12112 intel_crtc->atomic.wait_for_flips = true;
12113
12114 /*
12115 * FBC does not work on some platforms for rotated
12116 * planes, so disable it when rotation is not 0 and
12117 * update it when rotation is set back to 0.
12118 *
12119 * FIXME: This is redundant with the fbc update done in
12120 * the primary plane enable function except that that
12121 * one is done too late. We eventually need to unify
12122 * this.
12123 */
12124 if (intel_crtc->primary_enabled &&
12125 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12126 dev_priv->fbc.crtc == intel_crtc &&
12127 state->base.rotation != BIT(DRM_ROTATE_0)) {
12128 intel_crtc->atomic.disable_fbc = true;
12129 }
12130
12131 if (state->visible) {
12132 /*
12133 * BDW signals flip done immediately if the plane
12134 * is disabled, even if the plane enable is already
12135 * armed to occur at the next vblank :(
12136 */
12137 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12138 intel_crtc->atomic.wait_vblank = true;
12139 }
12140
12141 intel_crtc->atomic.fb_bits |=
12142 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12143
12144 intel_crtc->atomic.update_fbc = true;
12145
12146 /* Update watermarks on tiling changes. */
12147 if (!plane->state->fb || !state->base.fb ||
12148 plane->state->fb->modifier[0] !=
12149 state->base.fb->modifier[0])
12150 intel_crtc->atomic.update_wm = true;
12151 }
12152
12153 return 0;
12154}
12155
12156static void
12157intel_commit_primary_plane(struct drm_plane *plane,
12158 struct intel_plane_state *state)
12159{
12160 struct drm_crtc *crtc = state->base.crtc;
12161 struct drm_framebuffer *fb = state->base.fb;
12162 struct drm_device *dev = plane->dev;
12163 struct drm_i915_private *dev_priv = dev->dev_private;
12164 struct intel_crtc *intel_crtc;
12165 struct drm_rect *src = &state->src;
12166
12167 crtc = crtc ? crtc : plane->crtc;
12168 intel_crtc = to_intel_crtc(crtc);
12169
12170 plane->fb = fb;
12171 crtc->x = src->x1 >> 16;
12172 crtc->y = src->y1 >> 16;
12173
12174 if (intel_crtc->active) {
12175 if (state->visible) {
12176 /* FIXME: kill this fastboot hack */
12177 intel_update_pipe_size(intel_crtc);
12178
12179 intel_crtc->primary_enabled = true;
12180
12181 dev_priv->display.update_primary_plane(crtc, plane->fb,
12182 crtc->x, crtc->y);
12183 } else {
12184 /*
12185 * If clipping results in a non-visible primary plane,
12186 * we'll disable the primary plane. Note that this is
12187 * a bit different than what happens if userspace
12188 * explicitly disables the plane by passing fb=0
12189 * because plane->fb still gets set and pinned.
12190 */
12191 intel_disable_primary_hw_plane(plane, crtc);
12192 }
12193 }
12194}
12195
12196static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12197{
12198 struct drm_device *dev = crtc->dev;
12199 struct drm_i915_private *dev_priv = dev->dev_private;
12200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12201 struct intel_plane *intel_plane;
12202 struct drm_plane *p;
12203 unsigned fb_bits = 0;
12204
12205 /* Track fb's for any planes being disabled */
12206 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12207 intel_plane = to_intel_plane(p);
12208
12209 if (intel_crtc->atomic.disabled_planes &
12210 (1 << drm_plane_index(p))) {
12211 switch (p->type) {
12212 case DRM_PLANE_TYPE_PRIMARY:
12213 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12214 break;
12215 case DRM_PLANE_TYPE_CURSOR:
12216 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12217 break;
12218 case DRM_PLANE_TYPE_OVERLAY:
12219 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12220 break;
12221 }
12222
12223 mutex_lock(&dev->struct_mutex);
12224 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12225 mutex_unlock(&dev->struct_mutex);
12226 }
12227 }
12228
12229 if (intel_crtc->atomic.wait_for_flips)
12230 intel_crtc_wait_for_pending_flips(crtc);
12231
12232 if (intel_crtc->atomic.disable_fbc)
12233 intel_fbc_disable(dev);
12234
12235 if (intel_crtc->atomic.pre_disable_primary)
12236 intel_pre_disable_primary(crtc);
12237
12238 if (intel_crtc->atomic.update_wm)
12239 intel_update_watermarks(crtc);
12240
12241 intel_runtime_pm_get(dev_priv);
12242
12243 /* Perform vblank evasion around commit operation */
12244 if (intel_crtc->active)
12245 intel_crtc->atomic.evade =
12246 intel_pipe_update_start(intel_crtc,
12247 &intel_crtc->atomic.start_vbl_count);
12248}
12249
12250static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12251{
12252 struct drm_device *dev = crtc->dev;
12253 struct drm_i915_private *dev_priv = dev->dev_private;
12254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12255 struct drm_plane *p;
12256
12257 if (intel_crtc->atomic.evade)
12258 intel_pipe_update_end(intel_crtc,
12259 intel_crtc->atomic.start_vbl_count);
12260
12261 intel_runtime_pm_put(dev_priv);
12262
12263 if (intel_crtc->atomic.wait_vblank)
12264 intel_wait_for_vblank(dev, intel_crtc->pipe);
12265
12266 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12267
12268 if (intel_crtc->atomic.update_fbc) {
12269 mutex_lock(&dev->struct_mutex);
12270 intel_fbc_update(dev);
12271 mutex_unlock(&dev->struct_mutex);
12272 }
12273
12274 if (intel_crtc->atomic.post_enable_primary)
12275 intel_post_enable_primary(crtc);
12276
12277 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12278 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12279 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12280 false, false);
12281
12282 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12283}
12284
12285/**
12286 * intel_plane_destroy - destroy a plane
12287 * @plane: plane to destroy
12288 *
12289 * Common destruction function for all types of planes (primary, cursor,
12290 * sprite).
12291 */
12292void intel_plane_destroy(struct drm_plane *plane)
12293{
12294 struct intel_plane *intel_plane = to_intel_plane(plane);
12295 drm_plane_cleanup(plane);
12296 kfree(intel_plane);
12297}
12298
12299const struct drm_plane_funcs intel_plane_funcs = {
12300 .update_plane = drm_plane_helper_update,
12301 .disable_plane = drm_plane_helper_disable,
12302 .destroy = intel_plane_destroy,
12303 .set_property = drm_atomic_helper_plane_set_property,
12304 .atomic_get_property = intel_plane_atomic_get_property,
12305 .atomic_set_property = intel_plane_atomic_set_property,
12306 .atomic_duplicate_state = intel_plane_duplicate_state,
12307 .atomic_destroy_state = intel_plane_destroy_state,
12308
12309};
12310
12311static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12312 int pipe)
12313{
12314 struct intel_plane *primary;
12315 struct intel_plane_state *state;
12316 const uint32_t *intel_primary_formats;
12317 int num_formats;
12318
12319 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12320 if (primary == NULL)
12321 return NULL;
12322
12323 state = intel_create_plane_state(&primary->base);
12324 if (!state) {
12325 kfree(primary);
12326 return NULL;
12327 }
12328 primary->base.state = &state->base;
12329
12330 primary->can_scale = false;
12331 primary->max_downscale = 1;
12332 primary->pipe = pipe;
12333 primary->plane = pipe;
12334 primary->check_plane = intel_check_primary_plane;
12335 primary->commit_plane = intel_commit_primary_plane;
12336 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12337 primary->plane = !pipe;
12338
12339 if (INTEL_INFO(dev)->gen <= 3) {
12340 intel_primary_formats = intel_primary_formats_gen2;
12341 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12342 } else {
12343 intel_primary_formats = intel_primary_formats_gen4;
12344 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12345 }
12346
12347 drm_universal_plane_init(dev, &primary->base, 0,
12348 &intel_plane_funcs,
12349 intel_primary_formats, num_formats,
12350 DRM_PLANE_TYPE_PRIMARY);
12351
12352 if (INTEL_INFO(dev)->gen >= 4) {
12353 if (!dev->mode_config.rotation_property)
12354 dev->mode_config.rotation_property =
12355 drm_mode_create_rotation_property(dev,
12356 BIT(DRM_ROTATE_0) |
12357 BIT(DRM_ROTATE_180));
12358 if (dev->mode_config.rotation_property)
12359 drm_object_attach_property(&primary->base.base,
12360 dev->mode_config.rotation_property,
12361 state->base.rotation);
12362 }
12363
12364 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12365
12366 return &primary->base;
12367}
12368
12369static int
12370intel_check_cursor_plane(struct drm_plane *plane,
12371 struct intel_plane_state *state)
12372{
12373 struct drm_crtc *crtc = state->base.crtc;
12374 struct drm_device *dev = plane->dev;
12375 struct drm_framebuffer *fb = state->base.fb;
12376 struct drm_rect *dest = &state->dst;
12377 struct drm_rect *src = &state->src;
12378 const struct drm_rect *clip = &state->clip;
12379 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12380 struct intel_crtc *intel_crtc;
12381 unsigned stride;
12382 int ret;
12383
12384 crtc = crtc ? crtc : plane->crtc;
12385 intel_crtc = to_intel_crtc(crtc);
12386
12387 ret = drm_plane_helper_check_update(plane, crtc, fb,
12388 src, dest, clip,
12389 DRM_PLANE_HELPER_NO_SCALING,
12390 DRM_PLANE_HELPER_NO_SCALING,
12391 true, true, &state->visible);
12392 if (ret)
12393 return ret;
12394
12395
12396 /* if we want to turn off the cursor ignore width and height */
12397 if (!obj)
12398 goto finish;
12399
12400 /* Check for which cursor types we support */
12401 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12402 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12403 state->base.crtc_w, state->base.crtc_h);
12404 return -EINVAL;
12405 }
12406
12407 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12408 if (obj->base.size < stride * state->base.crtc_h) {
12409 DRM_DEBUG_KMS("buffer is too small\n");
12410 return -ENOMEM;
12411 }
12412
12413 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12414 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12415 ret = -EINVAL;
12416 }
12417
12418finish:
12419 if (intel_crtc->active) {
12420 if (plane->state->crtc_w != state->base.crtc_w)
12421 intel_crtc->atomic.update_wm = true;
12422
12423 intel_crtc->atomic.fb_bits |=
12424 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12425 }
12426
12427 return ret;
12428}
12429
12430static void
12431intel_commit_cursor_plane(struct drm_plane *plane,
12432 struct intel_plane_state *state)
12433{
12434 struct drm_crtc *crtc = state->base.crtc;
12435 struct drm_device *dev = plane->dev;
12436 struct intel_crtc *intel_crtc;
12437 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12438 uint32_t addr;
12439
12440 crtc = crtc ? crtc : plane->crtc;
12441 intel_crtc = to_intel_crtc(crtc);
12442
12443 plane->fb = state->base.fb;
12444 crtc->cursor_x = state->base.crtc_x;
12445 crtc->cursor_y = state->base.crtc_y;
12446
12447 if (intel_crtc->cursor_bo == obj)
12448 goto update;
12449
12450 if (!obj)
12451 addr = 0;
12452 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12453 addr = i915_gem_obj_ggtt_offset(obj);
12454 else
12455 addr = obj->phys_handle->busaddr;
12456
12457 intel_crtc->cursor_addr = addr;
12458 intel_crtc->cursor_bo = obj;
12459update:
12460
12461 if (intel_crtc->active)
12462 intel_crtc_update_cursor(crtc, state->visible);
12463}
12464
12465static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12466 int pipe)
12467{
12468 struct intel_plane *cursor;
12469 struct intel_plane_state *state;
12470
12471 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12472 if (cursor == NULL)
12473 return NULL;
12474
12475 state = intel_create_plane_state(&cursor->base);
12476 if (!state) {
12477 kfree(cursor);
12478 return NULL;
12479 }
12480 cursor->base.state = &state->base;
12481
12482 cursor->can_scale = false;
12483 cursor->max_downscale = 1;
12484 cursor->pipe = pipe;
12485 cursor->plane = pipe;
12486 cursor->check_plane = intel_check_cursor_plane;
12487 cursor->commit_plane = intel_commit_cursor_plane;
12488
12489 drm_universal_plane_init(dev, &cursor->base, 0,
12490 &intel_plane_funcs,
12491 intel_cursor_formats,
12492 ARRAY_SIZE(intel_cursor_formats),
12493 DRM_PLANE_TYPE_CURSOR);
12494
12495 if (INTEL_INFO(dev)->gen >= 4) {
12496 if (!dev->mode_config.rotation_property)
12497 dev->mode_config.rotation_property =
12498 drm_mode_create_rotation_property(dev,
12499 BIT(DRM_ROTATE_0) |
12500 BIT(DRM_ROTATE_180));
12501 if (dev->mode_config.rotation_property)
12502 drm_object_attach_property(&cursor->base.base,
12503 dev->mode_config.rotation_property,
12504 state->base.rotation);
12505 }
12506
12507 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12508
12509 return &cursor->base;
12510}
12511
12512static void intel_crtc_init(struct drm_device *dev, int pipe)
12513{
12514 struct drm_i915_private *dev_priv = dev->dev_private;
12515 struct intel_crtc *intel_crtc;
12516 struct intel_crtc_state *crtc_state = NULL;
12517 struct drm_plane *primary = NULL;
12518 struct drm_plane *cursor = NULL;
12519 int i, ret;
12520
12521 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12522 if (intel_crtc == NULL)
12523 return;
12524
12525 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12526 if (!crtc_state)
12527 goto fail;
12528 intel_crtc_set_state(intel_crtc, crtc_state);
12529 crtc_state->base.crtc = &intel_crtc->base;
12530
12531 primary = intel_primary_plane_create(dev, pipe);
12532 if (!primary)
12533 goto fail;
12534
12535 cursor = intel_cursor_plane_create(dev, pipe);
12536 if (!cursor)
12537 goto fail;
12538
12539 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12540 cursor, &intel_crtc_funcs);
12541 if (ret)
12542 goto fail;
12543
12544 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12545 for (i = 0; i < 256; i++) {
12546 intel_crtc->lut_r[i] = i;
12547 intel_crtc->lut_g[i] = i;
12548 intel_crtc->lut_b[i] = i;
12549 }
12550
12551 /*
12552 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12553 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12554 */
12555 intel_crtc->pipe = pipe;
12556 intel_crtc->plane = pipe;
12557 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12558 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12559 intel_crtc->plane = !pipe;
12560 }
12561
12562 intel_crtc->cursor_base = ~0;
12563 intel_crtc->cursor_cntl = ~0;
12564 intel_crtc->cursor_size = ~0;
12565
12566 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12567 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12568 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12569 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12570
12571 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12572
12573 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12574
12575 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12576 return;
12577
12578fail:
12579 if (primary)
12580 drm_plane_cleanup(primary);
12581 if (cursor)
12582 drm_plane_cleanup(cursor);
12583 kfree(crtc_state);
12584 kfree(intel_crtc);
12585}
12586
12587enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12588{
12589 struct drm_encoder *encoder = connector->base.encoder;
12590 struct drm_device *dev = connector->base.dev;
12591
12592 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12593
12594 if (!encoder || WARN_ON(!encoder->crtc))
12595 return INVALID_PIPE;
12596
12597 return to_intel_crtc(encoder->crtc)->pipe;
12598}
12599
12600int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12601 struct drm_file *file)
12602{
12603 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12604 struct drm_crtc *drmmode_crtc;
12605 struct intel_crtc *crtc;
12606
12607 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12608
12609 if (!drmmode_crtc) {
12610 DRM_ERROR("no such CRTC id\n");
12611 return -ENOENT;
12612 }
12613
12614 crtc = to_intel_crtc(drmmode_crtc);
12615 pipe_from_crtc_id->pipe = crtc->pipe;
12616
12617 return 0;
12618}
12619
12620static int intel_encoder_clones(struct intel_encoder *encoder)
12621{
12622 struct drm_device *dev = encoder->base.dev;
12623 struct intel_encoder *source_encoder;
12624 int index_mask = 0;
12625 int entry = 0;
12626
12627 for_each_intel_encoder(dev, source_encoder) {
12628 if (encoders_cloneable(encoder, source_encoder))
12629 index_mask |= (1 << entry);
12630
12631 entry++;
12632 }
12633
12634 return index_mask;
12635}
12636
12637static bool has_edp_a(struct drm_device *dev)
12638{
12639 struct drm_i915_private *dev_priv = dev->dev_private;
12640
12641 if (!IS_MOBILE(dev))
12642 return false;
12643
12644 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12645 return false;
12646
12647 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12648 return false;
12649
12650 return true;
12651}
12652
12653static bool intel_crt_present(struct drm_device *dev)
12654{
12655 struct drm_i915_private *dev_priv = dev->dev_private;
12656
12657 if (INTEL_INFO(dev)->gen >= 9)
12658 return false;
12659
12660 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12661 return false;
12662
12663 if (IS_CHERRYVIEW(dev))
12664 return false;
12665
12666 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12667 return false;
12668
12669 return true;
12670}
12671
12672static void intel_setup_outputs(struct drm_device *dev)
12673{
12674 struct drm_i915_private *dev_priv = dev->dev_private;
12675 struct intel_encoder *encoder;
12676 struct drm_connector *connector;
12677 bool dpd_is_edp = false;
12678
12679 intel_lvds_init(dev);
12680
12681 if (intel_crt_present(dev))
12682 intel_crt_init(dev);
12683
12684 if (HAS_DDI(dev)) {
12685 int found;
12686
12687 /*
12688 * Haswell uses DDI functions to detect digital outputs.
12689 * On SKL pre-D0 the strap isn't connected, so we assume
12690 * it's there.
12691 */
12692 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12693 /* WaIgnoreDDIAStrap: skl */
12694 if (found ||
12695 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12696 intel_ddi_init(dev, PORT_A);
12697
12698 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12699 * register */
12700 found = I915_READ(SFUSE_STRAP);
12701
12702 if (found & SFUSE_STRAP_DDIB_DETECTED)
12703 intel_ddi_init(dev, PORT_B);
12704 if (found & SFUSE_STRAP_DDIC_DETECTED)
12705 intel_ddi_init(dev, PORT_C);
12706 if (found & SFUSE_STRAP_DDID_DETECTED)
12707 intel_ddi_init(dev, PORT_D);
12708 } else if (HAS_PCH_SPLIT(dev)) {
12709 int found;
12710 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12711
12712 if (has_edp_a(dev))
12713 intel_dp_init(dev, DP_A, PORT_A);
12714
12715 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12716 /* PCH SDVOB multiplex with HDMIB */
12717 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12718 if (!found)
12719 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12720 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12721 intel_dp_init(dev, PCH_DP_B, PORT_B);
12722 }
12723
12724 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12725 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12726
12727 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12728 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12729
12730 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12731 intel_dp_init(dev, PCH_DP_C, PORT_C);
12732
12733 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12734 intel_dp_init(dev, PCH_DP_D, PORT_D);
12735 } else if (IS_VALLEYVIEW(dev)) {
12736 /*
12737 * The DP_DETECTED bit is the latched state of the DDC
12738 * SDA pin at boot. However since eDP doesn't require DDC
12739 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12740 * eDP ports may have been muxed to an alternate function.
12741 * Thus we can't rely on the DP_DETECTED bit alone to detect
12742 * eDP ports. Consult the VBT as well as DP_DETECTED to
12743 * detect eDP ports.
12744 */
12745 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12746 !intel_dp_is_edp(dev, PORT_B))
12747 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12748 PORT_B);
12749 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12750 intel_dp_is_edp(dev, PORT_B))
12751 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12752
12753 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12754 !intel_dp_is_edp(dev, PORT_C))
12755 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12756 PORT_C);
12757 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12758 intel_dp_is_edp(dev, PORT_C))
12759 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12760
12761 if (IS_CHERRYVIEW(dev)) {
12762 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12763 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12764 PORT_D);
12765 /* eDP not supported on port D, so don't check VBT */
12766 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12767 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12768 }
12769
12770 intel_dsi_init(dev);
12771 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12772 bool found = false;
12773
12774 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12775 DRM_DEBUG_KMS("probing SDVOB\n");
12776 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12777 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12778 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12779 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12780 }
12781
12782 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12783 intel_dp_init(dev, DP_B, PORT_B);
12784 }
12785
12786 /* Before G4X SDVOC doesn't have its own detect register */
12787
12788 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12789 DRM_DEBUG_KMS("probing SDVOC\n");
12790 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12791 }
12792
12793 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12794
12795 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12796 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12797 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12798 }
12799 if (SUPPORTS_INTEGRATED_DP(dev))
12800 intel_dp_init(dev, DP_C, PORT_C);
12801 }
12802
12803 if (SUPPORTS_INTEGRATED_DP(dev) &&
12804 (I915_READ(DP_D) & DP_DETECTED))
12805 intel_dp_init(dev, DP_D, PORT_D);
12806 } else if (IS_GEN2(dev))
12807 intel_dvo_init(dev);
12808
12809 if (SUPPORTS_TV(dev))
12810 intel_tv_init(dev);
12811
12812 /*
12813 * FIXME: We don't have full atomic support yet, but we want to be
12814 * able to enable/test plane updates via the atomic interface in the
12815 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12816 * will take some atomic codepaths to lookup properties during
12817 * drmModeGetConnector() that unconditionally dereference
12818 * connector->state.
12819 *
12820 * We create a dummy connector state here for each connector to ensure
12821 * the DRM core doesn't try to dereference a NULL connector->state.
12822 * The actual connector properties will never be updated or contain
12823 * useful information, but since we're doing this specifically for
12824 * testing/debug of the plane operations (and only when a specific
12825 * kernel module option is given), that shouldn't really matter.
12826 *
12827 * Once atomic support for crtc's + connectors lands, this loop should
12828 * be removed since we'll be setting up real connector state, which
12829 * will contain Intel-specific properties.
12830 */
12831 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12832 list_for_each_entry(connector,
12833 &dev->mode_config.connector_list,
12834 head) {
12835 if (!WARN_ON(connector->state)) {
12836 connector->state =
12837 kzalloc(sizeof(*connector->state),
12838 GFP_KERNEL);
12839 }
12840 }
12841 }
12842
12843 intel_psr_init(dev);
12844
12845 for_each_intel_encoder(dev, encoder) {
12846 encoder->base.possible_crtcs = encoder->crtc_mask;
12847 encoder->base.possible_clones =
12848 intel_encoder_clones(encoder);
12849 }
12850
12851 intel_init_pch_refclk(dev);
12852
12853 drm_helper_move_panel_connectors_to_head(dev);
12854}
12855
12856static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12857{
12858 struct drm_device *dev = fb->dev;
12859 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12860
12861 drm_framebuffer_cleanup(fb);
12862 mutex_lock(&dev->struct_mutex);
12863 WARN_ON(!intel_fb->obj->framebuffer_references--);
12864 drm_gem_object_unreference(&intel_fb->obj->base);
12865 mutex_unlock(&dev->struct_mutex);
12866 kfree(intel_fb);
12867}
12868
12869static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12870 struct drm_file *file,
12871 unsigned int *handle)
12872{
12873 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12874 struct drm_i915_gem_object *obj = intel_fb->obj;
12875
12876 return drm_gem_handle_create(file, &obj->base, handle);
12877}
12878
12879static const struct drm_framebuffer_funcs intel_fb_funcs = {
12880 .destroy = intel_user_framebuffer_destroy,
12881 .create_handle = intel_user_framebuffer_create_handle,
12882};
12883
12884static
12885u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12886 uint32_t pixel_format)
12887{
12888 u32 gen = INTEL_INFO(dev)->gen;
12889
12890 if (gen >= 9) {
12891 /* "The stride in bytes must not exceed the of the size of 8K
12892 * pixels and 32K bytes."
12893 */
12894 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12895 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12896 return 32*1024;
12897 } else if (gen >= 4) {
12898 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12899 return 16*1024;
12900 else
12901 return 32*1024;
12902 } else if (gen >= 3) {
12903 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12904 return 8*1024;
12905 else
12906 return 16*1024;
12907 } else {
12908 /* XXX DSPC is limited to 4k tiled */
12909 return 8*1024;
12910 }
12911}
12912
12913static int intel_framebuffer_init(struct drm_device *dev,
12914 struct intel_framebuffer *intel_fb,
12915 struct drm_mode_fb_cmd2 *mode_cmd,
12916 struct drm_i915_gem_object *obj)
12917{
12918 unsigned int aligned_height;
12919 int ret;
12920 u32 pitch_limit, stride_alignment;
12921
12922 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12923
12924 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12925 /* Enforce that fb modifier and tiling mode match, but only for
12926 * X-tiled. This is needed for FBC. */
12927 if (!!(obj->tiling_mode == I915_TILING_X) !=
12928 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12929 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12930 return -EINVAL;
12931 }
12932 } else {
12933 if (obj->tiling_mode == I915_TILING_X)
12934 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12935 else if (obj->tiling_mode == I915_TILING_Y) {
12936 DRM_DEBUG("No Y tiling for legacy addfb\n");
12937 return -EINVAL;
12938 }
12939 }
12940
12941 /* Passed in modifier sanity checking. */
12942 switch (mode_cmd->modifier[0]) {
12943 case I915_FORMAT_MOD_Y_TILED:
12944 case I915_FORMAT_MOD_Yf_TILED:
12945 if (INTEL_INFO(dev)->gen < 9) {
12946 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12947 mode_cmd->modifier[0]);
12948 return -EINVAL;
12949 }
12950 case DRM_FORMAT_MOD_NONE:
12951 case I915_FORMAT_MOD_X_TILED:
12952 break;
12953 default:
12954 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12955 mode_cmd->modifier[0]);
12956 return -EINVAL;
12957 }
12958
12959 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12960 mode_cmd->pixel_format);
12961 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12962 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12963 mode_cmd->pitches[0], stride_alignment);
12964 return -EINVAL;
12965 }
12966
12967 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12968 mode_cmd->pixel_format);
12969 if (mode_cmd->pitches[0] > pitch_limit) {
12970 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12971 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12972 "tiled" : "linear",
12973 mode_cmd->pitches[0], pitch_limit);
12974 return -EINVAL;
12975 }
12976
12977 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12978 mode_cmd->pitches[0] != obj->stride) {
12979 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12980 mode_cmd->pitches[0], obj->stride);
12981 return -EINVAL;
12982 }
12983
12984 /* Reject formats not supported by any plane early. */
12985 switch (mode_cmd->pixel_format) {
12986 case DRM_FORMAT_C8:
12987 case DRM_FORMAT_RGB565:
12988 case DRM_FORMAT_XRGB8888:
12989 case DRM_FORMAT_ARGB8888:
12990 break;
12991 case DRM_FORMAT_XRGB1555:
12992 case DRM_FORMAT_ARGB1555:
12993 if (INTEL_INFO(dev)->gen > 3) {
12994 DRM_DEBUG("unsupported pixel format: %s\n",
12995 drm_get_format_name(mode_cmd->pixel_format));
12996 return -EINVAL;
12997 }
12998 break;
12999 case DRM_FORMAT_XBGR8888:
13000 case DRM_FORMAT_ABGR8888:
13001 case DRM_FORMAT_XRGB2101010:
13002 case DRM_FORMAT_ARGB2101010:
13003 case DRM_FORMAT_XBGR2101010:
13004 case DRM_FORMAT_ABGR2101010:
13005 if (INTEL_INFO(dev)->gen < 4) {
13006 DRM_DEBUG("unsupported pixel format: %s\n",
13007 drm_get_format_name(mode_cmd->pixel_format));
13008 return -EINVAL;
13009 }
13010 break;
13011 case DRM_FORMAT_YUYV:
13012 case DRM_FORMAT_UYVY:
13013 case DRM_FORMAT_YVYU:
13014 case DRM_FORMAT_VYUY:
13015 if (INTEL_INFO(dev)->gen < 5) {
13016 DRM_DEBUG("unsupported pixel format: %s\n",
13017 drm_get_format_name(mode_cmd->pixel_format));
13018 return -EINVAL;
13019 }
13020 break;
13021 default:
13022 DRM_DEBUG("unsupported pixel format: %s\n",
13023 drm_get_format_name(mode_cmd->pixel_format));
13024 return -EINVAL;
13025 }
13026
13027 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13028 if (mode_cmd->offsets[0] != 0)
13029 return -EINVAL;
13030
13031 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13032 mode_cmd->pixel_format,
13033 mode_cmd->modifier[0]);
13034 /* FIXME drm helper for size checks (especially planar formats)? */
13035 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13036 return -EINVAL;
13037
13038 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13039 intel_fb->obj = obj;
13040 intel_fb->obj->framebuffer_references++;
13041
13042 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13043 if (ret) {
13044 DRM_ERROR("framebuffer init failed %d\n", ret);
13045 return ret;
13046 }
13047
13048 return 0;
13049}
13050
13051static struct drm_framebuffer *
13052intel_user_framebuffer_create(struct drm_device *dev,
13053 struct drm_file *filp,
13054 struct drm_mode_fb_cmd2 *mode_cmd)
13055{
13056 struct drm_i915_gem_object *obj;
13057
13058 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13059 mode_cmd->handles[0]));
13060 if (&obj->base == NULL)
13061 return ERR_PTR(-ENOENT);
13062
13063 return intel_framebuffer_create(dev, mode_cmd, obj);
13064}
13065
13066#ifndef CONFIG_DRM_I915_FBDEV
13067static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13068{
13069}
13070#endif
13071
13072static const struct drm_mode_config_funcs intel_mode_funcs = {
13073 .fb_create = intel_user_framebuffer_create,
13074 .output_poll_changed = intel_fbdev_output_poll_changed,
13075 .atomic_check = intel_atomic_check,
13076 .atomic_commit = intel_atomic_commit,
13077};
13078
13079/* Set up chip specific display functions */
13080static void intel_init_display(struct drm_device *dev)
13081{
13082 struct drm_i915_private *dev_priv = dev->dev_private;
13083
13084 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13085 dev_priv->display.find_dpll = g4x_find_best_dpll;
13086 else if (IS_CHERRYVIEW(dev))
13087 dev_priv->display.find_dpll = chv_find_best_dpll;
13088 else if (IS_VALLEYVIEW(dev))
13089 dev_priv->display.find_dpll = vlv_find_best_dpll;
13090 else if (IS_PINEVIEW(dev))
13091 dev_priv->display.find_dpll = pnv_find_best_dpll;
13092 else
13093 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13094
13095 if (INTEL_INFO(dev)->gen >= 9) {
13096 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13097 dev_priv->display.get_initial_plane_config =
13098 skylake_get_initial_plane_config;
13099 dev_priv->display.crtc_compute_clock =
13100 haswell_crtc_compute_clock;
13101 dev_priv->display.crtc_enable = haswell_crtc_enable;
13102 dev_priv->display.crtc_disable = haswell_crtc_disable;
13103 dev_priv->display.off = ironlake_crtc_off;
13104 dev_priv->display.update_primary_plane =
13105 skylake_update_primary_plane;
13106 } else if (HAS_DDI(dev)) {
13107 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13108 dev_priv->display.get_initial_plane_config =
13109 ironlake_get_initial_plane_config;
13110 dev_priv->display.crtc_compute_clock =
13111 haswell_crtc_compute_clock;
13112 dev_priv->display.crtc_enable = haswell_crtc_enable;
13113 dev_priv->display.crtc_disable = haswell_crtc_disable;
13114 dev_priv->display.off = ironlake_crtc_off;
13115 dev_priv->display.update_primary_plane =
13116 ironlake_update_primary_plane;
13117 } else if (HAS_PCH_SPLIT(dev)) {
13118 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13119 dev_priv->display.get_initial_plane_config =
13120 ironlake_get_initial_plane_config;
13121 dev_priv->display.crtc_compute_clock =
13122 ironlake_crtc_compute_clock;
13123 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13124 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13125 dev_priv->display.off = ironlake_crtc_off;
13126 dev_priv->display.update_primary_plane =
13127 ironlake_update_primary_plane;
13128 } else if (IS_VALLEYVIEW(dev)) {
13129 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13130 dev_priv->display.get_initial_plane_config =
13131 i9xx_get_initial_plane_config;
13132 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13133 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13134 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13135 dev_priv->display.off = i9xx_crtc_off;
13136 dev_priv->display.update_primary_plane =
13137 i9xx_update_primary_plane;
13138 } else {
13139 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13140 dev_priv->display.get_initial_plane_config =
13141 i9xx_get_initial_plane_config;
13142 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13143 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13144 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13145 dev_priv->display.off = i9xx_crtc_off;
13146 dev_priv->display.update_primary_plane =
13147 i9xx_update_primary_plane;
13148 }
13149
13150 /* Returns the core display clock speed */
13151 if (IS_VALLEYVIEW(dev))
13152 dev_priv->display.get_display_clock_speed =
13153 valleyview_get_display_clock_speed;
13154 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13155 dev_priv->display.get_display_clock_speed =
13156 i945_get_display_clock_speed;
13157 else if (IS_I915G(dev))
13158 dev_priv->display.get_display_clock_speed =
13159 i915_get_display_clock_speed;
13160 else if (IS_I945GM(dev) || IS_845G(dev))
13161 dev_priv->display.get_display_clock_speed =
13162 i9xx_misc_get_display_clock_speed;
13163 else if (IS_PINEVIEW(dev))
13164 dev_priv->display.get_display_clock_speed =
13165 pnv_get_display_clock_speed;
13166 else if (IS_I915GM(dev))
13167 dev_priv->display.get_display_clock_speed =
13168 i915gm_get_display_clock_speed;
13169 else if (IS_I865G(dev))
13170 dev_priv->display.get_display_clock_speed =
13171 i865_get_display_clock_speed;
13172 else if (IS_I85X(dev))
13173 dev_priv->display.get_display_clock_speed =
13174 i855_get_display_clock_speed;
13175 else /* 852, 830 */
13176 dev_priv->display.get_display_clock_speed =
13177 i830_get_display_clock_speed;
13178
13179 if (IS_GEN5(dev)) {
13180 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13181 } else if (IS_GEN6(dev)) {
13182 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13183 } else if (IS_IVYBRIDGE(dev)) {
13184 /* FIXME: detect B0+ stepping and use auto training */
13185 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13186 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13187 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13188 } else if (IS_VALLEYVIEW(dev)) {
13189 dev_priv->display.modeset_global_resources =
13190 valleyview_modeset_global_resources;
13191 }
13192
13193 switch (INTEL_INFO(dev)->gen) {
13194 case 2:
13195 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13196 break;
13197
13198 case 3:
13199 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13200 break;
13201
13202 case 4:
13203 case 5:
13204 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13205 break;
13206
13207 case 6:
13208 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13209 break;
13210 case 7:
13211 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13212 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13213 break;
13214 case 9:
13215 /* Drop through - unsupported since execlist only. */
13216 default:
13217 /* Default just returns -ENODEV to indicate unsupported */
13218 dev_priv->display.queue_flip = intel_default_queue_flip;
13219 }
13220
13221 intel_panel_init_backlight_funcs(dev);
13222
13223 mutex_init(&dev_priv->pps_mutex);
13224}
13225
13226/*
13227 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13228 * resume, or other times. This quirk makes sure that's the case for
13229 * affected systems.
13230 */
13231static void quirk_pipea_force(struct drm_device *dev)
13232{
13233 struct drm_i915_private *dev_priv = dev->dev_private;
13234
13235 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13236 DRM_INFO("applying pipe a force quirk\n");
13237}
13238
13239static void quirk_pipeb_force(struct drm_device *dev)
13240{
13241 struct drm_i915_private *dev_priv = dev->dev_private;
13242
13243 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13244 DRM_INFO("applying pipe b force quirk\n");
13245}
13246
13247/*
13248 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13249 */
13250static void quirk_ssc_force_disable(struct drm_device *dev)
13251{
13252 struct drm_i915_private *dev_priv = dev->dev_private;
13253 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13254 DRM_INFO("applying lvds SSC disable quirk\n");
13255}
13256
13257/*
13258 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13259 * brightness value
13260 */
13261static void quirk_invert_brightness(struct drm_device *dev)
13262{
13263 struct drm_i915_private *dev_priv = dev->dev_private;
13264 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13265 DRM_INFO("applying inverted panel brightness quirk\n");
13266}
13267
13268/* Some VBT's incorrectly indicate no backlight is present */
13269static void quirk_backlight_present(struct drm_device *dev)
13270{
13271 struct drm_i915_private *dev_priv = dev->dev_private;
13272 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13273 DRM_INFO("applying backlight present quirk\n");
13274}
13275
13276struct intel_quirk {
13277 int device;
13278 int subsystem_vendor;
13279 int subsystem_device;
13280 void (*hook)(struct drm_device *dev);
13281};
13282
13283/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13284struct intel_dmi_quirk {
13285 void (*hook)(struct drm_device *dev);
13286 const struct dmi_system_id (*dmi_id_list)[];
13287};
13288
13289static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13290{
13291 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13292 return 1;
13293}
13294
13295static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13296 {
13297 .dmi_id_list = &(const struct dmi_system_id[]) {
13298 {
13299 .callback = intel_dmi_reverse_brightness,
13300 .ident = "NCR Corporation",
13301 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13302 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13303 },
13304 },
13305 { } /* terminating entry */
13306 },
13307 .hook = quirk_invert_brightness,
13308 },
13309};
13310
13311static struct intel_quirk intel_quirks[] = {
13312 /* HP Mini needs pipe A force quirk (LP: #322104) */
13313 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13314
13315 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13316 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13317
13318 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13319 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13320
13321 /* 830 needs to leave pipe A & dpll A up */
13322 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13323
13324 /* 830 needs to leave pipe B & dpll B up */
13325 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13326
13327 /* Lenovo U160 cannot use SSC on LVDS */
13328 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13329
13330 /* Sony Vaio Y cannot use SSC on LVDS */
13331 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13332
13333 /* Acer Aspire 5734Z must invert backlight brightness */
13334 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13335
13336 /* Acer/eMachines G725 */
13337 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13338
13339 /* Acer/eMachines e725 */
13340 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13341
13342 /* Acer/Packard Bell NCL20 */
13343 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13344
13345 /* Acer Aspire 4736Z */
13346 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13347
13348 /* Acer Aspire 5336 */
13349 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13350
13351 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13352 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13353
13354 /* Acer C720 Chromebook (Core i3 4005U) */
13355 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13356
13357 /* Apple Macbook 2,1 (Core 2 T7400) */
13358 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13359
13360 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13361 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13362
13363 /* HP Chromebook 14 (Celeron 2955U) */
13364 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13365
13366 /* Dell Chromebook 11 */
13367 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13368};
13369
13370static void intel_init_quirks(struct drm_device *dev)
13371{
13372 struct pci_dev *d = dev->pdev;
13373 int i;
13374
13375 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13376 struct intel_quirk *q = &intel_quirks[i];
13377
13378 if (d->device == q->device &&
13379 (d->subsystem_vendor == q->subsystem_vendor ||
13380 q->subsystem_vendor == PCI_ANY_ID) &&
13381 (d->subsystem_device == q->subsystem_device ||
13382 q->subsystem_device == PCI_ANY_ID))
13383 q->hook(dev);
13384 }
13385 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13386 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13387 intel_dmi_quirks[i].hook(dev);
13388 }
13389}
13390
13391/* Disable the VGA plane that we never use */
13392static void i915_disable_vga(struct drm_device *dev)
13393{
13394 struct drm_i915_private *dev_priv = dev->dev_private;
13395 u8 sr1;
13396 u32 vga_reg = i915_vgacntrl_reg(dev);
13397
13398 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13399 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13400 outb(SR01, VGA_SR_INDEX);
13401 sr1 = inb(VGA_SR_DATA);
13402 outb(sr1 | 1<<5, VGA_SR_DATA);
13403 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13404 udelay(300);
13405
13406 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13407 POSTING_READ(vga_reg);
13408}
13409
13410void intel_modeset_init_hw(struct drm_device *dev)
13411{
13412 intel_prepare_ddi(dev);
13413
13414 if (IS_VALLEYVIEW(dev))
13415 vlv_update_cdclk(dev);
13416
13417 intel_init_clock_gating(dev);
13418
13419 intel_enable_gt_powersave(dev);
13420}
13421
13422void intel_modeset_init(struct drm_device *dev)
13423{
13424 struct drm_i915_private *dev_priv = dev->dev_private;
13425 int sprite, ret;
13426 enum pipe pipe;
13427 struct intel_crtc *crtc;
13428
13429 drm_mode_config_init(dev);
13430
13431 dev->mode_config.min_width = 0;
13432 dev->mode_config.min_height = 0;
13433
13434 dev->mode_config.preferred_depth = 24;
13435 dev->mode_config.prefer_shadow = 1;
13436
13437 dev->mode_config.allow_fb_modifiers = true;
13438
13439 dev->mode_config.funcs = &intel_mode_funcs;
13440
13441 intel_init_quirks(dev);
13442
13443 intel_init_pm(dev);
13444
13445 if (INTEL_INFO(dev)->num_pipes == 0)
13446 return;
13447
13448 intel_init_display(dev);
13449 intel_init_audio(dev);
13450
13451 if (IS_GEN2(dev)) {
13452 dev->mode_config.max_width = 2048;
13453 dev->mode_config.max_height = 2048;
13454 } else if (IS_GEN3(dev)) {
13455 dev->mode_config.max_width = 4096;
13456 dev->mode_config.max_height = 4096;
13457 } else {
13458 dev->mode_config.max_width = 8192;
13459 dev->mode_config.max_height = 8192;
13460 }
13461
13462 if (IS_845G(dev) || IS_I865G(dev)) {
13463 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13464 dev->mode_config.cursor_height = 1023;
13465 } else if (IS_GEN2(dev)) {
13466 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13467 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13468 } else {
13469 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13470 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13471 }
13472
13473 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13474
13475 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13476 INTEL_INFO(dev)->num_pipes,
13477 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13478
13479 for_each_pipe(dev_priv, pipe) {
13480 intel_crtc_init(dev, pipe);
13481 for_each_sprite(dev_priv, pipe, sprite) {
13482 ret = intel_plane_init(dev, pipe, sprite);
13483 if (ret)
13484 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13485 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13486 }
13487 }
13488
13489 intel_init_dpio(dev);
13490
13491 intel_shared_dpll_init(dev);
13492
13493 /* Just disable it once at startup */
13494 i915_disable_vga(dev);
13495 intel_setup_outputs(dev);
13496
13497 /* Just in case the BIOS is doing something questionable. */
13498 intel_fbc_disable(dev);
13499
13500 drm_modeset_lock_all(dev);
13501 intel_modeset_setup_hw_state(dev, false);
13502 drm_modeset_unlock_all(dev);
13503
13504 for_each_intel_crtc(dev, crtc) {
13505 if (!crtc->active)
13506 continue;
13507
13508 /*
13509 * Note that reserving the BIOS fb up front prevents us
13510 * from stuffing other stolen allocations like the ring
13511 * on top. This prevents some ugliness at boot time, and
13512 * can even allow for smooth boot transitions if the BIOS
13513 * fb is large enough for the active pipe configuration.
13514 */
13515 if (dev_priv->display.get_initial_plane_config) {
13516 dev_priv->display.get_initial_plane_config(crtc,
13517 &crtc->plane_config);
13518 /*
13519 * If the fb is shared between multiple heads, we'll
13520 * just get the first one.
13521 */
13522 intel_find_plane_obj(crtc, &crtc->plane_config);
13523 }
13524 }
13525}
13526
13527static void intel_enable_pipe_a(struct drm_device *dev)
13528{
13529 struct intel_connector *connector;
13530 struct drm_connector *crt = NULL;
13531 struct intel_load_detect_pipe load_detect_temp;
13532 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13533
13534 /* We can't just switch on the pipe A, we need to set things up with a
13535 * proper mode and output configuration. As a gross hack, enable pipe A
13536 * by enabling the load detect pipe once. */
13537 for_each_intel_connector(dev, connector) {
13538 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13539 crt = &connector->base;
13540 break;
13541 }
13542 }
13543
13544 if (!crt)
13545 return;
13546
13547 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13548 intel_release_load_detect_pipe(crt, &load_detect_temp);
13549}
13550
13551static bool
13552intel_check_plane_mapping(struct intel_crtc *crtc)
13553{
13554 struct drm_device *dev = crtc->base.dev;
13555 struct drm_i915_private *dev_priv = dev->dev_private;
13556 u32 reg, val;
13557
13558 if (INTEL_INFO(dev)->num_pipes == 1)
13559 return true;
13560
13561 reg = DSPCNTR(!crtc->plane);
13562 val = I915_READ(reg);
13563
13564 if ((val & DISPLAY_PLANE_ENABLE) &&
13565 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13566 return false;
13567
13568 return true;
13569}
13570
13571static void intel_sanitize_crtc(struct intel_crtc *crtc)
13572{
13573 struct drm_device *dev = crtc->base.dev;
13574 struct drm_i915_private *dev_priv = dev->dev_private;
13575 u32 reg;
13576
13577 /* Clear any frame start delays used for debugging left by the BIOS */
13578 reg = PIPECONF(crtc->config->cpu_transcoder);
13579 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13580
13581 /* restore vblank interrupts to correct state */
13582 drm_crtc_vblank_reset(&crtc->base);
13583 if (crtc->active) {
13584 update_scanline_offset(crtc);
13585 drm_crtc_vblank_on(&crtc->base);
13586 }
13587
13588 /* We need to sanitize the plane -> pipe mapping first because this will
13589 * disable the crtc (and hence change the state) if it is wrong. Note
13590 * that gen4+ has a fixed plane -> pipe mapping. */
13591 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13592 struct intel_connector *connector;
13593 bool plane;
13594
13595 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13596 crtc->base.base.id);
13597
13598 /* Pipe has the wrong plane attached and the plane is active.
13599 * Temporarily change the plane mapping and disable everything
13600 * ... */
13601 plane = crtc->plane;
13602 crtc->plane = !plane;
13603 crtc->primary_enabled = true;
13604 dev_priv->display.crtc_disable(&crtc->base);
13605 crtc->plane = plane;
13606
13607 /* ... and break all links. */
13608 for_each_intel_connector(dev, connector) {
13609 if (connector->encoder->base.crtc != &crtc->base)
13610 continue;
13611
13612 connector->base.dpms = DRM_MODE_DPMS_OFF;
13613 connector->base.encoder = NULL;
13614 }
13615 /* multiple connectors may have the same encoder:
13616 * handle them and break crtc link separately */
13617 for_each_intel_connector(dev, connector)
13618 if (connector->encoder->base.crtc == &crtc->base) {
13619 connector->encoder->base.crtc = NULL;
13620 connector->encoder->connectors_active = false;
13621 }
13622
13623 WARN_ON(crtc->active);
13624 crtc->base.state->enable = false;
13625 crtc->base.enabled = false;
13626 }
13627
13628 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13629 crtc->pipe == PIPE_A && !crtc->active) {
13630 /* BIOS forgot to enable pipe A, this mostly happens after
13631 * resume. Force-enable the pipe to fix this, the update_dpms
13632 * call below we restore the pipe to the right state, but leave
13633 * the required bits on. */
13634 intel_enable_pipe_a(dev);
13635 }
13636
13637 /* Adjust the state of the output pipe according to whether we
13638 * have active connectors/encoders. */
13639 intel_crtc_update_dpms(&crtc->base);
13640
13641 if (crtc->active != crtc->base.state->enable) {
13642 struct intel_encoder *encoder;
13643
13644 /* This can happen either due to bugs in the get_hw_state
13645 * functions or because the pipe is force-enabled due to the
13646 * pipe A quirk. */
13647 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13648 crtc->base.base.id,
13649 crtc->base.state->enable ? "enabled" : "disabled",
13650 crtc->active ? "enabled" : "disabled");
13651
13652 crtc->base.state->enable = crtc->active;
13653 crtc->base.enabled = crtc->active;
13654
13655 /* Because we only establish the connector -> encoder ->
13656 * crtc links if something is active, this means the
13657 * crtc is now deactivated. Break the links. connector
13658 * -> encoder links are only establish when things are
13659 * actually up, hence no need to break them. */
13660 WARN_ON(crtc->active);
13661
13662 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13663 WARN_ON(encoder->connectors_active);
13664 encoder->base.crtc = NULL;
13665 }
13666 }
13667
13668 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13669 /*
13670 * We start out with underrun reporting disabled to avoid races.
13671 * For correct bookkeeping mark this on active crtcs.
13672 *
13673 * Also on gmch platforms we dont have any hardware bits to
13674 * disable the underrun reporting. Which means we need to start
13675 * out with underrun reporting disabled also on inactive pipes,
13676 * since otherwise we'll complain about the garbage we read when
13677 * e.g. coming up after runtime pm.
13678 *
13679 * No protection against concurrent access is required - at
13680 * worst a fifo underrun happens which also sets this to false.
13681 */
13682 crtc->cpu_fifo_underrun_disabled = true;
13683 crtc->pch_fifo_underrun_disabled = true;
13684 }
13685}
13686
13687static void intel_sanitize_encoder(struct intel_encoder *encoder)
13688{
13689 struct intel_connector *connector;
13690 struct drm_device *dev = encoder->base.dev;
13691
13692 /* We need to check both for a crtc link (meaning that the
13693 * encoder is active and trying to read from a pipe) and the
13694 * pipe itself being active. */
13695 bool has_active_crtc = encoder->base.crtc &&
13696 to_intel_crtc(encoder->base.crtc)->active;
13697
13698 if (encoder->connectors_active && !has_active_crtc) {
13699 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13700 encoder->base.base.id,
13701 encoder->base.name);
13702
13703 /* Connector is active, but has no active pipe. This is
13704 * fallout from our resume register restoring. Disable
13705 * the encoder manually again. */
13706 if (encoder->base.crtc) {
13707 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13708 encoder->base.base.id,
13709 encoder->base.name);
13710 encoder->disable(encoder);
13711 if (encoder->post_disable)
13712 encoder->post_disable(encoder);
13713 }
13714 encoder->base.crtc = NULL;
13715 encoder->connectors_active = false;
13716
13717 /* Inconsistent output/port/pipe state happens presumably due to
13718 * a bug in one of the get_hw_state functions. Or someplace else
13719 * in our code, like the register restore mess on resume. Clamp
13720 * things to off as a safer default. */
13721 for_each_intel_connector(dev, connector) {
13722 if (connector->encoder != encoder)
13723 continue;
13724 connector->base.dpms = DRM_MODE_DPMS_OFF;
13725 connector->base.encoder = NULL;
13726 }
13727 }
13728 /* Enabled encoders without active connectors will be fixed in
13729 * the crtc fixup. */
13730}
13731
13732void i915_redisable_vga_power_on(struct drm_device *dev)
13733{
13734 struct drm_i915_private *dev_priv = dev->dev_private;
13735 u32 vga_reg = i915_vgacntrl_reg(dev);
13736
13737 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13738 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13739 i915_disable_vga(dev);
13740 }
13741}
13742
13743void i915_redisable_vga(struct drm_device *dev)
13744{
13745 struct drm_i915_private *dev_priv = dev->dev_private;
13746
13747 /* This function can be called both from intel_modeset_setup_hw_state or
13748 * at a very early point in our resume sequence, where the power well
13749 * structures are not yet restored. Since this function is at a very
13750 * paranoid "someone might have enabled VGA while we were not looking"
13751 * level, just check if the power well is enabled instead of trying to
13752 * follow the "don't touch the power well if we don't need it" policy
13753 * the rest of the driver uses. */
13754 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13755 return;
13756
13757 i915_redisable_vga_power_on(dev);
13758}
13759
13760static bool primary_get_hw_state(struct intel_crtc *crtc)
13761{
13762 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13763
13764 if (!crtc->active)
13765 return false;
13766
13767 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13768}
13769
13770static void intel_modeset_readout_hw_state(struct drm_device *dev)
13771{
13772 struct drm_i915_private *dev_priv = dev->dev_private;
13773 enum pipe pipe;
13774 struct intel_crtc *crtc;
13775 struct intel_encoder *encoder;
13776 struct intel_connector *connector;
13777 int i;
13778
13779 for_each_intel_crtc(dev, crtc) {
13780 memset(crtc->config, 0, sizeof(*crtc->config));
13781
13782 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13783
13784 crtc->active = dev_priv->display.get_pipe_config(crtc,
13785 crtc->config);
13786
13787 crtc->base.state->enable = crtc->active;
13788 crtc->base.enabled = crtc->active;
13789 crtc->primary_enabled = primary_get_hw_state(crtc);
13790
13791 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13792 crtc->base.base.id,
13793 crtc->active ? "enabled" : "disabled");
13794 }
13795
13796 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13797 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13798
13799 pll->on = pll->get_hw_state(dev_priv, pll,
13800 &pll->config.hw_state);
13801 pll->active = 0;
13802 pll->config.crtc_mask = 0;
13803 for_each_intel_crtc(dev, crtc) {
13804 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13805 pll->active++;
13806 pll->config.crtc_mask |= 1 << crtc->pipe;
13807 }
13808 }
13809
13810 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13811 pll->name, pll->config.crtc_mask, pll->on);
13812
13813 if (pll->config.crtc_mask)
13814 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13815 }
13816
13817 for_each_intel_encoder(dev, encoder) {
13818 pipe = 0;
13819
13820 if (encoder->get_hw_state(encoder, &pipe)) {
13821 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13822 encoder->base.crtc = &crtc->base;
13823 encoder->get_config(encoder, crtc->config);
13824 } else {
13825 encoder->base.crtc = NULL;
13826 }
13827
13828 encoder->connectors_active = false;
13829 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13830 encoder->base.base.id,
13831 encoder->base.name,
13832 encoder->base.crtc ? "enabled" : "disabled",
13833 pipe_name(pipe));
13834 }
13835
13836 for_each_intel_connector(dev, connector) {
13837 if (connector->get_hw_state(connector)) {
13838 connector->base.dpms = DRM_MODE_DPMS_ON;
13839 connector->encoder->connectors_active = true;
13840 connector->base.encoder = &connector->encoder->base;
13841 } else {
13842 connector->base.dpms = DRM_MODE_DPMS_OFF;
13843 connector->base.encoder = NULL;
13844 }
13845 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13846 connector->base.base.id,
13847 connector->base.name,
13848 connector->base.encoder ? "enabled" : "disabled");
13849 }
13850}
13851
13852/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13853 * and i915 state tracking structures. */
13854void intel_modeset_setup_hw_state(struct drm_device *dev,
13855 bool force_restore)
13856{
13857 struct drm_i915_private *dev_priv = dev->dev_private;
13858 enum pipe pipe;
13859 struct intel_crtc *crtc;
13860 struct intel_encoder *encoder;
13861 int i;
13862
13863 intel_modeset_readout_hw_state(dev);
13864
13865 /*
13866 * Now that we have the config, copy it to each CRTC struct
13867 * Note that this could go away if we move to using crtc_config
13868 * checking everywhere.
13869 */
13870 for_each_intel_crtc(dev, crtc) {
13871 if (crtc->active && i915.fastboot) {
13872 intel_mode_from_pipe_config(&crtc->base.mode,
13873 crtc->config);
13874 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13875 crtc->base.base.id);
13876 drm_mode_debug_printmodeline(&crtc->base.mode);
13877 }
13878 }
13879
13880 /* HW state is read out, now we need to sanitize this mess. */
13881 for_each_intel_encoder(dev, encoder) {
13882 intel_sanitize_encoder(encoder);
13883 }
13884
13885 for_each_pipe(dev_priv, pipe) {
13886 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13887 intel_sanitize_crtc(crtc);
13888 intel_dump_pipe_config(crtc, crtc->config,
13889 "[setup_hw_state]");
13890 }
13891
13892 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13893 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13894
13895 if (!pll->on || pll->active)
13896 continue;
13897
13898 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13899
13900 pll->disable(dev_priv, pll);
13901 pll->on = false;
13902 }
13903
13904 if (IS_GEN9(dev))
13905 skl_wm_get_hw_state(dev);
13906 else if (HAS_PCH_SPLIT(dev))
13907 ilk_wm_get_hw_state(dev);
13908
13909 if (force_restore) {
13910 i915_redisable_vga(dev);
13911
13912 /*
13913 * We need to use raw interfaces for restoring state to avoid
13914 * checking (bogus) intermediate states.
13915 */
13916 for_each_pipe(dev_priv, pipe) {
13917 struct drm_crtc *crtc =
13918 dev_priv->pipe_to_crtc_mapping[pipe];
13919
13920 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13921 crtc->primary->fb);
13922 }
13923 } else {
13924 intel_modeset_update_staged_output_state(dev);
13925 }
13926
13927 intel_modeset_check_state(dev);
13928}
13929
13930void intel_modeset_gem_init(struct drm_device *dev)
13931{
13932 struct drm_i915_private *dev_priv = dev->dev_private;
13933 struct drm_crtc *c;
13934 struct drm_i915_gem_object *obj;
13935
13936 mutex_lock(&dev->struct_mutex);
13937 intel_init_gt_powersave(dev);
13938 mutex_unlock(&dev->struct_mutex);
13939
13940 /*
13941 * There may be no VBT; and if the BIOS enabled SSC we can
13942 * just keep using it to avoid unnecessary flicker. Whereas if the
13943 * BIOS isn't using it, don't assume it will work even if the VBT
13944 * indicates as much.
13945 */
13946 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13947 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13948 DREF_SSC1_ENABLE);
13949
13950 intel_modeset_init_hw(dev);
13951
13952 intel_setup_overlay(dev);
13953
13954 /*
13955 * Make sure any fbs we allocated at startup are properly
13956 * pinned & fenced. When we do the allocation it's too early
13957 * for this.
13958 */
13959 mutex_lock(&dev->struct_mutex);
13960 for_each_crtc(dev, c) {
13961 obj = intel_fb_obj(c->primary->fb);
13962 if (obj == NULL)
13963 continue;
13964
13965 if (intel_pin_and_fence_fb_obj(c->primary,
13966 c->primary->fb,
13967 c->primary->state,
13968 NULL)) {
13969 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13970 to_intel_crtc(c)->pipe);
13971 drm_framebuffer_unreference(c->primary->fb);
13972 c->primary->fb = NULL;
13973 update_state_fb(c->primary);
13974 }
13975 }
13976 mutex_unlock(&dev->struct_mutex);
13977
13978 intel_backlight_register(dev);
13979}
13980
13981void intel_connector_unregister(struct intel_connector *intel_connector)
13982{
13983 struct drm_connector *connector = &intel_connector->base;
13984
13985 intel_panel_destroy_backlight(connector);
13986 drm_connector_unregister(connector);
13987}
13988
13989void intel_modeset_cleanup(struct drm_device *dev)
13990{
13991 struct drm_i915_private *dev_priv = dev->dev_private;
13992 struct drm_connector *connector;
13993
13994 intel_disable_gt_powersave(dev);
13995
13996 intel_backlight_unregister(dev);
13997
13998 /*
13999 * Interrupts and polling as the first thing to avoid creating havoc.
14000 * Too much stuff here (turning of connectors, ...) would
14001 * experience fancy races otherwise.
14002 */
14003 intel_irq_uninstall(dev_priv);
14004
14005 /*
14006 * Due to the hpd irq storm handling the hotplug work can re-arm the
14007 * poll handlers. Hence disable polling after hpd handling is shut down.
14008 */
14009 drm_kms_helper_poll_fini(dev);
14010
14011 mutex_lock(&dev->struct_mutex);
14012
14013 intel_unregister_dsm_handler();
14014
14015 intel_fbc_disable(dev);
14016
14017 mutex_unlock(&dev->struct_mutex);
14018
14019 /* flush any delayed tasks or pending work */
14020 flush_scheduled_work();
14021
14022 /* destroy the backlight and sysfs files before encoders/connectors */
14023 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14024 struct intel_connector *intel_connector;
14025
14026 intel_connector = to_intel_connector(connector);
14027 intel_connector->unregister(intel_connector);
14028 }
14029
14030 drm_mode_config_cleanup(dev);
14031
14032 intel_cleanup_overlay(dev);
14033
14034 mutex_lock(&dev->struct_mutex);
14035 intel_cleanup_gt_powersave(dev);
14036 mutex_unlock(&dev->struct_mutex);
14037}
14038
14039/*
14040 * Return which encoder is currently attached for connector.
14041 */
14042struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14043{
14044 return &intel_attached_encoder(connector)->base;
14045}
14046
14047void intel_connector_attach_encoder(struct intel_connector *connector,
14048 struct intel_encoder *encoder)
14049{
14050 connector->encoder = encoder;
14051 drm_mode_connector_attach_encoder(&connector->base,
14052 &encoder->base);
14053}
14054
14055/*
14056 * set vga decode state - true == enable VGA decode
14057 */
14058int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14059{
14060 struct drm_i915_private *dev_priv = dev->dev_private;
14061 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14062 u16 gmch_ctrl;
14063
14064 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14065 DRM_ERROR("failed to read control word\n");
14066 return -EIO;
14067 }
14068
14069 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14070 return 0;
14071
14072 if (state)
14073 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14074 else
14075 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14076
14077 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14078 DRM_ERROR("failed to write control word\n");
14079 return -EIO;
14080 }
14081
14082 return 0;
14083}
14084
14085struct intel_display_error_state {
14086
14087 u32 power_well_driver;
14088
14089 int num_transcoders;
14090
14091 struct intel_cursor_error_state {
14092 u32 control;
14093 u32 position;
14094 u32 base;
14095 u32 size;
14096 } cursor[I915_MAX_PIPES];
14097
14098 struct intel_pipe_error_state {
14099 bool power_domain_on;
14100 u32 source;
14101 u32 stat;
14102 } pipe[I915_MAX_PIPES];
14103
14104 struct intel_plane_error_state {
14105 u32 control;
14106 u32 stride;
14107 u32 size;
14108 u32 pos;
14109 u32 addr;
14110 u32 surface;
14111 u32 tile_offset;
14112 } plane[I915_MAX_PIPES];
14113
14114 struct intel_transcoder_error_state {
14115 bool power_domain_on;
14116 enum transcoder cpu_transcoder;
14117
14118 u32 conf;
14119
14120 u32 htotal;
14121 u32 hblank;
14122 u32 hsync;
14123 u32 vtotal;
14124 u32 vblank;
14125 u32 vsync;
14126 } transcoder[4];
14127};
14128
14129struct intel_display_error_state *
14130intel_display_capture_error_state(struct drm_device *dev)
14131{
14132 struct drm_i915_private *dev_priv = dev->dev_private;
14133 struct intel_display_error_state *error;
14134 int transcoders[] = {
14135 TRANSCODER_A,
14136 TRANSCODER_B,
14137 TRANSCODER_C,
14138 TRANSCODER_EDP,
14139 };
14140 int i;
14141
14142 if (INTEL_INFO(dev)->num_pipes == 0)
14143 return NULL;
14144
14145 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14146 if (error == NULL)
14147 return NULL;
14148
14149 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14150 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14151
14152 for_each_pipe(dev_priv, i) {
14153 error->pipe[i].power_domain_on =
14154 __intel_display_power_is_enabled(dev_priv,
14155 POWER_DOMAIN_PIPE(i));
14156 if (!error->pipe[i].power_domain_on)
14157 continue;
14158
14159 error->cursor[i].control = I915_READ(CURCNTR(i));
14160 error->cursor[i].position = I915_READ(CURPOS(i));
14161 error->cursor[i].base = I915_READ(CURBASE(i));
14162
14163 error->plane[i].control = I915_READ(DSPCNTR(i));
14164 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14165 if (INTEL_INFO(dev)->gen <= 3) {
14166 error->plane[i].size = I915_READ(DSPSIZE(i));
14167 error->plane[i].pos = I915_READ(DSPPOS(i));
14168 }
14169 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14170 error->plane[i].addr = I915_READ(DSPADDR(i));
14171 if (INTEL_INFO(dev)->gen >= 4) {
14172 error->plane[i].surface = I915_READ(DSPSURF(i));
14173 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14174 }
14175
14176 error->pipe[i].source = I915_READ(PIPESRC(i));
14177
14178 if (HAS_GMCH_DISPLAY(dev))
14179 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14180 }
14181
14182 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14183 if (HAS_DDI(dev_priv->dev))
14184 error->num_transcoders++; /* Account for eDP. */
14185
14186 for (i = 0; i < error->num_transcoders; i++) {
14187 enum transcoder cpu_transcoder = transcoders[i];
14188
14189 error->transcoder[i].power_domain_on =
14190 __intel_display_power_is_enabled(dev_priv,
14191 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14192 if (!error->transcoder[i].power_domain_on)
14193 continue;
14194
14195 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14196
14197 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14198 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14199 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14200 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14201 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14202 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14203 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14204 }
14205
14206 return error;
14207}
14208
14209#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14210
14211void
14212intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14213 struct drm_device *dev,
14214 struct intel_display_error_state *error)
14215{
14216 struct drm_i915_private *dev_priv = dev->dev_private;
14217 int i;
14218
14219 if (!error)
14220 return;
14221
14222 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14223 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14224 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14225 error->power_well_driver);
14226 for_each_pipe(dev_priv, i) {
14227 err_printf(m, "Pipe [%d]:\n", i);
14228 err_printf(m, " Power: %s\n",
14229 error->pipe[i].power_domain_on ? "on" : "off");
14230 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14231 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14232
14233 err_printf(m, "Plane [%d]:\n", i);
14234 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14235 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14236 if (INTEL_INFO(dev)->gen <= 3) {
14237 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14238 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14239 }
14240 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14241 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14242 if (INTEL_INFO(dev)->gen >= 4) {
14243 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14244 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14245 }
14246
14247 err_printf(m, "Cursor [%d]:\n", i);
14248 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14249 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14250 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14251 }
14252
14253 for (i = 0; i < error->num_transcoders; i++) {
14254 err_printf(m, "CPU transcoder: %c\n",
14255 transcoder_name(error->transcoder[i].cpu_transcoder));
14256 err_printf(m, " Power: %s\n",
14257 error->transcoder[i].power_domain_on ? "on" : "off");
14258 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14259 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14260 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14261 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14262 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14263 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14264 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14265 }
14266}
14267
14268void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14269{
14270 struct intel_crtc *crtc;
14271
14272 for_each_intel_crtc(dev, crtc) {
14273 struct intel_unpin_work *work;
14274
14275 spin_lock_irq(&dev->event_lock);
14276
14277 work = crtc->unpin_work;
14278
14279 if (work && work->event &&
14280 work->event->base.file_priv == file) {
14281 kfree(work->event);
14282 work->event = NULL;
14283 }
14284
14285 spin_unlock_irq(&dev->event_lock);
14286 }
14287}
Linux kernel - Deliverables
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