| 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <linux/export.h> |
| 31 | #include <linux/notifier.h> |
| 32 | #include <linux/reboot.h> |
| 33 | #include <drm/drmP.h> |
| 34 | #include <drm/drm_crtc.h> |
| 35 | #include <drm/drm_crtc_helper.h> |
| 36 | #include <drm/drm_edid.h> |
| 37 | #include "intel_drv.h" |
| 38 | #include <drm/i915_drm.h> |
| 39 | #include "i915_drv.h" |
| 40 | |
| 41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 42 | |
| 43 | struct dp_link_dpll { |
| 44 | int link_bw; |
| 45 | struct dpll dpll; |
| 46 | }; |
| 47 | |
| 48 | static const struct dp_link_dpll gen4_dpll[] = { |
| 49 | { DP_LINK_BW_1_62, |
| 50 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
| 51 | { DP_LINK_BW_2_7, |
| 52 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 53 | }; |
| 54 | |
| 55 | static const struct dp_link_dpll pch_dpll[] = { |
| 56 | { DP_LINK_BW_1_62, |
| 57 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
| 58 | { DP_LINK_BW_2_7, |
| 59 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 60 | }; |
| 61 | |
| 62 | static const struct dp_link_dpll vlv_dpll[] = { |
| 63 | { DP_LINK_BW_1_62, |
| 64 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
| 65 | { DP_LINK_BW_2_7, |
| 66 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 67 | }; |
| 68 | |
| 69 | /* |
| 70 | * CHV supports eDP 1.4 that have more link rates. |
| 71 | * Below only provides the fixed rate but exclude variable rate. |
| 72 | */ |
| 73 | static const struct dp_link_dpll chv_dpll[] = { |
| 74 | /* |
| 75 | * CHV requires to program fractional division for m2. |
| 76 | * m2 is stored in fixed point format using formula below |
| 77 | * (m2_int << 22) | m2_fraction |
| 78 | */ |
| 79 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ |
| 80 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
| 81 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ |
| 82 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
| 83 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ |
| 84 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 85 | }; |
| 86 | |
| 87 | /** |
| 88 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 89 | * @intel_dp: DP struct |
| 90 | * |
| 91 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 92 | * will return true, and false otherwise. |
| 93 | */ |
| 94 | static bool is_edp(struct intel_dp *intel_dp) |
| 95 | { |
| 96 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 97 | |
| 98 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
| 99 | } |
| 100 | |
| 101 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
| 102 | { |
| 103 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 104 | |
| 105 | return intel_dig_port->base.base.dev; |
| 106 | } |
| 107 | |
| 108 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 109 | { |
| 110 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
| 111 | } |
| 112 | |
| 113 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
| 114 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
| 115 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| 116 | |
| 117 | int |
| 118 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
| 119 | { |
| 120 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
| 121 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
| 122 | |
| 123 | switch (max_link_bw) { |
| 124 | case DP_LINK_BW_1_62: |
| 125 | case DP_LINK_BW_2_7: |
| 126 | break; |
| 127 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
| 128 | if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || |
| 129 | INTEL_INFO(dev)->gen >= 8) && |
| 130 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
| 131 | max_link_bw = DP_LINK_BW_5_4; |
| 132 | else |
| 133 | max_link_bw = DP_LINK_BW_2_7; |
| 134 | break; |
| 135 | default: |
| 136 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 137 | max_link_bw); |
| 138 | max_link_bw = DP_LINK_BW_1_62; |
| 139 | break; |
| 140 | } |
| 141 | return max_link_bw; |
| 142 | } |
| 143 | |
| 144 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 145 | { |
| 146 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 147 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 148 | u8 source_max, sink_max; |
| 149 | |
| 150 | source_max = 4; |
| 151 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && |
| 152 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) |
| 153 | source_max = 2; |
| 154 | |
| 155 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 156 | |
| 157 | return min(source_max, sink_max); |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * The units on the numbers in the next two are... bizarre. Examples will |
| 162 | * make it clearer; this one parallels an example in the eDP spec. |
| 163 | * |
| 164 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 165 | * |
| 166 | * 270000 * 1 * 8 / 10 == 216000 |
| 167 | * |
| 168 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 169 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 170 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 171 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 172 | * |
| 173 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 174 | * get the result in decakilobits instead of kilobits. |
| 175 | */ |
| 176 | |
| 177 | static int |
| 178 | intel_dp_link_required(int pixel_clock, int bpp) |
| 179 | { |
| 180 | return (pixel_clock * bpp + 9) / 10; |
| 181 | } |
| 182 | |
| 183 | static int |
| 184 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 185 | { |
| 186 | return (max_link_clock * max_lanes * 8) / 10; |
| 187 | } |
| 188 | |
| 189 | static enum drm_mode_status |
| 190 | intel_dp_mode_valid(struct drm_connector *connector, |
| 191 | struct drm_display_mode *mode) |
| 192 | { |
| 193 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 194 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 195 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
| 196 | int target_clock = mode->clock; |
| 197 | int max_rate, mode_rate, max_lanes, max_link_clock; |
| 198 | |
| 199 | if (is_edp(intel_dp) && fixed_mode) { |
| 200 | if (mode->hdisplay > fixed_mode->hdisplay) |
| 201 | return MODE_PANEL; |
| 202 | |
| 203 | if (mode->vdisplay > fixed_mode->vdisplay) |
| 204 | return MODE_PANEL; |
| 205 | |
| 206 | target_clock = fixed_mode->clock; |
| 207 | } |
| 208 | |
| 209 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
| 210 | max_lanes = intel_dp_max_lane_count(intel_dp); |
| 211 | |
| 212 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 213 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 214 | |
| 215 | if (mode_rate > max_rate) |
| 216 | return MODE_CLOCK_HIGH; |
| 217 | |
| 218 | if (mode->clock < 10000) |
| 219 | return MODE_CLOCK_LOW; |
| 220 | |
| 221 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 222 | return MODE_H_ILLEGAL; |
| 223 | |
| 224 | return MODE_OK; |
| 225 | } |
| 226 | |
| 227 | static uint32_t |
| 228 | pack_aux(const uint8_t *src, int src_bytes) |
| 229 | { |
| 230 | int i; |
| 231 | uint32_t v = 0; |
| 232 | |
| 233 | if (src_bytes > 4) |
| 234 | src_bytes = 4; |
| 235 | for (i = 0; i < src_bytes; i++) |
| 236 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 237 | return v; |
| 238 | } |
| 239 | |
| 240 | static void |
| 241 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 242 | { |
| 243 | int i; |
| 244 | if (dst_bytes > 4) |
| 245 | dst_bytes = 4; |
| 246 | for (i = 0; i < dst_bytes; i++) |
| 247 | dst[i] = src >> ((3-i) * 8); |
| 248 | } |
| 249 | |
| 250 | /* hrawclock is 1/4 the FSB frequency */ |
| 251 | static int |
| 252 | intel_hrawclk(struct drm_device *dev) |
| 253 | { |
| 254 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 255 | uint32_t clkcfg; |
| 256 | |
| 257 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
| 258 | if (IS_VALLEYVIEW(dev)) |
| 259 | return 200; |
| 260 | |
| 261 | clkcfg = I915_READ(CLKCFG); |
| 262 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 263 | case CLKCFG_FSB_400: |
| 264 | return 100; |
| 265 | case CLKCFG_FSB_533: |
| 266 | return 133; |
| 267 | case CLKCFG_FSB_667: |
| 268 | return 166; |
| 269 | case CLKCFG_FSB_800: |
| 270 | return 200; |
| 271 | case CLKCFG_FSB_1067: |
| 272 | return 266; |
| 273 | case CLKCFG_FSB_1333: |
| 274 | return 333; |
| 275 | /* these two are just a guess; one of them might be right */ |
| 276 | case CLKCFG_FSB_1600: |
| 277 | case CLKCFG_FSB_1600_ALT: |
| 278 | return 400; |
| 279 | default: |
| 280 | return 133; |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | static void |
| 285 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 286 | struct intel_dp *intel_dp, |
| 287 | struct edp_power_seq *out); |
| 288 | static void |
| 289 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 290 | struct intel_dp *intel_dp, |
| 291 | struct edp_power_seq *out); |
| 292 | |
| 293 | static void pps_lock(struct intel_dp *intel_dp) |
| 294 | { |
| 295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 296 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 297 | struct drm_device *dev = encoder->base.dev; |
| 298 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 299 | enum intel_display_power_domain power_domain; |
| 300 | |
| 301 | /* |
| 302 | * See vlv_power_sequencer_reset() why we need |
| 303 | * a power domain reference here. |
| 304 | */ |
| 305 | power_domain = intel_display_port_power_domain(encoder); |
| 306 | intel_display_power_get(dev_priv, power_domain); |
| 307 | |
| 308 | mutex_lock(&dev_priv->pps_mutex); |
| 309 | } |
| 310 | |
| 311 | static void pps_unlock(struct intel_dp *intel_dp) |
| 312 | { |
| 313 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 314 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 315 | struct drm_device *dev = encoder->base.dev; |
| 316 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 317 | enum intel_display_power_domain power_domain; |
| 318 | |
| 319 | mutex_unlock(&dev_priv->pps_mutex); |
| 320 | |
| 321 | power_domain = intel_display_port_power_domain(encoder); |
| 322 | intel_display_power_put(dev_priv, power_domain); |
| 323 | } |
| 324 | |
| 325 | static enum pipe |
| 326 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 327 | { |
| 328 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 329 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 330 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 331 | struct intel_encoder *encoder; |
| 332 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
| 333 | struct edp_power_seq power_seq; |
| 334 | |
| 335 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 336 | |
| 337 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 338 | return intel_dp->pps_pipe; |
| 339 | |
| 340 | /* |
| 341 | * We don't have power sequencer currently. |
| 342 | * Pick one that's not used by other ports. |
| 343 | */ |
| 344 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 345 | base.head) { |
| 346 | struct intel_dp *tmp; |
| 347 | |
| 348 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 349 | continue; |
| 350 | |
| 351 | tmp = enc_to_intel_dp(&encoder->base); |
| 352 | |
| 353 | if (tmp->pps_pipe != INVALID_PIPE) |
| 354 | pipes &= ~(1 << tmp->pps_pipe); |
| 355 | } |
| 356 | |
| 357 | /* |
| 358 | * Didn't find one. This should not happen since there |
| 359 | * are two power sequencers and up to two eDP ports. |
| 360 | */ |
| 361 | if (WARN_ON(pipes == 0)) |
| 362 | return PIPE_A; |
| 363 | |
| 364 | intel_dp->pps_pipe = ffs(pipes) - 1; |
| 365 | |
| 366 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| 367 | pipe_name(intel_dp->pps_pipe), |
| 368 | port_name(intel_dig_port->port)); |
| 369 | |
| 370 | /* init power sequencer on this pipe and port */ |
| 371 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
| 372 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 373 | &power_seq); |
| 374 | |
| 375 | return intel_dp->pps_pipe; |
| 376 | } |
| 377 | |
| 378 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| 379 | enum pipe pipe); |
| 380 | |
| 381 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| 382 | enum pipe pipe) |
| 383 | { |
| 384 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; |
| 385 | } |
| 386 | |
| 387 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| 388 | enum pipe pipe) |
| 389 | { |
| 390 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
| 391 | } |
| 392 | |
| 393 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| 394 | enum pipe pipe) |
| 395 | { |
| 396 | return true; |
| 397 | } |
| 398 | |
| 399 | static enum pipe |
| 400 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| 401 | enum port port, |
| 402 | vlv_pipe_check pipe_check) |
| 403 | { |
| 404 | enum pipe pipe; |
| 405 | |
| 406 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 407 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
| 408 | PANEL_PORT_SELECT_MASK; |
| 409 | |
| 410 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| 411 | continue; |
| 412 | |
| 413 | if (!pipe_check(dev_priv, pipe)) |
| 414 | continue; |
| 415 | |
| 416 | return pipe; |
| 417 | } |
| 418 | |
| 419 | return INVALID_PIPE; |
| 420 | } |
| 421 | |
| 422 | static void |
| 423 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 424 | { |
| 425 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 426 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 427 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 428 | struct edp_power_seq power_seq; |
| 429 | enum port port = intel_dig_port->port; |
| 430 | |
| 431 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 432 | |
| 433 | /* try to find a pipe with this port selected */ |
| 434 | /* first pick one where the panel is on */ |
| 435 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 436 | vlv_pipe_has_pp_on); |
| 437 | /* didn't find one? pick one where vdd is on */ |
| 438 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 439 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 440 | vlv_pipe_has_vdd_on); |
| 441 | /* didn't find one? pick one with just the correct port */ |
| 442 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 443 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 444 | vlv_pipe_any); |
| 445 | |
| 446 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 447 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 448 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| 449 | port_name(port)); |
| 450 | return; |
| 451 | } |
| 452 | |
| 453 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| 454 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
| 455 | |
| 456 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
| 457 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 458 | &power_seq); |
| 459 | } |
| 460 | |
| 461 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
| 462 | { |
| 463 | struct drm_device *dev = dev_priv->dev; |
| 464 | struct intel_encoder *encoder; |
| 465 | |
| 466 | if (WARN_ON(!IS_VALLEYVIEW(dev))) |
| 467 | return; |
| 468 | |
| 469 | /* |
| 470 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 471 | * mutex when power_domain functions are called while holding pps_mutex. |
| 472 | * That also means that in order to use pps_pipe the code needs to |
| 473 | * hold both a power domain reference and pps_mutex, and the power domain |
| 474 | * reference get/put must be done while _not_ holding pps_mutex. |
| 475 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 476 | * should use them always. |
| 477 | */ |
| 478 | |
| 479 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 480 | struct intel_dp *intel_dp; |
| 481 | |
| 482 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 483 | continue; |
| 484 | |
| 485 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 486 | intel_dp->pps_pipe = INVALID_PIPE; |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
| 491 | { |
| 492 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 493 | |
| 494 | if (HAS_PCH_SPLIT(dev)) |
| 495 | return PCH_PP_CONTROL; |
| 496 | else |
| 497 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
| 498 | } |
| 499 | |
| 500 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
| 501 | { |
| 502 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 503 | |
| 504 | if (HAS_PCH_SPLIT(dev)) |
| 505 | return PCH_PP_STATUS; |
| 506 | else |
| 507 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
| 508 | } |
| 509 | |
| 510 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 511 | This function only applicable when panel PM state is not to be tracked */ |
| 512 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 513 | void *unused) |
| 514 | { |
| 515 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| 516 | edp_notifier); |
| 517 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 518 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 519 | u32 pp_div; |
| 520 | u32 pp_ctrl_reg, pp_div_reg; |
| 521 | |
| 522 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
| 523 | return 0; |
| 524 | |
| 525 | pps_lock(intel_dp); |
| 526 | |
| 527 | if (IS_VALLEYVIEW(dev)) { |
| 528 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 529 | |
| 530 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 531 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 532 | pp_div = I915_READ(pp_div_reg); |
| 533 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| 534 | |
| 535 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 536 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| 537 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 538 | msleep(intel_dp->panel_power_cycle_delay); |
| 539 | } |
| 540 | |
| 541 | pps_unlock(intel_dp); |
| 542 | |
| 543 | return 0; |
| 544 | } |
| 545 | |
| 546 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
| 547 | { |
| 548 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 549 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 550 | |
| 551 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 552 | |
| 553 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
| 554 | } |
| 555 | |
| 556 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
| 557 | { |
| 558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 559 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 560 | |
| 561 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 562 | |
| 563 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
| 564 | } |
| 565 | |
| 566 | static void |
| 567 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 568 | { |
| 569 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 570 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 571 | |
| 572 | if (!is_edp(intel_dp)) |
| 573 | return; |
| 574 | |
| 575 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
| 576 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 577 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
| 578 | I915_READ(_pp_stat_reg(intel_dp)), |
| 579 | I915_READ(_pp_ctrl_reg(intel_dp))); |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | static uint32_t |
| 584 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 585 | { |
| 586 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 587 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 588 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 589 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
| 590 | uint32_t status; |
| 591 | bool done; |
| 592 | |
| 593 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 594 | if (has_aux_irq) |
| 595 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
| 596 | msecs_to_jiffies_timeout(10)); |
| 597 | else |
| 598 | done = wait_for_atomic(C, 10) == 0; |
| 599 | if (!done) |
| 600 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 601 | has_aux_irq); |
| 602 | #undef C |
| 603 | |
| 604 | return status; |
| 605 | } |
| 606 | |
| 607 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 608 | { |
| 609 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 610 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 611 | |
| 612 | /* |
| 613 | * The clock divider is based off the hrawclk, and would like to run at |
| 614 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
| 615 | */ |
| 616 | return index ? 0 : intel_hrawclk(dev) / 2; |
| 617 | } |
| 618 | |
| 619 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 620 | { |
| 621 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 622 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 623 | |
| 624 | if (index) |
| 625 | return 0; |
| 626 | |
| 627 | if (intel_dig_port->port == PORT_A) { |
| 628 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 629 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
| 630 | else |
| 631 | return 225; /* eDP input clock at 450Mhz */ |
| 632 | } else { |
| 633 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
| 634 | } |
| 635 | } |
| 636 | |
| 637 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 638 | { |
| 639 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 640 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 641 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 642 | |
| 643 | if (intel_dig_port->port == PORT_A) { |
| 644 | if (index) |
| 645 | return 0; |
| 646 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
| 647 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 648 | /* Workaround for non-ULT HSW */ |
| 649 | switch (index) { |
| 650 | case 0: return 63; |
| 651 | case 1: return 72; |
| 652 | default: return 0; |
| 653 | } |
| 654 | } else { |
| 655 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
| 656 | } |
| 657 | } |
| 658 | |
| 659 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 660 | { |
| 661 | return index ? 0 : 100; |
| 662 | } |
| 663 | |
| 664 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 665 | { |
| 666 | /* |
| 667 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 668 | * derive the clock from CDCLK automatically). We still implement the |
| 669 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 670 | */ |
| 671 | return index ? 0 : 1; |
| 672 | } |
| 673 | |
| 674 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 675 | bool has_aux_irq, |
| 676 | int send_bytes, |
| 677 | uint32_t aux_clock_divider) |
| 678 | { |
| 679 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 680 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 681 | uint32_t precharge, timeout; |
| 682 | |
| 683 | if (IS_GEN6(dev)) |
| 684 | precharge = 3; |
| 685 | else |
| 686 | precharge = 5; |
| 687 | |
| 688 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
| 689 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 690 | else |
| 691 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 692 | |
| 693 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 694 | DP_AUX_CH_CTL_DONE | |
| 695 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 696 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 697 | timeout | |
| 698 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 699 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 700 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 701 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
| 702 | } |
| 703 | |
| 704 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 705 | bool has_aux_irq, |
| 706 | int send_bytes, |
| 707 | uint32_t unused) |
| 708 | { |
| 709 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 710 | DP_AUX_CH_CTL_DONE | |
| 711 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 712 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 713 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
| 714 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 715 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 716 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| 717 | } |
| 718 | |
| 719 | static int |
| 720 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
| 721 | const uint8_t *send, int send_bytes, |
| 722 | uint8_t *recv, int recv_size) |
| 723 | { |
| 724 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 725 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 726 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 727 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
| 728 | uint32_t ch_data = ch_ctl + 4; |
| 729 | uint32_t aux_clock_divider; |
| 730 | int i, ret, recv_bytes; |
| 731 | uint32_t status; |
| 732 | int try, clock = 0; |
| 733 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
| 734 | bool vdd; |
| 735 | |
| 736 | pps_lock(intel_dp); |
| 737 | |
| 738 | /* |
| 739 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 740 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 741 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 742 | * ourselves. |
| 743 | */ |
| 744 | vdd = edp_panel_vdd_on(intel_dp); |
| 745 | |
| 746 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 747 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 748 | * deep sleep states. |
| 749 | */ |
| 750 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
| 751 | |
| 752 | intel_dp_check_edp(intel_dp); |
| 753 | |
| 754 | intel_aux_display_runtime_get(dev_priv); |
| 755 | |
| 756 | /* Try to wait for any previous AUX channel activity */ |
| 757 | for (try = 0; try < 3; try++) { |
| 758 | status = I915_READ_NOTRACE(ch_ctl); |
| 759 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 760 | break; |
| 761 | msleep(1); |
| 762 | } |
| 763 | |
| 764 | if (try == 3) { |
| 765 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 766 | I915_READ(ch_ctl)); |
| 767 | ret = -EBUSY; |
| 768 | goto out; |
| 769 | } |
| 770 | |
| 771 | /* Only 5 data registers! */ |
| 772 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 773 | ret = -E2BIG; |
| 774 | goto out; |
| 775 | } |
| 776 | |
| 777 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
| 778 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 779 | has_aux_irq, |
| 780 | send_bytes, |
| 781 | aux_clock_divider); |
| 782 | |
| 783 | /* Must try at least 3 times according to DP spec */ |
| 784 | for (try = 0; try < 5; try++) { |
| 785 | /* Load the send data into the aux channel data registers */ |
| 786 | for (i = 0; i < send_bytes; i += 4) |
| 787 | I915_WRITE(ch_data + i, |
| 788 | pack_aux(send + i, send_bytes - i)); |
| 789 | |
| 790 | /* Send the command and wait for it to complete */ |
| 791 | I915_WRITE(ch_ctl, send_ctl); |
| 792 | |
| 793 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
| 794 | |
| 795 | /* Clear done status and any errors */ |
| 796 | I915_WRITE(ch_ctl, |
| 797 | status | |
| 798 | DP_AUX_CH_CTL_DONE | |
| 799 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 800 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
| 801 | |
| 802 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 803 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
| 804 | continue; |
| 805 | if (status & DP_AUX_CH_CTL_DONE) |
| 806 | break; |
| 807 | } |
| 808 | if (status & DP_AUX_CH_CTL_DONE) |
| 809 | break; |
| 810 | } |
| 811 | |
| 812 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
| 813 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
| 814 | ret = -EBUSY; |
| 815 | goto out; |
| 816 | } |
| 817 | |
| 818 | /* Check for timeout or receive error. |
| 819 | * Timeouts occur when the sink is not connected |
| 820 | */ |
| 821 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 822 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
| 823 | ret = -EIO; |
| 824 | goto out; |
| 825 | } |
| 826 | |
| 827 | /* Timeouts occur when the device isn't connected, so they're |
| 828 | * "normal" -- don't fill the kernel log with these */ |
| 829 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
| 830 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
| 831 | ret = -ETIMEDOUT; |
| 832 | goto out; |
| 833 | } |
| 834 | |
| 835 | /* Unload any bytes sent back from the other side */ |
| 836 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 837 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
| 838 | if (recv_bytes > recv_size) |
| 839 | recv_bytes = recv_size; |
| 840 | |
| 841 | for (i = 0; i < recv_bytes; i += 4) |
| 842 | unpack_aux(I915_READ(ch_data + i), |
| 843 | recv + i, recv_bytes - i); |
| 844 | |
| 845 | ret = recv_bytes; |
| 846 | out: |
| 847 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 848 | intel_aux_display_runtime_put(dev_priv); |
| 849 | |
| 850 | if (vdd) |
| 851 | edp_panel_vdd_off(intel_dp, false); |
| 852 | |
| 853 | pps_unlock(intel_dp); |
| 854 | |
| 855 | return ret; |
| 856 | } |
| 857 | |
| 858 | #define BARE_ADDRESS_SIZE 3 |
| 859 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
| 860 | static ssize_t |
| 861 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
| 862 | { |
| 863 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 864 | uint8_t txbuf[20], rxbuf[20]; |
| 865 | size_t txsize, rxsize; |
| 866 | int ret; |
| 867 | |
| 868 | txbuf[0] = msg->request << 4; |
| 869 | txbuf[1] = msg->address >> 8; |
| 870 | txbuf[2] = msg->address & 0xff; |
| 871 | txbuf[3] = msg->size - 1; |
| 872 | |
| 873 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 874 | case DP_AUX_NATIVE_WRITE: |
| 875 | case DP_AUX_I2C_WRITE: |
| 876 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
| 877 | rxsize = 1; |
| 878 | |
| 879 | if (WARN_ON(txsize > 20)) |
| 880 | return -E2BIG; |
| 881 | |
| 882 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
| 883 | |
| 884 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 885 | if (ret > 0) { |
| 886 | msg->reply = rxbuf[0] >> 4; |
| 887 | |
| 888 | /* Return payload size. */ |
| 889 | ret = msg->size; |
| 890 | } |
| 891 | break; |
| 892 | |
| 893 | case DP_AUX_NATIVE_READ: |
| 894 | case DP_AUX_I2C_READ: |
| 895 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
| 896 | rxsize = msg->size + 1; |
| 897 | |
| 898 | if (WARN_ON(rxsize > 20)) |
| 899 | return -E2BIG; |
| 900 | |
| 901 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 902 | if (ret > 0) { |
| 903 | msg->reply = rxbuf[0] >> 4; |
| 904 | /* |
| 905 | * Assume happy day, and copy the data. The caller is |
| 906 | * expected to check msg->reply before touching it. |
| 907 | * |
| 908 | * Return payload size. |
| 909 | */ |
| 910 | ret--; |
| 911 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 912 | } |
| 913 | break; |
| 914 | |
| 915 | default: |
| 916 | ret = -EINVAL; |
| 917 | break; |
| 918 | } |
| 919 | |
| 920 | return ret; |
| 921 | } |
| 922 | |
| 923 | static void |
| 924 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
| 925 | { |
| 926 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 927 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 928 | enum port port = intel_dig_port->port; |
| 929 | const char *name = NULL; |
| 930 | int ret; |
| 931 | |
| 932 | switch (port) { |
| 933 | case PORT_A: |
| 934 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
| 935 | name = "DPDDC-A"; |
| 936 | break; |
| 937 | case PORT_B: |
| 938 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
| 939 | name = "DPDDC-B"; |
| 940 | break; |
| 941 | case PORT_C: |
| 942 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
| 943 | name = "DPDDC-C"; |
| 944 | break; |
| 945 | case PORT_D: |
| 946 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
| 947 | name = "DPDDC-D"; |
| 948 | break; |
| 949 | default: |
| 950 | BUG(); |
| 951 | } |
| 952 | |
| 953 | /* |
| 954 | * The AUX_CTL register is usually DP_CTL + 0x10. |
| 955 | * |
| 956 | * On Haswell and Broadwell though: |
| 957 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU |
| 958 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU |
| 959 | * |
| 960 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. |
| 961 | */ |
| 962 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
| 963 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
| 964 | |
| 965 | intel_dp->aux.name = name; |
| 966 | intel_dp->aux.dev = dev->dev; |
| 967 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
| 968 | |
| 969 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
| 970 | connector->base.kdev->kobj.name); |
| 971 | |
| 972 | ret = drm_dp_aux_register(&intel_dp->aux); |
| 973 | if (ret < 0) { |
| 974 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
| 975 | name, ret); |
| 976 | return; |
| 977 | } |
| 978 | |
| 979 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
| 980 | &intel_dp->aux.ddc.dev.kobj, |
| 981 | intel_dp->aux.ddc.dev.kobj.name); |
| 982 | if (ret < 0) { |
| 983 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); |
| 984 | drm_dp_aux_unregister(&intel_dp->aux); |
| 985 | } |
| 986 | } |
| 987 | |
| 988 | static void |
| 989 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
| 990 | { |
| 991 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
| 992 | |
| 993 | if (!intel_connector->mst_port) |
| 994 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
| 995 | intel_dp->aux.ddc.dev.kobj.name); |
| 996 | intel_connector_unregister(intel_connector); |
| 997 | } |
| 998 | |
| 999 | static void |
| 1000 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) |
| 1001 | { |
| 1002 | switch (link_bw) { |
| 1003 | case DP_LINK_BW_1_62: |
| 1004 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; |
| 1005 | break; |
| 1006 | case DP_LINK_BW_2_7: |
| 1007 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; |
| 1008 | break; |
| 1009 | case DP_LINK_BW_5_4: |
| 1010 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; |
| 1011 | break; |
| 1012 | } |
| 1013 | } |
| 1014 | |
| 1015 | static void |
| 1016 | intel_dp_set_clock(struct intel_encoder *encoder, |
| 1017 | struct intel_crtc_config *pipe_config, int link_bw) |
| 1018 | { |
| 1019 | struct drm_device *dev = encoder->base.dev; |
| 1020 | const struct dp_link_dpll *divisor = NULL; |
| 1021 | int i, count = 0; |
| 1022 | |
| 1023 | if (IS_G4X(dev)) { |
| 1024 | divisor = gen4_dpll; |
| 1025 | count = ARRAY_SIZE(gen4_dpll); |
| 1026 | } else if (HAS_PCH_SPLIT(dev)) { |
| 1027 | divisor = pch_dpll; |
| 1028 | count = ARRAY_SIZE(pch_dpll); |
| 1029 | } else if (IS_CHERRYVIEW(dev)) { |
| 1030 | divisor = chv_dpll; |
| 1031 | count = ARRAY_SIZE(chv_dpll); |
| 1032 | } else if (IS_VALLEYVIEW(dev)) { |
| 1033 | divisor = vlv_dpll; |
| 1034 | count = ARRAY_SIZE(vlv_dpll); |
| 1035 | } |
| 1036 | |
| 1037 | if (divisor && count) { |
| 1038 | for (i = 0; i < count; i++) { |
| 1039 | if (link_bw == divisor[i].link_bw) { |
| 1040 | pipe_config->dpll = divisor[i].dpll; |
| 1041 | pipe_config->clock_set = true; |
| 1042 | break; |
| 1043 | } |
| 1044 | } |
| 1045 | } |
| 1046 | } |
| 1047 | |
| 1048 | bool |
| 1049 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 1050 | struct intel_crtc_config *pipe_config) |
| 1051 | { |
| 1052 | struct drm_device *dev = encoder->base.dev; |
| 1053 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1054 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
| 1055 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1056 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1057 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
| 1058 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 1059 | int lane_count, clock; |
| 1060 | int min_lane_count = 1; |
| 1061 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
| 1062 | /* Conveniently, the link BW constants become indices with a shift...*/ |
| 1063 | int min_clock = 0; |
| 1064 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
| 1065 | int bpp, mode_rate; |
| 1066 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
| 1067 | int link_avail, link_clock; |
| 1068 | |
| 1069 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
| 1070 | pipe_config->has_pch_encoder = true; |
| 1071 | |
| 1072 | pipe_config->has_dp_encoder = true; |
| 1073 | pipe_config->has_drrs = false; |
| 1074 | pipe_config->has_audio = intel_dp->has_audio; |
| 1075 | |
| 1076 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 1077 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 1078 | adjusted_mode); |
| 1079 | if (!HAS_PCH_SPLIT(dev)) |
| 1080 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 1081 | intel_connector->panel.fitting_mode); |
| 1082 | else |
| 1083 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 1084 | intel_connector->panel.fitting_mode); |
| 1085 | } |
| 1086 | |
| 1087 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 1088 | return false; |
| 1089 | |
| 1090 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| 1091 | "max bw %02x pixel clock %iKHz\n", |
| 1092 | max_lane_count, bws[max_clock], |
| 1093 | adjusted_mode->crtc_clock); |
| 1094 | |
| 1095 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 1096 | * bpc in between. */ |
| 1097 | bpp = pipe_config->pipe_bpp; |
| 1098 | if (is_edp(intel_dp)) { |
| 1099 | if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { |
| 1100 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
| 1101 | dev_priv->vbt.edp_bpp); |
| 1102 | bpp = dev_priv->vbt.edp_bpp; |
| 1103 | } |
| 1104 | |
| 1105 | /* |
| 1106 | * Use the maximum clock and number of lanes the eDP panel |
| 1107 | * advertizes being capable of. The panels are generally |
| 1108 | * designed to support only a single clock and lane |
| 1109 | * configuration, and typically these values correspond to the |
| 1110 | * native resolution of the panel. |
| 1111 | */ |
| 1112 | min_lane_count = max_lane_count; |
| 1113 | min_clock = max_clock; |
| 1114 | } |
| 1115 | |
| 1116 | for (; bpp >= 6*3; bpp -= 2*3) { |
| 1117 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 1118 | bpp); |
| 1119 | |
| 1120 | for (clock = min_clock; clock <= max_clock; clock++) { |
| 1121 | for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { |
| 1122 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
| 1123 | link_avail = intel_dp_max_data_rate(link_clock, |
| 1124 | lane_count); |
| 1125 | |
| 1126 | if (mode_rate <= link_avail) { |
| 1127 | goto found; |
| 1128 | } |
| 1129 | } |
| 1130 | } |
| 1131 | } |
| 1132 | |
| 1133 | return false; |
| 1134 | |
| 1135 | found: |
| 1136 | if (intel_dp->color_range_auto) { |
| 1137 | /* |
| 1138 | * See: |
| 1139 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 1140 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 1141 | */ |
| 1142 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
| 1143 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 1144 | else |
| 1145 | intel_dp->color_range = 0; |
| 1146 | } |
| 1147 | |
| 1148 | if (intel_dp->color_range) |
| 1149 | pipe_config->limited_color_range = true; |
| 1150 | |
| 1151 | intel_dp->link_bw = bws[clock]; |
| 1152 | intel_dp->lane_count = lane_count; |
| 1153 | pipe_config->pipe_bpp = bpp; |
| 1154 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
| 1155 | |
| 1156 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
| 1157 | intel_dp->link_bw, intel_dp->lane_count, |
| 1158 | pipe_config->port_clock, bpp); |
| 1159 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 1160 | mode_rate, link_avail); |
| 1161 | |
| 1162 | intel_link_compute_m_n(bpp, lane_count, |
| 1163 | adjusted_mode->crtc_clock, |
| 1164 | pipe_config->port_clock, |
| 1165 | &pipe_config->dp_m_n); |
| 1166 | |
| 1167 | if (intel_connector->panel.downclock_mode != NULL && |
| 1168 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
| 1169 | pipe_config->has_drrs = true; |
| 1170 | intel_link_compute_m_n(bpp, lane_count, |
| 1171 | intel_connector->panel.downclock_mode->clock, |
| 1172 | pipe_config->port_clock, |
| 1173 | &pipe_config->dp_m2_n2); |
| 1174 | } |
| 1175 | |
| 1176 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 1177 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
| 1178 | else |
| 1179 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
| 1180 | |
| 1181 | return true; |
| 1182 | } |
| 1183 | |
| 1184 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
| 1185 | { |
| 1186 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1187 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 1188 | struct drm_device *dev = crtc->base.dev; |
| 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1190 | u32 dpa_ctl; |
| 1191 | |
| 1192 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
| 1193 | dpa_ctl = I915_READ(DP_A); |
| 1194 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 1195 | |
| 1196 | if (crtc->config.port_clock == 162000) { |
| 1197 | /* For a long time we've carried around a ILK-DevA w/a for the |
| 1198 | * 160MHz clock. If we're really unlucky, it's still required. |
| 1199 | */ |
| 1200 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
| 1201 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
| 1202 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
| 1203 | } else { |
| 1204 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
| 1205 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 1206 | } |
| 1207 | |
| 1208 | I915_WRITE(DP_A, dpa_ctl); |
| 1209 | |
| 1210 | POSTING_READ(DP_A); |
| 1211 | udelay(500); |
| 1212 | } |
| 1213 | |
| 1214 | static void intel_dp_prepare(struct intel_encoder *encoder) |
| 1215 | { |
| 1216 | struct drm_device *dev = encoder->base.dev; |
| 1217 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1218 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1219 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1220 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 1221 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
| 1222 | |
| 1223 | /* |
| 1224 | * There are four kinds of DP registers: |
| 1225 | * |
| 1226 | * IBX PCH |
| 1227 | * SNB CPU |
| 1228 | * IVB CPU |
| 1229 | * CPT PCH |
| 1230 | * |
| 1231 | * IBX PCH and CPU are the same for almost everything, |
| 1232 | * except that the CPU DP PLL is configured in this |
| 1233 | * register |
| 1234 | * |
| 1235 | * CPT PCH is quite different, having many bits moved |
| 1236 | * to the TRANS_DP_CTL register instead. That |
| 1237 | * configuration happens (oddly) in ironlake_pch_enable |
| 1238 | */ |
| 1239 | |
| 1240 | /* Preserve the BIOS-computed detected bit. This is |
| 1241 | * supposed to be read-only. |
| 1242 | */ |
| 1243 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 1244 | |
| 1245 | /* Handle DP bits in common between all three register formats */ |
| 1246 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 1247 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
| 1248 | |
| 1249 | if (crtc->config.has_audio) { |
| 1250 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
| 1251 | pipe_name(crtc->pipe)); |
| 1252 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
| 1253 | intel_write_eld(encoder); |
| 1254 | } |
| 1255 | |
| 1256 | /* Split out the IBX/CPU vs CPT settings */ |
| 1257 | |
| 1258 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
| 1259 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1260 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1261 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1262 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1263 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1264 | |
| 1265 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1266 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1267 | |
| 1268 | intel_dp->DP |= crtc->pipe << 29; |
| 1269 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
| 1270 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
| 1271 | intel_dp->DP |= intel_dp->color_range; |
| 1272 | |
| 1273 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1274 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1275 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1276 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1277 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1278 | |
| 1279 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1280 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1281 | |
| 1282 | if (!IS_CHERRYVIEW(dev)) { |
| 1283 | if (crtc->pipe == 1) |
| 1284 | intel_dp->DP |= DP_PIPEB_SELECT; |
| 1285 | } else { |
| 1286 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
| 1287 | } |
| 1288 | } else { |
| 1289 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1290 | } |
| 1291 | } |
| 1292 | |
| 1293 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1294 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
| 1295 | |
| 1296 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1297 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
| 1298 | |
| 1299 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1300 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| 1301 | |
| 1302 | static void wait_panel_status(struct intel_dp *intel_dp, |
| 1303 | u32 mask, |
| 1304 | u32 value) |
| 1305 | { |
| 1306 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1307 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1308 | u32 pp_stat_reg, pp_ctrl_reg; |
| 1309 | |
| 1310 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1311 | |
| 1312 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1313 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1314 | |
| 1315 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
| 1316 | mask, value, |
| 1317 | I915_READ(pp_stat_reg), |
| 1318 | I915_READ(pp_ctrl_reg)); |
| 1319 | |
| 1320 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
| 1321 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
| 1322 | I915_READ(pp_stat_reg), |
| 1323 | I915_READ(pp_ctrl_reg)); |
| 1324 | } |
| 1325 | |
| 1326 | DRM_DEBUG_KMS("Wait complete\n"); |
| 1327 | } |
| 1328 | |
| 1329 | static void wait_panel_on(struct intel_dp *intel_dp) |
| 1330 | { |
| 1331 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
| 1332 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
| 1333 | } |
| 1334 | |
| 1335 | static void wait_panel_off(struct intel_dp *intel_dp) |
| 1336 | { |
| 1337 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
| 1338 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
| 1339 | } |
| 1340 | |
| 1341 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
| 1342 | { |
| 1343 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
| 1344 | |
| 1345 | /* When we disable the VDD override bit last we have to do the manual |
| 1346 | * wait. */ |
| 1347 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
| 1348 | intel_dp->panel_power_cycle_delay); |
| 1349 | |
| 1350 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
| 1351 | } |
| 1352 | |
| 1353 | static void wait_backlight_on(struct intel_dp *intel_dp) |
| 1354 | { |
| 1355 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1356 | intel_dp->backlight_on_delay); |
| 1357 | } |
| 1358 | |
| 1359 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
| 1360 | { |
| 1361 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1362 | intel_dp->backlight_off_delay); |
| 1363 | } |
| 1364 | |
| 1365 | /* Read the current pp_control value, unlocking the register if it |
| 1366 | * is locked |
| 1367 | */ |
| 1368 | |
| 1369 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
| 1370 | { |
| 1371 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1372 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1373 | u32 control; |
| 1374 | |
| 1375 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1376 | |
| 1377 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
| 1378 | control &= ~PANEL_UNLOCK_MASK; |
| 1379 | control |= PANEL_UNLOCK_REGS; |
| 1380 | return control; |
| 1381 | } |
| 1382 | |
| 1383 | /* |
| 1384 | * Must be paired with edp_panel_vdd_off(). |
| 1385 | * Must hold pps_mutex around the whole on/off sequence. |
| 1386 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1387 | */ |
| 1388 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 1389 | { |
| 1390 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1391 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1392 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1393 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1394 | enum intel_display_power_domain power_domain; |
| 1395 | u32 pp; |
| 1396 | u32 pp_stat_reg, pp_ctrl_reg; |
| 1397 | bool need_to_disable = !intel_dp->want_panel_vdd; |
| 1398 | |
| 1399 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1400 | |
| 1401 | if (!is_edp(intel_dp)) |
| 1402 | return false; |
| 1403 | |
| 1404 | intel_dp->want_panel_vdd = true; |
| 1405 | |
| 1406 | if (edp_have_panel_vdd(intel_dp)) |
| 1407 | return need_to_disable; |
| 1408 | |
| 1409 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1410 | intel_display_power_get(dev_priv, power_domain); |
| 1411 | |
| 1412 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
| 1413 | |
| 1414 | if (!edp_have_panel_power(intel_dp)) |
| 1415 | wait_panel_power_cycle(intel_dp); |
| 1416 | |
| 1417 | pp = ironlake_get_pp_control(intel_dp); |
| 1418 | pp |= EDP_FORCE_VDD; |
| 1419 | |
| 1420 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1421 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1422 | |
| 1423 | I915_WRITE(pp_ctrl_reg, pp); |
| 1424 | POSTING_READ(pp_ctrl_reg); |
| 1425 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1426 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
| 1427 | /* |
| 1428 | * If the panel wasn't on, delay before accessing aux channel |
| 1429 | */ |
| 1430 | if (!edp_have_panel_power(intel_dp)) { |
| 1431 | DRM_DEBUG_KMS("eDP was not running\n"); |
| 1432 | msleep(intel_dp->panel_power_up_delay); |
| 1433 | } |
| 1434 | |
| 1435 | return need_to_disable; |
| 1436 | } |
| 1437 | |
| 1438 | /* |
| 1439 | * Must be paired with intel_edp_panel_vdd_off() or |
| 1440 | * intel_edp_panel_off(). |
| 1441 | * Nested calls to these functions are not allowed since |
| 1442 | * we drop the lock. Caller must use some higher level |
| 1443 | * locking to prevent nested calls from other threads. |
| 1444 | */ |
| 1445 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 1446 | { |
| 1447 | bool vdd; |
| 1448 | |
| 1449 | if (!is_edp(intel_dp)) |
| 1450 | return; |
| 1451 | |
| 1452 | pps_lock(intel_dp); |
| 1453 | vdd = edp_panel_vdd_on(intel_dp); |
| 1454 | pps_unlock(intel_dp); |
| 1455 | |
| 1456 | WARN(!vdd, "eDP VDD already requested on\n"); |
| 1457 | } |
| 1458 | |
| 1459 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
| 1460 | { |
| 1461 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1462 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1463 | struct intel_digital_port *intel_dig_port = |
| 1464 | dp_to_dig_port(intel_dp); |
| 1465 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1466 | enum intel_display_power_domain power_domain; |
| 1467 | u32 pp; |
| 1468 | u32 pp_stat_reg, pp_ctrl_reg; |
| 1469 | |
| 1470 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1471 | |
| 1472 | WARN_ON(intel_dp->want_panel_vdd); |
| 1473 | |
| 1474 | if (!edp_have_panel_vdd(intel_dp)) |
| 1475 | return; |
| 1476 | |
| 1477 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
| 1478 | |
| 1479 | pp = ironlake_get_pp_control(intel_dp); |
| 1480 | pp &= ~EDP_FORCE_VDD; |
| 1481 | |
| 1482 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1483 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1484 | |
| 1485 | I915_WRITE(pp_ctrl_reg, pp); |
| 1486 | POSTING_READ(pp_ctrl_reg); |
| 1487 | |
| 1488 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 1489 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1490 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
| 1491 | |
| 1492 | if ((pp & POWER_TARGET_ON) == 0) |
| 1493 | intel_dp->last_power_cycle = jiffies; |
| 1494 | |
| 1495 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1496 | intel_display_power_put(dev_priv, power_domain); |
| 1497 | } |
| 1498 | |
| 1499 | static void edp_panel_vdd_work(struct work_struct *__work) |
| 1500 | { |
| 1501 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1502 | struct intel_dp, panel_vdd_work); |
| 1503 | |
| 1504 | pps_lock(intel_dp); |
| 1505 | if (!intel_dp->want_panel_vdd) |
| 1506 | edp_panel_vdd_off_sync(intel_dp); |
| 1507 | pps_unlock(intel_dp); |
| 1508 | } |
| 1509 | |
| 1510 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 1511 | { |
| 1512 | unsigned long delay; |
| 1513 | |
| 1514 | /* |
| 1515 | * Queue the timer to fire a long time from now (relative to the power |
| 1516 | * down delay) to keep the panel power up across a sequence of |
| 1517 | * operations. |
| 1518 | */ |
| 1519 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| 1520 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 1521 | } |
| 1522 | |
| 1523 | /* |
| 1524 | * Must be paired with edp_panel_vdd_on(). |
| 1525 | * Must hold pps_mutex around the whole on/off sequence. |
| 1526 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1527 | */ |
| 1528 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
| 1529 | { |
| 1530 | struct drm_i915_private *dev_priv = |
| 1531 | intel_dp_to_dev(intel_dp)->dev_private; |
| 1532 | |
| 1533 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1534 | |
| 1535 | if (!is_edp(intel_dp)) |
| 1536 | return; |
| 1537 | |
| 1538 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
| 1539 | |
| 1540 | intel_dp->want_panel_vdd = false; |
| 1541 | |
| 1542 | if (sync) |
| 1543 | edp_panel_vdd_off_sync(intel_dp); |
| 1544 | else |
| 1545 | edp_panel_vdd_schedule_off(intel_dp); |
| 1546 | } |
| 1547 | |
| 1548 | /* |
| 1549 | * Must be paired with intel_edp_panel_vdd_on(). |
| 1550 | * Nested calls to these functions are not allowed since |
| 1551 | * we drop the lock. Caller must use some higher level |
| 1552 | * locking to prevent nested calls from other threads. |
| 1553 | */ |
| 1554 | static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
| 1555 | { |
| 1556 | if (!is_edp(intel_dp)) |
| 1557 | return; |
| 1558 | |
| 1559 | pps_lock(intel_dp); |
| 1560 | edp_panel_vdd_off(intel_dp, sync); |
| 1561 | pps_unlock(intel_dp); |
| 1562 | } |
| 1563 | |
| 1564 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 1565 | { |
| 1566 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1567 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1568 | u32 pp; |
| 1569 | u32 pp_ctrl_reg; |
| 1570 | |
| 1571 | if (!is_edp(intel_dp)) |
| 1572 | return; |
| 1573 | |
| 1574 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
| 1575 | |
| 1576 | pps_lock(intel_dp); |
| 1577 | |
| 1578 | if (edp_have_panel_power(intel_dp)) { |
| 1579 | DRM_DEBUG_KMS("eDP power already on\n"); |
| 1580 | goto out; |
| 1581 | } |
| 1582 | |
| 1583 | wait_panel_power_cycle(intel_dp); |
| 1584 | |
| 1585 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1586 | pp = ironlake_get_pp_control(intel_dp); |
| 1587 | if (IS_GEN5(dev)) { |
| 1588 | /* ILK workaround: disable reset around power sequence */ |
| 1589 | pp &= ~PANEL_POWER_RESET; |
| 1590 | I915_WRITE(pp_ctrl_reg, pp); |
| 1591 | POSTING_READ(pp_ctrl_reg); |
| 1592 | } |
| 1593 | |
| 1594 | pp |= POWER_TARGET_ON; |
| 1595 | if (!IS_GEN5(dev)) |
| 1596 | pp |= PANEL_POWER_RESET; |
| 1597 | |
| 1598 | I915_WRITE(pp_ctrl_reg, pp); |
| 1599 | POSTING_READ(pp_ctrl_reg); |
| 1600 | |
| 1601 | wait_panel_on(intel_dp); |
| 1602 | intel_dp->last_power_on = jiffies; |
| 1603 | |
| 1604 | if (IS_GEN5(dev)) { |
| 1605 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| 1606 | I915_WRITE(pp_ctrl_reg, pp); |
| 1607 | POSTING_READ(pp_ctrl_reg); |
| 1608 | } |
| 1609 | |
| 1610 | out: |
| 1611 | pps_unlock(intel_dp); |
| 1612 | } |
| 1613 | |
| 1614 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 1615 | { |
| 1616 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1617 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1618 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1619 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1620 | enum intel_display_power_domain power_domain; |
| 1621 | u32 pp; |
| 1622 | u32 pp_ctrl_reg; |
| 1623 | |
| 1624 | if (!is_edp(intel_dp)) |
| 1625 | return; |
| 1626 | |
| 1627 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
| 1628 | |
| 1629 | pps_lock(intel_dp); |
| 1630 | |
| 1631 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
| 1632 | |
| 1633 | pp = ironlake_get_pp_control(intel_dp); |
| 1634 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 1635 | * panels get very unhappy and cease to work. */ |
| 1636 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 1637 | EDP_BLC_ENABLE); |
| 1638 | |
| 1639 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1640 | |
| 1641 | intel_dp->want_panel_vdd = false; |
| 1642 | |
| 1643 | I915_WRITE(pp_ctrl_reg, pp); |
| 1644 | POSTING_READ(pp_ctrl_reg); |
| 1645 | |
| 1646 | intel_dp->last_power_cycle = jiffies; |
| 1647 | wait_panel_off(intel_dp); |
| 1648 | |
| 1649 | /* We got a reference when we enabled the VDD. */ |
| 1650 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1651 | intel_display_power_put(dev_priv, power_domain); |
| 1652 | |
| 1653 | pps_unlock(intel_dp); |
| 1654 | } |
| 1655 | |
| 1656 | /* Enable backlight in the panel power control. */ |
| 1657 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 1658 | { |
| 1659 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1660 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 1661 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1662 | u32 pp; |
| 1663 | u32 pp_ctrl_reg; |
| 1664 | |
| 1665 | /* |
| 1666 | * If we enable the backlight right away following a panel power |
| 1667 | * on, we may see slight flicker as the panel syncs with the eDP |
| 1668 | * link. So delay a bit to make sure the image is solid before |
| 1669 | * allowing it to appear. |
| 1670 | */ |
| 1671 | wait_backlight_on(intel_dp); |
| 1672 | |
| 1673 | pps_lock(intel_dp); |
| 1674 | |
| 1675 | pp = ironlake_get_pp_control(intel_dp); |
| 1676 | pp |= EDP_BLC_ENABLE; |
| 1677 | |
| 1678 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1679 | |
| 1680 | I915_WRITE(pp_ctrl_reg, pp); |
| 1681 | POSTING_READ(pp_ctrl_reg); |
| 1682 | |
| 1683 | pps_unlock(intel_dp); |
| 1684 | } |
| 1685 | |
| 1686 | /* Enable backlight PWM and backlight PP control. */ |
| 1687 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 1688 | { |
| 1689 | if (!is_edp(intel_dp)) |
| 1690 | return; |
| 1691 | |
| 1692 | DRM_DEBUG_KMS("\n"); |
| 1693 | |
| 1694 | intel_panel_enable_backlight(intel_dp->attached_connector); |
| 1695 | _intel_edp_backlight_on(intel_dp); |
| 1696 | } |
| 1697 | |
| 1698 | /* Disable backlight in the panel power control. */ |
| 1699 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 1700 | { |
| 1701 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1702 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1703 | u32 pp; |
| 1704 | u32 pp_ctrl_reg; |
| 1705 | |
| 1706 | if (!is_edp(intel_dp)) |
| 1707 | return; |
| 1708 | |
| 1709 | pps_lock(intel_dp); |
| 1710 | |
| 1711 | pp = ironlake_get_pp_control(intel_dp); |
| 1712 | pp &= ~EDP_BLC_ENABLE; |
| 1713 | |
| 1714 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1715 | |
| 1716 | I915_WRITE(pp_ctrl_reg, pp); |
| 1717 | POSTING_READ(pp_ctrl_reg); |
| 1718 | |
| 1719 | pps_unlock(intel_dp); |
| 1720 | |
| 1721 | intel_dp->last_backlight_off = jiffies; |
| 1722 | edp_wait_backlight_off(intel_dp); |
| 1723 | } |
| 1724 | |
| 1725 | /* Disable backlight PP control and backlight PWM. */ |
| 1726 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 1727 | { |
| 1728 | if (!is_edp(intel_dp)) |
| 1729 | return; |
| 1730 | |
| 1731 | DRM_DEBUG_KMS("\n"); |
| 1732 | |
| 1733 | _intel_edp_backlight_off(intel_dp); |
| 1734 | intel_panel_disable_backlight(intel_dp->attached_connector); |
| 1735 | } |
| 1736 | |
| 1737 | /* |
| 1738 | * Hook for controlling the panel power control backlight through the bl_power |
| 1739 | * sysfs attribute. Take care to handle multiple calls. |
| 1740 | */ |
| 1741 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 1742 | bool enable) |
| 1743 | { |
| 1744 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
| 1745 | bool is_enabled; |
| 1746 | |
| 1747 | pps_lock(intel_dp); |
| 1748 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
| 1749 | pps_unlock(intel_dp); |
| 1750 | |
| 1751 | if (is_enabled == enable) |
| 1752 | return; |
| 1753 | |
| 1754 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
| 1755 | enable ? "enable" : "disable"); |
| 1756 | |
| 1757 | if (enable) |
| 1758 | _intel_edp_backlight_on(intel_dp); |
| 1759 | else |
| 1760 | _intel_edp_backlight_off(intel_dp); |
| 1761 | } |
| 1762 | |
| 1763 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
| 1764 | { |
| 1765 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1766 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1767 | struct drm_device *dev = crtc->dev; |
| 1768 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1769 | u32 dpa_ctl; |
| 1770 | |
| 1771 | assert_pipe_disabled(dev_priv, |
| 1772 | to_intel_crtc(crtc)->pipe); |
| 1773 | |
| 1774 | DRM_DEBUG_KMS("\n"); |
| 1775 | dpa_ctl = I915_READ(DP_A); |
| 1776 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
| 1777 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1778 | |
| 1779 | /* We don't adjust intel_dp->DP while tearing down the link, to |
| 1780 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
| 1781 | * enable bits here to ensure that we don't enable too much. */ |
| 1782 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 1783 | intel_dp->DP |= DP_PLL_ENABLE; |
| 1784 | I915_WRITE(DP_A, intel_dp->DP); |
| 1785 | POSTING_READ(DP_A); |
| 1786 | udelay(200); |
| 1787 | } |
| 1788 | |
| 1789 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
| 1790 | { |
| 1791 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1792 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1793 | struct drm_device *dev = crtc->dev; |
| 1794 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1795 | u32 dpa_ctl; |
| 1796 | |
| 1797 | assert_pipe_disabled(dev_priv, |
| 1798 | to_intel_crtc(crtc)->pipe); |
| 1799 | |
| 1800 | dpa_ctl = I915_READ(DP_A); |
| 1801 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
| 1802 | "dp pll off, should be on\n"); |
| 1803 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1804 | |
| 1805 | /* We can't rely on the value tracked for the DP register in |
| 1806 | * intel_dp->DP because link_down must not change that (otherwise link |
| 1807 | * re-training will fail. */ |
| 1808 | dpa_ctl &= ~DP_PLL_ENABLE; |
| 1809 | I915_WRITE(DP_A, dpa_ctl); |
| 1810 | POSTING_READ(DP_A); |
| 1811 | udelay(200); |
| 1812 | } |
| 1813 | |
| 1814 | /* If the sink supports it, try to set the power state appropriately */ |
| 1815 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
| 1816 | { |
| 1817 | int ret, i; |
| 1818 | |
| 1819 | /* Should have a valid DPCD by this point */ |
| 1820 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 1821 | return; |
| 1822 | |
| 1823 | if (mode != DRM_MODE_DPMS_ON) { |
| 1824 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 1825 | DP_SET_POWER_D3); |
| 1826 | } else { |
| 1827 | /* |
| 1828 | * When turning on, we need to retry for 1ms to give the sink |
| 1829 | * time to wake up. |
| 1830 | */ |
| 1831 | for (i = 0; i < 3; i++) { |
| 1832 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 1833 | DP_SET_POWER_D0); |
| 1834 | if (ret == 1) |
| 1835 | break; |
| 1836 | msleep(1); |
| 1837 | } |
| 1838 | } |
| 1839 | |
| 1840 | if (ret != 1) |
| 1841 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
| 1842 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
| 1843 | } |
| 1844 | |
| 1845 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 1846 | enum pipe *pipe) |
| 1847 | { |
| 1848 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1849 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1850 | struct drm_device *dev = encoder->base.dev; |
| 1851 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1852 | enum intel_display_power_domain power_domain; |
| 1853 | u32 tmp; |
| 1854 | |
| 1855 | power_domain = intel_display_port_power_domain(encoder); |
| 1856 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
| 1857 | return false; |
| 1858 | |
| 1859 | tmp = I915_READ(intel_dp->output_reg); |
| 1860 | |
| 1861 | if (!(tmp & DP_PORT_EN)) |
| 1862 | return false; |
| 1863 | |
| 1864 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
| 1865 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 1866 | } else if (IS_CHERRYVIEW(dev)) { |
| 1867 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
| 1868 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
| 1869 | *pipe = PORT_TO_PIPE(tmp); |
| 1870 | } else { |
| 1871 | u32 trans_sel; |
| 1872 | u32 trans_dp; |
| 1873 | int i; |
| 1874 | |
| 1875 | switch (intel_dp->output_reg) { |
| 1876 | case PCH_DP_B: |
| 1877 | trans_sel = TRANS_DP_PORT_SEL_B; |
| 1878 | break; |
| 1879 | case PCH_DP_C: |
| 1880 | trans_sel = TRANS_DP_PORT_SEL_C; |
| 1881 | break; |
| 1882 | case PCH_DP_D: |
| 1883 | trans_sel = TRANS_DP_PORT_SEL_D; |
| 1884 | break; |
| 1885 | default: |
| 1886 | return true; |
| 1887 | } |
| 1888 | |
| 1889 | for_each_pipe(dev_priv, i) { |
| 1890 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
| 1891 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
| 1892 | *pipe = i; |
| 1893 | return true; |
| 1894 | } |
| 1895 | } |
| 1896 | |
| 1897 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
| 1898 | intel_dp->output_reg); |
| 1899 | } |
| 1900 | |
| 1901 | return true; |
| 1902 | } |
| 1903 | |
| 1904 | static void intel_dp_get_config(struct intel_encoder *encoder, |
| 1905 | struct intel_crtc_config *pipe_config) |
| 1906 | { |
| 1907 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1908 | u32 tmp, flags = 0; |
| 1909 | struct drm_device *dev = encoder->base.dev; |
| 1910 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1911 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1912 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 1913 | int dotclock; |
| 1914 | |
| 1915 | tmp = I915_READ(intel_dp->output_reg); |
| 1916 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) |
| 1917 | pipe_config->has_audio = true; |
| 1918 | |
| 1919 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
| 1920 | if (tmp & DP_SYNC_HS_HIGH) |
| 1921 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1922 | else |
| 1923 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 1924 | |
| 1925 | if (tmp & DP_SYNC_VS_HIGH) |
| 1926 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1927 | else |
| 1928 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1929 | } else { |
| 1930 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1931 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
| 1932 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1933 | else |
| 1934 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 1935 | |
| 1936 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
| 1937 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1938 | else |
| 1939 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1940 | } |
| 1941 | |
| 1942 | pipe_config->adjusted_mode.flags |= flags; |
| 1943 | |
| 1944 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
| 1945 | tmp & DP_COLOR_RANGE_16_235) |
| 1946 | pipe_config->limited_color_range = true; |
| 1947 | |
| 1948 | pipe_config->has_dp_encoder = true; |
| 1949 | |
| 1950 | intel_dp_get_m_n(crtc, pipe_config); |
| 1951 | |
| 1952 | if (port == PORT_A) { |
| 1953 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
| 1954 | pipe_config->port_clock = 162000; |
| 1955 | else |
| 1956 | pipe_config->port_clock = 270000; |
| 1957 | } |
| 1958 | |
| 1959 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
| 1960 | &pipe_config->dp_m_n); |
| 1961 | |
| 1962 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
| 1963 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
| 1964 | |
| 1965 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
| 1966 | |
| 1967 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
| 1968 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
| 1969 | /* |
| 1970 | * This is a big fat ugly hack. |
| 1971 | * |
| 1972 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 1973 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 1974 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 1975 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 1976 | * max, not what it tells us to use. |
| 1977 | * |
| 1978 | * Note: This will still be broken if the eDP panel is not lit |
| 1979 | * up by the BIOS, and thus we can't get the mode at module |
| 1980 | * load. |
| 1981 | */ |
| 1982 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
| 1983 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
| 1984 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
| 1985 | } |
| 1986 | } |
| 1987 | |
| 1988 | static bool is_edp_psr(struct intel_dp *intel_dp) |
| 1989 | { |
| 1990 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
| 1991 | } |
| 1992 | |
| 1993 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
| 1994 | { |
| 1995 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1996 | |
| 1997 | if (!HAS_PSR(dev)) |
| 1998 | return false; |
| 1999 | |
| 2000 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
| 2001 | } |
| 2002 | |
| 2003 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
| 2004 | struct edp_vsc_psr *vsc_psr) |
| 2005 | { |
| 2006 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2007 | struct drm_device *dev = dig_port->base.base.dev; |
| 2008 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2009 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 2010 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
| 2011 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
| 2012 | uint32_t *data = (uint32_t *) vsc_psr; |
| 2013 | unsigned int i; |
| 2014 | |
| 2015 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
| 2016 | the video DIP being updated before program video DIP data buffer |
| 2017 | registers for DIP being updated. */ |
| 2018 | I915_WRITE(ctl_reg, 0); |
| 2019 | POSTING_READ(ctl_reg); |
| 2020 | |
| 2021 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
| 2022 | if (i < sizeof(struct edp_vsc_psr)) |
| 2023 | I915_WRITE(data_reg + i, *data++); |
| 2024 | else |
| 2025 | I915_WRITE(data_reg + i, 0); |
| 2026 | } |
| 2027 | |
| 2028 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
| 2029 | POSTING_READ(ctl_reg); |
| 2030 | } |
| 2031 | |
| 2032 | static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp) |
| 2033 | { |
| 2034 | struct edp_vsc_psr psr_vsc; |
| 2035 | |
| 2036 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
| 2037 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
| 2038 | psr_vsc.sdp_header.HB0 = 0; |
| 2039 | psr_vsc.sdp_header.HB1 = 0x7; |
| 2040 | psr_vsc.sdp_header.HB2 = 0x2; |
| 2041 | psr_vsc.sdp_header.HB3 = 0x8; |
| 2042 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
| 2043 | } |
| 2044 | |
| 2045 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
| 2046 | { |
| 2047 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2048 | struct drm_device *dev = dig_port->base.base.dev; |
| 2049 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2050 | uint32_t aux_clock_divider; |
| 2051 | int precharge = 0x3; |
| 2052 | bool only_standby = false; |
| 2053 | static const uint8_t aux_msg[] = { |
| 2054 | [0] = DP_AUX_NATIVE_WRITE << 4, |
| 2055 | [1] = DP_SET_POWER >> 8, |
| 2056 | [2] = DP_SET_POWER & 0xff, |
| 2057 | [3] = 1 - 1, |
| 2058 | [4] = DP_SET_POWER_D0, |
| 2059 | }; |
| 2060 | int i; |
| 2061 | |
| 2062 | BUILD_BUG_ON(sizeof(aux_msg) > 20); |
| 2063 | |
| 2064 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
| 2065 | |
| 2066 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
| 2067 | only_standby = true; |
| 2068 | |
| 2069 | /* Enable PSR in sink */ |
| 2070 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) |
| 2071 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
| 2072 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
| 2073 | else |
| 2074 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
| 2075 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
| 2076 | |
| 2077 | /* Setup AUX registers */ |
| 2078 | for (i = 0; i < sizeof(aux_msg); i += 4) |
| 2079 | I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i, |
| 2080 | pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
| 2081 | |
| 2082 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
| 2083 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 2084 | (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 2085 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 2086 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
| 2087 | } |
| 2088 | |
| 2089 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
| 2090 | { |
| 2091 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2092 | struct drm_device *dev = dig_port->base.base.dev; |
| 2093 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2094 | uint32_t max_sleep_time = 0x1f; |
| 2095 | uint32_t idle_frames = 1; |
| 2096 | uint32_t val = 0x0; |
| 2097 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
| 2098 | bool only_standby = false; |
| 2099 | |
| 2100 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
| 2101 | only_standby = true; |
| 2102 | |
| 2103 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { |
| 2104 | val |= EDP_PSR_LINK_STANDBY; |
| 2105 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
| 2106 | val |= EDP_PSR_TP1_TIME_0us; |
| 2107 | val |= EDP_PSR_SKIP_AUX_EXIT; |
| 2108 | val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; |
| 2109 | } else |
| 2110 | val |= EDP_PSR_LINK_DISABLE; |
| 2111 | |
| 2112 | I915_WRITE(EDP_PSR_CTL(dev), val | |
| 2113 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
| 2114 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
| 2115 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
| 2116 | EDP_PSR_ENABLE); |
| 2117 | } |
| 2118 | |
| 2119 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
| 2120 | { |
| 2121 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2122 | struct drm_device *dev = dig_port->base.base.dev; |
| 2123 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2124 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 2125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2126 | |
| 2127 | lockdep_assert_held(&dev_priv->psr.lock); |
| 2128 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 2129 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); |
| 2130 | |
| 2131 | dev_priv->psr.source_ok = false; |
| 2132 | |
| 2133 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
| 2134 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
| 2135 | return false; |
| 2136 | } |
| 2137 | |
| 2138 | if (!i915.enable_psr) { |
| 2139 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
| 2140 | return false; |
| 2141 | } |
| 2142 | |
| 2143 | /* Below limitations aren't valid for Broadwell */ |
| 2144 | if (IS_BROADWELL(dev)) |
| 2145 | goto out; |
| 2146 | |
| 2147 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
| 2148 | S3D_ENABLE) { |
| 2149 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
| 2150 | return false; |
| 2151 | } |
| 2152 | |
| 2153 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
| 2154 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
| 2155 | return false; |
| 2156 | } |
| 2157 | |
| 2158 | out: |
| 2159 | dev_priv->psr.source_ok = true; |
| 2160 | return true; |
| 2161 | } |
| 2162 | |
| 2163 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
| 2164 | { |
| 2165 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2166 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2167 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2168 | |
| 2169 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
| 2170 | WARN_ON(dev_priv->psr.active); |
| 2171 | lockdep_assert_held(&dev_priv->psr.lock); |
| 2172 | |
| 2173 | /* Enable/Re-enable PSR on the host */ |
| 2174 | intel_edp_psr_enable_source(intel_dp); |
| 2175 | |
| 2176 | dev_priv->psr.active = true; |
| 2177 | } |
| 2178 | |
| 2179 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
| 2180 | { |
| 2181 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2182 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2183 | |
| 2184 | if (!HAS_PSR(dev)) { |
| 2185 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
| 2186 | return; |
| 2187 | } |
| 2188 | |
| 2189 | if (!is_edp_psr(intel_dp)) { |
| 2190 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); |
| 2191 | return; |
| 2192 | } |
| 2193 | |
| 2194 | mutex_lock(&dev_priv->psr.lock); |
| 2195 | if (dev_priv->psr.enabled) { |
| 2196 | DRM_DEBUG_KMS("PSR already in use\n"); |
| 2197 | goto unlock; |
| 2198 | } |
| 2199 | |
| 2200 | if (!intel_edp_psr_match_conditions(intel_dp)) |
| 2201 | goto unlock; |
| 2202 | |
| 2203 | dev_priv->psr.busy_frontbuffer_bits = 0; |
| 2204 | |
| 2205 | intel_edp_psr_setup_vsc(intel_dp); |
| 2206 | |
| 2207 | /* Avoid continuous PSR exit by masking memup and hpd */ |
| 2208 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
| 2209 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
| 2210 | |
| 2211 | /* Enable PSR on the panel */ |
| 2212 | intel_edp_psr_enable_sink(intel_dp); |
| 2213 | |
| 2214 | dev_priv->psr.enabled = intel_dp; |
| 2215 | unlock: |
| 2216 | mutex_unlock(&dev_priv->psr.lock); |
| 2217 | } |
| 2218 | |
| 2219 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
| 2220 | { |
| 2221 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2222 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2223 | |
| 2224 | mutex_lock(&dev_priv->psr.lock); |
| 2225 | if (!dev_priv->psr.enabled) { |
| 2226 | mutex_unlock(&dev_priv->psr.lock); |
| 2227 | return; |
| 2228 | } |
| 2229 | |
| 2230 | if (dev_priv->psr.active) { |
| 2231 | I915_WRITE(EDP_PSR_CTL(dev), |
| 2232 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
| 2233 | |
| 2234 | /* Wait till PSR is idle */ |
| 2235 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
| 2236 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
| 2237 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
| 2238 | |
| 2239 | dev_priv->psr.active = false; |
| 2240 | } else { |
| 2241 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
| 2242 | } |
| 2243 | |
| 2244 | dev_priv->psr.enabled = NULL; |
| 2245 | mutex_unlock(&dev_priv->psr.lock); |
| 2246 | |
| 2247 | cancel_delayed_work_sync(&dev_priv->psr.work); |
| 2248 | } |
| 2249 | |
| 2250 | static void intel_edp_psr_work(struct work_struct *work) |
| 2251 | { |
| 2252 | struct drm_i915_private *dev_priv = |
| 2253 | container_of(work, typeof(*dev_priv), psr.work.work); |
| 2254 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
| 2255 | |
| 2256 | /* We have to make sure PSR is ready for re-enable |
| 2257 | * otherwise it keeps disabled until next full enable/disable cycle. |
| 2258 | * PSR might take some time to get fully disabled |
| 2259 | * and be ready for re-enable. |
| 2260 | */ |
| 2261 | if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & |
| 2262 | EDP_PSR_STATUS_STATE_MASK) == 0, 50)) { |
| 2263 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); |
| 2264 | return; |
| 2265 | } |
| 2266 | |
| 2267 | mutex_lock(&dev_priv->psr.lock); |
| 2268 | intel_dp = dev_priv->psr.enabled; |
| 2269 | |
| 2270 | if (!intel_dp) |
| 2271 | goto unlock; |
| 2272 | |
| 2273 | /* |
| 2274 | * The delayed work can race with an invalidate hence we need to |
| 2275 | * recheck. Since psr_flush first clears this and then reschedules we |
| 2276 | * won't ever miss a flush when bailing out here. |
| 2277 | */ |
| 2278 | if (dev_priv->psr.busy_frontbuffer_bits) |
| 2279 | goto unlock; |
| 2280 | |
| 2281 | intel_edp_psr_do_enable(intel_dp); |
| 2282 | unlock: |
| 2283 | mutex_unlock(&dev_priv->psr.lock); |
| 2284 | } |
| 2285 | |
| 2286 | static void intel_edp_psr_do_exit(struct drm_device *dev) |
| 2287 | { |
| 2288 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2289 | |
| 2290 | if (dev_priv->psr.active) { |
| 2291 | u32 val = I915_READ(EDP_PSR_CTL(dev)); |
| 2292 | |
| 2293 | WARN_ON(!(val & EDP_PSR_ENABLE)); |
| 2294 | |
| 2295 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); |
| 2296 | |
| 2297 | dev_priv->psr.active = false; |
| 2298 | } |
| 2299 | |
| 2300 | } |
| 2301 | |
| 2302 | void intel_edp_psr_invalidate(struct drm_device *dev, |
| 2303 | unsigned frontbuffer_bits) |
| 2304 | { |
| 2305 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2306 | struct drm_crtc *crtc; |
| 2307 | enum pipe pipe; |
| 2308 | |
| 2309 | mutex_lock(&dev_priv->psr.lock); |
| 2310 | if (!dev_priv->psr.enabled) { |
| 2311 | mutex_unlock(&dev_priv->psr.lock); |
| 2312 | return; |
| 2313 | } |
| 2314 | |
| 2315 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
| 2316 | pipe = to_intel_crtc(crtc)->pipe; |
| 2317 | |
| 2318 | intel_edp_psr_do_exit(dev); |
| 2319 | |
| 2320 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 2321 | |
| 2322 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
| 2323 | mutex_unlock(&dev_priv->psr.lock); |
| 2324 | } |
| 2325 | |
| 2326 | void intel_edp_psr_flush(struct drm_device *dev, |
| 2327 | unsigned frontbuffer_bits) |
| 2328 | { |
| 2329 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2330 | struct drm_crtc *crtc; |
| 2331 | enum pipe pipe; |
| 2332 | |
| 2333 | mutex_lock(&dev_priv->psr.lock); |
| 2334 | if (!dev_priv->psr.enabled) { |
| 2335 | mutex_unlock(&dev_priv->psr.lock); |
| 2336 | return; |
| 2337 | } |
| 2338 | |
| 2339 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; |
| 2340 | pipe = to_intel_crtc(crtc)->pipe; |
| 2341 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
| 2342 | |
| 2343 | /* |
| 2344 | * On Haswell sprite plane updates don't result in a psr invalidating |
| 2345 | * signal in the hardware. Which means we need to manually fake this in |
| 2346 | * software for all flushes, not just when we've seen a preceding |
| 2347 | * invalidation through frontbuffer rendering. |
| 2348 | */ |
| 2349 | if (IS_HASWELL(dev) && |
| 2350 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) |
| 2351 | intel_edp_psr_do_exit(dev); |
| 2352 | |
| 2353 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
| 2354 | schedule_delayed_work(&dev_priv->psr.work, |
| 2355 | msecs_to_jiffies(100)); |
| 2356 | mutex_unlock(&dev_priv->psr.lock); |
| 2357 | } |
| 2358 | |
| 2359 | void intel_edp_psr_init(struct drm_device *dev) |
| 2360 | { |
| 2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2362 | |
| 2363 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); |
| 2364 | mutex_init(&dev_priv->psr.lock); |
| 2365 | } |
| 2366 | |
| 2367 | static void intel_disable_dp(struct intel_encoder *encoder) |
| 2368 | { |
| 2369 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2370 | struct drm_device *dev = encoder->base.dev; |
| 2371 | |
| 2372 | /* Make sure the panel is off before trying to change the mode. But also |
| 2373 | * ensure that we have vdd while we switch off the panel. */ |
| 2374 | intel_edp_panel_vdd_on(intel_dp); |
| 2375 | intel_edp_backlight_off(intel_dp); |
| 2376 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
| 2377 | intel_edp_panel_off(intel_dp); |
| 2378 | |
| 2379 | /* disable the port before the pipe on g4x */ |
| 2380 | if (INTEL_INFO(dev)->gen < 5) |
| 2381 | intel_dp_link_down(intel_dp); |
| 2382 | } |
| 2383 | |
| 2384 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
| 2385 | { |
| 2386 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2387 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2388 | |
| 2389 | intel_dp_link_down(intel_dp); |
| 2390 | if (port == PORT_A) |
| 2391 | ironlake_edp_pll_off(intel_dp); |
| 2392 | } |
| 2393 | |
| 2394 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
| 2395 | { |
| 2396 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2397 | |
| 2398 | intel_dp_link_down(intel_dp); |
| 2399 | } |
| 2400 | |
| 2401 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
| 2402 | { |
| 2403 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2404 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2405 | struct drm_device *dev = encoder->base.dev; |
| 2406 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2407 | struct intel_crtc *intel_crtc = |
| 2408 | to_intel_crtc(encoder->base.crtc); |
| 2409 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2410 | enum pipe pipe = intel_crtc->pipe; |
| 2411 | u32 val; |
| 2412 | |
| 2413 | intel_dp_link_down(intel_dp); |
| 2414 | |
| 2415 | mutex_lock(&dev_priv->dpio_lock); |
| 2416 | |
| 2417 | /* Propagate soft reset to data lane reset */ |
| 2418 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
| 2419 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2420 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
| 2421 | |
| 2422 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
| 2423 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2424 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
| 2425 | |
| 2426 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
| 2427 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2428 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
| 2429 | |
| 2430 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
| 2431 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2432 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
| 2433 | |
| 2434 | mutex_unlock(&dev_priv->dpio_lock); |
| 2435 | } |
| 2436 | |
| 2437 | static void |
| 2438 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 2439 | uint32_t *DP, |
| 2440 | uint8_t dp_train_pat) |
| 2441 | { |
| 2442 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2443 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2444 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2445 | enum port port = intel_dig_port->port; |
| 2446 | |
| 2447 | if (HAS_DDI(dev)) { |
| 2448 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
| 2449 | |
| 2450 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2451 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2452 | else |
| 2453 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2454 | |
| 2455 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2456 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2457 | case DP_TRAINING_PATTERN_DISABLE: |
| 2458 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2459 | |
| 2460 | break; |
| 2461 | case DP_TRAINING_PATTERN_1: |
| 2462 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2463 | break; |
| 2464 | case DP_TRAINING_PATTERN_2: |
| 2465 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2466 | break; |
| 2467 | case DP_TRAINING_PATTERN_3: |
| 2468 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2469 | break; |
| 2470 | } |
| 2471 | I915_WRITE(DP_TP_CTL(port), temp); |
| 2472 | |
| 2473 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
| 2474 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 2475 | |
| 2476 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2477 | case DP_TRAINING_PATTERN_DISABLE: |
| 2478 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
| 2479 | break; |
| 2480 | case DP_TRAINING_PATTERN_1: |
| 2481 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
| 2482 | break; |
| 2483 | case DP_TRAINING_PATTERN_2: |
| 2484 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2485 | break; |
| 2486 | case DP_TRAINING_PATTERN_3: |
| 2487 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2488 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2489 | break; |
| 2490 | } |
| 2491 | |
| 2492 | } else { |
| 2493 | if (IS_CHERRYVIEW(dev)) |
| 2494 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 2495 | else |
| 2496 | *DP &= ~DP_LINK_TRAIN_MASK; |
| 2497 | |
| 2498 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2499 | case DP_TRAINING_PATTERN_DISABLE: |
| 2500 | *DP |= DP_LINK_TRAIN_OFF; |
| 2501 | break; |
| 2502 | case DP_TRAINING_PATTERN_1: |
| 2503 | *DP |= DP_LINK_TRAIN_PAT_1; |
| 2504 | break; |
| 2505 | case DP_TRAINING_PATTERN_2: |
| 2506 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2507 | break; |
| 2508 | case DP_TRAINING_PATTERN_3: |
| 2509 | if (IS_CHERRYVIEW(dev)) { |
| 2510 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
| 2511 | } else { |
| 2512 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2513 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2514 | } |
| 2515 | break; |
| 2516 | } |
| 2517 | } |
| 2518 | } |
| 2519 | |
| 2520 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
| 2521 | { |
| 2522 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2523 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2524 | |
| 2525 | intel_dp->DP |= DP_PORT_EN; |
| 2526 | |
| 2527 | /* enable with pattern 1 (as per spec) */ |
| 2528 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
| 2529 | DP_TRAINING_PATTERN_1); |
| 2530 | |
| 2531 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2532 | POSTING_READ(intel_dp->output_reg); |
| 2533 | } |
| 2534 | |
| 2535 | static void intel_enable_dp(struct intel_encoder *encoder) |
| 2536 | { |
| 2537 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2538 | struct drm_device *dev = encoder->base.dev; |
| 2539 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2540 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
| 2541 | |
| 2542 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 2543 | return; |
| 2544 | |
| 2545 | intel_dp_enable_port(intel_dp); |
| 2546 | intel_edp_panel_vdd_on(intel_dp); |
| 2547 | intel_edp_panel_on(intel_dp); |
| 2548 | intel_edp_panel_vdd_off(intel_dp, true); |
| 2549 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2550 | intel_dp_start_link_train(intel_dp); |
| 2551 | intel_dp_complete_link_train(intel_dp); |
| 2552 | intel_dp_stop_link_train(intel_dp); |
| 2553 | } |
| 2554 | |
| 2555 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 2556 | { |
| 2557 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2558 | |
| 2559 | intel_enable_dp(encoder); |
| 2560 | intel_edp_backlight_on(intel_dp); |
| 2561 | } |
| 2562 | |
| 2563 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 2564 | { |
| 2565 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2566 | |
| 2567 | intel_edp_backlight_on(intel_dp); |
| 2568 | } |
| 2569 | |
| 2570 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
| 2571 | { |
| 2572 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2573 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2574 | |
| 2575 | intel_dp_prepare(encoder); |
| 2576 | |
| 2577 | /* Only ilk+ has port A */ |
| 2578 | if (dport->port == PORT_A) { |
| 2579 | ironlake_set_pll_cpu_edp(intel_dp); |
| 2580 | ironlake_edp_pll_on(intel_dp); |
| 2581 | } |
| 2582 | } |
| 2583 | |
| 2584 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 2585 | enum pipe pipe) |
| 2586 | { |
| 2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2588 | struct intel_encoder *encoder; |
| 2589 | |
| 2590 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2591 | |
| 2592 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 2593 | base.head) { |
| 2594 | struct intel_dp *intel_dp; |
| 2595 | enum port port; |
| 2596 | |
| 2597 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2598 | continue; |
| 2599 | |
| 2600 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 2601 | port = dp_to_dig_port(intel_dp)->port; |
| 2602 | |
| 2603 | if (intel_dp->pps_pipe != pipe) |
| 2604 | continue; |
| 2605 | |
| 2606 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
| 2607 | pipe_name(pipe), port_name(port)); |
| 2608 | |
| 2609 | /* make sure vdd is off before we steal it */ |
| 2610 | edp_panel_vdd_off_sync(intel_dp); |
| 2611 | |
| 2612 | intel_dp->pps_pipe = INVALID_PIPE; |
| 2613 | } |
| 2614 | } |
| 2615 | |
| 2616 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
| 2617 | { |
| 2618 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2619 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 2620 | struct drm_device *dev = encoder->base.dev; |
| 2621 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2622 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2623 | struct edp_power_seq power_seq; |
| 2624 | |
| 2625 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2626 | |
| 2627 | if (intel_dp->pps_pipe == crtc->pipe) |
| 2628 | return; |
| 2629 | |
| 2630 | /* |
| 2631 | * If another power sequencer was being used on this |
| 2632 | * port previously make sure to turn off vdd there while |
| 2633 | * we still have control of it. |
| 2634 | */ |
| 2635 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 2636 | edp_panel_vdd_off_sync(intel_dp); |
| 2637 | |
| 2638 | /* |
| 2639 | * We may be stealing the power |
| 2640 | * sequencer from another port. |
| 2641 | */ |
| 2642 | vlv_steal_power_sequencer(dev, crtc->pipe); |
| 2643 | |
| 2644 | /* now it's all ours */ |
| 2645 | intel_dp->pps_pipe = crtc->pipe; |
| 2646 | |
| 2647 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
| 2648 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
| 2649 | |
| 2650 | /* init power sequencer on this pipe and port */ |
| 2651 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
| 2652 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 2653 | &power_seq); |
| 2654 | } |
| 2655 | |
| 2656 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 2657 | { |
| 2658 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2659 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2660 | struct drm_device *dev = encoder->base.dev; |
| 2661 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2662 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 2663 | enum dpio_channel port = vlv_dport_to_channel(dport); |
| 2664 | int pipe = intel_crtc->pipe; |
| 2665 | u32 val; |
| 2666 | |
| 2667 | mutex_lock(&dev_priv->dpio_lock); |
| 2668 | |
| 2669 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
| 2670 | val = 0; |
| 2671 | if (pipe) |
| 2672 | val |= (1<<21); |
| 2673 | else |
| 2674 | val &= ~(1<<21); |
| 2675 | val |= 0x001000c4; |
| 2676 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
| 2677 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
| 2678 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
| 2679 | |
| 2680 | mutex_unlock(&dev_priv->dpio_lock); |
| 2681 | |
| 2682 | if (is_edp(intel_dp)) { |
| 2683 | pps_lock(intel_dp); |
| 2684 | vlv_init_panel_power_sequencer(intel_dp); |
| 2685 | pps_unlock(intel_dp); |
| 2686 | } |
| 2687 | |
| 2688 | intel_enable_dp(encoder); |
| 2689 | |
| 2690 | vlv_wait_port_ready(dev_priv, dport); |
| 2691 | } |
| 2692 | |
| 2693 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 2694 | { |
| 2695 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2696 | struct drm_device *dev = encoder->base.dev; |
| 2697 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2698 | struct intel_crtc *intel_crtc = |
| 2699 | to_intel_crtc(encoder->base.crtc); |
| 2700 | enum dpio_channel port = vlv_dport_to_channel(dport); |
| 2701 | int pipe = intel_crtc->pipe; |
| 2702 | |
| 2703 | intel_dp_prepare(encoder); |
| 2704 | |
| 2705 | /* Program Tx lane resets to default */ |
| 2706 | mutex_lock(&dev_priv->dpio_lock); |
| 2707 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
| 2708 | DPIO_PCS_TX_LANE2_RESET | |
| 2709 | DPIO_PCS_TX_LANE1_RESET); |
| 2710 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
| 2711 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 2712 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 2713 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 2714 | DPIO_PCS_CLK_SOFT_RESET); |
| 2715 | |
| 2716 | /* Fix up inter-pair skew failure */ |
| 2717 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
| 2718 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
| 2719 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
| 2720 | mutex_unlock(&dev_priv->dpio_lock); |
| 2721 | } |
| 2722 | |
| 2723 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
| 2724 | { |
| 2725 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2726 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2727 | struct drm_device *dev = encoder->base.dev; |
| 2728 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2729 | struct intel_crtc *intel_crtc = |
| 2730 | to_intel_crtc(encoder->base.crtc); |
| 2731 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2732 | int pipe = intel_crtc->pipe; |
| 2733 | int data, i; |
| 2734 | u32 val; |
| 2735 | |
| 2736 | mutex_lock(&dev_priv->dpio_lock); |
| 2737 | |
| 2738 | /* allow hardware to manage TX FIFO reset source */ |
| 2739 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); |
| 2740 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2741 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); |
| 2742 | |
| 2743 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
| 2744 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
| 2745 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); |
| 2746 | |
| 2747 | /* Deassert soft data lane reset*/ |
| 2748 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
| 2749 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2750 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
| 2751 | |
| 2752 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
| 2753 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
| 2754 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); |
| 2755 | |
| 2756 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); |
| 2757 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2758 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); |
| 2759 | |
| 2760 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
| 2761 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2762 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
| 2763 | |
| 2764 | /* Program Tx lane latency optimal setting*/ |
| 2765 | for (i = 0; i < 4; i++) { |
| 2766 | /* Set the latency optimal bit */ |
| 2767 | data = (i == 1) ? 0x0 : 0x6; |
| 2768 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), |
| 2769 | data << DPIO_FRC_LATENCY_SHFIT); |
| 2770 | |
| 2771 | /* Set the upar bit */ |
| 2772 | data = (i == 1) ? 0x0 : 0x1; |
| 2773 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
| 2774 | data << DPIO_UPAR_SHIFT); |
| 2775 | } |
| 2776 | |
| 2777 | /* Data lane stagger programming */ |
| 2778 | /* FIXME: Fix up value only after power analysis */ |
| 2779 | |
| 2780 | mutex_unlock(&dev_priv->dpio_lock); |
| 2781 | |
| 2782 | if (is_edp(intel_dp)) { |
| 2783 | pps_lock(intel_dp); |
| 2784 | vlv_init_panel_power_sequencer(intel_dp); |
| 2785 | pps_unlock(intel_dp); |
| 2786 | } |
| 2787 | |
| 2788 | intel_enable_dp(encoder); |
| 2789 | |
| 2790 | vlv_wait_port_ready(dev_priv, dport); |
| 2791 | } |
| 2792 | |
| 2793 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 2794 | { |
| 2795 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 2796 | struct drm_device *dev = encoder->base.dev; |
| 2797 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2798 | struct intel_crtc *intel_crtc = |
| 2799 | to_intel_crtc(encoder->base.crtc); |
| 2800 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2801 | enum pipe pipe = intel_crtc->pipe; |
| 2802 | u32 val; |
| 2803 | |
| 2804 | intel_dp_prepare(encoder); |
| 2805 | |
| 2806 | mutex_lock(&dev_priv->dpio_lock); |
| 2807 | |
| 2808 | /* program left/right clock distribution */ |
| 2809 | if (pipe != PIPE_B) { |
| 2810 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); |
| 2811 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
| 2812 | if (ch == DPIO_CH0) |
| 2813 | val |= CHV_BUFLEFTENA1_FORCE; |
| 2814 | if (ch == DPIO_CH1) |
| 2815 | val |= CHV_BUFRIGHTENA1_FORCE; |
| 2816 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); |
| 2817 | } else { |
| 2818 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); |
| 2819 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
| 2820 | if (ch == DPIO_CH0) |
| 2821 | val |= CHV_BUFLEFTENA2_FORCE; |
| 2822 | if (ch == DPIO_CH1) |
| 2823 | val |= CHV_BUFRIGHTENA2_FORCE; |
| 2824 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); |
| 2825 | } |
| 2826 | |
| 2827 | /* program clock channel usage */ |
| 2828 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); |
| 2829 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 2830 | if (pipe != PIPE_B) |
| 2831 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 2832 | else |
| 2833 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 2834 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); |
| 2835 | |
| 2836 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
| 2837 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; |
| 2838 | if (pipe != PIPE_B) |
| 2839 | val &= ~CHV_PCS_USEDCLKCHANNEL; |
| 2840 | else |
| 2841 | val |= CHV_PCS_USEDCLKCHANNEL; |
| 2842 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); |
| 2843 | |
| 2844 | /* |
| 2845 | * This a a bit weird since generally CL |
| 2846 | * matches the pipe, but here we need to |
| 2847 | * pick the CL based on the port. |
| 2848 | */ |
| 2849 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); |
| 2850 | if (pipe != PIPE_B) |
| 2851 | val &= ~CHV_CMN_USEDCLKCHANNEL; |
| 2852 | else |
| 2853 | val |= CHV_CMN_USEDCLKCHANNEL; |
| 2854 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); |
| 2855 | |
| 2856 | mutex_unlock(&dev_priv->dpio_lock); |
| 2857 | } |
| 2858 | |
| 2859 | /* |
| 2860 | * Native read with retry for link status and receiver capability reads for |
| 2861 | * cases where the sink may still be asleep. |
| 2862 | * |
| 2863 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
| 2864 | * supposed to retry 3 times per the spec. |
| 2865 | */ |
| 2866 | static ssize_t |
| 2867 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
| 2868 | void *buffer, size_t size) |
| 2869 | { |
| 2870 | ssize_t ret; |
| 2871 | int i; |
| 2872 | |
| 2873 | for (i = 0; i < 3; i++) { |
| 2874 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
| 2875 | if (ret == size) |
| 2876 | return ret; |
| 2877 | msleep(1); |
| 2878 | } |
| 2879 | |
| 2880 | return ret; |
| 2881 | } |
| 2882 | |
| 2883 | /* |
| 2884 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 2885 | * link status information |
| 2886 | */ |
| 2887 | static bool |
| 2888 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 2889 | { |
| 2890 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 2891 | DP_LANE0_1_STATUS, |
| 2892 | link_status, |
| 2893 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
| 2894 | } |
| 2895 | |
| 2896 | /* These are source-specific values. */ |
| 2897 | static uint8_t |
| 2898 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
| 2899 | { |
| 2900 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2901 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2902 | |
| 2903 | if (INTEL_INFO(dev)->gen >= 9) |
| 2904 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
| 2905 | else if (IS_VALLEYVIEW(dev)) |
| 2906 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 2907 | else if (IS_GEN7(dev) && port == PORT_A) |
| 2908 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
| 2909 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
| 2910 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 2911 | else |
| 2912 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
| 2913 | } |
| 2914 | |
| 2915 | static uint8_t |
| 2916 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 2917 | { |
| 2918 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2919 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2920 | |
| 2921 | if (INTEL_INFO(dev)->gen >= 9) { |
| 2922 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2923 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2924 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2925 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2926 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2927 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2928 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2929 | default: |
| 2930 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 2931 | } |
| 2932 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 2933 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2934 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2935 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2936 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2937 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2938 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2939 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2940 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 2941 | default: |
| 2942 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 2943 | } |
| 2944 | } else if (IS_VALLEYVIEW(dev)) { |
| 2945 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2946 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2947 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2948 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2949 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2950 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2951 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2952 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 2953 | default: |
| 2954 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 2955 | } |
| 2956 | } else if (IS_GEN7(dev) && port == PORT_A) { |
| 2957 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2958 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2959 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2960 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2961 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2962 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2963 | default: |
| 2964 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 2965 | } |
| 2966 | } else { |
| 2967 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2968 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2969 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2970 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2971 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2972 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2973 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2974 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 2975 | default: |
| 2976 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 2977 | } |
| 2978 | } |
| 2979 | } |
| 2980 | |
| 2981 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
| 2982 | { |
| 2983 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2984 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2985 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2986 | struct intel_crtc *intel_crtc = |
| 2987 | to_intel_crtc(dport->base.base.crtc); |
| 2988 | unsigned long demph_reg_value, preemph_reg_value, |
| 2989 | uniqtranscale_reg_value; |
| 2990 | uint8_t train_set = intel_dp->train_set[0]; |
| 2991 | enum dpio_channel port = vlv_dport_to_channel(dport); |
| 2992 | int pipe = intel_crtc->pipe; |
| 2993 | |
| 2994 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 2995 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 2996 | preemph_reg_value = 0x0004000; |
| 2997 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2998 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2999 | demph_reg_value = 0x2B405555; |
| 3000 | uniqtranscale_reg_value = 0x552AB83A; |
| 3001 | break; |
| 3002 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3003 | demph_reg_value = 0x2B404040; |
| 3004 | uniqtranscale_reg_value = 0x5548B83A; |
| 3005 | break; |
| 3006 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3007 | demph_reg_value = 0x2B245555; |
| 3008 | uniqtranscale_reg_value = 0x5560B83A; |
| 3009 | break; |
| 3010 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3011 | demph_reg_value = 0x2B405555; |
| 3012 | uniqtranscale_reg_value = 0x5598DA3A; |
| 3013 | break; |
| 3014 | default: |
| 3015 | return 0; |
| 3016 | } |
| 3017 | break; |
| 3018 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3019 | preemph_reg_value = 0x0002000; |
| 3020 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3021 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3022 | demph_reg_value = 0x2B404040; |
| 3023 | uniqtranscale_reg_value = 0x5552B83A; |
| 3024 | break; |
| 3025 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3026 | demph_reg_value = 0x2B404848; |
| 3027 | uniqtranscale_reg_value = 0x5580B83A; |
| 3028 | break; |
| 3029 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3030 | demph_reg_value = 0x2B404040; |
| 3031 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3032 | break; |
| 3033 | default: |
| 3034 | return 0; |
| 3035 | } |
| 3036 | break; |
| 3037 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3038 | preemph_reg_value = 0x0000000; |
| 3039 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3040 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3041 | demph_reg_value = 0x2B305555; |
| 3042 | uniqtranscale_reg_value = 0x5570B83A; |
| 3043 | break; |
| 3044 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3045 | demph_reg_value = 0x2B2B4040; |
| 3046 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3047 | break; |
| 3048 | default: |
| 3049 | return 0; |
| 3050 | } |
| 3051 | break; |
| 3052 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3053 | preemph_reg_value = 0x0006000; |
| 3054 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3055 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3056 | demph_reg_value = 0x1B405555; |
| 3057 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3058 | break; |
| 3059 | default: |
| 3060 | return 0; |
| 3061 | } |
| 3062 | break; |
| 3063 | default: |
| 3064 | return 0; |
| 3065 | } |
| 3066 | |
| 3067 | mutex_lock(&dev_priv->dpio_lock); |
| 3068 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
| 3069 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
| 3070 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
| 3071 | uniqtranscale_reg_value); |
| 3072 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
| 3073 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
| 3074 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
| 3075 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
| 3076 | mutex_unlock(&dev_priv->dpio_lock); |
| 3077 | |
| 3078 | return 0; |
| 3079 | } |
| 3080 | |
| 3081 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
| 3082 | { |
| 3083 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3084 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3085 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 3086 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
| 3087 | u32 deemph_reg_value, margin_reg_value, val; |
| 3088 | uint8_t train_set = intel_dp->train_set[0]; |
| 3089 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 3090 | enum pipe pipe = intel_crtc->pipe; |
| 3091 | int i; |
| 3092 | |
| 3093 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 3094 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3095 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3096 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3097 | deemph_reg_value = 128; |
| 3098 | margin_reg_value = 52; |
| 3099 | break; |
| 3100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3101 | deemph_reg_value = 128; |
| 3102 | margin_reg_value = 77; |
| 3103 | break; |
| 3104 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3105 | deemph_reg_value = 128; |
| 3106 | margin_reg_value = 102; |
| 3107 | break; |
| 3108 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3109 | deemph_reg_value = 128; |
| 3110 | margin_reg_value = 154; |
| 3111 | /* FIXME extra to set for 1200 */ |
| 3112 | break; |
| 3113 | default: |
| 3114 | return 0; |
| 3115 | } |
| 3116 | break; |
| 3117 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3118 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3119 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3120 | deemph_reg_value = 85; |
| 3121 | margin_reg_value = 78; |
| 3122 | break; |
| 3123 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3124 | deemph_reg_value = 85; |
| 3125 | margin_reg_value = 116; |
| 3126 | break; |
| 3127 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3128 | deemph_reg_value = 85; |
| 3129 | margin_reg_value = 154; |
| 3130 | break; |
| 3131 | default: |
| 3132 | return 0; |
| 3133 | } |
| 3134 | break; |
| 3135 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3136 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3138 | deemph_reg_value = 64; |
| 3139 | margin_reg_value = 104; |
| 3140 | break; |
| 3141 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3142 | deemph_reg_value = 64; |
| 3143 | margin_reg_value = 154; |
| 3144 | break; |
| 3145 | default: |
| 3146 | return 0; |
| 3147 | } |
| 3148 | break; |
| 3149 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3150 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3151 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3152 | deemph_reg_value = 43; |
| 3153 | margin_reg_value = 154; |
| 3154 | break; |
| 3155 | default: |
| 3156 | return 0; |
| 3157 | } |
| 3158 | break; |
| 3159 | default: |
| 3160 | return 0; |
| 3161 | } |
| 3162 | |
| 3163 | mutex_lock(&dev_priv->dpio_lock); |
| 3164 | |
| 3165 | /* Clear calc init */ |
| 3166 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 3167 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 3168 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 3169 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 3170 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 3171 | |
| 3172 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 3173 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
| 3174 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
| 3175 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; |
| 3176 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 3177 | |
| 3178 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
| 3179 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 3180 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 3181 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); |
| 3182 | |
| 3183 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); |
| 3184 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
| 3185 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; |
| 3186 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); |
| 3187 | |
| 3188 | /* Program swing deemph */ |
| 3189 | for (i = 0; i < 4; i++) { |
| 3190 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); |
| 3191 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
| 3192 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
| 3193 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); |
| 3194 | } |
| 3195 | |
| 3196 | /* Program swing margin */ |
| 3197 | for (i = 0; i < 4; i++) { |
| 3198 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
| 3199 | val &= ~DPIO_SWING_MARGIN000_MASK; |
| 3200 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; |
| 3201 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
| 3202 | } |
| 3203 | |
| 3204 | /* Disable unique transition scale */ |
| 3205 | for (i = 0; i < 4; i++) { |
| 3206 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
| 3207 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 3208 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
| 3209 | } |
| 3210 | |
| 3211 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 3212 | == DP_TRAIN_PRE_EMPH_LEVEL_0) && |
| 3213 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
| 3214 | == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) { |
| 3215 | |
| 3216 | /* |
| 3217 | * The document said it needs to set bit 27 for ch0 and bit 26 |
| 3218 | * for ch1. Might be a typo in the doc. |
| 3219 | * For now, for this unique transition scale selection, set bit |
| 3220 | * 27 for ch0 and ch1. |
| 3221 | */ |
| 3222 | for (i = 0; i < 4; i++) { |
| 3223 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); |
| 3224 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 3225 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); |
| 3226 | } |
| 3227 | |
| 3228 | for (i = 0; i < 4; i++) { |
| 3229 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); |
| 3230 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
| 3231 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
| 3232 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
| 3233 | } |
| 3234 | } |
| 3235 | |
| 3236 | /* Start swing calculation */ |
| 3237 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
| 3238 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 3239 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
| 3240 | |
| 3241 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); |
| 3242 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
| 3243 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
| 3244 | |
| 3245 | /* LRC Bypass */ |
| 3246 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
| 3247 | val |= DPIO_LRC_BYPASS; |
| 3248 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
| 3249 | |
| 3250 | mutex_unlock(&dev_priv->dpio_lock); |
| 3251 | |
| 3252 | return 0; |
| 3253 | } |
| 3254 | |
| 3255 | static void |
| 3256 | intel_get_adjust_train(struct intel_dp *intel_dp, |
| 3257 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 3258 | { |
| 3259 | uint8_t v = 0; |
| 3260 | uint8_t p = 0; |
| 3261 | int lane; |
| 3262 | uint8_t voltage_max; |
| 3263 | uint8_t preemph_max; |
| 3264 | |
| 3265 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
| 3266 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 3267 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
| 3268 | |
| 3269 | if (this_v > v) |
| 3270 | v = this_v; |
| 3271 | if (this_p > p) |
| 3272 | p = this_p; |
| 3273 | } |
| 3274 | |
| 3275 | voltage_max = intel_dp_voltage_max(intel_dp); |
| 3276 | if (v >= voltage_max) |
| 3277 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
| 3278 | |
| 3279 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
| 3280 | if (p >= preemph_max) |
| 3281 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 3282 | |
| 3283 | for (lane = 0; lane < 4; lane++) |
| 3284 | intel_dp->train_set[lane] = v | p; |
| 3285 | } |
| 3286 | |
| 3287 | static uint32_t |
| 3288 | intel_gen4_signal_levels(uint8_t train_set) |
| 3289 | { |
| 3290 | uint32_t signal_levels = 0; |
| 3291 | |
| 3292 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 3293 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 3294 | default: |
| 3295 | signal_levels |= DP_VOLTAGE_0_4; |
| 3296 | break; |
| 3297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 3298 | signal_levels |= DP_VOLTAGE_0_6; |
| 3299 | break; |
| 3300 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 3301 | signal_levels |= DP_VOLTAGE_0_8; |
| 3302 | break; |
| 3303 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 3304 | signal_levels |= DP_VOLTAGE_1_2; |
| 3305 | break; |
| 3306 | } |
| 3307 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 3308 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3309 | default: |
| 3310 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 3311 | break; |
| 3312 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3313 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 3314 | break; |
| 3315 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3316 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 3317 | break; |
| 3318 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3319 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 3320 | break; |
| 3321 | } |
| 3322 | return signal_levels; |
| 3323 | } |
| 3324 | |
| 3325 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 3326 | static uint32_t |
| 3327 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 3328 | { |
| 3329 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3330 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3331 | switch (signal_levels) { |
| 3332 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3333 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3334 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 3335 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3336 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
| 3337 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3338 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3339 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
| 3340 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3341 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3342 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
| 3343 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3344 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3345 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
| 3346 | default: |
| 3347 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3348 | "0x%x\n", signal_levels); |
| 3349 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 3350 | } |
| 3351 | } |
| 3352 | |
| 3353 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 3354 | static uint32_t |
| 3355 | intel_gen7_edp_signal_levels(uint8_t train_set) |
| 3356 | { |
| 3357 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3358 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3359 | switch (signal_levels) { |
| 3360 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3361 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
| 3362 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3363 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
| 3364 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3365 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 3366 | |
| 3367 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3368 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
| 3369 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3370 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 3371 | |
| 3372 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3373 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
| 3374 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3375 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 3376 | |
| 3377 | default: |
| 3378 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3379 | "0x%x\n", signal_levels); |
| 3380 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 3381 | } |
| 3382 | } |
| 3383 | |
| 3384 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
| 3385 | static uint32_t |
| 3386 | intel_hsw_signal_levels(uint8_t train_set) |
| 3387 | { |
| 3388 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3389 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3390 | switch (signal_levels) { |
| 3391 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3392 | return DDI_BUF_TRANS_SELECT(0); |
| 3393 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3394 | return DDI_BUF_TRANS_SELECT(1); |
| 3395 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3396 | return DDI_BUF_TRANS_SELECT(2); |
| 3397 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: |
| 3398 | return DDI_BUF_TRANS_SELECT(3); |
| 3399 | |
| 3400 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3401 | return DDI_BUF_TRANS_SELECT(4); |
| 3402 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3403 | return DDI_BUF_TRANS_SELECT(5); |
| 3404 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3405 | return DDI_BUF_TRANS_SELECT(6); |
| 3406 | |
| 3407 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3408 | return DDI_BUF_TRANS_SELECT(7); |
| 3409 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3410 | return DDI_BUF_TRANS_SELECT(8); |
| 3411 | default: |
| 3412 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3413 | "0x%x\n", signal_levels); |
| 3414 | return DDI_BUF_TRANS_SELECT(0); |
| 3415 | } |
| 3416 | } |
| 3417 | |
| 3418 | /* Properly updates "DP" with the correct signal levels. */ |
| 3419 | static void |
| 3420 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
| 3421 | { |
| 3422 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3423 | enum port port = intel_dig_port->port; |
| 3424 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3425 | uint32_t signal_levels, mask; |
| 3426 | uint8_t train_set = intel_dp->train_set[0]; |
| 3427 | |
| 3428 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
| 3429 | signal_levels = intel_hsw_signal_levels(train_set); |
| 3430 | mask = DDI_BUF_EMP_MASK; |
| 3431 | } else if (IS_CHERRYVIEW(dev)) { |
| 3432 | signal_levels = intel_chv_signal_levels(intel_dp); |
| 3433 | mask = 0; |
| 3434 | } else if (IS_VALLEYVIEW(dev)) { |
| 3435 | signal_levels = intel_vlv_signal_levels(intel_dp); |
| 3436 | mask = 0; |
| 3437 | } else if (IS_GEN7(dev) && port == PORT_A) { |
| 3438 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
| 3439 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
| 3440 | } else if (IS_GEN6(dev) && port == PORT_A) { |
| 3441 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
| 3442 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 3443 | } else { |
| 3444 | signal_levels = intel_gen4_signal_levels(train_set); |
| 3445 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 3446 | } |
| 3447 | |
| 3448 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 3449 | |
| 3450 | *DP = (*DP & ~mask) | signal_levels; |
| 3451 | } |
| 3452 | |
| 3453 | static bool |
| 3454 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 3455 | uint32_t *DP, |
| 3456 | uint8_t dp_train_pat) |
| 3457 | { |
| 3458 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3459 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3460 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3461 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
| 3462 | int ret, len; |
| 3463 | |
| 3464 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
| 3465 | |
| 3466 | I915_WRITE(intel_dp->output_reg, *DP); |
| 3467 | POSTING_READ(intel_dp->output_reg); |
| 3468 | |
| 3469 | buf[0] = dp_train_pat; |
| 3470 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
| 3471 | DP_TRAINING_PATTERN_DISABLE) { |
| 3472 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
| 3473 | len = 1; |
| 3474 | } else { |
| 3475 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
| 3476 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
| 3477 | len = intel_dp->lane_count + 1; |
| 3478 | } |
| 3479 | |
| 3480 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
| 3481 | buf, len); |
| 3482 | |
| 3483 | return ret == len; |
| 3484 | } |
| 3485 | |
| 3486 | static bool |
| 3487 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
| 3488 | uint8_t dp_train_pat) |
| 3489 | { |
| 3490 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
| 3491 | intel_dp_set_signal_levels(intel_dp, DP); |
| 3492 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
| 3493 | } |
| 3494 | |
| 3495 | static bool |
| 3496 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
| 3497 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
| 3498 | { |
| 3499 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3500 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3501 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3502 | int ret; |
| 3503 | |
| 3504 | intel_get_adjust_train(intel_dp, link_status); |
| 3505 | intel_dp_set_signal_levels(intel_dp, DP); |
| 3506 | |
| 3507 | I915_WRITE(intel_dp->output_reg, *DP); |
| 3508 | POSTING_READ(intel_dp->output_reg); |
| 3509 | |
| 3510 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
| 3511 | intel_dp->train_set, intel_dp->lane_count); |
| 3512 | |
| 3513 | return ret == intel_dp->lane_count; |
| 3514 | } |
| 3515 | |
| 3516 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
| 3517 | { |
| 3518 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3519 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3520 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3521 | enum port port = intel_dig_port->port; |
| 3522 | uint32_t val; |
| 3523 | |
| 3524 | if (!HAS_DDI(dev)) |
| 3525 | return; |
| 3526 | |
| 3527 | val = I915_READ(DP_TP_CTL(port)); |
| 3528 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 3529 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 3530 | I915_WRITE(DP_TP_CTL(port), val); |
| 3531 | |
| 3532 | /* |
| 3533 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 3534 | * we need to set idle transmission mode is to work around a HW issue |
| 3535 | * where we enable the pipe while not in idle link-training mode. |
| 3536 | * In this case there is requirement to wait for a minimum number of |
| 3537 | * idle patterns to be sent. |
| 3538 | */ |
| 3539 | if (port == PORT_A) |
| 3540 | return; |
| 3541 | |
| 3542 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 3543 | 1)) |
| 3544 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 3545 | } |
| 3546 | |
| 3547 | /* Enable corresponding port and start training pattern 1 */ |
| 3548 | void |
| 3549 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
| 3550 | { |
| 3551 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
| 3552 | struct drm_device *dev = encoder->dev; |
| 3553 | int i; |
| 3554 | uint8_t voltage; |
| 3555 | int voltage_tries, loop_tries; |
| 3556 | uint32_t DP = intel_dp->DP; |
| 3557 | uint8_t link_config[2]; |
| 3558 | |
| 3559 | if (HAS_DDI(dev)) |
| 3560 | intel_ddi_prepare_link_retrain(encoder); |
| 3561 | |
| 3562 | /* Write the link configuration data */ |
| 3563 | link_config[0] = intel_dp->link_bw; |
| 3564 | link_config[1] = intel_dp->lane_count; |
| 3565 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 3566 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 3567 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
| 3568 | |
| 3569 | link_config[0] = 0; |
| 3570 | link_config[1] = DP_SET_ANSI_8B10B; |
| 3571 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
| 3572 | |
| 3573 | DP |= DP_PORT_EN; |
| 3574 | |
| 3575 | /* clock recovery */ |
| 3576 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
| 3577 | DP_TRAINING_PATTERN_1 | |
| 3578 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 3579 | DRM_ERROR("failed to enable link training\n"); |
| 3580 | return; |
| 3581 | } |
| 3582 | |
| 3583 | voltage = 0xff; |
| 3584 | voltage_tries = 0; |
| 3585 | loop_tries = 0; |
| 3586 | for (;;) { |
| 3587 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
| 3588 | |
| 3589 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
| 3590 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 3591 | DRM_ERROR("failed to get link status\n"); |
| 3592 | break; |
| 3593 | } |
| 3594 | |
| 3595 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
| 3596 | DRM_DEBUG_KMS("clock recovery OK\n"); |
| 3597 | break; |
| 3598 | } |
| 3599 | |
| 3600 | /* Check to see if we've tried the max voltage */ |
| 3601 | for (i = 0; i < intel_dp->lane_count; i++) |
| 3602 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 3603 | break; |
| 3604 | if (i == intel_dp->lane_count) { |
| 3605 | ++loop_tries; |
| 3606 | if (loop_tries == 5) { |
| 3607 | DRM_ERROR("too many full retries, give up\n"); |
| 3608 | break; |
| 3609 | } |
| 3610 | intel_dp_reset_link_train(intel_dp, &DP, |
| 3611 | DP_TRAINING_PATTERN_1 | |
| 3612 | DP_LINK_SCRAMBLING_DISABLE); |
| 3613 | voltage_tries = 0; |
| 3614 | continue; |
| 3615 | } |
| 3616 | |
| 3617 | /* Check to see if we've tried the same voltage 5 times */ |
| 3618 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 3619 | ++voltage_tries; |
| 3620 | if (voltage_tries == 5) { |
| 3621 | DRM_ERROR("too many voltage retries, give up\n"); |
| 3622 | break; |
| 3623 | } |
| 3624 | } else |
| 3625 | voltage_tries = 0; |
| 3626 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 3627 | |
| 3628 | /* Update training set as requested by target */ |
| 3629 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
| 3630 | DRM_ERROR("failed to update link training\n"); |
| 3631 | break; |
| 3632 | } |
| 3633 | } |
| 3634 | |
| 3635 | intel_dp->DP = DP; |
| 3636 | } |
| 3637 | |
| 3638 | void |
| 3639 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 3640 | { |
| 3641 | bool channel_eq = false; |
| 3642 | int tries, cr_tries; |
| 3643 | uint32_t DP = intel_dp->DP; |
| 3644 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
| 3645 | |
| 3646 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ |
| 3647 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) |
| 3648 | training_pattern = DP_TRAINING_PATTERN_3; |
| 3649 | |
| 3650 | /* channel equalization */ |
| 3651 | if (!intel_dp_set_link_train(intel_dp, &DP, |
| 3652 | training_pattern | |
| 3653 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 3654 | DRM_ERROR("failed to start channel equalization\n"); |
| 3655 | return; |
| 3656 | } |
| 3657 | |
| 3658 | tries = 0; |
| 3659 | cr_tries = 0; |
| 3660 | channel_eq = false; |
| 3661 | for (;;) { |
| 3662 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
| 3663 | |
| 3664 | if (cr_tries > 5) { |
| 3665 | DRM_ERROR("failed to train DP, aborting\n"); |
| 3666 | break; |
| 3667 | } |
| 3668 | |
| 3669 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
| 3670 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 3671 | DRM_ERROR("failed to get link status\n"); |
| 3672 | break; |
| 3673 | } |
| 3674 | |
| 3675 | /* Make sure clock is still ok */ |
| 3676 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
| 3677 | intel_dp_start_link_train(intel_dp); |
| 3678 | intel_dp_set_link_train(intel_dp, &DP, |
| 3679 | training_pattern | |
| 3680 | DP_LINK_SCRAMBLING_DISABLE); |
| 3681 | cr_tries++; |
| 3682 | continue; |
| 3683 | } |
| 3684 | |
| 3685 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
| 3686 | channel_eq = true; |
| 3687 | break; |
| 3688 | } |
| 3689 | |
| 3690 | /* Try 5 times, then try clock recovery if that fails */ |
| 3691 | if (tries > 5) { |
| 3692 | intel_dp_link_down(intel_dp); |
| 3693 | intel_dp_start_link_train(intel_dp); |
| 3694 | intel_dp_set_link_train(intel_dp, &DP, |
| 3695 | training_pattern | |
| 3696 | DP_LINK_SCRAMBLING_DISABLE); |
| 3697 | tries = 0; |
| 3698 | cr_tries++; |
| 3699 | continue; |
| 3700 | } |
| 3701 | |
| 3702 | /* Update training set as requested by target */ |
| 3703 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
| 3704 | DRM_ERROR("failed to update link training\n"); |
| 3705 | break; |
| 3706 | } |
| 3707 | ++tries; |
| 3708 | } |
| 3709 | |
| 3710 | intel_dp_set_idle_link_train(intel_dp); |
| 3711 | |
| 3712 | intel_dp->DP = DP; |
| 3713 | |
| 3714 | if (channel_eq) |
| 3715 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
| 3716 | |
| 3717 | } |
| 3718 | |
| 3719 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
| 3720 | { |
| 3721 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
| 3722 | DP_TRAINING_PATTERN_DISABLE); |
| 3723 | } |
| 3724 | |
| 3725 | static void |
| 3726 | intel_dp_link_down(struct intel_dp *intel_dp) |
| 3727 | { |
| 3728 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3729 | enum port port = intel_dig_port->port; |
| 3730 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3731 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3732 | struct intel_crtc *intel_crtc = |
| 3733 | to_intel_crtc(intel_dig_port->base.base.crtc); |
| 3734 | uint32_t DP = intel_dp->DP; |
| 3735 | |
| 3736 | if (WARN_ON(HAS_DDI(dev))) |
| 3737 | return; |
| 3738 | |
| 3739 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
| 3740 | return; |
| 3741 | |
| 3742 | DRM_DEBUG_KMS("\n"); |
| 3743 | |
| 3744 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
| 3745 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 3746 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
| 3747 | } else { |
| 3748 | if (IS_CHERRYVIEW(dev)) |
| 3749 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 3750 | else |
| 3751 | DP &= ~DP_LINK_TRAIN_MASK; |
| 3752 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
| 3753 | } |
| 3754 | POSTING_READ(intel_dp->output_reg); |
| 3755 | |
| 3756 | if (HAS_PCH_IBX(dev) && |
| 3757 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
| 3758 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 3759 | |
| 3760 | /* Hardware workaround: leaving our transcoder select |
| 3761 | * set to transcoder B while it's off will prevent the |
| 3762 | * corresponding HDMI output on transcoder A. |
| 3763 | * |
| 3764 | * Combine this with another hardware workaround: |
| 3765 | * transcoder select bit can only be cleared while the |
| 3766 | * port is enabled. |
| 3767 | */ |
| 3768 | DP &= ~DP_PIPEB_SELECT; |
| 3769 | I915_WRITE(intel_dp->output_reg, DP); |
| 3770 | |
| 3771 | /* Changes to enable or select take place the vblank |
| 3772 | * after being written. |
| 3773 | */ |
| 3774 | if (WARN_ON(crtc == NULL)) { |
| 3775 | /* We should never try to disable a port without a crtc |
| 3776 | * attached. For paranoia keep the code around for a |
| 3777 | * bit. */ |
| 3778 | POSTING_READ(intel_dp->output_reg); |
| 3779 | msleep(50); |
| 3780 | } else |
| 3781 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3782 | } |
| 3783 | |
| 3784 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
| 3785 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 3786 | POSTING_READ(intel_dp->output_reg); |
| 3787 | msleep(intel_dp->panel_power_down_delay); |
| 3788 | } |
| 3789 | |
| 3790 | static bool |
| 3791 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
| 3792 | { |
| 3793 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3794 | struct drm_device *dev = dig_port->base.base.dev; |
| 3795 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3796 | |
| 3797 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3798 | sizeof(intel_dp->dpcd)) < 0) |
| 3799 | return false; /* aux transfer failed */ |
| 3800 | |
| 3801 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
| 3802 | |
| 3803 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 3804 | return false; /* DPCD not present */ |
| 3805 | |
| 3806 | /* Check if the panel supports PSR */ |
| 3807 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
| 3808 | if (is_edp(intel_dp)) { |
| 3809 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3810 | intel_dp->psr_dpcd, |
| 3811 | sizeof(intel_dp->psr_dpcd)); |
| 3812 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3813 | dev_priv->psr.sink_support = true; |
| 3814 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
| 3815 | } |
| 3816 | } |
| 3817 | |
| 3818 | /* Training Pattern 3 support */ |
| 3819 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
| 3820 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
| 3821 | intel_dp->use_tps3 = true; |
| 3822 | DRM_DEBUG_KMS("Displayport TPS3 supported\n"); |
| 3823 | } else |
| 3824 | intel_dp->use_tps3 = false; |
| 3825 | |
| 3826 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3827 | DP_DWN_STRM_PORT_PRESENT)) |
| 3828 | return true; /* native DP sink */ |
| 3829 | |
| 3830 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3831 | return true; /* no per-port downstream info */ |
| 3832 | |
| 3833 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3834 | intel_dp->downstream_ports, |
| 3835 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
| 3836 | return false; /* downstream port status fetch failed */ |
| 3837 | |
| 3838 | return true; |
| 3839 | } |
| 3840 | |
| 3841 | static void |
| 3842 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3843 | { |
| 3844 | u8 buf[3]; |
| 3845 | |
| 3846 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3847 | return; |
| 3848 | |
| 3849 | intel_edp_panel_vdd_on(intel_dp); |
| 3850 | |
| 3851 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
| 3852 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3853 | buf[0], buf[1], buf[2]); |
| 3854 | |
| 3855 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
| 3856 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3857 | buf[0], buf[1], buf[2]); |
| 3858 | |
| 3859 | intel_edp_panel_vdd_off(intel_dp, false); |
| 3860 | } |
| 3861 | |
| 3862 | static bool |
| 3863 | intel_dp_probe_mst(struct intel_dp *intel_dp) |
| 3864 | { |
| 3865 | u8 buf[1]; |
| 3866 | |
| 3867 | if (!intel_dp->can_mst) |
| 3868 | return false; |
| 3869 | |
| 3870 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
| 3871 | return false; |
| 3872 | |
| 3873 | intel_edp_panel_vdd_on(intel_dp); |
| 3874 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
| 3875 | if (buf[0] & DP_MST_CAP) { |
| 3876 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
| 3877 | intel_dp->is_mst = true; |
| 3878 | } else { |
| 3879 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
| 3880 | intel_dp->is_mst = false; |
| 3881 | } |
| 3882 | } |
| 3883 | intel_edp_panel_vdd_off(intel_dp, false); |
| 3884 | |
| 3885 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 3886 | return intel_dp->is_mst; |
| 3887 | } |
| 3888 | |
| 3889 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 3890 | { |
| 3891 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3892 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3893 | struct intel_crtc *intel_crtc = |
| 3894 | to_intel_crtc(intel_dig_port->base.base.crtc); |
| 3895 | u8 buf; |
| 3896 | int test_crc_count; |
| 3897 | int attempts = 6; |
| 3898 | |
| 3899 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 3900 | return -EIO; |
| 3901 | |
| 3902 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
| 3903 | return -ENOTTY; |
| 3904 | |
| 3905 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 3906 | return -EIO; |
| 3907 | |
| 3908 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3909 | buf | DP_TEST_SINK_START) < 0) |
| 3910 | return -EIO; |
| 3911 | |
| 3912 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 3913 | return -EIO; |
| 3914 | test_crc_count = buf & DP_TEST_COUNT_MASK; |
| 3915 | |
| 3916 | do { |
| 3917 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 3918 | DP_TEST_SINK_MISC, &buf) < 0) |
| 3919 | return -EIO; |
| 3920 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3921 | } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count); |
| 3922 | |
| 3923 | if (attempts == 0) { |
| 3924 | DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n"); |
| 3925 | return -EIO; |
| 3926 | } |
| 3927 | |
| 3928 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
| 3929 | return -EIO; |
| 3930 | |
| 3931 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 3932 | return -EIO; |
| 3933 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3934 | buf & ~DP_TEST_SINK_START) < 0) |
| 3935 | return -EIO; |
| 3936 | |
| 3937 | return 0; |
| 3938 | } |
| 3939 | |
| 3940 | static bool |
| 3941 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3942 | { |
| 3943 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3944 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3945 | sink_irq_vector, 1) == 1; |
| 3946 | } |
| 3947 | |
| 3948 | static bool |
| 3949 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3950 | { |
| 3951 | int ret; |
| 3952 | |
| 3953 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3954 | DP_SINK_COUNT_ESI, |
| 3955 | sink_irq_vector, 14); |
| 3956 | if (ret != 14) |
| 3957 | return false; |
| 3958 | |
| 3959 | return true; |
| 3960 | } |
| 3961 | |
| 3962 | static void |
| 3963 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 3964 | { |
| 3965 | /* NAK by default */ |
| 3966 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
| 3967 | } |
| 3968 | |
| 3969 | static int |
| 3970 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
| 3971 | { |
| 3972 | bool bret; |
| 3973 | |
| 3974 | if (intel_dp->is_mst) { |
| 3975 | u8 esi[16] = { 0 }; |
| 3976 | int ret = 0; |
| 3977 | int retry; |
| 3978 | bool handled; |
| 3979 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 3980 | go_again: |
| 3981 | if (bret == true) { |
| 3982 | |
| 3983 | /* check link status - esi[10] = 0x200c */ |
| 3984 | if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
| 3985 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
| 3986 | intel_dp_start_link_train(intel_dp); |
| 3987 | intel_dp_complete_link_train(intel_dp); |
| 3988 | intel_dp_stop_link_train(intel_dp); |
| 3989 | } |
| 3990 | |
| 3991 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
| 3992 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
| 3993 | |
| 3994 | if (handled) { |
| 3995 | for (retry = 0; retry < 3; retry++) { |
| 3996 | int wret; |
| 3997 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
| 3998 | DP_SINK_COUNT_ESI+1, |
| 3999 | &esi[1], 3); |
| 4000 | if (wret == 3) { |
| 4001 | break; |
| 4002 | } |
| 4003 | } |
| 4004 | |
| 4005 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 4006 | if (bret == true) { |
| 4007 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
| 4008 | goto go_again; |
| 4009 | } |
| 4010 | } else |
| 4011 | ret = 0; |
| 4012 | |
| 4013 | return ret; |
| 4014 | } else { |
| 4015 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4016 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
| 4017 | intel_dp->is_mst = false; |
| 4018 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4019 | /* send a hotplug event */ |
| 4020 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
| 4021 | } |
| 4022 | } |
| 4023 | return -EINVAL; |
| 4024 | } |
| 4025 | |
| 4026 | /* |
| 4027 | * According to DP spec |
| 4028 | * 5.1.2: |
| 4029 | * 1. Read DPCD |
| 4030 | * 2. Configure link according to Receiver Capabilities |
| 4031 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 4032 | * 4. Check link status on receipt of hot-plug interrupt |
| 4033 | */ |
| 4034 | void |
| 4035 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
| 4036 | { |
| 4037 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4038 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 4039 | u8 sink_irq_vector; |
| 4040 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 4041 | |
| 4042 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 4043 | |
| 4044 | if (!intel_encoder->connectors_active) |
| 4045 | return; |
| 4046 | |
| 4047 | if (WARN_ON(!intel_encoder->base.crtc)) |
| 4048 | return; |
| 4049 | |
| 4050 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
| 4051 | return; |
| 4052 | |
| 4053 | /* Try to read receiver status if the link appears to be up */ |
| 4054 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 4055 | return; |
| 4056 | } |
| 4057 | |
| 4058 | /* Now read the DPCD to see if it's actually running */ |
| 4059 | if (!intel_dp_get_dpcd(intel_dp)) { |
| 4060 | return; |
| 4061 | } |
| 4062 | |
| 4063 | /* Try to read the source of the interrupt */ |
| 4064 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4065 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 4066 | /* Clear interrupt source */ |
| 4067 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4068 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4069 | sink_irq_vector); |
| 4070 | |
| 4071 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4072 | intel_dp_handle_test_request(intel_dp); |
| 4073 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4074 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4075 | } |
| 4076 | |
| 4077 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
| 4078 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 4079 | intel_encoder->base.name); |
| 4080 | intel_dp_start_link_train(intel_dp); |
| 4081 | intel_dp_complete_link_train(intel_dp); |
| 4082 | intel_dp_stop_link_train(intel_dp); |
| 4083 | } |
| 4084 | } |
| 4085 | |
| 4086 | /* XXX this is probably wrong for multiple downstream ports */ |
| 4087 | static enum drm_connector_status |
| 4088 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
| 4089 | { |
| 4090 | uint8_t *dpcd = intel_dp->dpcd; |
| 4091 | uint8_t type; |
| 4092 | |
| 4093 | if (!intel_dp_get_dpcd(intel_dp)) |
| 4094 | return connector_status_disconnected; |
| 4095 | |
| 4096 | /* if there's no downstream port, we're done */ |
| 4097 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
| 4098 | return connector_status_connected; |
| 4099 | |
| 4100 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
| 4101 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 4102 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
| 4103 | uint8_t reg; |
| 4104 | |
| 4105 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
| 4106 | ®, 1) < 0) |
| 4107 | return connector_status_unknown; |
| 4108 | |
| 4109 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 4110 | : connector_status_disconnected; |
| 4111 | } |
| 4112 | |
| 4113 | /* If no HPD, poke DDC gently */ |
| 4114 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
| 4115 | return connector_status_connected; |
| 4116 | |
| 4117 | /* Well we tried, say unknown for unreliable port types */ |
| 4118 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 4119 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 4120 | if (type == DP_DS_PORT_TYPE_VGA || |
| 4121 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 4122 | return connector_status_unknown; |
| 4123 | } else { |
| 4124 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 4125 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 4126 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 4127 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 4128 | return connector_status_unknown; |
| 4129 | } |
| 4130 | |
| 4131 | /* Anything else is out of spec, warn and ignore */ |
| 4132 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
| 4133 | return connector_status_disconnected; |
| 4134 | } |
| 4135 | |
| 4136 | static enum drm_connector_status |
| 4137 | edp_detect(struct intel_dp *intel_dp) |
| 4138 | { |
| 4139 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4140 | enum drm_connector_status status; |
| 4141 | |
| 4142 | status = intel_panel_detect(dev); |
| 4143 | if (status == connector_status_unknown) |
| 4144 | status = connector_status_connected; |
| 4145 | |
| 4146 | return status; |
| 4147 | } |
| 4148 | |
| 4149 | static enum drm_connector_status |
| 4150 | ironlake_dp_detect(struct intel_dp *intel_dp) |
| 4151 | { |
| 4152 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4153 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4154 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4155 | |
| 4156 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
| 4157 | return connector_status_disconnected; |
| 4158 | |
| 4159 | return intel_dp_detect_dpcd(intel_dp); |
| 4160 | } |
| 4161 | |
| 4162 | static int g4x_digital_port_connected(struct drm_device *dev, |
| 4163 | struct intel_digital_port *intel_dig_port) |
| 4164 | { |
| 4165 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4166 | uint32_t bit; |
| 4167 | |
| 4168 | if (IS_VALLEYVIEW(dev)) { |
| 4169 | switch (intel_dig_port->port) { |
| 4170 | case PORT_B: |
| 4171 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
| 4172 | break; |
| 4173 | case PORT_C: |
| 4174 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
| 4175 | break; |
| 4176 | case PORT_D: |
| 4177 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
| 4178 | break; |
| 4179 | default: |
| 4180 | return -EINVAL; |
| 4181 | } |
| 4182 | } else { |
| 4183 | switch (intel_dig_port->port) { |
| 4184 | case PORT_B: |
| 4185 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 4186 | break; |
| 4187 | case PORT_C: |
| 4188 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 4189 | break; |
| 4190 | case PORT_D: |
| 4191 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 4192 | break; |
| 4193 | default: |
| 4194 | return -EINVAL; |
| 4195 | } |
| 4196 | } |
| 4197 | |
| 4198 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
| 4199 | return 0; |
| 4200 | return 1; |
| 4201 | } |
| 4202 | |
| 4203 | static enum drm_connector_status |
| 4204 | g4x_dp_detect(struct intel_dp *intel_dp) |
| 4205 | { |
| 4206 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4207 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4208 | int ret; |
| 4209 | |
| 4210 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4211 | if (is_edp(intel_dp)) { |
| 4212 | enum drm_connector_status status; |
| 4213 | |
| 4214 | status = intel_panel_detect(dev); |
| 4215 | if (status == connector_status_unknown) |
| 4216 | status = connector_status_connected; |
| 4217 | return status; |
| 4218 | } |
| 4219 | |
| 4220 | ret = g4x_digital_port_connected(dev, intel_dig_port); |
| 4221 | if (ret == -EINVAL) |
| 4222 | return connector_status_unknown; |
| 4223 | else if (ret == 0) |
| 4224 | return connector_status_disconnected; |
| 4225 | |
| 4226 | return intel_dp_detect_dpcd(intel_dp); |
| 4227 | } |
| 4228 | |
| 4229 | static struct edid * |
| 4230 | intel_dp_get_edid(struct intel_dp *intel_dp) |
| 4231 | { |
| 4232 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4233 | |
| 4234 | /* use cached edid if we have one */ |
| 4235 | if (intel_connector->edid) { |
| 4236 | /* invalid edid */ |
| 4237 | if (IS_ERR(intel_connector->edid)) |
| 4238 | return NULL; |
| 4239 | |
| 4240 | return drm_edid_duplicate(intel_connector->edid); |
| 4241 | } else |
| 4242 | return drm_get_edid(&intel_connector->base, |
| 4243 | &intel_dp->aux.ddc); |
| 4244 | } |
| 4245 | |
| 4246 | static void |
| 4247 | intel_dp_set_edid(struct intel_dp *intel_dp) |
| 4248 | { |
| 4249 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4250 | struct edid *edid; |
| 4251 | |
| 4252 | edid = intel_dp_get_edid(intel_dp); |
| 4253 | intel_connector->detect_edid = edid; |
| 4254 | |
| 4255 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
| 4256 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
| 4257 | else |
| 4258 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 4259 | } |
| 4260 | |
| 4261 | static void |
| 4262 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
| 4263 | { |
| 4264 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4265 | |
| 4266 | kfree(intel_connector->detect_edid); |
| 4267 | intel_connector->detect_edid = NULL; |
| 4268 | |
| 4269 | intel_dp->has_audio = false; |
| 4270 | } |
| 4271 | |
| 4272 | static enum intel_display_power_domain |
| 4273 | intel_dp_power_get(struct intel_dp *dp) |
| 4274 | { |
| 4275 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; |
| 4276 | enum intel_display_power_domain power_domain; |
| 4277 | |
| 4278 | power_domain = intel_display_port_power_domain(encoder); |
| 4279 | intel_display_power_get(to_i915(encoder->base.dev), power_domain); |
| 4280 | |
| 4281 | return power_domain; |
| 4282 | } |
| 4283 | |
| 4284 | static void |
| 4285 | intel_dp_power_put(struct intel_dp *dp, |
| 4286 | enum intel_display_power_domain power_domain) |
| 4287 | { |
| 4288 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; |
| 4289 | intel_display_power_put(to_i915(encoder->base.dev), power_domain); |
| 4290 | } |
| 4291 | |
| 4292 | static enum drm_connector_status |
| 4293 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 4294 | { |
| 4295 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4296 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4297 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4298 | struct drm_device *dev = connector->dev; |
| 4299 | enum drm_connector_status status; |
| 4300 | enum intel_display_power_domain power_domain; |
| 4301 | bool ret; |
| 4302 | |
| 4303 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4304 | connector->base.id, connector->name); |
| 4305 | intel_dp_unset_edid(intel_dp); |
| 4306 | |
| 4307 | if (intel_dp->is_mst) { |
| 4308 | /* MST devices are disconnected from a monitor POV */ |
| 4309 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4310 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4311 | return connector_status_disconnected; |
| 4312 | } |
| 4313 | |
| 4314 | power_domain = intel_dp_power_get(intel_dp); |
| 4315 | |
| 4316 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4317 | if (is_edp(intel_dp)) |
| 4318 | status = edp_detect(intel_dp); |
| 4319 | else if (HAS_PCH_SPLIT(dev)) |
| 4320 | status = ironlake_dp_detect(intel_dp); |
| 4321 | else |
| 4322 | status = g4x_dp_detect(intel_dp); |
| 4323 | if (status != connector_status_connected) |
| 4324 | goto out; |
| 4325 | |
| 4326 | intel_dp_probe_oui(intel_dp); |
| 4327 | |
| 4328 | ret = intel_dp_probe_mst(intel_dp); |
| 4329 | if (ret) { |
| 4330 | /* if we are in MST mode then this connector |
| 4331 | won't appear connected or have anything with EDID on it */ |
| 4332 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4333 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4334 | status = connector_status_disconnected; |
| 4335 | goto out; |
| 4336 | } |
| 4337 | |
| 4338 | intel_dp_set_edid(intel_dp); |
| 4339 | |
| 4340 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4341 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4342 | status = connector_status_connected; |
| 4343 | |
| 4344 | out: |
| 4345 | intel_dp_power_put(intel_dp, power_domain); |
| 4346 | return status; |
| 4347 | } |
| 4348 | |
| 4349 | static void |
| 4350 | intel_dp_force(struct drm_connector *connector) |
| 4351 | { |
| 4352 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4353 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 4354 | enum intel_display_power_domain power_domain; |
| 4355 | |
| 4356 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4357 | connector->base.id, connector->name); |
| 4358 | intel_dp_unset_edid(intel_dp); |
| 4359 | |
| 4360 | if (connector->status != connector_status_connected) |
| 4361 | return; |
| 4362 | |
| 4363 | power_domain = intel_dp_power_get(intel_dp); |
| 4364 | |
| 4365 | intel_dp_set_edid(intel_dp); |
| 4366 | |
| 4367 | intel_dp_power_put(intel_dp, power_domain); |
| 4368 | |
| 4369 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 4370 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 4371 | } |
| 4372 | |
| 4373 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 4374 | { |
| 4375 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4376 | struct edid *edid; |
| 4377 | |
| 4378 | edid = intel_connector->detect_edid; |
| 4379 | if (edid) { |
| 4380 | int ret = intel_connector_update_modes(connector, edid); |
| 4381 | if (ret) |
| 4382 | return ret; |
| 4383 | } |
| 4384 | |
| 4385 | /* if eDP has no EDID, fall back to fixed mode */ |
| 4386 | if (is_edp(intel_attached_dp(connector)) && |
| 4387 | intel_connector->panel.fixed_mode) { |
| 4388 | struct drm_display_mode *mode; |
| 4389 | |
| 4390 | mode = drm_mode_duplicate(connector->dev, |
| 4391 | intel_connector->panel.fixed_mode); |
| 4392 | if (mode) { |
| 4393 | drm_mode_probed_add(connector, mode); |
| 4394 | return 1; |
| 4395 | } |
| 4396 | } |
| 4397 | |
| 4398 | return 0; |
| 4399 | } |
| 4400 | |
| 4401 | static bool |
| 4402 | intel_dp_detect_audio(struct drm_connector *connector) |
| 4403 | { |
| 4404 | bool has_audio = false; |
| 4405 | struct edid *edid; |
| 4406 | |
| 4407 | edid = to_intel_connector(connector)->detect_edid; |
| 4408 | if (edid) |
| 4409 | has_audio = drm_detect_monitor_audio(edid); |
| 4410 | |
| 4411 | return has_audio; |
| 4412 | } |
| 4413 | |
| 4414 | static int |
| 4415 | intel_dp_set_property(struct drm_connector *connector, |
| 4416 | struct drm_property *property, |
| 4417 | uint64_t val) |
| 4418 | { |
| 4419 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 4420 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4421 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 4422 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4423 | int ret; |
| 4424 | |
| 4425 | ret = drm_object_property_set_value(&connector->base, property, val); |
| 4426 | if (ret) |
| 4427 | return ret; |
| 4428 | |
| 4429 | if (property == dev_priv->force_audio_property) { |
| 4430 | int i = val; |
| 4431 | bool has_audio; |
| 4432 | |
| 4433 | if (i == intel_dp->force_audio) |
| 4434 | return 0; |
| 4435 | |
| 4436 | intel_dp->force_audio = i; |
| 4437 | |
| 4438 | if (i == HDMI_AUDIO_AUTO) |
| 4439 | has_audio = intel_dp_detect_audio(connector); |
| 4440 | else |
| 4441 | has_audio = (i == HDMI_AUDIO_ON); |
| 4442 | |
| 4443 | if (has_audio == intel_dp->has_audio) |
| 4444 | return 0; |
| 4445 | |
| 4446 | intel_dp->has_audio = has_audio; |
| 4447 | goto done; |
| 4448 | } |
| 4449 | |
| 4450 | if (property == dev_priv->broadcast_rgb_property) { |
| 4451 | bool old_auto = intel_dp->color_range_auto; |
| 4452 | uint32_t old_range = intel_dp->color_range; |
| 4453 | |
| 4454 | switch (val) { |
| 4455 | case INTEL_BROADCAST_RGB_AUTO: |
| 4456 | intel_dp->color_range_auto = true; |
| 4457 | break; |
| 4458 | case INTEL_BROADCAST_RGB_FULL: |
| 4459 | intel_dp->color_range_auto = false; |
| 4460 | intel_dp->color_range = 0; |
| 4461 | break; |
| 4462 | case INTEL_BROADCAST_RGB_LIMITED: |
| 4463 | intel_dp->color_range_auto = false; |
| 4464 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 4465 | break; |
| 4466 | default: |
| 4467 | return -EINVAL; |
| 4468 | } |
| 4469 | |
| 4470 | if (old_auto == intel_dp->color_range_auto && |
| 4471 | old_range == intel_dp->color_range) |
| 4472 | return 0; |
| 4473 | |
| 4474 | goto done; |
| 4475 | } |
| 4476 | |
| 4477 | if (is_edp(intel_dp) && |
| 4478 | property == connector->dev->mode_config.scaling_mode_property) { |
| 4479 | if (val == DRM_MODE_SCALE_NONE) { |
| 4480 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 4481 | return -EINVAL; |
| 4482 | } |
| 4483 | |
| 4484 | if (intel_connector->panel.fitting_mode == val) { |
| 4485 | /* the eDP scaling property is not changed */ |
| 4486 | return 0; |
| 4487 | } |
| 4488 | intel_connector->panel.fitting_mode = val; |
| 4489 | |
| 4490 | goto done; |
| 4491 | } |
| 4492 | |
| 4493 | return -EINVAL; |
| 4494 | |
| 4495 | done: |
| 4496 | if (intel_encoder->base.crtc) |
| 4497 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
| 4498 | |
| 4499 | return 0; |
| 4500 | } |
| 4501 | |
| 4502 | static void |
| 4503 | intel_dp_connector_destroy(struct drm_connector *connector) |
| 4504 | { |
| 4505 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4506 | |
| 4507 | kfree(intel_connector->detect_edid); |
| 4508 | |
| 4509 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 4510 | kfree(intel_connector->edid); |
| 4511 | |
| 4512 | /* Can't call is_edp() since the encoder may have been destroyed |
| 4513 | * already. */ |
| 4514 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
| 4515 | intel_panel_fini(&intel_connector->panel); |
| 4516 | |
| 4517 | drm_connector_cleanup(connector); |
| 4518 | kfree(connector); |
| 4519 | } |
| 4520 | |
| 4521 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
| 4522 | { |
| 4523 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 4524 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 4525 | |
| 4526 | drm_dp_aux_unregister(&intel_dp->aux); |
| 4527 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 4528 | drm_encoder_cleanup(encoder); |
| 4529 | if (is_edp(intel_dp)) { |
| 4530 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 4531 | /* |
| 4532 | * vdd might still be enabled do to the delayed vdd off. |
| 4533 | * Make sure vdd is actually turned off here. |
| 4534 | */ |
| 4535 | pps_lock(intel_dp); |
| 4536 | edp_panel_vdd_off_sync(intel_dp); |
| 4537 | pps_unlock(intel_dp); |
| 4538 | |
| 4539 | if (intel_dp->edp_notifier.notifier_call) { |
| 4540 | unregister_reboot_notifier(&intel_dp->edp_notifier); |
| 4541 | intel_dp->edp_notifier.notifier_call = NULL; |
| 4542 | } |
| 4543 | } |
| 4544 | kfree(intel_dig_port); |
| 4545 | } |
| 4546 | |
| 4547 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
| 4548 | { |
| 4549 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4550 | |
| 4551 | if (!is_edp(intel_dp)) |
| 4552 | return; |
| 4553 | |
| 4554 | /* |
| 4555 | * vdd might still be enabled do to the delayed vdd off. |
| 4556 | * Make sure vdd is actually turned off here. |
| 4557 | */ |
| 4558 | pps_lock(intel_dp); |
| 4559 | edp_panel_vdd_off_sync(intel_dp); |
| 4560 | pps_unlock(intel_dp); |
| 4561 | } |
| 4562 | |
| 4563 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
| 4564 | { |
| 4565 | intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); |
| 4566 | } |
| 4567 | |
| 4568 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
| 4569 | .dpms = intel_connector_dpms, |
| 4570 | .detect = intel_dp_detect, |
| 4571 | .force = intel_dp_force, |
| 4572 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 4573 | .set_property = intel_dp_set_property, |
| 4574 | .destroy = intel_dp_connector_destroy, |
| 4575 | }; |
| 4576 | |
| 4577 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 4578 | .get_modes = intel_dp_get_modes, |
| 4579 | .mode_valid = intel_dp_mode_valid, |
| 4580 | .best_encoder = intel_best_encoder, |
| 4581 | }; |
| 4582 | |
| 4583 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
| 4584 | .reset = intel_dp_encoder_reset, |
| 4585 | .destroy = intel_dp_encoder_destroy, |
| 4586 | }; |
| 4587 | |
| 4588 | void |
| 4589 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
| 4590 | { |
| 4591 | return; |
| 4592 | } |
| 4593 | |
| 4594 | bool |
| 4595 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4596 | { |
| 4597 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 4598 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4599 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4600 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4601 | enum intel_display_power_domain power_domain; |
| 4602 | bool ret = true; |
| 4603 | |
| 4604 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
| 4605 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
| 4606 | |
| 4607 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
| 4608 | port_name(intel_dig_port->port), |
| 4609 | long_hpd ? "long" : "short"); |
| 4610 | |
| 4611 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 4612 | intel_display_power_get(dev_priv, power_domain); |
| 4613 | |
| 4614 | if (long_hpd) { |
| 4615 | |
| 4616 | if (HAS_PCH_SPLIT(dev)) { |
| 4617 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
| 4618 | goto mst_fail; |
| 4619 | } else { |
| 4620 | if (g4x_digital_port_connected(dev, intel_dig_port) != 1) |
| 4621 | goto mst_fail; |
| 4622 | } |
| 4623 | |
| 4624 | if (!intel_dp_get_dpcd(intel_dp)) { |
| 4625 | goto mst_fail; |
| 4626 | } |
| 4627 | |
| 4628 | intel_dp_probe_oui(intel_dp); |
| 4629 | |
| 4630 | if (!intel_dp_probe_mst(intel_dp)) |
| 4631 | goto mst_fail; |
| 4632 | |
| 4633 | } else { |
| 4634 | if (intel_dp->is_mst) { |
| 4635 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
| 4636 | goto mst_fail; |
| 4637 | } |
| 4638 | |
| 4639 | if (!intel_dp->is_mst) { |
| 4640 | /* |
| 4641 | * we'll check the link status via the normal hot plug path later - |
| 4642 | * but for short hpds we should check it now |
| 4643 | */ |
| 4644 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4645 | intel_dp_check_link_status(intel_dp); |
| 4646 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4647 | } |
| 4648 | } |
| 4649 | ret = false; |
| 4650 | goto put_power; |
| 4651 | mst_fail: |
| 4652 | /* if we were in MST mode, and device is not there get out of MST mode */ |
| 4653 | if (intel_dp->is_mst) { |
| 4654 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
| 4655 | intel_dp->is_mst = false; |
| 4656 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 4657 | } |
| 4658 | put_power: |
| 4659 | intel_display_power_put(dev_priv, power_domain); |
| 4660 | |
| 4661 | return ret; |
| 4662 | } |
| 4663 | |
| 4664 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 4665 | int |
| 4666 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
| 4667 | { |
| 4668 | struct drm_device *dev = crtc->dev; |
| 4669 | struct intel_encoder *intel_encoder; |
| 4670 | struct intel_dp *intel_dp; |
| 4671 | |
| 4672 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 4673 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4674 | |
| 4675 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 4676 | intel_encoder->type == INTEL_OUTPUT_EDP) |
| 4677 | return intel_dp->output_reg; |
| 4678 | } |
| 4679 | |
| 4680 | return -1; |
| 4681 | } |
| 4682 | |
| 4683 | /* check the VBT to see whether the eDP is on DP-D port */ |
| 4684 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
| 4685 | { |
| 4686 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4687 | union child_device_config *p_child; |
| 4688 | int i; |
| 4689 | static const short port_mapping[] = { |
| 4690 | [PORT_B] = PORT_IDPB, |
| 4691 | [PORT_C] = PORT_IDPC, |
| 4692 | [PORT_D] = PORT_IDPD, |
| 4693 | }; |
| 4694 | |
| 4695 | if (port == PORT_A) |
| 4696 | return true; |
| 4697 | |
| 4698 | if (!dev_priv->vbt.child_dev_num) |
| 4699 | return false; |
| 4700 | |
| 4701 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
| 4702 | p_child = dev_priv->vbt.child_dev + i; |
| 4703 | |
| 4704 | if (p_child->common.dvo_port == port_mapping[port] && |
| 4705 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
| 4706 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
| 4707 | return true; |
| 4708 | } |
| 4709 | return false; |
| 4710 | } |
| 4711 | |
| 4712 | void |
| 4713 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 4714 | { |
| 4715 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4716 | |
| 4717 | intel_attach_force_audio_property(connector); |
| 4718 | intel_attach_broadcast_rgb_property(connector); |
| 4719 | intel_dp->color_range_auto = true; |
| 4720 | |
| 4721 | if (is_edp(intel_dp)) { |
| 4722 | drm_mode_create_scaling_mode_property(connector->dev); |
| 4723 | drm_object_attach_property( |
| 4724 | &connector->base, |
| 4725 | connector->dev->mode_config.scaling_mode_property, |
| 4726 | DRM_MODE_SCALE_ASPECT); |
| 4727 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
| 4728 | } |
| 4729 | } |
| 4730 | |
| 4731 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 4732 | { |
| 4733 | intel_dp->last_power_cycle = jiffies; |
| 4734 | intel_dp->last_power_on = jiffies; |
| 4735 | intel_dp->last_backlight_off = jiffies; |
| 4736 | } |
| 4737 | |
| 4738 | static void |
| 4739 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 4740 | struct intel_dp *intel_dp, |
| 4741 | struct edp_power_seq *out) |
| 4742 | { |
| 4743 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4744 | struct edp_power_seq cur, vbt, spec, final; |
| 4745 | u32 pp_on, pp_off, pp_div, pp; |
| 4746 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
| 4747 | |
| 4748 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4749 | |
| 4750 | if (HAS_PCH_SPLIT(dev)) { |
| 4751 | pp_ctrl_reg = PCH_PP_CONTROL; |
| 4752 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 4753 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 4754 | pp_div_reg = PCH_PP_DIVISOR; |
| 4755 | } else { |
| 4756 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 4757 | |
| 4758 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 4759 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 4760 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 4761 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 4762 | } |
| 4763 | |
| 4764 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 4765 | * the very first thing. */ |
| 4766 | pp = ironlake_get_pp_control(intel_dp); |
| 4767 | I915_WRITE(pp_ctrl_reg, pp); |
| 4768 | |
| 4769 | pp_on = I915_READ(pp_on_reg); |
| 4770 | pp_off = I915_READ(pp_off_reg); |
| 4771 | pp_div = I915_READ(pp_div_reg); |
| 4772 | |
| 4773 | /* Pull timing values out of registers */ |
| 4774 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 4775 | PANEL_POWER_UP_DELAY_SHIFT; |
| 4776 | |
| 4777 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 4778 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 4779 | |
| 4780 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 4781 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 4782 | |
| 4783 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 4784 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 4785 | |
| 4786 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 4787 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 4788 | |
| 4789 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 4790 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 4791 | |
| 4792 | vbt = dev_priv->vbt.edp_pps; |
| 4793 | |
| 4794 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 4795 | * our hw here, which are all in 100usec. */ |
| 4796 | spec.t1_t3 = 210 * 10; |
| 4797 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 4798 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 4799 | spec.t10 = 500 * 10; |
| 4800 | /* This one is special and actually in units of 100ms, but zero |
| 4801 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 4802 | * table multiplies it with 1000 to make it in units of 100usec, |
| 4803 | * too. */ |
| 4804 | spec.t11_t12 = (510 + 100) * 10; |
| 4805 | |
| 4806 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 4807 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 4808 | |
| 4809 | /* Use the max of the register settings and vbt. If both are |
| 4810 | * unset, fall back to the spec limits. */ |
| 4811 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
| 4812 | spec.field : \ |
| 4813 | max(cur.field, vbt.field)) |
| 4814 | assign_final(t1_t3); |
| 4815 | assign_final(t8); |
| 4816 | assign_final(t9); |
| 4817 | assign_final(t10); |
| 4818 | assign_final(t11_t12); |
| 4819 | #undef assign_final |
| 4820 | |
| 4821 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
| 4822 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 4823 | intel_dp->backlight_on_delay = get_delay(t8); |
| 4824 | intel_dp->backlight_off_delay = get_delay(t9); |
| 4825 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 4826 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 4827 | #undef get_delay |
| 4828 | |
| 4829 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 4830 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 4831 | intel_dp->panel_power_cycle_delay); |
| 4832 | |
| 4833 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 4834 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
| 4835 | |
| 4836 | if (out) |
| 4837 | *out = final; |
| 4838 | } |
| 4839 | |
| 4840 | static void |
| 4841 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 4842 | struct intel_dp *intel_dp, |
| 4843 | struct edp_power_seq *seq) |
| 4844 | { |
| 4845 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4846 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
| 4847 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
| 4848 | int pp_on_reg, pp_off_reg, pp_div_reg; |
| 4849 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 4850 | |
| 4851 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4852 | |
| 4853 | if (HAS_PCH_SPLIT(dev)) { |
| 4854 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 4855 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 4856 | pp_div_reg = PCH_PP_DIVISOR; |
| 4857 | } else { |
| 4858 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 4859 | |
| 4860 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 4861 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 4862 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
| 4863 | } |
| 4864 | |
| 4865 | /* |
| 4866 | * And finally store the new values in the power sequencer. The |
| 4867 | * backlight delays are set to 1 because we do manual waits on them. For |
| 4868 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
| 4869 | * we'll end up waiting for the backlight off delay twice: once when we |
| 4870 | * do the manual sleep, and once when we disable the panel and wait for |
| 4871 | * the PP_STATUS bit to become zero. |
| 4872 | */ |
| 4873 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
| 4874 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 4875 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
| 4876 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
| 4877 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 4878 | * formula. */ |
| 4879 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 4880 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
| 4881 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 4882 | |
| 4883 | /* Haswell doesn't have any port selection bits for the panel |
| 4884 | * power sequencer any more. */ |
| 4885 | if (IS_VALLEYVIEW(dev)) { |
| 4886 | port_sel = PANEL_PORT_SELECT_VLV(port); |
| 4887 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 4888 | if (port == PORT_A) |
| 4889 | port_sel = PANEL_PORT_SELECT_DPA; |
| 4890 | else |
| 4891 | port_sel = PANEL_PORT_SELECT_DPD; |
| 4892 | } |
| 4893 | |
| 4894 | pp_on |= port_sel; |
| 4895 | |
| 4896 | I915_WRITE(pp_on_reg, pp_on); |
| 4897 | I915_WRITE(pp_off_reg, pp_off); |
| 4898 | I915_WRITE(pp_div_reg, pp_div); |
| 4899 | |
| 4900 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
| 4901 | I915_READ(pp_on_reg), |
| 4902 | I915_READ(pp_off_reg), |
| 4903 | I915_READ(pp_div_reg)); |
| 4904 | } |
| 4905 | |
| 4906 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
| 4907 | { |
| 4908 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4909 | struct intel_encoder *encoder; |
| 4910 | struct intel_dp *intel_dp = NULL; |
| 4911 | struct intel_crtc_config *config = NULL; |
| 4912 | struct intel_crtc *intel_crtc = NULL; |
| 4913 | struct intel_connector *intel_connector = dev_priv->drrs.connector; |
| 4914 | u32 reg, val; |
| 4915 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; |
| 4916 | |
| 4917 | if (refresh_rate <= 0) { |
| 4918 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 4919 | return; |
| 4920 | } |
| 4921 | |
| 4922 | if (intel_connector == NULL) { |
| 4923 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); |
| 4924 | return; |
| 4925 | } |
| 4926 | |
| 4927 | /* |
| 4928 | * FIXME: This needs proper synchronization with psr state. But really |
| 4929 | * hard to tell without seeing the user of this function of this code. |
| 4930 | * Check locking and ordering once that lands. |
| 4931 | */ |
| 4932 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
| 4933 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
| 4934 | return; |
| 4935 | } |
| 4936 | |
| 4937 | encoder = intel_attached_encoder(&intel_connector->base); |
| 4938 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 4939 | intel_crtc = encoder->new_crtc; |
| 4940 | |
| 4941 | if (!intel_crtc) { |
| 4942 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 4943 | return; |
| 4944 | } |
| 4945 | |
| 4946 | config = &intel_crtc->config; |
| 4947 | |
| 4948 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { |
| 4949 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 4950 | return; |
| 4951 | } |
| 4952 | |
| 4953 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) |
| 4954 | index = DRRS_LOW_RR; |
| 4955 | |
| 4956 | if (index == intel_dp->drrs_state.refresh_rate_type) { |
| 4957 | DRM_DEBUG_KMS( |
| 4958 | "DRRS requested for previously set RR...ignoring\n"); |
| 4959 | return; |
| 4960 | } |
| 4961 | |
| 4962 | if (!intel_crtc->active) { |
| 4963 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 4964 | return; |
| 4965 | } |
| 4966 | |
| 4967 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
| 4968 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
| 4969 | val = I915_READ(reg); |
| 4970 | if (index > DRRS_HIGH_RR) { |
| 4971 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
| 4972 | intel_dp_set_m_n(intel_crtc); |
| 4973 | } else { |
| 4974 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
| 4975 | } |
| 4976 | I915_WRITE(reg, val); |
| 4977 | } |
| 4978 | |
| 4979 | /* |
| 4980 | * mutex taken to ensure that there is no race between differnt |
| 4981 | * drrs calls trying to update refresh rate. This scenario may occur |
| 4982 | * in future when idleness detection based DRRS in kernel and |
| 4983 | * possible calls from user space to set differnt RR are made. |
| 4984 | */ |
| 4985 | |
| 4986 | mutex_lock(&intel_dp->drrs_state.mutex); |
| 4987 | |
| 4988 | intel_dp->drrs_state.refresh_rate_type = index; |
| 4989 | |
| 4990 | mutex_unlock(&intel_dp->drrs_state.mutex); |
| 4991 | |
| 4992 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 4993 | } |
| 4994 | |
| 4995 | static struct drm_display_mode * |
| 4996 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, |
| 4997 | struct intel_connector *intel_connector, |
| 4998 | struct drm_display_mode *fixed_mode) |
| 4999 | { |
| 5000 | struct drm_connector *connector = &intel_connector->base; |
| 5001 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5002 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 5003 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5004 | struct drm_display_mode *downclock_mode = NULL; |
| 5005 | |
| 5006 | if (INTEL_INFO(dev)->gen <= 6) { |
| 5007 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 5008 | return NULL; |
| 5009 | } |
| 5010 | |
| 5011 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
| 5012 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
| 5013 | return NULL; |
| 5014 | } |
| 5015 | |
| 5016 | downclock_mode = intel_find_panel_downclock |
| 5017 | (dev, fixed_mode, connector); |
| 5018 | |
| 5019 | if (!downclock_mode) { |
| 5020 | DRM_DEBUG_KMS("DRRS not supported\n"); |
| 5021 | return NULL; |
| 5022 | } |
| 5023 | |
| 5024 | dev_priv->drrs.connector = intel_connector; |
| 5025 | |
| 5026 | mutex_init(&intel_dp->drrs_state.mutex); |
| 5027 | |
| 5028 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
| 5029 | |
| 5030 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
| 5031 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
| 5032 | return downclock_mode; |
| 5033 | } |
| 5034 | |
| 5035 | void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) |
| 5036 | { |
| 5037 | struct drm_device *dev = intel_encoder->base.dev; |
| 5038 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5039 | struct intel_dp *intel_dp; |
| 5040 | enum intel_display_power_domain power_domain; |
| 5041 | |
| 5042 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 5043 | return; |
| 5044 | |
| 5045 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 5046 | |
| 5047 | pps_lock(intel_dp); |
| 5048 | |
| 5049 | if (!edp_have_panel_vdd(intel_dp)) |
| 5050 | goto out; |
| 5051 | /* |
| 5052 | * The VDD bit needs a power domain reference, so if the bit is |
| 5053 | * already enabled when we boot or resume, grab this reference and |
| 5054 | * schedule a vdd off, so we don't hold on to the reference |
| 5055 | * indefinitely. |
| 5056 | */ |
| 5057 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
| 5058 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 5059 | intel_display_power_get(dev_priv, power_domain); |
| 5060 | |
| 5061 | edp_panel_vdd_schedule_off(intel_dp); |
| 5062 | out: |
| 5063 | pps_unlock(intel_dp); |
| 5064 | } |
| 5065 | |
| 5066 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
| 5067 | struct intel_connector *intel_connector, |
| 5068 | struct edp_power_seq *power_seq) |
| 5069 | { |
| 5070 | struct drm_connector *connector = &intel_connector->base; |
| 5071 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 5072 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5073 | struct drm_device *dev = intel_encoder->base.dev; |
| 5074 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5075 | struct drm_display_mode *fixed_mode = NULL; |
| 5076 | struct drm_display_mode *downclock_mode = NULL; |
| 5077 | bool has_dpcd; |
| 5078 | struct drm_display_mode *scan; |
| 5079 | struct edid *edid; |
| 5080 | |
| 5081 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
| 5082 | |
| 5083 | if (!is_edp(intel_dp)) |
| 5084 | return true; |
| 5085 | |
| 5086 | intel_edp_panel_vdd_sanitize(intel_encoder); |
| 5087 | |
| 5088 | /* Cache DPCD and EDID for edp. */ |
| 5089 | intel_edp_panel_vdd_on(intel_dp); |
| 5090 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
| 5091 | intel_edp_panel_vdd_off(intel_dp, false); |
| 5092 | |
| 5093 | if (has_dpcd) { |
| 5094 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 5095 | dev_priv->no_aux_handshake = |
| 5096 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 5097 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 5098 | } else { |
| 5099 | /* if this fails, presume the device is a ghost */ |
| 5100 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
| 5101 | return false; |
| 5102 | } |
| 5103 | |
| 5104 | /* We now know it's not a ghost, init power sequence regs. */ |
| 5105 | pps_lock(intel_dp); |
| 5106 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
| 5107 | pps_unlock(intel_dp); |
| 5108 | |
| 5109 | mutex_lock(&dev->mode_config.mutex); |
| 5110 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
| 5111 | if (edid) { |
| 5112 | if (drm_add_edid_modes(connector, edid)) { |
| 5113 | drm_mode_connector_update_edid_property(connector, |
| 5114 | edid); |
| 5115 | drm_edid_to_eld(connector, edid); |
| 5116 | } else { |
| 5117 | kfree(edid); |
| 5118 | edid = ERR_PTR(-EINVAL); |
| 5119 | } |
| 5120 | } else { |
| 5121 | edid = ERR_PTR(-ENOENT); |
| 5122 | } |
| 5123 | intel_connector->edid = edid; |
| 5124 | |
| 5125 | /* prefer fixed mode from EDID if available */ |
| 5126 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 5127 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 5128 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 5129 | downclock_mode = intel_dp_drrs_init( |
| 5130 | intel_dig_port, |
| 5131 | intel_connector, fixed_mode); |
| 5132 | break; |
| 5133 | } |
| 5134 | } |
| 5135 | |
| 5136 | /* fallback to VBT if available for eDP */ |
| 5137 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 5138 | fixed_mode = drm_mode_duplicate(dev, |
| 5139 | dev_priv->vbt.lfp_lvds_vbt_mode); |
| 5140 | if (fixed_mode) |
| 5141 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 5142 | } |
| 5143 | mutex_unlock(&dev->mode_config.mutex); |
| 5144 | |
| 5145 | if (IS_VALLEYVIEW(dev)) { |
| 5146 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
| 5147 | register_reboot_notifier(&intel_dp->edp_notifier); |
| 5148 | } |
| 5149 | |
| 5150 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
| 5151 | intel_connector->panel.backlight_power = intel_edp_backlight_power; |
| 5152 | intel_panel_setup_backlight(connector); |
| 5153 | |
| 5154 | return true; |
| 5155 | } |
| 5156 | |
| 5157 | bool |
| 5158 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 5159 | struct intel_connector *intel_connector) |
| 5160 | { |
| 5161 | struct drm_connector *connector = &intel_connector->base; |
| 5162 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5163 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5164 | struct drm_device *dev = intel_encoder->base.dev; |
| 5165 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5166 | enum port port = intel_dig_port->port; |
| 5167 | struct edp_power_seq power_seq = { 0 }; |
| 5168 | int type; |
| 5169 | |
| 5170 | intel_dp->pps_pipe = INVALID_PIPE; |
| 5171 | |
| 5172 | /* intel_dp vfuncs */ |
| 5173 | if (INTEL_INFO(dev)->gen >= 9) |
| 5174 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
| 5175 | else if (IS_VALLEYVIEW(dev)) |
| 5176 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
| 5177 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 5178 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 5179 | else if (HAS_PCH_SPLIT(dev)) |
| 5180 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 5181 | else |
| 5182 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
| 5183 | |
| 5184 | if (INTEL_INFO(dev)->gen >= 9) |
| 5185 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 5186 | else |
| 5187 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
| 5188 | |
| 5189 | /* Preserve the current hw state. */ |
| 5190 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
| 5191 | intel_dp->attached_connector = intel_connector; |
| 5192 | |
| 5193 | if (intel_dp_is_edp(dev, port)) |
| 5194 | type = DRM_MODE_CONNECTOR_eDP; |
| 5195 | else |
| 5196 | type = DRM_MODE_CONNECTOR_DisplayPort; |
| 5197 | |
| 5198 | /* |
| 5199 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 5200 | * for DP the encoder type can be set by the caller to |
| 5201 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 5202 | */ |
| 5203 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 5204 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 5205 | |
| 5206 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 5207 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 5208 | port_name(port)); |
| 5209 | |
| 5210 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
| 5211 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 5212 | |
| 5213 | connector->interlace_allowed = true; |
| 5214 | connector->doublescan_allowed = 0; |
| 5215 | |
| 5216 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
| 5217 | edp_panel_vdd_work); |
| 5218 | |
| 5219 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
| 5220 | drm_connector_register(connector); |
| 5221 | |
| 5222 | if (HAS_DDI(dev)) |
| 5223 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 5224 | else |
| 5225 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
| 5226 | intel_connector->unregister = intel_dp_connector_unregister; |
| 5227 | |
| 5228 | /* Set up the hotplug pin. */ |
| 5229 | switch (port) { |
| 5230 | case PORT_A: |
| 5231 | intel_encoder->hpd_pin = HPD_PORT_A; |
| 5232 | break; |
| 5233 | case PORT_B: |
| 5234 | intel_encoder->hpd_pin = HPD_PORT_B; |
| 5235 | break; |
| 5236 | case PORT_C: |
| 5237 | intel_encoder->hpd_pin = HPD_PORT_C; |
| 5238 | break; |
| 5239 | case PORT_D: |
| 5240 | intel_encoder->hpd_pin = HPD_PORT_D; |
| 5241 | break; |
| 5242 | default: |
| 5243 | BUG(); |
| 5244 | } |
| 5245 | |
| 5246 | if (is_edp(intel_dp)) { |
| 5247 | pps_lock(intel_dp); |
| 5248 | if (IS_VALLEYVIEW(dev)) { |
| 5249 | vlv_initial_power_sequencer_setup(intel_dp); |
| 5250 | } else { |
| 5251 | intel_dp_init_panel_power_timestamps(intel_dp); |
| 5252 | intel_dp_init_panel_power_sequencer(dev, intel_dp, |
| 5253 | &power_seq); |
| 5254 | } |
| 5255 | pps_unlock(intel_dp); |
| 5256 | } |
| 5257 | |
| 5258 | intel_dp_aux_init(intel_dp, intel_connector); |
| 5259 | |
| 5260 | /* init MST on ports that can support it */ |
| 5261 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 5262 | if (port == PORT_B || port == PORT_C || port == PORT_D) { |
| 5263 | intel_dp_mst_encoder_init(intel_dig_port, |
| 5264 | intel_connector->base.base.id); |
| 5265 | } |
| 5266 | } |
| 5267 | |
| 5268 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
| 5269 | drm_dp_aux_unregister(&intel_dp->aux); |
| 5270 | if (is_edp(intel_dp)) { |
| 5271 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 5272 | /* |
| 5273 | * vdd might still be enabled do to the delayed vdd off. |
| 5274 | * Make sure vdd is actually turned off here. |
| 5275 | */ |
| 5276 | pps_lock(intel_dp); |
| 5277 | edp_panel_vdd_off_sync(intel_dp); |
| 5278 | pps_unlock(intel_dp); |
| 5279 | } |
| 5280 | drm_connector_unregister(connector); |
| 5281 | drm_connector_cleanup(connector); |
| 5282 | return false; |
| 5283 | } |
| 5284 | |
| 5285 | intel_dp_add_properties(intel_dp, connector); |
| 5286 | |
| 5287 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 5288 | * 0xd. Failure to do so will result in spurious interrupts being |
| 5289 | * generated on the port when a cable is not attached. |
| 5290 | */ |
| 5291 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 5292 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 5293 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 5294 | } |
| 5295 | |
| 5296 | return true; |
| 5297 | } |
| 5298 | |
| 5299 | void |
| 5300 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
| 5301 | { |
| 5302 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5303 | struct intel_digital_port *intel_dig_port; |
| 5304 | struct intel_encoder *intel_encoder; |
| 5305 | struct drm_encoder *encoder; |
| 5306 | struct intel_connector *intel_connector; |
| 5307 | |
| 5308 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
| 5309 | if (!intel_dig_port) |
| 5310 | return; |
| 5311 | |
| 5312 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
| 5313 | if (!intel_connector) { |
| 5314 | kfree(intel_dig_port); |
| 5315 | return; |
| 5316 | } |
| 5317 | |
| 5318 | intel_encoder = &intel_dig_port->base; |
| 5319 | encoder = &intel_encoder->base; |
| 5320 | |
| 5321 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
| 5322 | DRM_MODE_ENCODER_TMDS); |
| 5323 | |
| 5324 | intel_encoder->compute_config = intel_dp_compute_config; |
| 5325 | intel_encoder->disable = intel_disable_dp; |
| 5326 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
| 5327 | intel_encoder->get_config = intel_dp_get_config; |
| 5328 | intel_encoder->suspend = intel_dp_encoder_suspend; |
| 5329 | if (IS_CHERRYVIEW(dev)) { |
| 5330 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
| 5331 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 5332 | intel_encoder->enable = vlv_enable_dp; |
| 5333 | intel_encoder->post_disable = chv_post_disable_dp; |
| 5334 | } else if (IS_VALLEYVIEW(dev)) { |
| 5335 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
| 5336 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 5337 | intel_encoder->enable = vlv_enable_dp; |
| 5338 | intel_encoder->post_disable = vlv_post_disable_dp; |
| 5339 | } else { |
| 5340 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 5341 | intel_encoder->enable = g4x_enable_dp; |
| 5342 | if (INTEL_INFO(dev)->gen >= 5) |
| 5343 | intel_encoder->post_disable = ilk_post_disable_dp; |
| 5344 | } |
| 5345 | |
| 5346 | intel_dig_port->port = port; |
| 5347 | intel_dig_port->dp.output_reg = output_reg; |
| 5348 | |
| 5349 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 5350 | if (IS_CHERRYVIEW(dev)) { |
| 5351 | if (port == PORT_D) |
| 5352 | intel_encoder->crtc_mask = 1 << 2; |
| 5353 | else |
| 5354 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 5355 | } else { |
| 5356 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 5357 | } |
| 5358 | intel_encoder->cloneable = 0; |
| 5359 | intel_encoder->hot_plug = intel_dp_hot_plug; |
| 5360 | |
| 5361 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
| 5362 | dev_priv->hpd_irq_port[port] = intel_dig_port; |
| 5363 | |
| 5364 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
| 5365 | drm_encoder_cleanup(encoder); |
| 5366 | kfree(intel_dig_port); |
| 5367 | kfree(intel_connector); |
| 5368 | } |
| 5369 | } |
| 5370 | |
| 5371 | void intel_dp_mst_suspend(struct drm_device *dev) |
| 5372 | { |
| 5373 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5374 | int i; |
| 5375 | |
| 5376 | /* disable MST */ |
| 5377 | for (i = 0; i < I915_MAX_PORTS; i++) { |
| 5378 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
| 5379 | if (!intel_dig_port) |
| 5380 | continue; |
| 5381 | |
| 5382 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 5383 | if (!intel_dig_port->dp.can_mst) |
| 5384 | continue; |
| 5385 | if (intel_dig_port->dp.is_mst) |
| 5386 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
| 5387 | } |
| 5388 | } |
| 5389 | } |
| 5390 | |
| 5391 | void intel_dp_mst_resume(struct drm_device *dev) |
| 5392 | { |
| 5393 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5394 | int i; |
| 5395 | |
| 5396 | for (i = 0; i < I915_MAX_PORTS; i++) { |
| 5397 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; |
| 5398 | if (!intel_dig_port) |
| 5399 | continue; |
| 5400 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 5401 | int ret; |
| 5402 | |
| 5403 | if (!intel_dig_port->dp.can_mst) |
| 5404 | continue; |
| 5405 | |
| 5406 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
| 5407 | if (ret != 0) { |
| 5408 | intel_dp_check_mst_status(&intel_dig_port->dp); |
| 5409 | } |
| 5410 | } |
| 5411 | } |
| 5412 | } |